diff --git a/components/cloud/huawei/adapter/MQTTliteos_adapter.c b/components/cloud/huawei/adapter/MQTTliteos_adapter.c index ee973255f51174963fb2c464213bf360a9530220..f2d86792acccc3a46548baf9da1e900ba039d435 100644 --- a/components/cloud/huawei/adapter/MQTTliteos_adapter.c +++ b/components/cloud/huawei/adapter/MQTTliteos_adapter.c @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file MQTTliteos_adapter.c - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ + #include "MQTTliteos_adapter.h" #include "mbedtls/net_sockets.h" diff --git a/components/cloud/huawei/adapter/MQTTliteos_adapter.h b/components/cloud/huawei/adapter/MQTTliteos_adapter.h index 09cd48ba13d930fff4f0e6aae7c8be492e27a44c..4cc1d21c7ce1320be80ba1c1fe54b9613bb14eed 100644 --- a/components/cloud/huawei/adapter/MQTTliteos_adapter.h +++ b/components/cloud/huawei/adapter/MQTTliteos_adapter.h @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file MQTTliteos_adapter.h - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ + #ifndef MQTT_LITE_OS_H #define MQTT_LITE_OS_H diff --git a/components/cloud/huawei/adapter/atiny_osdep_adapter.c b/components/cloud/huawei/adapter/atiny_osdep_adapter.c index ed24cf3d2bf8688971fffd3ebdc3a63777ada881..a433ca22c65f12446ed6b7832acc3e14f680425e 100644 --- a/components/cloud/huawei/adapter/atiny_osdep_adapter.c +++ b/components/cloud/huawei/adapter/atiny_osdep_adapter.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file atiny_osdep_adapter.c - * - * @brief huawei cloud sdk file "atiny_osdep.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include "osdepends/atiny_osdep.h" diff --git a/components/cloud/huawei/adapter/atiny_socket_adapter.c b/components/cloud/huawei/adapter/atiny_socket_adapter.c index f387a2e9260c9f00c08ae5c8d64a2c255601188f..27a8b859351770d1e00c02dbf8d9001f8c9d8f32 100644 --- a/components/cloud/huawei/adapter/atiny_socket_adapter.c +++ b/components/cloud/huawei/adapter/atiny_socket_adapter.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file atiny_socket_adapter.c - * - * @brief huawei cloud sdk file "atiny_socket.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include #include diff --git a/components/cloud/huawei/adapter/atiny_socket_adapter.h b/components/cloud/huawei/adapter/atiny_socket_adapter.h index 64101e7d9cbb551720f9cd6d9cf83edbd2efdb2a..1847d5b7cdb4163802f6f0e3b1b7eec4fa39a687 100644 --- a/components/cloud/huawei/adapter/atiny_socket_adapter.h +++ b/components/cloud/huawei/adapter/atiny_socket_adapter.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file atiny_socket_adapter.h - * - * @brief huawei cloud sdk file "atiny_socket.h" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __ATINY_SOCKET_ADAPTER_H__ #define __ATINY_SOCKET_ADAPTER_H__ #include diff --git a/components/cloud/huawei/adapter/commandline_adapter.c b/components/cloud/huawei/adapter/commandline_adapter.c index 86332bbb49f749d7d1b1dadddbe7721960b8a86a..1a8519ac4840523b4e7514a358fb8313cef72966 100644 --- a/components/cloud/huawei/adapter/commandline_adapter.c +++ b/components/cloud/huawei/adapter/commandline_adapter.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file commandline_adapter.c, to do. - * - * @brief huawei cloud sdk file "commandline.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include "commandline_adapter.h" void output_buffer(FILE *stream, uint8_t *buffer, int length, int indent) diff --git a/components/cloud/huawei/adapter/commandline_adapter.h b/components/cloud/huawei/adapter/commandline_adapter.h index 584a6567e828b6b98f069c85aa2b6ce749563821..5a4ac0d50032a12893c559f36181a1232f90235d 100644 --- a/components/cloud/huawei/adapter/commandline_adapter.h +++ b/components/cloud/huawei/adapter/commandline_adapter.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file commandline_adapter.h - * - * @brief huawei cloud sdk file "commandline.h" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __COMMANDLINE_ADAPTER_H__ #define __COMMANDLINE_ADAPTER_H__ diff --git a/components/cloud/huawei/adapter/fota_adapter.c b/components/cloud/huawei/adapter/fota_adapter.c index 33b440accc40d12f68b4b37da098e3c8b5d3175d..f1b6a8dad6aa81f60c1f4c1abe277dc8db3aafbb 100644 --- a/components/cloud/huawei/adapter/fota_adapter.c +++ b/components/cloud/huawei/adapter/fota_adapter.c @@ -1,26 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file fota_adapter.c - * - * @brief huawei cloud sdk file "fota.c" adaptation, to do. - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ -/* stake: flag_manager.h */ #include "flag_manager.h" int flag_init(flag_op_s *flag) { diff --git a/components/cloud/huawei/adapter/los_config_adapter.h b/components/cloud/huawei/adapter/los_config_adapter.h index b36f5ab7ff24e498682fcedac70838435786482b..928fcf386ee649b40d404c6fe74b00654042d043 100644 --- a/components/cloud/huawei/adapter/los_config_adapter.h +++ b/components/cloud/huawei/adapter/los_config_adapter.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file los_config_adapter.c - * - * @brief huawei cloud sdk file "los_config.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __LOS_CONFIG_ADAPTER_H__ #define __LOS_CONFIG_ADAPTER_H__ #include diff --git a/components/cloud/huawei/adapter/los_task_adapter.c b/components/cloud/huawei/adapter/los_task_adapter.c index 8f18a6faee3355af90f6799fdadc34b6d877f187..edc280cfc39d6e55fbb0f872e542b54b3f967453 100644 --- a/components/cloud/huawei/adapter/los_task_adapter.c +++ b/components/cloud/huawei/adapter/los_task_adapter.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file los_task_adapter.c - * - * @brief huawei cloud sdk file "los_task.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include #include diff --git a/components/cloud/huawei/adapter/los_task_adapter.h b/components/cloud/huawei/adapter/los_task_adapter.h index cc3dbc72f5c875f68106b41af591c0e5b3865866..b919a47c318ca070dd25031f3ea1f870214f7502 100644 --- a/components/cloud/huawei/adapter/los_task_adapter.h +++ b/components/cloud/huawei/adapter/los_task_adapter.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file los_task_adapter.h - * - * @brief huawei cloud sdk file "los_task.h" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __LOS_TASK_ADAPTER__ #define __LOS_TASK_ADAPTER__ diff --git a/components/cloud/huawei/adapter/los_typedef_adapter.h b/components/cloud/huawei/adapter/los_typedef_adapter.h index 825de36ccf8131bc746f70cea3edc7ecb0d47b1c..a8b87872cf459b3eebd83ad908caf7a2b8b194f1 100644 --- a/components/cloud/huawei/adapter/los_typedef_adapter.h +++ b/components/cloud/huawei/adapter/los_typedef_adapter.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file los_typedef_adapter.c - * - * @brief huawei cloud sdk file "los_typedef.c" adaptation - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __LOS_TYPEDEF_ADAPTER__ #define __LOS_TYPEDEF_ADAPTER__ diff --git a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.c b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.c index f108f4725df5a07b4f6f6a4f1bc9e793a4befc4b..1bf0c82c13cddea1ae69452cd14563a6500567ac 100644 --- a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.c +++ b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.c @@ -31,28 +31,6 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_cmd_ioctl.c - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include "agent_tiny_cmd_ioctl.h" #include "atiny_lwm2m/agenttiny.h" diff --git a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.h b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.h index 1597a62bf81dc737de4f67fdf2484e2794fdaee9..47b77548d727af3d6f4cf56bad149c431660f99c 100644 --- a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.h +++ b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_cmd_ioctl.h @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_cmd_ioctl.h - * - * @brief Cloud platform command execution header file - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ + #ifndef AGENT_TINY_CMD_IOCTL_H #define AGENT_TINY_CMD_IOCTL_H diff --git a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_data_def.h b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_data_def.h index 75158f82dd6091ec2645c8552f765cbbb6d4b2f9..7e9073a824dab7f7dfe9656ee961c52724b6d92c 100644 --- a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_data_def.h +++ b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_data_def.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_data_def.h - * - * @brief Data format of APP message defined on cloud platform - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __AGENT_TINY_DATA_DEF_H_ #define __AGENT_TINY_DATA_DEF_H_ #include diff --git a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_demo.c b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_demo.c index bd21dd8c8e4ef88c1c2b461343682e9e5e0bd074..647982dfdc69e53619bf1e9e51c6f5effa1455aa 100644 --- a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_demo.c +++ b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_demo.c @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_demo.c - * - * @brief Handshake, connection and monitoring tasks between terminal and platform - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ + #include #include #include diff --git a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_report.c b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_report.c index 78a23c9e50b73528667895f302f49a1b9f21eb2c..a4847b051a6e9a5f5a10e47ca6559ca4fa983e0d 100644 --- a/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_report.c +++ b/components/cloud/huawei/demos/agenttiny_lwm2m/agent_tiny_report.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_report.c - * - * @brief Terminal message reporting function - * - * @revision - * Date Author Notes - * 2020-11-12 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include #include diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.c b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.c index f5787391f5ef4fd0c2e992ba632be8aa5f2fae9e..7525559fb10e8184b999fae24f6f0abe25f2d432 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.c +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_cmd_ioctl.c - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include #include diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.h b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.h index 54cab5fd0e5977ee8c98bc0f90a3b6f0907949e0..404efe7741a262d01b40686341ffe09a0c3681dc 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.h +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_cmd_ioctl.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_cmd_ioctl.h - * - * @brief Cloud platform command execution header file - * - * @revision - * Date Author Notes - * 2020-11-22 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef AGENT_TINY_CMD_IOCTL_H #define AGENT_TINY_CMD_IOCTL_H #include "atiny_mqtt/mqtt_client.h" diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_data_def.h b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_data_def.h index c8e954bca4601dbc916471fc86d06710de62b0e1..d2e51042c9a8ed2241611472c994a1e67cd75a4a 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_data_def.h +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_data_def.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_data_def.h - * - * @brief Data format of APP message defined on cloud platform - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __AGENT_TINY_DATA_DEF_H_ #define __AGENT_TINY_DATA_DEF_H_ #include diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.c b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.c index 4f0222a282c2bc9b68492a5fbe2ff8338c9fb172..1c31273dc8e88e73e3582e3351092c9d85b618b3 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.c +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.c @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_demo.c - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-12 OneOS Team First Version - *********************************************************************************************************************** - */ + #include #include "agent_tiny_demo.h" //#include "los_base.h" diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.h b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.h index 2eddcd2f918d3a096db0400c2aee9b1ba59673d6..cff2a6c8e35d01b9bbee17a2c90d0cad2b0d4786 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.h +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_demo.h @@ -31,28 +31,7 @@ * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_demo.h - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ + #ifndef __AGENT_TINY_DEMO_H_ #define __AGENT_TINY_DEMO_H_ diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.c b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.c index 34ce2b7832881d05c4a8889879f8c929dedcd7b1..59e7778e7f1d3c2663dd1dc4067a2aac8fed441b 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.c +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.c @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_report.c - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ #include #include "agent_tiny_demo.h" #include "los_task_adapter.h" diff --git a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.h b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.h index d1080532cc1a0b7b59f6735e8cde37600795f04a..49d3e4e66a9a0906591a58a4a177952ba1bb8275 100644 --- a/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.h +++ b/components/cloud/huawei/demos/agenttiny_mqtt/agent_tiny_report.h @@ -1,25 +1,3 @@ -/* - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file agent_tiny_report.h - * - * @brief Cloud platform command execution file - * - * @revision - * Date Author Notes - * 2020-12-22 OneOS Team First Version - *********************************************************************************************************************** - */ #ifndef __AGENT_TINY_REPORT_H__ #define __AGENT_TINY_REPORT_H__ diff --git a/components/cloud/onenet/mqtt-kit/Kconfig b/components/cloud/onenet/mqtt-kit/Kconfig index cf4c84684641ac01f0dc62fc925444da4c42b261..ad6ec98771a8d046bd362ae4db34d521e0464d95 100644 --- a/components/cloud/onenet/mqtt-kit/Kconfig +++ b/components/cloud/onenet/mqtt-kit/Kconfig @@ -20,7 +20,7 @@ config OS_USING_ONENET_MQTTS default n config ONENET_MQTTS_USING_AUTO_REGISTER - bool "Enable onenet device auto register" + bool "Enable onenet device auto register(new device must not select this option,old device must select this option)" default n config BUILD_ONENET_MQTTS_SAMPLE diff --git a/components/cloud/onenet/mqtt-kit/authorization/token.c b/components/cloud/onenet/mqtt-kit/authorization/token.c index 83216d91c302584bade3e7341053ead7fc11f816..a68776ed364a059fd461bf705e2abd96c4705244 100644 --- a/components/cloud/onenet/mqtt-kit/authorization/token.c +++ b/components/cloud/onenet/mqtt-kit/authorization/token.c @@ -154,13 +154,13 @@ int onenet_authorization(char *ver, memset(string_for_signature, 0, sizeof(string_for_signature)); if (flag) { - snprintf(string_for_signature, sizeof(string_for_signature), "%d\n%s\nproducts/%s\n%s", et, METHOD, res, ver); + snprintf(string_for_signature, sizeof(string_for_signature), "%u\n%s\nproducts/%s\n%s", et, METHOD, res, ver); } else { snprintf(string_for_signature, sizeof(string_for_signature), - "%d\n%s\nproducts/%s/devices/%s\n%s", + "%u\n%s\nproducts/%s/devices/%s\n%s", et, METHOD, res, @@ -192,7 +192,7 @@ int onenet_authorization(char *ver, { snprintf(authorization_buf, authorization_buf_len, - "version=%s&res=products%%2F%s&et=%d&method=%s&sign=%s", + "version=%s&res=products%%2F%s&et=%u&method=%s&sign=%s", ver, res, et, @@ -203,7 +203,7 @@ int onenet_authorization(char *ver, { snprintf(authorization_buf, authorization_buf_len, - "version=%s&res=products%%2F%s%%2Fdevices%%2F%s&et=%d&method=%s&sign=%s", + "version=%s&res=products%%2F%s%%2Fdevices%%2F%s&et=%u&method=%s&sign=%s", ver, res, dev_name, diff --git a/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_device_sample.h b/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_device_sample.h index 7317694012a88781181cc08e1f448fa3d1c1fed4..b8a67b8e6900cf8c32bce5fe26cfef9ed6d91c8c 100644 --- a/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_device_sample.h +++ b/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_device_sample.h @@ -34,19 +34,12 @@ #ifndef _ONENET_DEVICE_SAMPLE_H_ #define _ONENET_DEVICE_SAMPLE_H_ -#define USER_PRODUCT_ID "398523" -#define USER_ACCESS_KEY "TtqIgt8Q4S8u6iCOqEI1EmNWQr1x9eo+LpYMfRrz30s=" +#define USER_PRODUCT_ID "u3F813qG7o" +#define USER_ACCESS_KEY "p6OdzTWfIYNHtV/b3elfU6/7W3mP/WVv7UMHvfP7v0U=" #define USER_DEVICE_NAME \ - "pandora-mqtt-test" /*use characters, numbers or symbols like '_' or '-', \ + "onenet_mqtt_test" /*use characters, numbers or symbols like '_' or '-', \ no longer than 64, can use device serial num*/ #define USER_KEEPALIVE_INTERVAL 240 /*onenent heart interval 10~1800s*/ #define USER_PUBLISH_INTERVAL 10 /*user onenet data upload interval*/ -#ifndef ONENET_MQTTS_USING_AUTO_REGISTER -#define USER_DEVICE_ID "594722122" -#define USER_KEY "4EjlgCv+PW47/WK0ImryIOVwk9nXOYF2c6FJxRRRvfo=" -#endif - -extern const char *base_dp_upload_str; - #endif /* _ONENET_DEVICE_SAMPLE_H_ */ diff --git a/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_mqtts.c b/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_mqtts.c index 95ad05bb757d552e7c8330785609bbb17b8fb4eb..00e73829dc39b1a9972fad521d6d477983be8dd0 100644 --- a/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_mqtts.c +++ b/components/cloud/onenet/mqtt-kit/mqtts_device/onenet_mqtts.c @@ -93,8 +93,8 @@ #define SUBSCRIBE_IMAGE_TOPIC "$sys/%s/%s/image/#" /*rejected and accepted*/ #define MQTT_COMMAND_TIMEOUT 5000 /*or 30000ms*/ -#define MQTT_SEND_BUFF_SIZE 1024 -#define MQTT_READ_BUFF_SIZE 1024 +#define MQTT_SEND_BUFF_SIZE 2048 +#define MQTT_READ_BUFF_SIZE 2048 #define USER_MESSAGE_HANDLERS_NUM 5 /* must equal or less then MAX_MESSAGE_HANDLERS defined in MQTTClient.h*/ #define USER_MQTT_SUBTOPIC_LEN_MAX 128 @@ -136,7 +136,7 @@ typedef struct { char *ip; int port; - char pro_id[10]; + char pro_id[16]; char access_key[48]; char dev_name[64 + 1]; char dev_id[16]; @@ -296,16 +296,6 @@ int onenet_get_device_info(void) g_onenet_info.keepheart_interval = USER_KEEPALIVE_INTERVAL; -#ifndef ONENET_MQTTS_USING_AUTO_REGISTER - char dev_id[] = USER_DEVICE_ID; - char key[] = USER_KEY; - - memset(g_onenet_info.dev_id, 0, sizeof(g_onenet_info.dev_id)); - strcpy(g_onenet_info.dev_id, dev_id); - memset(g_onenet_info.key, 0, sizeof(g_onenet_info.key)); - strcpy(g_onenet_info.key, key); -#endif - return OS_TRUE; } @@ -527,12 +517,12 @@ static int set_onenet_state(onenet_state_t new_state) } #ifdef ONENET_MQTTS_USING_AUTO_REGISTER -static unsigned char get_device_resigter_state(void) +static unsigned char get_device_register_state(void) { return g_onenet_info.device_register; } -static void set_device_resigter_state(void) +static void set_device_register_state(void) { g_onenet_info.device_register = 1; } @@ -717,7 +707,7 @@ int onenet_mqtts_device_register(const char *access_key, int ret = OS_FALSE; register_network_t register_network; char version[] = "2018-10-31"; - unsigned int expiration_time = 1956499200; /* 2032-1-1 0:0:0 can set by user */ + unsigned int expiration_time = 4102416000; /* 2100-01-01 00:00:00 */ char authorization_buf[144] = {0}; unsigned short send_len = 11 + strlen(serial); int timeout = 5; @@ -780,16 +770,14 @@ int onenet_mqtts_device_register(const char *access_key, } if (data_ptr) { - char name[16]; + char name[16] = {0}; int pid = 0; - if (sscanf(data_ptr, - "device_id\" : \"%[^\"]\",\n \"name\" : \"%[^\"]\",\n \"pid\" : %d,\n \"key\" : " - "\"%[^\"]\"", + if (sscanf(data_ptr,"device_id\" : \"%[^\"]\",\n \"key\" : " "\"%[^\"]\",\n \"name\" : " "\"%[^\"]\",\n \"pid\" : %d,", dev_id, + key, name, - &pid, - key) == 4) + &pid) == 4) { LOG_I(DBG_EXT_TAG, "create device: %s, %s, %d, %s", dev_id, name, pid, key); ret = OS_TRUE; @@ -852,7 +840,7 @@ static int onenet_mqtts_client_connect(const char *username, const char *passwor static int onenet_device_link(const char *dev_name, const char *pro_id, const char *key) { char version[] = "2018-10-31"; - unsigned int expiration_time = 1956499200; + unsigned int expiration_time = 4102416000; /* 2100-01-01 00:00:00 */ char authorization_buf[160] = {0}; if (NULL == dev_name || NULL == pro_id || NULL == key) @@ -906,8 +894,13 @@ int onenet_mqtts_device_link(void) return OS_FALSE; } LOG_I(DBG_EXT_TAG, "establish network sucess"); - +#ifdef ONENET_MQTTS_USING_AUTO_REGISTER + /*onenet old product must use device access_key*/ if (OS_TRUE == onenet_device_link(g_onenet_info.dev_name, g_onenet_info.pro_id, g_onenet_info.key)) +#else + /*onenet new product only use product access_key*/ + if (OS_TRUE == onenet_device_link(g_onenet_info.dev_name, g_onenet_info.pro_id, g_onenet_info.access_key)) +#endif { onenet_event_callback(ONENET_EVENT_MQTTS_DEVICE_CONNECT_SUCCESS); ret = OS_TRUE; @@ -1101,77 +1094,6 @@ static int onenet_mqtts_client_publish(char *pubtopic, char *pub_msg) return OS_TRUE; } -/* method 1: publish data to onenet periodically, details in onenet_mqtts_device_entry() */ -#if 0 -static int onenet_mqtts_device_publish_cycle(os_tick_t *last_publish_tick) -{ - int ret = OS_TRUE; - os_tick_t tick_now = 0; - os_tick_t tick_pre = 0; - os_tick_t tick_diff = 0; - uint32_t publish_timeout = USER_PUBLISH_INTERVAL; - char *pro_id = USER_PRODUCT_ID; - char *dev_name = USER_DEVICE_NAME; - char pubtopic_buf[64] = {0}; - int pubtopic_buf_len = sizeof(pubtopic_buf); - char *pubtopic_filter = NULL; - char pub_buf[PUB_DATA_BUFF_LEN] = {0}; - static int data_id = 0; - int temperature_value = 0; - int power_value = 0; - char *publish_message_str = NULL; - /*char str[]="{\"id\":123,\"dp\":{\"temperature\":[{\"v\":50,}],\"power\":[{\"v\":6,}]}}";*/ - - snprintf(pubtopic_buf, pubtopic_buf_len, PUBLISH_DATA_TOPIC, pro_id, dev_name); - pubtopic_filter = pubtopic_buf; - - if (NULL == last_publish_tick) - { - return OS_FALSE; - } - - tick_now = os_tick_get_value(); - tick_pre = *last_publish_tick; - tick_diff = U32_DIFF(tick_now, tick_pre); - - if (tick_diff > os_tick_from_ms(publish_timeout * 1000)) - { - if (data_id != 2147483647) - { - data_id++; - } - else - { - data_id = 1; - } - temperature_value = rand() % 40; - power_value = rand() % 99; - snprintf(pub_buf, sizeof(pub_buf), base_dp_upload_str, data_id, temperature_value, power_value); - - publish_message_str = pub_buf; - if (NULL == publish_message_str) - { - return OS_FALSE; - } - - if (OS_TRUE == onenet_mqtts_client_publish(pubtopic_filter, publish_message_str)) - { - *last_publish_tick = tick_now; - onenet_event_callback(ONENET_EVENT_PUBLISH_SUCCESS); - ret = OS_TRUE; - } - else - { - /* here mqtts device has been disconnected */ - onenet_event_callback(ONENET_EVENT_MQTTS_DEVICE_DISCONNECT); - ret = OS_FALSE; - } - } - - return ret; -} -#endif - /** *********************************************************************************************************************** * @brief This function will let device publish MQTT message to OneNET. @@ -1268,7 +1190,7 @@ static int onenet_mqtts_device_entry(void) case ONENET_STATE_CONNECT: #ifdef ONENET_MQTTS_USING_AUTO_REGISTER - if (OS_FALSE == get_device_resigter_state()) + if (OS_FALSE == get_device_register_state()) { if (OS_FALSE == onenet_mqtts_device_register(g_onenet_info.access_key, g_onenet_info.pro_id, @@ -1280,7 +1202,7 @@ static int onenet_mqtts_device_entry(void) } else { - set_device_resigter_state(); + set_device_register_state(); onenet_event_callback(ONENET_EVENT_DEVICE_REGISTER_OK); continue; } diff --git a/components/cloud/onenet/mqtt-kit/mqtts_device/weave.yaml b/components/cloud/onenet/mqtt-kit/mqtts_device/weave.yaml index 91e03a58073a07e28c4b5bfe354c10a4a1ae1f7a..5fb824ae4088355a86c0ca184a5d497a58323e2e 100644 --- a/components/cloud/onenet/mqtt-kit/mqtts_device/weave.yaml +++ b/components/cloud/onenet/mqtt-kit/mqtts_device/weave.yaml @@ -12,4 +12,5 @@ build_option: # 源码（支持条件表达式） source_file: - - ./*.c?{is_define('OS_USING_ONENET_MQTTS')} \ No newline at end of file + - onenet_mqtts.c?{is_define('OS_USING_ONENET_MQTTS')} + - onenet_device_sample.c?{is_define('BUILD_ONENET_MQTTS_SAMPLE')} \ No newline at end of file diff --git a/components/cms/port/cms_adapter.h b/components/cms/port/cms_adapter.h index 6ec54c1bbb9794fbd102a8a8e4eb080b8919adb6..38920813f3fcbcd7f7d504781f82a482c190dcc9 100644 --- a/components/cms/port/cms_adapter.h +++ b/components/cms/port/cms_adapter.h @@ -21,16 +21,26 @@ ***********************************************************************************************************************/ #ifndef __CMS_ADAPTER_H__ #define __CMS_ADAPTER_H__ -#include +#include #if defined(__cplusplus) extern "C" { #endif #if defined(CMS_STD) -#define ASSERT(x) OS_ASSERT(x) +#define ASSERT(condition) \ + do \ + { \ + if (!(condition)) \ + { \ + printf("Assert failed. Condition(%s). [%s][%d]\r\n", #condition, __FUNCTION__, __LINE__); \ + cms_safety_assert_process(); \ + } \ + } while (0) + +void cms_safety_assert_process(void); #else -#define ASSERT(x) +#define ASSERT(condition) #endif #if defined(__cplusplus) diff --git a/components/cms/port/cms_net.h b/components/cms/port/cms_net.h index 71e6ef3d2bca7e6cf40000642ab2156066d09815..d07e7f81cab8d702c87245292810eeda9495b88c 100644 --- a/components/cms/port/cms_net.h +++ b/components/cms/port/cms_net.h @@ -21,7 +21,8 @@ ***********************************************************************************************************************/ #ifndef __CMS_NET_H__ #define __CMS_NET_H__ -#include +#include +#include #if defined(__cplusplus) extern "C" { @@ -41,22 +42,19 @@ extern "C" { #define CMS_HTONL(x) CMS_NTOHL(x) #endif -int cms_connect(const char *url, const char *port, const struct addrinfo *hints, struct sockaddr *to_addr); +enum CMS_TRANS_PROT_TYPE +{ + CMS_TCP, + CMS_UDP +}; -int cms_send_with_timeout(int fd, const void *data, size_t size, int timeout_ms); +void *cms_connect(const char *url, const char *port, enum CMS_TRANS_PROT_TYPE type); -int cms_sendto_with_timeout(int fd, - const void *data, - size_t size, - int timeout_ms, - const struct sockaddr *to, - size_t tolen); +int cms_send_with_timeout(void *net_handle, const void *data, size_t size, int timeout_ms); -int cms_recv_with_timeout(int fd, void *mem, size_t len, int timeout_ms); +int cms_recv_with_timeout(void *net_handle, void *mem, size_t len, int timeout_ms); -int cms_recvfrom_with_timeout(int fd, void *mem, size_t len, int timeout_ms, struct sockaddr *from, size_t *fromlen); - -int cms_closesocket(int fd); +int cms_closesocket(void *net_handle); #if defined(__cplusplus) } diff --git a/components/cms/port/oneos/atest/coap_atest.c b/components/cms/port/oneos/atest/coap_atest.c new file mode 100644 index 0000000000000000000000000000000000000000..994c85cf84967c291274c782d100aff8472c22c3 --- /dev/null +++ b/components/cms/port/oneos/atest/coap_atest.c @@ -0,0 +1,819 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2021, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file coap_atest.c + * + * @brief This is mqtt test file based atest. + * + * @revision + * Date Author Notes + * 2020-10-13 OneOS Team First Version + *********************************************************************************************************************** + */ +#include "oneos_config.h" +#if defined(CMS_CONNECT_COAP) +#include "cms_con_coap.h" +#include "cms_error.h" +#include "cms_def.h" +#include "cms_sem.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifndef OS_USING_DLOG +#error "pls enable dlog" +#endif +#include +#define LOG_TAG "cms_coap" +#if (SHELL_TASK_STACK_SIZE < 4096) +#error "shell task stack size must exceed 4095" +#endif + +#define COAP_TIME_OUT 5000 +#define COAP_BUFF_LENGTH 1024 +#define BLOCK_RES_NAME "block" +static int scode = 302; +static void *coap_context = NULL; +static cms_coap_optlist_t *coap_optlist = NULL; +static cms_coap_pdu_t *coap_pdu = NULL; +static os_task_id coap_task = NULL; +static const char *uri_path = "res"; +static const char *block_uri_path = BLOCK_RES_NAME; +static const char block_file[] = + "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 " + "42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 " + "80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 " + "113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 " + "141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 " + "169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 " + "197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 " + "225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 " + "253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 " + "281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 "; +static const int block_file_size = sizeof(block_file) - 1; +static const int block_size = 128; + +static cms_coap_method_code +cms_coap_response(void *coap_context, const cms_coap_pdu_t *sent, const cms_coap_pdu_t *received, uint32_t mid) +{ + printf("%d send pdu:\r\n", scode); + cms_coap_show_pdu(sent); + printf("mid = %d, recv pdu:\r\n", mid); + cms_coap_show_pdu(received); + return coap_empty_code; +} + +static int cms_coap_event(void *coap_context, const int error_code) +{ + LOG_E(LOG_TAG, "error code is %d", error_code); + return 0; +} + +static void atest_cms_coap_new_context_success(void) +{ + cms_coap_param param = {COAP_BUFF_LENGTH * 4, COAP_BUFF_LENGTH}; + cms_coap_free_context(coap_context); + coap_context = NULL; + coap_context = cms_coap_new_context(scode, ¶m); + tp_assert_true(coap_context != NULL); +} + +static void atest_cms_coap_new_context_fail(void) +{ + cms_coap_param error_param = {0, 0}; + cms_coap_free_context(coap_context); + coap_context = NULL; + coap_context = cms_coap_new_context(scode, &error_param); + tp_assert_true(coap_context == NULL); +} + +static void atest_cms_coap_new_context(void) +{ + atest_cms_coap_new_context_fail(); + atest_cms_coap_new_context_success(); +} + +static void atest_cms_coap_free_context_success(void) +{ + cms_coap_free_context(coap_context); + coap_context = NULL; +} + +static void atest_cms_coap_free_context_fail(void) +{ + cms_coap_free_context(NULL); //非法输入 +} + +static void atest_cms_coap_free_context(void) +{ + atest_cms_coap_free_context_fail(); + atest_cms_coap_free_context_success(); +} + +static void atest_cms_coap_create_session(void) +{ + int rc = cms_coap_create_session(NULL); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + if (coap_context == NULL) + atest_cms_coap_new_context_success(); + rc = cms_coap_create_session(coap_context); + tp_assert_true(rc == CMS_ERROR_SUCCESS); +} + +static void atest_cms_coap_release_session(void) +{ + int rc = cms_coap_release_session(NULL); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + if (coap_context == NULL) + atest_cms_coap_create_session(); + rc = cms_coap_release_session(coap_context); + tp_assert_true(rc == CMS_ERROR_SUCCESS); +} + +static void atest_cms_coap_register_response_handler(void) +{ + int rc; + rc = cms_coap_register_response_handler(NULL, cms_coap_response); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + if (coap_context == NULL) + atest_cms_coap_new_context_success(); + rc = cms_coap_register_response_handler(coap_context, NULL); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + rc = cms_coap_register_response_handler(coap_context, cms_coap_response); + tp_assert_true(rc == CMS_ERROR_SUCCESS); +} + +static void atest_cms_coap_register_event_handler(void) +{ + int rc; + rc = cms_coap_register_event_handler(NULL, cms_coap_event); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + if (coap_context == NULL) + atest_cms_coap_new_context_success(); + rc = cms_coap_register_event_handler(coap_context, NULL); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + rc = cms_coap_register_event_handler(coap_context, cms_coap_event); + tp_assert_true(rc == CMS_ERROR_SUCCESS); +} + +static void atest_cms_coap_new_single_optlist(cms_coap_option opt, int min_len, int max_len, const char *data) +{ + cms_coap_optlist_t *optlist; + + optlist = cms_coap_new_optlist(opt, min_len, (uint8_t *)data); + tp_assert_true(optlist != NULL); + cms_coap_delete_optlist(&optlist); + tp_assert_true(optlist == NULL); + + if (min_len != max_len) + { + optlist = cms_coap_new_optlist(opt, max_len, (uint8_t *)data); + tp_assert_true(optlist != NULL); + cms_coap_delete_optlist(&optlist); + tp_assert_true(optlist == NULL); + } + + if (min_len) + { + optlist = cms_coap_new_optlist(opt, min_len - 1, (uint8_t *)data); + tp_assert_true(optlist == NULL); + } + optlist = cms_coap_new_optlist(opt, max_len + 1, (uint8_t *)data); + tp_assert_true(optlist == NULL); +} + +static void atest_cms_coap_insert_single_optlist(cms_coap_option opt, int min_len, int max_len, const char *data) +{ + int rc; + cms_coap_optlist_t *head = cms_coap_new_optlist(coap_option_if_match, 0, NULL); + tp_assert_true(head != NULL); + + rc = cms_coap_insert_optlist(head, opt, min_len, (uint8_t *)data); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + + if (min_len != max_len) + { + rc = cms_coap_insert_optlist(head, opt, max_len, (uint8_t *)data); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + } + + if (min_len) + { + rc = cms_coap_insert_optlist(head, opt, min_len - 1, (uint8_t *)data); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + } + + if (max_len) + { + rc = cms_coap_insert_optlist(head, opt, max_len + 1, (uint8_t *)data); + tp_assert_true(rc != CMS_ERROR_SUCCESS); + } + cms_coap_delete_optlist(&head); +} + +static void atest_cms_coap_new_optlist(void) +{ + atest_cms_coap_new_single_optlist(coap_option_if_match, 0, 8, block_file); + atest_cms_coap_new_single_optlist(coap_option_uri_host, 1, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_etag, 1, 8, block_file); + atest_cms_coap_new_single_optlist(coap_option_if_none_match, 0, 0, block_file); + atest_cms_coap_new_single_optlist(coap_option_observe, 0, 3, block_file); + atest_cms_coap_new_single_optlist(coap_option_uri_port, 0, 2, block_file); + atest_cms_coap_new_single_optlist(coap_option_location_path, 0, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_uri_path, 0, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_content_type, 0, 2, block_file); + atest_cms_coap_new_single_optlist(coap_option_uri_query, 1, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_accept, 0, 2, block_file); + atest_cms_coap_new_single_optlist(coap_option_location_query, 0, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_block2, 0, 3, block_file); + atest_cms_coap_new_single_optlist(coap_option_block1, 0, 3, block_file); + atest_cms_coap_new_single_optlist(coap_option_size2, 0, 4, block_file); + atest_cms_coap_new_single_optlist(coap_option_proxy_uri, 1, 1034, block_file); + atest_cms_coap_new_single_optlist(coap_option_proxy_scheme, 1, 255, block_file); + atest_cms_coap_new_single_optlist(coap_option_size1, 0, 4, block_file); +} + +static void atest_cms_coap_insert_optlist(void) +{ + atest_cms_coap_insert_single_optlist(coap_option_if_match, 0, 8, block_file); + atest_cms_coap_insert_single_optlist(coap_option_uri_host, 1, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_etag, 1, 8, block_file); + atest_cms_coap_insert_single_optlist(coap_option_if_none_match, 0, 0, block_file); + atest_cms_coap_insert_single_optlist(coap_option_observe, 0, 3, block_file); + atest_cms_coap_insert_single_optlist(coap_option_uri_port, 0, 2, block_file); + atest_cms_coap_insert_single_optlist(coap_option_location_path, 0, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_uri_path, 0, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_content_type, 0, 2, block_file); + atest_cms_coap_insert_single_optlist(coap_option_uri_query, 1, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_accept, 0, 2, block_file); + atest_cms_coap_insert_single_optlist(coap_option_location_query, 0, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_block2, 0, 3, block_file); + atest_cms_coap_insert_single_optlist(coap_option_block1, 0, 3, block_file); + atest_cms_coap_insert_single_optlist(coap_option_size2, 0, 4, block_file); + atest_cms_coap_insert_single_optlist(coap_option_proxy_uri, 1, 1034, block_file); + atest_cms_coap_insert_single_optlist(coap_option_proxy_scheme, 1, 255, block_file); + atest_cms_coap_insert_single_optlist(coap_option_size1, 0, 4, block_file); +} + +#define CMS_COAP_NEW(x, l) \ + do \ + { \ + coap_optlist = cms_coap_new_optlist(x, strlen(#x) > l ? l : strlen(#x), (uint8_t *)#x); \ + tp_assert_true(coap_optlist != NULL); \ + } while (0) + +#define CMS_COAP_INSERT(x, l) \ + do \ + { \ + rc = cms_coap_insert_optlist(coap_optlist, x, strlen(#x) > l ? l : strlen(#x), (uint8_t *)#x); \ + tp_assert_true(rc == CMS_ERROR_SUCCESS); \ + } while (0) + +static void atest_cms_coap_insert_optlist_for_pdu(void) +{ + int rc; + + cms_coap_delete_optlist(&coap_optlist); + tp_assert_true(coap_optlist == NULL); + + CMS_COAP_NEW(coap_option_if_match, 8); + CMS_COAP_INSERT(coap_option_uri_host, 255); + CMS_COAP_INSERT(coap_option_etag, 8); + CMS_COAP_INSERT(coap_option_if_none_match, 0); + CMS_COAP_INSERT(coap_option_observe, 3); + CMS_COAP_INSERT(coap_option_uri_port, 2); + CMS_COAP_INSERT(coap_option_location_path, 255); + CMS_COAP_INSERT(coap_option_uri_path, 255); + CMS_COAP_INSERT(coap_option_content_type, 2); + CMS_COAP_INSERT(coap_option_uri_query, 255); + CMS_COAP_INSERT(coap_option_accept, 2); + CMS_COAP_INSERT(coap_option_location_query, 255); + CMS_COAP_INSERT(coap_option_block2, 3); + CMS_COAP_INSERT(coap_option_block1, 3); + CMS_COAP_INSERT(coap_option_size2, 4); + CMS_COAP_INSERT(coap_option_proxy_uri, 1034); + CMS_COAP_INSERT(coap_option_proxy_scheme, 255); + CMS_COAP_INSERT(coap_option_size1, 4); +} + +static void atest_cms_coap_delete_optlist(void) +{ + cms_coap_delete_optlist(&coap_optlist); + tp_assert_true(coap_optlist == NULL); +} + +static void atest_cms_coap_new_pdu(void) +{ + uint8_t data[] = "this is cms coap!"; + cms_coap_delete_pdu(&coap_pdu); + if (coap_context == NULL) + atest_cms_coap_new_context_success(); + if (coap_optlist == NULL) + { + atest_cms_coap_insert_optlist_for_pdu(); + } + coap_pdu = cms_coap_new_pdu(coap_context, + coap_message_confirmable, + coap_request_code_post, + &coap_optlist, + data, + strlen((char *)data)); + tp_assert_true(coap_pdu != NULL); + atest_cms_coap_delete_optlist(); +} + +static void atest_cms_coap_delete_pdu(void) +{ + cms_coap_delete_pdu(&coap_pdu); + tp_assert_true(coap_pdu == NULL); +} + +static void atest_cms_coap_send(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + if (coap_pdu == NULL) + atest_cms_coap_new_pdu(); + int rc = cms_coap_send(coap_context, &coap_pdu); + tp_assert_true(rc == CMS_ERROR_SUCCESS && coap_pdu == NULL); +} + +static int atest_cms_coap_io_process_single_time(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + if (coap_context && cms_coap_get_state(coap_context) == cms_con_state_connect) + { + return cms_coap_io_process(coap_context); + } + return CMS_ERROR_GENERIC_ERROR; +} + +static void atest_cms_coap_io_process(void) +{ + tp_assert_true(atest_cms_coap_io_process_single_time() == CMS_ERROR_SUCCESS); +} + +static void cms_coap_task_handle(void *param) +{ + printf("start coap task.\r\n"); + atest_cms_coap_io_process(); + while (coap_context != NULL || cms_coap_get_state(coap_context) == cms_con_state_connect) + { + os_task_msleep(10); + int rc = cms_coap_io_process(coap_context); + if (CMS_ERROR_SUCCESS != rc) + { + printf("coap io process error %d.\r\n", rc); + } + } + printf("stop coap task.\r\n"); + coap_task = NULL; +} + +static void atest_cms_coap_io_process_start(void) +{ + if (coap_task != NULL) + { + return; + } + coap_task = os_task_create(NULL, NULL, 8192, "cms coap", cms_coap_task_handle, NULL, OS_TASK_PRIORITY_MAX / 2); + OS_ASSERT(coap_task); + os_task_startup(coap_task); +} + +static void atest_cms_coap_io_process_stop(void) +{ + if (coap_task == NULL) + { + return; + } + os_task_destroy(coap_task); + printf("stop coap task.\r\n"); + coap_task = NULL; + return; +} + +static void atest_cms_coap_get_state(void) +{ + if (cms_coap_get_state(coap_context) == cms_con_state_connect) + printf("%d is connected\r\n", scode); + else + printf("%d is not connected\r\n", scode); +} + +//场景测试 +static void atest_cms_coap_operation_func(cms_coap_message_type type, cms_coap_method_code code, const char *body) +{ + cms_coap_optlist_t *optlist = cms_coap_new_optlist(coap_option_uri_path, strlen(uri_path), (uint8_t *)uri_path); + tp_assert_true(optlist != NULL); + size_t body_len = 0; + int rc; + if (body != NULL) + body_len = strlen(body); + cms_coap_pdu_t *pdu = cms_coap_new_pdu(coap_context, type, code, &optlist, (uint8_t *)body, body_len); + tp_assert_true(pdu != NULL); + rc = cms_coap_send(coap_context, &pdu); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + os_task_msleep(COAP_TIME_OUT); + atest_cms_coap_io_process(); + cms_coap_delete_optlist(&optlist); + cms_coap_delete_pdu(&pdu); +} + +static void atest_cms_coap_operation_post(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + atest_cms_coap_register_response_handler(); + atest_cms_coap_operation_func(coap_message_confirmable, coap_request_code_post, "put confirmable message"); + atest_cms_coap_operation_func(coap_message_non_confirmable, coap_request_code_post, "put non confirmable message"); +} + +static void atest_cms_coap_operation_put(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + atest_cms_coap_register_response_handler(); + atest_cms_coap_operation_func(coap_message_confirmable, coap_request_code_put, "put confirmable message"); + atest_cms_coap_operation_func(coap_message_non_confirmable, coap_request_code_put, "put non confirmable message"); +} + +static void atest_cms_coap_operation_get(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + atest_cms_coap_register_response_handler(); + atest_cms_coap_operation_func(coap_message_confirmable, coap_request_code_get, NULL); + atest_cms_coap_operation_func(coap_message_non_confirmable, coap_request_code_get, NULL); +} + +static void atest_cms_coap_operation_del(void) +{ + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + atest_cms_coap_register_response_handler(); + + atest_cms_coap_operation_func(coap_message_confirmable, coap_request_code_delete, NULL); + atest_cms_coap_operation_func(coap_message_non_confirmable, coap_request_code_delete, NULL); +} + +//块传输 +static uint16_t atest_cms_coap_coap_log_2(uint16_t value) +{ + uint16_t result = 0; + do + { + value = value >> 1; + result++; + } while (value); + + return result ? result - 1 : result; +} + +static uint32_t atest_cms_coap_structure_block(int block_num, char more_flag, int block_size) +{ + OS_ASSERT(block_num < 0x1000000); + uint32_t block = block_num << 4; + if (more_flag) + { + block |= 0x8; + } + block |= (atest_cms_coap_coap_log_2(block_size / 16) & 0x7); + return block; +} + +struct cms_coap_block +{ + const char *uri_path; //资源名字 + uint8_t *block_buff; // block接收缓存 + size_t totol_length; //缓存最大长度 + uint32_t sent_block_num; //已发送block序号 + uint16_t block_size; //块大小 + uint8_t more_flag; //是否还有更多的块 + void *sem; //信号量 +}; +static struct cms_coap_block coap_block = {NULL, NULL, 0, 0, 0, 0, NULL}; + +static void destroy_coap_block(struct cms_coap_block *coap_block) +{ + if (coap_block->block_buff) + free(coap_block->block_buff); + if (coap_block->sem) + cms_sem_destroy(coap_block->sem); + memset(coap_block, 0, sizeof(struct cms_coap_block)); +} + +static cms_coap_method_code atest_cms_coap_block_post_handle(void *coap_context, + const cms_coap_pdu_t *sent, + const cms_coap_pdu_t *received, + uint32_t mid) +{ + printf("%d send pdu:\r\n", scode); + cms_coap_show_pdu(sent); + printf("recv pdu:\r\n"); + cms_coap_show_pdu(received); + OS_ASSERT(coap_block.sem); + cms_sem_post(coap_block.sem); + return coap_empty_code; +} + +static void atest_cms_coap_block_post(void) +{ + int rc; + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + destroy_coap_block(&coap_block); + coap_block.uri_path = block_uri_path; + coap_block.block_size = block_size; + coap_block.sem = cms_sem_create(BLOCK_RES_NAME, 0, 1); + if (coap_block.sem == NULL) + { + LOG_E(LOG_TAG, "out of memory"); + return; + } + rc = cms_coap_register_response_handler(coap_context, atest_cms_coap_block_post_handle); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + int block_num = 0; + atest_cms_coap_io_process_start(); //开始io调度 + while ((block_num * block_size) < block_file_size) + { + uint8_t buff[4]; + cms_coap_optlist_t *optlist = + cms_coap_new_optlist(coap_option_uri_path, strlen(block_uri_path), (uint8_t *)block_uri_path); + tp_assert_true(optlist != NULL); // uri + int more_flag = 0; + int single_len = block_file_size - (block_num * block_size); + if (single_len > block_size) + { + single_len = block_size; + more_flag = 1; + } + uint32_t block1 = atest_cms_coap_structure_block(block_num, more_flag, block_size); + buff[0] = (block1 >> 16) & 0xFF; + buff[1] = (block1 >> 8) & 0xFF; + buff[2] = block1 & 0xFF; + rc = cms_coap_insert_optlist(optlist, coap_option_block1, 3, buff); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + buff[0] = (block_file_size >> 24) & 0xFF; + buff[1] = (block_file_size >> 16) & 0xFF; + buff[2] = (block_file_size >> 8) & 0xFF; + buff[3] = block_file_size & 0xFF; + rc = cms_coap_insert_optlist(optlist, coap_option_size1, 4, buff); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + cms_coap_pdu_t *pdu = cms_coap_new_pdu(coap_context, + coap_message_confirmable, + coap_request_code_post, + &optlist, + (uint8_t *)&block_file[block_num * block_size], + single_len); + tp_assert_true(pdu != NULL); + rc = cms_coap_send(coap_context, &pdu); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + cms_coap_delete_optlist(&optlist); + cms_coap_delete_pdu(&pdu); + // os_task_msleep(100); + if (cms_sem_wait(coap_block.sem, COAP_TIME_OUT * 10)) + { + LOG_E(LOG_TAG, "block %d post error", block_num); + break; + } + block_num++; + } + atest_cms_coap_io_process_stop(); + os_task_msleep(500); + destroy_coap_block(&coap_block); +} + +static cms_coap_method_code atest_cms_coap_block_get_handle(void *coap_context, + const cms_coap_pdu_t *sent, + const cms_coap_pdu_t *received, + uint32_t mid) +{ + OS_ASSERT(received != NULL); + cms_coap_optlist_t *optlist = NULL; + int block_num = 0; + char recv_block_more = 0; + int recv_block_size = 0; + int total_size = 0; + int rc = cms_coap_deserialization_option_list(received->option_data, received->option_len, &optlist); + if (rc != CMS_ERROR_SUCCESS || optlist == NULL) + { + LOG_E(LOG_TAG, "block get error!"); + cms_coap_show_pdu(received); + return coap_empty_code; + } + cms_coap_optlist_t *node = optlist; + while (node) + { + if (node->number == coap_option_uri_path) + { + if (memcmp(node->data, coap_block.uri_path, node->length)) + { + LOG_W(LOG_TAG, "resources is not %s", coap_block.uri_path); + break; + } + } + if (node->number == coap_option_block2) + { + int block_len = node->length; + int block2 = 0; + int index = 0; + while (block_len--) + { + block2 = (block2 << 8); + block2 += node->data[index++]; + } + block_num = (block2 >> 4); + if (block2 & 0x08) + recv_block_more = 1; + recv_block_size = 1 << ((block2 & 0x07) + 4); + } + if (node->number == coap_option_size2) + { + int node_len = node->length; + int size2 = 0; + int index = 0; + while (node_len--) + { + size2 = (size2 << 8); + size2 += node->data[index++]; + } + total_size = size2; + } + node = node->next; + } + cms_coap_delete_optlist(&optlist); + if (!recv_block_size || !total_size) + { + goto error; //报文异常，退出处理 + } + if (!received->body_len || received->body_data == NULL) + { + goto error; + } + if (coap_block.totol_length != total_size) + { + if (block_num) + { + LOG_E(LOG_TAG, "The total size has been modified, please try again"); + goto error; + } + coap_block.block_buff = realloc(coap_block.block_buff, total_size); + if (coap_block.block_buff == NULL) + { + LOG_E(LOG_TAG, "out of memory"); + return coap_empty_code; + } + memset(coap_block.block_buff, 0, total_size); + coap_block.totol_length = total_size; + } + if (block_num * block_size + received->body_len > coap_block.totol_length || block_num != coap_block.sent_block_num) + { + LOG_E(LOG_TAG, "block number(%d) error", block_num); + goto error; + } + LOG_I(LOG_TAG, "recv block %d", block_num); + memcpy(&coap_block.block_buff[block_num * block_size], received->body_data, received->body_len); + coap_block.more_flag = recv_block_more; + OS_ASSERT(coap_block.sem); + cms_sem_post(coap_block.sem); + return coap_empty_code; +error: + LOG_E(LOG_TAG, "Not expected message", mid); + cms_coap_show_pdu(received); + return coap_empty_code; +} +static int atest_cms_coap_single_block_get(struct cms_coap_block coap_block) +{ + uint8_t buff[4]; + uint32_t block2; + cms_coap_pdu_t *pdu = NULL; + cms_coap_optlist_t *optlist = NULL; + int rc; + optlist = cms_coap_new_optlist(coap_option_uri_path, strlen(coap_block.uri_path), (uint8_t *)coap_block.uri_path); + if (optlist == NULL) + return -1; + block2 = atest_cms_coap_structure_block(coap_block.sent_block_num, 0, coap_block.block_size); + buff[0] = (block2 >> 16) & 0xFF; + buff[1] = (block2 >> 8) & 0xFF; + buff[2] = block2 & 0xFF; + rc = cms_coap_insert_optlist(optlist, coap_option_block2, 3, buff); + if (rc != CMS_ERROR_SUCCESS) + { + goto exit; + } + pdu = cms_coap_new_pdu(coap_context, coap_message_confirmable, coap_request_code_get, &optlist, NULL, 0); + if (pdu == NULL) + { + rc = -1; + goto exit; + } + rc = cms_coap_send(coap_context, &pdu); +exit: + cms_coap_delete_optlist(&optlist); + cms_coap_delete_pdu(&pdu); + return rc; +} + +static void atest_cms_coap_block_get(void) +{ + int rc; + if (coap_context == NULL || cms_coap_get_state(coap_context) != cms_con_state_connect) + atest_cms_coap_create_session(); + destroy_coap_block(&coap_block); + coap_block.uri_path = block_uri_path; + coap_block.block_size = block_size; + coap_block.sem = cms_sem_create(BLOCK_RES_NAME, 0, 1); + if (coap_block.sem == NULL) + { + LOG_E(LOG_TAG, "out of memory"); + return; + } + rc = cms_coap_register_response_handler(coap_context, atest_cms_coap_block_get_handle); + tp_assert_true(rc == CMS_ERROR_SUCCESS); + atest_cms_coap_io_process_start(); //开始io调度 + do + { + rc = atest_cms_coap_single_block_get(coap_block); + if (rc != CMS_ERROR_SUCCESS) + { + tp_assert_true(0); + LOG_E(LOG_TAG, "block sent error"); + break; + } + rc = cms_sem_wait(coap_block.sem, COAP_TIME_OUT * 10); + if (rc) + { + tp_assert_true(0); + LOG_E(LOG_TAG, "time out(%d s)", COAP_TIME_OUT / 100); + break; + } + ++coap_block.sent_block_num; + if (coap_block.sent_block_num * coap_block.block_size >= coap_block.totol_length) + { + tp_assert_true(1); + LOG_I(LOG_TAG, "block transfer completed"); + break; + } + } while (coap_block.more_flag); + if (rc == CMS_ERROR_SUCCESS) + { + LOG_I(LOG_TAG, "bolck recv finish"); + LOG_HEX(LOG_TAG, 16, coap_block.block_buff, coap_block.totol_length); + } + atest_cms_coap_io_process_stop(); + os_task_msleep(500); + destroy_coap_block(&coap_block); +} + +static void atest_cms_coap_free_all(void) +{ + atest_cms_coap_free_context_success(); + cms_coap_delete_optlist(&coap_optlist); + tp_assert_true(coap_optlist == NULL); + cms_coap_delete_pdu(&coap_pdu); + tp_assert_true(coap_pdu == NULL); + atest_cms_coap_io_process_stop(); +} + +ATEST_TC_EXPORT(cms.coap.context.new, atest_cms_coap_new_context, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.context.free, atest_cms_coap_free_context, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.creat.session, atest_cms_coap_create_session, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.release.session, atest_cms_coap_release_session, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.reg.resp, atest_cms_coap_register_response_handler, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.reg.event, atest_cms_coap_register_event_handler, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.option.new, atest_cms_coap_new_optlist, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.option.insert, atest_cms_coap_insert_optlist, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.option.delete, atest_cms_coap_delete_optlist, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.pdu.new, atest_cms_coap_new_pdu, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.pdu.send, atest_cms_coap_send, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.pdu.delete, atest_cms_coap_delete_pdu, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.io.single, atest_cms_coap_io_process, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.io.start, atest_cms_coap_io_process_start, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.io.stop, atest_cms_coap_io_process_stop, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.state, atest_cms_coap_get_state, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.post.res, atest_cms_coap_operation_post, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.put.res, atest_cms_coap_operation_put, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.get.res, atest_cms_coap_operation_get, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.del.res, atest_cms_coap_operation_del, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.block.post, atest_cms_coap_block_post, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.operation.block.get, atest_cms_coap_block_get, NULL, NULL, TC_PRIORITY_LOW); +ATEST_TC_EXPORT(cms.coap.free, atest_cms_coap_free_all, NULL, NULL, TC_PRIORITY_LOW); + +#endif diff --git a/components/cms/port/oneos/cms_adapter.c b/components/cms/port/oneos/cms_adapter.c new file mode 100644 index 0000000000000000000000000000000000000000..8d0c979caf6295e94269d1c4a779a163afdf6200 --- /dev/null +++ b/components/cms/port/oneos/cms_adapter.c @@ -0,0 +1,31 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2021, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file cms_adapter.c + * + * @brief Interface related to OS. + * + * @revision + * Date Author Notes + * 2020-10-13 OneOS Team First Version + *********************************************************************************************************************** + */ +#include "cms_adapter.h" +#include + +void cms_safety_assert_process(void) +{ + os_irq_disable(); + while (1) + ; +} diff --git a/components/cms/port/oneos/cms_mutex.c b/components/cms/port/oneos/cms_mutex.c index 9c7e56248390074be5ca1ab4c1e2812d6b3810af..394ce8ef1ee96165baea7d64965bb8b4b4daaaa0 100644 --- a/components/cms/port/oneos/cms_mutex.c +++ b/components/cms/port/oneos/cms_mutex.c @@ -46,16 +46,22 @@ void *mutex_create(void) void mutex_destroy(void *mutex) { + if (mutex == NULL) + return; (void)os_mutex_destroy(*(os_mutex_id *)mutex); cms_free(mutex); } void mutex_lock(void *mutex) { + if (mutex == NULL) + return; os_mutex_recursive_lock(*(os_mutex_id *)mutex, OS_WAIT_FOREVER); } void mutex_unlock(void *mutex) { + if (mutex == NULL) + return; os_mutex_recursive_unlock(*(os_mutex_id *)mutex); } diff --git a/components/cms/port/oneos/cms_net.c b/components/cms/port/oneos/cms_net.c index c268928a6e429d87c9df494d37b5fbee0a2a76f3..32ca2b22ed1fbaa2abba1b255c351dd91a7ac238 100644 --- a/components/cms/port/oneos/cms_net.c +++ b/components/cms/port/oneos/cms_net.c @@ -21,41 +21,61 @@ *********************************************************************************************************************** */ #include "cms_net.h" +#include "cms_memory.h" #include #include #include #include -int cms_connect(const char *url, const char *port, const struct addrinfo *addr_info, struct sockaddr *to_addr) +typedef struct __CMS_NET_HANDEL__ +{ + int type; + struct sockaddr to_addr; + int fd; +} CMS_NET_HANDEL; + +void *cms_connect(const char *url, const char *port, enum CMS_TRANS_PROT_TYPE type) { int fd = -1; struct addrinfo *addr_list; struct addrinfo *addr; + struct addrinfo addr_info; + struct sockaddr to_addr; + + cms_memset(&addr_info, 0, sizeof(addr_info)); + if (CMS_TCP == type) + { + addr_info.ai_protocol = IPPROTO_TCP; + addr_info.ai_socktype = SOCK_STREAM; + } + else if (CMS_UDP == type) + { + addr_info.ai_protocol = IPPROTO_UDP; + addr_info.ai_socktype = SOCK_DGRAM; + } + else + return NULL; - if (getaddrinfo(url, port, addr_info, &addr_list)) + if (getaddrinfo(url, port, &addr_info, &addr_list)) { - return fd; + return NULL; } for (addr = addr_list; addr != NULL; addr = addr->ai_next) { - // if (addr_info->sa_family != addr->ai_addr->sa_family) - // { - // continue; - // } fd = socket(addr->ai_family, addr->ai_socktype, addr->ai_protocol); if (fd < 0) { continue; } - if (addr_info->ai_protocol == IPPROTO_UDP) + if (type == CMS_UDP) { - *to_addr = *(addr->ai_addr); + to_addr = *(addr->ai_addr); break; } - if (addr_info->ai_socktype == SOCK_STREAM && connect(fd, addr->ai_addr, addr->ai_addrlen) == 0) + if (type == CMS_TCP && connect(fd, addr->ai_addr, addr->ai_addrlen) == 0) { break; } @@ -63,10 +83,18 @@ int cms_connect(const char *url, const char *port, const struct addrinfo *addr_i fd = -1; } freeaddrinfo(addr_list); - return fd; + if (fd < 0) + return NULL; + CMS_NET_HANDEL *handle = cms_malloc(sizeof(CMS_NET_HANDEL)); + if (handle == NULL) + return NULL; + handle->type = type; + handle->to_addr = to_addr; + handle->fd = fd; + return (void *)handle; } -int cms_send_with_timeout(int fd, const void *data, size_t size, int timeout_ms) +static int cms_tcp_send(int fd, const void *data, size_t size, int timeout_ms) { if (timeout_ms) { @@ -76,22 +104,17 @@ int cms_send_with_timeout(int fd, const void *data, size_t size, int timeout_ms) return send(fd, data, size, 0); } -int cms_sendto_with_timeout(int fd, - const void *data, - size_t size, - int timeout_ms, - const struct sockaddr *to, - size_t tolen) +static int cms_udp_send(int fd, const void *data, size_t size, int timeout_ms, const struct sockaddr *to, size_t tolen) { if (timeout_ms) { struct timeval interval = {timeout_ms / 1000, (timeout_ms % 1000) * 1000}; setsockopt(fd, SOL_SOCKET, SO_SNDTIMEO, (char *)&interval, sizeof(struct timeval)); } - return sendto(fd, data, size, 0, to, sizeof(struct sockaddr)); + return sendto(fd, data, size, 0, to, tolen); } -int cms_recv_with_timeout(int fd, void *data, size_t size, int timeout_ms) +static int cms_tcp_recv(int fd, void *data, size_t size, int timeout_ms) { int rc; struct timeval interval; @@ -110,13 +133,13 @@ int cms_recv_with_timeout(int fd, void *data, size_t size, int timeout_ms) rc = recv(fd, data, size, 0); if (rc == 0) { - cms_closesocket(fd); + closesocket(fd); return -1; } return rc; } -int cms_recvfrom_with_timeout(int fd, void *data, size_t size, int timeout_ms, struct sockaddr *from, size_t *fromlen) +static int cms_udp_recv(int fd, void *data, size_t size, int timeout_ms, struct sockaddr *from, uint32_t *fromlen) { int rc; struct timeval interval; @@ -133,10 +156,46 @@ int cms_recvfrom_with_timeout(int fd, void *data, size_t size, int timeout_ms, s { return rc; } - return recvfrom(fd, data, size, 0, from, (socklen_t *)fromlen); + return recvfrom(fd, data, size, 0, from, fromlen); +} + +int cms_send_with_timeout(void *net_handle, const void *data, size_t size, int timeout_ms) +{ + CMS_NET_HANDEL *handle = (CMS_NET_HANDEL *)net_handle; + if (handle == NULL) + return -1; + if (handle->type == CMS_TCP) + { + return cms_tcp_send(handle->fd, data, size, timeout_ms); + } + else + { + return cms_udp_send(handle->fd, data, size, timeout_ms, &(handle->to_addr), sizeof(handle->to_addr)); + } } -int cms_closesocket(int fd) +int cms_recv_with_timeout(void *net_handle, void *mem, size_t len, int timeout_ms) { - return closesocket(fd); + CMS_NET_HANDEL *handle = (CMS_NET_HANDEL *)net_handle; + if (handle == NULL) + return -1; + if (handle->type == CMS_TCP) + { + return cms_tcp_recv(handle->fd, mem, len, timeout_ms); + } + else + { + uint32_t fromlen = sizeof(handle->to_addr); + return cms_udp_recv(handle->fd, mem, len, timeout_ms, &(handle->to_addr), &fromlen); + } +} + +int cms_closesocket(void *net_handle) +{ + CMS_NET_HANDEL *handle = (CMS_NET_HANDEL *)net_handle; + if (handle == NULL) + return -1; + int rc = closesocket(handle->fd); + cms_free(handle); + return rc; } diff --git a/components/cms/port/oneos/weave.yaml b/components/cms/port/oneos/weave.yaml index b9dda15edd0be4d89d510411b37ccb192684aaa2..cf259c1a939f041d82e832dee542e18e66b731e2 100644 --- a/components/cms/port/oneos/weave.yaml +++ b/components/cms/port/oneos/weave.yaml @@ -15,4 +15,5 @@ source_file: - cms_ring_buff.c - cms_sem.c - cms_thread.c + - cms_adapter.c \ No newline at end of file diff --git a/components/gui/lvgl8.2/Kconfig b/components/gui/lvgl8.2/Kconfig index 435f9ac02591c26391557b9efcc4e219f07128f6..8c15121a75611af2127ccce81103f8d505bc3d96 100644 --- a/components/gui/lvgl8.2/Kconfig +++ b/components/gui/lvgl8.2/Kconfig @@ -478,21 +478,15 @@ menu "LVGL FileSystem" select OS_SFUD_USING_QSPI select OS_SFLASH_SUPPORT select OS_USING_FAL - select OS_USING_AUTO_MOUNT + select OS_USING_AUTO_MOUNT - if OS_LV_FS_MOUNT_SFALSH + if OS_LV_FS_MOUNT_SFALSH choice - prompt "select mount fs type" - default OS_LV_MOUNT_FS_TYPE_JFFS2 - - config OS_LV_MOUNT_FS_TYPE_JFFS2 - bool "use jffs2 fs and mounted" - select OS_USING_VFS_JFFS2 - - config OS_LV_MOUNT_FS_TYPE_FATFS - bool "use fat fs and mounted" + prompt "select mount fs type" + default OS_LV_MOUNT_FS_TYPE_FATFS + config OS_LV_MOUNT_FS_TYPE_FATFS + bool "use fat fs and mounted" select OS_USING_VFS_FATFS - endchoice endif diff --git a/components/iotjs/deps/libtuv/include/uv-oneos.h b/components/iotjs/deps/libtuv/include/uv-oneos.h index 274b8ef411a9652a60339ddf94aed642af519442..2c46d0315e7e1a1a1197d86f37b4a9458dd22143 100644 --- a/components/iotjs/deps/libtuv/include/uv-oneos.h +++ b/components/iotjs/deps/libtuv/include/uv-oneos.h @@ -1,4 +1,48 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file uv-oneos.h + * + * @brief + * + * @revision + * Date Author Notes + * 2020-03-05 OneOS Team First version. + *********************************************************************************************************************** + */ + +/* Copyright Joyent, Inc. and other Node contributors. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + #ifndef UV_ONEOS_H #define UV_ONEOS_H diff --git a/components/iotjs/deps/libtuv/src/unix/oneos-event.c b/components/iotjs/deps/libtuv/src/unix/oneos-event.c index 66c76a15f4474b67ea88ac5756ed9201072d4cd2..3a75e05b9d2fc9575a52b0d47320549215eeb0fd 100644 --- a/components/iotjs/deps/libtuv/src/unix/oneos-event.c +++ b/components/iotjs/deps/libtuv/src/unix/oneos-event.c @@ -11,15 +11,37 @@ * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * - * @file socket.c + * @file oneos-event.c * - * @brief Implement socket functions + * @brief eventfs func adaptation for oneos * * @revision * Date Author Notes * 2020-03-21 OneOS Team First Version *********************************************************************************************************************** */ + +/* Copyright Joyent, Inc. and other Node contributors. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + #include #include #include diff --git a/components/iotjs/deps/libtuv/src/unix/oneos.c b/components/iotjs/deps/libtuv/src/unix/oneos.c index e0110d7e62257a2ed36048b565b3817311cfb98f..d7928aac7b0a48b8e01e55a2c5d43348e5645de2 100644 --- a/components/iotjs/deps/libtuv/src/unix/oneos.c +++ b/components/iotjs/deps/libtuv/src/unix/oneos.c @@ -11,9 +11,9 @@ * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * - * @file socket.c + * @file oneos.c * - * @brief Implement socket functions + * @brief uv functions adaptation for oneos * * @revision * Date Author Notes @@ -21,6 +21,27 @@ *********************************************************************************************************************** */ +/* Copyright Joyent, Inc. and other Node contributors. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + #include #include #include diff --git a/components/iotjs/src/modules/oneos/iotjs_module_gpio-oneos.c b/components/iotjs/src/modules/oneos/iotjs_module_gpio-oneos.c index 4b7c07da8837996508f284285edd7372c7556144..0e6073b651effee58d5fc8d40fe0d4eeddec8d42 100644 --- a/components/iotjs/src/modules/oneos/iotjs_module_gpio-oneos.c +++ b/components/iotjs/src/modules/oneos/iotjs_module_gpio-oneos.c @@ -1,3 +1,17 @@ +/* Copyright 2016-present Samsung Electronics Co., Ltd. and other contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include "modules/iotjs_module_gpio.h" #include "pin.h" diff --git a/components/iotjs/src/modules/oneos/iotjs_module_i2c-oneos.c b/components/iotjs/src/modules/oneos/iotjs_module_i2c-oneos.c index 0b443d80f2f0181fdc22f5f827a828b22f8933a3..4e063c2c177f8fb7534aadd41a6873ef560651f7 100644 --- a/components/iotjs/src/modules/oneos/iotjs_module_i2c-oneos.c +++ b/components/iotjs/src/modules/oneos/iotjs_module_i2c-oneos.c @@ -1,3 +1,17 @@ +/* Copyright 2016-present Samsung Electronics Co., Ltd. and other contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include #include diff --git a/components/iotjs/src/modules/oneos/iotjs_module_pwm-oneos.c b/components/iotjs/src/modules/oneos/iotjs_module_pwm-oneos.c index d08d01fd5b916fb1d9c98db4cad8808bfdf41b3a..2209d2f82bfb2502483f893bf542441e214de414 100644 --- a/components/iotjs/src/modules/oneos/iotjs_module_pwm-oneos.c +++ b/components/iotjs/src/modules/oneos/iotjs_module_pwm-oneos.c @@ -1,3 +1,17 @@ +/* Copyright 2016-present Samsung Electronics Co., Ltd. and other contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include #include diff --git a/components/iotjs/src/platform/oneos/iotjs_oneos.c b/components/iotjs/src/platform/oneos/iotjs_oneos.c index 28338c34813161f7ab2bf853e16a486d9d34313e..52cebdbd4f8ba20041b6d99674604668839a2623 100644 --- a/components/iotjs/src/platform/oneos/iotjs_oneos.c +++ b/components/iotjs/src/platform/oneos/iotjs_oneos.c @@ -1,3 +1,26 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file iotjs_oneos.c + * + * @brief Implementation of iotjs running cmd. + * + * @revision + * Date Author Notes + * 2020-03-05 OneOS Team First version. + *********************************************************************************************************************** + */ + #include "oneos_config.h" #include #include diff --git a/components/iotjs/src/platform/oneos/iotjs_recvfile.c b/components/iotjs/src/platform/oneos/iotjs_recvfile.c index 8366864c34737226eeb9c4c1ff91c19a9d0a8879..b69c5980a86148387fe9007907eaef596b1ae813 100644 --- a/components/iotjs/src/platform/oneos/iotjs_recvfile.c +++ b/components/iotjs/src/platform/oneos/iotjs_recvfile.c @@ -1,3 +1,26 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file iotjs_recfile.c + * + * @brief Implementation of recvfile func. + * + * @revision + * Date Author Notes + * 2020-03-05 OneOS Team First version. + *********************************************************************************************************************** + */ + #include "oneos_config.h" #include #include diff --git a/components/net/protocols/mqtt/pahomqtt-v1.1.0/MQTTClient-OneOS/samples/mqtt_sample.c b/components/net/protocols/mqtt/pahomqtt-v1.1.0/MQTTClient-OneOS/samples/mqtt_sample.c index 4f05e28a155d84d21d45a9d4f20c1318f85b603f..ba80a2760a0156b609649cd6ca2d1316a151a0f4 100644 --- a/components/net/protocols/mqtt/pahomqtt-v1.1.0/MQTTClient-OneOS/samples/mqtt_sample.c +++ b/components/net/protocols/mqtt/pahomqtt-v1.1.0/MQTTClient-OneOS/samples/mqtt_sample.c @@ -122,8 +122,8 @@ static void mqtt_sample_task_func(void *arg) connectData.cleansession = 1; connectData.willFlag = 0; connectData.clientID.cstring = "OneOS_MQTTClient"; - connectData.username.cstring = "username"; - connectData.password.cstring = "password"; + // connectData.username.cstring = "username"; + // connectData.password.cstring = "password"; if ((rc = MQTTConnect(&mqtt_context.client, &connectData)) != 0) { diff --git a/components/onejs/include/app_context.h b/components/onejs/include/app_context.h index 31702eb8c3b43e8957f06a81ba269f2bd21fe2ae..5a7ee102855bc91cd92df50d22a491bd3f851e45 100644 --- a/components/onejs/include/app_context.h +++ b/components/onejs/include/app_context.h @@ -13,11 +13,11 @@ * * @file app_context.h * - * @brief + * @brief app interface implementation * * @revision * Date Author Notes - * 2022-5-20 OneOS team First Version + * 2022-5-20 OneOS team First Version *********************************************************************************************************************** */ diff --git a/components/onejs/include/onejs.h b/components/onejs/include/onejs.h index 4b1fe8b28b3b05273fecce653e77c1176c7d754b..05b0deda5598cc160a6b2a20051e3b190ec6695c 100644 --- a/components/onejs/include/onejs.h +++ b/components/onejs/include/onejs.h @@ -13,11 +13,11 @@ * * @file onejs.h * - * @brief + * @brief onejs init and deinit interface implementation * * @revision * Date Author Notes - * 2022-5-20 OneOS team First Version + * 2022-5-20 OneOS team First Version *********************************************************************************************************************** */ diff --git a/components/onejs/include/utils/hashtable.h b/components/onejs/include/utils/hashtable.h index 4627ada86558255388f69aba7135d82dd5e734d5..f40a35603a0b1b0a0298e17b5a33c487ed793a8f 100644 --- a/components/onejs/include/utils/hashtable.h +++ b/components/onejs/include/utils/hashtable.h @@ -1,3 +1,24 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file hashtable.h + * + * @brief hashtable interface implement. + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version. + ***********************************************************************************************************************/ #ifndef _HASH_TABLE_H_ #define _HASH_TABLE_H_ diff --git a/components/onejs/include/utils/jsbridge.h b/components/onejs/include/utils/jsbridge.h index c2c649bdccca20d222dc656a3b4542ed4eecb7f0..c0b2bf394aba443ac1e92f2050a2181d093819ed 100644 --- a/components/onejs/include/utils/jsbridge.h +++ b/components/onejs/include/utils/jsbridge.h @@ -1,3 +1,24 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file jsbridge.h + * + * @brief jsbridge interface implementation. + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version. + ***********************************************************************************************************************/ #ifndef _ONEJS_JSBRIDGE_H_ #define _ONEJS_JSBRIDGE_H_ diff --git a/components/onejs/include/utils/onejs_assert.h b/components/onejs/include/utils/onejs_assert.h index 6060790b433cb35306317780d45119f45c8b3228..29ff316241c913268a744f150e38e41dff81351a 100644 --- a/components/onejs/include/utils/onejs_assert.h +++ b/components/onejs/include/utils/onejs_assert.h @@ -1,3 +1,24 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file onejs_assert.h + * + * @brief ONEJS_ASSERT macro implementation + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version. + ***********************************************************************************************************************/ #ifndef _ONEJS_ASSERT_H_ #define _ONEJS_ASSERT_H_ diff --git a/components/onejs/include/utils/onejs_error.h b/components/onejs/include/utils/onejs_error.h index eb64c063f85eba7f61f4d7e3a62a46bf92c9af18..10869059bed899b5f1757ce90d11f395bdfb5cc7 100644 --- a/components/onejs/include/utils/onejs_error.h +++ b/components/onejs/include/utils/onejs_error.h @@ -1,3 +1,24 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file onejs_error.h + * + * @brief onejs errno implementation. + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version. + ***********************************************************************************************************************/ #ifndef _ONEJS_ERROR_H_ #define _ONEJS_ERROR_H_ diff --git a/components/onejs/include/utils/onejs_list.h b/components/onejs/include/utils/onejs_list.h index e7068f3ab4c106f9e7c2aa467423cd4810f135b4..044d7cb90b9ef3ba3801e3f52ab874145a9beb6c 100644 --- a/components/onejs/include/utils/onejs_list.h +++ b/components/onejs/include/utils/onejs_list.h @@ -1,6 +1,6 @@ /** *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. * * Licensed under the Apache License, Version 2.0 (the "License"); you may not *use this file except in compliance with the License. You may obtain a copy of @@ -16,11 +16,11 @@ * * @file onejs_list.h * - * @brief Provide double list and single list functions + * @brief double-list and single-list functions implementation * * @revision * Date Author Notes - * 2020-02-13 OneOS Team First version + * 2022-05-20 OneOS Team First version *********************************************************************************************************************** */ diff --git a/components/onejs/include/utils/onejs_log.h b/components/onejs/include/utils/onejs_log.h index 498057d7647d3d6b9395bea370739e23081cfaf0..deb4e20aa42dd304e421422046b13fbccdd1768e 100644 --- a/components/onejs/include/utils/onejs_log.h +++ b/components/onejs/include/utils/onejs_log.h @@ -1,3 +1,29 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + *use this file except in compliance with the License. You may obtain a copy of + *the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + *distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + *WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + *License for the specific language governing permissions and limitations under + *the License. + * + * @file onejs_log.h + * + * @brief onejs log func implementation + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version + *********************************************************************************************************************** + */ + #ifndef _ONEJS_LOG_H_ #define _ONEJS_LOG_H_ diff --git a/components/onejs/include/utils/onejs_tree.h b/components/onejs/include/utils/onejs_tree.h index d64938f205510f2f3bf04ad111184fef825b1414..41212c40296b1f3b973e028b0651203fe28736fd 100644 --- a/components/onejs/include/utils/onejs_tree.h +++ b/components/onejs/include/utils/onejs_tree.h @@ -1,3 +1,28 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + *use this file except in compliance with the License. You may obtain a copy of + *the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + *distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + *WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + *License for the specific language governing permissions and limitations under + *the License. + * + * @file onejs_tree.h + * + * @brief onejs tree interface implementation. + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version + *********************************************************************************************************************** + */ #ifndef _ONEJS_TREE_H_ #define _ONEJS_TREE_H_ diff --git a/components/onejs/include/utils/onejs_util.h b/components/onejs/include/utils/onejs_util.h index 781c3a09030c5db24399213c62a8d2b2c3b1b5b6..ebe3f39d7f623652b4e4473c8d90fa5645f06e80 100644 --- a/components/onejs/include/utils/onejs_util.h +++ b/components/onejs/include/utils/onejs_util.h @@ -1,3 +1,28 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2022, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + *use this file except in compliance with the License. You may obtain a copy of + *the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + *distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + *WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + *License for the specific language governing permissions and limitations under + *the License. + * + * @file onejs_util.h + * + * @brief onejs util func implementation. + * + * @revision + * Date Author Notes + * 2022-05-20 OneOS Team First version + *********************************************************************************************************************** + */ #ifndef _ONEJS_UTIL_H_ #define _ONEJS_UTIL_H_ diff --git a/components/onejs/source/init/init.c b/components/onejs/source/init/init.c index d0d5feb5ef7bd3d01f1ba4697ee99f2aab9a4cc6..b3aa602bea1b5ae124c6ea4b8813a540faa2c490 100644 --- a/components/onejs/source/init/init.c +++ b/components/onejs/source/init/init.c @@ -13,11 +13,11 @@ * * @file init.c * - * @brief This file implements onejs init. + * @brief onejs init implementation. * * @revision * Date Author Notes - * 2022-5-20 OneOS team First Version + * 2022-05-20 OneOS team First Version *********************************************************************************************************************** */ #include @@ -182,8 +182,8 @@ ONEJS_EXPORT_BASE_COMPONENT(switch, &switch_func); #endif //todo -#if !defined(OS_USING_GUI_LVGL_FILESYSTEM) || !defined(OS_LV_FS_MOUNT_SFALSH) || !defined(OS_LV_MOUNT_FS_TYPE_JFFS2) -#error "Onejs depend on lvgl filesystem, must select OS_USING_GUI_LVGL_FILESYSTEM & OS_LV_FS_MOUNT_SFALSH & OS_LV_MOUNT_FS_TYPE_JFFS2" ONEJS_TASK_PRIORITY +#if !defined(OS_USING_GUI_LVGL_FILESYSTEM) || !defined(OS_LV_FS_MOUNT_SFALSH) || !defined(OS_LV_MOUNT_FS_TYPE_FATFS) +#error "Onejs depend on lvgl filesystem, must select OS_USING_GUI_LVGL_FILESYSTEM & OS_LV_FS_MOUNT_SFALSH & OS_LV_MOUNT_FS_TYPE_FATFS" #endif #ifdef OS_USING_ONEJS_AUTO_START diff --git a/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.c b/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.c index e065021c842469dc8a3abae4a69765330ec50240..0210554e22097064798c188b48441a1283f90aaf 100644 --- a/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.c +++ b/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.c @@ -1,3 +1,23 @@ +/* Copyright (c) 2018 authors + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + //#include "../../source/core/onejs-config.h" #include "onejs_util.h" #include "iotjs_def.h" diff --git a/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.h b/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.h index c1495feaf3c4a15bfa3a2302e8cb1fe23d7d1ab7..c974c369931191169c247e1bab2aa0a14e09ca5b 100644 --- a/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.h +++ b/components/onejs/thirdparty/lv_font_conv/onejs_parse_lv_font.h @@ -1,3 +1,23 @@ +/* Copyright (c) 2018 authors + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + #ifndef ONEJS_PARSE_LV_FONT #define ONEJS_PARSE_LV_FONT diff --git a/drivers/camera/driver/cam_hal.c b/drivers/camera/driver/cam_hal.c index eed5fa10609e3f28b0c4432b16284a4e9d19e872..77c1f21119c2563655095bf042fccf480291000f 100644 --- a/drivers/camera/driver/cam_hal.c +++ b/drivers/camera/driver/cam_hal.c @@ -272,6 +272,7 @@ static void cam_task(void *arg) } } +static uint8_t dcmi_line_buf[2][LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE]; static os_err_t cam_dma_config(const camera_config_t *config) { bool ret = ll_cam_dma_sizes(cam_obj); @@ -320,11 +321,8 @@ static os_err_t cam_dma_config(const camera_config_t *config) cam_obj->frames[x].en = 1; } -#if 1 - cam_obj->dma_buffer = - (uint8_t *)os_dma_malloc_align(cam_obj->dma_buffer_size * sizeof(uint8_t), BSP_CACHE_LINE_SIZE); - // cam_obj->dma_buffer = (uint8_t *)os_calloc(1, cam_obj->dma_buffer_size); + cam_obj->dma_buffer = (uint8_t *)&dcmi_line_buf; if (NULL == cam_obj->dma_buffer) { LOG_E(DRV_EXT_TAG, @@ -334,7 +332,7 @@ static os_err_t cam_dma_config(const camera_config_t *config) cam_obj->dma_buffer_size); return OS_FAILURE; } -#endif + return OS_SUCCESS; } @@ -407,7 +405,7 @@ os_err_t cam_config(const camera_config_t *config, framesize_t frame_size, uint1 ret = cam_dcmi_irq_init(); CAM_CHECK_GOTO(ret == OS_SUCCESS, "cam intr alloc failed", err); - cam_obj->task_handle = os_task_create(OS_NULL, OS_NULL, 4092, "cam_task", cam_task, NULL, 3); + cam_obj->task_handle = os_task_create(OS_NULL, OS_NULL, 4096, "cam_task", cam_task, NULL, 3); OS_ASSERT(cam_obj->task_handle); os_task_startup(cam_obj->task_handle); @@ -493,7 +491,7 @@ camera_fb_t *cam_take(uint32_t timeout) } else { - LOG_W(DRV_EXT_TAG, "NO-EOI"); + LOG_W(DRV_EXT_TAG, "NO-EOI,offset_s:%d,offset_e:%d",offset_s,offset_e); cam_give(dma_buffer); return cam_take(timeout - (os_tick_get_value() - start)); // recurse!!!! } diff --git a/drivers/camera/driver/camera.c b/drivers/camera/driver/camera.c index 4611466e4f9bc1fcc6760a72b3b83e881ff4f577..3d4bfba2450868fee46c65fc97d57f3c45582857 100644 --- a/drivers/camera/driver/camera.c +++ b/drivers/camera/driver/camera.c @@ -278,9 +278,15 @@ os_err_t esp_camera_init(const camera_config_t *config) s_state->sensor.set_wpc(&s_state->sensor, true); s_state->sensor.set_lenc(&s_state->sensor, true); s_state->sensor.set_wb_mode(&s_state->sensor, 0); - // s_state->sensor.set_contrast(&s_state->sensor,0); - // s_state->sensor.set_brightness(&s_state->sensor,1); - // s_state->sensor.set_saturation(&s_state->sensor,0); + s_state->sensor.set_hmirror(&s_state->sensor, true); + //s_state->sensor.set_vflip(&s_state->sensor,true); + //s_state->sensor.set_colorbar(&s_state->sensor,true); + } + else if (s_state->sensor.id.PID == OV5640_PID) + { + s_state->sensor.set_hmirror(&s_state->sensor,true); + s_state->sensor.set_vflip(&s_state->sensor,true); + //s_state->sensor.set_colorbar(&s_state->sensor,true); } if (pix_format == PIXFORMAT_JPEG) @@ -327,7 +333,7 @@ camera_fb_t *esp_camera_fb_get(void) } camera_fb_t *fb = cam_take(FB_GET_TIMEOUT); // set the frame properties - if (fb) + if (fb != NULL) { fb->width = resolution[s_state->sensor.status.framesize].width; fb->height = resolution[s_state->sensor.status.framesize].height; diff --git a/drivers/camera/target/private_include/ll_cam.h b/drivers/camera/target/private_include/ll_cam.h index ee746e4dacd4a41637288ba4f95753b00d52401d..083d63d37b24568529d9dd7c8d6d54a4f43255a3 100644 --- a/drivers/camera/target/private_include/ll_cam.h +++ b/drivers/camera/target/private_include/ll_cam.h @@ -35,7 +35,7 @@ goto lab; \ } -#define LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE (0xFFFF*4) +#define LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE (4096)//(0xFFFF*4) typedef enum { CAM_SEM_DMA_BUF0 = 0, diff --git a/drivers/fal/fal_mtd.c b/drivers/fal/fal_mtd.c index 22d810692ea5dcf75581eba222bd99935d4eeb03..b27022bc74690d2e0f1fd533cc0f472e567c4932 100644 --- a/drivers/fal/fal_mtd.c +++ b/drivers/fal/fal_mtd.c @@ -102,7 +102,6 @@ os_mtd_device_t *fal_mtd_device_create(const char *parition_name) { struct fal_mtd_device *fal_mtd_dev; struct fal_part *fal_part = fal_part_find(parition_name); - const struct fal_flash *fal_flash = fal_part->flash; if (!fal_part) { @@ -110,6 +109,8 @@ os_mtd_device_t *fal_mtd_device_create(const char *parition_name) return NULL; } + const struct fal_flash *fal_flash = fal_part->flash; + fal_mtd_dev = (struct fal_mtd_device *)os_calloc(1, sizeof(struct fal_mtd_device)); if (fal_mtd_dev == OS_NULL) { diff --git a/drivers/hal/beken/Kconfig b/drivers/hal/beken/Kconfig index 595909a2e39eaa394fa848371be0088c6614a317..4aac68aa6ad0be2bd8d0a4b9f6d6fee91f713cbc 100644 --- a/drivers/hal/beken/Kconfig +++ b/drivers/hal/beken/Kconfig @@ -1,8 +1,6 @@ -config SOC_FAMILY_BK72XX +config MANUFACTOR_BEKEN bool default n source "$OS_ROOT/drivers/hal/beken/beken72XX_HAL/Kconfig" source "$OS_ROOT/drivers/hal/beken/drivers/Kconfig" - -#comment "Configure base hal in beken" diff --git a/drivers/hal/beken/beken72XX_HAL/Kconfig b/drivers/hal/beken/beken72XX_HAL/Kconfig index af753af0c5bdec4741aedd653700c8cd5b838531..ca8e918c95d19e21bcaede6bc7ceb2d1ba0aaae4 100644 --- a/drivers/hal/beken/beken72XX_HAL/Kconfig +++ b/drivers/hal/beken/beken72XX_HAL/Kconfig @@ -1,6 +1,6 @@ -config SOC_ARM9_BK7231N +config SOC_ARM9E_BK7231N bool select ARCH_ARM_ARM968 - select SOC_FAMILY_BK72XX + select MANUFACTOR_BEKEN default n diff --git a/drivers/hal/beken/beken72XX_HAL/app/app.c b/drivers/hal/beken/beken72XX_HAL/app/app.c index 8835a960e27d5b65b20ed3e184aa7315ce854fd9..12cbc88fcba8f7996d8b31e0a4fc07fa5f28d212 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/app.c +++ b/drivers/hal/beken/beken72XX_HAL/app/app.c @@ -46,6 +46,7 @@ #include "demos_start.h" #endif #include "ap_idle_pub.h" +#include "arbitrate.h" beken_thread_t init_thread_handle; beken_thread_t app_thread_handle; @@ -84,7 +85,7 @@ static void kmsg_bk_thread_main( void *arg ) while(1) { ret = rtos_get_semaphore(&app_sema, BEKEN_WAIT_FOREVER); - ASSERT(kNoErr == ret); + OS_ASSERT(kNoErr == ret); rwnx_recv_msg(); ke_evt_none_core_scheduler(); @@ -97,7 +98,7 @@ static void init_thread_main( void *arg ) bk_wlan_app_init(); os_printf("bk_wlan_app_init finished\r\n"); - + rtos_delete_thread( NULL ); } @@ -240,7 +241,7 @@ void bmsg_tx_raw_handler(BUS_MSG_T *msg) txl_cntrl_push(txdesc_new, queue_idx); exit: - os_free(pkt); + os_free_loose(pkt); } void bmsg_ioctl_handler(BUS_MSG_T *msg) @@ -415,7 +416,7 @@ int bmsg_tx_sender(struct pbuf *p, uint32_t vif_idx) msg.sema = NULL; pbuf_ref(p); - ret = rtos_push_to_queue(&g_wifi_core.io_queue, &msg, 1 * SECONDS); + ret = rtos_push_to_queue(&g_wifi_core.io_queue, &msg, BEKEN_NO_WAIT); if(kNoErr != ret) { @@ -441,7 +442,7 @@ int bmsg_tx_raw_sender(uint8_t *payload, uint16_t length) if(ret != kNoErr) { APP_PRT("bmsg_tx_sender failed\r\n"); - os_free(payload); + os_free_loose(payload); } return ret; @@ -575,7 +576,7 @@ static void core_thread_main( void *arg ) { ret = rtos_pop_from_queue(&g_wifi_core.io_queue, &msg, BEKEN_WAIT_FOREVER); if(kNoErr == ret) - { + { switch(msg.type) { #if CFG_USE_STA_PS @@ -656,6 +657,7 @@ static void core_thread_main( void *arg ) bmsg_ps_handler(&msg); ps_flag = 0; } + power_save_rf_sleep_check(); #endif @@ -742,7 +744,7 @@ extern void h4tl_write_2_host_evt_acl(uint8_t *buf, uint16_t len); #endif #endif void app_pre_start(void) -{ +{ OSStatus ret; ret = rtos_init_semaphore(&app_sema, 1); diff --git a/drivers/hal/beken/beken72XX_HAL/app/ate_app.c b/drivers/hal/beken/beken72XX_HAL/app/ate_app.c index b88e4ebddd5e22d2a0ff4ee241dd9bc0e994de58..a444fb2a4aabefcf3134f1f6d6942286867486bb 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/ate_app.c +++ b/drivers/hal/beken/beken72XX_HAL/app/ate_app.c @@ -68,7 +68,7 @@ static void do_single_wave_test(void) os_memcpy(cmd_buf, CMD_SINGLE_WAVE, cmd_len); bk_test_cmd_handle_input((char *)cmd_buf, cmd_len); - os_free(cmd_buf); + os_free_loose(cmd_buf); } } diff --git a/drivers/hal/beken/beken72XX_HAL/app/config/param_config.c b/drivers/hal/beken/beken72XX_HAL/app/config/param_config.c index 752671c89e3e5322ba484c366f1cda41381e9c68..cd1701293d959cb0788a361621d8b6d0568478d9 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/config/param_config.c +++ b/drivers/hal/beken/beken72XX_HAL/app/config/param_config.c @@ -100,10 +100,13 @@ static void random_mac_address(u8 *mac) void cfg_load_mac(u8 *mac) { #if (WIFI_MAC_POS == MAC_EFUSE) + if(!wifi_get_mac_address_from_efuse((UINT8 *)mac)) #elif (WIFI_MAC_POS == MAC_RF_OTP_FLASH) + if(!manual_cal_get_macaddr_from_flash((UINT8 *)mac)) #elif (WIFI_MAC_POS == MAC_ITEM) + uint8_t tmp_mac[8] = {0}; if(get_info_item(WIFI_MAC_ITEM, (UINT8 *)tmp_mac, NULL, NULL)) { @@ -129,6 +132,8 @@ void wifi_get_mac_address(char *mac, u8 type) { static int mac_inited = 0; + int i = 0; + if (mac_inited == 0) { cfg_load_mac(system_mac); @@ -141,6 +146,7 @@ void wifi_get_mac_address(char *mac, u8 type) u8 mac_low; os_memcpy(mac, system_mac, 6); + mac_low = mac[5]; // if NX_VIRT_DEV_MAX == 4. diff --git a/drivers/hal/beken/beken72XX_HAL/app/ftp/ftpd.c b/drivers/hal/beken/beken72XX_HAL/app/ftp/ftpd.c index 416397ab14e2db82e95c833ec145d93416d0d775..92b97279b94b8ab22128bb1cbeda138a5a4c22d9 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/ftp/ftpd.c +++ b/drivers/hal/beken/beken72XX_HAL/app/ftp/ftpd.c @@ -295,7 +295,7 @@ static int sfifo_init(sfifo_t *f, int size) static void sfifo_close(sfifo_t *f) { if(f->buffer) - os_free(f->buffer); + os_free_loose(f->buffer); } /* @@ -368,7 +368,7 @@ static void ftpd_dataerr(void *arg, err_t err) return; fsd->msgfs->datafs = NULL; fsd->msgfs->state = FTPD_IDLE; - os_free(fsd); + os_free_loose(fsd); } static void ftpd_dataclose(struct tcp_pcb *pcb, struct ftpd_datastate *fsd) @@ -378,7 +378,7 @@ static void ftpd_dataclose(struct tcp_pcb *pcb, struct ftpd_datastate *fsd) tcp_recv(pcb, NULL); fsd->msgfs->datafs = NULL; sfifo_close(&fsd->fifo); - os_free(fsd); + os_free_loose(fsd); tcp_arg(pcb, NULL); tcp_close(pcb); } @@ -801,7 +801,7 @@ static void cmd_pwd(const char *arg, struct tcp_pcb *pcb, struct ftpd_msgstate * if (path) { send_msg(pcb, fsm, msg257PWD, path); - os_free(path); + os_free_loose(path); } } @@ -817,7 +817,7 @@ static void cmd_list_common(const char *arg, struct tcp_pcb *pcb, struct ftpd_ms return; } vfs_dir = vfs_opendir(fsm->vfs, cwd); - os_free(cwd); + os_free_loose(cwd); if (!vfs_dir) { send_msg(pcb, fsm, msg451); @@ -933,7 +933,7 @@ static void cmd_pasv(const char *arg, struct tcp_pcb *pcb, struct ftpd_msgstate fsm->datapcb = tcp_new(); if (!fsm->datapcb) { - os_free(fsm->datafs); + os_free_loose(fsm->datafs); send_msg(pcb, fsm, msg451); return; } @@ -1000,7 +1000,7 @@ static void cmd_abrt(const char *arg, struct tcp_pcb *pcb, struct ftpd_msgstate tcp_arg(fsm->datapcb, NULL); tcp_abort(pcb); sfifo_close(&fsm->datafs->fifo); - os_free(fsm->datafs); + os_free_loose(fsm->datafs); fsm->datafs = NULL; } fsm->state = FTPD_IDLE; @@ -1031,7 +1031,7 @@ static void cmd_rnfr(const char *arg, struct tcp_pcb *pcb, struct ftpd_msgstate return; } if (fsm->renamefrom) - os_free(fsm->renamefrom); + os_free_loose(fsm->renamefrom); fsm->renamefrom = (char *)os_malloc(strlen(arg) + 1); if (fsm->renamefrom == NULL) { @@ -1272,9 +1272,9 @@ static void ftpd_msgerr(void *arg, err_t err) vfs_close(fsm->vfs); fsm->vfs = NULL; if (fsm->renamefrom) - os_free(fsm->renamefrom); + os_free_loose(fsm->renamefrom); fsm->renamefrom = NULL; - os_free(fsm); + os_free_loose(fsm); } static void ftpd_msgclose(struct tcp_pcb *pcb, struct ftpd_msgstate *fsm) @@ -1288,9 +1288,9 @@ static void ftpd_msgclose(struct tcp_pcb *pcb, struct ftpd_msgstate *fsm) vfs_close(fsm->vfs); fsm->vfs = NULL; if (fsm->renamefrom) - os_free(fsm->renamefrom); + os_free_loose(fsm->renamefrom); fsm->renamefrom = NULL; - os_free(fsm); + os_free_loose(fsm); tcp_arg(pcb, NULL); tcp_close(pcb); } @@ -1366,7 +1366,7 @@ static err_t ftpd_msgrecv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t else send_msg(pcb, fsm, msg502); - os_free(text); + os_free_loose(text); } pbuf_free(p); } @@ -1426,7 +1426,7 @@ static err_t ftpd_msgaccept(void *arg, struct tcp_pcb *pcb, err_t err) fsm->vfs = vfs_openfs(); if (!fsm->vfs) { - os_free(fsm); + os_free_loose(fsm); return ERR_CLSD; } diff --git a/drivers/hal/beken/beken72XX_HAL/app/ftp/vfs.c b/drivers/hal/beken/beken72XX_HAL/app/ftp/vfs.c index d4fb20e65cbe91d509e3a38fd43fc499840c6654..3f5035609ea07707ea2fca02bef5cbc407b2e70c 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/ftp/vfs.c +++ b/drivers/hal/beken/beken72XX_HAL/app/ftp/vfs.c @@ -77,7 +77,7 @@ void vfs_close(vfs_t *vfs) /* Close a file */ f_close(vfs); } - os_free(vfs); + os_free_loose(vfs); } int vfs_write (void *buffer, int dummy, int len, vfs_file_t *file) @@ -106,7 +106,7 @@ vfs_file_t *vfs_open(vfs_t *vfs, const char *filename, const char *mode) FRESULT r = f_open(f, filename, flags); if (FR_OK != r) { - os_free(f); + os_free_loose(f); return NULL; } return f; @@ -118,7 +118,7 @@ char *vfs_getcwd(vfs_t *vfs, void *dummy1, int dummy2) FRESULT r = f_getcwd(cwd, 255); if (r != FR_OK) { - os_free(cwd); + os_free_loose(cwd); return NULL; } return cwd; @@ -130,7 +130,7 @@ vfs_dir_t *vfs_opendir(vfs_t *vfs, const char *path) FRESULT r = f_opendir(dir, path); if (FR_OK != r) { - os_free(dir); + os_free_loose(dir); return NULL; } return dir; @@ -138,7 +138,7 @@ vfs_dir_t *vfs_opendir(vfs_t *vfs, const char *path) void vfs_closedir(vfs_dir_t *dir) { - os_free(dir); + os_free_loose(dir); } struct tm dummy; diff --git a/drivers/hal/beken/beken72XX_HAL/app/http/utils_httpc.c b/drivers/hal/beken/beken72XX_HAL/app/http/utils_httpc.c index abcea716f112d9951d44f2975c5469910561eb30..8a5ee31df0762d42e5fd5cfe6715b414e629be5e 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/http/utils_httpc.c +++ b/drivers/hal/beken/beken72XX_HAL/app/http/utils_httpc.c @@ -363,13 +363,13 @@ int httpclient_send_header(httpclient_t *client, const char *url, int method, ht rc = ERROR_HTTP_CONN; } GO_ERR: - os_free(buf); + os_free_loose(buf); GO_ERR_1: - os_free(send_buf); + os_free_loose(send_buf); GO_ERR_2: - os_free(path); + os_free_loose(path); GO_ERR_3: - os_free(host); + os_free_loose(host); return rc;//SUCCESS_RETURN; } @@ -516,8 +516,8 @@ void http_flash_init(void) void http_flash_deinit(void) { - os_free(bk_http_ptr->wr_buf); - os_free(bk_http_ptr->wr_tmp_buf); + os_free_loose(bk_http_ptr->wr_buf); + os_free_loose(bk_http_ptr->wr_tmp_buf); bk_http_ptr->wr_buf = NULL; bk_http_ptr->wr_tmp_buf = NULL; bk_http_ptr->wr_last_len = 0; @@ -721,7 +721,7 @@ int httpclient_retrieve_content(httpclient_t *client, char *data, int len, uint3 } while (readLen); bk_http_ptr->do_data = 0; - os_free(b_data); + os_free_loose(b_data); b_data = NULL; if (client_data->is_chunked) { diff --git a/drivers/hal/beken/beken72XX_HAL/app/tftp/tftpclient.c b/drivers/hal/beken/beken72XX_HAL/app/tftp/tftpclient.c index f35bbe9f7637cb96b47c4930ea43d23e39c0b16f..a0005235400b0c1d8dfd3c98a3c11d43ebfdbaf9 100644 --- a/drivers/hal/beken/beken72XX_HAL/app/tftp/tftpclient.c +++ b/drivers/hal/beken/beken72XX_HAL/app/tftp/tftpclient.c @@ -146,7 +146,7 @@ void Tftp_Uninit(void) if(tftp_buf) { - os_free(tftp_buf); + os_free_loose(tftp_buf); tftp_buf = NULL; } @@ -428,7 +428,7 @@ exit: close( udp_tftp_listen_fd ); if(tftp_buf) - os_free(tftp_buf); + os_free_loose(tftp_buf); flash_protection_op(FLASH_XTX_16M_SR_WRITE_ENABLE, FLASH_UNPROTECT_LAST_BLOCK); rtos_delete_thread(&tftp_thread_handle); @@ -525,7 +525,7 @@ void store_block (unsigned block, uint8_t *src, unsigned len) { TFTP_PRT ("block%d flash write err\n", block); } - os_free(f_data); + os_free_loose(f_data); } else { diff --git a/drivers/hal/beken/beken72XX_HAL/common/doubly_list.h b/drivers/hal/beken/beken72XX_HAL/common/doubly_list.h index d34ddcba101bb7a02d3c4cc7344d20166659a5e6..0cfb43689235559075a8e9059509138268285d15 100644 --- a/drivers/hal/beken/beken72XX_HAL/common/doubly_list.h +++ b/drivers/hal/beken/beken72XX_HAL/common/doubly_list.h @@ -1,6 +1,8 @@ #ifndef _DOUBLY_LIST_H #define _DOUBLY_LIST_H +#include "compiler.h" + #ifndef offsetof #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) #endif diff --git a/drivers/hal/beken/beken72XX_HAL/common/fifo.h b/drivers/hal/beken/beken72XX_HAL/common/fifo.h index f7da22e0b4f24ab6a125a171f771e77ecbbef406..7f362b4fe6bbd1f3859e735861ebd8feb8397f62 100644 --- a/drivers/hal/beken/beken72XX_HAL/common/fifo.h +++ b/drivers/hal/beken/beken72XX_HAL/common/fifo.h @@ -67,7 +67,7 @@ __INLINE struct kfifo *kfifo_alloc(unsigned int size) ret = kfifo_init(buffer, size); if (!(ret)) - os_free(buffer); + os_free_loose(buffer); return ret; } @@ -78,10 +78,10 @@ __INLINE struct kfifo *kfifo_alloc(unsigned int size) */ __INLINE void kfifo_free(struct kfifo *fifo) { - os_free(fifo->buffer); + os_free_loose(fifo->buffer); fifo->buffer = 0; - os_free(fifo); + os_free_loose(fifo); } /** diff --git a/drivers/hal/beken/beken72XX_HAL/common/generic.h b/drivers/hal/beken/beken72XX_HAL/common/generic.h index 8f9210ea3d7e897175a9f4d60e66971fd63ecec9..6680d2eaea79c2e211a1e24549e3fa5a7d54f4d8 100644 --- a/drivers/hal/beken/beken72XX_HAL/common/generic.h +++ b/drivers/hal/beken/beken72XX_HAL/common/generic.h @@ -7,10 +7,21 @@ typedef void (*FUNCPTR)(void); typedef void (*FUNC_1PARAM_PTR)(void *ctxt); typedef void (*FUNC_2PARAM_PTR)(void *arg, uint8_t vif_idx); +#ifndef MAX #define MAX(x, y) (((x) > (y)) ? (x) : (y)) +#endif + +#ifndef MIN #define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +#ifndef max #define max(x, y) (((x) > (y)) ? (x) : (y)) +#endif + +#ifndef min #define min(x, y) (((x) < (y)) ? (x) : (y)) +#endif extern void bk_printf(const char *fmt, ...); #define as_printf (bk_printf("%s:%d\r\n",__FUNCTION__,__LINE__)) diff --git a/drivers/hal/beken/beken72XX_HAL/demo/ieee802_11_demo.c b/drivers/hal/beken/beken72XX_HAL/demo/ieee802_11_demo.c index 8acf85866ed39be3349fabfd36ed33cc255bb43d..66fa623b534a6558f6778f356621a6552986d3b9 100644 --- a/drivers/hal/beken/beken72XX_HAL/demo/ieee802_11_demo.c +++ b/drivers/hal/beken/beken72XX_HAL/demo/ieee802_11_demo.c @@ -71,7 +71,7 @@ static void scan_cb(void *ctxt, uint8_t param) bk_printf("Get ap end.......\r\n\r\n"); if (apList.ApList != NULL) { - os_free(apList.ApList); + os_free_loose(apList.ApList); apList.ApList = NULL; } @@ -112,7 +112,7 @@ static void scan_cb(void *ctxt, uint8_t param) apList.ApList[i].ssid, MAC2STR(apList.ApList[i].bssid), apList.ApList[i].ApPower, crypto_str[apList.ApList[i].security], apList.ApList[i].channel); - os_free(apList.ApList); + os_free_loose(apList.ApList); } #endif /* CFG_NEW_SUPP */ } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/Kconfig b/drivers/hal/beken/beken72XX_HAL/driver/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..1ce50caf43f4e47bd9181e540c881771bf006aa1 --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/driver/Kconfig @@ -0,0 +1 @@ +#source "$OS_ROOT/drivers/hal/beken/drivers/*/Kconfig" diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble/weave.yaml deleted file mode 100644 index e6342524eec2892828f8bb878c5d59db2770d97f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble/weave.yaml +++ /dev/null @@ -1,247 +0,0 @@ -# 组名 -group_name: beken_ble - -# 依赖宏控 -depend_macro: - - BUILD_LIB - -# 编译连接信息 -build_option: - cpppath: - - . ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - config ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/gernel_api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/mesh_model/ali ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/arch ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/ble_icu ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/ir ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/reg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/sys_ctrl ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/uart ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/comm/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/prf/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/sdp/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/src/dbg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/src/models/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - cppdefines: - - WIFI_BLE_COEXIST - libs: - - ble - - _7231n ? {is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _7231u ? {is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _7221u ? {is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _ps ? {is_define('CFG_USE_BLE_PS', 1)} - libpath: - - . - libname: - - libble.a - - lib_7231n.a ? {is_define('CFG_SOC_NAME', SOC_BK7231N)} - - lib_7231u.a ? {is_define('CFG_SOC_NAME', SOC_BK7231U)} - - lib_7221u.a ? {is_define('CFG_SOC_NAME', SOC_BK7221U)} - - lib_unknown.a ? {not is_define('CFG_SOC_NAME', SOC_BK7221U)} - - lib_unknown.a ? {not is_define('CFG_SOC_NAME', SOC_BK7231U)} - - lib_unknown.a ? {not is_define('CFG_SOC_NAME', SOC_BK7231N)} - - lib_ps.a ? {is_define('CFG_USE_BLE_PS', 1)} - -# 源码 -source_file: - - beken_ble_sdk/controller/src/ea/ea.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/em/em_buf.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc_ch_asses.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc_hci.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc_llcp.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llc/llc_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld_evt.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld_pdu.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld_sleep.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/lld/lld_wlcoex.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llm/llm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llm/llm_hci.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llm/llm_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/src/llm/llm_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/ahi/ahi.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/ahi/ahi_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/h4tl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/hci.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/hci_fc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/hci_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/hci_tl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/hci_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/attc/attc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/attm/attm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/attm/attm_db.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/atts/atts.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapc/gapc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapc/gapc_hci.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapc/gapc_sig.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapc/gapc_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapm/gapm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapm/gapm_hci.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapm/gapm_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gapm/gapm_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gattc/gattc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gattc/gattc_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gattm/gattm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/gattm/gattm_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cc/l2cc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cc/l2cc_lecb.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cc/l2cc_pdu.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cc/l2cc_sig.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cc/l2cc_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/l2cm/l2cm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/smpc/smpc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/smpc/smpc_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/smpc/smpc_crypto.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/smpc/smpc_util.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/src/smpm/smpm_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/co/rwble.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/co/rwble_hl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/co/rwip.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/common/common_list.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/common/common_utils.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ecc_p256/ecc_p256.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_event.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_mem.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_queue.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/ke/kernel_timer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/src/nvds/nvds.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - ble.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/src/app_ble.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/src/app_comm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/src/app_sdp.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/src/app_sec.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/src/app_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/ble_icu/ble_icu.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/uart/ble_uart.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/arch/ble_arch_main.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/common/RomCallFlash.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/dbg/dbg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/dbg/dbg_mwsgen.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/dbg/dbg_swdiag.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/dbg/dbg_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/rf/src/ble_rf_xvr.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/comm/src/comm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/comm/src/comm_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/prf/src/prf.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/prf/src/prf_utils.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/sdp/src/sdp_service.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/sdp/src/sdp_service_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/src/aes/aes.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_ccm.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_cmac.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_k1.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_k2.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_k3.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_k4.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/aes/aes_s1.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/bcn/m_bcn.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/bearer/m_bearer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/bearer/m_bearer_adv.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/bearer/m_bearer_gatt.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh_log.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh_tb.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh_tb_buf.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh_tb_sec.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/common/mesh_tb_timer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_bcn.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_buf.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_data.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_friend.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_key.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_lay.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_lpn.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_mio.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_prov.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_sec.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_state.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_store.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/dbg/m_dbg_timer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/fnd/m_fnd.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/fnd/m_fnd_confc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/fnd/m_fnd_confs.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/fnd/m_fnd_hlths.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_access.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_friend.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_hb.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_lpn.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_ltrans.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_net.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_proxy.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lay/m_lay_utrans.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/lld/lld_adv_test.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_adv.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_con.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_con.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_sec.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_task.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mal/mal_timer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/mesh_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/mesh_api_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/mesh_param_int.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/mm_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/mm_api_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/m_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/mesh_api/m_api_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/prov/m_prov.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/prov/m_prov_adv_trans.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/prov/m_prov_bearer.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_friend.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_key.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_lpn.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_mio.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_state.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/tb/m_tb_store_nvds.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/common/mm_route.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/common/mm_tb.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/common/mm_tb_bind.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/common/mm_tb_replay.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/common/mm_tb_state.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_bat.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_dtt.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_loc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_lvl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_oo.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_plvl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_poo.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/gens/mm_gens_prop.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lightc/mm_lightc.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lightc/mm_lightc_ctl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lightc/mm_lightc_hsl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lightc/mm_lightc_ln.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lightc/mm_lightc_xyl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lights/mm_lights.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lights/mm_lights_ctl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lights/mm_lights_hsl.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/lights/mm_lights_ln.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/Scenes/m_fnd_Scenes.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/transition_time/m_fnd_generic_transition_time.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - beken_ble_sdk/mesh/src/models/vendor/mm_vendors.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - modules/app/src/app_mesh.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - modules/app/src/app_mm_msg.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - modules/gernel_api/mesh_general_api.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - - modules/mesh_model/ali/app_light_ali_server.c ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2)) and (is_define('CFG_SUPPORT_BLE_MESH', 1))} - \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble_lib/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble_lib/weave.yaml deleted file mode 100644 index 6b079a0c1506802d7deab1f403e8f9fec1a9d45f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/ble/beken_ble_lib/weave.yaml +++ /dev/null @@ -1,49 +0,0 @@ -# 组名 -group_name: beken_usb_lib - -# 依赖宏控 -depend_macro: - - SOC_FAMILY_BK72XX - -# 编译连接信息 -build_option: - cpppath: - - . ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/controller/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/hci/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/host/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/sys/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - config ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/app/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/gernel_api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - modules/mesh_model/ali ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/arch ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/ble_icu ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/ir ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/reg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/sys_ctrl ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/driver/uart ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - plactform/modules/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/comm/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/prf/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - profiles/sdp/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/src/dbg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble_sdk/mesh/src/models/include ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - cppdefines: - - WIFI_BLE_COEXIST - libs: - - ble - - _7231n ? {is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _7231u ? {is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _7221u ? {is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _ps ? {is_define('CFG_USE_BLE_PS', 1)} - libpath: - - . - - - \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble/libble_7231n.a b/drivers/hal/beken/beken72XX_HAL/driver/ble/libble_7231n.aaaa similarity index 100% rename from drivers/hal/beken/beken72XX_HAL/driver/ble/libble_7231n.a rename to drivers/hal/beken/beken72XX_HAL/driver/ble/libble_7231n.aaaa diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/ble/weave.yaml deleted file mode 100644 index 808af54f71465ffaddb92f4c664dd97339fcf3d9..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/ble/weave.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# 子目录 -add_subdirectory: - - beken_ble_lib ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} - - beken_ble ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_4_2))} \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/beken_ble_pub/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/beken_ble_pub/weave.yaml deleted file mode 100644 index 19d87d352856fbaf15ad2fe2f60a8a136bea109a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/beken_ble_pub/weave.yaml +++ /dev/null @@ -1,72 +0,0 @@ -# 组名 -group_name: beken_ble_pub - -# 依赖宏控 -depend_macro: - - SOC_FAMILY_BK72XX - -# 编译连接信息 -build_option: - cpppath: - - . - - ble_lib/ip/ble/hl/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/inc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gap/gapc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gap/gapm ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt/attc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt/attm ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt/atts ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt/gattc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/gatt/gattm ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/l2c/l2cc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/hl/src/l2c/l2cm ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/ll/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/ll/import/reg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/ll/src ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/ll/src/llc ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - cwd + '/ble_lib/ip/ble/ll/src/lld ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/ble/ll/src/llm ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/em/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/hci/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/hci/src ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/sch/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/ip/sch/import ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/aes/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/aes/src ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/common/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/dbg/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/dbg/src ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/ecc_p256/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/h4tl/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/ke/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_lib/modules/ke/src ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_pub/prf ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/rwip/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/rwip/import/reg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/nvds/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/config ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/driver/reg ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/driver/rf ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/driver/uart ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - platform/7231n/entry ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - arch/armv5 ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - arch/armv5/ll ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - arch/armv5/compiler ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_pub/profiles/comm/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_pub/app/api ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - - ble_pub/ui ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', CFG_BLE_VERSION))} - libs: - - ble - - libble - - _7231n ? {is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _7231u ? {is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _7221u ? {is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7221U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231U)} - - _unknown ? {not is_define('CFG_SOC_NAME', SOC_BK7231N)} - - _ps ? {is_define('CFG_SOC_NAME', 1)} - libpath: - - . - -# 'SOC_FAMILY_BK72XX' compile BK72XX soc only \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/weave.yaml deleted file mode 100644 index dfb4ebb904882f8f22c8f7d9ffd3c16e06040943..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/ble_5_x_rw/weave.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# 子目录 -add_subdirectory: - - beken_ble_pub ? {(is_define('CFG_SUPPORT_BLE', 1)) and (is_define('CFG_BLE_VERSION', BLE_VERSION_5_x))} \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/driver.c b/drivers/hal/beken/beken72XX_HAL/driver/driver.c index 0ae16f5c9e66b54184ea162a0123069203376d3b..e180835581c2552b8c4bcb31467c96d0eef5ff76 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/driver.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/driver.c @@ -1,12 +1,29 @@ +/** +**************************************************************************************** +* +* @file driver.c +* +* @brief driver modules initialization +* +* Copyright (C) Beken Leonardo 2021 +* +* $Rev: $ +* +**************************************************************************************** +*/ + #include "include.h" #include "driver_pub.h" #include "dd_pub.h" #include "drv_model_pub.h" -UINT32 driver_init(void) +UINT32 soc_driver_init(void) { drv_model_init(); + g_dd_init(); + + intc_init(); return 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/entry/arch.h b/drivers/hal/beken/beken72XX_HAL/driver/entry/arch.h index 359947d1241cd5ad4988a376f19138b1a34f0e18..a3b74b4777f28717839b739f510bc29a6f7976d9 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/entry/arch.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/entry/arch.h @@ -40,9 +40,9 @@ #include "co_int.h" #include "compiler.h" #include "portmacro.h" +#include "drv_wlan.h" #if (CFG_SUPPORT_RTT) -#include #include #endif @@ -54,20 +54,49 @@ #define GLOBAL_INT_STOP portDISABLE_INTERRUPTS #endif + #if (CFG_SUPPORT_RTT) -#define GLOBAL_INT_DECLARATION() os_base_t irq_level -#define GLOBAL_INT_DISABLE() do{\ - irq_level = os_hw_interrupt_disable();\ - }while(0) +extern os_task_id g_os_current_task; +extern os_mutex_id bk_mutex_dynamic; + +extern void bk_mutex_init(void); + +extern void bk_mutex_lock(void); + +extern void bk_mutex_unlock(void); + +#define GLOBAL_INT_DECLARATION() os_base_t bk_irq_level = -1;os_err_t lock_ret = OS_SUCCESS; bk_mutex_init() + +#ifdef BSP_USE_RECURSIVE +#define GLOBAL_INT_DISABLE() if (OS_TRUE == os_is_irq_active()) \ + { \ + bk_irq_level = os_irq_lock(); \ + } \ + else \ + { \ + bk_irq_level = -1; \ + lock_ret = os_mutex_recursive_lock(bk_mutex_dynamic, OS_NO_WAIT);\ + } + +#define GLOBAL_INT_RESTORE() if (bk_irq_level != -1) \ + { \ + os_irq_unlock(bk_irq_level); \ + } \ + else \ + { \ + if (lock_ret == OS_SUCCESS) \ + os_mutex_recursive_unlock(bk_mutex_dynamic);\ + } -#define GLOBAL_INT_RESTORE() do{ \ - os_hw_interrupt_enable(irq_level);\ - }while(0) +#else +#define GLOBAL_INT_DISABLE() +#define GLOBAL_INT_RESTORE() +#endif #else #define GLOBAL_INT_DECLARATION() uint32_t fiq_tmp, irq_tmp -#define GLOBAL_INT_DISABLE() do{\ +#define GLOBAL_INT_DISABLE() do{ \ fiq_tmp = portDISABLE_FIQ();\ irq_tmp = portDISABLE_IRQ();\ }while(0) diff --git a/drivers/hal/beken/beken72XX_HAL/driver/entry/arch_main.c b/drivers/hal/beken/beken72XX_HAL/driver/entry/arch_main.c index b9942428b62e50ad8a3c5c2b39d5f29a3f0d7b14..adea559e6781353b6ef5ab048c38e13848e3f902 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/entry/arch_main.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/entry/arch_main.c @@ -14,6 +14,8 @@ #include "func_pub.h" #include "app.h" #include "ate_app.h" +#include "error.h" + beken_semaphore_t extended_app_sema = NULL; uint32_t extended_app_stack_size = 2048; @@ -41,7 +43,7 @@ void extended_app_waiting_for_launch(void) static void extended_app_task_handler(void *arg) { /* step 0: function layer initialization*/ - func_init_extended(); + func_init_extended(); /* step 1: startup application layer*/ if(get_ate_mode_state()) diff --git a/drivers/hal/beken/beken72XX_HAL/driver/include/driver_pub.h b/drivers/hal/beken/beken72XX_HAL/driver/include/driver_pub.h index 3c6368f38427ff9020a2cea128be958673ebc07e..e5d03e621af2b4c0930426a27f73a440163fdb8a 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/include/driver_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/include/driver_pub.h @@ -1,6 +1,8 @@ #ifndef _DRIVER_PUB_H_ #define _DRIVER_PUB_H_ +#include "typedef.h" + extern UINT32 driver_init(void); #endif // _DRIVER_PUB_H_ diff --git a/drivers/hal/beken/beken72XX_HAL/driver/include/uart_pub.h b/drivers/hal/beken/beken72XX_HAL/driver/include/uart_pub.h index 7ddfa3c08cd7a91aa2008fce6b4e2e7ada261384..de075a879e8ad075466f5b82e6b0335da1dc118b 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/include/uart_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/include/uart_pub.h @@ -99,13 +99,14 @@ typedef enum typedef struct { - UINT32 baud_rate; + uint32_t baud_rate; uart_data_width_t data_width; uart_parity_t parity; uart_stop_bits_t stop_bits; uart_flow_control_t flow_control; - UINT8 flags; /**< if set, UART can wake up MCU from stop mode, reference: @ref UART_WAKEUP_DISABLE and @ref UART_WAKEUP_ENABLE*/ -} bk_uart_config_t; + uint8_t flags; /**< if set, UART can wake up MCU from stop mode, reference: @ref UART_WAKEUP_DISABLE and @ref UART_WAKEUP_ENABLE*/ +} uart_config_t; + extern int uart_print_port; diff --git a/drivers/hal/beken/beken72XX_HAL/driver/irda/irda.c b/drivers/hal/beken/beken72XX_HAL/driver/irda/irda.c index 37c38301999f6b69bbda07c9e81924ce909e8645..a655e847d7686209e472a63c88aa4bba10c2d3f5 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/irda/irda.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/irda/irda.c @@ -240,7 +240,7 @@ void Irda_init_app(void) UINT32 param; IR_key.valid_flag = 0; - IR_key.IRkey_mq = rt_mq_create("ir_mq",4,3,OS_IPC_FLAG_FIFO); + IR_key.IRkey_mq = rt_mq_create("ir_mq",4,3,0); if(NULL == IR_key.IRkey_mq) { rt_kprintf("create ir mq error!!\r\n"); diff --git a/drivers/hal/beken/beken72XX_HAL/driver/qspi/qspi.c b/drivers/hal/beken/beken72XX_HAL/driver/qspi/qspi.c index caf0ffd74dba6d43044edfd4536c51137a43415a..2254b0d5d5ecbe4558ffd14c1c293aa21022188c 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/qspi/qspi.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/qspi/qspi.c @@ -657,7 +657,7 @@ void bk_qspi_psram_quad_mode_switch(unsigned char ucEnterOrExit) QSPI_DEBUG_PRINTF("sgucPsramSetLength = 0x%x\r\n", sgucPsramSetLength); QSPI_DEBUG_PRINTF("sgucPsramSetLineMode = 0x%x\r\n", sgucPsramSetLineMode); - os_free(p_QSPI_GE0_drv_desc); + os_free_loose(p_QSPI_GE0_drv_desc); } void bk_qspi_psram_reset_enable(void) @@ -701,7 +701,7 @@ void bk_qspi_psram_reset_enable(void) QSPI_DEBUG_PRINTF("sgucPsramSetLength = 0x%x\r\n", sgucPsramSetLength); QSPI_DEBUG_PRINTF("sgucPsramSetLineMode = 0x%x\r\n", sgucPsramSetLineMode); - os_free(p_QSPI_GE0_drv_desc); + os_free_loose(p_QSPI_GE0_drv_desc); } @@ -744,7 +744,7 @@ void bk_qspi_psram_reset(void) QSPI_DEBUG_PRINTF("sgucPsramSetLength = 0x%x\r\n", sgucPsramSetLength); QSPI_DEBUG_PRINTF("sgucPsramSetLineMode = 0x%x\r\n", sgucPsramSetLineMode); - os_free(p_QSPI_GE0_drv_desc); + os_free_loose(p_QSPI_GE0_drv_desc); QSPI_WPRT("psram: reset ok\r\n"); param = (FIQ_PSRAM_BIT); @@ -789,7 +789,7 @@ void bk_qspi_psram_set_length(void) QSPI_DEBUG_PRINTF("sgucPsramSetLength = 0x%x\r\n", sgucPsramSetLength); QSPI_DEBUG_PRINTF("sgucPsramSetLineMode = 0x%x\r\n", sgucPsramSetLineMode); - os_free(p_QSPI_GE0_drv_desc); + os_free_loose(p_QSPI_GE0_drv_desc); } static UINT8 qspi_ge0_busy(void) @@ -1067,6 +1067,7 @@ void qspi_isr(void) //debug:close int reg = (FIQ_PSRAM_BIT); + os_kprintf("close iqr!!!!!!!!!!!!!!!!------ %s, %d\r\n",__FUNCTION__,__LINE__); sddev_control(ICU_DEV_NAME, CMD_ICU_INT_DISABLE, ®); } // else diff --git a/drivers/hal/beken/beken72XX_HAL/driver/sdcard/sdcard.c b/drivers/hal/beken/beken72XX_HAL/driver/sdcard/sdcard.c index 60afe6bb1307336d6d8dacac7b6288d82e010f4c..39840116c9db2de7b56386352cc0c28941d5ec0b 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/sdcard/sdcard.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/sdcard/sdcard.c @@ -289,7 +289,7 @@ static SDIO_Error sdcard_mmc_cmd8_process(void) } freebuf: - os_free(tmpptr); + os_free_loose(tmpptr); return cmd.err; } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.c b/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.c index 7463a704c8d5df34b92fb71b4ed84bf39654ddb2..c13955bfbb414da4f8c68e74ef10c8a220895abf 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.c @@ -95,7 +95,7 @@ void sdio_free_valid_node(SDIO_NODE_PTR node_ptr) //os_memset(node_ptr->addr, MALLOC_MAGIC_BYTE1, node_ptr->length + MALLOC_MAGIC_LEN - 1); } - os_free(node_ptr->orig_addr); + os_free_loose(node_ptr->orig_addr); node_ptr->addr = 0; node_ptr->length = 0; node_ptr->orig_addr = 0; diff --git a/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.h b/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.h index 80df2d8d7964a871953bdb35bd5c1cc1e80061c8..306a0bf6a54ce19a6937542662dfeab1756464a9 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/sdio/sdio.h @@ -3,6 +3,8 @@ #include "doubly_list.h" #include "rwnx_config.h" +#include "sdio_pub.h" +#include "generic.h" #define SDIO_DEBUG diff --git a/drivers/hal/beken/beken72XX_HAL/driver/security/hal_sha.c b/drivers/hal/beken/beken72XX_HAL/driver/security/hal_sha.c index 31f1f70dcc42e6633eae68388e58a054da6e9f3e..332689f20bf5df20c17b138b374ea835daaf85cf 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/security/hal_sha.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/security/hal_sha.c @@ -151,7 +151,7 @@ void hal_sha_finish( void *ct, unsigned char output[32] ) bk_sha256_finish(ctx, output); os_memset(ctx, 0, sizeof(hal_sha_context)); - os_free(ctx); + os_free_loose(ctx); ctx = NULL; } @@ -285,7 +285,7 @@ int hal_sha256_self_test( int verbose ) os_printf( "\n" ); exit: - os_free( buf ); + os_free_loose( buf ); return( ret ); } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi.h b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi.h index d9f737b4d709d4a37575051785c7cc37f4ebc2f6..a297d22e6becad8f806a035c3a7c3148b1bd1626 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi.h @@ -58,5 +58,5 @@ /******************************************************************************* * Function Declarations *******************************************************************************/ -UINT32 spi_ctrl(UINT32 cmd, void *param); +unsigned int spi_ctrl(unsigned int cmd, void *param); #endif //_SPI_H_ diff --git a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_flash.c b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_flash.c index 665fdfbbc17295a0b20c12920f7add2e4f77d5ee..e679cbcf372c80f3a1b1472ccfe4c496d6ca3242 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_flash.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_flash.c @@ -284,7 +284,7 @@ static int spi_flash_program_page(UINT32 addr, UINT32 size, UINT8 *src) bk_spi_master_xfer(&msg); - os_free(ucmd); + os_free_loose(ucmd); return 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_master.c b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_master.c index 7f0e0bdad4b971498f33d6e648350addd1bf10bc..74d27e2a72f871236739df52caa9426a25efce86 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_master.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_master.c @@ -368,7 +368,7 @@ _exit: if (spi_dev) { - os_free(spi_dev); + os_free_loose(spi_dev); spi_dev = NULL; } @@ -396,7 +396,7 @@ int bk_spi_master_deinit(void) if (spi_dev) { - os_free(spi_dev); + os_free_loose(spi_dev); spi_dev = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_psram.c b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_psram.c index 26c8e195aac60066836c7f3437dca593624f12eb..fdc5bb5932c7aed775c49d1f766506210d0fd4c3 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_psram.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_psram.c @@ -169,7 +169,7 @@ uint32_t spi_psram_write(uint32_t addr, uint8_t* buffer, uint32_t size) bk_spi_master_xfer(&msg); - os_free(ucmd); + os_free_loose(ucmd); return 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_slave.c b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_slave.c index e428fabe06abfeebfb449e495ea79bc2d6a995cf..2168814bfcc41403737a752f77622c85be326c47 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_slave.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/spi/spi_slave.c @@ -348,6 +348,7 @@ int bk_spi_slave_xfer(struct spi_message *msg) len = bk_spi_slave_get_rx_data(recv_ptr, recv_len); if(len == 0) { + os_kprintf("%s, %d\r\n", __FUNCTION__, __LINE__); err = rtos_get_semaphore(&spi_slave_dev->rx_sem, BEKEN_WAIT_FOREVER); if(err != kNoErr) break; @@ -446,11 +447,11 @@ _exit: rtos_deinit_semaphore(&spi_slave_dev->rx_sem); if(spi_slave_dev->rx_fifo) - os_free(spi_slave_dev->rx_fifo); + os_free_loose(spi_slave_dev->rx_fifo); if (spi_slave_dev) { - os_free(spi_slave_dev); + os_free_loose(spi_slave_dev); spi_slave_dev = NULL; } @@ -477,7 +478,7 @@ int bk_spi_slave_deinit(void) rtos_deinit_semaphore(&spi_slave_dev->rx_sem); if(spi_slave_dev->rx_fifo) - os_free(spi_slave_dev->rx_fifo); + os_free_loose(spi_slave_dev->rx_fifo); if(spi_slave_dev->mutex) { @@ -485,7 +486,7 @@ int bk_spi_slave_deinit(void) rtos_deinit_mutex(&spi_slave_dev->mutex); } - os_free(spi_slave_dev); + os_free_loose(spi_slave_dev); spi_slave_dev = NULL; return 0; diff --git a/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.c b/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.c index ddc974db863fa1eeb44b991554a4899144dfeb14..aefed4dccadf263fcc9cbd24828449e86b727d33 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.c +++ b/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.c @@ -18,7 +18,6 @@ #if (CFG_SUPPORT_RTT) #include -#include #endif #if CFG_ENABLE_DEMO_TEST @@ -247,7 +246,7 @@ void uart_hw_init(UINT8 uport) return; } -void uart_hw_set_change(UINT8 uport, bk_uart_config_t *uart_config) +void uart_hw_set_change(UINT8 uport, uart_config_t *uart_config) { UINT32 reg, baud_div, width; uart_parity_t parity_en; diff --git a/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.h b/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.h index ba5ee922a6e7a9f2b6fc4edd8177c6ee97b35ab2..7ae37b30aea381c710e32d1c22d7ee6f13046d2d 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/uart/uart.h @@ -308,6 +308,6 @@ int uart_tx_fifo_needwr_callback_set(int uport, uart_callback callback, void *pa int uart_tx_end_callback_set(int uport, uart_callback callback, void *param); void uart_set_tx_stop_end_int(UINT8 uport, UINT8 set); void uart_set_tx_fifo_needwr_int(UINT8 uport, UINT8 set); -void uart_hw_set_change(UINT8 uport, bk_uart_config_t *uart_config); +void uart_hw_set_change(UINT8 uport, uart_config_t *uart_config); #endif // _UART_H_ diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/SConscript b/drivers/hal/beken/beken72XX_HAL/driver/usb/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..5049b1e2e1138df2c4632fb22d4f893725f368aa --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/driver/usb/SConscript @@ -0,0 +1,85 @@ +from build_tools import * +Import('OS_ROOT') +Import('BEKEN_CFG') + +cwd = PresentDir() + +src = [] +src += ["src/cd/mu_cntlr.c"] +src += ["src/cd/mu_descs.c"] +src += ["src/cd/mu_drc.c"] +src += ["src/cd/mu_fc.c"] +src += ["src/cd/mu_fdr.c"] +src += ["src/cd/mu_fun.c"] +src += ["src/cd/mu_funex.c"] +src += ["src/cd/mu_hc.c"] +src += ["src/cd/mu_hdr.c"] +src += ["src/cd/mu_hsdma.c"] +src += ["src/cd/mu_hst.c"] +src += ["src/cd/mu_list.c"] +src += ["src/cd/mu_mdr.c"] +src += ["src/cd/mu_pip.c"] + +src += ["src/drivers/comm/mu_comif.c"] +src += ["src/drivers/hid/mu_hidif.c"] +src += ["src/drivers/hid/mu_hidkb.c"] +src += ["src/drivers/hid/mu_hidmb.c"] +src += ["src/drivers/msd/mu_mapi.c"] +src += ["src/drivers/msd/mu_mbot.c"] +src += ["src/drivers/msd/mu_mscsi.c"] + +src += ["src/examples/msd/mu_msdfn.c"] + +src += ["src/hid/usb_hid.c"] + +src += ["src/lib/mu_bits.c"] +src += ["src/lib/mu_stack.c"] +src += ["src/lib/mu_stdio.c"] +src += ["src/lib/mu_strng.c"] +src += ["src/msc/usb_msd.c"] +src += ["src/systems/none/afs/board.c"] +src += ["src/systems/none/plat_uds.c"] +src += ["src/uvc/usb_uvc.c"] +src += ["src/uvc/uvc_driver.c"] + +path = [] +path += [cwd + '/'] +path += [cwd + '/include'] +path += [cwd + '/include/class'] +path += [cwd + '/src/cd'] +path += [cwd + '/src/drivers'] +path += [cwd + '/src/drivers/comm'] +path += [cwd + '/src/drivers/hid'] +path += [cwd + '/src/drivers/msd'] +path += [cwd + '/src/examples/msd'] +path += [cwd + '/src/hid'] +path += [cwd + '/src/lib'] +path += [cwd + '/src/msc'] +path += [cwd + '/src/systems/none/afs'] +path += [cwd + '/src/systems/none'] +path += [cwd + '/src/uvc'] + + +#sys_config = os.path.join(cwd, '..', '..', '..', 'config', 'sys_config.h') +sys_config = BEKEN_CFG +options = LocalOptions(sys_config) + +usb_lib_name = 'usb' + +libs = [usb_lib_name] +libpath = [cwd + '/'] + +""" +'SOC_FAMILY_BK72XX' compile BK72XX soc only +""" + +if (IsLocalDefined(options, 'CFG_SOC_NAME') == 'SOC_BK7231N') or (IsLocalDefined(options, 'CFG_USB') == 0): + group = [] +else: + group_use_lib = AddCodeGroup('beken_usb_lib', [], depend = ['SOC_FAMILY_BK72XX'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + + group_build_lib = AddCodeGroup('beken_usb', src, depend = ['BUILD_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath, LIBNAME = 'lib' + usb_lib_name + '.a') + + group = group_use_lib + group_build_lib + +Return('group') diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb/weave.yaml deleted file mode 100644 index d2d9495ed118e5936694e0292daadc44bcd3a9fc..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb/weave.yaml +++ /dev/null @@ -1,66 +0,0 @@ -# 组名 -group_name: beken_usb - -# 依赖宏控 -depend_macro: - - BUILD_LIB - -# 编译连接信息 -build_option: - cpppath: - - . - - include - - include/class - - src/cd - - src/drivers - - src/drivers/comm - - src/drivers/hid - - src/drivers/msd - - src/examples/msd - - src/hid - - src/lib - - src/msc - - src/systems/none/afs - - src/systems/none - - src/uvc - libs: - - usb - libpath: - - . - libname: - - libusb.a - -# 源码 -source_file: - - src/cd/mu_cntlr.c - - src/cd/mu_descs.c - - src/cd/mu_drc.c - - src/cd/mu_fc.c - - src/cd/mu_fdr.c - - src/cd/mu_fun.c - - src/cd/mu_funex.c - - src/cd/mu_hc.c - - src/cd/mu_hdr.c - - src/cd/mu_hsdma.c - - src/cd/mu_hst.c - - src/cd/mu_list.c - - src/cd/mu_mdr.c - - src/cd/mu_pip.c - - src/drivers/comm/mu_comif.c - - src/drivers/hid/mu_hidif.c - - src/drivers/hid/mu_hidkb.c - - src/drivers/hid/mu_hidmb.c - - src/drivers/msd/mu_mapi.c - - src/drivers/msd/mu_mbot.c - - src/drivers/msd/mu_mscsi.c - - src/examples/msd/mu_msdfn.c - - src/hid/usb_hid.c - - src/lib/mu_bits.c - - src/lib/mu_stack.c - - src/lib/mu_stdio.c - - src/lib/mu_strng.c - - src/msc/usb_msd.c - - src/systems/none/afs/board.c - - src/systems/none/plat_uds.c - - src/uvc/usb_uvc.c - - src/uvc/uvc_driver.c diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb_lib/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb_lib/weave.yaml deleted file mode 100644 index b35bc6e7034fcbdf93c0f716bcc869ac91ce73d6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/usb/beken_usb_lib/weave.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# 组名 -group_name: beken_usb_lib - -# 依赖宏控 -depend_macro: - - SOC_FAMILY_BK72XX - -# 编译连接信息 -build_option: - cpppath: - - . - - include - - include/class - - src/cd - - src/drivers - - src/drivers/comm - - src/drivers/hid - - src/drivers/msd - - src/examples/msd - - src/hid - - src/lib - - src/msc - - src/systems/none/afs - - src/systems/none - - src/uvc - libs: - - usb - libpath: - - . - - - \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/include/mu_mem.h b/drivers/hal/beken/beken72XX_HAL/driver/usb/include/mu_mem.h index 1a3efb04b3d9b6b34aa4c54cf49fcec648eb2e50..bed0716ad9c9000e601a7207b7924cdcb7c38eda 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/usb/include/mu_mem.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/usb/include/mu_mem.h @@ -34,7 +34,7 @@ #endif #ifndef MUSB_MemFree -#define MUSB_MemFree os_free +#define MUSB_MemFree os_free_loose #endif #ifndef MUSB_MemCopy diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/src/systems/none/afs/brd_mem.h b/drivers/hal/beken/beken72XX_HAL/driver/usb/src/systems/none/afs/brd_mem.h index 11c79775d1dd60676a71369fa06be871d58fbba1..2c743bc679ff968cbf57184203087e22a8f524d0 100644 --- a/drivers/hal/beken/beken72XX_HAL/driver/usb/src/systems/none/afs/brd_mem.h +++ b/drivers/hal/beken/beken72XX_HAL/driver/usb/src/systems/none/afs/brd_mem.h @@ -18,7 +18,7 @@ #define MUSB_MemAlloc(a) os_malloc(a) #define MUSB_MemRealloc os_realloc -#define MUSB_MemFree os_free +#define MUSB_MemFree os_free_loose #define MUSB_MemCopy(_pDest, _pSrc, _iSize) \ os_memcpy((void*)_pDest, (void*)_pSrc, _iSize) diff --git a/drivers/hal/beken/beken72XX_HAL/driver/usb/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/usb/weave.yaml deleted file mode 100644 index 67153a57f67025d62619b987346dfc8976f1978f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/usb/weave.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# 子目录 -add_subdirectory: - - beken_usb_lib ? {(not is_define('CFG_SOC_NAME', SOC_BK7231N)) and (not is_define('CFG_USB', 0))} - - beken_usb ? {(not is_define('CFG_SOC_NAME', SOC_BK7231N)) and (not is_define('CFG_USB', 0))} \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/driver/weave.yaml b/drivers/hal/beken/beken72XX_HAL/driver/weave.yaml deleted file mode 100644 index 467cff735f6d46a798f44f0bfa3ba0ec5e23236b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/driver/weave.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# 子目录 -add_subdirectory: - - ./* \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_main.c b/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_main.c index 5bae465c7b7485169183f498ceea7d5b2a427678..b4a91f17e047b1af7d8561eb87e18875c7278b50 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_main.c +++ b/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_main.c @@ -543,13 +543,13 @@ kiss_exit: if(ak_contex) { - os_free(ak_contex); + os_free_loose(ak_contex); ak_contex = NULL; } if(airkiss_read_buf) { - os_free(airkiss_read_buf); + os_free_loose(airkiss_read_buf); airkiss_read_buf = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_pingpong.c b/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_pingpong.c index a49fc8823b89e050472c617247e2b312b8e3bb75..6cc59118b2e626849f97c0992f36d7e0dbd0e68b 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_pingpong.c +++ b/drivers/hal/beken/beken72XX_HAL/func/airkiss/airkiss_pingpong.c @@ -136,7 +136,7 @@ void pingpong_free(void) if (pp_buf->buf1.addr) { PINIGPONG_PRT("buf1_free:0x%x\r\n", pp_buf->buf1.addr); - os_free(pp_buf->buf1.addr); + os_free_loose(pp_buf->buf1.addr); pp_buf->buf1.addr = NULL; pp_buf->buf1.next_buf_addr = NULL; diff --git a/drivers/hal/beken/beken72XX_HAL/func/airkiss/bk_airkiss.c b/drivers/hal/beken/beken72XX_HAL/func/airkiss/bk_airkiss.c index 1dcb77e5c2d0f2145f715865411847af0772f951..8b6499349f9b7c28c188dbb65e492424c59ba0c3 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/airkiss/bk_airkiss.c +++ b/drivers/hal/beken/beken72XX_HAL/func/airkiss/bk_airkiss.c @@ -91,7 +91,7 @@ uint32_t bk_airkiss_resource_destroy(void) if (airkiss_context_ptr != NULL) { - os_free(airkiss_context_ptr); + os_free_loose(airkiss_context_ptr); airkiss_context_ptr = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/bk7231N_cal.c b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/bk7231N_cal.c index 6968ecbe7544ba919e7c6c38ba9eff964ea7d1ab..dbb2ea47555069808af46ee04ca76b5fc456c223 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/bk7231N_cal.c +++ b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/bk7231N_cal.c @@ -6066,7 +6066,7 @@ void bk7011_la_sample_print(UINT32 isrx) os_printf("%08x\r\n", *((uint32_t *)(buf+i*4))); } - os_free(buf); + os_free_loose(buf); } void bk7011_max_rxsens_setting(void) diff --git a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231.c b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231.c index f718fdd71b36639810e5aa091a5f827f39da170e..f181b546d5334364b017f52825bff792fffec335 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231.c +++ b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231.c @@ -878,7 +878,7 @@ updata_exit: ddev_close(flash_handle); if(read_buf) - os_free(read_buf); + os_free_loose(read_buf); return ret; } @@ -1196,7 +1196,7 @@ int manual_cal_save_txpwr_tab_to_flash(void) addr_start -= pt->partition_start_addr;//TXPWR_TAB_FLASH_ADDR; manual_cal_update_flash_area(addr_start, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } @@ -1343,7 +1343,7 @@ int manual_cal_save_chipinfo_tab_to_flash(void) tag_com.value = *((UINT32 *)&saradc_val); os_memcpy(tag_com_ptr, &tag_com, sizeof(TAG_COMM_ST)); manual_cal_update_flash_area(0, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } @@ -1492,7 +1492,7 @@ void manual_cal_show_otp_flash(void) } MCAL_PRT("\r\n"); - os_free(buf); + os_free_loose(buf); } else { @@ -1509,7 +1509,7 @@ void manual_cal_clear_otp_flash(void) os_memset(buf, 0xff, sizeof(flash_len)); manual_cal_update_flash_area(0, (char *)buf, flash_len); - os_free(buf); + os_free_loose(buf); } static UINT32 manual_cal_g_rfcali_status(void) diff --git a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231U.c b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231U.c index e7965223c7c7867db16041af27d8545e1db4aa09..32d4bbd5efbad78634e163b16fadf5f5a75e67db 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231U.c +++ b/drivers/hal/beken/beken72XX_HAL/func/bk7011_cal/manual_cal_bk7231U.c @@ -1356,7 +1356,7 @@ updata_exit: ddev_close(flash_handle); if(read_buf) - os_free(read_buf); + os_free_loose(read_buf); return ret; } @@ -1729,7 +1729,7 @@ int manual_cal_save_txpwr_tab_to_flash(void) addr_start -= pt->partition_start_addr;//TXPWR_TAB_FLASH_ADDR; manual_cal_update_flash_area(addr_start, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } @@ -1889,7 +1889,7 @@ int manual_cal_save_chipinfo_tab_to_flash(void) os_memcpy(tag_lpf_iq_ptr, &tag_lpf_iq, sizeof(TAG_LPF_IQ_ST)); manual_cal_update_flash_area(0, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } @@ -2041,7 +2041,7 @@ void manual_cal_show_otp_flash(void) } MCAL_PRT("\r\n"); - os_free(buf); + os_free_loose(buf); } else { @@ -2058,7 +2058,7 @@ void manual_cal_clear_otp_flash(void) os_memset(buf, 0xff, sizeof(flash_len)); manual_cal_update_flash_area(0, (char *)buf, flash_len); - os_free(buf); + os_free_loose(buf); } static UINT32 manual_cal_g_rfcali_status(void) @@ -2635,7 +2635,7 @@ int manual_cal_save_cailmain_tx_tab_to_flash(void) addr_start -= pt->partition_start_addr;//TXPWR_TAB_FLASH_ADDR; manual_cal_update_flash_area(addr_start, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } @@ -2753,7 +2753,7 @@ int manual_cal_save_cailmain_rx_tab_to_flash(void) addr_start -= pt->partition_start_addr;//TXPWR_TAB_FLASH_ADDR; manual_cal_update_flash_area(addr_start, (char *)buf, len); - os_free(buf); + os_free_loose(buf); return 1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/easy_flash/bk_ef.c b/drivers/hal/beken/beken72XX_HAL/func/easy_flash/bk_ef.c index 45b587006b81897758e1c767347cc62e42b6eeb4..ae8582d23cf2b9073a392ba0615a060ba64dfb58 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/easy_flash/bk_ef.c +++ b/drivers/hal/beken/beken72XX_HAL/func/easy_flash/bk_ef.c @@ -44,14 +44,14 @@ EfErrCode bk_set_buf_env(const char *key, const char *buf, int len) ret = base64_encode((unsigned char*)buf, len, &out_len, ef_value); if(0 == ret) { - os_free(ef_value); + os_free_loose(ef_value); ef_value = NULL; return EF_ENV_INIT_FAILED; } result = ef_set_env(key, (char*)ef_value); - os_free(ef_value); + os_free_loose(ef_value); return result; } @@ -86,7 +86,7 @@ EfErrCode bk_get_buf_env(const char *key, const char *buf, int len) ret = base64_decode((unsigned char*)ef_value, value_len, &out_len, out_ptr); if(0 == ret) { - os_free(out_ptr); + os_free_loose(out_ptr); out_ptr = NULL; return EF_ENV_INIT_FAILED; } @@ -99,7 +99,7 @@ EfErrCode bk_get_buf_env(const char *key, const char *buf, int len) os_memcpy((void*)buf, out_ptr, count); } - os_free(out_ptr); + os_free_loose(out_ptr); return EF_NO_ERR; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/fatfs/test_fatfs.c b/drivers/hal/beken/beken72XX_HAL/func/fatfs/test_fatfs.c index b46601a7619722fe10d452e7098b682d6bfa9add..67166d46c0c803283c24c449bcb49e72e9c635a1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/fatfs/test_fatfs.c +++ b/drivers/hal/beken/beken72XX_HAL/func/fatfs/test_fatfs.c @@ -69,7 +69,7 @@ void test_mount(DISK_NUMBER number) if (pfs != NULL) { - os_free(pfs); + os_free_loose(pfs); } pfs = os_malloc(sizeof(FATFS)); diff --git a/drivers/hal/beken/beken72XX_HAL/func/func.c b/drivers/hal/beken/beken72XX_HAL/func/func.c index 625da7d6b78b8ec6e1c14ec1ad681364e1694988..f2171231908320e72cafe194636cafe3b827c05f 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/func.c +++ b/drivers/hal/beken/beken72XX_HAL/func/func.c @@ -48,7 +48,6 @@ UINT32 func_init_extended(void) cfg_param_init(); FUNC_PRT("[FUNC]rwnxl_init\r\n"); - os_kprintf("[FUNC]rwnxl_init\r\n"); rwnxl_init(); #if CFG_UART_DEBUG @@ -63,11 +62,11 @@ UINT32 func_init_extended(void) intc_init(); #endif - #if CFG_SUPPORT_CALIBRATION UINT32 is_tab_inflash = 0; FUNC_PRT("[FUNC]calibration_main\r\n"); calibration_main(); + #if CFG_SUPPORT_MANUAL_CALI is_tab_inflash = manual_cal_load_txpwr_tab_flash(); manual_cal_load_default_txpwr_tab(is_tab_inflash); @@ -136,8 +135,7 @@ UINT32 func_init_extended(void) bk_wdg_reload(); #endif - FUNC_PRT("[FUNC]func_init_extended OVER!!!\r\n\r\n"); - os_kprintf("start_type:%d\r\n",bk_misc_get_start_type()); + os_printf("start_type:%d\r\n",bk_misc_get_start_type()); UINT32 reg = 0; sddev_control(SCTRL_DEV_NAME, CMD_RF_HOLD_BIT_CLR, ®); diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/fake_socket.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/fake_socket.c index bd775bf6c8b50b37495abb581e5b29d3201e0376..35aa12488e0a489368c67d5f1acc08ac969b19e7 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/fake_socket.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/fake_socket.c @@ -49,7 +49,7 @@ int ke_sk_send(SOCKET sk, const unsigned char *buf, int len, int flag) return ret; malloc_buf_exit: - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = NULL; tx_exit: @@ -83,12 +83,12 @@ int ke_sk_recv(SOCKET sk, const unsigned char *buf, int len, int flag) ret = count; - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; dl_list_del(&sk_msg->data); - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = 0; break; @@ -250,7 +250,7 @@ int fsocket_send(SOCKET sk, const unsigned char *buf, int len, S_TYPE_PTR type) return ret; malloc_buf_exit: - os_free(sk_msg); + os_free_loose(sk_msg); tx_exit: return ret; @@ -287,12 +287,12 @@ int fsocket_recv(SOCKET sk, const unsigned char *buf, int len, int flag) os_memcpy((void *)buf, (void *)sk_msg->msg, count); ret = count; - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; dl_list_del(&sk_msg->data); - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = 0; break; @@ -325,12 +325,12 @@ void fsocket_close(SOCKET sk) if(sk_msg->msg) { - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; } - os_free(sk_msg); + os_free_loose(sk_msg); } dl_list_for_each_safe(sk_msg, tmp, &element->sk_rx_msg, SOCKET_MSG, data) @@ -339,17 +339,17 @@ void fsocket_close(SOCKET sk) if(sk_msg->msg) { - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; } - os_free(sk_msg); + os_free_loose(sk_msg); } dl_list_del(&element->sk_element); - os_free(element); + os_free_loose(element); element = 0; GLOBAL_INT_RESTORE(); diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/sk_intf.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/sk_intf.c index 3917e97df224ab6885268cc5721b9ed411b52f03..8e72d1649ddca06534431d33ce5379de08d4e43d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/sk_intf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/bk_patch/sk_intf.c @@ -50,7 +50,7 @@ void handle_dummy_read(int sock, void *eloop_ctx, void *sock_ctx) dummy_exit: if(buf) { - os_free(buf); + os_free_loose(buf); } return; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/hostapd/main_none.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/hostapd/main_none.c index fdfc903dca6dc9a881c89668f937b21fb1077e24..c0e802e874c8d0432f6901669c309444f353ec2e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/hostapd/main_none.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/hostapd/main_none.c @@ -136,14 +136,14 @@ struct hostapd_config * hostapd_cfg_defaults(void) if (conf == NULL || bss == NULL) { wpa_printf(MSG_ERROR, "Failed to allocate memory for " "configuration data."); - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss = os_calloc(1, sizeof(struct hostapd_bss_config *)); if (conf->bss == NULL) { - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss[0] = bss; @@ -267,7 +267,7 @@ struct hostapd_config *hostapd_config_read(const char *fname) } if (g_ap_param_ptr->cipher_suite > BK_SECURITY_TYPE_WEP) { const char *wpa_key = (char *)g_ap_param_ptr->key; - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = os_strdup(wpa_key); if (bss->ssid.wpa_passphrase) { hostapd_config_clear_wpa_psk(&bss->ssid.wpa_psk); @@ -324,7 +324,7 @@ static int hostapd_config_parse_key_mgmt(int line, const char *value) else { wpa_printf(MSG_ERROR, "Line %d: invalid key_mgmt '%s'", line, start); - os_free(buf); + os_free_loose(buf); return -1; } @@ -333,7 +333,7 @@ static int hostapd_config_parse_key_mgmt(int line, const char *value) start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, "Line %d: no key_mgmt values " "configured.", line); @@ -415,7 +415,7 @@ static int hostapd_parse_intlist(int **int_list, char *val) int count; char *pos, *end; - os_free(*int_list); + os_free_loose(*int_list); *int_list = NULL; pos = val; @@ -534,7 +534,7 @@ static int hostapd_config_fill(struct hostapd_config *conf, line, len); return 1; } - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = os_strdup(pos); if (bss->ssid.wpa_passphrase) { hostapd_config_clear_wpa_psk(&bss->ssid.wpa_psk); @@ -553,7 +553,7 @@ static int hostapd_config_fill(struct hostapd_config *conf, return 1; } bss->ssid.wpa_psk->group = 1; - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = NULL; bss->ssid.wpa_psk_set = 1; } else if (os_strcmp(buf, "wpa_key_mgmt") == 0) { @@ -800,7 +800,7 @@ static int hostapd_driver_init(struct hostapd_iface *iface) params.own_addr = hapd->own_addr; hapd->drv_priv = hapd->driver->hapd_init(hapd, ¶ms); - os_free(params.bridge); + os_free_loose(params.bridge); if (hapd->drv_priv == NULL) { wpa_printf(MSG_ERROR, "%s driver initialization failed.", hapd->driver->name); @@ -825,7 +825,7 @@ static int hostapd_driver_init(struct hostapd_iface *iface) if (hapd->driver->set_wowlan(hapd->drv_priv, triggs)) wpa_printf(MSG_ERROR, "set_wowlan failed"); } - os_free(triggs); + os_free_loose(triggs); #endif } @@ -900,7 +900,7 @@ static void hostapd_global_deinit(const char *pid_file) if(wpa_drivers[i]->global_deinit) wpa_drivers[i]->global_deinit(s_hapd_global.drv_priv[i]); } - os_free(s_hapd_global.drv_priv); + os_free_loose(s_hapd_global.drv_priv); s_hapd_global.drv_priv = NULL; eloop_free_resource(); @@ -952,7 +952,7 @@ int hostapd_main_exit(void) hostapd_interface_deinit_free(g_hapd_interfaces.iface[i]); g_hapd_interfaces.iface[i] = NULL; } - os_free(g_hapd_interfaces.iface); + os_free_loose(g_hapd_interfaces.iface); g_hapd_interfaces.iface = NULL; g_hapd_interfaces.count = 0; @@ -1001,7 +1001,7 @@ int hostapd_main_entry(int argc, char *argv[]) //os_memcpy(ap_iface_buf, CFG_AP_IFACE_CONFIG,(strlen(CFG_AP_IFACE_CONFIG) + 1)); if (os_program_init()) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); return -1; } @@ -1024,14 +1024,14 @@ int hostapd_main_entry(int argc, char *argv[]) g_hapd_interfaces.iface = os_calloc(g_hapd_interfaces.count + num_bss_configs, sizeof(struct hostapd_iface *)); if (g_hapd_interfaces.iface == NULL) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); fatal_prf("malloc failed\r\n"); return -1; } } if (hostapd_global_init(&g_hapd_interfaces, entropy_file)) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); fatal_prf("Failed to initialize global context\r\n"); return -1; } @@ -1107,7 +1107,7 @@ int hostapd_main_entry(int argc, char *argv[]) ret = 0; - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); //ap_iface_buf = NULL; return ret; @@ -1126,14 +1126,14 @@ out: hostapd_interface_deinit_free(g_hapd_interfaces.iface[i]); g_hapd_interfaces.iface[i] = NULL; } - os_free(g_hapd_interfaces.iface); + os_free_loose(g_hapd_interfaces.iface); g_hapd_interfaces.iface = NULL; g_hapd_interfaces.count = 0; eloop_cancel_timeout(hostapd_periodic, &g_hapd_interfaces, NULL); hostapd_global_deinit(pid_file); - os_free(pid_file); + os_free_loose(pid_file); pid_file = NULL; if (log_file) diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_config.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_config.c index 614d49cef5412de5bd86fa6d50e73cb0bf7e1962..d16314cce6cee48b2d60d9c82d92e0f970e39cc3 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_config.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_config.c @@ -26,7 +26,7 @@ static void hostapd_config_free_vlan(struct hostapd_bss_config *bss) while (vlan) { prev = vlan; vlan = vlan->next; - os_free(prev); + os_free_loose(prev); } bss->vlan = NULL; @@ -128,14 +128,14 @@ struct hostapd_config * hostapd_config_defaults(void) if (conf == NULL || bss == NULL) { wpa_printf(MSG_ERROR, "Failed to allocate memory for " "configuration data."); - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss = os_calloc(1, sizeof(struct hostapd_bss_config *)); if (conf->bss == NULL) { - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss[0] = bss; @@ -256,7 +256,7 @@ static void hostapd_config_free_anqp_elem(struct hostapd_bss_config *conf) list))) { dl_list_del(&elem->list); wpabuf_free(elem->payload); - os_free(elem); + os_free_loose(elem); } } #endif @@ -273,24 +273,24 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) str_clear_free(conf->ssid.wpa_passphrase); hostapd_config_free_wep(&conf->ssid.wep); #ifdef CONFIG_FULL_DYNAMIC_VLAN - os_free(conf->ssid.vlan_tagged_interface); + os_free_loose(conf->ssid.vlan_tagged_interface); #endif /* CONFIG_FULL_DYNAMIC_VLAN */ - os_free(conf->rsn_preauth_interfaces); - os_free(conf->ctrl_interface); - os_free(conf->ca_cert); - os_free(conf->server_cert); - os_free(conf->private_key); - os_free(conf->private_key_passwd); - os_free(conf->ocsp_stapling_response); - os_free(conf->ocsp_stapling_response_multi); - os_free(conf->dh_file); - os_free(conf->openssl_ciphers); - os_free(conf->pac_opaque_encr_key); - os_free(conf->eap_fast_a_id); - os_free(conf->eap_fast_a_id_info); + os_free_loose(conf->rsn_preauth_interfaces); + os_free_loose(conf->ctrl_interface); + os_free_loose(conf->ca_cert); + os_free_loose(conf->server_cert); + os_free_loose(conf->private_key); + os_free_loose(conf->private_key_passwd); + os_free_loose(conf->ocsp_stapling_response); + os_free_loose(conf->ocsp_stapling_response_multi); + os_free_loose(conf->dh_file); + os_free_loose(conf->openssl_ciphers); + os_free_loose(conf->pac_opaque_encr_key); + os_free_loose(conf->eap_fast_a_id); + os_free_loose(conf->eap_fast_a_id_info); hostapd_config_free_vlan(conf); - os_free(conf->time_zone); + os_free_loose(conf->time_zone); #ifdef CONFIG_IEEE80211R { @@ -302,7 +302,7 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) while (r0kh) { r0kh_prev = r0kh; r0kh = r0kh->next; - os_free(r0kh_prev); + os_free_loose(r0kh_prev); } r1kh = conf->r1kh_list; @@ -310,17 +310,17 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) while (r1kh) { r1kh_prev = r1kh; r1kh = r1kh->next; - os_free(r1kh_prev); + os_free_loose(r1kh_prev); } } #endif /* CONFIG_IEEE80211R */ - os_free(conf->roaming_consortium); - os_free(conf->venue_name); - os_free(conf->nai_realm_data); - os_free(conf->network_auth_type); - os_free(conf->anqp_3gpp_cell_net); - os_free(conf->domain_name); + os_free_loose(conf->roaming_consortium); + os_free_loose(conf->venue_name); + os_free_loose(conf->nai_realm_data); + os_free_loose(conf->network_auth_type); + os_free_loose(conf->anqp_3gpp_cell_net); + os_free_loose(conf->domain_name); #ifdef CONFIG_INTERWORKING hostapd_config_free_anqp_elem(conf); #endif @@ -328,16 +328,16 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) wpabuf_free(conf->vendor_elements); wpabuf_free(conf->assocresp_elements); - os_free(conf->sae_groups); + os_free_loose(conf->sae_groups); - os_free(conf->wowlan_triggers); + os_free_loose(conf->wowlan_triggers); - os_free(conf->server_id); + os_free_loose(conf->server_id); - os_free(conf->no_probe_resp_if_seen_on); - os_free(conf->no_auth_if_seen_on); + os_free_loose(conf->no_probe_resp_if_seen_on); + os_free_loose(conf->no_auth_if_seen_on); - os_free(conf); + os_free_loose(conf); } @@ -354,16 +354,16 @@ void hostapd_config_free(struct hostapd_config *conf) for (i = 0; i < conf->num_bss; i++) hostapd_config_free_bss(conf->bss[i]); - os_free(conf->bss); - os_free(conf->supported_rates); - os_free(conf->basic_rates); - os_free(conf->acs_ch_list.range); - os_free(conf->driver_params); + os_free_loose(conf->bss); + os_free_loose(conf->supported_rates); + os_free_loose(conf->basic_rates); + os_free_loose(conf->acs_ch_list.range); + os_free_loose(conf->driver_params); #ifdef CONFIG_ACS - os_free(conf->acs_chan_bias); + os_free_loose(conf->acs_chan_bias); #endif /* CONFIG_ACS */ - os_free(conf); + os_free_loose(conf); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_drv_ops.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_drv_ops.c index 3342971f26685d94613c6160bdf6c647a8b6b5c9..da25179fe50b7800fcb962faefc4843a32de3a47 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_drv_ops.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_drv_ops.c @@ -600,7 +600,10 @@ int hostapd_drv_set_key(const char *ifname, struct hostapd_data *hapd, const u8 *key, size_t key_len) { if (hapd->driver == NULL || hapd->driver->set_key == NULL) + { return 0; + } + return hapd->driver->set_key(ifname, hapd->drv_priv, alg, addr, key_idx, set_tx, seq, seq_len, key, key_len); @@ -855,7 +858,7 @@ int hostapd_drv_do_acs(struct hostapd_data *hapd) } ret = hapd->driver->do_acs(hapd->drv_priv, ¶ms); - os_free(channels); + os_free_loose(channels); return ret; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_list.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_list.c index 1930231a46e2a8a3af079d352ded4465e098039c..de285c0bf3f95d7cc5fc13f99511c1c0cb1b46ec 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_list.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ap_list.c @@ -122,7 +122,7 @@ static void ap_free_ap(struct hostapd_iface *iface, struct ap_info *ap) ap_ap_list_del(iface, ap); iface->num_ap--; - os_free(ap); + os_free_loose(ap); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/beacon.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/beacon.c index cbdea1046f5357019d23f704f7ffd6815f92a6e0..7098861b2c04cfdbd07ed7cbd8236a0b0cce4157 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/beacon.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/beacon.c @@ -887,7 +887,7 @@ void handle_probe_req(struct hostapd_data *hapd, if (ret < 0) wpa_printf(MSG_INFO, "handle_probe_req: send failed"); - os_free(resp); + os_free_loose(resp); wpa_printf(MSG_EXCESSIVE, "STA " MACSTR " sent probe request for %s " "SSID", MAC2STR(mgmt->sa), @@ -939,7 +939,7 @@ void sta_track_del(struct hostapd_sta_info *info) wpabuf_free(info->probe_ie_taxonomy); info->probe_ie_taxonomy = NULL; #endif /* CONFIG_TAXONOMY */ - os_free(info); + os_free_loose(info); } @@ -977,8 +977,8 @@ int ieee802_11_build_ap_params(struct hostapd_data *hapd, tailpos = tail = os_malloc(tail_len); if (head == NULL || tail == NULL) { wpa_printf(MSG_ERROR, "Failed to set beacon data"); - os_free(head); - os_free(tail); + os_free_loose(head); + os_free_loose(tail); return -1; } @@ -1189,11 +1189,11 @@ int ieee802_11_build_ap_params(struct hostapd_data *hapd, void ieee802_11_free_ap_params(struct wpa_driver_ap_params *params) { - os_free(params->tail); + os_free_loose(params->tail); params->tail = NULL; - os_free(params->head); + os_free_loose(params->head); params->head = NULL; - os_free(params->proberesp); + os_free_loose(params->proberesp); params->proberesp = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/drv_callbacks.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/drv_callbacks.c index 531c5601cf70cc4f72430c9104c03bee70a7f6a5..4112fc4842ffced82dad8f4ac7715d6afd843170 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/drv_callbacks.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/drv_callbacks.c @@ -841,7 +841,7 @@ static int hostapd_mgmt_rx(struct hostapd_data *hapd, struct rx_mgmt *rx_mgmt) wpa_snprintf_hex(hex, hex_len, rx_mgmt->frame, rx_mgmt->frame_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "MGMT-RX %s", hex); - os_free(hex); + os_free_loose(hex); } return 1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hostapd.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hostapd.c index 6689271130de61faaa5f0cac7f2505b7845f2df2..0025baaad92fb5950653a6d321db0e7251186aad 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hostapd.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hostapd.c @@ -203,6 +203,7 @@ static void hostapd_broadcast_key_clear_iface(struct hostapd_data *hapd, int i; for (i = 0; i < NUM_WEP_KEYS; i++) { + os_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); if (hostapd_drv_set_key(ifname, hapd, WPA_ALG_NONE, NULL, i, 0, NULL, 0, NULL, 0)) { wpa_printf(MSG_DEBUG, "Failed to clear default " @@ -213,6 +214,7 @@ static void hostapd_broadcast_key_clear_iface(struct hostapd_data *hapd, #ifdef CONFIG_IEEE80211W if (hapd->conf->ieee80211w) { for (i = NUM_WEP_KEYS; i < NUM_WEP_KEYS + 2; i++) { + os_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); if (hostapd_drv_set_key(ifname, hapd, WPA_ALG_NONE, NULL, i, 0, NULL, 0, NULL, 0)) { @@ -254,7 +256,7 @@ static int hostapd_broadcast_wep_set(struct hostapd_data *hapd) static void hostapd_free_hapd_data(struct hostapd_data *hapd) { - os_free(hapd->probereq_cb); + os_free_loose(hapd->probereq_cb); hapd->probereq_cb = NULL; hapd->num_probereq_cb = 0; @@ -382,10 +384,10 @@ static void hostapd_cleanup_iface_partial(struct hostapd_iface *iface) hostapd_free_hw_features(iface->hw_features, iface->num_hw_features); iface->hw_features = NULL; - os_free(iface->current_rates); + os_free_loose(iface->current_rates); iface->current_rates = NULL; - os_free(iface->basic_rates); + os_free_loose(iface->basic_rates); iface->basic_rates = NULL; ap_list_deinit(iface); @@ -409,10 +411,10 @@ static void hostapd_cleanup_iface(struct hostapd_iface *iface) hostapd_config_free(iface->conf); iface->conf = NULL; - os_free(iface->config_fname); - os_free(iface->bss); + os_free_loose(iface->config_fname); + os_free_loose(iface->bss); wpa_printf(MSG_DEBUG, "%s: free iface=%p", __func__, iface); - os_free(iface); + os_free_loose(iface); } @@ -920,7 +922,7 @@ static int hostapd_set_acl_list(struct hostapd_data *hapd, err = hostapd_drv_set_acl(hapd, acl_params); - os_free(acl_params); + os_free_loose(acl_params); return err; } @@ -1565,7 +1567,7 @@ void hostapd_interface_free(struct hostapd_iface *iface) break; wpa_printf(MSG_DEBUG, "%s: free hapd %p", __func__, iface->bss[j]); - os_free(iface->bss[j]); + os_free_loose(iface->bss[j]); } hostapd_cleanup_iface(iface); } @@ -1638,11 +1640,11 @@ fail: if (conf) hostapd_config_free(conf); if (hapd_iface) { - os_free(hapd_iface->config_fname); - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->config_fname); + os_free_loose(hapd_iface->bss); wpa_printf(MSG_DEBUG, "%s: free iface %p", __func__, hapd_iface); - os_free(hapd_iface); + os_free_loose(hapd_iface); } return NULL; } @@ -2023,10 +2025,10 @@ static int hostapd_data_alloc(struct hostapd_iface *hapd_iface, if (hapd == NULL) { while (i > 0) { i--; - os_free(hapd_iface->bss[i]); + os_free_loose(hapd_iface->bss[i]); hapd_iface->bss[i] = NULL; } - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->bss); hapd_iface->bss = NULL; return -1; } @@ -2114,7 +2116,7 @@ int hostapd_add_iface(struct hapd_interfaces *interfaces, char *buf) __func__, hapd, hapd->conf->iface); hostapd_config_free_bss(hapd->conf); hapd->conf = NULL; - os_free(hapd); + os_free_loose(hapd); return -1; } } @@ -2197,10 +2199,10 @@ fail: __func__, hapd_iface->bss[i], hapd->conf->iface); hostapd_cleanup(hapd); - os_free(hapd); + os_free_loose(hapd); hapd_iface->bss[i] = NULL; } - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->bss); hapd_iface->bss = NULL; } if (new_iface) { @@ -2228,7 +2230,7 @@ static int hostapd_remove_bss(struct hostapd_iface *iface, unsigned int idx) __func__, hapd, hapd->conf->iface); hostapd_config_free_bss(hapd->conf); hapd->conf = NULL; - os_free(hapd); + os_free_loose(hapd); iface->num_bss--; @@ -2400,17 +2402,17 @@ int hostapd_csa_in_progress(struct hostapd_iface *iface) #ifdef NEED_AP_MLME static void free_beacon_data(struct beacon_data *beacon) { - os_free(beacon->head); + os_free_loose(beacon->head); beacon->head = NULL; - os_free(beacon->tail); + os_free_loose(beacon->tail); beacon->tail = NULL; - os_free(beacon->probe_resp); + os_free_loose(beacon->probe_resp); beacon->probe_resp = NULL; - os_free(beacon->beacon_ies); + os_free_loose(beacon->beacon_ies); beacon->beacon_ies = NULL; - os_free(beacon->proberesp_ies); + os_free_loose(beacon->proberesp_ies); beacon->proberesp_ies = NULL; - os_free(beacon->assocresp_ies); + os_free_loose(beacon->assocresp_ies); beacon->assocresp_ies = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hw_features.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hw_features.c index 83f354f85a72149cce6095b053d9018786c56e38..ff06e35b2f1ecc5cfdb4429613773f5c9303ed9b 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hw_features.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/hw_features.c @@ -37,11 +37,11 @@ void hostapd_free_hw_features(struct hostapd_hw_modes *hw_features, return; for (i = 0; i < num_hw_features; i++) { - os_free(hw_features[i].channels); - os_free(hw_features[i].rates); + os_free_loose(hw_features[i].channels); + os_free_loose(hw_features[i].rates); } - os_free(hw_features); + os_free_loose(hw_features); } @@ -177,13 +177,13 @@ int hostapd_prepare_rates(struct hostapd_iface *iface, i++; if (i) i++; /* -1 termination */ - os_free(iface->basic_rates); + os_free_loose(iface->basic_rates); iface->basic_rates = os_malloc(i * sizeof(int)); if (iface->basic_rates) os_memcpy(iface->basic_rates, basic_rates, i * sizeof(int)); if (iface->current_rates) - os_free(iface->current_rates); + os_free_loose(iface->current_rates); iface->num_rates = 0; iface->current_rates = @@ -442,7 +442,7 @@ static void ap_ht40_scan_retry(void *eloop_data, void *user_data) ret = hostapd_driver_scan(iface->bss[0], ¶ms); iface->num_ht40_scan_tries++; - os_free(params.freqs); + os_free_loose(params.freqs); if (ret == -ERRBUSY && iface->num_ht40_scan_tries < HT2040_COEX_SCAN_RETRY) { @@ -491,7 +491,7 @@ static int ieee80211n_check_40mhz(struct hostapd_iface *iface) ieee80211n_scan_channels_5g(iface, ¶ms); ret = hostapd_driver_scan(iface->bss[0], ¶ms); - os_free(params.freqs); + os_free_loose(params.freqs); if (ret == -ERRBUSY) { wpa_printf(MSG_ERROR, diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11.c index c2e55aaf6af00f3f1064b94aba8220627999a301..d9be568836b2b674e2f68207d57db65faacd4103 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11.c @@ -222,7 +222,7 @@ static u16 auth_shared_key(struct hostapd_data *hapd, struct sta_info *sta, return WLAN_STATUS_UNSPECIFIED_FAILURE; if (os_get_random(key, sizeof(key)) < 0) { - os_free(sta->challenge); + os_free_loose(sta->challenge); sta->challenge = NULL; return WLAN_STATUS_UNSPECIFIED_FAILURE; } @@ -252,7 +252,7 @@ static u16 auth_shared_key(struct hostapd_data *hapd, struct sta_info *sta, "authentication OK (shared key)"); sta->flags |= WLAN_STA_AUTH; wpa_auth_sm_event(sta->wpa_sm, WPA_AUTH); - os_free(sta->challenge); + os_free_loose(sta->challenge); sta->challenge = NULL; return 0; @@ -298,7 +298,7 @@ static int send_auth_reply(struct hostapd_data *hapd, else reply_res = WLAN_STATUS_SUCCESS; - os_free(buf); + os_free_loose(buf); return reply_res; } @@ -1362,8 +1362,8 @@ static void handle_auth(struct hostapd_data *hapd, } fail: - os_free(identity); - os_free(radius_cui); + os_free_loose(identity); + os_free_loose(radius_cui); hostapd_free_psk_list(psk); reply_res = send_auth_reply(hapd, mgmt->sa, mgmt->bssid, auth_alg, @@ -2538,7 +2538,7 @@ static int handle_action(struct hostapd_data *hapd, wpa_printf(MSG_ERROR, "IEEE 802.11: Failed to send " "Action frame"); } - os_free(resp); + os_free_loose(resp); } return 1; @@ -2851,7 +2851,7 @@ static void handle_assoc_cb(struct hostapd_data *hapd, wpabuf_len(sta->pending_eapol_rx->buf)); } wpabuf_free(sta->pending_eapol_rx->buf); - os_free(sta->pending_eapol_rx); + os_free_loose(sta->pending_eapol_rx); sta->pending_eapol_rx = NULL; } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_auth.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_auth.c index cc762b883b5a3f5c0ffa9620be827ddf61cc3831..b9385181edea6852ad37c40a2b815b96020fb79e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_auth.c @@ -53,10 +53,10 @@ struct hostapd_acl_query_data { #ifndef CONFIG_NO_RADIUS static void hostapd_acl_cache_free_entry(struct hostapd_cached_radius_acl *e) { - os_free(e->identity); - os_free(e->radius_cui); + os_free_loose(e->identity); + os_free_loose(e->radius_cui); hostapd_free_psk_list(e->psk); - os_free(e); + os_free_loose(e); } @@ -137,8 +137,8 @@ static void hostapd_acl_query_free(struct hostapd_acl_query_data *query) { if (query == NULL) return; - os_free(query->auth_msg); - os_free(query); + os_free_loose(query->auth_msg); + os_free_loose(query); } @@ -247,7 +247,7 @@ int hostapd_check_acl(struct hostapd_data *hapd, const u8 *addr, * Returns: HOSTAPD_ACL_ACCEPT, HOSTAPD_ACL_REJECT, or HOSTAPD_ACL_PENDING * * The caller is responsible for freeing the returned *identity and *radius_cui - * values with os_free(). + * values with os_free_loose(). */ int hostapd_allowed_address(struct hostapd_data *hapd, const u8 *addr, const u8 *msg, size_t len, u32 *session_timeout, @@ -297,11 +297,11 @@ int hostapd_allowed_address(struct hostapd_data *hapd, const u8 *addr, /* pending query in RADIUS retransmit queue; * do not generate a new one */ if (identity) { - os_free(*identity); + os_free_loose(*identity); *identity = NULL; } if (radius_cui) { - os_free(*radius_cui); + os_free_loose(*radius_cui); *radius_cui = NULL; } return HOSTAPD_ACL_PENDING; @@ -483,9 +483,9 @@ static void decode_tunnel_passwords(struct hostapd_data *hapd, psk = NULL; } skip: - os_free(psk); + os_free_loose(psk); free_pass: - os_free(passphrase); + os_free_loose(passphrase); } } @@ -688,6 +688,6 @@ void hostapd_free_psk_list(struct hostapd_sta_wpa_psk_short *psk) while (psk) { struct hostapd_sta_wpa_psk_short *prev = psk; psk = psk->next; - os_free(prev); + os_free_loose(prev); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_ht.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_ht.c index 45c70a183038f6283a029b3c2fde40eaa95c399b..24bd1ace469add479ad5517136b8697755caa993 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_ht.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_ht.c @@ -343,7 +343,7 @@ u16 copy_sta_ht_capab(struct hostapd_data *hapd, struct sta_info *sta, if (!ht_capab || !(sta->flags & WLAN_STA_WMM) || hapd->conf->disable_11n) { sta->flags &= ~WLAN_STA_HT; - os_free(sta->ht_capabilities); + os_free_loose(sta->ht_capabilities); sta->ht_capabilities = NULL; return WLAN_STATUS_SUCCESS; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_shared.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_shared.c index cddbd5157ff5607141e9b425273350d2ad910d48..c0c9bb361ea8912fc3e0dd498f6f9446a12f7556 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_shared.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_shared.c @@ -566,7 +566,7 @@ void ap_copy_sta_supp_op_classes(struct sta_info *sta, { if (!supp_op_classes) return; - os_free(sta->supp_op_classes); + os_free_loose(sta->supp_op_classes); sta->supp_op_classes = os_malloc(1 + supp_op_classes_len); if (!sta->supp_op_classes) return; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_vht.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_vht.c index f30f63bc5709418f30f73478c7f97c4f7d9e7f7f..30462f1aea09718dc78549c1c08f54d17895f0f3 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_vht.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/ieee802_11_vht.c @@ -337,7 +337,7 @@ u16 copy_sta_vht_capab(struct hostapd_data *hapd, struct sta_info *sta, hapd->conf->disable_11ac || !check_valid_vht_mcs(hapd->iface->current_mode, vht_capab)) { sta->flags &= ~WLAN_STA_VHT; - os_free(sta->vht_capabilities); + os_free_loose(sta->vht_capabilities); sta->vht_capabilities = NULL; return WLAN_STATUS_SUCCESS; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/pmksa_cache_auth.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/pmksa_cache_auth.c index 5676a6fecfe9a8bbc0e893d6019a7d163712b92f..e0e4f636a27f56211001c22ac9104a5d6d976c0a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/pmksa_cache_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/pmksa_cache_auth.c @@ -40,8 +40,8 @@ static void pmksa_cache_set_expiration(struct rsn_pmksa_cache *pmksa); static void _pmksa_cache_free_entry(struct rsn_pmksa_cache_entry *entry) { - os_free(entry->vlan_desc); - os_free(entry->identity); + os_free_loose(entry->vlan_desc); + os_free_loose(entry->identity); wpabuf_free(entry->cui); #ifndef CONFIG_NO_RADIUS radius_free_class(&entry->radius_class); @@ -187,7 +187,7 @@ void pmksa_cache_to_eapol_data(struct hostapd_data *hapd, return; if (entry->identity) { - os_free(eapol->identity); + os_free_loose(eapol->identity); eapol->identity = os_malloc(entry->identity_len); if (eapol->identity) { eapol->identity_len = entry->identity_len; @@ -411,7 +411,7 @@ void pmksa_cache_auth_deinit(struct rsn_pmksa_cache *pmksa) pmksa->pmksa = NULL; for (i = 0; i < PMKID_HASH_SIZE; i++) pmksa->pmkid[i] = NULL; - os_free(pmksa); + os_free_loose(pmksa); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/sta_info.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/sta_info.c index 8b470c851e83a95a5b08fe92d1e327e7ef101e7f..a6951d32a900f4c8e55d60f52ec3a26406be08de 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/sta_info.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/sta_info.c @@ -282,10 +282,10 @@ void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta) } #endif /* CONFIG_NO_VLAN */ - os_free(sta->challenge); + os_free_loose(sta->challenge); #ifdef CONFIG_IEEE80211W - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); #endif /* CONFIG_IEEE80211W */ @@ -296,21 +296,21 @@ void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta) wpabuf_free(sta->wps_ie); wpabuf_free(sta->p2p_ie); - os_free(sta->ht_capabilities); - os_free(sta->vht_capabilities); + os_free_loose(sta->ht_capabilities); + os_free_loose(sta->vht_capabilities); hostapd_free_psk_list(sta->psk); #ifdef CONFIG_SAE sae_clear_data(sta->sae); - os_free(sta->sae); + os_free_loose(sta->sae); #endif /* CONFIG_SAE */ #ifdef CONFIG_MBO mbo_ap_sta_free(sta); #endif - os_free(sta->supp_op_classes); + os_free_loose(sta->supp_op_classes); - os_free(sta); + os_free_loose(sta); } @@ -390,6 +390,7 @@ void ap_handle_timer(void *eloop_ctx, void *timeout_ctx) MAC2STR(sta->addr)); /* Avoid sending client probe on removed client */ + os_kprintf("%s ,%d\r\n", __FUNCTION__, __LINE__); sta->timeout_next = STA_DISASSOC; goto skip_poll; } else if (inactive_sec < hapd->conf->ap_max_inactivity) { @@ -409,7 +410,7 @@ void ap_handle_timer(void *eloop_ctx, void *timeout_ctx) "inactive too long: %d sec, max allowed: %d", MAC2STR(sta->addr), inactive_sec, hapd->conf->ap_max_inactivity); - + os_kprintf("%s ,%d\r\n", __FUNCTION__, __LINE__); if (hapd->conf->skip_inactivity_poll) sta->timeout_next = STA_DISASSOC; } @@ -466,6 +467,7 @@ skip_poll: switch (sta->timeout_next) { case STA_NULLFUNC: + os_kprintf("%s ,%d\r\n", __FUNCTION__, __LINE__); sta->timeout_next = STA_DISASSOC; wpa_printf(MSG_DEBUG, "%s: register ap_handle_timer timeout " "for " MACSTR " (%d seconds - AP_DISASSOC_DELAY)", @@ -621,7 +623,7 @@ struct sta_info * ap_sta_add(struct hostapd_data *hapd, const u8 *addr) sta->acct_interim_interval = hapd->conf->acct_interim_interval; #endif if (accounting_sta_get_id(hapd, sta) < 0) { - os_free(sta); + os_free_loose(sta); return NULL; } @@ -995,7 +997,7 @@ int ap_check_sa_query_timeout(struct hostapd_data *hapd, struct sta_info *sta) HOSTAPD_LEVEL_DEBUG, "association SA Query timed out"); sta->sa_query_timed_out = 1; - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); sta->sa_query_trans_id = NULL; sta->sa_query_count = 0; eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); @@ -1066,7 +1068,7 @@ void ap_sta_start_sa_query(struct hostapd_data *hapd, struct sta_info *sta) void ap_sta_stop_sa_query(struct hostapd_data *hapd, struct sta_info *sta) { eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); sta->sa_query_trans_id = NULL; sta->sa_query_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth.c index 392fdc10df1e519cb848a1d04bb902a726f84ca7..48a9dd7e2fec5197b9f7afd3073bb28fac4ae083 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth.c @@ -128,6 +128,7 @@ static inline int wpa_auth_set_key(struct wpa_authenticator *wpa_auth, { if (wpa_auth->cb.set_key == NULL) return -1; + return wpa_auth->cb.set_key(wpa_auth->cb.ctx, vlan_id, alg, addr, idx, key, key_len); } @@ -214,7 +215,7 @@ void wpa_auth_vlogger(struct wpa_authenticator *wpa_auth, const u8 *addr, wpa_auth_logger(wpa_auth, addr, level, format); - os_free(format); + os_free_loose(format); } #endif @@ -381,7 +382,7 @@ static struct wpa_group * wpa_group_init(struct wpa_authenticator *wpa_auth, if (wpa_group_init_gmk_and_counter(wpa_auth, group) < 0) { wpa_printf(MSG_ERROR, "Failed to get random data for WPA " "initialization."); - os_free(group); + os_free_loose(group); return NULL; } @@ -422,14 +423,14 @@ struct wpa_authenticator * wpa_init(const u8 *addr, if (wpa_auth_gen_wpa_ie(wpa_auth)) { wpa_printf(MSG_ERROR, "Could not generate WPA IE."); - os_free(wpa_auth); + os_free_loose(wpa_auth); return NULL; } wpa_auth->group = wpa_group_init(wpa_auth, 0, 1); if (wpa_auth->group == NULL) { - os_free(wpa_auth->wpa_ie); - os_free(wpa_auth); + os_free_loose(wpa_auth->wpa_ie); + os_free_loose(wpa_auth); return NULL; } @@ -437,9 +438,9 @@ struct wpa_authenticator * wpa_init(const u8 *addr, wpa_auth); if (wpa_auth->pmksa == NULL) { wpa_printf(MSG_ERROR, "PMKSA cache initialization failed."); - os_free(wpa_auth->group); - os_free(wpa_auth->wpa_ie); - os_free(wpa_auth); + os_free_loose(wpa_auth->group); + os_free_loose(wpa_auth->wpa_ie); + os_free_loose(wpa_auth); return NULL; } @@ -447,10 +448,10 @@ struct wpa_authenticator * wpa_init(const u8 *addr, wpa_auth->ft_pmk_cache = wpa_ft_pmk_cache_init(); if (wpa_auth->ft_pmk_cache == NULL) { wpa_printf(MSG_ERROR, "FT PMK cache initialization failed."); - os_free(wpa_auth->group); - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->group); + os_free_loose(wpa_auth->wpa_ie); pmksa_cache_auth_deinit(wpa_auth->pmksa); - os_free(wpa_auth); + os_free_loose(wpa_auth); return NULL; } #endif /* CONFIG_IEEE80211R */ @@ -523,16 +524,16 @@ void wpa_deinit(struct wpa_authenticator *wpa_auth) #endif /* CONFIG_P2P */ - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->wpa_ie); group = wpa_auth->group; while (group) { prev = group; group = group->next; - os_free(prev); + os_free_loose(prev); } - os_free(wpa_auth); + os_free_loose(wpa_auth); } @@ -661,13 +662,13 @@ static void wpa_free_sta_sm(struct wpa_state_machine *sm) sm->GUpdateStationKeys = FALSE; } #ifdef CONFIG_IEEE80211R - os_free(sm->assoc_resp_ftie); + os_free_loose(sm->assoc_resp_ftie); wpabuf_free(sm->ft_pending_req_ies); #endif /* CONFIG_IEEE80211R */ - os_free(sm->last_rx_eapol_key); - os_free(sm->wpa_ie); + os_free_loose(sm->last_rx_eapol_key); + os_free_loose(sm->wpa_ie); wpa_group_put(sm->wpa_auth, sm->group); - os_free(sm); + os_free_loose(sm); } @@ -1339,7 +1340,7 @@ continue_processing: } #endif /* CONFIG_PEERKEY */ - os_free(sm->last_rx_eapol_key); + os_free_loose(sm->last_rx_eapol_key); sm->last_rx_eapol_key = os_malloc(data_len); if (sm->last_rx_eapol_key == NULL) return; @@ -1514,7 +1515,7 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, } else if (encr && kde) { buf = os_zalloc(key_data_len); if (buf == NULL) { - os_free(hdr); + os_free_loose(hdr); return; } pos = buf; @@ -1532,8 +1533,8 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, version == WPA_KEY_INFO_TYPE_AES_128_CMAC) { if (aes_wrap(sm->PTK.kek, sm->PTK.kek_len, (key_data_len - 8) / 8, buf, key_data)) { - os_free(hdr); - os_free(buf); + os_free_loose(hdr); + os_free_loose(buf); return; } if (mic_len == 24) @@ -1560,11 +1561,11 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, key_data_len); #endif /* CONFIG_NO_RC4 */ } else { - os_free(hdr); - os_free(buf); + os_free_loose(hdr); + os_free_loose(buf); return; } - os_free(buf); + os_free_loose(buf); } if (key_info & WPA_KEY_INFO_MIC) { @@ -1574,7 +1575,7 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, wpa_auth_logger(wpa_auth, sm->addr, LOGGER_DEBUG, "PTK not valid when sending EAPOL-Key " "frame"); - os_free(hdr); + os_free_loose(hdr); return; } @@ -1588,7 +1589,7 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, 1); wpa_auth_send_eapol(wpa_auth, sm->addr, (u8 *) hdr, len, sm->pairwise_set); - os_free(hdr); + os_free_loose(hdr); } @@ -2309,7 +2310,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) if (res < 0) { wpa_printf(MSG_ERROR, "FT: Failed to insert " "PMKR1Name into RSN IE in EAPOL-Key data"); - os_free(kde); + os_free_loose(kde); return; } pos -= wpa_ie_len; @@ -2346,7 +2347,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) if (res < 0) { wpa_printf(MSG_ERROR, "FT: Failed to insert FTIE " "into EAPOL-Key Key Data"); - os_free(kde); + os_free_loose(kde); return; } pos += res; @@ -2382,7 +2383,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) WPA_KEY_INFO_ACK | WPA_KEY_INFO_INSTALL | WPA_KEY_INFO_KEY_TYPE, _rsc, sm->ANonce, kde, pos - kde, keyidx, encr); - os_free(kde); + os_free_loose(kde); } @@ -2630,7 +2631,7 @@ SM_STATE(WPA_PTK_GROUP, REKEYNEGOTIATING) (!sm->Pair ? WPA_KEY_INFO_INSTALL : 0), rsc, gsm->GNonce, kde, kde_len, gsm->GN, 1); - os_free(kde_buf); + os_free_loose(kde_buf); } @@ -3287,7 +3288,7 @@ static void wpa_group_free(struct wpa_authenticator *wpa_auth, if (prev->next == group) { /* This never frees the special first group as needed */ prev->next = group->next; - os_free(group); + os_free_loose(group); break; } prev = prev->next; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_glue.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_glue.c index d0e43b3ac4f3754986ea1339983b6a008f394bf6..2944482fb20154853d1542f392a10505204ae4b9 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_glue.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_glue.c @@ -349,7 +349,7 @@ static int hostapd_wpa_auth_send_eapol(void *ctx, const u8 *addr, wpa_snprintf_hex(hex, hex_len, data, data_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(addr), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -471,7 +471,7 @@ static int hostapd_wpa_auth_send_ether(void *ctx, const u8 *dst, u16 proto, wpa_snprintf_hex(hex, hex_len, data, data_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(dst), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -509,7 +509,7 @@ static int hostapd_wpa_auth_send_ether(void *ctx, const u8 *dst, u16 proto, os_memcpy(buf + 1, data, data_len); ret = l2_packet_send(hapd->l2, dst, proto, (u8 *) buf, sizeof(*buf) + data_len); - os_free(buf); + os_free_loose(buf); return ret; } @@ -541,7 +541,7 @@ static int hostapd_wpa_auth_send_ft_action(void *ctx, const u8 *dst, os_memcpy(&m->u, data, data_len); res = hostapd_drv_send_mlme(hapd, (u8 *) m, mlen, 0); - os_free(m); + os_free_loose(m); return res; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_ie.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_ie.c index b415fa5a7d5b4ddac2e2d305d4cefb7ffb63762d..a532f115c8854ddb22dcebb04ccf2b8a97a4576c 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_ie.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/ap/wpa_auth_ie.c @@ -345,7 +345,7 @@ int wpa_auth_gen_wpa_ie(struct wpa_authenticator *wpa_auth) pos += res; } - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->wpa_ie); wpa_auth->wpa_ie = os_malloc(pos - buf); if (wpa_auth->wpa_ie == NULL) return -1; @@ -598,7 +598,7 @@ int wpa_validate_wpa_ie(struct wpa_authenticator *wpa_auth, } if (sm->wpa_ie == NULL || sm->wpa_ie_len < wpa_ie_len) { - os_free(sm->wpa_ie); + os_free_loose(sm->wpa_ie); sm->wpa_ie = os_malloc(wpa_ie_len); if (sm->wpa_ie == NULL) return WPA_ALLOC_FAIL; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/notifier.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/notifier.c index f3da2eeb454d7b2716149593b83e3d092b4c4373..b436f6223ade8d610f94e8920d710b8bf83f6a76 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/notifier.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/notifier.c @@ -40,7 +40,7 @@ void remove_notifier(struct notifier **notif, notify_func func, void *arg) for (; (np = *notif) != 0; notif = &np->next) { if (np->func == func && np->arg == arg) { *notif = np->next; - os_free(np); + os_free_loose(np); break; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/sae.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/sae.c index 02a15d2ac9e82c1b4a1a496bccba8da76ef59b77..3646146a9a6ce8a1683ba4e3700022b3a5929dc6 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/sae.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/sae.c @@ -159,7 +159,7 @@ static struct crypto_bignum * sae_get_rand(struct sae_data *sae) os_memset(val, 0, order_len); out: #ifdef CONFIG_SAE_SMALL_STACK - os_free(val); + os_free_loose(val); #endif return bn; } @@ -870,14 +870,14 @@ int sae_process_commit(struct sae_data *sae) (sae->tmp->dh && sae_derive_k_ffc(sae, k) < 0) || sae_derive_keys(sae, k) < 0) { #ifdef CONFIG_SAE_SMALL_STACK - os_free(k); + os_free_loose(k); #endif return -1; } bk_printf("%s: after %d %d\n", __func__, xPortGetFreeHeapSize(), xPortGetMinimumEverFreeHeapSize()); #ifdef CONFIG_SAE_SMALL_STACK - os_free(k); + os_free_loose(k); #endif return 0; } @@ -1204,8 +1204,8 @@ static void sae_cn_confirm(struct sae_data *sae, const u8 *sc, scalar_b1 = os_malloc(SAE_MAX_PRIME_LEN); scalar_b2 = os_malloc(SAE_MAX_PRIME_LEN); if (!scalar_b1 || !scalar_b2) { - os_free(scalar_b1); - os_free(scalar_b2); + os_free_loose(scalar_b1); + os_free_loose(scalar_b2); return; } #else @@ -1237,8 +1237,8 @@ static void sae_cn_confirm(struct sae_data *sae, const u8 *sc, hmac_sha256_vector(sae->tmp->kck, sizeof(sae->tmp->kck), 5, addr, len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(scalar_b1); - os_free(scalar_b2); + os_free_loose(scalar_b1); + os_free_loose(scalar_b2); #endif } @@ -1256,8 +1256,8 @@ static void sae_cn_confirm_ecc(struct sae_data *sae, const u8 *sc, element_b1 = os_malloc(2 * SAE_MAX_ECC_PRIME_LEN); element_b2 = os_malloc(2 * SAE_MAX_ECC_PRIME_LEN); if (!element_b1 || !element_b2) { - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); return; } #else @@ -1273,8 +1273,8 @@ static void sae_cn_confirm_ecc(struct sae_data *sae, const u8 *sc, sae_cn_confirm(sae, sc, scalar1, element_b1, 2 * sae->tmp->prime_len, scalar2, element_b2, 2 * sae->tmp->prime_len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); #endif } @@ -1292,8 +1292,8 @@ static void sae_cn_confirm_ffc(struct sae_data *sae, const u8 *sc, element_b1 = os_malloc(SAE_MAX_PRIME_LEN); element_b2 = os_malloc(SAE_MAX_PRIME_LEN); if (!element_b1 || !element_b2) { - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); return; } #else @@ -1309,8 +1309,8 @@ static void sae_cn_confirm_ffc(struct sae_data *sae, const u8 *sc, sae_cn_confirm(sae, sc, scalar1, element_b1, sae->tmp->prime_len, scalar2, element_b2, sae->tmp->prime_len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); #endif } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_common.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_common.c index f3fc0945b10dcda1f9ba3b8a24c28f183faee413..db2ec6f4d3f7c795435ccbd80c40fa006722eea4 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_common.c @@ -1112,7 +1112,7 @@ int wpa_parse_cipher(const char *value) else if (os_strcmp(start, "GTK_NOT_USED") == 0) val |= WPA_CIPHER_GTK_NOT_USED; else { - os_free(buf); + os_free_loose(buf); return -1; } @@ -1120,7 +1120,7 @@ int wpa_parse_cipher(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); return val; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_psk_cache.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_psk_cache.c index b6a5db3a3ea19b34661f283e940d81971d7e447d..7d3bb3b7e4ec6c74d81cca12ed4b1f080d85aa75 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_psk_cache.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/common/wpa_psk_cache.c @@ -31,8 +31,8 @@ static void wpa_psk_cache_expire(struct wpa_psk_cache *cache) while (dl_list_len(&cache->all) > WPA_PSK_ENTRIES) { item = dl_list_first(&cache->all, struct wpa_psk_cache_item, node); dl_list_del(&item->node); // delete first entry - os_free(item->passphrase); - os_free(item->ssid); + os_free_loose(item->passphrase); + os_free_loose(item->ssid); os_printf("vanish one\n"); } } @@ -126,9 +126,9 @@ static int ___wpa_psk_cache_add(struct wpa_psk_cache *cache, item->ssid_len = ssid_len; item->passphrase = os_strdup(passphrase); if (!item->ssid || !item->passphrase) { - os_free(item->ssid); - os_free(item->passphrase); - os_free(item); + os_free_loose(item->ssid); + os_free_loose(item->passphrase); + os_free_loose(item); goto out; } @@ -308,8 +308,8 @@ int wpa_psk_request(u8 *ssid, size_t ssid_len, char *passphrase, u8 *psk, size_t } /* a new request */ - os_free(cache->item.ssid); - os_free(cache->item.passphrase); + os_free_loose(cache->item.ssid); + os_free_loose(cache->item.passphrase); if (os_strlen(passphrase) == 2 * PMK_LEN) { /* passphrase is hex string of psk, convert it to binary */ @@ -356,8 +356,8 @@ void wpa_psk_cal_thread(void *arg) rtos_set_semaphore(&cache->sema); if (!ssid || !passphrase) { - os_free(ssid); - os_free(passphrase); + os_free_loose(ssid); + os_free_loose(passphrase); GLOBAL_INT_DISABLE(); wpa_pskcalc_thread_handle = 0; GLOBAL_INT_RESTORE(); @@ -382,8 +382,8 @@ void wpa_psk_cal_thread(void *arg) } rtos_set_semaphore(&cache->sema); - os_free(ssid); - os_free(passphrase); + os_free_loose(ssid); + os_free_loose(passphrase); if (done) break; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-dec.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-dec.c index d0daae3eef59f977863157c0137f5edaec155ce6..715a7d2f92680df6fe0531419fec16d47d6caa2d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-dec.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-dec.c @@ -66,7 +66,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) return NULL; res = rijndaelKeySetupDec(rk, key, len * 8); if (res < 0) { - os_free(rk); + os_free_loose(rk); return NULL; } rk[AES_PRIV_NR_POS] = res; @@ -158,6 +158,6 @@ void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { os_memset(ctx, 0, AES_PRIV_SIZE); - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-enc.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-enc.c index 365991887705210d7038f67b5e6fc715c2c67fe6..349dfce9a8143d69e95d95da994f9a1e392a2411 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-enc.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/aes-internal-enc.c @@ -105,7 +105,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) return NULL; res = rijndaelKeySetupEnc(rk, key, len * 8); if (res < 0) { - os_free(rk); + os_free_loose(rk); return NULL; } rk[AES_PRIV_NR_POS] = res; @@ -123,6 +123,6 @@ void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { os_memset(ctx, 0, AES_PRIV_SIZE); - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_ali.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_ali.c index 38ce15d03570c8d7cda5673aa357f2f43c9873b7..95efc8bbd573efed27feb1d693053c04684debb0 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_ali.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_ali.c @@ -29,7 +29,7 @@ void des_encrypt(const u8 *clear, const u8 *key, u8 *cypher) ali_des_init(DES_ECB, true, key, 64, NULL, context); ali_des_process(clear, cypher, 8, context); - os_free(context); + os_free_loose(context); } @@ -53,7 +53,7 @@ int md5_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac) } ali_hash_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -78,7 +78,7 @@ int sha1_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac) } ali_hash_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -102,7 +102,7 @@ int hmac_sha1_vector(const u8 *key, size_t key_len, size_t num_elem, } ali_hmac_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -135,7 +135,7 @@ int hmac_md5_vector(const u8 *key, size_t key_len, size_t num_elem, } ali_hmac_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -164,7 +164,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) len, NULL, context); if (ret != 0) { - os_free(context); + os_free_loose(context); return NULL; } return context; @@ -177,7 +177,7 @@ void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } void * aes_decrypt_init(const u8 *key, size_t len) @@ -198,7 +198,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) len, NULL, context); if (ret != 0) { - os_free(context); + os_free_loose(context); return NULL; } return context; @@ -211,7 +211,7 @@ void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } #elif CFG_USE_MBEDTLS #include "mbedtls/platform.h" @@ -359,7 +359,7 @@ void *aes_encrypt_init(const u8 *key, size_t len) ret = mbedtls_aes_setkey_enc(aes, key, len * 8); if (ret != 0) { CRYPTO_DBG("%s:%d mbedtls_aes_setkey_enc failed\n", __FUNCTION__, __LINE__); - os_free(aes); + os_free_loose(aes); return NULL; } @@ -373,7 +373,7 @@ void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } void * aes_decrypt_init(const u8 *key, size_t len) @@ -391,7 +391,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) ret = mbedtls_aes_setkey_dec(aes, key, len * 8); if (ret != 0) { CRYPTO_DBG("%s:%d mbedtls_aes_setkey_dec failed\n", __FUNCTION__, __LINE__); - os_free(aes); + os_free_loose(aes); return NULL; } @@ -405,6 +405,6 @@ void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_wolfssl.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_wolfssl.c index c73a5b92c6c5e16ca09f4ee4c2a356eed119454d..7e397d3c92af7423daa698ce2c0960844001f25e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_wolfssl.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/crypto/crypto_wolfssl.c @@ -318,7 +318,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) return NULL; if (wc_AesSetKey(aes, key, len, NULL, AES_ENCRYPTION) < 0) { - os_free(aes); + os_free_loose(aes); return NULL; } @@ -335,7 +335,7 @@ int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } @@ -351,7 +351,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) return NULL; if (wc_AesSetKey(aes, key, len, NULL, AES_DECRYPTION) < 0) { - os_free(aes); + os_free_loose(aes); return NULL; } @@ -368,7 +368,7 @@ int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } @@ -507,14 +507,14 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, case 32: break; default: - os_free(ctx); + os_free_loose(ctx); return NULL; } if (wc_AesSetKey(&ctx->enc.aes, key, key_len, iv, AES_ENCRYPTION) || wc_AesSetKey(&ctx->dec.aes, key, key_len, iv, AES_DECRYPTION)) { - os_free(ctx); + os_free_loose(ctx); return NULL; } break; @@ -524,7 +524,7 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, if (key_len != DES3_KEYLEN || wc_Des3_SetKey(&ctx->enc.des3, key, iv, DES_ENCRYPTION) || wc_Des3_SetKey(&ctx->dec.des3, key, iv, DES_DECRYPTION)) { - os_free(ctx); + os_free_loose(ctx); return NULL; } break; @@ -532,7 +532,7 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, case CRYPTO_CIPHER_ALG_RC2: case CRYPTO_CIPHER_ALG_DES: default: - os_free(ctx); + os_free_loose(ctx); return NULL; } @@ -604,7 +604,7 @@ int crypto_cipher_decrypt(struct crypto_cipher *ctx, const u8 *crypt, void crypto_cipher_deinit(struct crypto_cipher *ctx) { - os_free(ctx); + os_free_loose(ctx); } #endif @@ -793,7 +793,7 @@ int crypto_dh_init(u8 generator, const u8 *prime, size_t prime_len, u8 *privkey, wc_InitDhKey(dh); if (wc_InitRng(&rng) != 0) { - os_free(dh); + os_free_loose(dh); return -1; } @@ -820,7 +820,7 @@ int crypto_dh_init(u8 generator, const u8 *prime, size_t prime_len, u8 *privkey, ret = 0; done: wc_FreeDhKey(dh); - os_free(dh); + os_free_loose(dh); wc_FreeRng(&rng); return ret; } @@ -852,7 +852,7 @@ int crypto_dh_derive_secret(u8 generator, const u8 *prime, size_t prime_len, ret = 0; done: wc_FreeDhKey(dh); - os_free(dh); + os_free_loose(dh); return ret; } @@ -922,7 +922,7 @@ struct crypto_hash * crypto_hash_init(enum crypto_hash_alg alg, const u8 *key, ret = hash; hash = NULL; done: - os_free(hash); + os_free_loose(hash); return ret; } @@ -1015,7 +1015,7 @@ struct crypto_bignum * crypto_bignum_init(void) a = os_malloc(sizeof(*a)); if (!a || mp_init(a) != MP_OKAY) { - os_free(a); + os_free_loose(a); a = NULL; } @@ -1035,7 +1035,7 @@ struct crypto_bignum * crypto_bignum_init_set(const u8 *buf, size_t len) return NULL; if (mp_read_unsigned_bin(a, buf, len) != MP_OKAY) { - os_free(a); + os_free_loose(a); a = NULL; } @@ -1051,7 +1051,7 @@ void crypto_bignum_deinit(struct crypto_bignum *n, int clear) if (clear) mp_forcezero((mp_int *) n); mp_clear((mp_int *) n); - os_free((mp_int *) n); + os_free_loose((mp_int *) n); } @@ -1347,7 +1347,7 @@ void crypto_ec_deinit(struct crypto_ec* e) mp_clear(&e->prime); mp_clear(&e->a); wc_ecc_free(&e->key); - os_free(e); + os_free_loose(e); } @@ -1626,7 +1626,7 @@ done: if (!calced) { if (y2) { mp_clear(y2); - os_free(y2); + os_free_loose(y2); } mp_clear(&t); } @@ -1701,7 +1701,7 @@ void crypto_ecdh_deinit(struct crypto_ecdh *ecdh) { if (ecdh) { crypto_ec_deinit(ecdh->ec); - os_free(ecdh); + os_free_loose(ecdh); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver.h b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver.h index f955ae915d9482e52b9cb1c4cb794d4650d25348..f97cd7e8a451921e08f745c9904de8c85061b9b1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver.h +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver.h @@ -355,7 +355,7 @@ struct wpa_driver_scan_params { * * The driver wrapper is allowed to take this allocated buffer into its * own use by setting the pointer to %NULL. In that case, the driver - * wrapper is responsible for freeing the buffer with os_free() once it + * wrapper is responsible for freeing the buffer with os_free_loose() once it * is not needed anymore. */ struct wpa_driver_scan_filter { @@ -4062,7 +4062,7 @@ enum wpa_event_type { * stored in struct survey_results. The results provide at most one * survey entry for each frequency and at minimum will provide one * survey entry for one frequency. The survey data can be os_malloc()'d - * and then os_free()'d, so the event callback must only copy data. + * and then os_free_loose()'d, so the event callback must only copy data. */ EVENT_SURVEY, diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_beken.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_beken.c index 4f532bd2908eabefc0a3e4f5e07206bfd4f5fd78..5734848d96121b6632a3e76f92f4eeb579366893 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_beken.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_beken.c @@ -237,7 +237,7 @@ static void handle_read(int sock, void *eloop_ctx, void *sock_ctx) read_exit: if(buf) { - os_free(buf); + os_free_loose(buf); } return; @@ -418,7 +418,7 @@ static int wpa_driver_hostap_set_key(const char *ifname, void *priv, break; default: os_printf("%s: unsupport alg %d\n", __func__, alg); - os_free(buf); + os_free_loose(buf); return -1; } param->u.crypt.flags = set_tx ? HOSTAP_CRYPT_FLAG_SET_TX_KEY : 0; @@ -432,7 +432,7 @@ static int wpa_driver_hostap_set_key(const char *ifname, void *priv, { ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } @@ -469,7 +469,7 @@ static int hostap_get_seqnum(const char *ifname, void *priv, const u8 *addr, { os_memcpy(seq, param->u.crypt.seq, 8); } - os_free(buf); + os_free_loose(buf); return ret; } @@ -753,7 +753,7 @@ static int hostapd_ioctl_set_generic_elem(struct hostap_driver_data *drv) param->u.generic_elem.data, elem_len); res = hostapd_ioctl(drv, param, blen); - os_free(param); + os_free_loose(param); return res; } @@ -764,7 +764,7 @@ static int hostap_set_generic_elem(void *priv, { struct hostap_driver_data *drv = priv; - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; drv->generic_ie_len = 0; if (elem) @@ -792,7 +792,7 @@ static int hostap_set_ap_wps_ie(void *priv, const struct wpabuf *beacon, * more information. */ - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; drv->wps_ie_len = 0; if (proberesp) @@ -895,7 +895,7 @@ static void hostapd_wireless_event_wireless(struct hostap_driver_data *drv, buf[iwe->u.data.length] = '\0'; hostapd_wireless_event_wireless_custom(drv, buf); - os_free(buf); + os_free_loose(buf); break; } @@ -960,7 +960,7 @@ static int hostap_get_we_version(struct hostap_driver_data *drv) if (ioctl_inet(drv->ioctl_sock, drv->vif_index, SIOCGIWRANGE, (unsigned long)&iwr) < 0) { - os_free(range); + os_free_loose(range); return -1; } else if (iwr.u.data.length >= minlen && @@ -969,7 +969,7 @@ static int hostap_get_we_version(struct hostap_driver_data *drv) drv->we_version = range->we_version_compiled; } - os_free(range); + os_free_loose(range); return 0; } @@ -988,7 +988,7 @@ static int hostap_wireless_event_init(struct hostap_driver_data *drv) drv->netlink = 0; if (drv->netlink == NULL) { - os_free(cfg); + os_free_loose(cfg); } return 0; @@ -1016,7 +1016,7 @@ static void *hostap_init(struct hostapd_data *hapd, ret = wpa_driver_hostap_init_vif(drv, NL80211_IFTYPE_AP); if(ret || (drv->vif_index == 0xff)) { os_printf("Could not found vif indix: %d\n", drv->vif_index); - os_free(drv); + os_free_loose(drv); return NULL; } @@ -1028,7 +1028,7 @@ static void *hostap_init(struct hostapd_data *hapd, drv->iface); fsocket_close(drv->ioctl_sock); - os_free(drv); + os_free_loose(drv); drv = NULL; return NULL; @@ -1044,7 +1044,7 @@ static void *hostap_init(struct hostapd_data *hapd, hostap_wireless_event_init(drv)) { fsocket_close(drv->ioctl_sock); - os_free(drv); + os_free_loose(drv); drv = NULL; return NULL; @@ -1082,13 +1082,13 @@ static void hostap_driver_deinit(void *priv) l2_packet_deinit(drv->sock_xmit); drv->sock_xmit = NULL; - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; - os_free(drv); + os_free_loose(drv); drv = NULL; } @@ -1144,7 +1144,7 @@ int hostap_channel_switch(void *priv, struct csa_settings *settings) if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } @@ -1157,11 +1157,11 @@ int hostap_channel_switch(void *priv, struct csa_settings *settings) param->u.reg_csa_event.arg = (void *)SIGCSA; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } - os_free(buf); + os_free_loose(buf); return 0; } @@ -1237,9 +1237,9 @@ static struct hostapd_hw_modes *hostap_get_hw_feature_data(void *priv, mode->channels = os_zalloc(clen); mode->rates = os_zalloc(rlen); if (mode->channels == NULL || mode->rates == NULL) { - os_free(mode->channels); - os_free(mode->rates); - os_free(mode); + os_free_loose(mode->channels); + os_free_loose(mode->rates); + os_free_loose(mode); return NULL; } @@ -1318,7 +1318,7 @@ int hostap_set_ap(void *priv, struct wpa_driver_ap_params *params) ret = hostapd_ioctl(drv, ¶m, sizeof(param)); - os_free(beacon); + os_free_loose(beacon); return ret; } @@ -1426,7 +1426,7 @@ static void *wpa_driver_init(void *ctx, const char *ifname) ret = wpa_driver_hostap_init_vif(drv, NL80211_IFTYPE_STATION); if(ret || (drv->vif_index == 0xff)) { os_printf("Could not found vif indix: %d\n", drv->vif_index); - os_free(drv); + os_free_loose(drv); return NULL; } @@ -1469,13 +1469,13 @@ static void wpa_driver_deinit(void *priv) fsocket_close(drv->sock); } - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; - os_free(drv); + os_free_loose(drv); drv = NULL; } @@ -1551,7 +1551,7 @@ int wpa_driver_scan2(void *priv, struct wpa_driver_scan_params *params) ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } @@ -1596,26 +1596,26 @@ struct wpa_scan_results *wpa_driver_get_scan_results2(void *priv) if(!ret) { - os_free(buf); + os_free_loose(buf); return results; } fail_result: if(results && results->res) { - os_free(results->res); + os_free_loose(results->res); results->res = NULL; } if(results) { - os_free(results); + os_free_loose(results); results = NULL; } if(buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -1709,7 +1709,7 @@ int wpa_driver_associate(void *priv, struct wpa_driver_associate_params *params) ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } @@ -1733,11 +1733,11 @@ int wpa_driver_get_bssid(void *priv, u8 *bssid) param->vif_idx = drv->vif_index; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } os_memcpy(bssid, param->u.bss_info.bssid, ETH_ALEN); - os_free(buf); + os_free_loose(buf); return 0; } @@ -1761,13 +1761,13 @@ int wpa_driver_get_ssid(void *priv, u8 *ssid) param->vif_idx = drv->vif_index; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } len = MIN(SSID_MAX_LEN, os_strlen((char *)param->u.bss_info.ssid)); os_memcpy(ssid, param->u.bss_info.ssid, len); - os_free(buf); + os_free_loose(buf); return len; } @@ -1819,7 +1819,7 @@ int wpa_driver_set_operstate(void *priv, int state) if(hostapd_ioctl(drv, param, blen)) { ret = -1; } - os_free(buf); + os_free_loose(buf); #endif return ret; @@ -1880,7 +1880,7 @@ int wpa_driver_authenticate(void *priv, struct wpa_driver_auth_params *params) if (hostapd_ioctl(drv, param, blen)) ret = -1; - os_free(buf); + os_free_loose(buf); return ret; } @@ -1954,7 +1954,7 @@ int wpa_driver_send_action(void *priv, unsigned int freq, unsigned int wait, res = fsocket_send(drv->sock, buf, total_len, type_ptr); - os_free(buf); + os_free_loose(buf); return res; } @@ -1984,7 +1984,7 @@ int wpa_driver_deauthenticate(void *priv, const u8 *addr, int reason_code) ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_common.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_common.c index 91189ebe8f85346ce9bb774581aa51c6ddb9dfc3..1381f959efc9987f90b3d5ceca4529af76e612be 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/drivers/driver_common.c @@ -19,14 +19,14 @@ void wpa_scan_results_free(struct wpa_scan_results *res) for (i = 0; i < res->num; i++) { - os_free(res->res[i]); + os_free_loose(res->res[i]); res->res[i] = 0; } - os_free(res->res); + os_free_loose(res->res); res->res = 0; - os_free(res); + os_free_loose(res); res = 0; } @@ -210,7 +210,7 @@ wpa_get_wowlan_triggers(const char *wowlan_triggers, wpa_printf(MSG_DEBUG, "Unknown/unsupported wowlan trigger '%s'", start); - os_free(triggers); + os_free_loose(triggers); triggers = NULL; goto out; } @@ -222,6 +222,6 @@ wpa_get_wowlan_triggers(const char *wowlan_triggers, #undef CHECK_TRIGGER out: - os_free(buf); + os_free_loose(buf); return triggers; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/eapol_supp/eapol_supp_sm.h b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/eapol_supp/eapol_supp_sm.h index 0433881a7d25361e8d9e1dbb6587481c68bc4292..aff1d4031523cf42eb70dbb2eea665fb55d9ec31 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/eapol_supp/eapol_supp_sm.h +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/eapol_supp/eapol_supp_sm.h @@ -313,7 +313,7 @@ int eapol_sm_get_eap_proxy_imsi(struct eapol_sm *sm, char *imsi, size_t *len); #else /* IEEE8021X_EAPOL */ static inline struct eapol_sm *eapol_sm_init(struct eapol_ctx *ctx) { - os_free(ctx); + os_free_loose(ctx); return (struct eapol_sm *) 1; } static inline void eapol_sm_deinit(struct eapol_sm *sm) diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/l2_packet/l2_packet_none.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/l2_packet/l2_packet_none.c index 6092824cf2e83ad84a48110b00dfb475e81fc3e8..bcf23c3ed91c242556eaa9d8eae1393a5e654c85 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/l2_packet/l2_packet_none.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/l2_packet/l2_packet_none.c @@ -54,7 +54,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, if(!type_ptr) { ret = -1; if(type_ptr){ - os_free(type_ptr); + os_free_loose(type_ptr); } goto send_exit; } @@ -83,6 +83,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, } fsocket_send(l2->fd, data_buf, data_len, type_ptr); if (sync) { + os_printf("%s %d\r\n", __FUNCTION__, __LINE__); ret = rtos_get_semaphore(&cb.sema, 5*1000 /*BEKEN_NEVER_TIMEOUT*/); if (ret != kNoErr) { os_printf("%s: send failed\r\n", __func__); @@ -94,7 +95,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, send_exit: if(data_buf){ - os_free(data_buf); + os_free_loose(data_buf); } return ret; @@ -139,7 +140,7 @@ static void l2_packet_receive(int sock, void *eloop_ctx, void *sock_ctx) recv_exit: if(buf) { - os_free(buf); + os_free_loose(buf); } return; @@ -205,7 +206,7 @@ void l2_packet_deinit(struct l2_packet_data *l2) fsocket_close(l2->fd); } - os_free(l2); + os_free_loose(l2); l2 = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/pmksa_cache.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/pmksa_cache.c index 66bee693af7b5b4f3a4699024d53293d13bb6bd1..82adbf3a5e9000ed5e818ac7ac6b6cd109b93984 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/pmksa_cache.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/pmksa_cache.c @@ -171,7 +171,7 @@ pmksa_cache_add(struct rsn_pmksa_cache *pmksa, const u8 *pmk, size_t pmk_len, PMKID_LEN) == 0) { wpa_printf(MSG_DEBUG, "WPA: reusing previous " "PMKSA entry"); - os_free(entry); + os_free_loose(entry); return pos; } if (prev == NULL) @@ -307,10 +307,10 @@ void pmksa_cache_deinit(struct rsn_pmksa_cache *pmksa) while (entry) { prev = entry; entry = entry->next; - os_free(prev); + os_free_loose(prev); } pmksa_cache_set_expiration(pmksa); - os_free(pmksa); + os_free_loose(pmksa); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa.c index b6d4cd03bb7584d3fc9468e37147e98f7c908f21..e3d6270372d49a2499bbef239a0e955374b8b966 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa.c @@ -79,7 +79,7 @@ int wpa_eapol_key_send(struct wpa_sm *sm, const u8 *kck, size_t kck_len, ret = wpa_sm_ether_send(sm, dest, proto, msg, msg_len); eapol_sm_notify_tx_eapol_key(sm->eapol); out: - os_free(msg); + os_free_loose(msg); return ret; } @@ -296,7 +296,7 @@ static int wpa_supplicant_get_pmk(struct wpa_sm *sm, if (buf) { wpa_sm_ether_send(sm, sm->bssid, ETH_P_EAPOL, buf, buflen); - os_free(buf); + os_free_loose(buf); return -2; } @@ -344,7 +344,7 @@ int wpa_supplicant_send_2_of_4(struct wpa_sm *sm, const unsigned char *dst, NULL, hdrlen + wpa_ie_len, &rlen, (void *) &reply); if (rbuf == NULL) { - os_free(rsn_ie_buf); + os_free_loose(rsn_ie_buf); return -1; } reply192 = (struct wpa_eapol_key_192 *) reply; @@ -371,7 +371,7 @@ int wpa_supplicant_send_2_of_4(struct wpa_sm *sm, const unsigned char *dst, WPA_PUT_BE16(reply->key_data_length, wpa_ie_len); os_memcpy(reply + 1, wpa_ie, wpa_ie_len); } - os_free(rsn_ie_buf); + os_free_loose(rsn_ie_buf); os_memcpy(reply->key_nonce, nonce, WPA_NONCE_LEN); @@ -489,12 +489,12 @@ static void wpa_supplicant_process_1_of_4(struct wpa_sm *sm, kde, kde_len, ptk) < 0) goto failed; - os_free(kde_buf); + os_free_loose(kde_buf); os_memcpy(sm->anonce, key->key_nonce, WPA_NONCE_LEN); return; failed: - os_free(kde_buf); + os_free_loose(kde_buf); wpa_sm_deauthenticate(sm, WLAN_REASON_UNSPECIFIED); } @@ -1989,7 +1989,7 @@ struct wpa_sm * wpa_sm_init(struct wpa_sm_ctx *ctx) if (sm->pmksa == NULL) { wpa_msg(sm->ctx->msg_ctx, MSG_ERROR, "RSN: PMKSA cache initialization failed"); - os_free(sm); + os_free_loose(sm); return NULL; } @@ -2008,16 +2008,16 @@ void wpa_sm_deinit(struct wpa_sm *sm) pmksa_cache_deinit(sm->pmksa); eloop_cancel_timeout(wpa_sm_start_preauth, sm, NULL); eloop_cancel_timeout(wpa_sm_rekey_ptk, sm, NULL); - os_free(sm->assoc_wpa_ie); - os_free(sm->ap_wpa_ie); - os_free(sm->ap_rsn_ie); + os_free_loose(sm->assoc_wpa_ie); + os_free_loose(sm->ap_wpa_ie); + os_free_loose(sm->ap_rsn_ie); wpa_sm_drop_sa(sm); - os_free(sm->ctx); + os_free_loose(sm->ctx); peerkey_deinit(sm); #ifdef CONFIG_IEEE80211R - os_free(sm->assoc_resp_ies); + os_free_loose(sm->assoc_resp_ies); #endif /* CONFIG_IEEE80211R */ - os_free(sm); + os_free_loose(sm); } @@ -2446,7 +2446,7 @@ int wpa_sm_set_assoc_wpa_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->assoc_wpa_ie); + os_free_loose(sm->assoc_wpa_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing own WPA/RSN IE"); @@ -2481,7 +2481,7 @@ int wpa_sm_set_ap_wpa_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->ap_wpa_ie); + os_free_loose(sm->ap_wpa_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing AP WPA IE"); @@ -2516,7 +2516,7 @@ int wpa_sm_set_ap_rsn_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->ap_rsn_ie); + os_free_loose(sm->ap_rsn_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing AP RSN IE"); diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa_i.h b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa_i.h index b8e73343399a9ac1c17b3942dbdc7f3c9a15f90b..9e4e48abc4a333548e5a4248f176f1ec0c0f0e39 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa_i.h +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/rsn_supp/wpa_i.h @@ -146,6 +146,9 @@ static inline int wpa_sm_set_key(struct wpa_sm *sm, enum wpa_alg alg, const u8 *key, size_t key_len) { WPA_ASSERT(sm->ctx->set_key); + + os_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + return sm->ctx->set_key(sm->ctx->ctx, alg, addr, key_idx, set_tx, seq, seq_len, key, key_len); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/common.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/common.c index 6f2e4cc550c3dd565d4c2c48a795fedf1115a95b..e842ece41b72c353f6b4417ba0efcb7a1d3b944a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/common.c @@ -657,12 +657,12 @@ char * wpa_config_parse_string(const char *value, size_t *len) str = os_malloc(tlen + 1); if (str == NULL) { - os_free(tstr); + os_free_loose(tstr); return NULL; } *len = printf_decode((u8 *) str, tlen + 1, tstr); - os_free(tstr); + os_free_loose(tstr); return str; } else { @@ -675,7 +675,7 @@ char * wpa_config_parse_string(const char *value, size_t *len) if (str == NULL) return NULL; if (hexstr2bin(value, str, tlen)) { - os_free(str); + os_free_loose(str); return NULL; } str[tlen] = '\0'; @@ -783,7 +783,7 @@ int freq_range_list_parse(struct wpa_freq_range_list *res, const char *value) n = os_realloc_array(freq, count + 1, sizeof(struct wpa_freq_range)); if (n == NULL) { - os_free(freq); + os_free_loose(freq); return -1; } freq = n; @@ -801,7 +801,7 @@ int freq_range_list_parse(struct wpa_freq_range_list *res, const char *value) count++; } - os_free(res->range); + os_free_loose(res->range); res->range = freq; res->num = count; @@ -854,7 +854,7 @@ char * freq_range_list_str(const struct wpa_freq_range_list *list) i == 0 ? "" : ",", range->min, range->max); if (os_snprintf_error(end - pos, res)) { - os_free(buf); + os_free_loose(buf); return NULL; } pos += res; @@ -883,7 +883,7 @@ void int_array_concat(int **res, const int *a) n = os_realloc_array(*res, reslen + alen + 1, sizeof(int)); if (n == NULL) { - os_free(*res); + os_free_loose(*res); *res = NULL; return; } @@ -944,7 +944,7 @@ void int_array_add_unique(int **res, int a) n = os_realloc_array(*res, reslen + 2, sizeof(int)); if (n == NULL) { - os_free(*res); + os_free_loose(*res); *res = NULL; return; } @@ -961,7 +961,7 @@ void str_clear_free(char *str) if (str) { size_t len = os_strlen(str); os_memset(str, 0, len); - os_free(str); + os_free_loose(str); } } @@ -970,7 +970,7 @@ void bin_clear_free(void *bin, size_t len) { if (bin) { os_memset(bin, 0, len); - os_free(bin); + os_free_loose(bin); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/eloop.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/eloop.c index 979107221f0057742a5d19940ee571b8b6321c1f..abf18900c73213d92ba74ef3b364516d4c24e21a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/eloop.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/eloop.c @@ -130,7 +130,7 @@ static void eloop_sock_table_destroy(struct eloop_sock_table *table) wpa_trace_dump("eloop sock", &table->table[i]); } - os_free(table->table); + os_free_loose(table->table); } } @@ -206,7 +206,7 @@ int eloop_register_timeout(unsigned int secs, if (os_get_reltime(&timeout->time) < 0) { - os_free(timeout); + os_free_loose(timeout); os_printf("------------os_get_reltimeErr\r\n"); return -1; } @@ -219,7 +219,7 @@ int eloop_register_timeout(unsigned int secs, * to be infinite, i.e., the timeout would never happen. */ os_printf("------------ELOOP: Too long timeout\r\n"); - os_free(timeout); + os_free_loose(timeout); return 0; } @@ -246,7 +246,7 @@ int eloop_register_timeout(unsigned int secs, void eloop_remove_timeout(struct eloop_timeout *timeout) { dl_list_del(&timeout->list); - os_free(timeout); + os_free_loose(timeout); } int eloop_cancel_timeout(eloop_timeout_handler handler, @@ -793,7 +793,7 @@ void eloop_destroy(void) eloop_sock_table_destroy(&eloop.writers); eloop_sock_table_destroy(&eloop.exceptions); if(eloop.signal_count == 0) { - os_free(eloop.signals); + os_free_loose(eloop.signals); eloop.signals = NULL; } } @@ -807,7 +807,7 @@ void eloop_free_resource(void) eloop_sock_table_destroy(&eloop.writers); eloop_sock_table_destroy(&eloop.exceptions); if(eloop.signal_count == 0) { - os_free(eloop.signals); + os_free_loose(eloop.signals); eloop.signals = NULL; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/os.h b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/os.h index 79dacf949b607ca877551863d83c47b7296b00dc..8b64a766fb57bba8df1d451fe7eb47c632c86b7a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/os.h +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/os.h @@ -240,7 +240,7 @@ int os_unsetenv(const char *name); * * This function allocates memory and reads the given file to this buffer. Both * binary and text files can be read with this function. The caller is - * responsible for freeing the returned buffer with os_free(). + * responsible for freeing the returned buffer with os_free_loose(). */ char * os_readfile(const char *name, size_t *len); @@ -263,7 +263,7 @@ int os_fdatasync(FILE *stream); * @size: Number of bytes to allocate * Returns: Pointer to allocated and zeroed memory or %NULL on failure * - * Caller is responsible for freeing the returned buffer with os_free(). + * Caller is responsible for freeing the returned buffer with os_free_loose(). */ //void * os_zalloc(size_t size); @@ -277,7 +277,7 @@ int os_fdatasync(FILE *stream); * allocation is used for an array. The main benefit over os_zalloc() is in * having an extra check to catch integer overflows in multiplication. * - * Caller is responsible for freeing the returned buffer with os_free(). + * Caller is responsible for freeing the returned buffer with os_free_loose(). */ static inline void * os_calloc(size_t nmemb, size_t size) { diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpa_debug.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpa_debug.c index f746e5068fdbd6d82c766521f3807f1193d62a6a..6f4d5693012501baeac3a4b8c0e112ff542cde70 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpa_debug.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpa_debug.c @@ -72,7 +72,7 @@ void wpa_dbg(void *ctx, int level, const char *fmt, ...) len = vsnprintf(buf, buflen, fmt, ap); va_end(ap); bk_send_string(1, buf); - os_free(buf); + os_free_loose(buf); os_printf("\r\n"); } @@ -377,7 +377,7 @@ void wpa_msg_global_only(void *ctx, int level, const char *fmt, ...) wpa_printf(level, "%s", buf); if (wpa_msg_cb) wpa_msg_cb(ctx, level, WPA_MSG_ONLY_GLOBAL, buf, len); - os_free(buf); + os_free_loose(buf); } #endif /* CONFIG_NO_WPA_MSG */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpabuf.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpabuf.c index 6737b66fa27bdd64188d24e4117fa7c59db2c9bf..69e9ebafb51c16c12bec7d1c0807dc306a75533c 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpabuf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/src/utils/wpabuf.c @@ -190,14 +190,14 @@ void wpabuf_free(struct wpabuf *buf) wpa_trace_show("wpabuf_free magic mismatch"); } if (buf->flags & WPABUF_FLAG_EXT_DATA) - os_free(buf->buf); - os_free(trace); + os_free_loose(buf->buf); + os_free_loose(trace); #else /* WPA_TRACE */ if (buf == NULL) return; if (buf->flags & WPABUF_FLAG_EXT_DATA) - os_free(buf->buf); - os_free(buf); + os_free_loose(buf->buf); + os_free_loose(buf); #endif /* WPA_TRACE */ } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/blacklist.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/blacklist.c index c035bc7b1a9c0d4b6e8a8e29c3522b58d0ffdb70..5524b010d0d6cc20504597aa1c01064a12afc529 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/blacklist.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/blacklist.c @@ -108,7 +108,7 @@ int wpa_blacklist_del(struct wpa_supplicant *wpa_s, const u8 *bssid) } wpa_printf(MSG_DEBUG, "Removed BSSID " MACSTR " from " "blacklist", MAC2STR(bssid)); - os_free(e); + os_free_loose(e); return 0; } prev = e; @@ -136,7 +136,7 @@ void wpa_blacklist_clear(struct wpa_supplicant *wpa_s) e = e->next; wpa_printf(MSG_DEBUG, "Removed BSSID " MACSTR " from " "blacklist (clear)", MAC2STR(prev->bssid)); - os_free(prev); + os_free_loose(prev); } wpa_s->extra_blacklist_count += max_count; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/bss.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/bss.c index 2262cb3c954294eedf06593546e77b2d99de7cd4..f8f1c1a1c10ef78f2591df45e46a43afbb7c5016 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/bss.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/bss.c @@ -169,7 +169,7 @@ static void wpa_bss_anqp_free(struct wpa_bss_anqp *anqp) wpabuf_free(anqp->hs20_osu_providers_list); #endif /* CONFIG_HS20 */ - os_free(anqp); + os_free_loose(anqp); } @@ -223,7 +223,7 @@ void wpa_bss_remove(struct wpa_supplicant *wpa_s, struct wpa_bss *bss, wpa_ssid_txt(bss->ssid, bss->ssid_len), reason); wpas_notify_bss_removed(wpa_s, bss->bssid, bss->id); wpa_bss_anqp_free(bss->anqp); - os_free(bss); + os_free_loose(bss); } @@ -1239,7 +1239,7 @@ int wpa_bss_get_max_rate(const struct wpa_bss *bss) * @rates: Buffer for returning a pointer to the rates list (units of 500 kbps) * Returns: number of legacy TX rates or -1 on failure * - * The caller is responsible for freeing the returned buffer with os_free() in + * The caller is responsible for freeing the returned buffer with os_free_loose() in * case of success. */ int wpa_bss_get_bit_rates(const struct wpa_bss *bss, u8 **rates) diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/cmd_wlan.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/cmd_wlan.c index 7b4fb518a9d99716e5a88bb919ec4d4c0dbf0bff..32d8de3603fd86acf2b4315942e84481bce70b2f 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/cmd_wlan.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/cmd_wlan.c @@ -252,7 +252,7 @@ static int cmd_wpas_parse_key_mgmt(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { os_printf("No key_mgmt values configured\n"); @@ -302,7 +302,7 @@ static int cmd_wpas_parse_cipher(const char *value) else if (os_strcmp(start, "GTK_NOT_USED") == 0) val |= WPA_CIPHER_GTK_NOT_USED; else { - os_free(buf); + os_free_loose(buf); return -1; } @@ -310,7 +310,7 @@ static int cmd_wpas_parse_cipher(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); return val; } @@ -358,7 +358,7 @@ static int cmd_wpas_parse_proto(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); /* softAP work on open mode. */ #if 0 @@ -409,7 +409,7 @@ static int cmd_wpas_parse_auth_alg(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { os_printf("No auth_alg values configured\n"); @@ -736,7 +736,7 @@ int cmd_wlan_sta_exec(char *cmd) ret = wlan_sta_scan_result(&results); if (ret == 0) cmd_wlan_sta_print_scan_results(&results); - os_free(results.ap); + os_free_loose(results.ap); } else if (os_strncmp(cmd, "scan interval ", 14) == 0) { int sec; if (cmd_wpas_parse_int(cmd + 14, 0, INT32_MAX, &sec) != 0) { @@ -784,7 +784,7 @@ int cmd_wlan_sta_exec(char *cmd) ret = wlan_sta_ap_info(ap); if (ret == 0) cmd_wlan_sta_print_ap(ap); - os_free(ap); + os_free_loose(ap); } else if (os_strncmp(cmd, "genpsk ", 7) == 0) { uint8_t i; char *argv[2]; @@ -1180,7 +1180,7 @@ int cmd_wlan_ap_exec(char *cmd) ret = wlan_ap_sta_info(&stas); if (ret == 0) cmd_wlan_ap_print_sta_info(&stas); - os_free(stas.sta); + os_free_loose(stas.sta); } else { os_printf("unknown cmd '%s'\n", cmd); return -1; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/config.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/config.c index 8b1e4e0fbb0395802ec1488469e4acb4d4d2ce32..d751c46a9f91158265d51b161038b07b12b389ef 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/config.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/config.c @@ -90,7 +90,7 @@ static int wpa_config_parse_str(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: too short %s (len=%lu " "min_len=%ld)", line, data->name, (unsigned long) res_len, (long) data->param3); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -98,7 +98,7 @@ static int wpa_config_parse_str(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: too long %s (len=%lu " "max_len=%ld)", line, data->name, (unsigned long) res_len, (long) data->param4); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -116,11 +116,11 @@ set: (*dst && tmp && prev_len == res_len && os_memcmp(*dst, tmp, res_len) == 0)) { /* No change to the previously configured value */ - os_free(tmp); + os_free_loose(tmp); return 1; } - os_free(*dst); + os_free_loose(*dst); *dst = tmp; if (data->param2) *dst_len = res_len; @@ -245,7 +245,7 @@ static char * wpa_config_write_int(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, "%d", *src); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -276,7 +276,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: Invalid %s address '%s'", line, name, value); - os_free(buf); + os_free_loose(buf); return -1; } /* continue anyway since this could have been from a @@ -287,7 +287,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, } else { n = os_realloc_array(buf, count + 1, 2 * ETH_ALEN); if (n == NULL) { - os_free(buf); + os_free_loose(buf); return -1; } buf = n; @@ -304,7 +304,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, pos = os_strchr(pos, ' '); } - os_free(*list); + os_free_loose(*list); *list = buf; *num = count; @@ -337,7 +337,7 @@ static char * wpa_config_write_addr_list(const struct parse_data *data, *pos++ = ' '; res = hwaddr_mask_txt(pos, end - pos, a, m); if (res < 0) { - os_free(value); + os_free_loose(value); return NULL; } pos += res; @@ -383,7 +383,7 @@ static char * wpa_config_write_bssid(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, MACSTR, MAC2STR(ssid->bssid)); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -445,7 +445,7 @@ static int wpa_config_parse_psk(const struct parse_data *data, str_clear_free(ssid->passphrase); ssid->passphrase = NULL; ssid->psk_set = 0; - os_free(ssid->ext_psk); + os_free_loose(ssid->ext_psk); ssid->ext_psk = os_strdup(value + 4); if (ssid->ext_psk == NULL) return -1; @@ -528,7 +528,7 @@ static char * wpa_config_write_psk(const struct parse_data *data, return NULL; res = os_snprintf(buf, len, "ext:%s", ssid->ext_psk); if (os_snprintf_error(len, res)) { - os_free(buf); + os_free_loose(buf); buf = NULL; } return buf; @@ -587,7 +587,7 @@ static int wpa_config_parse_proto(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -640,7 +640,7 @@ static char * wpa_config_write_proto(const struct parse_data *data, } if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -725,7 +725,7 @@ static int wpa_config_parse_key_mgmt(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -918,7 +918,7 @@ static char * wpa_config_write_key_mgmt(const struct parse_data *data, #endif /* CONFIG_SUITEB192 */ if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -959,7 +959,7 @@ static char * wpa_config_write_cipher(int cipher) return NULL; if (wpa_write_ciphers(buf, buf + 50, cipher, " ") < 0) { - os_free(buf); + os_free_loose(buf); return NULL; } @@ -1076,7 +1076,7 @@ static int wpa_config_parse_auth_alg(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -1135,7 +1135,7 @@ static char * wpa_config_write_auth_alg(const struct parse_data *data, } if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -1165,7 +1165,7 @@ static int * wpa_config_parse_int_array(const char *value) size_t i; n = os_realloc_array(freqs, len * 2 + 1, sizeof(int)); if (n == NULL) { - os_free(freqs); + os_free_loose(freqs); return NULL; } for (i = len; i <= len * 2; i++) @@ -1195,10 +1195,10 @@ static int wpa_config_parse_scan_freq(const struct parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(ssid->scan_freq); + os_free_loose(ssid->scan_freq); ssid->scan_freq = freqs; return 0; @@ -1215,10 +1215,10 @@ static int wpa_config_parse_freq_list(const struct parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(ssid->freq_list); + os_free_loose(ssid->freq_list); ssid->freq_list = freqs; return 0; @@ -1303,8 +1303,8 @@ static int wpa_config_parse_eap(const struct parse_data *data, methods = os_realloc_array(methods, num_methods + 1, sizeof(*methods)); if (methods == NULL) { - os_free(tmp); - os_free(buf); + os_free_loose(tmp); + os_free_loose(buf); return -1; } methods[num_methods].method = eap_peer_get_type( @@ -1328,12 +1328,12 @@ static int wpa_config_parse_eap(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); tmp = methods; methods = os_realloc_array(methods, num_methods + 1, sizeof(*methods)); if (methods == NULL) { - os_free(tmp); + os_free_loose(tmp); return -1; } methods[num_methods].vendor = EAP_VENDOR_IETF; @@ -1362,13 +1362,13 @@ static int wpa_config_parse_eap(const struct parse_data *data, } } if (match == num_methods) { - os_free(methods); + os_free_loose(methods); return 1; } } wpa_hexdump(MSG_MSGDUMP, "eap methods", (u8 *) methods, num_methods * sizeof(*methods)); - os_free(ssid->eap.eap_methods); + os_free_loose(ssid->eap.eap_methods); ssid->eap.eap_methods = methods; return errors ? -1 : 0; } @@ -1476,7 +1476,7 @@ static int wpa_config_parse_password(const struct parse_data *data, return -1; if (hexstr2bin(value + 5, hash, 16)) { - os_free(hash); + os_free_loose(hash); wpa_printf(MSG_ERROR, "Line %d: Invalid password hash", line); return -1; } @@ -1552,7 +1552,7 @@ static int wpa_config_parse_wep_key(u8 *key, size_t *len, int line, if (*len > MAX_WEP_KEY_LEN) { wpa_printf(MSG_ERROR, "Line %d: Too long WEP key %d '%s'.", line, idx, value); - os_free(buf); + os_free_loose(buf); return -1; } if (*len && *len != 5 && *len != 13 && *len != 16) { @@ -1687,7 +1687,7 @@ static char * wpa_config_write_go_p2p_dev_addr(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, MACSTR, MAC2STR(ssid->go_p2p_dev_addr)); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -1738,14 +1738,14 @@ static int wpa_config_parse_psk_list(const struct parse_data *data, if (hwaddr_aton(pos, p->addr)) { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list address '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } pos += 17; if (*pos != '-') { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } pos++; @@ -1753,7 +1753,7 @@ static int wpa_config_parse_psk_list(const struct parse_data *data, if (hexstr2bin(pos, p->psk, PMK_LEN) || pos[PMK_LEN * 2] != '\0') { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list PSK '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } @@ -1788,11 +1788,11 @@ static int wpa_config_parse_mesh_basic_rates(const struct parse_data *data, return -1; } if (rates[0] == 0) { - os_free(rates); + os_free_loose(rates); rates = NULL; } - os_free(ssid->mesh_basic_rates); + os_free_loose(ssid->mesh_basic_rates); ssid->mesh_basic_rates = rates; return 0; @@ -2140,7 +2140,7 @@ int wpa_config_update_prio_list(struct wpa_config *config) struct wpa_ssid *ssid; int ret = 0; - os_free(config->pssid); + os_free_loose(config->pssid); config->pssid = NULL; config->num_prio = 0; @@ -2166,28 +2166,28 @@ void wpa_config_free_ssid(struct wpa_ssid *ssid) { struct psk_list_entry *psk; - os_free(ssid->ssid); + os_free_loose(ssid->ssid); str_clear_free(ssid->passphrase); - os_free(ssid->ext_psk); + os_free_loose(ssid->ext_psk); #ifdef IEEE8021X_EAPOL eap_peer_config_free(&ssid->eap); #endif /* IEEE8021X_EAPOL */ - os_free(ssid->id_str); - os_free(ssid->scan_freq); - os_free(ssid->freq_list); - os_free(ssid->bgscan); - os_free(ssid->p2p_client_list); - os_free(ssid->bssid_blacklist); - os_free(ssid->bssid_whitelist); + os_free_loose(ssid->id_str); + os_free_loose(ssid->scan_freq); + os_free_loose(ssid->freq_list); + os_free_loose(ssid->bgscan); + os_free_loose(ssid->p2p_client_list); + os_free_loose(ssid->bssid_blacklist); + os_free_loose(ssid->bssid_whitelist); #ifdef CONFIG_HT_OVERRIDES - os_free(ssid->ht_mcs); + os_free_loose(ssid->ht_mcs); #endif /* CONFIG_HT_OVERRIDES */ #ifdef CONFIG_MESH - os_free(ssid->mesh_basic_rates); + os_free_loose(ssid->mesh_basic_rates); #endif /* CONFIG_MESH */ while (NULL != (psk = dl_list_first(&ssid->psk_list, struct psk_list_entry, @@ -2203,30 +2203,30 @@ void wpa_config_free_cred(struct wpa_cred *cred) { size_t i; - os_free(cred->realm); + os_free_loose(cred->realm); str_clear_free(cred->username); str_clear_free(cred->password); - os_free(cred->ca_cert); - os_free(cred->client_cert); - os_free(cred->private_key); + os_free_loose(cred->ca_cert); + os_free_loose(cred->client_cert); + os_free_loose(cred->private_key); str_clear_free(cred->private_key_passwd); - os_free(cred->imsi); + os_free_loose(cred->imsi); str_clear_free(cred->milenage); for (i = 0; i < cred->num_domain; i++) - os_free(cred->domain[i]); - os_free(cred->domain); - os_free(cred->domain_suffix_match); - os_free(cred->eap_method); - os_free(cred->phase1); - os_free(cred->phase2); - os_free(cred->excluded_ssid); - os_free(cred->roaming_partner); - os_free(cred->provisioning_sp); + os_free_loose(cred->domain[i]); + os_free_loose(cred->domain); + os_free_loose(cred->domain_suffix_match); + os_free_loose(cred->eap_method); + os_free_loose(cred->phase1); + os_free_loose(cred->phase2); + os_free_loose(cred->excluded_ssid); + os_free_loose(cred->roaming_partner); + os_free_loose(cred->provisioning_sp); for (i = 0; i < cred->num_req_conn_capab; i++) - os_free(cred->req_conn_capab_port[i]); - os_free(cred->req_conn_capab_port); - os_free(cred->req_conn_capab_proto); - os_free(cred); + os_free_loose(cred->req_conn_capab_port[i]); + os_free_loose(cred->req_conn_capab_port); + os_free_loose(cred->req_conn_capab_proto); + os_free_loose(cred); } @@ -2253,43 +2253,43 @@ void wpa_config_free(struct wpa_config *config) wpabuf_free(config->wps_vendor_ext_m1); for (i = 0; i < MAX_WPS_VENDOR_EXT; i++) wpabuf_free(config->wps_vendor_ext[i]); - os_free(config->ctrl_interface); - os_free(config->ctrl_interface_group); - os_free(config->opensc_engine_path); - os_free(config->pkcs11_engine_path); - os_free(config->pkcs11_module_path); - os_free(config->openssl_ciphers); - os_free(config->pcsc_reader); + os_free_loose(config->ctrl_interface); + os_free_loose(config->ctrl_interface_group); + os_free_loose(config->opensc_engine_path); + os_free_loose(config->pkcs11_engine_path); + os_free_loose(config->pkcs11_module_path); + os_free_loose(config->openssl_ciphers); + os_free_loose(config->pcsc_reader); str_clear_free(config->pcsc_pin); - os_free(config->driver_param); - os_free(config->device_name); - os_free(config->manufacturer); - os_free(config->model_name); - os_free(config->model_number); - os_free(config->serial_number); - os_free(config->config_methods); - os_free(config->p2p_ssid_postfix); - os_free(config->pssid); - os_free(config->p2p_pref_chan); - os_free(config->p2p_no_go_freq.range); - os_free(config->autoscan); - os_free(config->freq_list); + os_free_loose(config->driver_param); + os_free_loose(config->device_name); + os_free_loose(config->manufacturer); + os_free_loose(config->model_name); + os_free_loose(config->model_number); + os_free_loose(config->serial_number); + os_free_loose(config->config_methods); + os_free_loose(config->p2p_ssid_postfix); + os_free_loose(config->pssid); + os_free_loose(config->p2p_pref_chan); + os_free_loose(config->p2p_no_go_freq.range); + os_free_loose(config->autoscan); + os_free_loose(config->freq_list); wpabuf_free(config->wps_nfc_dh_pubkey); wpabuf_free(config->wps_nfc_dh_privkey); wpabuf_free(config->wps_nfc_dev_pw); - os_free(config->ext_password_backend); - os_free(config->sae_groups); + os_free_loose(config->ext_password_backend); + os_free_loose(config->sae_groups); wpabuf_free(config->ap_vendor_elements); - os_free(config->osu_dir); - os_free(config->bgscan); - os_free(config->wowlan_triggers); - os_free(config->fst_group_id); - os_free(config->sched_scan_plans); + os_free_loose(config->osu_dir); + os_free_loose(config->bgscan); + os_free_loose(config->wowlan_triggers); + os_free_loose(config->fst_group_id); + os_free_loose(config->sched_scan_plans); #ifdef CONFIG_MBO - os_free(config->non_pref_chan); + os_free_loose(config->non_pref_chan); #endif /* CONFIG_MBO */ - os_free(config); + os_free_loose(config); } @@ -2530,7 +2530,7 @@ int wpa_config_set_quoted(struct wpa_ssid *ssid, const char *var, buf[len + 1] = '"'; buf[len + 2] = '\0'; ret = wpa_config_set(ssid, var, buf, 0); - os_free(buf); + os_free_loose(buf); return ret; } @@ -2574,13 +2574,13 @@ char ** wpa_config_get_all(struct wpa_ssid *ssid, int get_keys) if (value == NULL) continue; if (os_strlen(value) == 0) { - os_free(value); + os_free_loose(value); continue; } key = os_strdup(field->name); if (key == NULL) { - os_free(value); + os_free_loose(value); goto err; } @@ -2594,8 +2594,8 @@ char ** wpa_config_get_all(struct wpa_ssid *ssid, int get_keys) err: for (i = 0; props[i]; i++) - os_free(props[i]); - os_free(props); + os_free_loose(props[i]); + os_free_loose(props); return NULL; #endif /* NO_CONFIG_WRITE */ } @@ -2630,7 +2630,7 @@ char * wpa_config_get(struct wpa_ssid *ssid, const char *var) wpa_printf(MSG_ERROR, "Found newline in value for %s; not returning it", var); - os_free(ret); + os_free_loose(ret); ret = NULL; } @@ -2678,7 +2678,7 @@ char * wpa_config_get_no_key(struct wpa_ssid *ssid, const char *var) return os_strdup("*"); } - os_free(res); + os_free_loose(res); return NULL; } return res; @@ -2769,7 +2769,7 @@ static int wpa_config_set_cred_req_conn_capab(struct wpa_cred *cred, while (*pos) { nports = os_realloc_array(ports, num_ports + 1, sizeof(int)); if (nports == NULL) { - os_free(ports); + os_free_loose(ports); return -1; } ports = nports; @@ -2783,7 +2783,7 @@ static int wpa_config_set_cred_req_conn_capab(struct wpa_cred *cred, nports = os_realloc_array(ports, num_ports + 1, sizeof(int)); if (nports == NULL) { - os_free(ports); + os_free_loose(ports); return -1; } ports = nports; @@ -2879,7 +2879,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "realm") == 0) { - os_free(cred->realm); + os_free_loose(cred->realm); cred->realm = val; return 0; } @@ -2898,19 +2898,19 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "ca_cert") == 0) { - os_free(cred->ca_cert); + os_free_loose(cred->ca_cert); cred->ca_cert = val; return 0; } if (os_strcmp(var, "client_cert") == 0) { - os_free(cred->client_cert); + os_free_loose(cred->client_cert); cred->client_cert = val; return 0; } if (os_strcmp(var, "private_key") == 0) { - os_free(cred->private_key); + os_free_loose(cred->private_key); cred->private_key = val; return 0; } @@ -2922,7 +2922,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "imsi") == 0) { - os_free(cred->imsi); + os_free_loose(cred->imsi); cred->imsi = val; return 0; } @@ -2934,7 +2934,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "domain_suffix_match") == 0) { - os_free(cred->domain_suffix_match); + os_free_loose(cred->domain_suffix_match); cred->domain_suffix_match = val; return 0; } @@ -2945,7 +2945,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_domain + 1, sizeof(char *)); if (new_domain == NULL) { - os_free(val); + os_free_loose(val); return -1; } new_domain[cred->num_domain++] = val; @@ -2954,13 +2954,13 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "phase1") == 0) { - os_free(cred->phase1); + os_free_loose(cred->phase1); cred->phase1 = val; return 0; } if (os_strcmp(var, "phase2") == 0) { - os_free(cred->phase2); + os_free_loose(cred->phase2); cred->phase2 = val; return 0; } @@ -2970,12 +2970,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, wpa_printf(MSG_ERROR, "Line %d: invalid " "roaming_consortium length %d (3..15 " "expected)", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } os_memcpy(cred->roaming_consortium, val, len); cred->roaming_consortium_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -2985,12 +2985,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, wpa_printf(MSG_ERROR, "Line %d: invalid " "required_roaming_consortium length %d " "(3..15 expected)", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } os_memcpy(cred->required_roaming_consortium, val, len); cred->required_roaming_consortium_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -3000,7 +3000,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, if (len > SSID_MAX_LEN) { wpa_printf(MSG_ERROR, "Line %d: invalid " "excluded_ssid length %d", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } @@ -3008,7 +3008,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_excluded_ssid + 1, sizeof(struct excluded_ssid)); if (e == NULL) { - os_free(val); + os_free_loose(val); return -1; } cred->excluded_ssid = e; @@ -3017,7 +3017,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, os_memcpy(e->ssid, val, len); e->ssid_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -3030,7 +3030,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_roaming_partner + 1, sizeof(struct roaming_partner)); if (p == NULL) { - os_free(val); + os_free_loose(val); return -1; } cred->roaming_partner = p; @@ -3039,12 +3039,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(val, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; if (pos - val - 1 >= (int) sizeof(p->fqdn)) { - os_free(val); + os_free_loose(val); return -1; } os_memcpy(p->fqdn, val, pos - val); @@ -3053,7 +3053,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(pos, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; @@ -3062,25 +3062,25 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(pos, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; if (os_strlen(pos) >= sizeof(p->country)) { - os_free(val); + os_free_loose(val); return -1; } os_memcpy(p->country, pos, os_strlen(pos) + 1); cred->num_roaming_partner++; - os_free(val); + os_free_loose(val); return 0; } if (os_strcmp(var, "provisioning_sp") == 0) { - os_free(cred->provisioning_sp); + os_free_loose(cred->provisioning_sp); cred->provisioning_sp = val; return 0; } @@ -3090,7 +3090,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, line, var); } - os_free(val); + os_free_loose(val); return -1; } @@ -3106,7 +3106,7 @@ static char * alloc_int_str(int val) return NULL; res = os_snprintf(buf, bufsize, "%d", val); if (os_snprintf_error(bufsize, res)) { - os_free(buf); + os_free_loose(buf); buf = NULL; } return buf; @@ -3598,7 +3598,7 @@ static int wpa_global_config_parse_str(const struct global_parse_data *data, return -1; dst = (char **) (((u8 *) config) + (long) data->param1); - os_free(*dst); + os_free_loose(*dst); *dst = tmp; wpa_printf(MSG_DEBUG, "%s='%s'", data->name, *dst); @@ -3622,7 +3622,7 @@ static int wpa_config_process_bgscan(const struct global_parse_data *data, } res = wpa_global_config_parse_str(data, config, line, tmp); - os_free(tmp); + os_free_loose(tmp); return res; } @@ -3656,10 +3656,10 @@ static int wpa_config_process_freq_list(const struct global_parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(config->freq_list); + os_free_loose(config->freq_list); config->freq_list = freqs; return 0; } @@ -3748,7 +3748,7 @@ static int wpa_config_process_sae_groups( return -1; } - os_free(config->sae_groups); + os_free_loose(config->sae_groups); config->sae_groups = groups; return 0; @@ -3798,7 +3798,7 @@ static int wpa_config_process_no_ctrl_interface( struct wpa_config *config, int line, const char *pos) { wpa_printf(MSG_DEBUG, "no_ctrl_interface -> ctrl_interface=NULL"); - os_free(config->ctrl_interface); + os_free_loose(config->ctrl_interface); config->ctrl_interface = NULL; return 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/ctrl_iface.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/ctrl_iface.c index 8eb8f8ff52c397a8b1bdd698985a0367c065dea2..69c415483d9cc03f914014046d8bee3167c88bc2 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/ctrl_iface.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/ctrl_iface.c @@ -131,7 +131,7 @@ static int wpa_supplicant_ctrl_iface_select_network( int *freqs = freq_range_to_channel_list(wpa_s, pos + 6); if (freqs) { wpa_s->scan_req = MANUAL_SCAN_REQ; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = freqs; } } @@ -607,7 +607,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) #endif wpa_s->num_ssids_from_scan_req = ssid_count; - os_free(wpa_s->ssids_from_scan_req); + os_free_loose(wpa_s->ssids_from_scan_req); if (ssid_count) { wpa_s->ssids_from_scan_req = ssid; ssid = NULL; @@ -631,7 +631,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) wpa_s->scan_id_count = scan_id_count; os_memcpy(wpa_s->scan_id, scan_id, scan_id_count * sizeof(int)); wpa_s->scan_res_handler = scan_res_handler; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = manual_scan_freqs; manual_scan_freqs = NULL; @@ -657,7 +657,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) wpa_s->scan_id_count = scan_id_count; os_memcpy(wpa_s->scan_id, scan_id, scan_id_count * sizeof(int)); wpa_s->scan_res_handler = scan_res_handler; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = manual_scan_freqs; manual_scan_freqs = NULL; @@ -680,8 +680,8 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) } done: - os_free(manual_scan_freqs); - os_free(ssid); + os_free_loose(manual_scan_freqs); + os_free_loose(ssid); return ret; } @@ -824,7 +824,7 @@ int wpa_supplicant_ctrl_iface_set_network(struct wpa_supplicant *wpa_s, wlan_sta wpa_sm_pmksa_cache_flush(wpa_s->wpa, ssid); } if (ssid->ssid) - os_free(ssid->ssid); + os_free_loose(ssid->ssid); ssid->ssid = (u8 *)dup_binstr(config->u.ssid.ssid, config->u.ssid.ssid_len); ssid->ssid_len = config->u.ssid.ssid_len; break; @@ -908,7 +908,7 @@ int wpa_supplicant_ctrl_iface_set_network(struct wpa_supplicant *wpa_s, wlan_sta case WLAN_STA_FIELD_SAE_GROUPS: { int *groups = os_malloc(sizeof(config->u.sae_groups)); if (groups) { - os_free(wpa_s->conf->sae_groups); + os_free_loose(wpa_s->conf->sae_groups); os_memcpy(groups, config->u.sae_groups, sizeof(config->u.sae_groups)); wpa_s->conf->sae_groups = groups; //while (*groups) { @@ -1187,7 +1187,7 @@ exit: if (msg->sema) rtos_set_semaphore(&msg->sema); if (msg->flags & WPAH_FLAG_FREE) - os_free((void *)msg->argu); + os_free_loose((void *)msg->argu); #undef CHECK_WPA_S @@ -1287,7 +1287,7 @@ exit: if (msg->sema) rtos_set_semaphore(&msg->sema); if (msg->flags & WPAH_FLAG_FREE) - os_free((void *)msg->argu); + os_free_loose((void *)msg->argu); #undef CHECK_WPA_S diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/events.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/events.c index 4a6c362cad7e16f7b6da4abbe29025a016920c3b..5396393b7b8aae1014e18450159cd4d8c1ee5c42 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/events.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/events.c @@ -951,7 +951,7 @@ struct wpa_ssid * wpa_scan_res_match(struct wpa_supplicant *wpa_s, #if CFG_SUPPORT_BSSID_CONNECT } else if (0 == ssid->ssid_len) { if (NULL != ssid->ssid) { - os_free(ssid->ssid); + os_free_loose(ssid->ssid); } ssid->ssid = dup_binstr(bss->ssid, bss->ssid_len); if (NULL != ssid->ssid) { @@ -3325,7 +3325,7 @@ static void wpa_supplicant_notify_avoid_freq(struct wpa_supplicant *wpa_s, } #endif /* CONFIG_P2P */ - os_free(str); + os_free_loose(str); } @@ -3701,7 +3701,7 @@ void wpa_supplicant_event_sta(void *ctx, enum wpa_event_type event, wpa_msg(wpa_s, MSG_INFO, "MGMT-RX freq=%d datarate=%u ssi_signal=%d %s", rx->freq, rx->datarate, rx->ssi_signal, hex); - os_free(hex); + os_free_loose(hex); } break; } @@ -4095,7 +4095,7 @@ void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event, if (!wpa_i) return; wpa_s = wpa_supplicant_add_iface(ctx, wpa_i, NULL); - os_free(wpa_i); + os_free_loose(wpa_i); if (wpa_s) wpa_s->matched = 1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/main_supplicant.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/main_supplicant.c index 8470a56cb9b067ad976abc28d389e95b7e6f7f6f..6790011c229707d119850b7eefb1175609592501 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/main_supplicant.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/main_supplicant.c @@ -110,12 +110,12 @@ int supplicant_main_exit(void) } if (wpas_ifaces) { - os_free(wpas_ifaces); + os_free_loose(wpas_ifaces); wpas_ifaces = 0; } if (wpas_connect_ssid) { - os_free(wpas_connect_ssid); + os_free_loose(wpas_connect_ssid); wpas_connect_ssid = 0; } @@ -235,10 +235,10 @@ int supplicant_main_entry(char *oob_ssid) } out: - os_free(wpas_ifaces); + os_free_loose(wpas_ifaces); wpas_ifaces = 0; - os_free(params.pid_file); + os_free_loose(params.pid_file); params.pid_file = 0; return exitcode; diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/notify.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/notify.c index 22a466b7f758f0db4d290cfd9f2eba0177b8f686..aefa31383e5665ded5f4c99184998609786b91ab 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/notify.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/notify.c @@ -831,7 +831,7 @@ void wpas_notify_certification(struct wpa_supplicant *wpa_s, int depth, WPA_EVENT_EAP_PEER_CERT "depth=%d subject='%s' cert=%s", depth, subject, cert_hex); - os_free(cert_hex); + os_free_loose(cert_hex); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/sme.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/sme.c index 2e3ca23cd9aedb95a4f838dacffe289ebaa1de6d..fd9b7e8cb1744e56ccde2050af62dc186d8822cf 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/sme.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/sme.c @@ -908,7 +908,7 @@ void sme_event_auth(struct wpa_supplicant *wpa_s, union wpa_event_data *data) MAC2STR(data->auth.peer), data->auth.auth_type, data->auth.auth_transaction, data->auth.status_code, ie_txt); - os_free(ie_txt); + os_free_loose(ie_txt); if (data->auth.status_code != WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG || @@ -1075,7 +1075,7 @@ int sme_update_ft_ies(struct wpa_supplicant *wpa_s, const u8 *md, { if (md == NULL || ies == NULL) { wpa_dbg(wpa_s, MSG_DEBUG, "SME: Remove mobility domain"); - os_free(wpa_s->sme.ft_ies); + os_free_loose(wpa_s->sme.ft_ies); wpa_s->sme.ft_ies = NULL; wpa_s->sme.ft_ies_len = 0; wpa_s->sme.ft_used = 0; @@ -1084,7 +1084,7 @@ int sme_update_ft_ies(struct wpa_supplicant *wpa_s, const u8 *md, os_memcpy(wpa_s->sme.mobility_domain, md, MOBILITY_DOMAIN_ID_LEN); wpa_hexdump(MSG_DEBUG, "SME: FT IEs", ies, ies_len); - os_free(wpa_s->sme.ft_ies); + os_free_loose(wpa_s->sme.ft_ies); wpa_s->sme.ft_ies = os_malloc(ies_len); if (wpa_s->sme.ft_ies == NULL) return -1; @@ -1263,7 +1263,7 @@ void sme_clear_on_disassoc(struct wpa_supplicant *wpa_s) void sme_deinit(struct wpa_supplicant *wpa_s) { - os_free(wpa_s->sme.ft_ies); + os_free_loose(wpa_s->sme.ft_ies); wpa_s->sme.ft_ies = NULL; wpa_s->sme.ft_ies_len = 0; #ifdef CONFIG_IEEE80211W @@ -1485,7 +1485,7 @@ static void sme_obss_scan_timeout(void *eloop_ctx, void *timeout_ctx) wpa_printf(MSG_DEBUG, "SME OBSS: Failed to trigger scan"); else wpa_s->sme.sched_obss_scan = 1; - os_free(params.freqs); + os_free_loose(params.freqs); eloop_register_timeout(wpa_s->sme.obss_scan_int, 0, sme_obss_scan_timeout, wpa_s, NULL); @@ -1653,7 +1653,7 @@ static void sme_start_sa_query(struct wpa_supplicant *wpa_s) static void sme_stop_sa_query(struct wpa_supplicant *wpa_s) { eloop_cancel_timeout(sme_sa_query_timer, wpa_s, NULL); - os_free(wpa_s->sme.sa_query_trans_id); + os_free_loose(wpa_s->sme.sa_query_trans_id); wpa_s->sme.sa_query_trans_id = NULL; wpa_s->sme.sa_query_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wmm_ac.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wmm_ac.c index 5301b011f59321a57e8134d393816e1849763f10..1c112c885d31d11340e7d94b625e58a7dacf2aa3 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wmm_ac.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wmm_ac.c @@ -101,7 +101,7 @@ static int wmm_ac_add_ts(struct wpa_supplicant *wpa_s, const u8 *addr, " TSID=%u admitted time=%u, ret=%d", MAC2STR(addr), tsid, admitted_time, ret); if (ret < 0) { - os_free(_tspec); + os_free_loose(_tspec); return -1; } } @@ -137,7 +137,7 @@ static void wmm_ac_del_ts_idx(struct wpa_supplicant *wpa_s, u8 ac, wpa_msg(wpa_s, MSG_INFO, WMM_AC_EVENT_TSPEC_REMOVED "tsid=%d addr=" MACSTR, tsid, MAC2STR(wpa_s->bssid)); - os_free(wpa_s->tspecs[ac][dir]); + os_free_loose(wpa_s->tspecs[ac][dir]); wpa_s->tspecs[ac][dir] = NULL; } @@ -155,7 +155,7 @@ static void wmm_ac_del_req(struct wpa_supplicant *wpa_s, int failed) eloop_cancel_timeout(wmm_ac_addts_req_timeout, wpa_s, req); wpa_s->addts_request = NULL; - os_free(req); + os_free_loose(req); } @@ -529,7 +529,7 @@ static void wmm_ac_deinit(struct wpa_supplicant *wpa_s) /* delete pending add_ts requset */ wmm_ac_del_req(wpa_s, 1); - os_free(wpa_s->wmm_ac_assoc_info); + os_free_loose(wpa_s->wmm_ac_assoc_info); wpa_s->wmm_ac_assoc_info = NULL; } @@ -632,7 +632,7 @@ int wpas_wmm_ac_addts(struct wpa_supplicant *wpa_s, wpa_s, addts_req); return 0; err: - os_free(addts_req); + os_free_loose(addts_req); return -1; } @@ -972,7 +972,7 @@ void wmm_ac_clear_saved_tspecs(struct wpa_supplicant *wpa_s) { if (wpa_s->last_tspecs) { wpa_printf(MSG_DEBUG, "WMM AC: Clear saved tspecs"); - os_free(wpa_s->last_tspecs); + os_free_loose(wpa_s->last_tspecs); wpa_s->last_tspecs = NULL; wpa_s->last_tspecs_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_scan.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_scan.c index e399dc5be3944ac4ea2dfcc2ba056b8c1b5c85e5..ea668f69dc1d7b519b23a5f988f5b09066e7d454 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_scan.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_scan.c @@ -809,7 +809,7 @@ static void wpa_supplicant_scan(void *eloop_ctx, void *timeout_ctx) int_array_concat(¶ms.freqs, tssid->scan_freq); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } freqs_set = 1; @@ -882,7 +882,7 @@ ssid_list_set: "generated frequency list"); params.freqs = wpa_s->next_scan_freqs; } else - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; wpa_setband_scan_freqs(wpa_s, ¶ms); @@ -905,7 +905,7 @@ ssid_list_set: "current operating channels since " "scan_cur_freq is enabled"); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } } @@ -985,7 +985,7 @@ scan: if (num > 0 && num == wpa_s->num_multichan_concurrent) { wpa_dbg(wpa_s, MSG_DEBUG, "Scan only the current operating channels since all channels are already used"); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } } @@ -1002,8 +1002,8 @@ scan: } wpabuf_free(extra_ie); - os_free(params.freqs); - os_free(params.filter_ssids); + os_free_loose(params.freqs); + os_free_loose(params.filter_ssids); if (ret) { wpa_msg(wpa_s, MSG_WARNING, "Failed to initiate AP scan"); @@ -1265,7 +1265,7 @@ int wpa_supplicant_req_sched_scan(struct wpa_supplicant *wpa_s) { wpa_dbg(wpa_s, MSG_DEBUG, "Not enough room for SSID " "filter for sched_scan - drop filter"); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); params.filter_ssids = NULL; params.num_filter_ssids = 0; } @@ -1302,7 +1302,7 @@ int wpa_supplicant_req_sched_scan(struct wpa_supplicant *wpa_s) } if (params.num_filter_ssids == 0) { - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); params.filter_ssids = NULL; } @@ -1385,7 +1385,7 @@ scan: ret = wpa_supplicant_start_sched_scan(wpa_s, scan_params); wpabuf_free(extra_ie); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); if (ret) { wpa_msg(wpa_s, MSG_WARNING, "Failed to initiate sched scan"); if (prev_state != wpa_s->wpa_state) @@ -1839,7 +1839,7 @@ void filter_scan_res(struct wpa_supplicant *wpa_s, res->res[i]->bssid)) { res->res[j++] = res->res[i]; } else { - os_free(res->res[i]); + os_free_loose(res->res[i]); res->res[i] = NULL; } } @@ -2277,21 +2277,21 @@ void wpa_scan_free_params(struct wpa_driver_scan_params *params) return; for (i = 0; i < params->num_ssids; i++) - os_free((u8 *) params->ssids[i].ssid); - os_free((u8 *) params->extra_ies); - os_free(params->freqs); - os_free(params->filter_ssids); - os_free(params->sched_scan_plans); + os_free_loose((u8 *) params->ssids[i].ssid); + os_free_loose((u8 *) params->extra_ies); + os_free_loose(params->freqs); + os_free_loose(params->filter_ssids); + os_free_loose(params->sched_scan_plans); /* * Note: params->mac_addr_mask points to same memory allocation and * must not be freed separately. */ - os_free((u8 *) params->mac_addr); + os_free_loose((u8 *) params->mac_addr); - os_free((u8 *) params->bssid); + os_free_loose((u8 *) params->bssid); - os_free(params); + os_free_loose(params); } #if 0 @@ -2444,7 +2444,7 @@ int wpas_start_pno(struct wpa_supplicant *wpa_s) } ret = wpa_supplicant_start_sched_scan(wpa_s, ¶ms); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); if (ret == 0) wpa_s->pno = 1; else @@ -2480,17 +2480,17 @@ void wpas_mac_addr_rand_scan_clear(struct wpa_supplicant *wpa_s, wpa_s->mac_addr_rand_enable &= ~type; if (type & MAC_ADDR_RAND_SCAN) { - os_free(wpa_s->mac_addr_scan); + os_free_loose(wpa_s->mac_addr_scan); wpa_s->mac_addr_scan = NULL; } if (type & MAC_ADDR_RAND_SCHED_SCAN) { - os_free(wpa_s->mac_addr_sched_scan); + os_free_loose(wpa_s->mac_addr_sched_scan); wpa_s->mac_addr_sched_scan = NULL; } if (type & MAC_ADDR_RAND_PNO) { - os_free(wpa_s->mac_addr_pno); + os_free_loose(wpa_s->mac_addr_pno); wpa_s->mac_addr_pno = NULL; } } @@ -2522,7 +2522,7 @@ int wpas_mac_addr_rand_scan_set(struct wpa_supplicant *wpa_s, wpa_printf(MSG_INFO, "scan: Invalid MAC randomization type=0x%x", type); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -2560,7 +2560,7 @@ int wpas_sched_scan_plans_set(struct wpa_supplicant *wpa_s, const char *cmd) if (!cmd[0]) { wpa_printf(MSG_DEBUG, "Clear sched scan plans"); - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = NULL; wpa_s->sched_scan_plans_num = 0; return 0; @@ -2648,14 +2648,14 @@ int wpas_sched_scan_plans_set(struct wpa_supplicant *wpa_s, const char *cmd) num = wpa_s->max_sched_scan_plans; } - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = scan_plans; wpa_s->sched_scan_plans_num = num; return 0; fail: - os_free(scan_plans); + os_free_loose(scan_plans); wpa_printf(MSG_ERROR, "invalid scan plans list"); return -1; #else /* !CONFIG_FULL_SUPPLICANT */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_supplicant.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_supplicant.c index 58aa23985e52cde0bdb320b74f01743483973f90..4ecb99cf19964626a236b168eb70ecb325d5088d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_supplicant.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpa_supplicant.c @@ -350,11 +350,11 @@ void free_hw_features(struct wpa_supplicant *wpa_s) return; for (i = 0; i < wpa_s->hw.num_modes; i++) { - os_free(wpa_s->hw.modes[i].channels); - os_free(wpa_s->hw.modes[i].rates); + os_free_loose(wpa_s->hw.modes[i].channels); + os_free_loose(wpa_s->hw.modes[i].rates); } - os_free(wpa_s->hw.modes); + os_free_loose(wpa_s->hw.modes); wpa_s->hw.modes = NULL; } @@ -366,7 +366,7 @@ static void free_bss_tmp_disallowed(struct wpa_supplicant *wpa_s) dl_list_for_each_safe(bss, prev, &wpa_s->bss_tmp_disallowed, struct wpa_bss_tmp_disallowed, list) { dl_list_del(&bss->list); - os_free(bss); + os_free_loose(bss); } } @@ -391,10 +391,10 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wpas_notify_network_removed(wpa_s, ssid); } - os_free(wpa_s->confname); + os_free_loose(wpa_s->confname); wpa_s->confname = NULL; - os_free(wpa_s->confanother); + os_free_loose(wpa_s->confanother); wpa_s->confanother = NULL; wpa_sm_set_eapol(wpa_s->wpa, NULL); @@ -450,13 +450,13 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wpa_supplicant_cancel_sched_scan(wpa_s); - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = NULL; - os_free(wpa_s->manual_sched_scan_freqs); + os_free_loose(wpa_s->manual_sched_scan_freqs); wpa_s->manual_sched_scan_freqs = NULL; wpas_mac_addr_rand_scan_clear(wpa_s, MAC_ADDR_RAND_ALL); @@ -465,12 +465,12 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) ieee802_1x_dealloc_kay_sm(wpa_s); - os_free(wpa_s->bssid_filter); + os_free_loose(wpa_s->bssid_filter); wpa_s->bssid_filter = NULL; - os_free(wpa_s->disallow_aps_bssid); + os_free_loose(wpa_s->disallow_aps_bssid); wpa_s->disallow_aps_bssid = NULL; - os_free(wpa_s->disallow_aps_ssid); + os_free_loose(wpa_s->disallow_aps_ssid); wpa_s->disallow_aps_ssid = NULL; wnm_bss_keep_alive_deinit(wpa_s); @@ -478,7 +478,7 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wnm_deallocate_memory(wpa_s); #endif /* CONFIG_WNM */ - os_free(wpa_s->last_scan_res); + os_free_loose(wpa_s->last_scan_res); wpa_s->last_scan_res = NULL; #ifdef CONFIG_HS20 @@ -493,7 +493,7 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wmm_ac_notify_disassoc(wpa_s); wpa_s->sched_scan_plans_num = 0; - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = NULL; @@ -1374,7 +1374,7 @@ void wpas_connect_work_free(struct wpa_connect_work *cwork) { if (cwork == NULL) return; - os_free(cwork); + os_free_loose(cwork); } @@ -1604,7 +1604,7 @@ void wpa_supplicant_associate(struct wpa_supplicant *wpa_s, if (radio_add_work(wpa_s, bss ? bss->freq : 0, "connect", 1, wpas_start_assoc_cb, cwork) < 0) { - os_free(cwork); + os_free_loose(cwork); } } @@ -2822,7 +2822,7 @@ void wpa_supplicant_select_network(struct wpa_supplicant *wpa_s, * Don't optimize next scan freqs since a new ESS has been * selected. */ - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; } else { wpa_s->connect_without_scan = NULL; @@ -3834,7 +3834,7 @@ static void radio_work_free(struct wpa_radio_work *work) } dl_list_del(&work->list); - os_free(work); + os_free_loose(work); } @@ -4029,7 +4029,7 @@ static void radio_remove_interface(struct wpa_supplicant *wpa_s) wpa_printf(MSG_DEBUG, "Remove radio %s", radio->name); eloop_cancel_timeout(radio_start_next_work, radio, NULL); - os_free(radio); + os_free_loose(radio); } @@ -4257,19 +4257,19 @@ static int wpa_supplicant_init_iface(struct wpa_supplicant *wpa_s, * line. */ if (iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = os_strdup(iface->ctrl_interface); } if (iface->driver_param) { - os_free(wpa_s->conf->driver_param); + os_free_loose(wpa_s->conf->driver_param); wpa_s->conf->driver_param = os_strdup(iface->driver_param); } if (iface->p2p_mgmt && !iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = NULL; } } else{ @@ -4282,19 +4282,19 @@ static int wpa_supplicant_init_iface(struct wpa_supplicant *wpa_s, * line. */ if (iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = os_strdup(iface->ctrl_interface); } if (iface->driver_param) { - os_free(wpa_s->conf->driver_param); + os_free_loose(wpa_s->conf->driver_param); wpa_s->conf->driver_param = os_strdup(iface->driver_param); } if (iface->p2p_mgmt && !iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = NULL; } } @@ -4585,13 +4585,13 @@ static void wpa_supplicant_deinit_iface(struct wpa_supplicant *wpa_s, wpa_s->conf = NULL; } - os_free(wpa_s->ssids_from_scan_req); + os_free_loose(wpa_s->ssids_from_scan_req); #if !CFG_NEW_SUPP wpa_s->ssids_from_scan_req = 0; wpas_connect_ssid = 0; #endif - os_free(wpa_s); + os_free_loose(wpa_s); } @@ -4650,7 +4650,7 @@ static int wpa_supplicant_match_existing(struct wpa_global *global) iface = wpa_supplicant_match_iface(global, ifi->if_name); if (iface) { wpa_s = wpa_supplicant_add_iface(global, iface, NULL); - os_free(iface); + os_free_loose(iface); if (wpa_s) wpa_s->matched = 1; } @@ -4803,7 +4803,7 @@ int wpa_supplicant_remove_iface(struct wpa_global *global, #ifdef CONFIG_MESH if (mesh_if_created) { wpa_drv_if_remove(global->ifaces, WPA_IF_MESH, ifname); - os_free(ifname); + os_free_loose(ifname); } #endif /* CONFIG_MESH */ @@ -5072,7 +5072,7 @@ void wpa_supplicant_deinit(struct wpa_global *global) if(wpa_drivers[i]->global_deinit) wpa_drivers[i]->global_deinit(global->drv_priv[i]); } - os_free(global->drv_priv); + os_free_loose(global->drv_priv); random_deinit(); @@ -5081,24 +5081,24 @@ void wpa_supplicant_deinit(struct wpa_global *global) if (global->params.pid_file) { os_daemonize_terminate(global->params.pid_file); - os_free(global->params.pid_file); + os_free_loose(global->params.pid_file); } - os_free(global->params.ctrl_interface); - os_free(global->params.ctrl_interface_group); - os_free(global->params.override_driver); - os_free(global->params.override_ctrl_interface); + os_free_loose(global->params.ctrl_interface); + os_free_loose(global->params.ctrl_interface_group); + os_free_loose(global->params.override_driver); + os_free_loose(global->params.override_ctrl_interface); #ifdef CONFIG_MATCH_IFACE - os_free(global->params.match_ifaces); + os_free_loose(global->params.match_ifaces); #endif /* CONFIG_MATCH_IFACE */ #ifdef CONFIG_P2P - os_free(global->params.conf_p2p_dev); + os_free_loose(global->params.conf_p2p_dev); #endif /* CONFIG_P2P */ - os_free(global->p2p_disallow_freq.range); - os_free(global->p2p_go_avoid_freq.range); - os_free(global->add_psk); + os_free_loose(global->p2p_disallow_freq.range); + os_free_loose(global->p2p_go_avoid_freq.range); + os_free_loose(global->add_psk); - os_free(global); + os_free_loose(global); wpa_debug_close_syslog(); wpa_debug_close_file(); wpa_debug_close_linux_tracing(); @@ -5168,7 +5168,7 @@ static int * get_bss_freqs_in_ess(struct wpa_supplicant *wpa_s) } if (num_freqs == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } @@ -5231,7 +5231,7 @@ void wpas_connection_failed(struct wpa_supplicant *wpa_s, const u8 *bssid) * used in this ESS based on previous scans to speed up * common load balancing use case. */ - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = freqs; } } @@ -5638,7 +5638,7 @@ int get_shared_radio_freqs(struct wpa_supplicant *wpa_s, for (i = 0; i < num; i++) freq_array[i] = freqs_data[i].freq; - os_free(freqs_data); + os_free_loose(freqs_data); return num; } @@ -6273,7 +6273,7 @@ int wpa_is_bss_tmp_disallowed(struct wpa_supplicant *wpa_s, const u8 *bssid) if (!os_reltime_before(&now, &tmp->disallowed_until)) { /* This BSS is not disallowed anymore */ dl_list_del(&tmp->list); - os_free(tmp); + os_free_loose(tmp); continue; } if (os_memcmp(bssid, tmp->bssid, ETH_ALEN) == 0) { diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpas_glue.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpas_glue.c index babfa72e779fc58940166095874f9948f913fe58..5792b1ecf797e53dfa5ffc9de263dfda2ec4cf02 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpas_glue.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd-2.5/wpa_supplicant/wpas_glue.c @@ -79,7 +79,7 @@ static int wpa_ether_send(struct wpa_supplicant *wpa_s, const u8 *dest, wpa_snprintf_hex(hex, hex_len, buf, len); wpa_msg(wpa_s, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(dest), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -184,7 +184,7 @@ static int wpa_supplicant_eapol_send(void *ctx, int type, const u8 *buf, wpa_printf(MSG_DEBUG, "TX EAPOL: dst=" MACSTR, MAC2STR(dst)); wpa_hexdump(MSG_MSGDUMP, "TX EAPOL", msg, msglen); res = wpa_ether_send(wpa_s, dst, ETH_P_EAPOL, msg, msglen); - os_free(msg); + os_free_loose(msg); return res; } @@ -553,7 +553,7 @@ static int wpa_supplicant_send_ft_action(void *ctx, u8 action, ret = wpa_drv_send_action(wpa_s, wpa_s->assoc_freq, 0, wpa_s->bssid, wpa_s->own_addr, wpa_s->bssid, data, data_len, 0); - os_free(data); + os_free_loose(data); return ret; } @@ -791,7 +791,7 @@ void wpas_send_ctrl_req(struct wpa_supplicant *wpa_s, struct wpa_ssid *ssid, len = os_snprintf(buf, buflen, "%s-%d:%s needed for SSID ", field_name, ssid->id, txt); if (os_snprintf_error(buflen, len)) { - os_free(buf); + os_free_loose(buf); return; } if (ssid->ssid && buflen > len + ssid->ssid_len) { @@ -801,7 +801,7 @@ void wpas_send_ctrl_req(struct wpa_supplicant *wpa_s, struct wpa_ssid *ssid, } buf[buflen - 1] = '\0'; wpa_msg(wpa_s, MSG_INFO, WPA_CTRL_REQ "%s", buf); - os_free(buf); + os_free_loose(buf); } @@ -919,7 +919,7 @@ static void wpa_supplicant_set_anon_id(void *ctx, const u8 *id, size_t len) wpa_snprintf_hex(str, len * 2 + 1, id, len); res = wpa_config_set(wpa_s->current_ssid, "anonymous_identity", str, 0); - os_free(str); + os_free_loose(str); if (res < 0) return; } @@ -975,7 +975,7 @@ int wpa_supplicant_init_eapol(struct wpa_supplicant *wpa_s) ctx->cb_ctx = wpa_s; wpa_s->eapol = eapol_sm_init(ctx); if (wpa_s->eapol == NULL) { - os_free(ctx); + os_free_loose(ctx); wpa_printf(MSG_ERROR, "Failed to initialize EAPOL state " "machines."); return -1; @@ -1064,7 +1064,7 @@ int wpa_supplicant_init_wpa(struct wpa_supplicant *wpa_s) if (wpa_s->wpa == NULL) { wpa_printf(MSG_ERROR, "Failed to initialize WPA state " "machine"); - os_free(ctx); + os_free_loose(ctx); return -1; } #endif /* CONFIG_NO_WPA */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/hostapd_intf/hostapd_intf.c b/drivers/hal/beken/beken72XX_HAL/func/hostapd_intf/hostapd_intf.c index d3ce0c9b465857e0cf28d7dc8af80663d86a23d4..08f2197a725565c93bea8d29f0b20c7fe8b097cd 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/hostapd_intf/hostapd_intf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/hostapd_intf/hostapd_intf.c @@ -7,7 +7,7 @@ #include "fake_socket.h" #include "uart_pub.h" #include "ieee802_11_defs.h" -#include "driver.h" +#include "wpa_supplicant-2.9\src\drivers\driver.h" #include "driver_beken.h" #include "hostapd_cfg.h" #include "rw_pub.h" @@ -42,7 +42,6 @@ void bk_ap_no_password_connected_register_cb(bk_ap_no_password_cb_t func) bk_ap_no_password_connected = func; } - struct scanu_rst_upload *s_scan_result_upload_ptr; struct mm_bcn_change_req *hadp_intf_get_bcn_change_req(uint8_t vif_id, struct beacon_data *bcn_info) @@ -100,10 +99,10 @@ struct mm_bcn_change_req *hadp_intf_get_bcn_change_req(uint8_t vif_id, struct be exit_get_failed: if(req) - os_free(req); + os_free_loose(req); if(beacon_ptr) - os_free(beacon_ptr); + os_free_loose(beacon_ptr); return NULL; } @@ -199,7 +198,7 @@ int hapd_intf_sta_add(struct prism2_hostapd_param *param, int len) rwm_flush_txing_list(cfm->sta_idx); #endif } - os_free(cfm); + os_free_loose(cfm); return ret; } @@ -315,21 +314,23 @@ int hapd_intf_add_key(struct prism2_hostapd_param *param, int len) key_param.sta_idx, key_param.inst_nbr, key_param.key_idx); ps_set_key_prevent(); + mcu_prevent_set(MCU_PS_ADD_KEY); UINT32 reg = RF_HOLD_BY_KEY_BIT; + sddev_control(SCTRL_DEV_NAME, CMD_RF_HOLD_BIT_SET, ®); #if CFG_USE_STA_PS power_save_rf_dtim_manual_do_wakeup(); #endif - ret = rw_msg_send_key_add(&key_param, cfm); + if(!ret && (cfm->status == CO_OK)) { WPAS_PRT("add hw key idx:%d\r\n", cfm->hw_key_idx); } - os_free(cfm); + os_free_loose(cfm); return ret; } @@ -377,7 +378,7 @@ int hapd_intf_add_vif(struct prism2_hostapd_param *param, int len) if(ret || (cfm->status != CO_OK)) { SAAP_PRT("MM_ADD_IF_REQ failed!\r\n"); - os_free(cfm); + os_free_loose(cfm); return -1; } SAAP_PRT("hapd_intf_add_vif,type:%d, s:%d, id:%d\r\n", @@ -388,7 +389,7 @@ int hapd_intf_add_vif(struct prism2_hostapd_param *param, int len) *(param->u.add_if.indx_ptr) = cfm->inst_nbr; - os_free(cfm); + os_free_loose(cfm); return 0; } @@ -420,7 +421,7 @@ int hapd_intf_start_apm(struct prism2_hostapd_param *param, int len) if(ret) { SAAP_PRT("hapd_intf_start_apm failed!\r\n"); - os_free(cfm); + os_free_loose(cfm); return -1; } @@ -430,7 +431,7 @@ int hapd_intf_start_apm(struct prism2_hostapd_param *param, int len) cfm->ch_idx, cfm->bcmc_idx); } - os_free(cfm); + os_free_loose(cfm); return 0; } @@ -669,7 +670,7 @@ int wpa_send_auth_req(struct prism2_hostapd_param *param, int len) } ret = rw_msg_send_sm_auth_req(auth_param); - os_free(auth_param); + os_free_loose(auth_param); return ret; } @@ -711,7 +712,7 @@ int wpa_send_assoc_req(struct prism2_hostapd_param *param, int len) assoc_param->auth_type = param->u.assoc_req.auth_alg; ret = sa_station_send_associate_cmd(assoc_param); - os_free(assoc_param); + os_free_loose(assoc_param); //assoc_exit: if(s_scan_result_upload_ptr) { @@ -758,7 +759,7 @@ int wpa_send_assoc_req(struct prism2_hostapd_param *param, int len) connect_param->auth_type = param->u.assoc_req.auth_alg; ret = sa_station_send_associate_cmd(connect_param); - os_free(connect_param); + os_free_loose(connect_param); #if CFG_ROLE_LAUNCH assoc_exit: #endif @@ -823,7 +824,7 @@ int wpa_get_bss_info(struct prism2_hostapd_param *param, int len) os_memcpy(param->u.bss_info.bssid, cfm->bssid, ETH_ALEN); ssid_len = MIN(SSID_MAX_LEN, os_strlen((char *)cfm->ssid)); os_memcpy(param->u.bss_info.ssid, cfm->ssid, ssid_len); - os_free(cfm); + os_free_loose(cfm); return 0; } @@ -1188,17 +1189,17 @@ void hapd_intf_ke_rx_handle(int dummy) rwm_transfer(type_ptr->vif_index, pd_ptr, payload_size, type_ptr->sync, type_ptr->args); - os_free(pd_ptr); + os_free_loose(pd_ptr); } - os_free(type_ptr); + os_free_loose(type_ptr); return; kmsg_malloc_fail: - os_free(buf); + os_free_loose(buf); exit: - os_free(type_ptr); + os_free_loose(type_ptr); return; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/include/fake_clock_pub.h b/drivers/hal/beken/beken72XX_HAL/func/include/fake_clock_pub.h index cdaedc3d07caca9160683879379ac6ea96d0f2dd..d82f46600875c221259a730dd920ae410589b736 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/include/fake_clock_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/func/include/fake_clock_pub.h @@ -2,6 +2,7 @@ #define _FAKE_CLOCK_PUB_H_ #include "include.h" +#include "pwm_pub.h" typedef enum { diff --git a/drivers/hal/beken/beken72XX_HAL/func/include/func_pub.h b/drivers/hal/beken/beken72XX_HAL/func/include/func_pub.h index 90dee4b9ef37abca0a926823c4c00a60b1341ccc..a6f67c7d407aca5dda0550c24d074a877fc9fdcb 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/include/func_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/func/include/func_pub.h @@ -1,6 +1,8 @@ #ifndef _FUNC_PUB_H_ #define _FUNC_PUB_H_ +#include "typedef.h" + #define FUNC_DEBUG #ifdef FUNC_DEBUG #define FUNC_PRT os_printf @@ -10,6 +12,7 @@ #define FUNC_WPRT os_null_printf #endif + extern UINT32 func_init_extended(void); extern UINT32 func_init_basic(void); #endif // _FUNC_PUB_H_ diff --git a/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.c b/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.c index c79995b1c3fa9f09d59d5863e0a21d580b83b1b2..670c69d604fd88be4456ce2ec16d822653aecd4d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.c +++ b/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.c @@ -441,7 +441,7 @@ void rl_enter_handler(void *left, void *right) _ap_request_enter(ap_param, ap_completion); } - os_free(ptr); + os_free_loose(ptr); ptr = 0; } @@ -607,7 +607,7 @@ RL_ENTITY_T *rl_alloc_entity(LAUNCH_REQ *param, FUNC_1PARAM_PTR completion) void rl_free_entity(RL_ENTITY_T *d) { - os_free(d); + os_free_loose(d); } uint32_t rl_pre_sta_stop_launch(void) diff --git a/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.h b/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.h index d6aa9ef90c2f40c138094c02de35a6338072ea6b..e8df96255f90d564dea2fc76f8111648c979abd6 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.h +++ b/drivers/hal/beken/beken72XX_HAL/func/joint_up/role_launch.h @@ -3,7 +3,7 @@ #include "wlan_ui_pub.h" -#define JL_DEBUG 0 +#define JL_DEBUG 1 #if JL_DEBUG #define JL_PRT os_printf diff --git a/drivers/hal/beken/beken72XX_HAL/func/key/key_main.c b/drivers/hal/beken/beken72XX_HAL/func/key/key_main.c index ea66c79cd7cc2d34aec412477826f3e03cffb5d8..098578446ae5f5016a2f7ff76084697f15e102d7 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/key/key_main.c +++ b/drivers/hal/beken/beken72XX_HAL/func/key/key_main.c @@ -183,7 +183,7 @@ int matrix_key_item_configure(KEYITEM key, void short_press(void *), void double if (result < 0) { KEY_PRT("button_start failed\n"); - os_free(handle); + os_free_loose(handle); return kGeneralErr; } @@ -220,7 +220,7 @@ int key_item_configure(uint32_t gpio, void short_press(void *), void double_pres if (result < 0) { KEY_PRT("button_start failed\n"); - os_free(handle); + os_free_loose(handle); return kGeneralErr; } @@ -240,7 +240,7 @@ int key_item_unconfigure(uint32_t gpio) break; } button_stop(handle); - os_free(handle); + os_free_loose(handle); } return kNoErr; diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/dhcpd/dhcp-server.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/dhcpd/dhcp-server.c index 5084fa733022de049e7735674750b9b1d70b326e..313d9c1a18b00895326153b05f2710b337bbb3e8 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/dhcpd/dhcp-server.c +++ b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/dhcpd/dhcp-server.c @@ -10,7 +10,7 @@ #include "lwip/etharp.h" #define os_mem_alloc os_malloc -#define os_mem_free os_free +#define os_mem_free os_free_loose #define SEND_RESPONSE(w,x,y,z) send_response(w,x,y,z) #define DEFAULT_DHCP_ADDRESS_TIMEOUT (60U*60U*1U) /* 1 hour */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/CHANGELOG b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/CHANGELOG deleted file mode 100644 index 3a277195cecc4cceae772b6100fa25ce82464bdc..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/CHANGELOG +++ /dev/null @@ -1,4276 +0,0 @@ -HISTORY - -(git master) - - * [Enter new changes just after this line - do not remove this line] - -(STABLE-2.0.2) - - ++ New features: - - 2017-02-10: Dirk Ziegelmeier - * Implement task #14367: Hooks need a better place to be defined: - We now have a #define for a header file name that is #included in every .c - file that provides hooks. - - ++ Bugfixes: - - 2017-03-08 - * tcp: do not keep sending SYNs when getting ACKs - - 2017-03-08: Joel Cunningham - * tcp: Initialize ssthresh to TCP_SND_BUF (bug #50476) - - 2017-03-01: Simon Goldschmidt - * httpd: LWIP_HTTPD_POST_MANUAL_WND: fixed double-free when httpd_post_data_recved - is called nested from httpd_post_receive_data() (bug #50424) - - 2017-02-28: David van Moolenbroek/Simon Goldschmidt - * tcp: fixed bug #50418: LWIP_EVENT_API: fix invalid calbacks for SYN_RCVD pcb - - 2017-02-17: Simon Goldschmidt - * dns: Improved DNS_LOCAL_HOSTLIST interface (bug #50325) - - 2017-02-16: Simon Goldschmidt - * LWIP_NETCONN_FULLDUPLEX: fixed shutdown during write (bug #50274) - - 2017-02-13: Simon Goldschmidt/Dirk Ziegelmeier - * For tiny targtes, LWIP_RAND is optional (fix compile time checks) - - 2017-02-10: Simon Goldschmidt - * tcp: Fixed bug #47485 (tcp_close() should not fail on memory error) by retrying - to send FIN from tcp_fasttmr - - 2017-02-09: Simon Goldschmidt - * sockets: Fixed bug #44032 (LWIP_NETCONN_FULLDUPLEX: select might work on - invalid/reused socket) by not allowing to reallocate a socket that has - "select_waiting != 0" - - 2017-02-09: Simon Goldschmidt - * httpd: Fixed bug #50059 (httpd LWIP_HTTPD_SUPPORT_11_KEEPALIVE vs. - LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED) - - 2017-02-08: Dirk Ziegelmeier - * Rename "IPv6 mapped IPv4 addresses" to their correct name from RFC4191: - "IPv4-mapped IPv6 address" - - 2017-02-08: Luc Revardel - * mld6.c: Fix bug #50220 (mld6_leavegroup does not send ICMP6_TYPE_MLD, even - if last reporter) - - 2017-02-08: David van Moolenbroek - * ip6.c: Patch #9250: fix source substitution in ip6_output_if() - - 2017-02-08: Simon Goldschmidt - * tcp_out.c: Fixed bug #50090 (last_unsent->oversize_left can become wrong value - in tcp_write error path) - - 2017-02-02: Dirk Ziegelmeier - * Fix bug #50206: UDP Netconn bind to IP6_ADDR_ANY fails - - 2017-01-18: Dirk Ziegelmeier - * Fix zero-copy RX, see bug bug #50064. PBUF_REFs were not supported as ARP requests. - - 2017-01-15: Axel Lin, Dirk Ziegelmeier - * minor bug fixes in mqtt - - 2017-01-11: Knut Andre Tidemann - * sockets/netconn: fix broken default ICMPv6 handling of checksums - -(STABLE-2.0.1) - - ++ New features: - - 2016-12-31: Simon Goldschmidt - * tcp.h/.c: added function tcp_listen_with_backlog_and_err() to get the error - reason when listening fails (bug #49861) - - 2016-12-20: Erik Andersen - * Add MQTT client - - 2016-12-14: Jan Breuer: - * opt.h, ndc.h/.c: add support for RDNSS option (as per RFC 6106) - - 2016-12-14: David van Moolenbroek - * opt.h, nd6.c: Added LWIP_HOOK_ND6_GET_GW() - - 2016-12-09: Dirk Ziegelmeier - * ip6_frag.c: Implemented support for LWIP_NETIF_TX_SINGLE_PBUF - - 2016-12-09: Simon Goldschmidt - * dns.c: added one-shot multicast DNS queries - - 2016-11-24: Ambroz Bizjak, David van Moolenbroek - * tcp_out.c: Optimize passing contiguous nocopy buffers to tcp_write (bug #46290) - - 2016-11-16: Dirk Ziegelmeier - * sockets.c: added support for IPv6 mapped IPv4 addresses - - ++ Bugfixes: - - 2016-12-16: Thomas Mueller - * api_lib.c: fixed race condition in return value of netconn_gethostbyname() - (and thus also lwip_gethostbyname/_r() and lwip_getaddrinfo()) - - 2016-12-15: David van Moolenbroek - * opt.h, tcp: added LWIP_HOOK_TCP_ISN() to implement less predictable initial - sequence numbers (see contrib/addons/tcp_isn for an example implementation) - - 2016-12-05: Dirk Ziegelmeier - * fixed compiling with IPv4 disabled (IPv6 only case) - - 2016-11-28: Simon Goldschmidt - * api_lib.c: fixed bug #49725 (send-timeout: netconn_write() can return - ERR_OK without all bytes being written) - - 2016-11-28: Ambroz Bizjak - * tcpi_in.c: fixed bug #49717 (window size in received SYN and SYN-ACK - assumed scaled) - - 2016-11-25: Simon Goldschmidt - * dhcp.c: fixed bug #49676 (Possible endless loop when parsing dhcp options) - - 2016-11-23: Dirk Ziegelmeier - * udp.c: fixed bug #49662: multicast traffic is now only received on a UDP PCB - (and therefore on a UDP socket/netconn) when the PCB is bound to IP_ADDR_ANY - - 2016-11-16: Dirk Ziegelmeier - * *: Fixed dual-stack behaviour, IPv6 mapped IPv4 support in socket API - - 2016-11-14: Joel Cunningham - * tcp_out.c: fixed bug #49533 (start persist timer when unsent seg can't fit - in window) - - 2016-11-16: Roberto Barbieri Carrera - * autoip.c: fixed bug #49610 (sometimes AutoIP fails to reuse the same address) - - 2016-11-11: Dirk Ziegelmeier - * sockets.c: fixed bug #49578 (dropping multicast membership does not work - with LWIP_SOCKET_OFFSET) - -(STABLE-2.0.0) - - ++ New features: - - 2016-07-27: Simon Goldschmidt - * opt.h, timeouts.h/.c: added LWIP_TIMERS_CUSTOM to override the default - implementation of timeouts - - 2016-07-xx: Dirk Ziegelmeier - * Large overhaul of doxygen documentation - - 2016-04-05: Simon Goldschmidt - * timers.h/.c: prepare for overriding current timeout implementation: all - stack-internal caclic timers are avaliable in the lwip_cyclic_timers array - - 2016-03-23: Simon Goldschmidt - * tcp: call accept-callback with ERR_MEM when allocating a pcb fails on - passive open to inform the application about this error - ATTENTION: applications have to handle NULL pcb in accept callback! - - 2016-02-22: Ivan Delamer - * Initial 6LoWPAN support - - 2016-02-XX to 2016-03-XX: Dirk Ziegelmeier - * Cleanup TCPIP thread sync methods in a way that it is possibe to use them - in arbitrary code that needs things to be done in TCPIP thread. Used to - decouple netconn, netif, ppp and 6LoWPAN from LWIP core. - - 2016-02-XX: Dirk Ziegelmeier - * Implement dual-stack support in RAW, UDP and TCP. Add new IP address - type IPADDR_ANY_TYPE for this. Netconn/Socket API: Dual-stack is - automatically supported when an IPv6 netconn/socket is created. - - 2015-12-26: Martin Hentschel and Dirk Ziegelmeier - * Rewrite SNMP agent. SNMPv2c + MIB compiler. - - 2015-11-12: Dirk Ziegelmeier - * Decouple SNMP stack from lwIP core and move stack to apps/ directory. - Breaking change: Users have to call snmp_init() now! - - 2015-11-12: Dirk Ziegelmeier - * Implement possibility to declare private memory pools. This is useful to - decouple some apps from the core (SNMP stack) or make contrib app usage - simpler (httpserver_raw) - - 2015-10-09: Simon Goldschmidt - * started to move "private" header files containing implementation details to - "lwip/priv/" include directory to seperate the API from the implementation. - - 2015-10-07: Simon Goldschmidt - * added sntp client as first "supported" application layer protocol implementation - added 'apps' folder - - 2015-09-30: Dirk Ziegelmeier - * snmp_structs.h, mib_structs.c, mib2.c: snmp: fixed ugly inheritance - implementation by aggregating the "base class" (struct mib_node) in all - derived node classes to get more type-safe code - - 2015-09-23: Simon Goldschmidt - * netif.h/.c, nd6.c: task #13729: Convert netif addresses (IPv4 & IPv6) to - ip_addr_t (so they can be used without conversion/temporary storage) - - 2015-09-08: Dirk Ziegelmeier - * snmp: Separate mib2 counter/table callbacks from snmp agent. This both cleans - up the code and should allow integration of a 3rd party agent/mib2. Simple - counters are kept in MIB2_STATS, tree/table change function prototypes moved to - snmp_mib2.h. - - 2015-09-03: Simon Goldschmidt - * opt.h, dns.h/.c: DNS/IPv6: added support for AAAA records - - 2015-09-01: Simon Goldschmidt - * task #12178: hardware checksum capabilities can be configured per netif - (use NETIF_SET_CHECKSUM_CTRL() in your netif's init function) - - 2015-08-30: Simon Goldschmidt - * PBUF_REF with "custom" pbufs is now supported for RX pbufs (see pcapif in - contrib for an example, LWIP_SUPPORT_CUSTOM_PBUF is required) - - 2015-08-30: Simon Goldschmidt - * support IPv4 source based routing: define LWIP_HOOK_IP4_ROUTE_SRC to point - to a routing function - - 2015-08-05: Simon Goldschmidt - * many files: allow multicast socket options IP_MULTICAST_TTL, IP_MULTICAST_IF - and IP_MULTICAST_LOOP to be used without IGMP - - 2015-04-24: Simon Goldschmidt - * dhcp.h/c, autoip.h/.c: added functions dhcp/autoip_supplied_address() to - check for the source of address assignment (replacement for NETIF_FLAG_DHCP) - - 2015-04-10: Simon Goldschmidt - * many files: task #13480: added LWIP_IPV4 define - IPv4 can be disabled, - leaving an IPv6-only stack - - 2015-04-09: Simon Goldschmidt - * nearly all files: task #12722 (improve IPv4/v6 address handling): renamed - ip_addr_t to ip4_addr_t, renamed ipX_addr_t to ip_addr_t and added IP - version; ip_addr_t is used for all generic IP addresses for the API, - ip(4/6)_addr_t are only used internally or when initializing netifs or when - calling version-related functions - - 2015-03-24: Simon Goldschmidt - * opt.h, ip4_addr.h, ip4.c, ip6.c: loopif is not required for loopback traffic - any more but passed through any netif (ENABLE_LOOPBACK has to be enabled) - - 2015-03-23: Simon Goldschmidt - * opt.h, etharp.c: with ETHARP_TABLE_MATCH_NETIF== 1, duplicate (Auto)-IP - addresses on multiple netifs should now be working correctly (if correctly - addressed by routing, that is) - - 2015-03-23: Simon Goldschmidt - * etharp.c: Stable etharp entries that are about to expire are now refreshed - using unicast to prevent unnecessary broadcast. Only if no answer is received - after 15 seconds, broadcast is used. - - 2015-03-06: Philip Gladstone - * netif.h/.c: patch #8359 (Provide utility function to add an IPv6 address to - an interface) - - 2015-03-05: Simon Goldschmidt - * netif.c, ip4.c, dhcp.c, autoip.c: fixed bug #37068 (netif up/down handling - is unclear): correclty separated administrative status of a netif (up/down) - from 'valid address' status - ATTENTION: netif_set_up() now always has to be called, even when dhcp/autoip - is used! - - 2015-02-26: patch by TabascoEye - * netif.c, udp.h/.c: fixed bug #40753 (re-bind UDP pcbs on change of IP address) - - 2015-02-22: chrysn, Simon Goldschmidt - * *.*: Changed nearly all functions taking 'ip(X)_addr_t' pointer to take - const pointers (changed user callbacks: raw_recv_fn, udp_recv_fn; changed - port callbacks: netif_output_fn, netif_igmp_mac_filter_fn) - - 2015-02-19: Ivan Delamer - * netif.h, dhcp.c: Removed unused netif flag for DHCP. The preferred way to evaluate - if DHCP is active is through netif->dhcp field. - - 2015-02-19: Ivan Delamer - * netif.h, slipif.c, ppp.c: Removed unused netif flag for point to point connections - - 2015-02-18: Simon Goldschmidt - * api_lib.c: fixed bug #37958 "netconn API doesn't handle correctly - connections half-closed by peer" - - 2015-02-18: Simon Goldschmidt - * tcp.c: tcp_alloc() prefers killing CLOSING/LAST_ACK over active connections - (see bug #39565) - - 2015-02-16: Claudius Zingerli, Sergio Caprile - * opt.h, dhcp.h/.c: patch #8361 "Add support for NTP option in DHCP" - - 2015-02-14: Simon Goldschmidt - * opt.h, snmp*: added support for write-access community and dedicated - community for sending traps - - 2015-02-13: Simon Goldschmidt - * opt.h, memp.c: added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when - a memp pool was empty and an item is now available - - 2015-02-13: Simon Goldschmidt - * opt.h, pbuf.h/.c, etharp.c: Added the option PBUF_LINK_ENCAPSULATION_HLEN to - allocate additional header space for TX on netifs requiring additional headers - - 2015-02-12: chrysn - * timers.h/.c: introduce sys_timeouts_sleeptime (returns the time left before - the next timeout is due, for NO_SYS==1) - - 2015-02-11: Nick van Ijzendoorn - * opt.h, sockets.h/c: patch #7702 "Include ability to increase the socket number - with defined offset" - - 2015-02-11: Frederick Baksik - * opt.h, def.h, others: patch #8423 "arch/perf.h" should be made an optional item - - 2015-02-11: Simon Goldschmidt - * api_msg.c, opt.h: started to implement fullduplex sockets/netconns - (note that this is highly unstable yet!) - - 2015-01-17: Simon Goldschmidt - * api: allow enabling socket API without (public) netconn API - netconn API is - still used by sockets, but keeping it private (static) should allow better - compiler optimizations - - 2015-01-16: Simon Goldschmidt - * tcp_in.c: fixed bug #20506 "Initial congestion window is very small" again - by implementing the calculation formula from RFC3390 - - 2014-12-10: Simon Goldschmidt - * api: added option LWIP_NETCONN_SEM_PER_THREAD to use a semaphore per thread - instead of using one per netconn and per select call - - 2014-12-08: Simon Goldschmidt - * ip6.h: fixed bug #43778: IPv6 header version not set on 16-bit platform - (macro IP6H_VTCFL_SET()) - - 2014-12-08: Simon Goldschmidt - * icmp.c, ip4.c, pbuf.c, udp.c, pbuf.h: task #11472 Support PBUF_REF for RX - (IPv6 and IPv4/v6 reassembly might not work yet) - - 2014-11-06: Simon Goldschmidt - * sockets.c/.h, init.c: lwip_socket_init() is not needed any more - -> compatibility define - - 2014-09-16: Simon Goldschmidt - * dns.c, opt.h: reduced ram usage by parsing DNS responses in place - - 2014-09-16: Simon Goldschmidt - * pbuf.h/.c: added pbuf_take_at() and pbuf_put_at() - - 2014-09-15: Simon Goldschmidt - * dns.c: added source port randomization to make the DNS client more robust - (see bug #43144) - - 2013-09-02: Simon Goldschmidt - * arch.h and many other files: added optional macros PACK_STRUCT_FLD_8() and - PACK_STRUCT_FLD_S() to prevent gcc 4 from warning about struct members that - do not need packing - - 2013-08-19: Simon Goldschmidt - * netif.h: bug #42998: made NETIF_MAX_HWADDR_LEN overridable for some special - networks - - 2013-03-17: Simon Goldschmidt (patch by Ghobad Emadi) - * opt.h, etharp.c: Added LWIP_HOOK_ETHARP_GET_GW to implement IPv4 routing with - multiple gateways - - 2013-04-20: Fatih Asici - * opt.h, etharp.h/.c: patch #7993: Added support for transmitting packets - with VLAN headers via hook function LWIP_HOOK_VLAN_SET and to check them - via hook function LWIP_HOOK_VLAN_CHECK - - 2014-02-20: Simon Goldschmidt (based on patch by Artem Pisarenko) - * patch #7885: modification of api modules to support FreeRTOS-MPU - (don't pass stack-pointers to other threads) - - 2014-02-05: Simon Goldschmidt (patch by "xtian" and "alex_ab") - * patch #6537/#7858: TCP window scaling support - - 2014-01-17: Jiri Engelthaler - * icmp, icmp6, opt.h: patch #8027: Completed HW checksuming for IPv4 and - IPv6 ICMP's - - 2012-08-22: Sylvain Rochet - * New PPP stack for lwIP, developed in ppp-new branch. - Based from pppd 2.4.5, released 2009-11-17, with huge changes to match - code size and memory requirements for embedded devices, including: - - Gluing together the previous low-level PPP code in lwIP to pppd 2.4.5, which - is more or less what pppd sys-* files are, so that we get something working - using the unix port. - - Merged some patchs from lwIP Git repository which add interesting features - or fix bugs. - - Merged some patchs from Debian pppd package which add interesting features - or fix bugs. - - Ported PPP timeout handling to the lwIP timers system - - Disabled all the PPP code using filesystem access, replaced in necessary cases - to configuration variables. - - Disabled all the PPP code forking processes. - - Removed IPX support, lwIP does not support IPX. - - Ported and improved random module from the previous PPP port. - - Removed samba TDB (file-driven database) usage, because it needs a filesystem. - - MS-CHAP required a DES implementation, we added the latest PolarSSL DES - implementation which is under a BSD-ish license. - - Also switched to PolarSSL MD4,MD5,SHA1 implementations, which are meant to be - used in embedded devices with reduced memory footprint. - - Removed PPP configuration file parsing support. - - Added macro definition EAP_SUPPORT to make EAP support optional. - - Added macro definition CHAP_SUPPORT to make CHAP support optional. - - Added macro definition MSCHAP_SUPPORT to make MSCHAP support optional. - - Added macro definition PAP_SUPPORT to make PAP support optional. - - Cleared all Linux syscall calls. - - Disabled demand support using a macro, so that it can be ported later. - - Disabled ECP support using a macro, so that it can be ported later. - - Disabled CCP support using a macro, so that it can be ported later. - - Disabled CBCP support using a macro, so that it can be ported later. - - Disabled LQR support using a macro, so that it can be ported later. - - Print packet debug feature optional, through PRINTPKT_SUPPORT - - Removed POSIX signal usage. - - Fully ported PPPoS code from the previous port. - - Fully ported PPPoE code from the previous port. - - Fully ported VJ compression protocol code from the previous port. - - Removed all malloc()/free() use from PPP, replaced by stack usage or PBUF. - - Disabled PPP server support using a macro, so that it can be ported later. - - Switched all PPP debug to lwIP debug system. - - Created PPP Control Block (PPP PCB), removed PPP unit integer everywhere, - removed all global variables everywhere, did everything necessary for - the PPP stack to support more than one PPP session (pppd only support - one session per process). - - Removed the statically allocated output buffer, now using PBUF. - - Improved structure size of all PPP modules, deep analyze of code to reduce - variables size to the bare minimum. Switched all boolean type (char type in - most architecture) to compiler generated bitfields. - - Added PPP IPv6 support, glued lwIP IPv6 support to PPP. - - Now using a persistent netif interface which can then be used in lwIP - functions requiring a netif. - - Now initializing PPP in lwip_init() function. - - Reworked completely the PPP state machine, so that we don't end up in - anymore in inconsistent state, especially with PPPoE. - - Improved the way we handle PPP reconnection after disconnect, cleaning - everything required so that we start the PPP connection again from a - clean state. - - Added PPP holdoff support, allow the lwIP user to wait a little bit before - reconnecting, prevents connection flood, especially when using PPPoL2TP. - - Added PPPoL2TP LAC support (a.k.a. UDP tunnels), adding a VPN client - feature to lwIP, L2TP being a widely used tunnel protocol. - - Switched all used PPP types to lwIP types (u8t, u16t, u32t, ...) - - Added PPP API "sequential" thread-safe API, based from NETIFAPI. - - 2011-07-21: Simon Goldschmidt - * sockets.c, opt.h: (bug #30185): added LWIP_FIONREAD_LINUXMODE that makes - ioctl/FIONREAD return the size of the next pending datagram. - - 2011-05-25: Simon Goldschmidt - * again nearly the whole stack, renamed ip.c to ip4.c, ip_addr.c to ip4_addr.c, - combined ipv4/ipv6 inet_chksum.c, added ip.h, ip_addr.h: Combined IPv4 - and IPv6 code where possible, added defines to access IPv4/IPv6 in non-IP - code so that the code is more readable. - - 2011-05-17: Patch by Ivan Delamer (only checked in by Simon Goldschmidt) - * nearly the whole stack: Finally, we got decent IPv6 support, big thanks to - Ivan! (this is work in progress: we're just post release anyway :-) - - - ++ Bugfixes: - - 2016-08-23: Simon Goldschmidt - * etharp: removed ETHARP_TRUST_IP_MAC since it is insecure and we don't need - it any more after implementing unicast ARP renewal towards arp entry timeout - - 2016-07-20: Simon Goldschmidt - * memp.h/.c: fixed bug #48442 (memp stats don't work for MEMP_MEM_MALLOC) - - 2016-07-21: Simon Goldschmidt (patch by Ambroz Bizjak) - * tcp_in.c, tcp_out.c: fixed bug #48543 (TCP sent callback may prematurely - report sent data when only part of a segment is acked) and don't include - SYN/FIN in snd_buf counter - - 2016-07-19: Simon Goldschmidt - * etharp.c: fixed bug #48477 (ARP input packet might update static entry) - - 2016-07-11: Simon Goldschmidt - * tcp_in.c: fixed bug #48476 (TCP sent callback called wrongly due to picking - up old pcb->acked - - 2016-06-30: Simon Goldschmidt (original patch by Fabian Koch) - * tcp_in.c: fixed bug #48170 (Vulnerable to TCP RST spoofing) - - 2016-05-20: Dirk Ziegelmeier - * sntp.h/.c: Fix return value of sntp_getserver() call to return a pointer - - 2016-04-05: Simon Goldschmidt (patch by Philip Gladstone) - * udp.c: patch #8358: allow more combinations of listening PCB for IPv6 - - 2016-04-05: Simon Goldschmidt - * netconn/socket API: fixed bug# 43739 (Accept not reporting errors about - aborted connections): netconn_accept() returns ERR_ABRT (sockets: ECONNABORTED) - for aborted connections, ERR_CLSD (sockets: EINVAL) if the listening netconn - is closed, which better seems to follow the standard. - - 2016-03-23: Florent Matignon - * dhcp.c: fixed bug #38203: DHCP options are not recorded in all DHCP ack messages - - 2016-03-22: Simon Goldschmidt - * tcp: changed accept handling to be done internally: the application does not - have to call tcp_accepted() any more. Instead, when delaying accept (e.g. sockets - do), call tcp_backlog_delayed()/tcp_backlog_accepted() (fixes bug #46696) - - 2016-03-22: Simon Goldschmidt - * dns.c: ignore dns response parsing errors, only abort resolving for correct - responses or error responses from correct server (bug #47459) - - 2016-03-17: Simon Goldschmidt - * api_msg.c: fixed bug #47448 (netconn/socket leak if RST is received during close) - - 2016-03-17: Joel Cunningham - * api_msg.c: don't fail closing a socket/netconn when failing to allocate the - FIN segment; blocking the calling thread for a while is better than risking - leaking a netconn/socket (see bug #46701) - - 2016-03-16: Joel Cunningham - * tcp_out.c: reset rto timer on fast retransmission - - 2016-03-16: Deomid Ryabkov - * tcp_out.c: fixed bug #46384 Segment size calculation bug with MSS != TCP_MSS - - 2016-03-05: Simon Goldschmidt - * err.h/.c, sockets.c: ERR_IF is not necessarily a fatal error - - 2015-11-19: fix by Kerem Hadimli - * sockets.c: fixed bug #46471: lwip_accept() leaks socket descriptors if new - netconn was already closed because of peer behavior - - 2015-11-12: fix by Valery Ushakov - * tcp_in.c: fixed bug #46365 tcp_accept_null() should call tcp_abort() - - 2015-10-02: Dirk Ziegelmeier/Simon Goldschmidt - * snmp: cleaned up snmp structs API (fixed race conditions from bug #46089, - reduce ram/rom usage of tables): incompatible change for private MIBs - - 2015-09-30: Simon Goldschmidt - * ip4_addr.c: fixed bug #46072: ip4addr_aton() does not check the number range - of all address parts - - 2015-08-28: Simon Goldschmidt - * tcp.c, tcp_in.c: fixed bug #44023: TCP ssthresh value is unclear: ssthresh - is set to the full send window for active open, too, and is updated once - after SYN to ensure the correct send window is used - - 2015-08-28: Simon Goldschmidt - * tcp: fixed bug #45559: Window scaling casts u32_t to u16_t without checks - - 2015-08-26: Simon Goldschmidt - * ip6_frag.h/.c: fixed bug bug #41009: IPv6 reassembly broken on 64-bit platforms: - define IPV6_FRAG_COPYHEADER==1 on these platforms to copy the IPv6 header - instead of referencing it, which gives more room for struct ip6_reass_helper - - 2015-08-25: Simon Goldschmidt - * sockets.c: fixed bug #45827: recvfrom: TCP window is updated with MSG_PEEK - - 2015-08-20: Manoj Kumar - * snmp_msg.h, msg_in.c: fixed bug #43790: Sending octet string of Length >255 - from SNMP agent - - 2015-08-19: Jens Nielsen - * icmp.c, ip4.c, tcp_in.c, udp.c, raw.c: fixed bug #45120: Broadcast & multiple - interfaces handling - - 2015-08-19: Simon Goldschmidt (patch by "Sandra") - * dns.c: fixed bug #45004: dns response without answer might be discarded - - 2015-08-18: Chrysn - * timers.c: patch #8704 fix sys_timeouts_sleeptime function - - 2015-07-01: Erik Ekman - * puf.c: fixed bug #45454 (pbuf_take_at() skips write and returns OK if offset - is at start of pbuf in chain) - - 2015-05-19: Simon Goldschmidt - * dhcp.h/.c: fixed bugs #45140 and #45141 (dhcp was not stopped correctly after - fixing bug #38204) - - 2015-03-21: Simon Goldschmidt (patch by Homyak) - * tcp_in.c: fixed bug #44766 (LWIP_WND_SCALE: tcphdr->wnd was not scaled in - two places) - - 2015-03-21: Simon Goldschmidt - * tcp_impl.h, tcp.c, tcp_in.c: fixed bug #41318 (Bad memory ref in tcp_input() - after tcp_close()) - - 2015-03-21: Simon Goldschmidt - * tcp_in.c: fixed bug #38468 (tcp_sent() not called on half-open connection for - data ACKed with the same ack as FIN) - - 2015-03-21: Simon Goldschmidt (patch by Christoffer Lind) - * dhcp.h/.c: fixed bug #38204 (DHCP lease time not handled correctly) - - 2015-03-20: Simon Goldschmidt - * dhcp.c: fixed bug #38714 (Missing option and client address in DHCPRELEASE message) - - 2015-03-19: Simon Goldschmidt - * api.h, tcpip.h, api_lib.c, api_msg.c: fixed race conditions in assigning - netconn->last_err (fixed bugs #38121 and #37676) - - 2015-03-09: Simon Goldschmidt - * ip4.c: fixed the IPv4 part of bug #43904 (ip_route() must detect linkup status) - - 2015-03-04: Simon Goldschmidt - * nd6.c: fixed bug #43784 (a host should send at least one Router Solicitation) - - 2015-03-04: Valery Ushakov - * ip6.c: fixed bug #41094 (Byte-order bug in IPv6 fragmentation header test) - - 2015-03-04: Zach Smith - * nd6.c: fixed bug #38153 (nd6_input() byte order issues) - - 2015-02-26: Simon Goldschmidt - * netif.c, tcp.h/.c: fixed bug #44378 (TCP connections are not aborted on netif - remove) - - 2015-02-25: Simon Goldschmidt - * ip4.c, etharp.c: fixed bug #40177 (System hangs when dealing with corrupted - packets), implemented task #12357 (Ensure that malicious packets don't - assert-fail): improved some pbuf_header calls to not assert-fail. - - 2015-02-25: patch by Joel Cunningham - * udp.h/.c, sockets.c: fixed bug #43028 (IP_MULTICAST_TTL affects unicast - datagrams) - - 2015-02-25: patch by Greg Renda - * ip4_frag.c: fixed bug #38210 (ip reassembly while remove oldest datagram) - - 2015-02-25: Simon Goldschmidt - * sockets.c: fixed bug #38165 (socket with mulicast): ensure igmp membership - are dropped when socket (not netconn!) is closed. - - 2015-02-25: Simon Goldschmidt - * ip4.h/.c, udp.c: fixed bug #38061 (wrong multicast routing in IPv4) by - adding an optional default netif for multicast routing - - 2015-02-25: Simon Goldschmidt - * netconn API: fixed that netconn_connect still used message passing for - LWIP_TCPIP_CORE_LOCKING==1 - - 2015-02-22: patch by Jens Nielsen - * icmp.c: fixed bug #38803 (Source address in broadcast ping reply) - - 2015-02-22: Simon Goldschmidt - * udp.h, sockets.c: added proper accessor functions for pcb->multicast_ip - (previously used by get/setsockopt only) - - 2015-02-18: Simon Goldschmidt - * sockets.c: Fixed select not reporting received FIN as 'readable' in certain - rare cases (bug #43779: select(), close(), and TCP retransmission error) - - 2015-02-17: Simon Goldschmidt - * err.h, sockets.c, api_msg.c: fixed bug #38853 "connect() use a wrong errno": - return ERR_ALREADY/EALRADY during connect, ERR_ISCONN/EISCONN when already - connected - - 2015-02-17: Simon Goldschmidt - * tcp_impl.h, tcp_out.c, tcp.c, api_msg.c: fixed bug #37614 "Errors from - ipX_output are not processed". Now tcp_output(_segment) checks for the return - value of ipX_output and does not try to send more on error. A netif driver - can call tcp_txnow() (from tcpip_thread!) to try to send again if TX buffers - are available again. - - 2015-02-14: patches by Freddie Chopin - * snmp*: made community writable, fixed some const pointers - - 2015-02-13: Simon Goldschmidt - * msg_in.c: fixed bug #22070 "MIB_OBJECT_WRITE_ONLY not implemented in SNMP" - - 2015-02-12: Simon Goldschmidt - * ip.h, ip4.c, ip6.c: fixed bug #36403 "ip4_input() and ip6_input() always pass - inp to higher layers": now the accepting netif is passed up, but the input - netif is available through ip_current_input_netif() if required. - - 2015-02-11: patch by hichard - * tcpip.c: fixed bug #43094 "The function tcpip_input() forget to handle IPv6" - - 2015-02-10: Simon Goldschmidt - * netconn API: fixed that netconn_close/netconn_delete still used message passing - for LWIP_TCPIP_CORE_LOCKING==1 - - 2015-02-10: Simon Goldschmidt - * netconn/socket api: fixed bug #44225 "closing TCP socket should time out - eventually", implemented task #6930 "Implement SO_LINGER": closing TCP sockets - times out after 20 seconds or after the configured SND_TIMEOUT or depending - on the linger settings. - - 2015-01-27: Simon Goldschmidt - * api_msg.c: fixed that SHUT_RD followed by SHUT_WR was different to SHUT_RDWR, - fixed return value of lwip_netconn_do_close on unconnected netconns - - 2015-01-17: Simon Goldschmidt - * sockets.c: fixed bug #43361 select() crashes with stale FDs - - 2015-01-17: Simon Goldschmidt - * sockets.c/.h, memp_std.h: fixed bug #40788 "lwip_setsockopt_internal() crashes" - by rewriting set/getsockopt functions to combine checks with the actual code - and add more NULL checks; this also fixes that CORE_LOCKING used message - passing for set/getsockopt. - - 2014-12-19: Simon Goldschmidt - * opt.h, dhcp.h/.c: prevent dhcp from starting when netif link is down (only - when LWIP_DHCP_CHECK_LINK_UP==1, which is disabled by default for - compatibility reasons) - - 2014-12-17: Simon Goldschmidt - * tcp_out.c: fixed bug #43840 Checksum error for TCP_CHECKSUM_ON_COPY==1 for - no-copy data with odd length - - 2014-12-10: Simon Goldschmidt - * sockets.c, tcp.c, others: fixed bug #43797 set/getsockopt: SO_SNDTIMEO/SO_RCVTIMEO - take int as option but should take timeval (LWIP_SO_SNDRCVTIMEO_STANDARD==0 can - be used to revert to the old 'winsock' style behaviour) - Fixed implementation of SO_ACCEPTCONN to just look at the pcb state - - 2014-12-09: Simon Goldschmidt - * ip4.c: fixed bug #43596 IGMP queries from 0.0.0.0 are discarded - - 2014-10-21: Simon Goldschmidt (patch by Joel Cunningham and Albert Huitsing) - * sockts.c: fixed bugs #41495 Possible threading issue in select() and #43278 - event_callback() handle context switch when calling sys_sem_signal() - - 2014-10-21: Simon Goldschmidt - * api_msg.c: fixed bug #38219 Assert on TCP netconn_write with sndtimeout set - - 2014-09-16: Kevin Cernekee - * dns.c: patch #8480 Fix handling of dns_seqno wraparound - - 2014-09-16: Simon Goldschmidt - * tcp_out.c: fixed bug #43192 tcp_enqueue_flags() should not check TCP_SND_QUEUELEN - when sending FIN - - 2014-09-03: Simon Goldschmidt - * msg_in.c: fixed bug #39355 SNMP Memory Leak in case of error - - 2014-09-02: Simon Goldschmidt - * err.h/.c, sockets.c, api_msg.c: fixed bug #43110 call getpeername() before - listen() will cause a error - - 2014-09-02: Simon Goldschmidt - * sockets.c: fixed bug #42117 lwip_fcntl does not set errno - - 2014-09-02: Simon Goldschmidt - * tcp.c: fixed bug #42299 tcp_abort() leaves freed pcb on tcp_bound_pcbs list - - 2014-08-20: Simon Goldschmidt - * dns.c: fixed bug #42987 lwIP is vulnerable to DNS cache poisoning due to - non-randomized TXIDs - - 2014-06-03: Simon Goldschmidt - * tcp_impl.h, tcp_in.c: fixed bug #37969 SYN packet dropped as short packet in - tcp_input function - - 2014-05-20: Simon Goldschmidt - * tcp_out.c: fixed bug #37184 tcp_write problem for pcbs in the SYN_SENT state - - 2014-05-19: Simon Goldschmidt - * *.h: Fixed bug #35874 reserved identifier violation (removed leading underscores - from header include guards) - - 2014-04-08: Simon Goldschmidt - * tcp.c: Fixed bug #36167 tcp server crash when client closes (maximum window) - - 2014-04-06: Simon Goldschmidt - * tcp_in.c: Fixed bug #36210 lwIP does not elicit an empty ACK when received - unacceptable ACK - - 2014-04-06: Simon Goldschmidt - * dhcp.c, ip4.c/.h, ip6.c/.h, udp.c/.h, ip.h: Fixed bug #41787 DHCP Discovery - is invalid when an IP is set to thet netif. - - 2014-03-14: Simon Goldschmidt - * tcp_out.c: Fixed bug #36153 TCP Cheksum error if LWIP_CHECKSUM_ON_COPY=1 - - 2014-03-11: Simon Goldschmidt (patch by Mason) - * opt.h, sockets.c: fixed bug #35928 BSD sockets functions must set errno for - POSIX-compliance - - 2014-02-27: Simon Goldschmidt - * dhcp.c: fixed bug #40303 DHCP xid renewed when sending a DHCPREQUEST - - 2014-02-27: Simon Goldschmidt - * raw.c: fixed bug #41680 raw socket can not receive IPv6 packet when - IP_SOF_BROADCAST_RECV==1 - - 2014-02-27: Simon Goldschmidt - * api_msg.c, sockets.c: fixed bug #38404 getpeeraddr returns success on - unconnected/listening TCP sockets - - 2014-02-27: Simon Goldschmidt - * sockets.c: fixed bug #41729 Some socket functions return Exyz instead of -1 - - 2014-02-25: Simon Goldschmidt - * ip4.c: fixed bug #39514 ip_route() may return an IPv6-only interface - - 2014-02-25: Simon Goldschmidt, patch by Fatih Asici - * pbuf.c: fixed bug #39356 Wrong increment in pbuf_memfind() - - 2014-02-25: Simon Goldschmidt - * netif.c/.h, udp.c: fixed bug #39225 udp.c uses netif_matches_ip6_addr() incorrectly; - renamed function netif_matches_ip6_addr() to netif_get_ip6_addr_match() - - 2014-02-25: Simon Goldschmidt - * igmp.c: fixed bug #39145 IGMP membership report for 224.0.0.1 - - 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) - * etharp.c, opt.h: fixed bug #34681 Limit ARP queue length by ARP_QUEUE_LEN (=3) - - 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) - * etharp.h/.c: fixed bug #34682 Limit ARP request flood for unresolved entry - - 2014-02-20: Simon Goldschmidt - * tcp_out.c: fixed bug #39683 Assertion "seg->tcphdr not aligned" failed with - MEM_ALIGNMENT = 8 - - 2014-02-20: Simon Goldschmidt - * sockets.c: fixed bug #39882 No function shall set errno to 0 - - 2014-02-20: Simon Goldschmidt - * mib_structs.c: fixed bug #40050 SNMP problem with MIB arrays > 255 - - 2014-02-20: Simon Goldschmidt - * api.h, sockets.c: fixed bug #41499 netconn::recv_avail can overflow - - 2014-01-08: Stathis Voukelatos - * memp_std.h: patch #7928 Fixed size calculation in MALLOC memory pool - creation macro - - 2014-01-18: Brian Fahs - * tcp_out.c: patch #8237: tcp_rexmit_rto fails to update pcb->unsent_oversize - when necessary - - 2014-01-17: Grant Erickson, Jay Logue, Simon Goldschmidt - * ipv6.c, netif.c: patch #7913 Enable Support for IPv6 Loopback - - 2014-01-16: Stathis Voukelatos - * netif.c: patch #7902 Fixed netif_poll() operation when LWIP_LOOPBACK_MAX_PBUFS > 0 - - 2014-01-14: "Freddie Chopin" - * snmp.h, mib2.c: fixed constness and spelling of sysdescr - - 2014-01-14: Simon Goldschmidt (patch by Thomas Faber) - * tcpip.c: patch #8241: Fix implicit declaration of ip_input with - LWIP_TCPIP_CORE_LOCKING_INPUT disabled - - 2014-01-14: chrysn - * timers.c: patch #8244 make timeouts usable reliably from outside of the - timeout routine - - 2014-01-10: Simon Goldschmidt - * ip_frag.c, ip6_frag.c: fixed bug #41041 Potential use-after-free in IPv6 reassembly - - 2014-01-10: Simon Goldschmidt - * memp.c: fixed bug #41188 Alignment error in memp_init() when MEMP_SEPARATE_POOLS==1 - - 2014-01-10: Simon Goldschmidt - * tcp.c: fixed bug #39898 tcp_fasttmr() possible lock due to infinte queue process loop - - 2013-06-29: Simon Goldschmidt - * inet.h, sockets.h: partially fixed bug #37585: IPv6 compatibility (in socket structs) - - 2013-06-29: Simon Goldschmidt - * inet6.h: bug #37585/task #12600: fixed struct in6_addr.s6_addr to conform to spec - - 2013-04-24: patch by Liam - * api_msg.c: patch #8008 Fix a potential null pointer dereference in assert - - 2013-04-24: Simon Goldschmidt - * igmp.c: fixed possible division by zero - - 2013-04-24: Simon Goldschmidt - * ip6.h, some ipv6 C files: fixed bug #38526 Coverity: Recursive Header Inclusion in ip6.h - - 2013-04-24: Simon Goldschmidt (patch by Emil Ljungdahl): - * netif.c: fixed bug #38586 netif_loop_output() "deadlocks" - - 2013-01-15: Simon Goldschmidt - * ip4.c: fixed bug #37665 ip_canforward operates on address in wrong byte order - - 2013-01-15: Simon Goldschmidt - * pbuf.h: fixed bug #38097 pbuf_free_ooseq() warning - - 2013-01-14: Simon Goldschmidt - * dns.c: fixed bug #37705 Possible memory corruption in DNS query - - 2013-01-11: Simon Goldschmidt - * raw.c: fixed bug #38066 Raw pcbs can alter packet without eating it - - 2012-08-22: Simon Goldschmidt - * memp.c: fixed bug #37166: memp_sanity check loops itself - - 2012-08-13: Simon Goldschmidt - * dhcp.c: fixed bug #36645: Calling dhcp_release before dhcp_start - dereferences NULL - - 2012-08-13: Simon Goldschmidt - * msg_out.c: fixed bug #36840 snmp_send_trap() NULL de-reference if traps - configured but no interfaces available - - 2012-08-13: Simon Goldschmidt - * dns.c: fixed bug #36899 DNS TTL 0 is cached for a long time - - 2012-05-11: Simon Goldschmidt (patch by Marty) - * memp.c: fixed bug #36412: memp.c does not compile when - MEMP_OVERFLOW_CHECK > zero and MEMP_SEPARATE_POOLS == 1 - - 2012-05-03: Simon Goldschmidt (patch by Sylvain Rochet) - * ppp.c: fixed bug #36283 (PPP struct used on header size computation and - not packed) - - 2012-05-03: Simon Goldschmidt (patch by David Empson) - * ppp.c: fixed bug #36388 (PPP: checksum-only in last pbuf leads to pbuf with - zero length) - - 2012-03-25: Simon Goldschmidt - * api_msg.c: Fixed bug #35817: do_connect() invalidly signals op_completed - for UDP/RAW with LWIP_TCPIP_CORE_LOCKING==1 - - 2012-03-25: Simon Goldschmidt - * api_msg.h, api_lib.c, api_msg.c, netifapi.c: fixed bug #35931: Name space - pollution in api_msg.c and netifapi.c - - 2011-08-24: Simon Goldschmidt - * inet6.h: fixed bug #34124 struct in6_addr does not conform to the standard - - - -(STABLE-1.4.1) - - ++ New features: - - 2012-03-25: Simon Goldschmidt (idea by Mason) - * posix/*: added posix-compatibility include files posix/netdb.h and posix/sys/socket.h - which are a simple wrapper to the correct lwIP include files. - - 2012-01-16: Simon Goldschmidt - * opt.h, icmp.c: Added option CHECKSUM_GEN_ICMP - - 2011-12-17: Simon Goldschmidt - * ip.h: implemented API functions to access so_options of IP pcbs (UDP, TCP, RAW) - (fixes bug #35061) - - 2011-09-27: Simon Goldschmidt - * opt.h, tcp.c, tcp_in.c: Implemented limiting data on ooseq queue (task #9989) - (define TCP_OOSEQ_MAX_BYTES / TCP_OOSEQ_MAX_PBUFS in lwipopts.h) - - 2011-09-21: Simon Goldschmidt - * opt.h, api.h, api_lib.c, api_msg.h/.c, sockets.c: Implemented timeout on - send (TCP only, bug #33820) - - 2011-09-21: Simon Goldschmidt - * init.c: Converted runtime-sanity-checks into compile-time checks that can - be disabled (since runtime checks can often not be seen on embedded targets) - - 2011-09-11: Simon Goldschmidt - * ppp.h, ppp_impl.h: splitted ppp.h to an internal and external header file - to get a clear separation of which functions an application or port may use - (task #11281) - - 2011-09-11: Simon Goldschmidt - * opt.h, tcp_impl.h, tcp.c, udp.h/.c: Added a config option to randomize - initial local TCP/UDP ports (so that different port ranges are used after - a reboot; bug #33818; this one added tcp_init/udp_init functions again) - - 2011-09-03: Simon Goldschmidt - * dhcp.c: DHCP uses LWIP_RAND() for xid's (bug #30302) - - 2011-08-24: Simon Goldschmidt - * opt.h, netif.h/.c: added netif remove callback (bug #32397) - - 2011-07-26: Simon Goldschmidt - * etharp.c: ETHARP_SUPPORT_VLAN: add support for an external VLAN filter - function instead of only checking for one VLAN (define ETHARP_VLAN_CHECK_FN) - - 2011-07-21: Simon Goldschmidt (patch by hanhui) - * ip4.c, etharp.c, pbuf.h: bug #33634 ip_forward() have a faulty behaviour: - Added pbuf flags to mark incoming packets as link-layer broadcast/multicast. - Also added code to allow ip_forward() to forward non-broadcast packets to - the input netif (set IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1). - - 2011-06-26: Simon Goldschmidt (patch by Cameron Gutman) - * tcp.c, tcp_out.c: bug #33604: added some more asserts to check that - pcb->state != LISTEN - - 2011-05-14: Simon Goldschmidt (patch by Stéphane Lesage) - * tcpip.c/.h: patch #7449 allow tcpip callback from interrupt with static - memory message - - - ++ Bugfixes: - - 2012-09-26: Simon Goldschmidt - * api_msg.c: fixed bug #37405 'err_tcp()' uses already freed 'netconn' object - - 2012-09-26: patch by Henrik Persson - * dhcp.c: patch #7843 Fix corner case with dhcp timeouts - - 2012-09-26: patch by Henrik Persson - * dhcp.c: patch #7840 Segfault in dhcp_parse_reply if no end marker in dhcp packet - - 2012-08-22: Simon Goldschmidt - * memp.c: fixed bug #37166: memp_sanity check loops itself - - 2012-05-08: Simon Goldschmidt - * tcp_out.c: fixed bug: #36380 unsent_oversize mismatch in 1.4.1RC1 (this was - a debug-check issue only) - - 2012-03-27: Simon Goldschmidt - * vj.c: fixed bug #35756 header length calculation problem in ppp/vj.c - - 2012-03-27: Simon Goldschmidt (patch by Mason) - * tcp_out.c: fixed bug #35945: SYN packet should provide the recv MSS not the - send MSS - - 2012-03-22: Simon Goldschmidt - * ip4.c: fixed bug #35927: missing refragmentaion in ip_forward - - 2012-03-20: Simon Goldschmidt (patch by Mason) - * netdb.c: fixed bug #35907: lwip_gethostbyname_r returns an invalid h_addr_list - - 2012-03-12: Simon Goldschmidt (patch by Bostjan Meglic) - * ppp.c: fixed bug #35809: PPP GetMask(): Compiler warning on big endian, - possible bug on little endian system - - 2012-02-23: Simon Goldschmidt - * etharp.c: fixed bug #35595: Impossible to send broadcast without a gateway - (introduced when fixing bug# 33551) - - 2012-02-16: Simon Goldschmidt - * ppp.c: fixed pbuf leak when PPP session is aborted through pppSigHUP() - (bug #35541: PPP Memory Leak) - - 2012-02-16: Simon Goldschmidt - * etharp.c: fixed bug #35531: Impossible to send multicast without a gateway - (introduced when fixing bug# 33551) - - 2012-02-16: Simon Goldschmidt (patch by Stéphane Lesage) - * msg_in.c, msg_out.c: fixed bug #35536 SNMP: error too big response is malformed - - 2012-02-15: Simon Goldschmidt - * init.c: fixed bug #35537: MEMP_NUM_* sanity checks should be disabled with - MEMP_MEM_MALLOC==1 - - 2012-02-12: Simon Goldschmidt - * tcp.h, tcp_in.c, tcp_out.c: partly fixed bug #25882: TCP hangs on - MSS > pcb->snd_wnd (by not creating segments bigger than half the window) - - 2012-02-11: Simon Goldschmidt - * tcp.c: fixed bug #35435: No pcb state check before adding it to time-wait - queue while closing - - 2012-01-22: Simon Goldschmidt - * tcp.c, tcp_in.c: fixed bug #35305: pcb may be freed too early on shutdown(WR) - - 2012-01-21: Simon Goldschmidt - * tcp.c: fixed bug #34636: FIN_WAIT_2 - Incorrect shutdown of TCP pcb - - 2012-01-20: Simon Goldschmidt - * dhcp.c: fixed bug #35151: DHCP asserts on incoming option lengths - - 2012-01-20: Simon Goldschmidt - * pbuf.c: fixed bug #35291: NULL pointer in pbuf_copy - - 2011-11-25: Simon Goldschmidt - * tcp.h/.c, tcp_impl.h, tcp_in.c: fixed bug #31177: tcp timers can corrupt - tcp_active_pcbs in some cases - - 2011-11-23: Simon Goldschmidt - * sys.c: fixed bug #34884: sys_msleep() body needs to be surrounded with - '#ifndef sys_msleep' - - 2011-11-22: Simon Goldschmidt - * netif.c, etharp.h/.c: fixed bug #34684: Clear the arp table cache when - netif is brought down - - 2011-10-28: Simon Goldschmidt - * tcp_in.c: fixed bug #34638: Dead code in tcp_receive - pcb->dupacks - - 2011-10-23: Simon Goldschmidt - * mem.c: fixed bug #34429: possible memory corruption with - LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT set to 1 - - 2011-10-18: Simon Goldschmidt - * arch.h, netdb.c: fixed bug #34592: lwip_gethostbyname_r uses nonstandard - error value - - 2011-10-18: Simon Goldschmidt - * opt.h: fixed default values of TCP_SNDLOWAT and TCP_SNDQUEUELOWAT for small - windows (bug #34176 select after non-blocking send times out) - - 2011-10-18: Simon Goldschmidt - * tcp_impl.h, tcp_out.c: fixed bug #34587: TCP_BUILD_MSS_OPTION doesn't - consider netif->mtu, causes slow network - - 2011-10-18: Simon Goldschmidt - * sockets.c: fixed bug #34581 missing parentheses in udplite sockets code - - 2011-10-18: Simon Goldschmidt - * sockets.h: fixed bug #34580 fcntl() is missing in LWIP_COMPAT_SOCKETS - - 2011-10-17: Simon Goldschmidt - * api_msg.c: fixed bug #34569: shutdown(SHUT_WR) crashes netconn/socket api - - 2011-10-13: Simon Goldschmidt - * tcp_in.c, tcp_out.c: fixed bug #34517 (persist timer is started although no - zero window is received) by starting the persist timer when a zero window is - received, not when we have more data queued for sending than fits into the - window - - 2011-10-13: Simon Goldschmidt - * def.h, timers.c: fixed bug #34541: LWIP_U32_DIFF is unnecessarily complex - - 2011-10-13: Simon Goldschmidt - * sockets.c, api_lib.c: fixed bug #34540: compiler error when CORE_LOCKING is - used and not all protocols are enabled - - 2011-10-12: Simon Goldschmidt - * pbuf.c: fixed bug #34534: Error in sending fragmented IP if MEM_ALIGNMENT > 4 - - 2011-10-09: Simon Goldschmidt - * tcp_out.c: fixed bug #34426: tcp_zero_window_probe() transmits incorrect - byte value when pcb->unacked != NULL - - 2011-10-09: Simon Goldschmidt - * ip4.c: fixed bug #34447 LWIP_IP_ACCEPT_UDP_PORT(dst_port) wrong - - 2011-09-27: Simon Goldschmidt - * tcp_in.c, tcp_out.c: Reset pcb->unsent_oversize in 2 more places... - - 2011-09-27: Simon Goldschmidt - * tcp_in.c: fixed bug #28288: Data after FIN in oos queue - - 2011-09-27: Simon Goldschmidt - * dhcp.c: fixed bug #34406 dhcp_option_hostname() can overflow the pbuf - - 2011-09-24: Simon Goldschmidt - * mem.h: fixed bug #34377 MEM_SIZE_F is not defined if MEM_LIBC_MALLOC==1 - - 2011-09-23: Simon Goldschmidt - * pbuf.h, tcp.c, tcp_in.c: fixed bug #33871: rejecting TCP_EVENT_RECV() for - the last packet including FIN can lose data - - 2011-09-22: Simon Goldschmidt - * tcp_impl.h: fixed bug #34355: nagle does not take snd_buf/snd_queuelen into - account - - 2011-09-21: Simon Goldschmidt - * opt.h: fixed default value of TCP_SND_BUF to not violate the sanity checks - in init.c - - 2011-09-20: Simon Goldschmidt - * timers.c: fixed bug #34337 (possible NULL pointer in sys_check_timeouts) - - 2011-09-11: Simon Goldschmidt - * tcp_out.c: use pcb->mss instead of TCP_MSS for preallocate mss-sized pbufs - (bug #34019) - - 2011-09-09: Simon Goldschmidt - * udp.c: fixed bug #34072: UDP broadcast is received from wrong UDP pcb if - udp port matches - - 2011-09-03: Simon Goldschmidt - * tcp_in.c: fixed bug #33952 PUSH flag in incoming packet is lost when packet - is aggregated and sent to application - - 2011-09-01: Simon Goldschmidt - * opt.h: fixed bug #31809 LWIP_EVENT_API in opts.h is inconsistent compared - to other options - - 2011-09-01: Simon Goldschmidt - * tcp_in.c: fixed bug #34111 RST for ACK to listening pcb has wrong seqno - - 2011-08-24: Simon Goldschmidt - * api_msg.c, sockets.c: fixed bug #33956 Wrong error returned when calling - accept() on UDP connections - - 2011-08-24: Simon Goldschmidt - * sockets.h: fixed bug #34057 socklen_t should be a typedef - - 2011-08-24: Simon Goldschmidt - * pbuf.c: fixed bug #34112 Odd check in pbuf_alloced_custom (typo) - - 2011-08-24: Simon Goldschmidt - * dhcp.c: fixed bug #34122 dhcp: hostname can overflow - - 2011-08-24: Simon Goldschmidt - * netif.c: fixed bug #34121 netif_add/netif_set_ipaddr fail on NULL ipaddr - - 2011-08-22: Simon Goldschmidt - * tcp_out.c: fixed bug #33962 TF_FIN not always set after FIN is sent. (This - merely prevents nagle from not transmitting fast after closing.) - - 2011-07-22: Simon Goldschmidt - * api_lib.c, api_msg.c, sockets.c, api.h: fixed bug #31084 (socket API returns - always EMSGSIZE on non-blocking sockets if data size > send buffers) -> now - lwip_send() sends as much as possible for non-blocking sockets - - 2011-07-22: Simon Goldschmidt - * pbuf.c/.h, timers.c: freeing ooseq pbufs when the pbuf pool is empty implemented - for NO_SYS==1: when not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() - at regular intervals from main level. - - 2011-07-21: Simon Goldschmidt - * etharp.c: fixed bug #33551 (ARP entries may time out although in use) by - sending an ARP request when an ARP entry is used in the last minute before - it would time out. - - 2011-07-04: Simon Goldschmidt - * sys_arch.txt: Fixed documentation after changing sys arch prototypes for 1.4.0. - - 2011-06-26: Simon Goldschmidt - * tcp.c: fixed bug #31723 (tcp_kill_prio() kills pcbs with the same prio) by - updating its documentation only. - - 2011-06-26: Simon Goldschmidt - * mem.c: fixed bug #33545: With MEM_USE_POOLS==1, mem_malloc can return an - unaligned pointer. - - 2011-06-26: Simon Goldschmidt - * mem.c: fixed bug #33544 "warning in mem.c in lwip 1.4.0 with NO_SYS=1" - - 2011-05-25: Simon Goldschmidt - * tcp.c: fixed bug #33398 (pointless conversion when checking TCP port range) - - - -(STABLE-1.4.0) - - ++ New features: - - 2011-03-27: Simon Goldschmidt - * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and - calculate it in tcp_zero_window_probe (the only place where it was used). - - 2010-11-21: Simon Goldschmidt - * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif - (fixes bug #31525). - - 2010-07-12: Simon Goldschmidt (patch by Stephane Lesage) - * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for - IP_MULTICAST_LOOP at socket- and raw-API level. - - 2010-06-16: Simon Goldschmidt - * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow - link-layer-addressed UDP traffic to be received while a netif is down (just - like DHCP during configuration) - - 2010-05-22: Simon Goldschmidt - * many many files: bug #27352: removed packing from ip_addr_t, the packed - version is now only used in protocol headers. Added global storage for - current src/dest IP address while in input functions. - - 2010-05-16: Simon Goldschmidt - * def.h: task #10391: Add preprocessor-macros for compile-time htonl - calculation (and use them throughout the stack where applicable) - - 2010-05-16: Simon Goldschmidt - * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool - instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h) - - 2010-05-16: Simon Goldschmidt - * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own - MEMP pool instead of the heap - - 2010-05-13: Simon Goldschmidt - * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added - new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast - packets to more than one pcb. - - 2010-05-02: Simon Goldschmidt - * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending - UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1 - - 2010-04-30: Simon Goldschmidt - * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that - take a precalculated checksum, added pbuf_fill_chksum() to copy data - into a pbuf and at the same time calculating the checksum for that data - - 2010-04-29: Simon Goldschmidt - * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying - 2-byte-aligned IP addresses and MAC addresses - - 2010-04-28: Patch by Bill Auerbach - * ip.c: Inline generating IP checksum to save a function call - - 2010-04-14: Simon Goldschmidt - * tcpip.h/.c, timers.c: Added an overridable define to get informed when the - tcpip_thread processes messages or timeouts to implement a watchdog. - - 2010-03-28: Simon Goldschmidt - * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing - fragment if LWIP_NETIF_TX_SINGLE_PBUF==1 - - 2010-03-27: Simon Goldschmidt - * etharp.c: Speedup TX by moving code from find_entry to etharp_output/ - etharp_query to prevent unnecessary function calls (inspired by - patch #7135). - - 2010-03-20: Simon Goldschmidt - * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code - since the linker cannot do this automatically to save space. - - 2010-03-20: Simon Goldschmidt - * opt.h, etharp.c/.h: Added support for static ARP table entries - - 2010-03-14: Simon Goldschmidt - * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum - when creating TCP segments, not when (re-)transmitting them. - - 2010-03-07: Simon Goldschmidt - * sockets.c: bug #28775 (select/event_callback: only check select_cb_list - on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code. - This should speed up receiving data on sockets as the select code in - event_callback is only executed when select is waiting. - - 2010-03-06: Simon Goldschmidt - * tcp_out.c: task #7013 (Create option to have all packets delivered to - netif->output in one piece): Always copy to try to create single pbufs - in tcp_write. - - 2010-03-06: Simon Goldschmidt - * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv - by not allocating a netbuf): added function netconn_recv_tcp_pbuf() - for tcp netconns to receive pbufs, not netbufs; use that function - for tcp sockets. - - 2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt - * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040: - Work on tcp_enqueue: Don't waste memory when chaining segments, - added option TCP_OVERSIZE to prevent creating many small pbufs when - calling tcp_write with many small blocks of data. Instead, pbufs are - allocated larger than needed and the space is used for later calls to - tcp_write. - - 2010-02-21: Simon Goldschmidt - * stats.c/.h: Added const char* name to mem- and memp-stats for easier - debugging. - - 2010-02-21: Simon Goldschmidt - * tcp.h (and usages), added tcp_impl.h: Splitted API and internal - implementation of tcp to make API usage cleare to application programmers - - 2010-02-14: Simon Goldschmidt/Stephane Lesage - * ip_addr.h: Improved some defines working on ip addresses, added faster - macro to copy addresses that cannot be NULL - - 2010-02-13: Simon Goldschmidt - * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non- - blocking send operation) - - 2010-02-12: Simon Goldschmidt - * sockets.c/.h: Added a minimal version of posix fctl() to have a - standardised way to set O_NONBLOCK for nonblocking sockets. - - 2010-02-12: Simon Goldschmidt - * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated - memory): added autoip_set_struct() and dhcp_set_struct() to let autoip - and dhcp work with user-allocated structs instead of callin mem_malloc - - 2010-02-12: Simon Goldschmidt/Jeff Barber - * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has - SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT - - 2010-02-12: Simon Goldschmidt - * sys layer: task #10139 (Prefer statically allocated memory): converted - mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t; - converted sys_mbox_new/sys_sem_new to take pointers and return err_t; - task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX - to let sys.h use binary semaphores instead of mutexes - as before) - - 2010-02-09: Simon Goldschmidt (Simon Kallweit) - * timers.c/.h: Added function sys_restart_timeouts() from patch #7085 - (Restart system timeout handling) - - 2010-02-09: Simon Goldschmidt - * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into - netif.c) - loopif does not have to be created by the port any more, - just define LWIP_HAVE_LOOPIF to 1. - - 2010-02-08: Simon Goldschmidt - * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa - inet_ntoa_r/ipaddr_ntoa_r - - 2010-02-08: Simon Goldschmidt - * netif.h: Added netif_s/get_igmp_mac_filter() macros - - 2010-02-05: Simon Goldschmidt - * netif.h: Added function-like macros to get/set the hostname on a netif - - 2010-02-04: Simon Goldschmidt - * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to - make changing the actual implementation behind the typedef easier. - - 2010-02-01: Simon Goldschmidt - * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool - for allocating memory when getaddrinfo() is called. - - 2010-01-31: Simon Goldschmidt - * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse - them once instead of parsing for every option. This also removes - the need for mem_malloc from dhcp_recv and makes it possible to - correctly retrieve the BOOTP file. - - 2010-01-30: simon Goldschmidt - * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect - the sockets array. - - 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) - * api.h, api_msg.c, sockets.c: Added except set support in select - (patch #6860) - - 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) - * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c: - Add non-blocking support for connect (partly from patch #6860), - plus many cleanups in socket & netconn API. - - 2010-01-27: Simon Goldschmidt - * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding - to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605 - - 2010-01-26: Simon Goldschmidt - * snmp: Use memp pools for snmp instead of the heap; added 4 new pools. - - 2010-01-14: Simon Goldschmidt - * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback - by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback() - - 2010-01-13: Simon Goldschmidt - * mem.c: The heap now may be moved to user-defined memory by defining - LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address - (patch #6966 and bug #26133) - - 2010-01-10: Simon Goldschmidt (Bill Auerbach) - * opt.h, memp.c: patch #6822 (Add option to place memory pools in - separate arrays) - - 2010-01-10: Simon Goldschmidt - * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define - LWIP_RAND() for lwip-wide randomization (to be defined in cc.h) - - 2009-12-31: Simon Goldschmidt - * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h - added timers.c/.h: Separated timer implementation from semaphore/mbox - implementation, moved timer implementation to timers.c/.h, timers are - now only called from tcpip_thread or by explicitly checking them. - (TASK#7235) - - 2009-12-27: Simon Goldschmidt - * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option - LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) - - - ++ Bugfixes: - - 2011-04-20: Simon Goldschmidt - * sys_arch.txt: sys_arch_timeouts() is not needed any more. - - 2011-04-13: Simon Goldschmidt - * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by - using ports in the IANA private/dynamic range (49152 through 65535). - - 2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl: - * etharp.h/.c: Fixed broken VLAN support. - - 2011-03-27: Simon Goldschmidt - * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp - pcbs) by checking if the pcb was bound (local_port != 0). - - 2011-03-27: Simon Goldschmidt - * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice) - - 2011-03-27: Simon Goldschmidt - * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and - raw pcbs with LWIP_TCPIP_CORE_LOCKING==1. - - 2011-03-27: Simon Goldschmidt - * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route - is present never times out) by starting retransmission timer before checking - route. - - 2011-03-22: Simon Goldschmidt - * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only - calling sio_read_abort() if the file descriptor is valid. - - 2011-03-14: Simon Goldschmidt - * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect - more than once can render a socket useless) since it mainly involves changing - "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal. - - 2011-03-13: Simon Goldschmidt - * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing - err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN: - use EALRADY instead of -1 - - 2011-03-13: Simon Goldschmidt - * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the - connection has been aborted by err_tcp (since this is not a normal closing - procedure). - - 2011-03-13: Simon Goldschmidt - * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind - with pcb->state != CLOSED - - 2011-02-17: Simon Goldschmidt - * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in - documentation - - 2011-02-17: Simon Goldschmidt - * many files: Added missing U/UL modifiers to fix 16-bit-arch portability. - - 2011-01-24: Simon Goldschmidt - * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems - - 2010-12-02: Simon Goldschmidt - * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal. - - 2010-11-23: Simon Goldschmidt - * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for - LWIP_SO_RCVBUF and ioctl/FIONREAD. - - 2010-11-23: Simon Goldschmidt - * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at - least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet. - - 2010-11-23: Simon Goldschmidt - * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after - refusing 'refused_data' again. - - 2010-11-22: Simon Goldschmidt - * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS - after a successful nonblocking connection. - - 2010-11-22: Simon Goldschmidt - * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr - must be sent link-local - - 2010-11-22: Simon Goldschmidt - * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for - LWIP_TIMERS==0 - - 2010-11-20: Simon Goldschmidt - * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number - - 2010-11-20: Simon Goldschmidt - * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to - resemble other stacks. - - 2010-11-20: Simon Goldschmidt - * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else - no-copy TCP writes will never succeed. - - 2010-11-20: Simon Goldschmidt - * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does - not match documentation: return ERR_ARG instead of ERR_VAL if not - initialized or wrong argument. - - 2010-10-20: Simon Goldschmidt - * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16 - - 2010-10-05: Simon Goldschmidt - * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when - replugging the network cable after an AutoIP address was assigned. - - 2010-08-10: Simon Goldschmidt - * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs - - 2010-08-03: Simon Goldschmidt - * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625) - - 2010-08-01: Simon Goldschmidt (patch by Greg Renda) - * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big - endian architectures) - - 2010-07-28: Simon Goldschmidt - * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP - disabled. - - 2010-07-27: Simon Goldschmidt - * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no - harm but never did anything - - 2010-07-21: Simon Goldschmidt - * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not - add IP options) - - 2010-07-16: Kieran Mansley - * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator - - 2010-07-10: Simon Goldschmidt - * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options - - 2010-06-30: Simon Goldschmidt - * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in - netconn_delete) - - 2010-06-28: Kieran Mansley - * timers.c remove unportable printing of C function pointers - - 2010-06-24: Simon Goldschmidt - * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag - NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading - - 2010-06-24: Simon Goldschmidt - * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly - implemented shutdown at socket level. - - 2010-06-21: Simon Goldschmidt - * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has - problems with zero-copy DMA MACs) by adding custom pbufs and implementing - custom pbufs that reference other (original) pbufs. Additionally set - IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side. - - 2010-06-15: Simon Goldschmidt - * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses - - 2010-06-14: Simon Goldschmidt - * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses - - 2010-06-12: Simon Goldschmidt - * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop - state - - 2010-05-17: Simon Goldschmidt - * netdb.c: Correctly NULL-terminate h_addr_list - - 2010-05-16: Simon Goldschmidt - * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent - "symbol already defined" i.e. when linking to winsock - - 2010-05-05: Simon Goldschmidt - * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may - overflow) - - 2010-04-21: Simon Goldschmidt - * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening - connection) - - 2010-03-28: Luca Ceresoli - * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers - - 2010-03-27: Luca Ceresoli - * mib2.c: patch #7130: remove meaningless const qualifiers - - 2010-03-26: Simon Goldschmidt - * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too - - 2010-03-26: Simon Goldschmidt - * various files: Fixed compiling with different options disabled (TCP/UDP), - triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled - - 2010-03-25: Simon Goldschmidt - * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly - - 2010-03-25: Simon Goldschmidt - * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side - overrunning our rcv_wnd in ooseq case. - - 2010-03-22: Simon Goldschmidt - * tcp.c: tcp_listen() did not copy the pcb's prio. - - 2010-03-19: Simon Goldschmidt - * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set - - 2010-03-14: Simon Goldschmidt - * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports - where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h - and basing PBUF_LINK_HLEN on it. - - 2010-03-08: Simon Goldschmidt - * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections - when assiging routable address): when checking incoming packets and - aborting existing connection on address change, filter out link-local - addresses. - - 2010-03-06: Simon Goldschmidt - * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING - - 2010-03-06: Simon Goldschmidt - * ipv4/ip.c: Don't try to forward link-local addresses - - 2010-03-06: Simon Goldschmidt - * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal- - addresses to gw - - 2010-03-05: Simon Goldschmidt - * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type - and state. - - 2010-03-05: Simon Goldschmidt - * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split - into multiple calls to tcp_write. - - 2010-02-21: Simon Goldschmidt - * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep - the implementation of DNS_USES_STATIC_BUF==1) - - 2010-02-20: Simon Goldschmidt - * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement - close() vs. shutdown(). Now the application does not get any more - recv callbacks after calling tcp_close(). Added tcp_shutdown(). - - 2010-02-19: Simon Goldschmidt - * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent - confusion with realloc() - - 2010-02-15: Simon Goldschmidt/Stephane Lesage - * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK - (fixes bug #28899) - - 2010-02-14: Simon Goldschmidt - * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with - LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and - admin-status of a netif are up - - 2010-02-14: Simon Goldschmidt - * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet - reception and is not really necessary - - 2010-02-14: Simon Goldschmidt - * etharp.c/.h: Fixed ARP input processing: only add a new entry if a - request was directed as us (RFC 826, Packet Reception), otherwise - only update existing entries; internalized some functions - - 2010-02-14: Simon Goldschmidt - * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be - disabled on netif used for PPPoE) by adding a new netif flag - (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet - device but prevents usage of ARP (so that ethernet_input can be used - for PPPoE). - - 2010-02-12: Simon Goldschmidt - * netif.c: netif_set_link_up/down: only do something if the link state - actually changes - - 2010-02-12: Simon Goldschmidt/Stephane Lesage - * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking - connect) - - 2010-02-12: Simon Goldschmidt - * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h) - - 2010-02-09: Simon Goldschmidt - * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110 - (recv() makes receive window update for data that wasn't received by - application) - - 2010-02-09: Simon Goldschmidt/Stephane Lesage - * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out - or any netconn_recv() error) - - 2010-02-09: Simon Goldschmidt - * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets) - - 2010-02-09: Simon Goldschmidt - * netif.c: For loopback packets, adjust the stats- and snmp-counters - for the loopback netif. - - 2010-02-08: Simon Goldschmidt - * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity - since they are not used anywhere else. - - 2010-02-08: Simon Goldschmidt (Stéphane Lesage) - * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats - (patch from bug #28798) - - 2010-02-08: Simon Goldschmidt (Stéphane Lesage) - * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and - another bug when LWIP_RAND() returns zero. - - 2010-02-04: Simon Goldschmidt - * nearly every file: Use macros defined in ip_addr.h (some of them new) - to work with IP addresses (preparation for bug #27352 - Change ip_addr - from struct to typedef (u32_t) - and better code). - - 2010-01-31: Simon Goldschmidt - * netif.c: Don't call the link-callback from netif_set_up/down() since - this invalidly retriggers DHCP. - - 2010-01-29: Simon Goldschmidt - * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the - portability file inet.h and its contents from the stack: moved htonX- - functions to def.h (and the new def.c - they are not ipv4 dependent), - let inet.h depend on ip_addr.h and not the other way round. - This fixes bug #28732. - - 2010-01-28: Kieran Mansley - * tcp.c: Ensure ssthresh >= 2*MSS - - 2010-01-27: Simon Goldschmidt - * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv - callback can lead to accessing unallocated memory. As a consequence, - ERR_ABRT means the application has called tcp_abort()! - - 2010-01-25: Simon Goldschmidt - * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY - not implemented in SNMP): write-only or not-accessible are still - returned by getnext (though not by get) - - 2010-01-24: Simon Goldschmidt - * snmp: Renamed the private mib node from 'private' to 'mib_private' to - not use reserved C/C++ keywords - - 2010-01-23: Simon Goldschmidt - * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less - than 1 ms - - 2010-01-21: Simon Goldschmidt - * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called - if tcp_enqueue fails) both in raw- and netconn-API - - 2010-01-19: Simon Goldschmidt - * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp - - 2010-01-18: Iordan Neshev/Simon Goldschmidt - * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some - bugfix backports from 2.4.x. - - 2010-01-18: Simon Goldschmidt - * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong - - 2010-01-17: Simon Goldschmidt - * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c): - task #10102: "netconn: clean up conn->err threading issues" by adding - error return value to struct api_msg_msg - - 2010-01-17: Simon Goldschmidt - * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept() - to return err_t (bugs #27709 and #28087) - - 2010-01-14: Simon Goldschmidt - * ...: Use typedef for function prototypes throughout the stack. - - 2010-01-13: Simon Goldschmidt - * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive - window = 0) by correctly draining recvmbox/acceptmbox - - 2010-01-11: Simon Goldschmidt - * pap.c: Fixed bug #13315 (PPP PAP authentication can result in - erroneous callbacks) by copying the code from recent pppd - - 2010-01-10: Simon Goldschmidt - * raw.c: Fixed bug #28506 (raw_bind should filter received packets) - - 2010-01-10: Simon Goldschmidt - * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)()) - - 2010-01-08: Simon Goldschmidt - * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535) - - 2010-01-08: Simon Goldschmidt - * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string - passed to dns_local_addhost() might be volatile - - 2010-01-07: Simon Goldschmidt - * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too - - 2010-01-06: Simon Goldschmidt - * netdb.h: Fixed bug #28496: missing include guards in netdb.h - - 2009-12-31: Simon Goldschmidt - * many ppp files: Reorganised PPP source code from ucip structure to pppd - structure to easily compare our code against the pppd code (around v2.3.1) - - 2009-12-27: Simon Goldschmidt - * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted - unit test - - -(STABLE-1.3.2) - - ++ New features: - - 2009-10-27 Simon Goldschmidt/Stephan Lesage - * netifapi.c/.h: Added netifapi_netif_set_addr() - - 2009-10-07 Simon Goldschmidt/Fabian Koch - * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to - support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO) - - 2009-08-26 Simon Goldschmidt/Simon Kallweit - * slipif.c/.h: bug #26397: SLIP polling support - - 2009-08-25 Simon Goldschmidt - * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN), - New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK. - - 2009-08-25 Simon Goldschmidt - * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*) - - 2009-08-24 Jakob Stoklund Olesen - * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond - to netif_set_link_up(). - - 2009-08-23 Simon Goldschmidt - * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state - to a human-readable string. - - ++ Bugfixes: - - 2009-12-24: Kieran Mansley - * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing - (BUG#28241) - - 2009-12-06: Simon Goldschmidt - * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can - be statically allocated (like in ucip) - - 2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev) - * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT - - 2009-12-03: Simon Goldschmidt - * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit - could have non-zero length - - 2009-12-02: Simon Goldschmidt - * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting - tcp_input_pcb until after calling the pcb's callbacks - - 2009-11-29: Simon Goldschmidt - * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of- - sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code - - 2009-11-29: Simon Goldschmidt - * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by - queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty - - 2009-11-26: Simon Goldschmidt - * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending - segment - - 2009-11-26: Simon Goldschmidt - * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle - algorithm at PCB level - - 2009-11-22: Simon Goldschmidt - * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent - - 2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach) - * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when - reusing time-wait pcb - - 2009-11-20: Simon Goldschmidt (patch by Albert Bartel) - * sockets.c: Fixed bug #28062: Data received directly after accepting - does not wake up select - - 2009-11-11: Simon Goldschmidt - * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo) - - 2009-10-30: Simon Goldschmidt - * opt.h: Increased default value for TCP_MSS to 536, updated default - value for TCP_WND to 4*TCP_MSS to keep delayed ACK working. - - 2009-10-28: Kieran Mansley - * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code - to follow algorithm from TCP/IP Illustrated - - 2009-10-27: Kieran Mansley - * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK - - 2009-10-25: Simon Goldschmidt - * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if - pcb->recv is NULL to keep rcv_wnd correct) - - 2009-10-25: Simon Goldschmidt - * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state - - 2009-10-23: Simon Goldschmidt (David Empson) - * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes - - 2009-10-21: Simon Goldschmidt - * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and - trailing 1 byte len (SYN/FIN) - - 2009-10-21: Simon Goldschmidt - * tcp_out.c: Fixed bug #27315: zero window probe and FIN - - 2009-10-19: Simon Goldschmidt - * dhcp.c/.h: Minor code simplification (don't store received pbuf, change - conditional code to assert where applicable), check pbuf length before - testing for valid reply - - 2009-10-19: Simon Goldschmidt - * dhcp.c: Removed most calls to udp_connect since they aren't necessary - when using udp_sendto_if() - always stay connected to IP_ADDR_ANY. - - 2009-10-16: Simon Goldschmidt - * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop - valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is - enabled - - 2009-10-15: Simon Goldschmidt (Oleg Tyshev) - * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit - - 2009-10-15: Simon Goldschmidt - * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv() - timeout - - 2009-10-15: Simon Goldschmidt - * autoip.c: Fixed bug #27704: autoip starts with wrong address - LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead - of network byte order - - 2009-10-11 Simon Goldschmidt (Jörg Kesten) - * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments - which are not consecutive when retransmitting unacked segments - - 2009-10-09 Simon Goldschmidt - * opt.h: Fixed default values of some stats to only be enabled if used - Fixes bug #27338: sys_stats is defined when NO_SYS = 1 - - 2009-08-30 Simon Goldschmidt - * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK - function" by checking for loopback before calling ip_frag - - 2009-08-25 Simon Goldschmidt - * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0 - - 2009-08-23 Simon Goldschmidt - * ppp.c: bug #27078: Possible memory leak in pppInit() - - 2009-08-23 Simon Goldschmidt - * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result - is error. - - 2009-08-23 Simon Goldschmidt - * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF - Fixed wrong parenthesis, added check in init.c - - 2009-08-23 Simon Goldschmidt - * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms - - 2009-08-23 Simon Goldschmidt - * many ppp files: bug #27267: Added include to string.h where needed - - 2009-08-23 Simon Goldschmidt - * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian) - - -(STABLE-1.3.1) - - ++ New features: - - 2009-05-10 Simon Goldschmidt - * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option - LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only - one pbuf to help MACs that don't support scatter-gather DMA. - - 2009-05-09 Simon Goldschmidt - * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming - ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN - - 2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen - * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive - extended info about the currently received packet. - - 2009-04-27 Simon Goldschmidt - * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1 - - 2009-04-25 Simon Goldschmidt - * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next - bigger malloc pool if one is empty (only usable with MEM_USE_POOLS). - - 2009-04-21 Simon Goldschmidt - * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static - hosts table. New configuration options DNS_LOCAL_HOSTLIST and - DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined - as an external function for lookup. - - 2009-04-15 Simon Goldschmidt - * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique - - 2009-03-31 Kieran Mansley - * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for - TCP timestamp options, off by default. Rework tcp_enqueue() to - take option flags rather than specified option data - - 2009-02-18 Simon Goldschmidt - * cc.h: Added printf formatter for size_t: SZT_F - - 2009-02-16 Simon Goldschmidt (patch by Rishi Khan) - * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast - pings - - 2009-02-12 Simon Goldschmidt - * init.h: Added LWIP_VERSION to get the current version of the stack - - 2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler) - * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead - of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc - is otherwise used) - - 2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach) - * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial() - is only used by UDPLITE at present, so conditionalise it. - - 2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli) - * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP - "seed" address. This should reduce AUTOIP conflicts if - LWIP_AUTOIP_CREATE_SEED_ADDR is overridden. - - 2008-10-02 Jonathan Larmour and Rishi Khan - * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking - socket. - - 2008-06-30 Simon Goldschmidt - * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from - interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows - mem_free to run between mem_malloc iterations. Added illegal counter for - mem stats. - - 2008-06-27 Simon Goldschmidt - * stats.h/.c, some other files: patch #6483: stats module improvement: - Added defines to display each module's statistic individually, added stats - defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter. - - 2008-06-17 Simon Goldschmidt - * err.h: patch #6459: Made err_t overridable to use a more efficient type - (define LWIP_ERR_T in cc.h) - - 2008-06-17 Simon Goldschmidt - * slipif.c: patch #6480: Added a configuration option for slipif for symmetry - to loopif - - 2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli) - * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly - modified version of patch # 6370: Moved loopif code to netif.c so that - loopback traffic is supported on all netifs (all local IPs). - Added option to limit loopback packets for each netifs. - - - ++ Bugfixes: - 2009-08-12 Kieran Mansley - * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when - out of window or out of order properly - - 2009-08-12 Kieran Mansley - * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1 - - 2009-07-28 Simon Goldschmidt - * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s - - 2009-07-27 Kieran Mansley - * api.h api_msg.h netdb.h sockets.h: add missing #include directives - - 2009-07-09 Kieran Mansley - * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for - recv_avail and don't increment counters until message successfully - sent to mbox - - 2009-06-25 Kieran Mansley - * api_msg.c api.h: BUG26722: initialise netconn write variables - in netconn_alloc - - 2009-06-25 Kieran Mansley - * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set - - 2009-06-25 Kieran Mansley - * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct - simultaneous close behaviour, and make snd_nxt have the same meaning - as in the RFCs. - - 2009-05-12 Simon Goldschmidt - * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on - arp_table / uses etharp_query" by adding etharp_gratuitous() - - 2009-05-12 Simon Goldschmidt - * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options - to the IP header (used by igmp_ip_output_if) - - 2009-05-06 Simon Goldschmidt - * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if - defined) for SWAP_BYTES_IN_WORD to speed up checksumming. - - 2009-05-05 Simon Goldschmidt - * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select() - to crash - - 2009-05-04 Simon Goldschmidt - * init.c: snmp was not initialized in lwip_init() - - 2009-05-04 Frédéric Bernon - * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled. - - 2009-05-03 Simon Goldschmidt - * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full - (and unsent->next == NULL) - - 2009-05-02 Simon Goldschmidt - * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after - 1.3.0 in CVS only) - fixes compilation of ppp_oe.c - - 2009-05-02 Simon Goldschmidt - * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields - - 2009-05-01 Simon Goldschmidt - * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets - - 2009-05-01 Simon Goldschmidt - * ppp.c: bug #24228: Memory corruption with PPP and DHCP - - 2009-04-29 Frédéric Bernon - * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the - SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception - of broadcast packets even when this option wasn't set. Port maintainers - which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h. - If you want this option also filter broadcast on recv operations, you also - have to set IP_SOF_BROADCAST_RECV=1 in opt.h. - - 2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen - * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and - DHCP/AUTOIP cooperation - - 2009-04-25 Simon Goldschmidt, Oleg Tyshev - * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd - Fixed by sorting the unsent and unacked queues (segments are inserted at the - right place in tcp_output and tcp_rexmit). - - 2009-04-25 Simon Goldschmidt - * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation - when debugging": memp_sizes contained the wrong sizes (including sanity - regions); memp pools for MEM_USE_POOLS were too small - - 2009-04-24 Simon Goldschmidt, Frédéric Bernon - * inet.c: patch #6765: Fix a small problem with the last changes (incorrect - behavior, with with ip address string not ended by a '\0', a space or a - end of line) - - 2009-04-19 Simon Goldschmidt - * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails, - pcb->err is called, not pcb->connected (with an error code). - - 2009-04-19 Simon Goldschmidt - * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with - no-copy-tcpwrite": deallocate option data, only concat segments with same flags - - 2009-04-19 Simon Goldschmidt - * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated - in the header pbuf, not the data pbuf) - - 2009-04-18 Simon Goldschmidt - * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore() - - 2009-04-15 Simon Goldschmidt - * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp - - 2009-04-15 Simon Goldschmidt - * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in - - 2009-04-15 Simon Goldschmidt - * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function - ip_hinted_output() (for smaller code mainly) - - 2009-04-15 Simon Goldschmidt - * inet.c: patch #6765: Supporting new line characters in inet_aton() - - 2009-04-15 Simon Goldschmidt - * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option; - Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu - is big enough in dhcp_start - - 2009-04-15 Simon Goldschmidt - * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak - - 2009-04-15 Simon Goldschmidt - * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY - - 2009-04-15 Simon Goldschmidt - * sockets.c: bug #26121: set_errno can be overridden - - 2009-04-09 Kieran Mansley (patch from Luca Ceresoli ) - * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when - LWIP_TCP==0 - - 2009-04-09 Kieran Mansley (patch from Roy Lee ) - * tcp.h: Patch#6802 Add do-while-clauses to those function like - macros in tcp.h - - 2009-03-31 Kieran Mansley - * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window - updates are calculated and sent (BUG20515) - - * tcp_in.c: cope with SYN packets received during established states, - and retransmission of initial SYN. - - * tcp_out.c: set push bit correctly when tcp segments are merged - - 2009-03-27 Kieran Mansley - * tcp_out.c set window correctly on probes (correcting change made - yesterday) - - 2009-03-26 Kieran Mansley - * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping - connections where no reset required (bug #25622) - - * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes - (bug #20779) - - 2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach) - * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be - too small depending on MEM_ALIGNMENT - - 2009-02-16 Simon Goldschmidt - * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard; - converted size argument of netconn_write to 'size_t' - - 2009-02-16 Simon Goldschmidt - * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host - by moving accept callback function pointer to TCP_PCB_COMMON - - 2009-02-12 Simon Goldschmidt - * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size" - option) - - 2009-02-11 Simon Goldschmidt - * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start) - - 2009-02-11 Simon Goldschmidt - * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize: - RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv()) - - 2009-02-10 Simon Goldschmidt - * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD: - Accepts_pending is decrease on a corresponding listen pcb when a connection - in state SYN_RCVD is close. - - 2009-01-28 Jonathan Larmour - * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run - out of pool pbufs. - - 2008-12-19 Simon Goldschmidt - * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 - - 2008-12-10 Tamas Somogyi, Frédéric Bernon - * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and - port uses deleted netbuf. - - 2008-10-18 Simon Goldschmidt - * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length - in tcp_parseopt - - 2008-10-15 Simon Goldschmidt - * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers - by packing the struct ip_reass_helper. - - 2008-10-03 David Woodhouse, Jonathan Larmour - * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address. - - 2008-10-02 Jonathan Larmour - * dns.c: Hard-code structure sizes, to avoid issues on some compilers where - padding is included. - - 2008-09-30 Jonathan Larmour - * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an - assertion check that addrlen isn't NULL. - - 2008-09-30 Jonathan Larmour - * tcp.c: Fix bug #24227, wrong error message in tcp_bind. - - 2008-08-26 Simon Goldschmidt - * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and - inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h - - 2008-08-14 Simon Goldschmidt - * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when - tcp_close returns != ERR_OK) - - 2008-07-08 Frédéric Bernon - * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters - in macros, mainly if MEM_STATS=0 and MEMP_STATS=0). - - 2008-06-24 Jonathan Larmour - * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused - if tcp_seg_copy fails. - - 2008-06-17 Simon Goldschmidt - * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations) - and created defines for swapping bytes and folding u32 to u16. - - 2008-05-30 Kieran Mansley - * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd - rather than rcv_ann_wnd when deciding if packets are in-window. - Contributed by - - 2008-05-30 Kieran Mansley - * mem.h: Fix BUG#23254. Change macro definition of mem_* to allow - passing as function pointers when MEM_LIBC_MALLOC is defined. - - 2008-05-09 Jonathan Larmour - * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to - stop it being treated as a fatal error. - - 2008-04-15 Simon Goldschmidt - * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP - (flag now cleared) - - 2008-03-27 Simon Goldschmidt - * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free - from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1 - in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs - or heap memory from interrupt context - - 2008-03-26 Simon Goldschmidt - * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote - host sent a zero mss as TCP option. - - -(STABLE-1.3.0) - - ++ New features: - - 2008-03-10 Jonathan Larmour - * inet_chksum.c: Allow choice of one of the sample algorithms to be - made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM. - - 2008-01-22 Frédéric Bernon - * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in - TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names. - - 2008-01-14 Frédéric Bernon - * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable - to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the - tcp_recv callback (see rawapi.txt). - - 2008-01-14 Frédéric Bernon, Marc Chaland - * ip.c: Integrate patch #6369" ip_input : checking before realloc". - - 2008-01-12 Frédéric Bernon - * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field - netconn::sem per netconn::op_completed like suggested for the task #7490 - "Add return value to sys_mbox_post". - - 2008-01-12 Frédéric Bernon - * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE, - DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues - sizes), like suggested for the task #7490 "Add return value to sys_mbox_post". - - 2008-01-10 Frédéric Bernon - * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490 - "Add return value to sys_mbox_post". tcpip_callback is always defined as - "blocking" ("block" parameter = 1). - - 2008-01-10 Frédéric Bernon - * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field - netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490 - "Add return value to sys_mbox_post". - - 2008-01-05 Frédéric Bernon - * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h: - Introduce changes for task #7490 "Add return value to sys_mbox_post" with some - modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which - indicate the number of pointers query by the mailbox. There is three defines - in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the - netconn::acceptmbox. Port maintainers, you can decide to just add this new - parameter in your implementation, but to ignore it to keep the previous behavior. - The new sys_mbox_trypost function return a value to know if the mailbox is - full or if the message is posted. Take a look to sys_arch.txt for more details. - This new function is used in tcpip_input (so, can be called in an interrupt - context since the function is not blocking), and in recv_udp and recv_raw. - - 2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour - * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c, - tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the - "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add - documentation in the rawapi.txt file. - - 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm) - * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer - - 2007-12-31 Frédéric Bernon, Luca Ceresoli - * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets - in autoip". The change in etharp_raw could be removed, since all calls to - etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be - wrong in the future. - - 2007-12-30 Frédéric Bernon, Tom Evans - * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address - Filtering" reported by Tom Evans. - - 2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour - * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c, - sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API - applications have to call 'tcp_accepted(pcb)' in their accept callback to - keep accepting new connections. - - 2007-12-13 Frédéric Bernon - * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result" - by err_t type. Add a new err_t code "ERR_INPROGRESS". - - 2007-12-12 Frédéric Bernon - * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles - are the one which have ram usage. - - 2007-12-05 Frédéric Bernon - * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static - set of variables (=0) or a local one (=1). In this last case, your port should - provide a function "struct hostent* sys_thread_hostent( struct hostent* h)" - which have to do a copy of "h" and return a pointer ont the "per-thread" copy. - - 2007-12-03 Simon Goldschmidt - * ip.c: ip_input: check if a packet is for inp first before checking all other - netifs on netif_list (speeds up packet receiving in most cases) - - 2007-11-30 Simon Goldschmidt - * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access - UDP: move a (connected) pcb selected for input to the front of the list of - pcbs so that it is found faster next time. Same for RAW pcbs that have eaten - a packet. - - 2007-11-28 Simon Goldschmidt - * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS - - 2007-11-25 Simon Goldschmidt - * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy - algorithm. - - 2007-11-24 Simon Goldschmidt - * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c - to the new file netdb.c; included lwip_getaddrinfo. - - 2007-11-21 Simon Goldschmidt - * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss - based on the MTU of the netif used to send. Enabled by default. Disable by - setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492. - - 2007-11-19 Frédéric Bernon - * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name - received match the name query), implement DNS_USES_STATIC_BUF (the place where - copy dns payload to parse the response), return an error if there is no place - for a new query, and fix some minor problems. - - 2007-11-16 Simon Goldschmidt - * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c - removed files: core/inet.c, core/inet6.c - Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into - inet and chksum part; changed includes in all lwIP files as appropriate - - 2007-11-16 Simon Goldschmidt - * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential - dns resolver function for netconn api (netconn_gethostbyname) and socket api - (gethostbyname/gethostbyname_r). - - 2007-11-15 Jim Pettinato, Frédéric Bernon - * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name - requests with RAW api interface. Initialization is done in lwip_init() with - build time options. DNS timer is added in tcpip_thread context. DHCP can set - DNS server ip addresses when options are received. You need to set LWIP_DNS=1 - in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get - some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo" - list with points to improve. - - 2007-11-06 Simon Goldschmidt - * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly - enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status - for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined. - - 2007-11-06 Simon Goldschmidt - * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include - core header files in api.h (ip/tcp/udp/raw.h) to hide the internal - implementation from netconn api applications. - - 2007-11-03 Frédéric Bernon - * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP & - RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled - by default). Netconn API users can use the netconn_recv_bufsize macro to access - it. This is a first release which have to be improve for TCP. Note it used the - netconn::recv_avail which need to be more "thread-safe" (note there is already - the problem for FIONREAD with lwip_ioctl/ioctlsocket). - - 2007-11-01 Frédéric Bernon, Marc Chaland - * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c: - Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api - layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api - layer. This option enable to delayed TCP PUSH flag on multiple "write" calls. - Note that previous "copy" parameter for "write" APIs is now called "apiflags". - - 2007-10-24 Frédéric Bernon - * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than - TCP_EVENT_xxx macros to get a code more readable. It could also help to remove - some code (like we have talk in "patch #5919 : Create compile switch to remove - select code"), but it could be done later. - - 2007-10-08 Simon Goldschmidt - * many files: Changed initialization: many init functions are not needed any - more since we now rely on the compiler initializing global and static - variables to zero! - - 2007-10-06 Simon Goldschmidt - * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY - to enqueue the received pbufs so that multiple packets can be reassembled - simultaneously and no static reassembly buffer is needed. - - 2007-10-05 Simon Goldschmidt - * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so - all netifs (or ports) can use it. - - 2007-10-05 Frédéric Bernon - * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the - common function to reduce a little bit the footprint (for all functions using - only the "netif" parameter). - - 2007-10-03 Frédéric Bernon - * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down, - netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce - a little bit the footprint (for all functions using only the "netif" parameter). - - 2007-09-15 Frédéric Bernon - * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF - option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for - netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for - IP_MULTICAST_TTL and IP_MULTICAST_IF. - - 2007-09-10 Frédéric Bernon - * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles - even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime() - each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can - decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but - call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime() - or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. - This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside - snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only - when it's queried (any direct call to "sysuptime" is changed by a call to - snmp_get_sysuptime). - - 2007-09-09 Frédéric Bernon, Bill Florac - * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP, - and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags - if you want IGMP on an interface. igmp_stop() is now called inside netif_remove(). - igmp_report_groups() is now called inside netif_set_link_up() (need to have - LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait - the next query message to receive the matching multicast streams). - - 2007-09-08 Frédéric Bernon - * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains - IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change). - Use this new field to access to common pcb fields (ttl, tos, so_options, etc...). - Enable to access to these fields with LWIP_TCP=0. - - 2007-09-05 Frédéric Bernon - * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h, - ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option - LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default). - Be careful, disabling ICMP make your product non-compliant to RFC1122, but - help to reduce footprint, and to reduce "visibility" on the Internet. - - 2007-09-05 Frédéric Bernon, Bill Florac - * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list - for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new - parameters have to be provided: a task name, and a task stack size. For this - one, since it's platform dependant, you could define the best one for you in - your lwipopts.h. For port maintainers, you can just add these new parameters - in your sys_arch.c file, and but it's not mandatory, use them in your OS - specific functions. - - 2007-09-05 Frédéric Bernon - * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings - inside init.c for task #7142 "Sanity check user-configurable values". - - 2007-09-04 Frédéric Bernon, Bill Florac - * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by - memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the - value). It will avoid potential fragmentation problems, use a counter to know - how many times a group is used on an netif, and free it when all applications - leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity - check if LWIP_IGMP!=0). - - 2007-09-03 Frédéric Bernon - * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement". - Initialize igmp_mac_filter to NULL in netif_add (this field should be set in - the netif's "init" function). Use the "imr_interface" field (for socket layer) - and/or the "interface" field (for netconn layer), for join/leave operations. - The igmp_join/leavegroup first parameter change from a netif to an ipaddr. - This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany). - - 2007-08-30 Frédéric Bernon - * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions - from api/api_lib". Now netbuf API is independant of netconn, and can be used - with other API (application based on raw API, or future "socket2" API). Ports - maintainers just have to add src/api/netbuf.c in their makefile/projects. - - 2007-08-30 Frédéric Bernon, Jonathan Larmour - * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check - user-configurable values". - - 2007-08-29 Frédéric Bernon - * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start. - igmp_start is call inside netif_add. Now, igmp initialization is in the same - spirit than the others modules. Modify some IGMP debug traces. - - 2007-08-29 Frédéric Bernon - * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function" - Add lwip_init function to regroup all modules initializations, and to provide - a place to add code for task #7142 "Sanity check user-configurable values". - Ports maintainers should remove direct initializations calls from their code, - and add init.c in their makefiles. Note that lwip_init() function is called - inside tcpip_init, but can also be used by raw api users since all calls are - disabled when matching options are disabled. Also note that their is new options - in opt.h, you should configure in your lwipopts.h (they are enabled per default). - - 2007-08-26 Marc Boucher - * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL - since they can under certain circumstances be called with an invalid conn - pointer after the connection has been closed (and conn has been freed). - - 2007-08-25 Frédéric Bernon (Artem Migaev's Patch) - * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up". - Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set. - - 2007-08-22 Frédéric Bernon - * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK - to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release. - - 2007-08-22 Frédéric Bernon - * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT & - ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the - name is tcpip_input (we keep the name of 1.2.0 function). - - 2007-08-17 Jared Grubb - * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool - settings into new memp_std.h and optional user file lwippools.h. This adds - more dynamic mempools, and allows the user to create an arbitrary number of - mempools for mem_malloc. - - 2007-08-16 Marc Boucher - * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function; - otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely - close the connection. - - 2007-08-16 Marc Boucher - * sockets.c: lwip_accept(): check netconn_peer() error return. - - 2007-08-16 Marc Boucher - * mem.c, mem.h: Added mem_calloc(). - - 2007-08-16 Marc Boucher - * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT) - for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG - and starving other message types. - Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API - - 2007-08-16 Marc Boucher - * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf - type and flgs (later renamed to flags). - Use enum pbuf_flag as pbuf_type. Renumber PBUF_FLAG_*. - Improved lwip_recvfrom(). TCP push now propagated. - - 2007-08-16 Marc Boucher - * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global - provided by etharp. - - 2007-08-16 Marc Boucher - * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h, - etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c: - Added PPPoE support and various PPP improvements. - - 2007-07-25 Simon Goldschmidt - * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial, - making netbuf_copy_partial use this function. - - 2007-07-25 Simon Goldschmidt - * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with - 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and - other stacks. - - 2007-07-13 Jared Grubb (integrated by Frédéric Bernon) - * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add - a link callback in the netif struct, and functions to handle it. Be carefull - for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c) - if you want to be sure to be compatible with future changes... - - 2007-06-30 Frédéric Bernon - * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions. - - 2007-06-21 Simon Goldschmidt - * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both - LWIP_AUTOIP =0 and =1 to remove redundant code. - - 2007-06-21 Simon Goldschmidt - * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option - MEM_USE_POOLS to use 4 pools with different sized elements instead of a - heap. This both prevents memory fragmentation and gives a higher speed - at the cost of more memory consumption. Turned off by default. - - 2007-06-21 Simon Goldschmidt - * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of - netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into - int to be able to send a bigger buffer than 64K with one time (mainly - used from lwip_send). - - 2007-06-21 Simon Goldschmidt - * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write - into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too. - - 2007-06-21 Simon Goldschmidt - * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in - netconn_write from api_lib.c to api_msg.c to also prevent multiple context- - changes on low memory or empty send-buffer. - - 2007-06-18 Simon Goldschmidt - * etharp.c, etharp.h: Changed etharp to use a defined hardware address length - of 6 to avoid loading netif->hwaddr_len every time (since this file is only - used for ethernet and struct eth_addr already had a defined length of 6). - - 2007-06-17 Simon Goldschmidt - * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets - to disable UDP checksum generation on transmit. - - 2007-06-13 Frédéric Bernon, Simon Goldschmidt - * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid - pointers or parameters, and let the possibility to redefined it in cc.h. Use - this macro to check "conn" parameter in api_msg.c functions. - - 2007-06-11 Simon Goldschmidt - * sockets.c, sockets.h: Added UDP lite support for sockets - - 2007-06-10 Simon Goldschmidt - * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled - by default) to switch off UDP-Lite support if not needed (reduces udp.c code - size) - - 2007-06-09 Dominik Spies (integrated by Frédéric Bernon) - * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h: - AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and - LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt - (see TODO mark in the source code). - - 2007-06-09 Simon Goldschmidt - * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for - etharp_output() to match netif->output so etharp_output() can be used - directly as netif->output to save one function call. - - 2007-06-08 Simon Goldschmidt - * netif.h, ethernetif.c, slipif.c, loopif.c: Added define - NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables, - added initialization of those to ethernetif, slipif and loopif. - - 2007-05-18 Simon Goldschmidt - * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF - (defaulting to off for now) that can be set to 0 to send fragmented - packets by passing PBUF_REFs down the stack. - - 2007-05-23 Frédéric Bernon - * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP - connections, such present in patch #5959. - - 2007-05-23 Frédéric Bernon - * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx - code in only one part... - - 2007-05-18 Simon Goldschmidt - * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp - elements to overflow. This is achieved by adding some bytes before and after - each pool element (increasing their size, of course), filling them with a - prominent value and checking them on freeing the element. - Set it to 2 to also check every element in every pool each time memp_malloc() - or memp_free() is called (slower but more helpful). - - 2007-05-10 Simon Goldschmidt - * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for - PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce - code size. - - 2007-05-11 Frédéric Bernon - * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c: - Include a function pointer instead of a table index in the message to reduce - footprint. Disable some part of lwip_send and lwip_sendto if some options are - not set (LWIP_TCP, LWIP_UDP, LWIP_RAW). - - 2007-05-10 Simon Goldschmidt - * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus - \ extern "C" {' in all header files. Now you can write your application using - the lwIP stack in C++ and simply #include the core files. Note I have left - out the netif/ppp/*h header files for now, since I don't know which files are - included by applications and which are for internal use only. - - 2007-05-09 Simon Goldschmidt - * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library - memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for - situations where some compilers might inline the copy and save a function - call. Also replaced all calls to memcpy() with calls to (S)MEMCPY(). - - 2007-05-08 Simon Goldschmidt - * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc()) - to be overriden in case the C-library malloc implementation is not protected - against concurrent access. - - 2007-05-04 Simon Goldschmidt (Atte Kojo) - * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending - multiple packets to the same host. - - 2007-05-04 Frédéric Bernon, Jonathan Larmour - * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible - to corrupt remote addr/port connection state". Reduce problems "not enought memory" with - netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between - sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function. - Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct, - these fields are now renamed "addr" & "port". - - 2007-04-11 Jonathan Larmour - * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new - sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return - with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro - by the port in sys_arch.h if desired. - - 2007-04-06 Frédéric Bernon, Simon Goldschmidt - * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API - allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp - clients, using new functions from netifapi.h. Disable as default (no port change to do). - - 2007-04-05 Frédéric Bernon - * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant. - - 2007-04-04 Simon Goldschmidt - * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x) - use this for and architecture-independent form to tell the compiler you intentionally - are not using this variable. Can be overriden in cc.h. - - 2007-03-28 Frédéric Bernon - * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to - define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded - string, point on one of your's ethernetif field, or alloc a string you will free yourself). - It will be used by DHCP to register a client hostname, but can also be use when you call - snmp_set_sysname. - - 2007-03-28 Frédéric Bernon - * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to - initialize a network interface's flag with. It tell this interface is an ethernet - device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility - Support for IPv4" section 4.6) when interface is "up" with netif_set_up(). - - 2007-03-26 Frédéric Bernon, Jonathan Larmour - * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build - time if you only use PPP or SLIP. The default is enable. Note we don't have to call - etharp_init in your port's initilization sequence if you use tcpip.c, because this call - is done in tcpip_init function. - - 2007-03-22 Frédéric Bernon - * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the - new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in - your lwipopts.h. More, unused counters are not defined in the stats structs, and not - display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined - but never used. Fix msg_in.c with the correct #if test for a stat display. - - 2007-03-21 Kieran Mansley - * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). - Provides callback on netif up/down state change. - - 2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds - * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c, - ip.c, netif.h, tcpip.c, opt.h: - New configuration option LWIP_IGMP to enable IGMP processing. Based on only one - filter per all network interfaces. Declare a new function in netif to enable to - control the MAC filter (to reduce lwIP traffic processing). - - 2007-03-11 Frédéric Bernon - * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can - be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this - unless you know what you're doing (default are RFC1122 compliant). Note - that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds. - - 2007-03-08 Frédéric Bernon - * tcp.h: Keepalive values can be configured at compile time, but don't change - this unless you know what you're doing (default are RFC1122 compliant). - - 2007-03-08 Frédéric Bernon - * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h: - Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO - on UDP sockets/netconn. - - 2007-03-08 Simon Goldschmidt - * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time. - - 2007-03-06 Frédéric Bernon - * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: - Implement SO_RCVTIMEO on UDP sockets/netconn. - - 2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt) - * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated - on the stack and remove the API msg type from memp - - 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) - * sockets.h, sockets.c: Move socket initialization to new - lwip_socket_init() function. - NOTE: this changes the API with ports. Ports will have to be - updated to call lwip_socket_init() now. - - 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) - * api_lib.c: Use memcpy in netbuf_copy_partial. - - - ++ Bug fixes: - - 2008-03-17 Frédéric Bernon, Ed Kerekes - * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have - some problems to fill the IP header on some targets, use now the - ip.h macros to do it). - - 2008-03-13 Frédéric Bernon - * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using - (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a - TCP connection caused a crash. Note that using (lwip_)recvfrom - like this is a bit slow and that using (lwip)getpeername is the - good lwip way to do it (so, using recv is faster on tcp sockets). - - 2008-03-12 Frédéric Bernon, Jonathan Larmour - * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's - recv_raw() does not consume data", and the ping sample (with - LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom - returned the IP payload, without the IP header). - - 2008-03-04 Jonathan Larmour - * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors - and/or warnings on some systems where mem_size_t and size_t differ. - * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc. - - 2008-03-04 Kieran Mansley (contributions by others) - * Numerous small compiler error/warning fixes from contributions to - mailing list after 1.3.0 release candidate made. - - 2008-01-25 Cui hengbin (integrated by Frédéric Bernon) - * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures. - - 2008-01-15 Kieran Mansley - * tcp_out.c: BUG20511. Modify persist timer to start when we are - prevented from sending by a small send window, not just a zero - send window. - - 2008-01-09 Jonathan Larmour - * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid - conflict with Linux system headers. - - 2008-01-06 Jonathan Larmour - * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP - address entirely on receiving a DHCPNAK, and restarting discovery. - - 2007-12-21 Simon Goldschmidt - * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail - is not protected" by using new macros for interlocked access to modify/test - netconn->recv_avail. - - 2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev) - * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state) - - 2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm) - * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling - of silly window avoidance and prevent lwIP from shrinking the window) - - 2007-12-04 Simon Goldschmidt - * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last - data packet was lost): add assert that all segment lists are empty in - tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED - state from LAST_ACK in tcp_process - - 2007-12-02 Simon Goldschmidt - * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET - If including for system-struct timeval, LWIP_TIMEVAL_PRIVATE now - has to be set to 0 in lwipopts.h - - 2007-12-02 Simon Goldschmidt - * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always - allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen - netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox. - This is a fix for thread-safety and allocates all items needed for a netconn - when the netconn is created. - - 2007-11-30 Simon Goldschmidt - * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple - netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed - to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same - port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address) - - 2007-11-27 Simon Goldschmidt - * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by - letting ip_route only use netifs that are up. - - 2007-11-27 Simon Goldschmidt - * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF - and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and - sockets block most operations once they have seen a fatal error. - - 2007-11-27 Simon Goldschmidt - * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the - netif to send as an argument (to be able to send on netifs that are down). - - 2007-11-26 Simon Goldschmidt - * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs - arrive out-of-order - - 2007-11-21 Simon Goldschmidt - * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early - Fixed the nagle algorithm; nagle now also works for all raw API applications - and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY' - - 2007-11-12 Frédéric Bernon - * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most - of the netconn_peer and netconn_addr processing is done inside tcpip_thread - context in do_getaddr. - - 2007-11-10 Simon Goldschmidt - * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can - happen any time). Now the packet simply isn't enqueued when out of memory. - - 2007-11-01 Simon Goldschmidt - * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or - TCP_MSS if that is smaller) as long as no MSS option is received from the - remote host. - - 2007-11-01 Simon Goldschmidt - * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN) - is now based on TCP_MSS instead of pcb->mss (on passive open now effectively - sending our configured TCP_MSS instead of the one received). - - 2007-11-01 Simon Goldschmidt - * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was - calculated based on the configured TCP_MSS, not on the MSS option received - with SYN+ACK. - - 2007-10-09 Simon Goldschmidt - * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too - short and also was generated wrong if checksum coverage != tot_len; - receive: checksum was calculated wrong if checksum coverage != tot_len - - 2007-10-08 Simon Goldschmidt - * mem.c: lfree was not updated in mem_realloc! - - 2007-10-07 Frédéric Bernon - * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential - crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT: - this change cause an API breakage for netconn_addr, since a parameter - type change. Any compiler should cause an error without any changes in - yours netconn_peer calls (so, it can't be a "silent change"). It also - reduce a little bit the footprint for socket layer (lwip_getpeername & - lwip_getsockname use now a common lwip_getaddrname function since - netconn_peer & netconn_addr have the same parameters). - - 2007-09-20 Simon Goldschmidt - * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state) - by checking tcp_tw_pcbs also - - 2007-09-19 Simon Goldschmidt - * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies) - - 2007-09-15 Mike Kleshov - * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used) - - 2007-09-06 Frédéric Bernon - * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove - it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which - already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h" - if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h. - - 2007-08-30 Frédéric Bernon - * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, - and fix some coding style. - - 2007-08-28 Frédéric Bernon - * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any - kind of packets. These packets are considered like Ethernet packets (payload - pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets - are considered like IP packets (payload pointing to iphdr). - - 2007-08-27 Frédéric Bernon - * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error - problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state - and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT). - - 2007-08-24 Kieran Mansley - * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy - compiler (Paradigm C++) - - 2007-08-09 Frédéric Bernon, Bill Florac - * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement. - Introduce IGMP_STATS to centralize statistics management. - - 2007-08-09 Frédéric Bernon, Bill Florac - * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast - packet on a udp pcb binded on an netif's IP address, and not on "any". - - 2007-08-09 Frédéric Bernon, Bill Florac - * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement. - This is mainly on using lookup/lookfor, and some coding styles... - - 2007-07-26 Frédéric Bernon (and "thedoctor") - * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages. - - 2007-07-25 Simon Goldschmidt - * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if - tcp_output fails in tcp_close, the code in do_close_internal gets simpler - (tcp_output is called again later from tcp timers). - - 2007-07-25 Simon Goldschmidt - * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old - copy_from_pbuf, which illegally modified the given pbuf. - - 2007-07-25 Simon Goldschmidt - * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs: - changed snd_queuelen++ to snd_queuelen += pbuf_clen(p). - - 2007-07-24 Simon Goldschmidt - * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the - correct state (must be CLOSED). - - 2007-07-13 Thomas Taranowski (commited by Jared Grubb) - * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed - allocation. It now returns NULL. - - 2007-07-13 Frédéric Bernon - * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in - all error cases. - - 2007-07-13 Frédéric Bernon - * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed, - because current code doesn't follow rawapi.txt documentation. - - 2007-07-13 Kieran Mansley - * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in - out of sequence processing of received packets - - 2007-07-03 Simon Goldschmidt - * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an - assumption is made that this pbuf is in one piece (i.e. not chained). These - assumptions clash with the possibility of converting to fully pool-based - pbuf implementations, where PBUF_RAM pbufs might be chained. - - 2007-07-03 Simon Goldschmidt - * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems - when closing tcp netconns: removed conn->sem, less context switches when - closing, both netconn_close and netconn_delete should safely close tcp - connections. - - 2007-07-02 Simon Goldschmidt - * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c, - tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off) - to cache ARP table indices with each pcb instead of single-entry cache for - the complete stack. - - 2007-07-02 Simon Goldschmidt - * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent - warnings when assigning to smaller types. - - 2007-06-28 Simon Goldschmidt - * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing. - - 2007-06-28 Simon Goldschmidt - * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if - a segment contained chained pbufs) - - 2007-06-28 Frédéric Bernon - * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute - a "pseudo-random" value based on netif's MAC and some autoip fields. It's always - possible to define this macro in your own lwipopts.h to always use C library's - rand(). Note that autoip_create_rand_addr doesn't use this macro. - - 2007-06-28 Frédéric Bernon - * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option - LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications - in api_lib/api_msg (use pointers and not type with table, etc...) - - 2007-06-26 Simon Goldschmidt - * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines. - - 2007-06-25 Simon Goldschmidt - * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload - for udp packets with no matching pcb. - - 2007-06-25 Simon Goldschmidt - * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match - could get udp input packets if the remote side matched. - - 2007-06-13 Simon Goldschmidt - * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get - changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0. - - 2007-06-13 Simon Goldschmidt - * api_msg.c: pcb_new sets conn->err if protocol is not implemented - -> netconn_new_..() does not allocate a new connection for unsupported - protocols. - - 2007-06-13 Frédéric Bernon, Simon Goldschmidt - * api_lib.c: change return expression in netconn_addr and netconn_peer, because - conn->err was reset to ERR_OK without any reasons (and error was lost)... - - 2007-06-13 Frédéric Bernon, Matthias Weisser - * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename - MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid - some macro names collision with some OS macros. - - 2007-06-11 Simon Goldschmidt - * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0, - create checksum over the complete packet. On RX, if it's < 8 (and not 0), - discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both - UDP & UDP Lite. - - 2007-06-11 Srinivas Gollakota & Oleg Tyshev - * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags" - where TCP flags wasn't initialized in tcp_keepalive. - - 2007-06-03 Simon Goldschmidt - * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function - registered, p->payload was modified without modifying p->len if sending - icmp_dest_unreach() (had no negative effect but was definitively wrong). - - 2007-06-03 Simon Goldschmidt - * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp - re-used the input pbuf even if that didn't have enough space to include the - link headers. Now the space is tested and a new pbuf is allocated for the - echo response packet if the echo request pbuf isn't big enough. - - 2007-06-01 Simon Goldschmidt - * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread. - - 2007-05-23 Frédéric Bernon - * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only - allocated by do_listen if success) and netconn_accept errors handling. In - most of api_lib functions, we replace some errors checkings like "if (conn==NULL)" - by ASSERT, except for netconn_delete. - - 2007-05-23 Frédéric Bernon - * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return - an error code if it's impossible to fetch a pbuf on a TCP connection (and not - directly close the recvmbox). - - 2007-05-22 Simon Goldschmidt - * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of - bound but unconnected (and non-listening) tcp_pcbs. - - 2007-05-22 Frédéric Bernon - * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only - used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of - sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features - like "sys_timeout" in their application threads. - - 2007-05-22 Frédéric Bernon - * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see - which parameters are used by which do_xxx function, and to avoid "misusing" - parameters (patch #5938). - - 2007-05-22 Simon Goldschmidt - * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938: - changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto - is only 8 bits wide. This affects the api, as there, the protocol was - u16_t, too. - - 2007-05-18 Simon Goldschmidt - * memp.c: addition to patch #5913: smaller pointer was returned but - memp_memory was the same size -> did not save memory. - - 2007-05-16 Simon Goldschmidt - * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns - != ERR_OK. - - 2007-05-16 Simon Goldschmidt - * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same - as the one of the netif used for sending to prevent sending from old - addresses after a netif address gets changed (partly fixes bug #3168). - - 2007-05-16 Frédéric Bernon - * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work - with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in - tcpip_init) because we have to be sure that network interfaces are already - added (mac filter is updated only in igmp_init for the moment). - - 2007-05-16 Simon Goldschmidt - * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls - into sys_arch_sem_wait calls to prevent timers from running while waiting - for the heap. This fixes bug #19167. - - 2007-05-13 Simon Goldschmidt - * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines - for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from - tcp.h to sockets.h. - - 2007-05-07 Simon Goldschmidt - * mem.c: Another attempt to fix bug #17922. - - 2007-05-04 Simon Goldschmidt - * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy() - implementation so that it can be reused (don't allocate the target - pbuf inside pbuf_copy()). - - 2007-05-04 Simon Goldschmidt - * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem - to save a little RAM (next pointer of memp is not used while not in pool). - - 2007-05-03 "maq" - * sockets.c: Fix ioctl FIONREAD when some data remains from last recv. - (patch #3574). - - 2007-04-23 Simon Goldschmidt - * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results - in NULL reference for incoming TCP packets". Loopif has to be configured - (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input() - (multithreading environments, e.g. netif->input() = tcpip_input()) or - putting packets on a list that is fed to the stack by calling loopif_poll() - (single-thread / NO_SYS / polling environment where e.g. - netif->input() = ip_input). - - 2007-04-17 Jonathan Larmour - * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold - the difference between two u16_t's. - * sockets.h: FD_SETSIZE needs to match number of sockets, which is - MEMP_NUM_NETCONN in sockets.c right now. - - 2007-04-12 Jonathan Larmour - * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580). - - 2007-04-12 Kieran Mansley - * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission - timer is reset to fix bug#19434, with help from Oleg Tyshev. - - 2007-04-11 Simon Goldschmidt - * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than - previously thought need to be copied (everything but PBUF_ROM!). Cleaned up - pbuf.c: removed functions no needed any more (by etharp). - - 2007-04-11 Kieran Mansley - * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix - "Constant is long" warnings with 16bit compilers. Contributed by - avatar@mmlab.cse.yzu.edu.tw - - 2007-04-05 Frédéric Bernon, Jonathan Larmour - * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on - the mailbox is active". Now, the post is only done during a connect, and do_send, - do_write and do_join_leave_group don't do anything if a previous error was signaled. - - 2007-04-03 Frédéric Bernon - * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output - packets. See patch #5834. - - 2007-03-30 Frédéric Bernon - * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add - missing pcb allocations checking (in do_bind, and for each raw_new). Fix style. - - 2007-03-30 Frédéric Bernon - * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with - others environment defines (these were too "generic"). - - 2007-03-28 Frédéric Bernon - * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call - result and can cause a crash. lwip_send now check netbuf_ref result. - - 2007-03-28 Simon Goldschmidt - * sockets.c Remove "#include " from sockets.c to avoid multiple - definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is - defined. This is the way it should have been already (looking at - doc/sys_arch.txt) - - 2007-03-28 Kieran Mansley - * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS + - IP and TCP headers *and* physical link headers - - 2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov) - * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause - to send some garbage. It is not a definitive solution, but the patch does solve - the problem for most cases. - - 2007-03-22 Frédéric Bernon - * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used). - - 2007-03-22 Frédéric Bernon - * api_lib.c: somes resources couldn't be freed if there was errors during - netconn_new_with_proto_and_callback. - - 2007-03-22 Frédéric Bernon - * ethernetif.c: update netif->input calls to check return value. In older ports, - it's a good idea to upgrade them, even if before, there could be another problem - (access to an uninitialized mailbox). - - 2007-03-21 Simon Goldschmidt - * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed - by casting to unsigned). - - 2007-03-21 Frédéric Bernon - * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from - api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a - dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call. - Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a - faster and more reliable communication between api_lib and tcpip. - - 2007-03-21 Frédéric Bernon - * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0. - - 2007-03-21 Frédéric Bernon - * api_msg.c, igmp.c, igmp.h: Fix C++ style comments - - 2007-03-21 Kieran Mansley - * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS + - IP and TCP headers - - 2007-03-21 Kieran Mansley - * Fix all uses of pbuf_header to check the return value. In some - cases just assert if it fails as I'm not sure how to fix them, but - this is no worse than before when they would carry on regardless - of the failure. - - 2007-03-21 Kieran Mansley - * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and - comment out missing header include in icmp.c - - 2007-03-20 Frédéric Bernon - * memp.h, stats.c: Fix stats_display function where memp_names table wasn't - synchronized with memp.h. - - 2007-03-20 Frédéric Bernon - * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input, - tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with - network interfaces. Also fix a compiler warning. - - 2007-03-20 Kieran Mansley - * udp.c: Only try and use pbuf_header() to make space for headers if - not a ROM or REF pbuf. - - 2007-03-19 Frédéric Bernon - * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg() - and api_msg_post(). - - 2007-03-19 Frédéric Bernon - * Remove unimplemented "memp_realloc" function from memp.h. - - 2007-03-11 Simon Goldschmidt - * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused - memory corruption. - - 2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov) - * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251 - (missing `const' qualifier in socket functions), to get more compatible to - standard POSIX sockets. - - 2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov) - * sockets.c: Add asserts inside bind, connect and sendto to check input - parameters. Remove excessive set_errno() calls after get_socket(), because - errno is set inside of get_socket(). Move last sock_set_errno() inside - lwip_close. - - 2007-03-09 Simon Goldschmidt - * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory - was allocated too small. - - 2007-03-06 Simon Goldschmidt - * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect - the stack from concurrent access. - - 2007-03-06 Frédéric Bernon, Dmitry Potapov - * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy - call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input(). - - 2007-03-06 Simon Goldschmidt - * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files - if IP_FRAG == 0 and IP_REASSEMBLY == 0 - - 2007-03-06 Frédéric Bernon, Simon Goldschmidt - * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration - option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput. - Allow to do ARP processing for incoming packets inside tcpip_thread - (protecting ARP layer against concurrent access). You can also disable - old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0. - Older ports have to use tcpip_ethinput. - - 2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov) - * err.h, err.c: fixed compiler warning "initialization dircards qualifiers - from pointer target type" - - 2007-03-05 Frédéric Bernon - * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES, - ETHARP_TRUST_IP_MAC, review SO_REUSE) - - 2007-03-04 Frédéric Bernon - * api_msg.c: Remove some compiler warnings : parameter "pcb" was never - referenced. - - 2007-03-04 Frédéric Bernon - * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from - Dmitry Potapov). - The api_msg struct stay on the stack (not moved to netconn struct). - - 2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov) - * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if - SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available) - Also fixed cast warning in pbuf_alloc() - - 2007-03-04 Simon Goldschmidt - * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt - existing pbuf chain when enqueuing multiple pbufs to a pending ARP request - - 2007-03-03 Frédéric Bernon - * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;" - It is static, and never used in udp.c except udp_init(). - - 2007-03-02 Simon Goldschmidt - * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from - tcpip_thread() to tcpip_init(). This way, raw API connections can be - initialized before tcpip_thread is running (e.g. before OS is started) - - 2007-03-02 Frédéric Bernon - * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call - interval. - - 2007-02-28 Kieran Mansley - * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved - outside the region of the pbuf by pbuf_header() - - 2007-02-28 Kieran Mansley - * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero - when supplied timeout is also non-zero - -(STABLE-1.2.0) - - 2006-12-05 Leon Woestenberg - * CHANGELOG: Mention STABLE-1.2.0 release. - - ++ New features: - - 2006-12-01 Christiaan Simons - * mem.h, opt.h: Added MEM_LIBC_MALLOC option. - Note this is a workaround. Currently I have no other options left. - - 2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour) - * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define - to include/lwip/opt.h. - * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL. - Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h. - * opt.h: Add above new options. - - 2006-08-18 Christiaan Simons - * tcp_{in,out}.c: added SNMP counters. - * ipv4/ip.c: added SNMP counters. - * ipv4/ip_frag.c: added SNMP counters. - - 2006-08-08 Christiaan Simons - * etharp.{c,h}: added etharp_find_addr() to read - (stable) ethernet/IP address pair from ARP table - - 2006-07-14 Christiaan Simons - * mib_structs.c: added - * include/lwip/snmp_structs.h: added - * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct - - 2006-07-06 Christiaan Simons - * snmp/asn1_{enc,dec}.c added - * snmp/mib2.c added - * snmp/msg_{in,out}.c added - * include/lwip/snmp_asn1.h added - * include/lwip/snmp_msg.h added - * doc/snmp_agent.txt added - - 2006-03-29 Christiaan Simons - * inet.c, inet.h: Added platform byteswap support. - Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and - optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros. - - ++ Bug fixes: - - 2006-11-30 Christiaan Simons - * dhcp.c: Fixed false triggers of request_timeout. - - 2006-11-28 Christiaan Simons - * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags. - - 2006-10-11 Christiaan Simons - * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h: - Partially accepted patch #5449 for ANSI C compatibility / build fixes. - * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol - identifier from 170 to 136 (bug #17574). - - 2006-10-10 Christiaan Simons - * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice. - - 2006-08-17 Christiaan Simons - * udp.c: Fixed bug #17200, added check for broadcast - destinations for PCBs bound to a unicast address. - - 2006-08-07 Christiaan Simons - * api_msg.c: Flushing TCP output in do_close() (bug #15926). - - 2006-06-27 Christiaan Simons - * api_msg.c: Applied patch for cold case (bug #11135). - In accept_function() ensure newconn->callback is always initialized. - - 2006-06-15 Christiaan Simons - * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748), - facilitate printing of mem_size_t and u16_t statistics. - - 2006-06-14 Christiaan Simons - * api_msg.c: Applied patch #5146 to handle allocation failures - in accept() by Kevin Lawson. - - 2006-05-26 Christiaan Simons - * api_lib.c: Removed conn->sem creation and destruction - from netconn_write() and added sys_sem_new to netconn_new_*. - -(STABLE-1_1_1) - - 2006-03-03 Christiaan Simons - * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap - access and added pbuf_alloc() return value checks. - - 2006-01-01 Leon Woestenberg - * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is - now handled by the checksum routine properly. - - 2006-02-27 Leon Woestenberg - * pbuf.c: Fix alignment; pbuf_init() would not work unless - pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) - - 2005-12-20 Leon Woestenberg - * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch - submitted by Mitrani Hiroshi. - - 2005-12-15 Christiaan Simons - * inet.c: Disabled the added summing routine to preserve code space. - - 2005-12-14 Leon Woestenberg - * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. - Added Curt McDowell's optimized checksumming routine for future - inclusion. Need to create test case for unaliged, aligned, odd, - even length combination of cases on various endianess machines. - - 2005-12-09 Christiaan Simons - * inet.c: Rewrote standard checksum routine in proper portable C. - - 2005-11-25 Christiaan Simons - * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. - * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, - u32_t, s32_t typedefs. This solves most debug word-length assumes. - - 2005-07-17 Leon Woestenberg - * inet.c: Fixed unaligned 16-bit access in the standard checksum - routine by Peter Jolasson. - * slipif.c: Fixed implementation assumption of single-pbuf datagrams. - - 2005-02-04 Leon Woestenberg - * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. - * tcp_{out|in}.c: Applied patch fixing unaligned access. - - 2005-01-04 Leon Woestenberg - * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. - - 2005-01-03 Leon Woestenberg - * udp.c: UDP pcb->recv() was called even when it was NULL. - -(STABLE-1_1_0) - - 2004-12-28 Leon Woestenberg - * etharp.*: Disabled multiple packets on the ARP queue. - This clashes with TCP queueing. - - 2004-11-28 Leon Woestenberg - * etharp.*: Fixed race condition from ARP request to ARP timeout. - Halved the ARP period, doubled the period counts. - ETHARP_MAX_PENDING now should be at least 2. This prevents - the counter from reaching 0 right away (which would allow - too little time for ARP responses to be received). - - 2004-11-25 Leon Woestenberg - * dhcp.c: Decline messages were not multicast but unicast. - * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. - Do not try hard to insert arbitrary packet's source address, - etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. - etharp_query() now always DOES call ETHARP_TRY_HARD so that users - querying an address will see it appear in the cache (DHCP could - suffer from this when a server invalidly gave an in-use address.) - * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are - comparing network addresses (identifiers), not the network masks - themselves. - * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given - IP address actually belongs to the network of the given interface. - - 2004-11-24 Kieran Mansley - * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. - -(STABLE-1_1_0-RC1) - - 2004-10-16 Kieran Mansley - * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, - even if one is already pending, if the rcv_wnd is above a threshold - (currently TCP_WND/2). This avoids waiting for a timer to expire to send a - delayed ACK in order to open the window if the stack is only receiving data. - - 2004-09-12 Kieran Mansley - * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. - - 2004-08-20 Tony Mountifield - * etharp.c: Make sure the first pbuf queued on an ARP entry - is properly ref counted. - - 2004-07-27 Tony Mountifield - * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler - warnings about comparison. - * pbuf.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. Closed an unclosed comment. - * tcp.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. - * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). - * inet.c: Added a couple of casts to quiet the compiler. - No need to test isascii(c) before isdigit(c) or isxdigit(c). - - 2004-07-22 Tony Mountifield - * inet.c: Made data types consistent in inet_ntoa(). - Added casts for return values of checksum routines, to pacify compiler. - * ip_frag.c, tcp_out.c, sockets.c, pbuf.c - Small corrections to some debugging statements, to pacify compiler. - - 2004-07-21 Tony Mountifield - * etharp.c: Removed spurious semicolon and added missing end-of-comment. - * ethernetif.c Updated low_level_output() to match prototype for - netif->linkoutput and changed low_level_input() similarly for consistency. - * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype - of raw_recv() in raw.h and so avoid compiler error. - * sockets.c: Added trivial (int) cast to keep compiler happier. - * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. - -(STABLE-1_0_0) - - ++ Changes: - - 2004-07-05 Leon Woestenberg - * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure - your cc.h file defines this either 1 or 0. If non-defined, - defaults to 1. - * .c: Added and includes where used. - * etharp.c: Made some array indices unsigned. - - 2004-06-27 Leon Woestenberg - * netif.*: Added netif_set_up()/down(). - * dhcp.c: Changes to restart program flow. - - 2004-05-07 Leon Woestenberg - * etharp.c: In find_entry(), instead of a list traversal per candidate, do a - single-pass lookup for different candidates. Should exploit locality. - - 2004-04-29 Leon Woestenberg - * tcp*.c: Cleaned up source comment documentation for Doxygen processing. - * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. - * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by - the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. - - ++ Bug fixes: - - 2004-04-27 Leon Woestenberg - * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution - suggested by Timmy Brolin. Fix for 32-bit processors that cannot access - non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix - is to prefix the 14-bit Ethernet headers with two padding bytes. - - 2004-04-23 Leon Woestenberg - * ip_addr.c: Fix in the ip_addr_isbroadcast() check. - * etharp.c: Fixed the case where the packet that initiates the ARP request - is not queued, and gets lost. Fixed the case where the packets destination - address is already known; we now always queue the packet and perform an ARP - request. - -(STABLE-0_7_0) - - ++ Bug fixes: - - * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. - * Fixed TCP bug in dequeueing of FIN from out of order segment queue. - * Fixed two possible NULL references in rare cases. - -(STABLE-0_6_6) - - ++ Bug fixes: - - * Fixed DHCP which did not include the IP address in DECLINE messages. - - ++ Changes: - - * etharp.c has been hauled over a bit. - -(STABLE-0_6_5) - - ++ Bug fixes: - - * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. - * Packets sent from ARP queue had invalid source hardware address. - - ++ Changes: - - * Pass-by ARP requests do now update the cache. - - ++ New features: - - * No longer dependent on ctype.h. - * New socket options. - * Raw IP pcb support. - -(STABLE-0_6_4) - - ++ Bug fixes: - - * Some debug formatters and casts fixed. - * Numereous fixes in PPP. - - ++ Changes: - - * DEBUGF now is LWIP_DEBUGF - * pbuf_dechain() has been re-enabled. - * Mentioned the changed use of CVS branches in README. - -(STABLE-0_6_3) - - ++ Bug fixes: - - * Fixed pool pbuf memory leak in pbuf_alloc(). - Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. - Reported by Savin Zlobec. - - * PBUF_POOL chains had their tot_len field not set for non-first - pbufs. Fixed in pbuf_alloc(). - - ++ New features: - - * Added PPP stack contributed by Marc Boucher - - ++ Changes: - - * Now drops short packets for ICMP/UDP/TCP protocols. More robust. - - * ARP queueuing now queues the latest packet instead of the first. - This is the RFC recommended behaviour, but can be overridden in - lwipopts.h. - -(0.6.2) - - ++ Bugfixes: - - * TCP has been fixed to deal with the new use of the pbuf->ref - counter. - - * DHCP dhcp_inform() crash bug fixed. - - ++ Changes: - - * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed - pbuf_refresh(). This has sped up pbuf pool operations considerably. - Implemented by David Haas. - -(0.6.1) - - ++ New features: - - * The packet buffer implementation has been enhanced to support - zero-copy and copy-on-demand for packet buffers which have their - payloads in application-managed memory. - Implemented by David Haas. - - Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy - if an outgoing packet can be directly sent on the link, or perform - a copy-on-demand when necessary. - - The application can safely assume the packet is sent, and the RAM - is available to the application directly after calling udp_send() - or similar function. - - ++ Bugfixes: - - * ARP_QUEUEING should now correctly work for all cases, including - PBUF_REF. - Implemented by Leon Woestenberg. - - ++ Changes: - - * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer - to a '0.0.0.0' IP address. - - * The packet buffer implementation is changed. The pbuf->ref counter - meaning has changed, and several pbuf functions have been - adapted accordingly. - - * netif drivers have to be changed to set the hardware address length field - that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). - See the contrib/ports/c16x cs8900 driver as a driver example. - - * netif's have a dhcp field that must be initialized to NULL by the driver. - See the contrib/ports/c16x cs8900 driver as a driver example. - -(0.5.x) This file has been unmaintained up to 0.6.1. All changes are - logged in CVS but have not been explained here. - -(0.5.3) Changes since version 0.5.2 - - ++ Bugfixes: - - * memp_malloc(MEMP_API_MSG) could fail with multiple application - threads because it wasn't protected by semaphores. - - ++ Other changes: - - * struct ip_addr now packed. - - * The name of the time variable in arp.c has been changed to ctime - to avoid conflicts with the time() function. - -(0.5.2) Changes since version 0.5.1 - - ++ New features: - - * A new TCP function, tcp_tmr(), now handles both TCP timers. - - ++ Bugfixes: - - * A bug in tcp_parseopt() could cause the stack to hang because of a - malformed TCP option. - - * The address of new connections in the accept() function in the BSD - socket library was not handled correctly. - - * pbuf_dechain() did not update the ->tot_len field of the tail. - - * Aborted TCP connections were not handled correctly in all - situations. - - ++ Other changes: - - * All protocol header structs are now packed. - - * The ->len field in the tcp_seg structure now counts the actual - amount of data, and does not add one for SYN and FIN segments. - -(0.5.1) Changes since version 0.5.0 - - ++ New features: - - * Possible to run as a user process under Linux. - - * Preliminary support for cross platform packed structs. - - * ARP timer now implemented. - - ++ Bugfixes: - - * TCP output queue length was badly initialized when opening - connections. - - * TCP delayed ACKs were not sent correctly. - - * Explicit initialization of BSS segment variables. - - * read() in BSD socket library could drop data. - - * Problems with memory alignment. - - * Situations when all TCP buffers were used could lead to - starvation. - - * TCP MSS option wasn't parsed correctly. - - * Problems with UDP checksum calculation. - - * IP multicast address tests had endianess problems. - - * ARP requests had wrong destination hardware address. - - ++ Other changes: - - * struct eth_addr changed from u16_t[3] array to u8_t[6]. - - * A ->linkoutput() member was added to struct netif. - - * TCP and UDP ->dest_* struct members where changed to ->remote_*. - - * ntoh* macros are now null definitions for big endian CPUs. - -(0.5.0) Changes since version 0.4.2 - - ++ New features: - - * Redesigned operating system emulation layer to make porting easier. - - * Better control over TCP output buffers. - - * Documenation added. - - ++ Bugfixes: - - * Locking issues in buffer management. - - * Bugfixes in the sequential API. - - * IP forwarding could cause memory leakage. This has been fixed. - - ++ Other changes: - - * Directory structure somewhat changed; the core/ tree has been - collapsed. - -(0.4.2) Changes since version 0.4.1 - - ++ New features: - - * Experimental ARP implementation added. - - * Skeleton Ethernet driver added. - - * Experimental BSD socket API library added. - - ++ Bugfixes: - - * In very intense situations, memory leakage could occur. This has - been fixed. - - ++ Other changes: - - * Variables named "data" and "code" have been renamed in order to - avoid name conflicts in certain compilers. - - * Variable++ have in appliciable cases been translated to ++variable - since some compilers generate better code in the latter case. - -(0.4.1) Changes since version 0.4 - - ++ New features: - - * TCP: Connection attempts time out earlier than data - transmissions. Nagle algorithm implemented. Push flag set on the - last segment in a burst. - - * UDP: experimental support for UDP-Lite extensions. - - ++ Bugfixes: - - * TCP: out of order segments were in some cases handled incorrectly, - and this has now been fixed. Delayed acknowledgements was broken - in 0.4, has now been fixed. Binding to an address that is in use - now results in an error. Reset connections sometimes hung an - application; this has been fixed. - - * Checksum calculation sometimes failed for chained pbufs with odd - lengths. This has been fixed. - - * API: a lot of bug fixes in the API. The UDP API has been improved - and tested. Error reporting and handling has been - improved. Logical flaws and race conditions for incoming TCP - connections has been found and removed. - - * Memory manager: alignment issues. Reallocating memory sometimes - failed, this has been fixed. - - * Generic library: bcopy was flawed and has been fixed. - - ++ Other changes: - - * API: all datatypes has been changed from generic ones such as - ints, to specified ones such as u16_t. Functions that return - errors now have the correct type (err_t). - - * General: A lot of code cleaned up and debugging code removed. Many - portability issues have been fixed. - - * The license was changed; the advertising clause was removed. - - * C64 port added. - - * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri - Kosunen, Mikael Caleres, and Frits Wilmink for reporting and - fixing bugs! - -(0.4) Changes since version 0.3.1 - - * Memory management has been radically changed; instead of - allocating memory from a shared heap, memory for objects that are - rapidly allocated and deallocated is now kept in pools. Allocation - and deallocation from those memory pools is very fast. The shared - heap is still present but is used less frequently. - - * The memory, memory pool, and packet buffer subsystems now support - 4-, 2-, or 1-byte alignment. - - * "Out of memory" situations are handled in a more robust way. - - * Stack usage has been reduced. - - * Easier configuration of lwIP parameters such as memory usage, - TTLs, statistics gathering, etc. All configuration parameters are - now kept in a single header file "lwipopts.h". - - * The directory structure has been changed slightly so that all - architecture specific files are kept under the src/arch - hierarchy. - - * Error propagation has been improved, both in the protocol modules - and in the API. - - * The code for the RTXC architecture has been implemented, tested - and put to use. - - * Bugs have been found and corrected in the TCP, UDP, IP, API, and - the Internet checksum modules. - - * Bugs related to porting between a 32-bit and a 16-bit architecture - have been found and corrected. - - * The license has been changed slightly to conform more with the - original BSD license, including the advertisement clause. - -(0.3.1) Changes since version 0.3 - - * Fix of a fatal bug in the buffer management. Pbufs with allocated - RAM never returned the RAM when the pbuf was deallocated. - - * TCP congestion control, window updates and retransmissions did not - work correctly. This has now been fixed. - - * Bugfixes in the API. - -(0.3) Changes since version 0.2 - - * New and improved directory structure. All include files are now - kept in a dedicated include/ directory. - - * The API now has proper error handling. A new function, - netconn_err(), now returns an error code for the connection in - case of errors. - - * Improvements in the memory management subsystem. The system now - keeps a pointer to the lowest free memory block. A new function, - mem_malloc2() tries to allocate memory once, and if it fails tries - to free some memory and retry the allocation. - - * Much testing has been done with limited memory - configurations. lwIP now does a better job when overloaded. - - * Some bugfixes and improvements to the buffer (pbuf) subsystem. - - * Many bugfixes in the TCP code: - - - Fixed a bug in tcp_close(). - - - The TCP receive window was incorrectly closed when out of - sequence segments was received. This has been fixed. - - - Connections are now timed-out of the FIN-WAIT-2 state. - - - The initial congestion window could in some cases be too - large. This has been fixed. - - - The retransmission queue could in some cases be screwed up. This - has been fixed. - - - TCP RST flag now handled correctly. - - - Out of sequence data was in some cases never delivered to the - application. This has been fixed. - - - Retransmitted segments now contain the correct acknowledgment - number and advertised window. - - - TCP retransmission timeout backoffs are not correctly computed - (ala BSD). After a number of retransmissions, TCP now gives up - the connection. - - * TCP connections now are kept on three lists, one for active - connections, one for listening connections, and one for - connections that are in TIME-WAIT. This greatly speeds up the fast - timeout processing for sending delayed ACKs. - - * TCP now provides proper feedback to the application when a - connection has been successfully set up. - - * More comments have been added to the code. The code has also been - somewhat cleaned up. - -(0.2) Initial public release. diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/COPYING b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/COPYING deleted file mode 100644 index e23898b5e8feaec5b3d7e5066bab64fd82bf99a6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/COPYING +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/FILES b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/FILES deleted file mode 100644 index e6e09989d9484926ca64e6a626b516f9f52cb3fa..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/FILES +++ /dev/null @@ -1,5 +0,0 @@ -src/ - The source code for the lwIP TCP/IP stack. -doc/ - The documentation for lwIP. -test/ - Some code to test whether the sources do what they should. - -See also the FILES file in each subdirectory. diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/README b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/README deleted file mode 100644 index 0884d27bea5ae306d6b937ef3ab6bef7c5e2a584..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/README +++ /dev/null @@ -1,100 +0,0 @@ -INTRODUCTION - -lwIP is a small independent implementation of the TCP/IP protocol -suite that has been developed by Adam Dunkels at the Computer and -Networks Architectures (CNA) lab at the Swedish Institute of Computer -Science (SICS). - -The focus of the lwIP TCP/IP implementation is to reduce the RAM usage -while still having a full scale TCP. This making lwIP suitable for use -in embedded systems with tens of kilobytes of free RAM and room for -around 40 kilobytes of code ROM. - - -FEATURES - - * IP (Internet Protocol, IPv4 and IPv6) including packet forwarding over - multiple network interfaces - * ICMP (Internet Control Message Protocol) for network maintenance and debugging - * IGMP (Internet Group Management Protocol) for multicast traffic management - * MLD (Multicast listener discovery for IPv6). Aims to be compliant with - RFC 2710. No support for MLDv2 - * ND (Neighbor discovery and stateless address autoconfiguration for IPv6). - Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 - (Address autoconfiguration) - * UDP (User Datagram Protocol) including experimental UDP-lite extensions - * TCP (Transmission Control Protocol) with congestion control, RTT estimation - and fast recovery/fast retransmit - * raw/native API for enhanced performance - * Optional Berkeley-like socket API - * DNS (Domain names resolver) - - -APPLICATIONS - - * HTTP server with SSI and CGI - * SNMPv2c agent with MIB compiler (Simple Network Management Protocol) - * SNTP (Simple network time protocol) - * NetBIOS name service responder - * MDNS (Multicast DNS) responder - * iPerf server implementation - - -LICENSE - -lwIP is freely available under a BSD license. - - -DEVELOPMENT - -lwIP has grown into an excellent TCP/IP stack for embedded devices, -and developers using the stack often submit bug fixes, improvements, -and additions to the stack to further increase its usefulness. - -Development of lwIP is hosted on Savannah, a central point for -software development, maintenance and distribution. Everyone can -help improve lwIP by use of Savannah's interface, Git and the -mailing list. A core team of developers will commit changes to the -Git source tree. - -The lwIP TCP/IP stack is maintained in the 'lwip' Git module and -contributions (such as platform ports) are in the 'contrib' Git module. - -See doc/savannah.txt for details on Git server access for users and -developers. - -The current Git trees are web-browsable: - http://git.savannah.gnu.org/cgit/lwip.git - http://git.savannah.gnu.org/cgit/lwip/lwip-contrib.git - -Submit patches and bugs via the lwIP project page: - http://savannah.nongnu.org/projects/lwip/ - -Continuous integration builds (GCC, clang): - https://travis-ci.org/yarrick/lwip-merged - - -DOCUMENTATION - -Self documentation of the source code is regularly extracted from the current -Git sources and is available from this web page: - http://www.nongnu.org/lwip/ - -There is now a constantly growing wiki about lwIP at - http://lwip.wikia.com/wiki/LwIP_Wiki - -Also, there are mailing lists you can subscribe at - http://savannah.nongnu.org/mail/?group=lwip -plus searchable archives: - http://lists.nongnu.org/archive/html/lwip-users/ - http://lists.nongnu.org/archive/html/lwip-devel/ - -lwIP was originally written by Adam Dunkels: - http://dunkels.com/adam/ - -Reading Adam's papers, the files in docs/, browsing the source code -documentation and browsing the mailing list archives is a good way to -become familiar with the design of lwIP. - -Adam Dunkels -Leon Woestenberg diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/UPGRADING b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/UPGRADING deleted file mode 100644 index 3a984c9270a2cedebdd7ab32589935795701b644..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/UPGRADING +++ /dev/null @@ -1,235 +0,0 @@ -This file lists major changes between release versions that require -ports or applications to be changed. Use it to update a port or an -application written for an older version of lwIP to correctly work -with newer versions. - - -(git master) - - * [Enter new changes just after this line - do not remove this line] - -(2.0.1) - - ++ Application changes: - - * UDP does NOT receive multicast traffic from ALL netifs on an UDP PCB bound to a specific - netif any more. Users need to bind to IP_ADDR_ANY to receive multicast traffic and compare - ip_current_netif() to the desired netif for every packet. - See bug #49662 for an explanation. - -(2.0.0) - - ++ Application changes: - - * Changed netif "up" flag handling to be an administrative flag (as opposed to the previous meaning of - "ip4-address-valid", a netif will now not be used for transmission if not up) -> even a DHCP netif - has to be set "up" before starting the DHCP client - * Added IPv6 support (dual-stack or IPv4/IPv6 only) - * Changed ip_addr_t to be a union in dual-stack mode (use ip4_addr_t where referring to IPv4 only). - * Major rewrite of SNMP (added MIB parser that creates code stubs for custom MIBs); - supports SNMPv2c (experimental v3 support) - * Moved some core applications from contrib repository to src/apps (and include/lwip/apps) - - +++ Raw API: - * Changed TCP listen backlog: removed tcp_accepted(), added the function pair tcp_backlog_delayed()/ - tcp_backlog_accepted() to explicitly delay backlog handling on a connection pcb - - +++ Socket API: - * Added an implementation for posix sendmsg() - * Added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram - - ++ Port changes - - +++ new files: - * MANY new and moved files! - * Added src/Filelists.mk for use in Makefile projects - * Continued moving stack-internal parts from abc.h to abc_priv.h in sub-folder "priv" - to let abc.h only contain the actual application programmer's API - - +++ sys layer: - * Made LWIP_TCPIP_CORE_LOCKING==1 the default as it usually performs better than - the traditional message passing (although with LWIP_COMPAT_MUTEX you are still - open to priority inversion, so this is not recommended any more) - * Added LWIP_NETCONN_SEM_PER_THREAD to use one "op_completed" semaphore per thread - instead of using one per netconn (these semaphores are used even with core locking - enabled as some longer lasting functions like big writes still need to delay) - * Added generalized abstraction for itoa(), strnicmp(), stricmp() and strnstr() - in def.h (to be overridden in cc.h) instead of config - options for netbiosns, httpd, dns, etc. ... - * New abstraction for hton* and ntoh* functions in def.h. - To override them, use the following in cc.h: - #define lwip_htons(x) - #define lwip_htonl(x) - - +++ new options: - * TODO - - +++ new pools: - * Added LWIP_MEMPOOL_* (declare/init/alloc/free) to declare private memp pools - that share memp.c code but do not have to be made global via lwippools.h - * Added pools for IPv6, MPU_COMPATIBLE, dns-api, netif-api, etc. - * added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item - is now available - - * Signature of LWIP_HOOK_VLAN_SET macro was changed - - * LWIP_DECLARE_MEMORY_ALIGNED() may be used to declare aligned memory buffers (mem/memp) - or to move buffers to dedicated memory using compiler attributes - - * Standard C headers are used to define sized types and printf formatters - (disable by setting LWIP_NO_STDINT_H=1 or LWIP_NO_INTTYPES_H=1 if your compiler - does not support these) - - - ++ Major bugfixes/improvements - - * Added IPv6 support (dual-stack or IPv4/IPv6 only) - * Major rewrite of PPP (incl. keep-up with apache pppd) - see doc/ppp.txt for an upgrading how-to - * Major rewrite of SNMP (incl. MIB parser) - * Fixed timing issues that might have lead to losing a DHCP lease - * Made rx processing path more robust against crafted errors - * TCP window scaling support - * modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads) - * made DNS client more robust - * support PBUF_REF for RX packets - * LWIP_NETCONN_FULLDUPLEX allows netconn/sockets to be used for reading/writing from separate - threads each (needs LWIP_NETCONN_SEM_PER_THREAD) - * Moved and reordered stats (mainly memp/mib2) - -(1.4.0) - - ++ Application changes: - - * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for - compatibility to old applications, but will be removed in the future). - - * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() - - +++ Raw API: - * Changed the semantics of tcp_close() (since it was rather a - shutdown before): Now the application does *NOT* get any calls to the recv - callback (aside from NULL/closed) after calling tcp_close() - - * When calling tcp_abort() from a raw API TCP callback function, - make sure you return ERR_ABRT to prevent accessing unallocated memory. - (ERR_ABRT now means the applicaiton has called tcp_abort!) - - +++ Netconn API: - * Changed netconn_receive() and netconn_accept() to return - err_t, not a pointer to new data/netconn. - - +++ Socket API: - * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they - now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT. - - * Added a minimal version of posix fctl() to have a - standardised way to set O_NONBLOCK for nonblocking sockets. - - +++ all APIs: - * correctly implemented SO(F)_REUSEADDR - - ++ Port changes - - +++ new files: - - * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h: - - * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains - the actual application programmer's API - - * Separated timer implementation from sys.h/.c, moved to timers.h/.c; - Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you - still want to use your own timer implementation for NO_SYS==0 (as before). - - +++ sys layer: - - * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/ - sys_sem_t; - - * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t; - - * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use - binary semaphores instead of mutexes - as before) - - +++ new options: - - * Don't waste memory when chaining segments, added option TCP_OVERSIZE to - prevent creating many small pbufs when calling tcp_write with many small - blocks of data. Instead, pbufs are allocated larger than needed and the - space is used for later calls to tcp_write. - - * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs - in tcp_write/udp_send. - - * Added an additional option LWIP_ETHERNET to support ethernet without ARP - (necessary for pure PPPoE) - - * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may - be used to place these pools into user-defined memory by using external - declaration. - - * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT - - +++ new pools: - - * Netdb uses a memp pool for allocating memory when getaddrinfo() is called, - so MEMP_NUM_NETDB has to be set accordingly. - - * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so - MEMP_NUM_LOCALHOSTLIST has to be set accordingly. - - * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have - to be set accordingly. - - * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES - has to be set accordingly - - * Integrated loopif into netif.c - loopif does not have to be created by the - port any more, just define LWIP_HAVE_LOOPIF to 1. - - * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined - in cc.h, e.g. used by igmp) - - * Added printf-formatter X8_F to printf u8_t as hex - - * The heap now may be moved to user-defined memory by defining - LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address - - * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work - with user-allocated structs instead of calling mem_malloc - - * Added const char* name to mem- and memp-stats for easier debugging. - - * Calculate the TCP/UDP checksum while copying to only fetch data once: - Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum - - * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to - more than one pcb. - - * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned - off any more, if this is set to 0, only one packet (the most recent one) is - queued (like demanded by RFC 1122). - - - ++ Major bugfixes/improvements - - * Implemented tcp_shutdown() to only shut down one end of a connection - * Implemented shutdown() at socket- and netconn-level - * Added errorset support to select() + improved select speed overhead - * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x) - * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1 - * Use macros defined in ip_addr.h to work with IP addresses - * Implemented many nonblocking socket/netconn functions - * Fixed ARP input processing: only add a new entry if a request was directed as us - * mem_realloc() to mem_trim() to prevent confusion with realloc() - * Some improvements for AutoIP (don't route/forward link-local addresses, don't break - existing connections when assigning a routable address) - * Correctly handle remote side overrunning our rcv_wnd in ooseq case - * Removed packing from ip_addr_t, the packed version is now only used in protocol headers - * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0 - * Added support for static ARP table entries - -(STABLE-1.3.2) - - * initial version of this file diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/cc.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/cc.h deleted file mode 100644 index 611e360945d90e1beb6be80d67786e9eaaf917c6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/cc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * cc.h - Architecture environment, some compiler specific, some - * environment specific (probably should move env stuff - * to sys_arch.h.) - * - * Typedefs for the types used by lwip - - * u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t - * - * Compiler hints for packing lwip's structures - - * PACK_STRUCT_FIELD(x) - * PACK_STRUCT_STRUCT - * PACK_STRUCT_BEGIN - * PACK_STRUCT_END - * - * Platform specific diagnostic output - - * LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. - * LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. - * Portability defines for printf formatters: - * U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F - * - * "lightweight" synchronization mechanisms - - * SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable. - * SYS_ARCH_PROTECT(x) - enter protection mode. - * SYS_ARCH_UNPROTECT(x) - leave protection mode. - * - * If the compiler does not provide memset() this file must include a - * definition of it, or include a file which defines it. - * - * This file must either include a system-local which defines - * the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO - * to make lwip/arch.h define the codes which are used throughout. - */ - -#ifndef __CC_H__ -#define __CC_H__ - -#include "typedef.h" -#include "uart_pub.h" - - -/* - * Typedefs for the types used by lwip - - * u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t - */ -typedef unsigned char u8_t; /* Unsigned 8 bit quantity */ -typedef signed char s8_t; /* Signed 8 bit quantity */ -typedef unsigned short u16_t; /* Unsigned 16 bit quantity */ -typedef signed short s16_t; /* Signed 16 bit quantity */ -typedef unsigned long u32_t; /* Unsigned 32 bit quantity */ -typedef signed long s32_t; /* Signed 32 bit quantity */ -//typedef unsigned long mem_ptr_t; /* Unsigned 32 bit quantity */ -typedef int intptr_t; -typedef unsigned int uintptr_t; -typedef int sys_prot_t; - - - -#if defined(__GNUC__) - #define PACK_STRUCT_BEGIN - #define PACK_STRUCT_STRUCT __attribute__((packed)) - #define PACK_STRUCT_FIELD(x) x -#elif defined(__ICCARM__) - #define PACK_STRUCT_BEGIN __packed - #define PACK_STRUCT_STRUCT - #define PACK_STRUCT_FIELD(x) x -#else - #define PACK_STRUCT_BEGIN - #define PACK_STRUCT_STRUCT - #define PACK_STRUCT_FIELD(x) x -#endif - - -/* - * Platform specific diagnostic output - - * LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. - * LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. - * Portability defines for printf formatters: - * U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F - */ -#ifndef LWIP_PLATFORM_ASSERT -#define LWIP_PLATFORM_ASSERT(x) \ - do \ - { fatal_prf("Assertion \"%s\" failed at line %d in %s\n", x, __LINE__, __FILE__); \ - } while(0) -#endif - -#ifndef LWIP_PLATFORM_DIAG -#define LWIP_PLATFORM_DIAG(x) do {fatal_prf x ;} while(0) -#endif - -#define U16_F "4d" -#define S16_F "4d" -#define X16_F "4x" -#define U32_F "8ld" -#define S32_F "8ld" -#define X32_F "8lx" - -/* - * unknow defination - */ -// cup byte order -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif - -#define LWIP_RAND() ((uint32_t)bk_rand()) -#endif -// eof - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/sys_arch.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/sys_arch.h deleted file mode 100644 index c938e83234b1d8ac327572077545020f13629671..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/arch/sys_arch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __SYS_RTXC_H__ -#define __SYS_RTXC_H__ - -#include "sys_rtos.h" - -#define SYS_MBOX_NULL (xQueueHandle)0 -#define SYS_SEM_NULL (xSemaphoreHandle)0 -#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE - -typedef xSemaphoreHandle sys_sem_t; -typedef xQueueHandle sys_mbox_t; -typedef xTaskHandle sys_thread_t; - -typedef struct _sys_arch_state_t -{ - // Task creation data. - char cTaskName[configMAX_TASK_NAME_LEN]; - unsigned short nStackDepth; - unsigned short nTaskCount; -} sys_arch_state_t; - -/* Message queue constants. */ -#define archMESG_QUEUE_LENGTH ( 32 ) -#endif /* __SYS_RTXC_H__ */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.c deleted file mode 100644 index 7a8bfe0488a7b838d6d46d2acce63948570329e2..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.c +++ /dev/null @@ -1,335 +0,0 @@ -/** - * @file - * Ethernet Interface Skeleton - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. - */ - -#include "include.h" - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include "ethernetif.h" - -#include -#include - -#include "netif/etharp.h" - -#include "lwip_netif_address.h" - -#include "sa_station.h" - -#include "drv_model_pub.h" -#include "mem_pub.h" -#include "common.h" - -#include "hostapd_cfg.h" - -#include "sk_intf.h" -#include "rw_pub.h" -#include "rtos_pub.h" -#include "param_config.h" - -/* Define those to better describe your network interface. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -#include "uart_pub.h" - -#define ETH_INTF_DEBUG -#ifdef ETH_INTF_DEBUG -#define ETH_INTF_PRT warning_prf -#define ETH_INTF_WARN warning_prf -#define ETH_INTF_FATAL fatal_prf -#else -#define ETH_INTF_PRT null_prf -#define ETH_INTF_WARN null_prf -#define ETH_INTF_FATAL null_prf -#endif - -extern int bmsg_tx_sender(struct pbuf *p, uint32_t vif_idx); - -/* Forward declarations. */ -void ethernetif_input(int iface, struct pbuf *p); - -/** - * In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ - -const char wlan_name[][6] = -{ - "wlan0\0", - "wlan1\0", - "wlan2\0", - "wlan3\0", -}; -static void low_level_init(struct netif *netif) -{ - VIF_INF_PTR vif_entry = (VIF_INF_PTR)(netif->state); - u8 *macptr = (u8*)&vif_entry->mac_addr; - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = (char*)&wlan_name[vif_entry->index]; -#endif /* LWIP_NETIF_HOSTNAME */ - - //wifi_get_mac_address((char *)wireless_mac, type); - - /* set MAC hardware address length */ - ETH_INTF_PRT("enter low level!\r\n"); - ETH_INTF_PRT("mac %2x:%2x:%2x:%2x:%2x:%2x\r\n", macptr[0], macptr[1], macptr[2], - macptr[3], macptr[4], macptr[5]); - - netif->hwaddr_len = ETHARP_HWADDR_LEN; - os_memcpy(netif->hwaddr, macptr, ETHARP_HWADDR_LEN); - /* maximum transfer unit */ - netif->mtu = 1500; - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - ETH_INTF_PRT("leave low level!\r\n"); -} - -/** - * This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become availale since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ - int ret; - err_t err = ERR_OK; - uint8_t vif_idx = rwm_mgmt_get_netif2vif(netif); - - //os_printf("output:%x\r\n", p); - ret = bmsg_tx_sender(p, (uint32_t)vif_idx); - if(0 != ret) - { - err = ERR_TIMEOUT; - } - - return err; -} - -/** - * This function should be called when a packet is ready to be read - * from the interface. It uses the function low_level_input() that - * should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -void -ethernetif_input(int iface, struct pbuf *p) -{ - struct eth_hdr *ethhdr; - struct netif *netif; - - if (p->len <= SIZEOF_ETH_HDR) { - pbuf_free(p); - return; - } - - netif = rwm_mgmt_get_vif2netif((uint8_t)iface); - if(!netif) { - //ETH_INTF_PRT("ethernetif_input no netif found %d\r\n", iface); - pbuf_free(p); - p = NULL; - return; - } - - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - - switch (htons(ethhdr->type)) - { - /* IP or ARP packet? */ - case ETHTYPE_IP: - case ETHTYPE_ARP: -#if PPPOE_SUPPORT - /* PPPoE packet? */ - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: -#endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif) != ERR_OK) // ethernet_input - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\r\n")); - pbuf_free(p); - p = NULL; - } - break; - - case ETHTYPE_EAPOL: - ke_l2_packet_tx(p->payload, p->len, iface); - pbuf_free(p); - p = NULL; - break; - - default: - pbuf_free(p); - p = NULL; - break; - } - -} - -/** - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t -ethernetif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000); - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -/** - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netifapi_netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t lwip_netif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000); - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; -#ifdef CONFIG_IPV6 - netif->output_ip6 = ethip6_output; -#endif - - /* initialize the hardware */ - low_level_init(netif); - return ERR_OK; -} - -err_t lwip_netif_uap_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - - //netif->state = NULL; - netif->name[0] = 'u'; - netif->name[1] = 'a'; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -// eof diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.h deleted file mode 100644 index 95e287b024b1276bfb117b65e9d4341fed7b9627..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/ethernetif.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ETHERNETIF_H__ -#define __ETHERNETIF_H__ - - -#include "lwip/err.h" -#include "lwip/netif.h" - - -void ethernetif_recv(struct netif *netif, int total_len); -err_t ethernetif_init(struct netif *netif); - - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_intf.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_intf.h deleted file mode 100644 index 803fbd4e601d3040d2395cdbe600d0ba9e15d173..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_intf.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __LWIP_INTF_H__ -#define __LWIP_INTF_H__ - -#define LWIP_INTF_DEBUG -#ifdef LWIP_INTF_DEBUG -#define LWIP_INTF_PRT warning_prf -#define LWIP_INTF_WARN warning_prf -#define LWIP_INTF_FATAL fatal_prf -#else -#define LWIP_INTF_PRT null_prf -#define LWIP_INTF_WARN null_prf -#define LWIP_INTF_FATAL null_prf -#endif - -#endif -// eof - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_netif_address.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_netif_address.h deleted file mode 100644 index d92ac24751f7a0fa41362a799951bc57da794da9..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwip_netif_address.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _MXCHIP_NETIF_ADDR_H_ -#define _MXCHIP_NETIF_ADDR_H_ - -/** MLAN BSS type */ -typedef enum _wifi_interface_type -{ - WIFI_INTERFACE_TYPE_STA = 0, - WIFI_INTERFACE_TYPE_UAP = 1, - - WIFI_INTERFACE_TYPE_ANY = 0xff, -} wifi_interface_type; - -#define ADDR_TYPE_STATIC 1 -#define ADDR_TYPE_DHCP 0 - -/** This data structure represents an IPv4 address */ -struct ipv4_config { - /** DHCP_Disable DHCP_Client DHCP_Server */ - unsigned addr_type; - /** The system's IP address in network order. */ - unsigned address; - /** The system's default gateway in network order. */ - unsigned gw; - /** The system's subnet mask in network order. */ - unsigned netmask; - /** The system's primary dns server in network order. */ - unsigned dns1; - /** The system's secondary dns server in network order. */ - unsigned dns2; -}; - -/** Network IP configuration. - * - * This data structure represents the network IP configuration - * for IPv4 as well as IPv6 addresses - */ -struct wlan_ip_config { -#ifdef CONFIG_IPV6 - /** The network IPv6 address configuration that should be - * associated with this interface. */ - struct ipv6_config ipv6[MAX_IPV6_ADDRESSES]; -#endif - /** The network IPv4 address configuration that should be - * associated with this interface. */ - struct ipv4_config ipv4; -}; - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwipopts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwipopts.h deleted file mode 100644 index be8cee5f6fe753389dfc6e58d2a90806c9f64582..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/lwipopts.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIPOPTS_H__ -#define __LWIPOPTS_H__ - -#include "sys_config.h" - -/** - * Loopback demo related options. - */ -#define LWIP_NETIF_LOOPBACK 1 -#define LWIP_HAVE_LOOPIF 1 -#define LWIP_NETIF_LOOPBACK_MULTITHREADING 1 -#define LWIP_LOOPBACK_MAX_PBUFS 8 - -#define TCPIP_THREAD_NAME "tcp/ip" -#define TCPIP_THREAD_STACKSIZE 512 -#define TCPIP_THREAD_PRIO 7 - -#define DEFAULT_THREAD_STACKSIZE 200 -#define DEFAULT_THREAD_PRIO 1 - -/* Disable lwIP asserts */ -#define LWIP_NOASSERT 1 - -#define LWIP_DEBUG 0 -#define LWIP_DEBUG_TRACE 0 -#define SOCKETS_DEBUG LWIP_DBG_OFF -#define IP_DEBUG LWIP_DBG_OFF -#define ETHARP_DEBUG LWIP_DBG_OFF -#define NETIF_DEBUG LWIP_DBG_OFF -#define PBUF_DEBUG LWIP_DBG_OFF -#define MEMP_DEBUG LWIP_DBG_OFF -#define API_LIB_DEBUG LWIP_DBG_OFF -#define API_MSG_DEBUG LWIP_DBG_OFF -#define ICMP_DEBUG LWIP_DBG_OFF -#define IGMP_DEBUG LWIP_DBG_OFF -#define INET_DEBUG LWIP_DBG_OFF -#define IP_REASS_DEBUG LWIP_DBG_OFF -#define RAW_DEBUG LWIP_DBG_OFF -#define MEM_DEBUG LWIP_DBG_OFF -#define SYS_DEBUG LWIP_DBG_OFF -#define TCP_DEBUG LWIP_DBG_OFF -#define TCP_INPUT_DEBUG LWIP_DBG_OFF -#define TCP_FR_DEBUG LWIP_DBG_OFF -#define TCP_RTO_DEBUG LWIP_DBG_OFF -#define TCP_CWND_DEBUG LWIP_DBG_OFF -#define TCP_WND_DEBUG LWIP_DBG_OFF -#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF -#define TCP_RST_DEBUG LWIP_DBG_OFF -#define TCP_QLEN_DEBUG LWIP_DBG_OFF -#define UDP_DEBUG LWIP_DBG_OFF -#define TCPIP_DEBUG LWIP_DBG_OFF -#define PPP_DEBUG LWIP_DBG_OFF -#define SLIP_DEBUG LWIP_DBG_OFF -#define DHCP_DEBUG LWIP_DBG_OFF -#define AUTOIP_DEBUG LWIP_DBG_OFF -#define SNMP_MSG_DEBUG LWIP_DBG_OFF -#define SNMP_MIB_DEBUG LWIP_DBG_OFF -#define DNS_DEBUG LWIP_DBG_OFF - -//#define LWIP_COMPAT_MUTEX 1 -/** - * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain - * critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#define SYS_LIGHTWEIGHT_PROT 1 - -/* - ------------------------------------ - ---------- Memory options ---------- - ------------------------------------ -*/ - -/** - * MEM_ALIGNMENT: should be set to the alignment of the CPU - * 4 byte alignment -> #define MEM_ALIGNMENT 4 - * 2 byte alignment -> #define MEM_ALIGNMENT 2 - */ -#define MEM_ALIGNMENT 4 - -#define MAX_SOCKETS_TCP 12 -#define MAX_LISTENING_SOCKETS_TCP 4 -#define MAX_SOCKETS_UDP 22 -#define TCP_SND_BUF_COUNT 5 - -/* Value of TCP_SND_BUF_COUNT denotes the number of buffers and is set by - * CONFIG option available in the SDK - */ -/* Buffer size needed for TCP: Max. number of TCP sockets * Size of pbuf * - * Max. number of TCP sender buffers per socket - * - * Listening sockets for TCP servers do not require the same amount buffer - * space. Hence do not consider these sockets for memory computation - */ -#define TCP_MEM_SIZE (MAX_SOCKETS_TCP * \ - PBUF_POOL_BUFSIZE * (TCP_SND_BUF/TCP_MSS)) - -/* Buffer size needed for UDP: Max. number of UDP sockets * Size of pbuf - */ -#define UDP_MEM_SIZE (MAX_SOCKETS_UDP * PBUF_POOL_BUFSIZE) - -/** - * MEM_SIZE: the size of the heap memory. If the application will send - * a lot of data that needs to be copied, this should be set high. - */ -#if ((defined(CFG_LWIP_MEM_POLICY))&&(CFG_LWIP_MEM_POLICY == LWIP_REDUCE_THE_PLAN)) -#define MEM_SIZE (16*1024) -#else -#define MEM_SIZE (32*1024) -#endif - - -/* - ------------------------------------------------ - ---------- Internal Memory Pool Sizes ---------- - ------------------------------------------------ -*/ -/** - * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). - * If the application sends a lot of data out of ROM (or other static memory), - * this should be set high. - */ -#define MEMP_NUM_PBUF 10 - -/** - * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. - * (requires the LWIP_TCP option) - */ -#define MEMP_NUM_TCP_PCB MAX_SOCKETS_TCP - -#define MEMP_NUM_TCP_PCB_LISTEN MAX_LISTENING_SOCKETS_TCP - -/** - * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. - * (requires the LWIP_TCP option) - */ -//#define MEMP_NUM_TCP_SEG 12 - -/** - * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used - * for incoming packets. - * (only needed if you use tcpip.c) - */ - -#define MEMP_NUM_TCPIP_MSG_INPKT 16 - -/** - * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. - * (requires NO_SYS==0) - */ -#define MEMP_NUM_SYS_TIMEOUT 12 - -/** - * MEMP_NUM_NETBUF: the number of struct netbufs. - * (only needed if you use the sequential API, like api_lib.c) - */ - -#define MEMP_NUM_NETBUF 16 - -/** - * MEMP_NUM_NETCONN: the number of struct netconns. - * (only needed if you use the sequential API, like api_lib.c) - * - * This number corresponds to the maximum number of active sockets at any - * given point in time. This number must be sum of max. TCP sockets, max. TCP - * sockets used for listening, and max. number of UDP sockets - */ -#define MEMP_NUM_NETCONN (MAX_SOCKETS_TCP + \ - MAX_LISTENING_SOCKETS_TCP + MAX_SOCKETS_UDP) - - - -/** - * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. - */ -#if ((defined(CFG_LWIP_MEM_POLICY))&&(CFG_LWIP_MEM_POLICY == LWIP_REDUCE_THE_PLAN)) -#define PBUF_POOL_SIZE 3 -#else -#define PBUF_POOL_SIZE 10 -#endif - -/* - ---------------------------------- - ---------- Pbuf options ---------- - ---------------------------------- -*/ - -/** - * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is - * designed to accomodate single full size TCP frame in one pbuf, including - * TCP_MSS, IP header, and link header. - */ -#define PBUF_POOL_BUFSIZE 1580 - - -/* - --------------------------------- - ---------- RAW options ---------- - --------------------------------- -*/ -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#define LWIP_RAW 1 -#ifdef CONFIG_IPV6 -#define LWIP_IPV6 1 -#endif - -/* Enable IPv4 Auto IP */ -#ifdef CONFIG_AUTOIP -#define LWIP_AUTOIP 1 -#define LWIP_DHCP_AUTOIP_COOP 1 -#define LWIP_DHCP_AUTOIP_COOP_TRIES 5 -#endif - -/* - ------------------------------------ - ---------- Socket options ---------- - ------------------------------------ -*/ -/** - * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) - */ -#define LWIP_SOCKET 1 -#define LWIP_NETIF_API 1 - -/** - * LWIP_RECV_CB==1: Enable callback when a socket receives data. - */ -#define LWIP_RECV_CB 1 -/** - * SO_REUSE==1: Enable SO_REUSEADDR option. - */ -#define SO_REUSE 1 -#define SO_REUSE_RXTOALL 1 - -/** - * Enable TCP_KEEPALIVE - */ -#define LWIP_TCP_KEEPALIVE 1 - -/* - ---------------------------------------- - ---------- Statistics options ---------- - ---------------------------------------- -*/ -/** - * LWIP_STATS==1: Enable statistics collection in lwip_stats. - */ -#define LWIP_STATS 1 - -/** - * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. - */ -#define LWIP_STATS_DISPLAY 0 - -/* - ---------------------------------- - ---------- DHCP options ---------- - ---------------------------------- -*/ -/** - * LWIP_DHCP==1: Enable DHCP module. - */ -#define LWIP_DHCP 1 -#define LWIP_NETIF_STATUS_CALLBACK 1 - -/** - * DNS related options, revisit later to fine tune. - */ -#define LWIP_DNS 1 -#define DNS_TABLE_SIZE 2 // number of table entries, default 4 -//#define DNS_MAX_NAME_LENGTH 64 // max. name length, default 256 -#define DNS_MAX_SERVERS 2 // number of DNS servers, default 2 -#define DNS_DOES_NAME_CHECK 1 // compare received name with given,def 0 -#define DNS_MSG_SIZE 512 -#define MDNS_MSG_SIZE 512 -#define MDNS_TABLE_SIZE 1 // number of mDNS table entries -#define MDNS_MAX_SERVERS 1 // number of mDNS multicast addresses -/* TODO: Number of active UDP PCBs is equal to number of active UDP sockets plus - * two. Need to find the users of these 2 PCBs - */ -#define MEMP_NUM_UDP_PCB (MAX_SOCKETS_UDP + 2) -/* NOTE: some times the socket() call for SOCK_DGRAM might fail if you dont - * have enough MEMP_NUM_UDP_PCB */ - -/* - ---------------------------------- - ---------- IGMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_IGMP==1: Turn on IGMP module. - */ -#define LWIP_IGMP 1 - -/** - * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and - * SO_SNDTIMEO processing. - */ -#define LWIP_SO_SNDTIMEO 1 - -/** - * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and - * SO_RCVTIMEO processing. - */ -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -/** - * TCP_LISTEN_BACKLOG==1: Handle backlog connections. - */ -#define TCP_LISTEN_BACKLOG 1 -#define LWIP_PROVIDE_ERRNO 1 - -#include -#define ERRNO 1 - -//#define LWIP_SNMP 1 - - -/* - ------------------------------------------------ - ---------- Network Interfaces options ---------- - ------------------------------------------------ -*/ -/** - * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname - * field. - */ -#define LWIP_NETIF_HOSTNAME 1 - - -/* -The STM32F107 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware: - - To use this feature let the following define uncommented. - - To disable it and process by CPU comment the the checksum. -*/ -//#define CHECKSUM_BY_HARDWARE - - -#ifdef CHECKSUM_BY_HARDWARE - /* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/ - #define CHECKSUM_GEN_IP 0 - /* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/ - #define CHECKSUM_GEN_UDP 0 - /* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/ - #define CHECKSUM_GEN_TCP 0 - /* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/ - #define CHECKSUM_CHECK_IP 0 - /* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/ - #define CHECKSUM_CHECK_UDP 0 - /* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/ - #define CHECKSUM_CHECK_TCP 0 -#else - /* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/ - #define CHECKSUM_GEN_IP 1 - /* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/ - #define CHECKSUM_GEN_UDP 1 - /* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/ - #define CHECKSUM_GEN_TCP 1 - /* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/ - #define CHECKSUM_CHECK_IP 1 - /* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/ - #define CHECKSUM_CHECK_UDP 1 - /* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/ - #define CHECKSUM_CHECK_TCP 1 -#endif - -/** - * TCP_RESOURCE_FAIL_RETRY_LIMIT: limit for retrying sending of tcp segment - * on resource failure error returned by driver. - */ -#define TCP_RESOURCE_FAIL_RETRY_LIMIT 50 - -//#ifdef CONFIG_ENABLE_MXCHIP -/* save memory */ -#if ((defined(CFG_LWIP_MEM_POLICY))&&(CFG_LWIP_MEM_POLICY == LWIP_REDUCE_THE_PLAN)) -#define PBUF_POOL_SIZE (3) -#define TCP_MSS (1500 - 40) -/* TCP receive window. */ -#define TCP_WND (3 * TCP_MSS) -/* TCP sender buffer space (bytes). */ -#define TCP_SND_BUF (10*TCP_MSS) - -#define TCP_SND_QUEUELEN (20) -#else -#define PBUF_POOL_SIZE 10 -#define TCP_MSS (1500 - 40) -/* TCP receive window. */ -#define TCP_WND (10*TCP_MSS) -/* TCP sender buffer space (bytes). */ -#define TCP_SND_BUF (10*TCP_MSS) - -#define TCP_SND_QUEUELEN (20) -#endif - -/* ARP before DHCP causes multi-second delay - turn it off */ -#define DHCP_DOES_ARP_CHECK (0) - -#define TCP_MAX_ACCEPT_CONN 5 -#define MEMP_NUM_TCP_SEG (TCP_SND_QUEUELEN*2) - -#define IP_REASS_MAX_PBUFS 0 -#define IP_REASSEMBLY 0 -#define IP_REASS_MAX_PBUFS 0 -#define IP_REASSEMBLY 0 -#define MEMP_NUM_REASSDATA 0 -#define IP_FRAG 0 - -#define MEM_LIBC_MALLOC (0) - -#define DEFAULT_UDP_RECVMBOX_SIZE 3 //each udp socket max buffer 3 packets. - -#define MEMP_MEM_MALLOC (0) -#define TCP_MSL (TCP_TMR_INTERVAL) - -#define LWIP_COMPAT_MUTEX_ALLOWED (1) - -#define MEMP_STATS 1 -#define MEM_STATS 1 - -#define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS - -#define ETHARP_SUPPORT_STATIC_ENTRIES 1 - -#define LWIP_RIPPLE20 1 -#endif /* __LWIPOPTS_H__ */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.c deleted file mode 100644 index b45886effead61093fd3f88179ac3748b5feb185..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.c +++ /dev/null @@ -1,789 +0,0 @@ -#include "include.h" -#include -#include - -#include -#include "netif/etharp.h" -#include "lwip/netif.h" -#include -#include -#include -#include -#include "lwip/prot/dhcp.h" - -#include -#include "ethernetif.h" - -#include "sa_station.h" -#include "drv_model_pub.h" -#include "mem_pub.h" -#include "common.h" -#include "rw_pub.h" -#include "lwip_netif_address.h" -#include "rtos_pub.h" - -#if CFG_ROLE_LAUNCH -#include "role_launch.h" -#endif - -struct ipv4_config sta_ip_settings; -struct ipv4_config uap_ip_settings; -static int up_iface; -uint32_t sta_ip_start_flag = 0; -uint32_t uap_ip_start_flag = 0; - -#ifdef CONFIG_IPV6 -#define IPV6_ADDR_STATE_TENTATIVE "Tentative" -#define IPV6_ADDR_STATE_PREFERRED "Preferred" -#define IPV6_ADDR_STATE_INVALID "Invalid" -#define IPV6_ADDR_STATE_VALID "Valid" -#define IPV6_ADDR_STATE_DEPRECATED "Deprecated" -#define IPV6_ADDR_TYPE_LINKLOCAL "Link-Local" -#define IPV6_ADDR_TYPE_GLOBAL "Global" -#define IPV6_ADDR_TYPE_UNIQUELOCAL "Unique-Local" -#define IPV6_ADDR_TYPE_SITELOCAL "Site-Local" -#define IPV6_ADDR_UNKNOWN "Unknown" -#endif - - -#define net_e warning_prf -#define net_d warning_prf - -typedef void (*net_sta_ipup_cb_fn)(void* data); - -struct interface { - struct netif netif; - ip_addr_t ipaddr; - ip_addr_t nmask; - ip_addr_t gw; -}; -FUNCPTR sta_connected_func; - -static struct interface g_mlan = {{0}}; -static struct interface g_uap = {{0}}; -net_sta_ipup_cb_fn sta_ipup_cb = NULL; - -extern void *net_get_sta_handle(void); -extern void *net_get_uap_handle(void); -extern err_t lwip_netif_init(struct netif *netif); -extern err_t lwip_netif_uap_init(struct netif *netif); -extern int net_get_if_ip_addr(uint32_t *ip, void *intrfc_handle); -extern int net_get_if_ip_mask(uint32_t *nm, void *intrfc_handle); -extern int net_configure_address(struct ipv4_config *addr, void *intrfc_handle); -extern int dhcp_server_start(void *intrfc_handle); -extern void dhcp_server_stop(void); -extern void net_configure_dns(struct wlan_ip_config *ip); - -#ifdef CONFIG_IPV6 -char *ipv6_addr_state_to_desc(unsigned char addr_state) -{ - if (ip6_addr_istentative(addr_state)) - return IPV6_ADDR_STATE_TENTATIVE; - else if (ip6_addr_ispreferred(addr_state)) - return IPV6_ADDR_STATE_PREFERRED; - else if (ip6_addr_isinvalid(addr_state)) - return IPV6_ADDR_STATE_INVALID; - else if (ip6_addr_isvalid(addr_state)) - return IPV6_ADDR_STATE_VALID; - else if (ip6_addr_isdeprecated(addr_state)) - return IPV6_ADDR_STATE_DEPRECATED; - else - return IPV6_ADDR_UNKNOWN; -} - -char *ipv6_addr_type_to_desc(struct ipv6_config *ipv6_conf) -{ - if (ip6_addr_islinklocal((ip6_addr_t *)ipv6_conf->address)) - return IPV6_ADDR_TYPE_LINKLOCAL; - else if (ip6_addr_isglobal((ip6_addr_t *)ipv6_conf->address)) - return IPV6_ADDR_TYPE_GLOBAL; - else if (ip6_addr_isuniquelocal((ip6_addr_t *)ipv6_conf->address)) - return IPV6_ADDR_TYPE_UNIQUELOCAL; - else if (ip6_addr_issitelocal((ip6_addr_t *)ipv6_conf->address)) - return IPV6_ADDR_TYPE_SITELOCAL; - else - return IPV6_ADDR_UNKNOWN; -} -#endif /* CONFIG_IPV6 */ - -int net_dhcp_hostname_set(char *hostname) -{ - netif_set_hostname(&g_mlan.netif, hostname); - return 0; -} - -void net_ipv4stack_init(void) -{ - static bool tcpip_init_done = 0; - if (tcpip_init_done) - return; - - net_d("Initializing TCP/IP stack\r\n"); - tcpip_init(NULL, NULL); - tcpip_init_done = true; -} - -#ifdef CONFIG_IPV6 -void net_ipv6stack_init(struct netif *netif) -{ - uint8_t mac[6]; - - netif->flags |= NETIF_IPV6_FLAG_UP; - - /* Set Multicast filter for IPV6 link local address - * It contains first three bytes: 0x33 0x33 0xff (fixed) - * and last three bytes as last three bytes of device mac */ - mac[0] = 0x33; - mac[1] = 0x33; - mac[2] = 0xff; - mac[3] = netif->hwaddr[3]; - mac[4] = netif->hwaddr[4]; - mac[5] = netif->hwaddr[5]; - wifi_add_mcast_filter(mac); - - netif_create_ip6_linklocal_address(netif, 1); - netif->ip6_autoconfig_enabled = 1; - - /* IPv6 routers use multicast IPv6 ff02::1 and MAC address - 33:33:00:00:00:01 for router advertisements */ - mac[0] = 0x33; - mac[1] = 0x33; - mac[2] = 0x00; - mac[3] = 0x00; - mac[4] = 0x00; - mac[5] = 0x01; - wifi_add_mcast_filter(mac); -} - -static void wm_netif_ipv6_status_callback(struct netif *n) -{ - /* TODO: Implement appropriate functionality here*/ - net_d("Received callback on IPv6 address state change"); - wlan_wlcmgr_send_msg(WIFI_EVENT_NET_IPV6_CONFIG, - WIFI_EVENT_REASON_SUCCESS, NULL); -} -#endif /* CONFIG_IPV6 */ - -void net_wlan_init(void) -{ - static int wlan_init_done = 0; - int ret; - - if (!wlan_init_done) { - net_ipv4stack_init(); - g_mlan.ipaddr.addr = INADDR_ANY; - ret = netifapi_netif_add(&g_mlan.netif, &g_mlan.ipaddr, - &g_mlan.ipaddr, &g_mlan.ipaddr, NULL, - lwip_netif_init, tcpip_input); - if (ret) { - /*FIXME: Handle the error case cleanly */ - net_e("MLAN interface add failed"); - } -#ifdef CONFIG_IPV6 - net_ipv6stack_init(&g_mlan.netif); -#endif /* CONFIG_IPV6 */ - - ret = netifapi_netif_add(&g_uap.netif, &g_uap.ipaddr, - &g_uap.ipaddr, &g_uap.ipaddr, NULL, - lwip_netif_uap_init, tcpip_input); - if (ret) { - /*FIXME: Handle the error case cleanly */ - net_e("UAP interface add failed"); - } - wlan_init_done = 1; - } - - return; -} - -void net_set_sta_ipup_callback(void *fn) -{ - sta_ipup_cb = (net_sta_ipup_cb_fn)fn; -} - -void user_connected_callback(FUNCPTR fn) -{ - sta_connected_func = fn; -} - -static void wm_netif_status_static_callback(struct netif *n) -{ - if (n->flags & NETIF_FLAG_UP) - { - // static IP success; - os_printf("using static ip...\n"); - mhdr_set_station_status(RW_EVT_STA_GOT_IP);/* dhcp success*/ - - if(sta_ipup_cb != NULL) - sta_ipup_cb(NULL); - - if(sta_connected_func != NULL) - (*sta_connected_func)(); - } - else - { - // static IP fail; - } -} - - -static void wm_netif_status_callback(struct netif *n) -{ - FUNC_1PARAM_PTR fn; - struct dhcp *dhcp; - u32 val; - - if (n->flags & NETIF_FLAG_UP) - { - dhcp = netif_dhcp_data(n); - if(dhcp != NULL) - { - if (dhcp->state == DHCP_STATE_BOUND) - { - os_printf("ip_addr: %x\r\n", n->ip_addr.addr); - -#if CFG_ROLE_LAUNCH - rl_pre_sta_set_status(RL_STATUS_STA_LAUNCHED); -#endif - fn = (FUNC_1PARAM_PTR)bk_wlan_get_status_cb(); - if(fn) - { - val = RW_EVT_STA_GOT_IP; - (*fn)(&val); - } - mhdr_set_station_status(RW_EVT_STA_GOT_IP); - /* dhcp success*/ - if(sta_ipup_cb != NULL) - sta_ipup_cb(NULL); - - if(sta_connected_func != NULL) - (*sta_connected_func)(); - } - else - { - // dhcp fail - } - } - else - { - // static IP success; - } - } - else - { - // dhcp fail; - } -} - -static int check_iface_mask(void *handle, uint32_t ipaddr) -{ - uint32_t interface_ip, interface_mask; - net_get_if_ip_addr(&interface_ip, handle); - net_get_if_ip_mask(&interface_mask, handle); - if (interface_ip > 0) - if ((interface_ip & interface_mask) == - (ipaddr & interface_mask)) - return 0; - return -1; -} - -void *net_ip_to_interface(uint32_t ipaddr) -{ - int ret; - void *handle; - /* Check mlan handle */ - handle = net_get_sta_handle(); - ret = check_iface_mask(handle, ipaddr); - if (ret == 0) - return handle; - - /* Check uap handle */ - handle = net_get_uap_handle(); - ret = check_iface_mask(handle, ipaddr); - if (ret == 0) - return handle; - - /* If more interfaces are added then above check needs to done for - * those newly added interfaces - */ - return NULL; -} - -void *net_sock_to_interface(int sock) -{ - struct sockaddr_in peer; - unsigned long peerlen = sizeof(struct sockaddr_in); - void *req_iface = NULL; - - getpeername(sock, (struct sockaddr *)&peer, &peerlen); - req_iface = net_ip_to_interface(peer.sin_addr.s_addr); - return req_iface; -} - -void *net_get_sta_handle(void) -{ - return &g_mlan.netif; -} - -void *net_get_uap_handle(void) -{ - return &g_uap.netif; -} - -void *net_get_netif_handle(uint8_t iface) -{ - - return NULL; -} - -void net_interface_up(void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - netifapi_netif_set_up(&if_handle->netif); -} - -void net_interface_down(void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - netifapi_netif_set_down(&if_handle->netif); -} - -#ifdef CONFIG_IPV6 -void net_interface_deregister_ipv6_callback(void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - if (intrfc_handle == &g_mlan) - netif_set_ipv6_status_callback(&if_handle->netif, NULL); -} -#endif - -void net_interface_dhcp_stop(void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - netifapi_dhcp_stop(&if_handle->netif); - netif_set_status_callback(&if_handle->netif, NULL); -} - -void sta_ip_down(void) -{ - if(sta_ip_start_flag) - { - os_printf("sta_ip_down\r\n"); - - sta_ip_start_flag = 0; - - netifapi_netif_set_down(&g_mlan.netif); - netif_set_status_callback(&g_mlan.netif, NULL); - netifapi_dhcp_stop(&g_mlan.netif); - } -} - -void sta_ip_start(void) -{ - struct wlan_ip_config address = {0}; - - if(!sta_ip_start_flag) - { - os_printf("sta_ip_start\r\n"); - sta_ip_start_flag = 1; - net_configure_address(&sta_ip_settings, net_get_sta_handle()); - - return; - } - - os_printf("sta_ip_start2:0x%x\r\n", address.ipv4.address); - net_get_if_addr(&address, net_get_sta_handle()); - if((mhdr_get_station_status() == RW_EVT_STA_CONNECTED) - && (0 != address.ipv4.address)) - { - mhdr_set_station_status(RW_EVT_STA_GOT_IP); - } -} - -void sta_set_vif_netif(void) -{ - rwm_mgmt_set_vif_netif(&g_mlan.netif); -} - -void ap_set_vif_netif(void) -{ - rwm_mgmt_set_vif_netif(&g_uap.netif); -} - -void sta_set_default_netif(void) -{ - netifapi_netif_set_default(net_get_sta_handle()); -} - -void ap_set_default_netif(void) -{ - // as the default netif is sta's netif, so ap need to send - // boardcast or not sub net packets, need set ap netif before - // send those packets, after finish sending, reset default netif - // to sat's netif. - netifapi_netif_set_default(net_get_uap_handle()); -} - -void reset_default_netif(void) -{ - netifapi_netif_set_default(NULL); -} - -uint32_t sta_ip_is_start(void) -{ - return sta_ip_start_flag; -} - -void uap_ip_down(void) -{ - if (uap_ip_start_flag ) - { - os_printf("uap_ip_down\r\n"); - uap_ip_start_flag = 0; - - netifapi_netif_set_down(&g_uap.netif); - netif_set_status_callback(&g_uap.netif, NULL); - dhcp_server_stop(); - } -} - -void uap_ip_start(void) -{ - if ( !uap_ip_start_flag ) - { - os_printf("uap_ip_start\r\n"); - uap_ip_start_flag = 1; - net_configure_address(&uap_ip_settings, net_get_uap_handle()); - } -} - -uint32_t uap_ip_is_start(void) -{ - return uap_ip_start_flag; -} - -#define DEF_UAP_IP 0xc0a80a01UL /* 192.168.10.1 */ - -void ip_address_set(int iface, int dhcp, char *ip, char *mask, char*gw, char*dns) -{ - uint32_t tmp; - struct ipv4_config addr; - - memset(&addr, 0, sizeof(struct ipv4_config)); - if (dhcp == 1) { - addr.addr_type = ADDR_TYPE_DHCP; - } else { - addr.addr_type = ADDR_TYPE_STATIC; - tmp = inet_addr((char*)ip); - addr.address = (tmp); - tmp = inet_addr((char*)mask); - if (tmp == 0xFFFFFFFF) - tmp = 0x00FFFFFF;// if not set valid netmask, set as 255.255.255.0 - addr.netmask= (tmp); - tmp = inet_addr((char*)gw); - addr.gw = (tmp); - - tmp = inet_addr((char*)dns); - addr.dns1 = (tmp); - } - - if (iface == 1) // Station - memcpy(&sta_ip_settings, &addr, sizeof(addr)); - else - memcpy(&uap_ip_settings, &addr, sizeof(addr)); -} - -int net_configure_address(struct ipv4_config *addr, void *intrfc_handle) -{ - if (!intrfc_handle) - return -1; - - struct interface *if_handle = (struct interface *)intrfc_handle; - - net_d("\r\nconfiguring interface %s (with %s)", - (if_handle == &g_mlan) ? "mlan" :"uap", - (addr->addr_type == ADDR_TYPE_DHCP) - ? "DHCP client" : "Static IP"); - netifapi_netif_set_down(&if_handle->netif); - - /* De-register previously registered DHCP Callback for correct - * address configuration. - */ - netif_set_status_callback(&if_handle->netif, NULL); -#ifdef CONFIG_IPV6 - if (if_handle == &g_mlan) { - netif_set_ipv6_status_callback(&if_handle->netif, - wm_netif_ipv6_status_callback); - /* Explicitly call this function so that the linklocal address - * gets updated even if the interface does not get any IPv6 - * address in its lifetime */ - wm_netif_ipv6_status_callback(&if_handle->netif); - } -#endif - switch (addr->addr_type) { - case ADDR_TYPE_STATIC: - if_handle->ipaddr.addr = addr->address; - if_handle->nmask.addr = addr->netmask; - if_handle->gw.addr = addr->gw; - - netifapi_netif_set_addr(&if_handle->netif, &if_handle->ipaddr, - &if_handle->nmask, &if_handle->gw); - netifapi_netif_set_up(&if_handle->netif); - net_configure_dns((struct wlan_ip_config *)addr); - if(if_handle == &g_mlan) - { - netif_set_status_callback(&if_handle->netif, - wm_netif_status_static_callback); - } - break; - - case ADDR_TYPE_DHCP: - /* Reset the address since we might be transitioning from static to DHCP */ - memset(&if_handle->ipaddr, 0, sizeof(ip_addr_t)); - memset(&if_handle->nmask, 0, sizeof(ip_addr_t)); - memset(&if_handle->gw, 0, sizeof(ip_addr_t)); - netifapi_netif_set_addr(&if_handle->netif, &if_handle->ipaddr, - &if_handle->nmask, &if_handle->gw); - - netif_set_status_callback(&if_handle->netif, - wm_netif_status_callback); - netifapi_netif_set_up(&if_handle->netif); - netifapi_dhcp_start(&if_handle->netif); - break; - - default: - break; - } - /* Finally this should send the following event. */ - if (if_handle == &g_mlan) { - // static IP up; - - /* XXX For DHCP, the above event will only indicate that the - * DHCP address obtaining process has started. Once the DHCP - * address has been obtained, another event, - * WD_EVENT_NET_DHCP_CONFIG, should be sent to the wlcmgr. - */ - up_iface = 1; - - // we always set sta netif as the default. - sta_set_default_netif(); - } else { - // softap IP up, start dhcp server; - dhcp_server_start(net_get_uap_handle()); - up_iface = 0; - - // as the default netif is sta's netif, so ap need to send - // boardcast or not sub net packets, need set ap netif before - // send those packets, after finish sending, reset default netif - // to sta's netif. - os_printf("def netif is no ap's netif, sending boardcast or no-subnet ip packets may failed\r\n"); - } - - return 0; -} - -int net_get_if_addr(struct wlan_ip_config *addr, void *intrfc_handle) -{ - const ip_addr_t *tmp; - struct interface *if_handle = (struct interface *)intrfc_handle; - - if(netif_is_up(&if_handle->netif)) { - addr->ipv4.address = if_handle->netif.ip_addr.addr; - addr->ipv4.netmask = if_handle->netif.netmask.addr; - addr->ipv4.gw = if_handle->netif.gw.addr; - - tmp = dns_getserver(0); - addr->ipv4.dns1 = tmp->addr; - tmp = dns_getserver(1); - addr->ipv4.dns2 = tmp->addr; - } - - return 0; -} - -int net_get_if_macaddr(void *macaddr, void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - - os_memcpy(macaddr, &if_handle->netif.hwaddr[0], if_handle->netif.hwaddr_len); - - return 0; -} - -#ifdef CONFIG_IPV6 -int net_get_if_ipv6_addr(struct wlan_ip_config *addr, void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - int i; - - for (i = 0; i < MAX_IPV6_ADDRESSES; i++) { - memcpy(addr->ipv6[i].address, - if_handle->netif.ip6_addr[i].addr, 16); - addr->ipv6[i].addr_state = if_handle->netif.ip6_addr_state[i]; - } - /* TODO carry out more processing based on IPv6 fields in netif */ - return 0; -} - -int net_get_if_ipv6_pref_addr(struct wlan_ip_config *addr, void *intrfc_handle) -{ - int i, ret = 0; - struct interface *if_handle = (struct interface *)intrfc_handle; - - for (i = 0; i < MAX_IPV6_ADDRESSES; i++) { - if (if_handle->netif.ip6_addr_state[i] == IP6_ADDR_PREFERRED) { - memcpy(addr->ipv6[ret++].address, - if_handle->netif.ip6_addr[i].addr, 16); - } - } - return ret; -} -#endif /* CONFIG_IPV6 */ - -int net_get_if_ip_addr(uint32_t *ip, void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - - *ip = if_handle->netif.ip_addr.addr; - return 0; -} - -int net_get_if_gw_addr(uint32_t *ip, void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - - *ip = if_handle->netif.gw.addr; - - return 0; -} - -int net_get_if_ip_mask(uint32_t *nm, void *intrfc_handle) -{ - struct interface *if_handle = (struct interface *)intrfc_handle; - - *nm = if_handle->netif.netmask.addr; - return 0; -} - -void net_configure_dns(struct wlan_ip_config *ip) -{ - ip_addr_t tmp; - - if (ip->ipv4.addr_type == ADDR_TYPE_STATIC) { - - if (ip->ipv4.dns1 == 0) - ip->ipv4.dns1 = ip->ipv4.gw; - if (ip->ipv4.dns2 == 0) - ip->ipv4.dns2 = ip->ipv4.dns1; - - tmp.addr = ip->ipv4.dns1; - dns_setserver(0, &tmp); - tmp.addr = ip->ipv4.dns2; - dns_setserver(1, &tmp); - } - - /* DNS MAX Retries should be configured in lwip/dns.c to 3/4 */ - /* DNS Cache size of about 4 is sufficient */ -} - -void net_wlan_initial(void) -{ - net_ipv4stack_init(); - -#ifdef CONFIG_IPV6 - net_ipv6stack_init(&g_mlan.netif); -#endif /* CONFIG_IPV6 */ -} - -void net_wlan_add_netif(void *mac) -{ - VIF_INF_PTR vif_entry = NULL; - struct interface *wlan_if = NULL; - err_t err; - u8 vif_idx; - u8 *b = (u8*)mac; - - if(!b || (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5]))) - return; - - vif_idx = rwm_mgmt_vif_mac2idx(mac); - if(vif_idx == 0xff) { - os_printf("net_add_netif-not-found\r\n"); - return ; - } - - vif_entry = rwm_mgmt_vif_idx2ptr(vif_idx); - if(!vif_entry) { - os_printf("net_wlan_add_netif not vif found, %d\r\n", vif_idx); - return ; - } - - if(vif_entry->type == VIF_AP) { - wlan_if = &g_uap; - } else if(vif_entry->type == VIF_STA) { - wlan_if = &g_mlan; - } else { - os_printf("net_wlan_add_netif with other role\r\n"); - return ; - } - - wlan_if->ipaddr.addr = INADDR_ANY; - - err = netifapi_netif_add(&wlan_if->netif, - &wlan_if->ipaddr, - &wlan_if->ipaddr, - &wlan_if->ipaddr, - (void*)vif_entry, - ethernetif_init, - tcpip_input); - if (err) - { - os_printf("net_wlan_add_netif failed\r\n"); - } - else - { - vif_entry->priv = &wlan_if->netif; - } - - os_printf("[net]addvif_idx:%d\r\n", vif_idx); -} - -void net_wlan_remove_netif(void *mac) -{ - err_t err; - u8 vif_idx; - VIF_INF_PTR vif_entry = NULL; - struct netif *netif = NULL; - u8 *b = (u8*)mac; - - if(!b || (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5]))) - return; - - vif_idx = rwm_mgmt_vif_mac2idx(mac); - if(vif_idx == 0xff) { - os_printf("net_wlan_add_netif not vif idx found\r\n"); - return ; - } - vif_entry = rwm_mgmt_vif_idx2ptr(vif_idx); - if(!vif_entry) { - os_printf("net_wlan_add_netif not vif found, %d\r\n", vif_idx); - return ; - } - - netif = (struct netif *)vif_entry->priv; - if(!netif) { - os_printf("net_wlan_remove_netif netif is null\r\n"); - return; - } - - err = netifapi_netif_remove(netif); - if(err != ERR_OK) { - os_printf("net_wlan_remove_netif failed\r\n"); - } else { - netif->state = NULL; - } - - os_printf("[net]remoVif_idx:%d\r\n", vif_idx); -} -//eof - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.h deleted file mode 100644 index 89c3cbef5d01607ad6fbbcf55086b38731debd1a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/net.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef _NET_H_ -#define _NET_H_ - -#include "lwip_netif_address.h" - -extern void uap_ip_down(void); -extern void uap_ip_start(void); -extern void sta_ip_down(void); -extern void sta_ip_start(void); -extern uint32_t uap_ip_is_start(void); -extern uint32_t sta_ip_is_start(void); -extern void *net_get_sta_handle(void); -extern void *net_get_uap_handle(void); -extern void net_wlan_remove_netif(void *mac); -extern int net_get_if_macaddr(void *macaddr, void *intrfc_handle); -extern int net_get_if_addr(struct wlan_ip_config *addr, void *intrfc_handle); -extern void ip_address_set(int iface, int dhcp, char *ip, char *mask, char*gw, char*dns); - -#endif // _NET_H_ -// eof - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/sys_arch.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/sys_arch.c deleted file mode 100644 index 411ba82d9bb4b9efe62292fa8d22515dd586c485..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/port/sys_arch.c +++ /dev/null @@ -1,500 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* lwIP includes. */ -#include "lwip/debug.h" -#include "lwip/def.h" -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/stats.h" -#include "sys_rtos.h" -#include "lwip/timeouts.h" -#include "rtos_pub.h" -#include "portmacro.h" - -#define CFG_ENABLE_LWIP_MUTEX 1 - -#if CFG_ENABLE_LWIP_MUTEX -static sys_mutex_t sys_arch_mutex; -#endif - -/*-----------------------------------------------------------------------------------*/ -err_t sys_mbox_new(sys_mbox_t *mbox, int size) -{ - (void ) size; - - if (size > 0) - *mbox = xQueueCreate( size, sizeof( void * ) ); - else - *mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) ); - -#if SYS_STATS - ++lwip_stats.sys.mbox.used; - if (lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) { - lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; - } -#endif /* SYS_STATS */ - - if (*mbox == NULL) - return ERR_MEM; - - return ERR_OK; -} - -/*-----------------------------------------------------------------------------------*/ -/* - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. -*/ -void sys_mbox_free(sys_mbox_t *mbox) -{ - if( uxQueueMessagesWaiting( *mbox ) ) - { - /* Line for breakpoint. Should never break here! */ - portNOP(); -#if SYS_STATS - lwip_stats.sys.mbox.err++; -#endif /* SYS_STATS */ - - // TODO notify the user of failure. - } - - vQueueDelete( *mbox ); - -#if SYS_STATS - --lwip_stats.sys.mbox.used; -#endif /* SYS_STATS */ -} - -/*-----------------------------------------------------------------------------------*/ -// Posts the "msg" to the mailbox. -void sys_mbox_post(sys_mbox_t *mbox, void *data) -{ - while ( xQueueSendToBack(*mbox, &data, portMAX_DELAY ) != pdTRUE ){} -} - - -/*-----------------------------------------------------------------------------------*/ -// Try to post the "msg" to the mailbox. -err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) -{ -err_t result; - - if ( xQueueSend( *mbox, &msg, 0 ) == pdPASS ) - { - result = ERR_OK; - } - else { - // could not post, queue must be full - result = ERR_MEM; - -#if SYS_STATS - lwip_stats.sys.mbox.err++; -#endif /* SYS_STATS */ - - } - - return result; -} - -/*-----------------------------------------------------------------------------------*/ -/* - Blocks the thread until a message arrives in the mailbox, but does - not block the thread longer than "timeout" milliseconds (similar to - the sys_arch_sem_wait() function). The "msg" argument is a result - parameter that is set by the function (i.e., by doing "*msg = - ptr"). The "msg" parameter maybe NULL to indicate that the message - should be dropped. - - The return values are the same as for the sys_arch_sem_wait() function: - Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a - timeout. - - Note that a function with a similar name, sys_mbox_fetch(), is - implemented by lwIP. -*/ -u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) -{ -void *dummyptr; -portTickType StartTime, EndTime, Elapsed; - - StartTime = xTaskGetTickCount(); - - if ( msg == NULL ) - { - msg = &dummyptr; - } - - if ( timeout != 0 ) - { - if ( pdTRUE == xQueueReceive( *mbox, &(*msg), timeout / portTICK_RATE_MS ) ) - { - EndTime = xTaskGetTickCount(); - Elapsed = (EndTime - StartTime) * portTICK_RATE_MS; - - return ( Elapsed ); - } - else // timed out blocking for message - { - *msg = NULL; - - return SYS_ARCH_TIMEOUT; - } - } - else // block forever for a message. - { - while( pdTRUE != xQueueReceive( *mbox, &(*msg), portMAX_DELAY ) ){} // time is arbitrary - EndTime = xTaskGetTickCount(); - Elapsed = (EndTime - StartTime) * portTICK_RATE_MS; - - return ( Elapsed ); // return time blocked TODO test - } -} - -/*-----------------------------------------------------------------------------------*/ -/* - Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll - return with SYS_MBOX_EMPTY. On success, 0 is returned. -*/ -u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) -{ -void *dummyptr; - - if ( msg == NULL ) - { - msg = &dummyptr; - } - - if ( pdTRUE == xQueueReceive( *mbox, &(*msg), 0 ) ) - { - return ERR_OK; - } - else - { - return SYS_MBOX_EMPTY; - } -} -/*----------------------------------------------------------------------------------*/ -int sys_mbox_valid(sys_mbox_t *mbox) -{ - if (*mbox == SYS_MBOX_NULL) - return 0; - else - return 1; -} -/*-----------------------------------------------------------------------------------*/ -void sys_mbox_set_invalid(sys_mbox_t *mbox) -{ - *mbox = SYS_MBOX_NULL; -} - -/*-----------------------------------------------------------------------------------*/ -// Creates a new semaphore. The "count" argument specifies -// the initial state of the semaphore. -err_t sys_sem_new(sys_sem_t *sem, u8_t count) -{ - vSemaphoreCreateBinary(*sem ); - if(*sem == NULL) - { - -#if SYS_STATS - ++lwip_stats.sys.sem.err; -#endif /* SYS_STATS */ - return ERR_MEM; - } - - if(count == 0) // Means it can't be taken - { - xSemaphoreTake(*sem,1); - } - -#if SYS_STATS - ++lwip_stats.sys.sem.used; - if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) { - lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; - } -#endif /* SYS_STATS */ - - return ERR_OK; -} - -/*-----------------------------------------------------------------------------------*/ -/* - Blocks the thread while waiting for the semaphore to be - signaled. If the "timeout" argument is non-zero, the thread should - only be blocked for the specified time (measured in - milliseconds). - - If the timeout argument is non-zero, the return value is the number of - milliseconds spent waiting for the semaphore to be signaled. If the - semaphore wasn't signaled within the specified time, the return value is - SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - (i.e., it was already signaled), the function may return zero. - - Notice that lwIP implements a function with a similar name, - sys_sem_wait(), that uses the sys_arch_sem_wait() function. -*/ -u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) -{ - portTickType StartTime, EndTime, Elapsed; - - StartTime = xTaskGetTickCount(); - - if( timeout != 0) - { - if( xSemaphoreTake( *sem, timeout / portTICK_RATE_MS ) == pdTRUE ) - { - EndTime = xTaskGetTickCount(); - Elapsed = (EndTime - StartTime) * portTICK_RATE_MS; - - return (Elapsed); // return time blocked TODO test - } - else - { - return SYS_ARCH_TIMEOUT; - } - } - else // must block without a timeout - { - while( xSemaphoreTake( *sem, portMAX_DELAY) != pdTRUE) - { - ; - } - - EndTime = xTaskGetTickCount(); - Elapsed = (EndTime - StartTime) * portTICK_RATE_MS; - - return ( Elapsed ); // return time blocked - } -} - -/*-----------------------------------------------------------------------------------*/ -// Signals a semaphore -void sys_sem_signal(sys_sem_t *sem) -{ - xSemaphoreGive(*sem); -} - -/*-----------------------------------------------------------------------------------*/ -// Deallocates a semaphore -void sys_sem_free(sys_sem_t *sem) -{ -#if SYS_STATS - --lwip_stats.sys.sem.used; -#endif /* SYS_STATS */ - - vQueueDelete(*sem); -} -/*-----------------------------------------------------------------------------------*/ -int sys_sem_valid(sys_sem_t *sem) -{ - if (*sem == SYS_SEM_NULL) - return 0; - else - return 1; -} - -/*-----------------------------------------------------------------------------------*/ -void sys_sem_set_invalid(sys_sem_t *sem) -{ - *sem = SYS_SEM_NULL; -} - -/*-----------------------------------------------------------------------------------*/ -err_t sys_mutex_trylock(sys_mutex_t *pxMutex) -{ - if (xSemaphoreTake(*pxMutex, 0) == pdPASS) - return 0; - else - return -1; -} - -/*-----------------------------------------------------------------------------------*/ -// Initialize sys arch -void sys_init(void) -{ -#if CFG_ENABLE_LWIP_MUTEX - sys_mutex_new(&sys_arch_mutex); -#endif -} - -/*-----------------------------------------------------------------------------------*/ - /* Mutexes*/ -/*-----------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------*/ -/* Create a new mutex*/ -err_t sys_mutex_new(sys_mutex_t *mutex) { - *mutex = xSemaphoreCreateMutex(); - if(*mutex == NULL) - { -#if SYS_STATS - ++lwip_stats.sys.mutex.err; -#endif /* SYS_STATS */ - return ERR_MEM; - } - -#if SYS_STATS - ++lwip_stats.sys.mutex.used; - if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) { - lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used; - } -#endif /* SYS_STATS */ - - return ERR_OK; -} -/*-----------------------------------------------------------------------------------*/ -/* Deallocate a mutex*/ -void sys_mutex_free(sys_mutex_t *mutex) -{ -#if SYS_STATS - --lwip_stats.sys.mutex.used; -#endif /* SYS_STATS */ - - vQueueDelete(*mutex); -} -/*-----------------------------------------------------------------------------------*/ -/* Lock a mutex*/ -void sys_mutex_lock(sys_mutex_t *mutex) -{ - sys_arch_sem_wait(mutex, BEKEN_WAIT_FOREVER); -} - -/*-----------------------------------------------------------------------------------*/ -/* Unlock a mutex*/ -void sys_mutex_unlock(sys_mutex_t *mutex) -{ - xSemaphoreGive(*mutex); -} - -/*-----------------------------------------------------------------------------------*/ -// TODO -/*-----------------------------------------------------------------------------------*/ -/* - Starts a new thread with priority "prio" that will begin its execution in the - function "thread()". The "arg" argument will be passed as an argument to the - thread() function. The id of the new thread is returned. Both the id and - the priority are system dependent. -*/ -sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio) -{ - xTaskHandle CreatedTask; - int result; - - result = xTaskCreate( thread, ( portCHAR * ) name, stacksize, arg, prio, &CreatedTask ); - if(result == pdPASS) - { - return CreatedTask; - } - else - { - return NULL; - } -} - -int sys_thread_delete(xTaskHandle pid) -{ - return pdPASS; -} - -/* - This optional function does a "fast" critical region protection and returns - the previous protection level. This function is only called during very short - critical regions. An embedded system which supports ISR-based drivers might - want to implement this function by disabling interrupts. Task-based systems - might want to implement this by using a mutex or disabling tasking. This - function should support recursive calls from the same task or interrupt. In - other words, sys_arch_protect() could be called while already protected. In - that case the return value indicates that it is already protected. - - sys_arch_protect() is only required if your port is supporting an operating - system. -*/ -sys_prot_t sys_arch_protect(void) -{ -#if CFG_ENABLE_LWIP_MUTEX - sys_mutex_lock(&sys_arch_mutex); - - return 0; -#else - return port_disable_interrupts_flag(); -#endif -} - -/* - This optional function does a "fast" set of critical region protection to the - value specified by pval. See the documentation for sys_arch_protect() for - more information. This function is only required if your port is supporting - an operating system. -*/ -void sys_arch_unprotect(sys_prot_t pval) -{ -#if CFG_ENABLE_LWIP_MUTEX - (void)pval; - sys_mutex_unlock(&sys_arch_mutex); -#else - port_enable_interrupts_flag(pval); -#endif -} - -/* - * Prints an assertion messages and aborts execution. - */ -void sys_assert( const char *msg ) -{ - (void) msg; - - /*FSL:only needed for debugging*/ - os_printf(msg); - os_printf("\n\r"); - vPortEnterCritical(); - - for(;;) - ; -} - -u32_t sys_now(void) -{ - return xTaskGetTickCount() * portTICK_RATE_MS; -} - -u32_t sys_jiffies(void) -{ - return xTaskGetTickCount() * portTICK_RATE_MS; -} - -void sys_arch_msleep(int ms) -{ - vTaskDelay(ms / portTICK_RATE_MS); -} -// eof - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/FILES b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/FILES deleted file mode 100644 index 0be0741d0858c6ebbc4098fba8dbb641057b778a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/FILES +++ /dev/null @@ -1,15 +0,0 @@ -api/ - The code for the high-level wrapper API. Not needed if - you use the lowel-level call-back/raw API. - -apps/ - Higher layer applications that are specifically programmed - with the lwIP low-level raw API. - -core/ - The core of the TPC/IP stack; protocol implementations, - memory and buffer management, and the low-level raw API. - -include/ - lwIP include files. - -netif/ - Generic network interface device drivers are kept here. - -For more information on the various subdirectories, check the FILES -file in each directory. diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/Filelists.mk b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/Filelists.mk deleted file mode 100644 index 7d30bb8f5397c1f39743406e9d670dc5157f529c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/Filelists.mk +++ /dev/null @@ -1,181 +0,0 @@ -# -# Copyright (c) 2001, 2002 Swedish Institute of Computer Science. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -# SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -# OF SUCH DAMAGE. -# -# This file is part of the lwIP TCP/IP stack. -# -# Author: Adam Dunkels -# - -# COREFILES, CORE4FILES: The minimum set of files needed for lwIP. -COREFILES=$(LWIPDIR)/core/init.c \ - $(LWIPDIR)/core/def.c \ - $(LWIPDIR)/core/dns.c \ - $(LWIPDIR)/core/inet_chksum.c \ - $(LWIPDIR)/core/ip.c \ - $(LWIPDIR)/core/mem.c \ - $(LWIPDIR)/core/memp.c \ - $(LWIPDIR)/core/netif.c \ - $(LWIPDIR)/core/pbuf.c \ - $(LWIPDIR)/core/raw.c \ - $(LWIPDIR)/core/stats.c \ - $(LWIPDIR)/core/sys.c \ - $(LWIPDIR)/core/tcp.c \ - $(LWIPDIR)/core/tcp_in.c \ - $(LWIPDIR)/core/tcp_out.c \ - $(LWIPDIR)/core/timeouts.c \ - $(LWIPDIR)/core/udp.c - -CORE4FILES=$(LWIPDIR)/core/ipv4/autoip.c \ - $(LWIPDIR)/core/ipv4/dhcp.c \ - $(LWIPDIR)/core/ipv4/etharp.c \ - $(LWIPDIR)/core/ipv4/icmp.c \ - $(LWIPDIR)/core/ipv4/igmp.c \ - $(LWIPDIR)/core/ipv4/ip4_frag.c \ - $(LWIPDIR)/core/ipv4/ip4.c \ - $(LWIPDIR)/core/ipv4/ip4_addr.c - -CORE6FILES=$(LWIPDIR)/core/ipv6/dhcp6.c \ - $(LWIPDIR)/core/ipv6/ethip6.c \ - $(LWIPDIR)/core/ipv6/icmp6.c \ - $(LWIPDIR)/core/ipv6/inet6.c \ - $(LWIPDIR)/core/ipv6/ip6.c \ - $(LWIPDIR)/core/ipv6/ip6_addr.c \ - $(LWIPDIR)/core/ipv6/ip6_frag.c \ - $(LWIPDIR)/core/ipv6/mld6.c \ - $(LWIPDIR)/core/ipv6/nd6.c - -# APIFILES: The files which implement the sequential and socket APIs. -APIFILES=$(LWIPDIR)/api/api_lib.c \ - $(LWIPDIR)/api/api_msg.c \ - $(LWIPDIR)/api/err.c \ - $(LWIPDIR)/api/netbuf.c \ - $(LWIPDIR)/api/netdb.c \ - $(LWIPDIR)/api/netifapi.c \ - $(LWIPDIR)/api/sockets.c \ - $(LWIPDIR)/api/tcpip.c - -# NETIFFILES: Files implementing various generic network interface functions -NETIFFILES=$(LWIPDIR)/netif/ethernet.c \ - $(LWIPDIR)/netif/slipif.c - -# SIXLOWPAN: 6LoWPAN -SIXLOWPAN=$(LWIPDIR)/netif/lowpan6.c \ - -# PPPFILES: PPP -PPPFILES=$(LWIPDIR)/netif/ppp/auth.c \ - $(LWIPDIR)/netif/ppp/ccp.c \ - $(LWIPDIR)/netif/ppp/chap-md5.c \ - $(LWIPDIR)/netif/ppp/chap_ms.c \ - $(LWIPDIR)/netif/ppp/chap-new.c \ - $(LWIPDIR)/netif/ppp/demand.c \ - $(LWIPDIR)/netif/ppp/eap.c \ - $(LWIPDIR)/netif/ppp/ecp.c \ - $(LWIPDIR)/netif/ppp/eui64.c \ - $(LWIPDIR)/netif/ppp/fsm.c \ - $(LWIPDIR)/netif/ppp/ipcp.c \ - $(LWIPDIR)/netif/ppp/ipv6cp.c \ - $(LWIPDIR)/netif/ppp/lcp.c \ - $(LWIPDIR)/netif/ppp/magic.c \ - $(LWIPDIR)/netif/ppp/mppe.c \ - $(LWIPDIR)/netif/ppp/multilink.c \ - $(LWIPDIR)/netif/ppp/ppp.c \ - $(LWIPDIR)/netif/ppp/pppapi.c \ - $(LWIPDIR)/netif/ppp/pppcrypt.c \ - $(LWIPDIR)/netif/ppp/pppoe.c \ - $(LWIPDIR)/netif/ppp/pppol2tp.c \ - $(LWIPDIR)/netif/ppp/pppos.c \ - $(LWIPDIR)/netif/ppp/upap.c \ - $(LWIPDIR)/netif/ppp/utils.c \ - $(LWIPDIR)/netif/ppp/vj.c \ - $(LWIPDIR)/netif/ppp/polarssl/arc4.c \ - $(LWIPDIR)/netif/ppp/polarssl/des.c \ - $(LWIPDIR)/netif/ppp/polarssl/md4.c \ - $(LWIPDIR)/netif/ppp/polarssl/md5.c \ - $(LWIPDIR)/netif/ppp/polarssl/sha1.c - -# LWIPNOAPPSFILES: All LWIP files without apps -LWIPNOAPPSFILES=$(COREFILES) \ - $(CORE4FILES) \ - $(CORE6FILES) \ - $(APIFILES) \ - $(NETIFFILES) \ - $(PPPFILES) \ - $(SIXLOWPAN) - -# SNMPFILES: SNMPv2c agent -SNMPFILES=$(LWIPDIR)/apps/snmp/snmp_asn1.c \ - $(LWIPDIR)/apps/snmp/snmp_core.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_icmp.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_interfaces.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_ip.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_snmp.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_system.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_tcp.c \ - $(LWIPDIR)/apps/snmp/snmp_mib2_udp.c \ - $(LWIPDIR)/apps/snmp/snmp_msg.c \ - $(LWIPDIR)/apps/snmp/snmpv3.c \ - $(LWIPDIR)/apps/snmp/snmp_netconn.c \ - $(LWIPDIR)/apps/snmp/snmp_pbuf_stream.c \ - $(LWIPDIR)/apps/snmp/snmp_raw.c \ - $(LWIPDIR)/apps/snmp/snmp_scalar.c \ - $(LWIPDIR)/apps/snmp/snmp_table.c \ - $(LWIPDIR)/apps/snmp/snmp_threadsync.c \ - $(LWIPDIR)/apps/snmp/snmp_traps.c \ - $(LWIPDIR)/apps/snmp/snmpv3_mbedtls.c \ - $(LWIPDIR)/apps/snmp/snmpv3_dummy.c - -# HTTPDFILES: HTTP server -HTTPDFILES=$(LWIPDIR)/apps/httpd/fs.c \ - $(LWIPDIR)/apps/httpd/httpd.c - -# LWIPERFFILES: IPERF server -LWIPERFFILES=$(LWIPDIR)/apps/lwiperf/lwiperf.c - -# SNTPFILES: SNTP client -SNTPFILES=$(LWIPDIR)/apps/sntp/sntp.c - -# MDNSFILES: MDNS responder -MDNSFILES=$(LWIPDIR)/apps/mdns/mdns.c - -# NETBIOSNSFILES: NetBIOS name server -NETBIOSNSFILES=$(LWIPDIR)/apps/netbiosns/netbiosns.c - -# TFTPFILES: TFTP server files -TFTPFILES=$(LWIPDIR)/apps/tftp/tftp_server.c - -# MQTTFILES: MQTT client files -MQTTFILES=$(LWIPDIR)/apps/mqtt/mqtt.c - -# LWIPAPPFILES: All LWIP APPs -LWIPAPPFILES=$(SNMPFILES) \ - $(HTTPDFILES) \ - $(LWIPERFFILES) \ - $(SNTPFILES) \ - $(MDNSFILES) \ - $(NETBIOSNSFILES) \ - $(TFTPFILES) \ - $(MQTTFILES) diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_lib.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_lib.c deleted file mode 100644 index c5a4b4f8b2ab9f8337b42b6dbd8cc4fff4288eb4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_lib.c +++ /dev/null @@ -1,1012 +0,0 @@ -/** - * @file - * Sequential API External module - * - * @defgroup netconn Netconn API - * @ingroup sequential_api - * Thread-safe, to be called from non-TCPIP threads only. - * TX/RX handling based on @ref netbuf (containing @ref pbuf) - * to avoid copying data around. - * - * @defgroup netconn_common Common functions - * @ingroup netconn - * For use with TCP and UDP - * - * @defgroup netconn_tcp TCP only - * @ingroup netconn - * TCP only functions - * - * @defgroup netconn_udp UDP only - * @ingroup netconn - * UDP only functions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - */ - -/* This is the part of the API that is linked with - the application */ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/api.h" -#include "lwip/memp.h" - -#include "lwip/ip.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/priv/api_msg.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/priv/tcpip_priv.h" - -#include - -#define API_MSG_VAR_REF(name) API_VAR_REF(name) -#define API_MSG_VAR_DECLARE(name) API_VAR_DECLARE(struct api_msg, name) -#define API_MSG_VAR_ALLOC(name) API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, ERR_MEM) -#define API_MSG_VAR_ALLOC_RETURN_NULL(name) API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, NULL) -#define API_MSG_VAR_FREE(name) API_VAR_FREE(MEMP_API_MSG, name) - -static err_t netconn_close_shutdown(struct netconn *conn, u8_t how); - -/** - * Call the lower part of a netconn_* function - * This function is then running in the thread context - * of tcpip_thread and has exclusive access to lwIP core code. - * - * @param fn function to call - * @param apimsg a struct containing the function to call and its parameters - * @return ERR_OK if the function was called, another err_t if not - */ -static err_t -netconn_apimsg(tcpip_callback_fn fn, struct api_msg *apimsg) -{ - err_t err; - -#ifdef LWIP_DEBUG - /* catch functions that don't set err */ - apimsg->err = ERR_VAL; -#endif /* LWIP_DEBUG */ - -#if LWIP_NETCONN_SEM_PER_THREAD - apimsg->op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - err = tcpip_send_msg_wait_sem(fn, apimsg, LWIP_API_MSG_SEM(apimsg)); - if (err == ERR_OK) { - return apimsg->err; - } - return err; -} - -/** - * Create a new netconn (of a specific type) that has a callback function. - * The corresponding pcb is also created. - * - * @param t the type of 'connection' to create (@see enum netconn_type) - * @param proto the IP protocol for RAW IP pcbs - * @param callback a function to call on status changes (RX available, TX'ed) - * @return a newly allocated struct netconn or - * NULL on memory error - */ -struct netconn* -netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback) -{ - struct netconn *conn; - API_MSG_VAR_DECLARE(msg); - API_MSG_VAR_ALLOC_RETURN_NULL(msg); - - conn = netconn_alloc(t, callback); - if (conn != NULL) { - err_t err; - - API_MSG_VAR_REF(msg).msg.n.proto = proto; - API_MSG_VAR_REF(msg).conn = conn; - err = netconn_apimsg(lwip_netconn_do_newconn, &API_MSG_VAR_REF(msg)); - if (err != ERR_OK) { - LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL); - LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox)); -#if LWIP_TCP - LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox)); -#endif /* LWIP_TCP */ -#if !LWIP_NETCONN_SEM_PER_THREAD - LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed)); - sys_sem_free(&conn->op_completed); -#endif /* !LWIP_NETCONN_SEM_PER_THREAD */ - sys_mbox_free(&conn->recvmbox); - memp_free(MEMP_NETCONN, conn); - API_MSG_VAR_FREE(msg); - return NULL; - } - } - API_MSG_VAR_FREE(msg); - return conn; -} - -/** - * @ingroup netconn_common - * Close a netconn 'connection' and free its resources. - * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate - * after this returns. - * - * @param conn the netconn to delete - * @return ERR_OK if the connection was deleted - */ -err_t -netconn_delete(struct netconn *conn) -{ - err_t err; - API_MSG_VAR_DECLARE(msg); - - /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ - if (conn == NULL) { - return ERR_OK; - } - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; -#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER - /* get the time we started, which is later compared to - sys_now() + conn->send_timeout */ - API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); -#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ -#if LWIP_TCP - API_MSG_VAR_REF(msg).msg.sd.polls_left = - ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; -#endif /* LWIP_TCP */ -#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - err = netconn_apimsg(lwip_netconn_do_delconn, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - if (err != ERR_OK) { - return err; - } - - netconn_free(conn); - - return ERR_OK; -} - -/** - * Get the local or remote IP address and port of a netconn. - * For RAW netconns, this returns the protocol instead of a port! - * - * @param conn the netconn to query - * @param addr a pointer to which to save the IP address - * @param port a pointer to which to save the port (or protocol for RAW) - * @param local 1 to get the local IP address, 0 to get the remote one - * @return ERR_CONN for invalid connections - * ERR_OK if the information was retrieved - */ -err_t -netconn_getaddr(struct netconn *conn, ip_addr_t *addr, u16_t *port, u8_t local) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;); - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.ad.local = local; -#if LWIP_MPU_COMPATIBLE - err = netconn_apimsg(lwip_netconn_do_getaddr, &API_MSG_VAR_REF(msg)); - *addr = msg->msg.ad.ipaddr; - *port = msg->msg.ad.port; -#else /* LWIP_MPU_COMPATIBLE */ - msg.msg.ad.ipaddr = addr; - msg.msg.ad.port = port; - err = netconn_apimsg(lwip_netconn_do_getaddr, &msg); -#endif /* LWIP_MPU_COMPATIBLE */ - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_common - * Bind a netconn to a specific local IP address and port. - * Binding one netconn twice might not always be checked correctly! - * - * @param conn the netconn to bind - * @param addr the local IP address to bind the netconn to - * (use IP4_ADDR_ANY/IP6_ADDR_ANY to bind to all addresses) - * @param port the local port to bind the netconn to (not used for RAW) - * @return ERR_OK if bound, any other err_t on failure - */ -err_t -netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;); - -#if LWIP_IPV4 - /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ - if (addr == NULL) { - addr = IP4_ADDR_ANY; - } -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV4 && LWIP_IPV6 - /* "Socket API like" dual-stack support: If IP to bind to is IP6_ADDR_ANY, - * and NETCONN_FLAG_IPV6_V6ONLY is 0, use IP_ANY_TYPE to bind - */ - if ((netconn_get_ipv6only(conn) == 0) && - ip_addr_cmp(addr, IP6_ADDR_ANY)) { - addr = IP_ANY_TYPE; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); - API_MSG_VAR_REF(msg).msg.bc.port = port; - err = netconn_apimsg(lwip_netconn_do_bind, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_common - * Connect a netconn to a specific remote IP address and port. - * - * @param conn the netconn to connect - * @param addr the remote IP address to connect to - * @param port the remote port to connect to (no used for RAW) - * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise - */ -err_t -netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;); - -#if LWIP_IPV4 - /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ - if (addr == NULL) { - addr = IP4_ADDR_ANY; - } -#endif /* LWIP_IPV4 */ - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); - API_MSG_VAR_REF(msg).msg.bc.port = port; - err = netconn_apimsg(lwip_netconn_do_connect, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_udp - * Disconnect a netconn from its current peer (only valid for UDP netconns). - * - * @param conn the netconn to disconnect - * @return See @ref err_t - */ -err_t -netconn_disconnect(struct netconn *conn) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;); - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; - err = netconn_apimsg(lwip_netconn_do_disconnect, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_tcp - * Set a TCP netconn into listen mode - * - * @param conn the tcp netconn to set to listen mode - * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1 - * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns - * don't return any error (yet?)) - */ -err_t -netconn_listen_with_backlog(struct netconn *conn, u8_t backlog) -{ -#if LWIP_TCP - API_MSG_VAR_DECLARE(msg); - err_t err; - - /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */ - LWIP_UNUSED_ARG(backlog); - - LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;); - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_REF(msg).msg.lb.backlog = backlog; -#endif /* TCP_LISTEN_BACKLOG */ - err = netconn_apimsg(lwip_netconn_do_listen, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -#else /* LWIP_TCP */ - LWIP_UNUSED_ARG(conn); - LWIP_UNUSED_ARG(backlog); - return ERR_ARG; -#endif /* LWIP_TCP */ -} - -/** - * @ingroup netconn_tcp - * Accept a new connection on a TCP listening netconn. - * - * @param conn the TCP listen netconn - * @param new_conn pointer where the new connection is stored - * @return ERR_OK if a new connection has been received or an error - * code otherwise - */ -err_t -netconn_accept(struct netconn *conn, struct netconn **new_conn) -{ -#if LWIP_TCP - void *accept_ptr; - struct netconn *newconn; -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_DECLARE(msg); -#endif /* TCP_LISTEN_BACKLOG */ - - LWIP_ERROR("netconn_accept: invalid pointer", (new_conn != NULL), return ERR_ARG;); - *new_conn = NULL; - LWIP_ERROR("netconn_accept: invalid conn", (conn != NULL), return ERR_ARG;); - - if (ERR_IS_FATAL(conn->last_err)) { - /* don't recv on fatal errors: this might block the application task - waiting on acceptmbox forever! */ - return conn->last_err; - } - if (!sys_mbox_valid(&conn->acceptmbox)) { - return ERR_CLSD; - } - -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_ALLOC(msg); -#endif /* TCP_LISTEN_BACKLOG */ - -#if LWIP_SO_RCVTIMEO - if (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_FREE(msg); -#endif /* TCP_LISTEN_BACKLOG */ - return ERR_TIMEOUT; - } -#else - sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); -#endif /* LWIP_SO_RCVTIMEO*/ - newconn = (struct netconn *)accept_ptr; - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); - - if (accept_ptr == &netconn_aborted) { - /* a connection has been aborted: out of pcbs or out of netconns during accept */ - /* @todo: set netconn error, but this would be fatal and thus block further accepts */ -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_FREE(msg); -#endif /* TCP_LISTEN_BACKLOG */ - return ERR_ABRT; - } - if (newconn == NULL) { - /* connection has been aborted */ - /* in this special case, we set the netconn error from application thread, as - on a ready-to-accept listening netconn, there should not be anything running - in tcpip_thread */ - NETCONN_SET_SAFE_ERR(conn, ERR_CLSD); -#if TCP_LISTEN_BACKLOG - API_MSG_VAR_FREE(msg); -#endif /* TCP_LISTEN_BACKLOG */ - return ERR_CLSD; - } -#if TCP_LISTEN_BACKLOG - /* Let the stack know that we have accepted the connection. */ - API_MSG_VAR_REF(msg).conn = newconn; - /* don't care for the return value of lwip_netconn_do_recv */ - netconn_apimsg(lwip_netconn_do_accepted, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); -#endif /* TCP_LISTEN_BACKLOG */ - - *new_conn = newconn; - /* don't set conn->last_err: it's only ERR_OK, anyway */ - return ERR_OK; -#else /* LWIP_TCP */ - LWIP_UNUSED_ARG(conn); - LWIP_UNUSED_ARG(new_conn); - return ERR_ARG; -#endif /* LWIP_TCP */ -} - -/** - * @ingroup netconn_common - * Receive data: actual implementation that doesn't care whether pbuf or netbuf - * is received - * - * @param conn the netconn from which to receive data - * @param new_buf pointer where a new pbuf/netbuf is stored when received data - * @return ERR_OK if data has been received, an error code otherwise (timeout, - * memory error or another error) - */ -static err_t -netconn_recv_data(struct netconn *conn, void **new_buf) -{ - void *buf = NULL; - u16_t len; -#if LWIP_TCP - API_MSG_VAR_DECLARE(msg); -#if LWIP_MPU_COMPATIBLE - msg = NULL; -#endif -#endif /* LWIP_TCP */ - - LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); - *new_buf = NULL; - LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); -#if LWIP_TCP -#if (LWIP_UDP || LWIP_RAW) - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) -#endif /* (LWIP_UDP || LWIP_RAW) */ - { - if (!sys_mbox_valid(&conn->recvmbox)) { - /* This happens when calling this function after receiving FIN */ - return sys_mbox_valid(&conn->acceptmbox) ? ERR_CONN : ERR_CLSD; - } - } -#endif /* LWIP_TCP */ - LWIP_ERROR("netconn_recv: invalid recvmbox", sys_mbox_valid(&conn->recvmbox), return ERR_CONN;); - - if (ERR_IS_FATAL(conn->last_err)) { - /* don't recv on fatal errors: this might block the application task - waiting on recvmbox forever! */ - /* @todo: this does not allow us to fetch data that has been put into recvmbox - before the fatal error occurred - is that a problem? */ - return conn->last_err; - } -#if LWIP_TCP -#if (LWIP_UDP || LWIP_RAW) - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) -#endif /* (LWIP_UDP || LWIP_RAW) */ - { - API_MSG_VAR_ALLOC(msg); - } -#endif /* LWIP_TCP */ - -#if LWIP_SO_RCVTIMEO - if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { -#if LWIP_TCP -#if (LWIP_UDP || LWIP_RAW) - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) -#endif /* (LWIP_UDP || LWIP_RAW) */ - { - API_MSG_VAR_FREE(msg); - } -#endif /* LWIP_TCP */ - return ERR_TIMEOUT; - } -#else - sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); -#endif /* LWIP_SO_RCVTIMEO*/ - -#if LWIP_TCP -#if (LWIP_UDP || LWIP_RAW) - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) -#endif /* (LWIP_UDP || LWIP_RAW) */ - { - /* Let the stack know that we have taken the data. */ - /* @todo: Speedup: Don't block and wait for the answer here - (to prevent multiple thread-switches). */ - API_MSG_VAR_REF(msg).conn = conn; - if (buf != NULL) { - API_MSG_VAR_REF(msg).msg.r.len = ((struct pbuf *)buf)->tot_len; - } else { - API_MSG_VAR_REF(msg).msg.r.len = 1; - } - - /* don't care for the return value of lwip_netconn_do_recv */ - netconn_apimsg(lwip_netconn_do_recv, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - /* If we are closed, we indicate that we no longer wish to use the socket */ - if (buf == NULL) { - API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); - if (conn->pcb.ip == NULL) { - /* race condition: RST during recv */ - return conn->last_err == ERR_OK ? ERR_RST : conn->last_err; - } - /* RX side is closed, so deallocate the recvmbox */ - netconn_close_shutdown(conn, NETCONN_SHUT_RD); - /* Don' store ERR_CLSD as conn->err since we are only half-closed */ - return ERR_CLSD; - } - len = ((struct pbuf *)buf)->tot_len; - } -#endif /* LWIP_TCP */ -#if LWIP_TCP && (LWIP_UDP || LWIP_RAW) - else -#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ -#if (LWIP_UDP || LWIP_RAW) - { - LWIP_ASSERT("buf != NULL", buf != NULL); - len = netbuf_len((struct netbuf*)buf); - } -#endif /* (LWIP_UDP || LWIP_RAW) */ - -#if LWIP_SO_RCVBUF - SYS_ARCH_DEC(conn->recv_avail, len); -#endif /* LWIP_SO_RCVBUF */ - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVMINUS, len); - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len)); - - *new_buf = buf; - /* don't set conn->last_err: it's only ERR_OK, anyway */ - return ERR_OK; -} - -/** - * @ingroup netconn_tcp - * Receive data (in form of a pbuf) from a TCP netconn - * - * @param conn the netconn from which to receive data - * @param new_buf pointer where a new pbuf is stored when received data - * @return ERR_OK if data has been received, an error code otherwise (timeout, - * memory error or another error) - * ERR_ARG if conn is not a TCP netconn - */ -err_t -netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf) -{ - LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL) && - NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); - - return netconn_recv_data(conn, (void **)new_buf); -} - -/** - * @ingroup netconn_common - * Receive data (in form of a netbuf containing a packet buffer) from a netconn - * - * @param conn the netconn from which to receive data - * @param new_buf pointer where a new netbuf is stored when received data - * @return ERR_OK if data has been received, an error code otherwise (timeout, - * memory error or another error) - */ -err_t -netconn_recv(struct netconn *conn, struct netbuf **new_buf) -{ -#if LWIP_TCP - struct netbuf *buf = NULL; - err_t err; -#endif /* LWIP_TCP */ - - LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); - *new_buf = NULL; - LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); - -#if LWIP_TCP -#if (LWIP_UDP || LWIP_RAW) - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) -#endif /* (LWIP_UDP || LWIP_RAW) */ - { - struct pbuf *p = NULL; - /* This is not a listening netconn, since recvmbox is set */ - - buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - return ERR_MEM; - } - - err = netconn_recv_data(conn, (void **)&p); - if (err != ERR_OK) { - memp_free(MEMP_NETBUF, buf); - return err; - } - LWIP_ASSERT("p != NULL", p != NULL); - - buf->p = p; - buf->ptr = p; - buf->port = 0; - ip_addr_set_zero(&buf->addr); - *new_buf = buf; - /* don't set conn->last_err: it's only ERR_OK, anyway */ - return ERR_OK; - } -#endif /* LWIP_TCP */ -#if LWIP_TCP && (LWIP_UDP || LWIP_RAW) - else -#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ - { -#if (LWIP_UDP || LWIP_RAW) - return netconn_recv_data(conn, (void **)new_buf); -#endif /* (LWIP_UDP || LWIP_RAW) */ - } -} - -/** - * @ingroup netconn_udp - * Send data (in form of a netbuf) to a specific remote IP address and port. - * Only to be used for UDP and RAW netconns (not TCP). - * - * @param conn the netconn over which to send data - * @param buf a netbuf containing the data to send - * @param addr the remote IP address to which to send the data - * @param port the remote port to which to send the data - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_sendto(struct netconn *conn, struct netbuf *buf, const ip_addr_t *addr, u16_t port) -{ - if (buf != NULL) { - ip_addr_set(&buf->addr, addr); - buf->port = port; - return netconn_send(conn, buf); - } - return ERR_VAL; -} - -/** - * @ingroup netconn_udp - * Send data over a UDP or RAW netconn (that is already connected). - * - * @param conn the UDP or RAW netconn over which to send data - * @param buf a netbuf containing the data to send - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_send(struct netconn *conn, struct netbuf *buf) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_send: invalid conn", (conn != NULL), return ERR_ARG;); - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len)); - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.b = buf; - err = netconn_apimsg(lwip_netconn_do_send, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_tcp - * Send data over a TCP netconn. - * - * @param conn the TCP netconn over which to send data - * @param dataptr pointer to the application buffer that contains the data to send - * @param size size of the application data to send - * @param apiflags combination of following flags : - * - NETCONN_COPY: data will be copied into memory belonging to the stack - * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent - * - NETCONN_DONTBLOCK: only write the data if all data can be written at once - * @param bytes_written pointer to a location that receives the number of written bytes - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, - u8_t apiflags, size_t *bytes_written) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - u8_t dontblock; - - LWIP_ERROR("netconn_write: invalid conn", (conn != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_write: invalid conn->type", (NETCONNTYPE_GROUP(conn->type)== NETCONN_TCP), return ERR_VAL;); - if (size == 0) { - return ERR_OK; - } - dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); -#if LWIP_SO_SNDTIMEO - if (conn->send_timeout != 0) { - dontblock = 1; - } -#endif /* LWIP_SO_SNDTIMEO */ - if (dontblock && !bytes_written) { - /* This implies netconn_write() cannot be used for non-blocking send, since - it has no way to return the number of bytes written. */ - return ERR_VAL; - } - - API_MSG_VAR_ALLOC(msg); - /* non-blocking write sends as much */ - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.w.dataptr = dataptr; - API_MSG_VAR_REF(msg).msg.w.apiflags = apiflags; - API_MSG_VAR_REF(msg).msg.w.len = size; -#if LWIP_SO_SNDTIMEO - if (conn->send_timeout != 0) { - /* get the time we started, which is later compared to - sys_now() + conn->send_timeout */ - API_MSG_VAR_REF(msg).msg.w.time_started = sys_now(); - } else { - API_MSG_VAR_REF(msg).msg.w.time_started = 0; - } -#endif /* LWIP_SO_SNDTIMEO */ - - /* For locking the core: this _can_ be delayed on low memory/low send buffer, - but if it is, this is done inside api_msg.c:do_write(), so we can use the - non-blocking version here. */ - err = netconn_apimsg(lwip_netconn_do_write, &API_MSG_VAR_REF(msg)); - if ((err == ERR_OK) && (bytes_written != NULL)) { - if (dontblock) { - /* nonblocking write: maybe the data has been sent partly */ - *bytes_written = API_MSG_VAR_REF(msg).msg.w.len; - } else { - /* blocking call succeeded: all data has been sent if it */ - *bytes_written = size; - } - } - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_tcp - * Close or shutdown a TCP netconn (doesn't delete it). - * - * @param conn the TCP netconn to close or shutdown - * @param how fully close or only shutdown one side? - * @return ERR_OK if the netconn was closed, any other err_t on error - */ -static err_t -netconn_close_shutdown(struct netconn *conn, u8_t how) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - LWIP_UNUSED_ARG(how); - - LWIP_ERROR("netconn_close: invalid conn", (conn != NULL), return ERR_ARG;); - - API_MSG_VAR_ALLOC(msg); - API_MSG_VAR_REF(msg).conn = conn; -#if LWIP_TCP - /* shutting down both ends is the same as closing */ - API_MSG_VAR_REF(msg).msg.sd.shut = how; -#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER - /* get the time we started, which is later compared to - sys_now() + conn->send_timeout */ - API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); -#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - API_MSG_VAR_REF(msg).msg.sd.polls_left = - ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; -#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ -#endif /* LWIP_TCP */ - err = netconn_apimsg(lwip_netconn_do_close, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} - -/** - * @ingroup netconn_tcp - * Close a TCP netconn (doesn't delete it). - * - * @param conn the TCP netconn to close - * @return ERR_OK if the netconn was closed, any other err_t on error - */ -err_t -netconn_close(struct netconn *conn) -{ - /* shutting down both ends is the same as closing */ - return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR); -} - -/** - * @ingroup netconn_tcp - * Shut down one or both sides of a TCP netconn (doesn't delete it). - * - * @param conn the TCP netconn to shut down - * @param shut_rx shut down the RX side (no more read possible after this) - * @param shut_tx shut down the TX side (no more write possible after this) - * @return ERR_OK if the netconn was closed, any other err_t on error - */ -err_t -netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx) -{ - return netconn_close_shutdown(conn, (shut_rx ? NETCONN_SHUT_RD : 0) | (shut_tx ? NETCONN_SHUT_WR : 0)); -} - -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) -/** - * @ingroup netconn_udp - * Join multicast groups for UDP netconns. - * - * @param conn the UDP netconn for which to change multicast addresses - * @param multiaddr IP address of the multicast group to join or leave - * @param netif_addr the IP address of the network interface on which to send - * the igmp message - * @param join_or_leave flag whether to send a join- or leave-message - * @return ERR_OK if the action was taken, any err_t on error - */ -err_t -netconn_join_leave_group(struct netconn *conn, - const ip_addr_t *multiaddr, - const ip_addr_t *netif_addr, - enum netconn_igmp join_or_leave) -{ - API_MSG_VAR_DECLARE(msg); - err_t err; - - LWIP_ERROR("netconn_join_leave_group: invalid conn", (conn != NULL), return ERR_ARG;); - - API_MSG_VAR_ALLOC(msg); - -#if LWIP_IPV4 - /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ - if (multiaddr == NULL) { - multiaddr = IP4_ADDR_ANY; - } - if (netif_addr == NULL) { - netif_addr = IP4_ADDR_ANY; - } -#endif /* LWIP_IPV4 */ - - API_MSG_VAR_REF(msg).conn = conn; - API_MSG_VAR_REF(msg).msg.jl.multiaddr = API_MSG_VAR_REF(multiaddr); - API_MSG_VAR_REF(msg).msg.jl.netif_addr = API_MSG_VAR_REF(netif_addr); - API_MSG_VAR_REF(msg).msg.jl.join_or_leave = join_or_leave; - err = netconn_apimsg(lwip_netconn_do_join_leave_group, &API_MSG_VAR_REF(msg)); - API_MSG_VAR_FREE(msg); - - return err; -} -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - -#if LWIP_DNS -/** - * @ingroup netconn_common - * Execute a DNS query, only one IP address is returned - * - * @param name a string representation of the DNS host name to query - * @param addr a preallocated ip_addr_t where to store the resolved IP address - * @param dns_addrtype IP address type (IPv4 / IPv6) - * @return ERR_OK: resolving succeeded - * ERR_MEM: memory error, try again later - * ERR_ARG: dns client not initialized or invalid hostname - * ERR_VAL: dns server response was invalid - */ -#if LWIP_IPV4 && LWIP_IPV6 -err_t -netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype) -#else -err_t -netconn_gethostbyname(const char *name, ip_addr_t *addr) -#endif -{ - API_VAR_DECLARE(struct dns_api_msg, msg); -#if !LWIP_MPU_COMPATIBLE - sys_sem_t sem; -#endif /* LWIP_MPU_COMPATIBLE */ - err_t err; - err_t cberr; - - LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;); -#if LWIP_MPU_COMPATIBLE - if (strlen(name) >= DNS_MAX_NAME_LENGTH) { - return ERR_ARG; - } -#endif - - API_VAR_ALLOC(struct dns_api_msg, MEMP_DNS_API_MSG, msg, ERR_MEM); -#if LWIP_MPU_COMPATIBLE - strncpy(API_VAR_REF(msg).name, name, DNS_MAX_NAME_LENGTH-1); - API_VAR_REF(msg).name[DNS_MAX_NAME_LENGTH-1] = 0; -#else /* LWIP_MPU_COMPATIBLE */ - msg.err = &err; - msg.sem = &sem; - API_VAR_REF(msg).addr = API_VAR_REF(addr); - API_VAR_REF(msg).name = name; -#endif /* LWIP_MPU_COMPATIBLE */ - -#if LWIP_IPV4 && LWIP_IPV6 - API_VAR_REF(msg).dns_addrtype = dns_addrtype; -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#if LWIP_NETCONN_SEM_PER_THREAD - API_VAR_REF(msg).sem = LWIP_NETCONN_THREAD_SEM_GET(); -#else /* LWIP_NETCONN_SEM_PER_THREAD*/ - err = sys_sem_new(API_EXPR_REF(API_VAR_REF(msg).sem), 0); - if (err != ERR_OK) { - API_VAR_FREE(MEMP_DNS_API_MSG, msg); - return err; - } -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - cberr = tcpip_callback(lwip_netconn_do_gethostbyname, &API_VAR_REF(msg)); - if (cberr != ERR_OK) { -#if !LWIP_NETCONN_SEM_PER_THREAD - sys_sem_free(API_EXPR_REF(API_VAR_REF(msg).sem)); -#endif /* !LWIP_NETCONN_SEM_PER_THREAD */ - API_VAR_FREE(MEMP_DNS_API_MSG, msg); - return cberr; - } - sys_sem_wait(API_EXPR_REF_SEM(API_VAR_REF(msg).sem)); -#if !LWIP_NETCONN_SEM_PER_THREAD - sys_sem_free(API_EXPR_REF(API_VAR_REF(msg).sem)); -#endif /* !LWIP_NETCONN_SEM_PER_THREAD */ - -#if LWIP_MPU_COMPATIBLE - *addr = msg->addr; - err = msg->err; -#endif /* LWIP_MPU_COMPATIBLE */ - - API_VAR_FREE(MEMP_DNS_API_MSG, msg); - return err; -} -#endif /* LWIP_DNS*/ - -#if LWIP_NETCONN_SEM_PER_THREAD -void -netconn_thread_init(void) -{ - sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET(); - if ((sem == NULL) || !sys_sem_valid(sem)) { - /* call alloc only once */ - LWIP_NETCONN_THREAD_SEM_ALLOC(); - LWIP_ASSERT("LWIP_NETCONN_THREAD_SEM_ALLOC() failed", sys_sem_valid(LWIP_NETCONN_THREAD_SEM_GET())); - } -} - -void -netconn_thread_cleanup(void) -{ - sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET(); - if ((sem != NULL) && sys_sem_valid(sem)) { - /* call free only once */ - LWIP_NETCONN_THREAD_SEM_FREE(); - } -} -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - -#endif /* LWIP_NETCONN */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_msg.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_msg.c deleted file mode 100644 index dd99c1e01b8de863a14df84736844225d39f4ccc..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/api_msg.c +++ /dev/null @@ -1,1947 +0,0 @@ -/** - * @file - * Sequential API Internal module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/priv/api_msg.h" - -#include "lwip/ip.h" -#include "lwip/ip_addr.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/raw.h" - -#include "lwip/memp.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" -#include "lwip/mld6.h" -#include "lwip/priv/tcpip_priv.h" - -#include - -/* netconns are polled once per second (e.g. continue write on memory error) */ -#define NETCONN_TCP_POLL_INTERVAL 2 - -#define SET_NONBLOCKING_CONNECT(conn, val) do { if (val) { \ - (conn)->flags |= NETCONN_FLAG_IN_NONBLOCKING_CONNECT; \ -} else { \ - (conn)->flags &= ~ NETCONN_FLAG_IN_NONBLOCKING_CONNECT; }} while(0) -#define IN_NONBLOCKING_CONNECT(conn) (((conn)->flags & NETCONN_FLAG_IN_NONBLOCKING_CONNECT) != 0) - -/* forward declarations */ -#if LWIP_TCP -#if LWIP_TCPIP_CORE_LOCKING -#define WRITE_DELAYED , 1 -#define WRITE_DELAYED_PARAM , u8_t delayed -#else /* LWIP_TCPIP_CORE_LOCKING */ -#define WRITE_DELAYED -#define WRITE_DELAYED_PARAM -#endif /* LWIP_TCPIP_CORE_LOCKING */ -static err_t lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM); -static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM); -#endif - -#if LWIP_TCPIP_CORE_LOCKING -#define TCPIP_APIMSG_ACK(m) NETCONN_SET_SAFE_ERR((m)->conn, (m)->err) -#else /* LWIP_TCPIP_CORE_LOCKING */ -#define TCPIP_APIMSG_ACK(m) do { NETCONN_SET_SAFE_ERR((m)->conn, (m)->err); sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0) -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -#if LWIP_TCP -u8_t netconn_aborted; -#endif /* LWIP_TCP */ - -#if LWIP_RAW -/** - * Receive callback function for RAW netconns. - * Doesn't 'eat' the packet, only copies it and sends it to - * conn->recvmbox - * - * @see raw.h (struct raw_pcb.recv) for parameters and return value - */ -static u8_t -recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, - const ip_addr_t *addr) -{ - struct pbuf *q; - struct netbuf *buf; - struct netconn *conn; - - LWIP_UNUSED_ARG(addr); - conn = (struct netconn *)arg; - - if ((conn != NULL) && sys_mbox_valid(&conn->recvmbox)) { -#if LWIP_SO_RCVBUF - int recv_avail; - SYS_ARCH_GET(conn->recv_avail, recv_avail); - if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) { - return 0; - } -#endif /* LWIP_SO_RCVBUF */ - /* copy the whole packet into new pbufs */ - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if (q != NULL) { - if (pbuf_copy(q, p) != ERR_OK) { - pbuf_free(q); - q = NULL; - } - } - - if (q != NULL) { - u16_t len; - buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(q); - return 0; - } - - buf->p = q; - buf->ptr = q; - ip_addr_copy(buf->addr, *ip_current_src_addr()); - buf->port = pcb->protocol; - - len = q->tot_len; - if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { - netbuf_delete(buf); - return 0; - } else { -#if LWIP_SO_RCVBUF - SYS_ARCH_INC(conn->recv_avail, len); -#endif /* LWIP_SO_RCVBUF */ - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); - } - } - } - - return 0; /* do not eat the packet */ -} -#endif /* LWIP_RAW*/ - -#if LWIP_UDP -/** - * Receive callback function for UDP netconns. - * Posts the packet to conn->recvmbox or deletes it on memory error. - * - * @see udp.h (struct udp_pcb.recv) for parameters - */ -static void -recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *addr, u16_t port) -{ - struct netbuf *buf; - struct netconn *conn; - u16_t len; -#if LWIP_SO_RCVBUF - int recv_avail; -#endif /* LWIP_SO_RCVBUF */ - - LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ - LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); - LWIP_ASSERT("recv_udp must have an argument", arg != NULL); - conn = (struct netconn *)arg; - LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); - -#if LWIP_SO_RCVBUF - SYS_ARCH_GET(conn->recv_avail, recv_avail); - if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox) || - ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { -#else /* LWIP_SO_RCVBUF */ - if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox)) { -#endif /* LWIP_SO_RCVBUF */ - pbuf_free(p); - return; - } - - buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(p); - return; - } else { - buf->p = p; - buf->ptr = p; - ip_addr_set(&buf->addr, addr); - buf->port = port; -#if LWIP_NETBUF_RECVINFO - { - /* get the UDP header - always in the first pbuf, ensured by udp_input */ - const struct udp_hdr* udphdr = (const struct udp_hdr*)ip_next_header_ptr(); -#if LWIP_CHECKSUM_ON_COPY - buf->flags = NETBUF_FLAG_DESTADDR; -#endif /* LWIP_CHECKSUM_ON_COPY */ - ip_addr_set(&buf->toaddr, ip_current_dest_addr()); - buf->toport_chksum = udphdr->dest; - } -#endif /* LWIP_NETBUF_RECVINFO */ - } - - len = p->tot_len; - if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { - netbuf_delete(buf); - return; - } else { -#if LWIP_SO_RCVBUF - SYS_ARCH_INC(conn->recv_avail, len); -#endif /* LWIP_SO_RCVBUF */ - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); - } -} -#endif /* LWIP_UDP */ - -#if LWIP_TCP -/** - * Receive callback function for TCP netconns. - * Posts the packet to conn->recvmbox, but doesn't delete it on errors. - * - * @see tcp.h (struct tcp_pcb.recv) for parameters and return value - */ -static err_t -recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct netconn *conn; - u16_t len; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); - LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); - conn = (struct netconn *)arg; - - if (conn == NULL) { - return ERR_VAL; - } - LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); - - if (!sys_mbox_valid(&conn->recvmbox)) { - /* recvmbox already deleted */ - if (p != NULL) { - tcp_recved(pcb, p->tot_len); - pbuf_free(p); - } - return ERR_OK; - } - /* Unlike for UDP or RAW pcbs, don't check for available space - using recv_avail since that could break the connection - (data is already ACKed) */ - - /* don't overwrite fatal errors! */ - if (err != ERR_OK) { - NETCONN_SET_SAFE_ERR(conn, err); - } - - if (p != NULL) { - len = p->tot_len; - } else { - len = 0; - } - - if (sys_mbox_trypost(&conn->recvmbox, p) != ERR_OK) { - /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ - return ERR_MEM; - } else { -#if LWIP_SO_RCVBUF - SYS_ARCH_INC(conn->recv_avail, len); -#endif /* LWIP_SO_RCVBUF */ - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); - } - - return ERR_OK; -} - -/** - * Poll callback function for TCP netconns. - * Wakes up an application thread that waits for a connection to close - * or data to be sent. The application thread then takes the - * appropriate action to go on. - * - * Signals the conn->sem. - * netconn_close waits for conn->sem if closing failed. - * - * @see tcp.h (struct tcp_pcb.poll) for parameters and return value - */ -static err_t -poll_tcp(void *arg, struct tcp_pcb *pcb) -{ - struct netconn *conn = (struct netconn *)arg; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - if (conn->state == NETCONN_WRITE) { - lwip_netconn_do_writemore(conn WRITE_DELAYED); - } else if (conn->state == NETCONN_CLOSE) { -#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER - if (conn->current_msg && conn->current_msg->msg.sd.polls_left) { - conn->current_msg->msg.sd.polls_left--; - } -#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */ - lwip_netconn_do_close_internal(conn WRITE_DELAYED); - } - /* @todo: implement connect timeout here? */ - - /* Did a nonblocking write fail before? Then check available write-space. */ - if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { - /* If the queued byte- or pbuf-count drops below the configured low-water limit, - let select mark this pcb as writable again. */ - if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && - (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { - conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; - API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); - } - } - - return ERR_OK; -} - -/** - * Sent callback function for TCP netconns. - * Signals the conn->sem and calls API_EVENT. - * netconn_write waits for conn->sem if send buffer is low. - * - * @see tcp.h (struct tcp_pcb.sent) for parameters and return value - */ -static err_t -sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct netconn *conn = (struct netconn *)arg; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - if (conn) { - if (conn->state == NETCONN_WRITE) { - lwip_netconn_do_writemore(conn WRITE_DELAYED); - } else if (conn->state == NETCONN_CLOSE) { - lwip_netconn_do_close_internal(conn WRITE_DELAYED); - } - - /* If the queued byte- or pbuf-count drops below the configured low-water limit, - let select mark this pcb as writable again. */ - if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && - (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { - conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; - API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); - } - } - - return ERR_OK; -} - -/** - * Error callback function for TCP netconns. - * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. - * The application thread has then to decide what to do. - * - * @see tcp.h (struct tcp_pcb.err) for parameters - */ -static void -err_tcp(void *arg, err_t err) -{ - struct netconn *conn; - enum netconn_state old_state; - - conn = (struct netconn *)arg; - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - conn->pcb.tcp = NULL; - - /* reset conn->state now before waking up other threads */ - old_state = conn->state; - conn->state = NETCONN_NONE; - - if (old_state == NETCONN_CLOSE) { - /* RST during close: let close return success & dealloc the netconn */ - err = ERR_OK; - NETCONN_SET_SAFE_ERR(conn, ERR_OK); - } else { - /* no check since this is always fatal! */ - SYS_ARCH_SET(conn->last_err, err); - } - - /* @todo: the type of NETCONN_EVT created should depend on 'old_state' */ - - /* Notify the user layer about a connection error. Used to signal select. */ - API_EVENT(conn, NETCONN_EVT_ERROR, 0); - /* Try to release selects pending on 'read' or 'write', too. - They will get an error if they actually try to read or write. */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); - - /* pass NULL-message to recvmbox to wake up pending recv */ - if (sys_mbox_valid(&conn->recvmbox)) { - /* use trypost to prevent deadlock */ - sys_mbox_trypost(&conn->recvmbox, NULL); - } - /* pass NULL-message to acceptmbox to wake up pending accept */ - if (sys_mbox_valid(&conn->acceptmbox)) { - /* use trypost to preven deadlock */ - sys_mbox_trypost(&conn->acceptmbox, NULL); - } - - if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || - (old_state == NETCONN_CONNECT)) { - /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary - since the pcb has already been deleted! */ - int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); - SET_NONBLOCKING_CONNECT(conn, 0); - - if (!was_nonblocking_connect) { - sys_sem_t* op_completed_sem; - /* set error return code */ - LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); - conn->current_msg->err = err; - op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); - LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem)); - conn->current_msg = NULL; - /* wake up the waiting task */ - NETCONN_SET_SAFE_ERR(conn, err); - sys_sem_signal(op_completed_sem); - } - } else { - LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); - } -} - -/** - * Setup a tcp_pcb with the correct callback function pointers - * and their arguments. - * - * @param conn the TCP netconn to setup - */ -static void -setup_tcp(struct netconn *conn) -{ - struct tcp_pcb *pcb; - - pcb = conn->pcb.tcp; - tcp_arg(pcb, conn); - tcp_recv(pcb, recv_tcp); - tcp_sent(pcb, sent_tcp); - tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL); - tcp_err(pcb, err_tcp); -} - -/** - * Accept callback function for TCP netconns. - * Allocates a new netconn and posts that to conn->acceptmbox. - * - * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value - */ -static err_t -accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) -{ - struct netconn *newconn; - struct netconn *conn = (struct netconn *)arg; - - LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->tate: %s\n", tcp_debug_state_str(newpcb->state))); - - if (conn == NULL) { - return ERR_VAL; - } - if (!sys_mbox_valid(&conn->acceptmbox)) { - LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); - return ERR_VAL; - } - - if (newpcb == NULL) { - /* out-of-pcbs during connect: pass on this error to the application */ - if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - } - return ERR_VAL; - } - - /* We have to set the callback here even though - * the new socket is unknown. newconn->socket is marked as -1. */ - newconn = netconn_alloc(conn->type, conn->callback); - if (newconn == NULL) { - /* outof netconns: pass on this error to the application */ - if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - } - return ERR_MEM; - } - newconn->pcb.tcp = newpcb; - setup_tcp(newconn); - /* no protection: when creating the pcb, the netconn is not yet known - to the application thread */ - newconn->last_err = err; - - /* handle backlog counter */ - tcp_backlog_delayed(newpcb); - - if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) { - /* When returning != ERR_OK, the pcb is aborted in tcp_process(), - so do nothing here! */ - /* remove all references to this netconn from the pcb */ - struct tcp_pcb* pcb = newconn->pcb.tcp; - tcp_arg(pcb, NULL); - tcp_recv(pcb, NULL); - tcp_sent(pcb, NULL); - tcp_poll(pcb, NULL, 0); - tcp_err(pcb, NULL); - /* remove reference from to the pcb from this netconn */ - newconn->pcb.tcp = NULL; - /* no need to drain since we know the recvmbox is empty. */ - sys_mbox_free(&newconn->recvmbox); - sys_mbox_set_invalid(&newconn->recvmbox); - netconn_free(newconn); - return ERR_MEM; - } else { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - } - - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Create a new pcb of a specific type. - * Called from lwip_netconn_do_newconn(). - * - * @param msg the api_msg_msg describing the connection type - */ -static void -pcb_new(struct api_msg *msg) -{ - enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4; - - LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); - -#if LWIP_IPV6 && LWIP_IPV4 - /* IPv6: Dual-stack by default, unless netconn_set_ipv6only() is called */ - if(NETCONNTYPE_ISIPV6(netconn_type(msg->conn))) { - iptype = IPADDR_TYPE_ANY; - } -#endif - - /* Allocate a PCB for this connection */ - switch(NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new_ip_type(iptype, msg->msg.n.proto); - if (msg->conn->pcb.raw != NULL) { -#if LWIP_IPV6 - /* ICMPv6 packets should always have checksum calculated by the stack as per RFC 3542 chapter 3.1 */ - if (NETCONNTYPE_ISIPV6(msg->conn->type) && msg->conn->pcb.raw->protocol == IP6_NEXTH_ICMP6) { - msg->conn->pcb.raw->chksum_reqd = 1; - msg->conn->pcb.raw->chksum_offset = 2; - } -#endif /* LWIP_IPV6 */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - } - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new_ip_type(iptype); - if (msg->conn->pcb.udp != NULL) { -#if LWIP_UDPLITE - if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) { - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - } -#endif /* LWIP_UDPLITE */ - if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) { - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - } - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new_ip_type(iptype); - if (msg->conn->pcb.tcp != NULL) { - setup_tcp(msg->conn); - } - break; -#endif /* LWIP_TCP */ - default: - /* Unsupported netconn type, e.g. protocol disabled */ - msg->err = ERR_VAL; - return; - } - if (msg->conn->pcb.ip == NULL) { - msg->err = ERR_MEM; - } -} - -/** - * Create a new pcb of a specific type inside a netconn. - * Called from netconn_new_with_proto_and_callback. - * - * @param m the api_msg_msg describing the connection type - */ -void -lwip_netconn_do_newconn(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - msg->err = ERR_OK; - if (msg->conn->pcb.tcp == NULL) { - pcb_new(msg); - } - /* Else? This "new" connection already has a PCB allocated. */ - /* Is this an error condition? Should it be deleted? */ - /* We currently just are happy and return. */ - - TCPIP_APIMSG_ACK(msg); -} - -/** - * Create a new netconn (of a specific type) that has a callback function. - * The corresponding pcb is NOT created! - * - * @param t the type of 'connection' to create (@see enum netconn_type) - * @param callback a function to call on status changes (RX available, TX'ed) - * @return a newly allocated struct netconn or - * NULL on memory error - */ -struct netconn* -netconn_alloc(enum netconn_type t, netconn_callback callback) -{ - struct netconn *conn; - int size; - - conn = (struct netconn *)memp_malloc(MEMP_NETCONN); - if (conn == NULL) { - return NULL; - } - - conn->last_err = ERR_OK; - conn->type = t; - conn->pcb.tcp = NULL; - - /* If all sizes are the same, every compiler should optimize this switch to nothing */ - switch(NETCONNTYPE_GROUP(t)) { -#if LWIP_RAW - case NETCONN_RAW: - size = DEFAULT_RAW_RECVMBOX_SIZE; - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - size = DEFAULT_UDP_RECVMBOX_SIZE; - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - size = DEFAULT_TCP_RECVMBOX_SIZE; - break; -#endif /* LWIP_TCP */ - default: - LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); - goto free_and_return; - } - - if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { - goto free_and_return; - } -#if !LWIP_NETCONN_SEM_PER_THREAD - if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { - sys_mbox_free(&conn->recvmbox); - goto free_and_return; - } -#endif - -#if LWIP_TCP - sys_mbox_set_invalid(&conn->acceptmbox); -#endif - conn->state = NETCONN_NONE; -#if LWIP_SOCKET - /* initialize socket to -1 since 0 is a valid socket */ - conn->socket = -1; -#endif /* LWIP_SOCKET */ - conn->callback = callback; -#if LWIP_TCP - conn->current_msg = NULL; - conn->write_offset = 0; -#endif /* LWIP_TCP */ -#if LWIP_SO_SNDTIMEO - conn->send_timeout = 0; -#endif /* LWIP_SO_SNDTIMEO */ -#if LWIP_SO_RCVTIMEO - conn->recv_timeout = 0; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; - conn->recv_avail = 0; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_SO_LINGER - conn->linger = -1; -#endif /* LWIP_SO_LINGER */ - conn->flags = 0; - return conn; -free_and_return: - memp_free(MEMP_NETCONN, conn); - return NULL; -} - -/** - * Delete a netconn and all its resources. - * The pcb is NOT freed (since we might not be in the right thread context do this). - * - * @param conn the netconn to free - */ -void -netconn_free(struct netconn *conn) -{ - LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); - LWIP_ASSERT("recvmbox must be deallocated before calling this function", - !sys_mbox_valid(&conn->recvmbox)); -#if LWIP_TCP - LWIP_ASSERT("acceptmbox must be deallocated before calling this function", - !sys_mbox_valid(&conn->acceptmbox)); -#endif /* LWIP_TCP */ - -#if !LWIP_NETCONN_SEM_PER_THREAD - sys_sem_free(&conn->op_completed); - sys_sem_set_invalid(&conn->op_completed); -#endif - - memp_free(MEMP_NETCONN, conn); -} - -/** - * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in - * these mboxes - * - * @param conn the netconn to free - * @bytes_drained bytes drained from recvmbox - * @accepts_drained pending connections drained from acceptmbox - */ -static void -netconn_drain(struct netconn *conn) -{ - void *mem; -#if LWIP_TCP - struct pbuf *p; -#endif /* LWIP_TCP */ - - /* This runs in tcpip_thread, so we don't need to lock against rx packets */ - - /* Delete and drain the recvmbox. */ - if (sys_mbox_valid(&conn->recvmbox)) { - while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { -#if LWIP_TCP - if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) { - if (mem != NULL) { - p = (struct pbuf*)mem; - /* pcb might be set to NULL already by err_tcp() */ - if (conn->pcb.tcp != NULL) { - tcp_recved(conn->pcb.tcp, p->tot_len); - } - pbuf_free(p); - } - } else -#endif /* LWIP_TCP */ - { - netbuf_delete((struct netbuf *)mem); - } - } - sys_mbox_free(&conn->recvmbox); - sys_mbox_set_invalid(&conn->recvmbox); - } - - /* Delete and drain the acceptmbox. */ -#if LWIP_TCP - if (sys_mbox_valid(&conn->acceptmbox)) { - while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { - if (mem != &netconn_aborted) { - struct netconn *newconn = (struct netconn *)mem; - /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ - /* pcb might be set to NULL already by err_tcp() */ - /* drain recvmbox */ - netconn_drain(newconn); - if (newconn->pcb.tcp != NULL) { - tcp_abort(newconn->pcb.tcp); - newconn->pcb.tcp = NULL; - } - netconn_free(newconn); - } - } - sys_mbox_free(&conn->acceptmbox); - sys_mbox_set_invalid(&conn->acceptmbox); - } -#endif /* LWIP_TCP */ -} - -#if LWIP_TCP -/** - * Internal helper function to close a TCP netconn: since this sometimes - * doesn't work at the first attempt, this function is called from multiple - * places. - * - * @param conn the TCP netconn to close - */ -static err_t -lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM) -{ - err_t err; - u8_t shut, shut_rx, shut_tx, close; - u8_t close_finished = 0; - struct tcp_pcb* tpcb; -#if LWIP_SO_LINGER - u8_t linger_wait_required = 0; -#endif /* LWIP_SO_LINGER */ - - LWIP_ASSERT("invalid conn", (conn != NULL)); - LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)); - LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); - LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); - LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); - - tpcb = conn->pcb.tcp; - shut = conn->current_msg->msg.sd.shut; - shut_rx = shut & NETCONN_SHUT_RD; - shut_tx = shut & NETCONN_SHUT_WR; - /* shutting down both ends is the same as closing - (also if RD or WR side was shut down before already) */ - if (shut == NETCONN_SHUT_RDWR) { - close = 1; - } else if (shut_rx && - ((tpcb->state == FIN_WAIT_1) || - (tpcb->state == FIN_WAIT_2) || - (tpcb->state == CLOSING))) { - close = 1; - } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) { - close = 1; - } else { - close = 0; - } - - /* Set back some callback pointers */ - if (close) { - tcp_arg(tpcb, NULL); - } - if (tpcb->state == LISTEN) { - tcp_accept(tpcb, NULL); - } else { - /* some callbacks have to be reset if tcp_close is not successful */ - if (shut_rx) { - tcp_recv(tpcb, NULL); - tcp_accept(tpcb, NULL); - } - if (shut_tx) { - tcp_sent(tpcb, NULL); - } - if (close) { - tcp_poll(tpcb, NULL, 0); - tcp_err(tpcb, NULL); - } - } - /* Try to close the connection */ - if (close) { -#if LWIP_SO_LINGER - /* check linger possibilites before calling tcp_close */ - err = ERR_OK; - /* linger enabled/required at all? (i.e. is there untransmitted data left?) */ - if ((conn->linger >= 0) && (conn->pcb.tcp->unsent || conn->pcb.tcp->unacked)) { - if ((conn->linger == 0)) { - /* data left but linger prevents waiting */ - tcp_abort(tpcb); - tpcb = NULL; - } else if (conn->linger > 0) { - /* data left and linger says we should wait */ - if (netconn_is_nonblocking(conn)) { - /* data left on a nonblocking netconn -> cannot linger */ - err = ERR_WOULDBLOCK; - } else if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= - (conn->linger * 1000)) { - /* data left but linger timeout has expired (this happens on further - calls to this function through poll_tcp */ - tcp_abort(tpcb); - tpcb = NULL; - } else { - /* data left -> need to wait for ACK after successful close */ - linger_wait_required = 1; - } - } - } - if ((err == ERR_OK) && (tpcb != NULL)) -#endif /* LWIP_SO_LINGER */ - { - err = tcp_close(tpcb); - } - } else { - err = tcp_shutdown(tpcb, shut_rx, shut_tx); - } - if (err == ERR_OK) { - close_finished = 1; -#if LWIP_SO_LINGER - if (linger_wait_required) { - /* wait for ACK of all unsent/unacked data by just getting called again */ - close_finished = 0; - err = ERR_INPROGRESS; - } -#endif /* LWIP_SO_LINGER */ - } else { - if (err == ERR_MEM) { - /* Closing failed because of memory shortage, try again later. Even for - nonblocking netconns, we have to wait since no standard socket application - is prepared for close failing because of resource shortage. - Check the timeout: this is kind of an lwip addition to the standard sockets: - we wait for some time when failing to allocate a segment for the FIN */ -#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER - s32_t close_timeout = LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT; -#if LWIP_SO_SNDTIMEO - if (conn->send_timeout > 0) { - close_timeout = conn->send_timeout; - } -#endif /* LWIP_SO_SNDTIMEO */ -#if LWIP_SO_LINGER - if (conn->linger >= 0) { - /* use linger timeout (seconds) */ - close_timeout = conn->linger * 1000U; - } -#endif - if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) { -#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - if (conn->current_msg->msg.sd.polls_left == 0) { -#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - close_finished = 1; - if (close) { - /* in this case, we want to RST the connection */ - tcp_abort(tpcb); - err = ERR_OK; - } - } - } else { - /* Closing failed for a non-memory error: give up */ - close_finished = 1; - } - } - if (close_finished) { - /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */ - sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); - conn->current_msg->err = err; - conn->current_msg = NULL; - conn->state = NETCONN_NONE; - if (err == ERR_OK) { - if (close) { - /* Set back some callback pointers as conn is going away */ - conn->pcb.tcp = NULL; - /* Trigger select() in socket layer. Make sure everybody notices activity - on the connection, error first! */ - API_EVENT(conn, NETCONN_EVT_ERROR, 0); - } - if (shut_rx) { - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - } - if (shut_tx) { - API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); - } - } - NETCONN_SET_SAFE_ERR(conn, err); -#if LWIP_TCPIP_CORE_LOCKING - if (delayed) -#endif - { - /* wake up the application task */ - sys_sem_signal(op_completed_sem); - } - return ERR_OK; - } - if (!close_finished) { - /* Closing failed and we want to wait: restore some of the callbacks */ - /* Closing of listen pcb will never fail! */ - LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN)); - if (shut_tx) { - tcp_sent(tpcb, sent_tcp); - } - /* when waiting for close, set up poll interval to 500ms */ - tcp_poll(tpcb, poll_tcp, 1); - tcp_err(tpcb, err_tcp); - tcp_arg(tpcb, conn); - /* don't restore recv callback: we don't want to receive any more data */ - } - /* If closing didn't succeed, we get called again either - from poll_tcp or from sent_tcp */ - LWIP_ASSERT("err != ERR_OK", err != ERR_OK); - return err; -} -#endif /* LWIP_TCP */ - -/** - * Delete the pcb inside a netconn. - * Called from netconn_delete. - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_delconn(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - enum netconn_state state = msg->conn->state; - LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */ - (state == NETCONN_NONE) || (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP)); -#if LWIP_NETCONN_FULLDUPLEX - /* In full duplex mode, blocking write/connect is aborted with ERR_CLSD */ - if (state != NETCONN_NONE) { - if ((state == NETCONN_WRITE) || - ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { - /* close requested, abort running write/connect */ - sys_sem_t* op_completed_sem; - LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); - op_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); - msg->conn->current_msg->err = ERR_CLSD; - msg->conn->current_msg = NULL; - msg->conn->write_offset = 0; - msg->conn->state = NETCONN_NONE; - NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); - sys_sem_signal(op_completed_sem); - } - } -#else /* LWIP_NETCONN_FULLDUPLEX */ - if (((state != NETCONN_NONE) && - (state != NETCONN_LISTEN) && - (state != NETCONN_CONNECT)) || - ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { - /* This means either a blocking write or blocking connect is running - (nonblocking write returns and sets state to NONE) */ - msg->err = ERR_INPROGRESS; - } else -#endif /* LWIP_NETCONN_FULLDUPLEX */ - { - LWIP_ASSERT("blocking connect in progress", - (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); - msg->err = ERR_OK; - /* Drain and delete mboxes */ - netconn_drain(msg->conn); - - if (msg->conn->pcb.tcp != NULL) { - - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - raw_remove(msg->conn->pcb.raw); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->pcb.udp->recv_arg = NULL; - udp_remove(msg->conn->pcb.udp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && - msg->conn->write_offset == 0); - msg->conn->state = NETCONN_CLOSE; - msg->msg.sd.shut = NETCONN_SHUT_RDWR; - msg->conn->current_msg = msg; -#if LWIP_TCPIP_CORE_LOCKING - if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { - LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); - UNLOCK_TCPIP_CORE(); - sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); - LOCK_TCPIP_CORE(); - LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); - } -#else /* LWIP_TCPIP_CORE_LOCKING */ - lwip_netconn_do_close_internal(msg->conn); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing - the application thread, so we can return at this point! */ - return; -#endif /* LWIP_TCP */ - default: - break; - } - msg->conn->pcb.tcp = NULL; - } - /* tcp netconns don't come here! */ - - /* @todo: this lets select make the socket readable and writable, - which is wrong! errfd instead? */ - API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); - API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); - } - if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) { - TCPIP_APIMSG_ACK(msg); - } -} - -/** - * Bind a pcb contained in a netconn - * Called from netconn_bind. - * - * @param m the api_msg_msg pointing to the connection and containing - * the IP address and port to bind to - */ -void -lwip_netconn_do_bind(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (ERR_IS_FATAL(msg->conn->last_err)) { - msg->err = msg->conn->last_err; - } else { - msg->err = ERR_VAL; - if (msg->conn->pcb.tcp != NULL) { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); - break; -#endif /* LWIP_TCP */ - default: - break; - } - } - } - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_TCP -/** - * TCP callback function if a connection (opened by tcp_connect/lwip_netconn_do_connect) has - * been established (or reset by the remote host). - * - * @see tcp.h (struct tcp_pcb.connected) for parameters and return values - */ -static err_t -lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct netconn *conn; - int was_blocking; - sys_sem_t* op_completed_sem = NULL; - - LWIP_UNUSED_ARG(pcb); - - conn = (struct netconn *)arg; - - if (conn == NULL) { - return ERR_VAL; - } - - LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); - LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", - (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); - - if (conn->current_msg != NULL) { - conn->current_msg->err = err; - op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); - } - if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) { - setup_tcp(conn); - } - was_blocking = !IN_NONBLOCKING_CONNECT(conn); - SET_NONBLOCKING_CONNECT(conn, 0); - LWIP_ASSERT("blocking connect state error", - (was_blocking && op_completed_sem != NULL) || - (!was_blocking && op_completed_sem == NULL)); - conn->current_msg = NULL; - conn->state = NETCONN_NONE; - NETCONN_SET_SAFE_ERR(conn, ERR_OK); - API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); - - if (was_blocking) { - sys_sem_signal(op_completed_sem); - } - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Connect a pcb contained inside a netconn - * Called from netconn_connect. - * - * @param m the api_msg_msg pointing to the connection and containing - * the IP address and port to connect to - */ -void -lwip_netconn_do_connect(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (msg->conn->pcb.tcp == NULL) { - /* This may happen when calling netconn_connect() a second time */ - msg->err = ERR_CLSD; - } else { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - /* Prevent connect while doing any other action. */ - if (msg->conn->state == NETCONN_CONNECT) { - msg->err = ERR_ALREADY; - } else if (msg->conn->state != NETCONN_NONE) { - msg->err = ERR_ISCONN; - } else { - setup_tcp(msg->conn); - msg->err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), - msg->msg.bc.port, lwip_netconn_do_connected); - if (msg->err == ERR_OK) { - u8_t non_blocking = netconn_is_nonblocking(msg->conn); - msg->conn->state = NETCONN_CONNECT; - SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); - if (non_blocking) { - msg->err = ERR_INPROGRESS; - } else { - msg->conn->current_msg = msg; - /* sys_sem_signal() is called from lwip_netconn_do_connected (or err_tcp()), - when the connection is established! */ -#if LWIP_TCPIP_CORE_LOCKING - LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT); - UNLOCK_TCPIP_CORE(); - sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); - LOCK_TCPIP_CORE(); - LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - return; - } - } - } - break; -#endif /* LWIP_TCP */ - default: - LWIP_ERROR("Invalid netconn type", 0, do{ msg->err = ERR_VAL; }while(0)); - break; - } - } - /* For all other protocols, netconn_connect() calls TCPIP_APIMSG(), - so use TCPIP_APIMSG_ACK() here. */ - TCPIP_APIMSG_ACK(msg); -} - -/** - * Disconnect a pcb contained inside a netconn - * Only used for UDP netconns. - * Called from netconn_disconnect. - * - * @param m the api_msg_msg pointing to the connection to disconnect - */ -void -lwip_netconn_do_disconnect(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - -#if LWIP_UDP - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { - udp_disconnect(msg->conn->pcb.udp); - msg->err = ERR_OK; - } else -#endif /* LWIP_UDP */ - { - msg->err = ERR_VAL; - } - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_TCP -/** - * Set a TCP pcb contained in a netconn into listen mode - * Called from netconn_listen. - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_listen(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (ERR_IS_FATAL(msg->conn->last_err)) { - msg->err = msg->conn->last_err; - } else { - msg->err = ERR_CONN; - if (msg->conn->pcb.tcp != NULL) { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { - if (msg->conn->state == NETCONN_NONE) { - struct tcp_pcb* lpcb; - if (msg->conn->pcb.tcp->state != CLOSED) { - /* connection is not closed, cannot listen */ - msg->err = ERR_VAL; - } else { - err_t err; - u8_t backlog; -#if TCP_LISTEN_BACKLOG - backlog = msg->msg.lb.backlog; -#else /* TCP_LISTEN_BACKLOG */ - backlog = TCP_DEFAULT_LISTEN_BACKLOG; -#endif /* TCP_LISTEN_BACKLOG */ -#if LWIP_IPV4 && LWIP_IPV6 - /* "Socket API like" dual-stack support: If IP to listen to is IP6_ADDR_ANY, - * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to listen - */ - if (ip_addr_cmp(&msg->conn->pcb.ip->local_ip, IP6_ADDR_ANY) && - (netconn_get_ipv6only(msg->conn) == 0)) { - /* change PCB type to IPADDR_TYPE_ANY */ - IP_SET_TYPE_VAL(msg->conn->pcb.tcp->local_ip, IPADDR_TYPE_ANY); - IP_SET_TYPE_VAL(msg->conn->pcb.tcp->remote_ip, IPADDR_TYPE_ANY); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - lpcb = tcp_listen_with_backlog_and_err(msg->conn->pcb.tcp, backlog, &err); - - if (lpcb == NULL) { - /* in this case, the old pcb is still allocated */ - msg->err = err; - } else { - /* delete the recvmbox and allocate the acceptmbox */ - if (sys_mbox_valid(&msg->conn->recvmbox)) { - /** @todo: should we drain the recvmbox here? */ - sys_mbox_free(&msg->conn->recvmbox); - sys_mbox_set_invalid(&msg->conn->recvmbox); - } - msg->err = ERR_OK; - if (!sys_mbox_valid(&msg->conn->acceptmbox)) { - msg->err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE); - } - if (msg->err == ERR_OK) { - msg->conn->state = NETCONN_LISTEN; - msg->conn->pcb.tcp = lpcb; - tcp_arg(msg->conn->pcb.tcp, msg->conn); - tcp_accept(msg->conn->pcb.tcp, accept_function); - } else { - /* since the old pcb is already deallocated, free lpcb now */ - tcp_close(lpcb); - msg->conn->pcb.tcp = NULL; - } - } - } - } else if (msg->conn->state == NETCONN_LISTEN) { - /* already listening, allow updating of the backlog */ - msg->err = ERR_OK; - tcp_backlog_set(msg->conn->pcb.tcp, msg->msg.lb.backlog); - } - } else { - msg->err = ERR_ARG; - } - } - } - TCPIP_APIMSG_ACK(msg); -} -#endif /* LWIP_TCP */ - -/** - * Send some data on a RAW or UDP pcb contained in a netconn - * Called from netconn_send - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_send(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (ERR_IS_FATAL(msg->conn->last_err)) { - msg->err = msg->conn->last_err; - } else { - msg->err = ERR_CONN; - if (msg->conn->pcb.tcp != NULL) { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { - msg->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); - } else { - msg->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr); - } - break; -#endif -#if LWIP_UDP - case NETCONN_UDP: -#if LWIP_CHECKSUM_ON_COPY - if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { - msg->err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p, - msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); - } else { - msg->err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p, - &msg->msg.b->addr, msg->msg.b->port, - msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); - } -#else /* LWIP_CHECKSUM_ON_COPY */ - if (ip_addr_isany_val(msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { - msg->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); - } else { - msg->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port); - } -#endif /* LWIP_CHECKSUM_ON_COPY */ - break; -#endif /* LWIP_UDP */ - default: - break; - } - } - } - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_TCP -/** - * Indicate data has been received from a TCP pcb contained in a netconn - * Called from netconn_recv - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_recv(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - msg->err = ERR_OK; - if (msg->conn->pcb.tcp != NULL) { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { - u32_t remaining = msg->msg.r.len; - do { - u16_t recved = (remaining > 0xffff) ? 0xffff : (u16_t)remaining; - tcp_recved(msg->conn->pcb.tcp, recved); - remaining -= recved; - } while (remaining != 0); - } - } - TCPIP_APIMSG_ACK(msg); -} - -#if TCP_LISTEN_BACKLOG -/** Indicate that a TCP pcb has been accepted - * Called from netconn_accept - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_accepted(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - msg->err = ERR_OK; - if (msg->conn->pcb.tcp != NULL) { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { - tcp_backlog_accepted(msg->conn->pcb.tcp); - } - } - TCPIP_APIMSG_ACK(msg); -} -#endif /* TCP_LISTEN_BACKLOG */ - -/** - * See if more data needs to be written from a previous call to netconn_write. - * Called initially from lwip_netconn_do_write. If the first call can't send all data - * (because of low memory or empty send-buffer), this function is called again - * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the - * blocking application thread (waiting in netconn_write) is released. - * - * @param conn netconn (that is currently in state NETCONN_WRITE) to process - * @return ERR_OK - * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished - */ -static err_t -lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM) -{ - err_t err; - const void *dataptr; - u16_t len, available; - u8_t write_finished = 0; - size_t diff; - u8_t dontblock; - u8_t apiflags; - - LWIP_ASSERT("conn != NULL", conn != NULL); - LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); - LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); - LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); - LWIP_ASSERT("conn->write_offset < conn->current_msg->msg.w.len", - conn->write_offset < conn->current_msg->msg.w.len); - - apiflags = conn->current_msg->msg.w.apiflags; - dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); - -#if LWIP_SO_SNDTIMEO - if ((conn->send_timeout != 0) && - ((s32_t)(sys_now() - conn->current_msg->msg.w.time_started) >= conn->send_timeout)) { - write_finished = 1; - if (conn->write_offset == 0) { - /* nothing has been written */ - err = ERR_WOULDBLOCK; - conn->current_msg->msg.w.len = 0; - } else { - /* partial write */ - err = ERR_OK; - conn->current_msg->msg.w.len = conn->write_offset; - conn->write_offset = 0; - } - } else -#endif /* LWIP_SO_SNDTIMEO */ - { - dataptr = (const u8_t*)conn->current_msg->msg.w.dataptr + conn->write_offset; - diff = conn->current_msg->msg.w.len - conn->write_offset; - if (diff > 0xffffUL) { /* max_u16_t */ - len = 0xffff; - apiflags |= TCP_WRITE_FLAG_MORE; - } else { - len = (u16_t)diff; - } - available = tcp_sndbuf(conn->pcb.tcp); - if (available < len) { - /* don't try to write more than sendbuf */ - len = available; - if (dontblock) { - if (!len) { - err = ERR_WOULDBLOCK; - goto err_mem; - } - } else { - apiflags |= TCP_WRITE_FLAG_MORE; - } - } - LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!", ((conn->write_offset + len) <= conn->current_msg->msg.w.len)); - err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); - /* if OK or memory error, check available space */ - if ((err == ERR_OK) || (err == ERR_MEM)) { -err_mem: - if (dontblock && (len < conn->current_msg->msg.w.len)) { - /* non-blocking write did not write everything: mark the pcb non-writable - and let poll_tcp check writable space to mark the pcb writable again */ - API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); - conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; - } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || - (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) { - /* The queued byte- or pbuf-count exceeds the configured low-water limit, - let select mark this pcb as non-writable. */ - API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); - } - } - - if (err == ERR_OK) { - err_t out_err; - conn->write_offset += len; - if ((conn->write_offset == conn->current_msg->msg.w.len) || dontblock) { - /* return sent length */ - conn->current_msg->msg.w.len = conn->write_offset; - /* everything was written */ - write_finished = 1; - } - out_err = tcp_output(conn->pcb.tcp); - if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { - /* If tcp_output fails with fatal error or no route is found, - don't try writing any more but return the error - to the application thread. */ - err = out_err; - write_finished = 1; - conn->current_msg->msg.w.len = 0; - } - } else if (err == ERR_MEM) { - /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called. - For blocking sockets, we do NOT return to the application - thread, since ERR_MEM is only a temporary error! Non-blocking - will remain non-writable until sent_tcp/poll_tcp is called */ - - /* tcp_write returned ERR_MEM, try tcp_output anyway */ - err_t out_err = tcp_output(conn->pcb.tcp); - if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { - /* If tcp_output fails with fatal error or no route is found, - don't try writing any more but return the error - to the application thread. */ - err = out_err; - write_finished = 1; - conn->current_msg->msg.w.len = 0; - } else if (dontblock) { - /* non-blocking write is done on ERR_MEM */ - err = ERR_WOULDBLOCK; - write_finished = 1; - conn->current_msg->msg.w.len = 0; - } - } else { - /* On errors != ERR_MEM, we don't try writing any more but return - the error to the application thread. */ - write_finished = 1; - conn->current_msg->msg.w.len = 0; - } - } - if (write_finished) { - /* everything was written: set back connection state - and back to application task */ - sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); - conn->current_msg->err = err; - conn->current_msg = NULL; - conn->write_offset = 0; - conn->state = NETCONN_NONE; - NETCONN_SET_SAFE_ERR(conn, err); -#if LWIP_TCPIP_CORE_LOCKING - if (delayed) -#endif - { - sys_sem_signal(op_completed_sem); - } - } -#if LWIP_TCPIP_CORE_LOCKING - else { - return ERR_MEM; - } -#endif - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Send some data on a TCP pcb contained in a netconn - * Called from netconn_write - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_write(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (ERR_IS_FATAL(msg->conn->last_err)) { - msg->err = msg->conn->last_err; - } else { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { -#if LWIP_TCP - if (msg->conn->state != NETCONN_NONE) { - /* netconn is connecting, closing or in blocking write */ - msg->err = ERR_INPROGRESS; - } else if (msg->conn->pcb.tcp != NULL) { - msg->conn->state = NETCONN_WRITE; - /* set all the variables used by lwip_netconn_do_writemore */ - LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && - msg->conn->write_offset == 0); - LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); - msg->conn->current_msg = msg; - msg->conn->write_offset = 0; -#if LWIP_TCPIP_CORE_LOCKING - if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) { - LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); - UNLOCK_TCPIP_CORE(); - sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); - LOCK_TCPIP_CORE(); - LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE); - } -#else /* LWIP_TCPIP_CORE_LOCKING */ - lwip_netconn_do_writemore(msg->conn); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG - since lwip_netconn_do_writemore ACKs it! */ - return; - } else { - msg->err = ERR_CONN; - } -#else /* LWIP_TCP */ - msg->err = ERR_VAL; -#endif /* LWIP_TCP */ -#if (LWIP_UDP || LWIP_RAW) - } else { - msg->err = ERR_VAL; -#endif /* (LWIP_UDP || LWIP_RAW) */ - } - } - TCPIP_APIMSG_ACK(msg); -} - -/** - * Return a connection's local or remote address - * Called from netconn_getaddr - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_getaddr(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (msg->conn->pcb.ip != NULL) { - if (msg->msg.ad.local) { - ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), - msg->conn->pcb.ip->local_ip); - } else { - ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), - msg->conn->pcb.ip->remote_ip); - } - - msg->err = ERR_OK; - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - if (msg->msg.ad.local) { - API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; - } else { - /* return an error as connecting is only a helper for upper layers */ - msg->err = ERR_CONN; - } - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - if (msg->msg.ad.local) { - API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; - } else { - if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { - msg->err = ERR_CONN; - } else { - API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; - } - } - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - if ((msg->msg.ad.local == 0) && - ((msg->conn->pcb.tcp->state == CLOSED) || (msg->conn->pcb.tcp->state == LISTEN))) { - /* pcb is not connected and remote name is requested */ - msg->err = ERR_CONN; - } else { - API_EXPR_DEREF(msg->msg.ad.port) = (msg->msg.ad.local ? msg->conn->pcb.tcp->local_port : msg->conn->pcb.tcp->remote_port); - } - break; -#endif /* LWIP_TCP */ - default: - LWIP_ASSERT("invalid netconn_type", 0); - break; - } - } else { - msg->err = ERR_CONN; - } - TCPIP_APIMSG_ACK(msg); -} - -/** - * Close or half-shutdown a TCP pcb contained in a netconn - * Called from netconn_close - * In contrast to closing sockets, the netconn is not deallocated. - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_close(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - -#if LWIP_TCP - enum netconn_state state = msg->conn->state; - /* First check if this is a TCP netconn and if it is in a correct state - (LISTEN doesn't support half shutdown) */ - if ((msg->conn->pcb.tcp != NULL) && - (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && - ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { - /* Check if we are in a connected state */ - if (state == NETCONN_CONNECT) { - /* TCP connect in progress: cannot shutdown */ - msg->err = ERR_CONN; - } else if (state == NETCONN_WRITE) { -#if LWIP_NETCONN_FULLDUPLEX - if (msg->msg.sd.shut & NETCONN_SHUT_WR) { - /* close requested, abort running write */ - sys_sem_t* write_completed_sem; - LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); - write_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); - msg->conn->current_msg->err = ERR_CLSD; - msg->conn->current_msg = NULL; - msg->conn->write_offset = 0; - msg->conn->state = NETCONN_NONE; - state = NETCONN_NONE; - NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); - sys_sem_signal(write_completed_sem); - } else { - LWIP_ASSERT("msg->msg.sd.shut == NETCONN_SHUT_RD", msg->msg.sd.shut == NETCONN_SHUT_RD); - /* In this case, let the write continue and do not interfere with - conn->current_msg or conn->state! */ - msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0); - } - } - if (state == NETCONN_NONE) { -#else /* LWIP_NETCONN_FULLDUPLEX */ - msg->err = ERR_INPROGRESS; - } else { -#endif /* LWIP_NETCONN_FULLDUPLEX */ - if (msg->msg.sd.shut & NETCONN_SHUT_RD) { - /* Drain and delete mboxes */ - netconn_drain(msg->conn); - } - LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && - msg->conn->write_offset == 0); - msg->conn->state = NETCONN_CLOSE; - msg->conn->current_msg = msg; -#if LWIP_TCPIP_CORE_LOCKING - if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { - LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); - UNLOCK_TCPIP_CORE(); - sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); - LOCK_TCPIP_CORE(); - LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); - } -#else /* LWIP_TCPIP_CORE_LOCKING */ - lwip_netconn_do_close_internal(msg->conn); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */ - return; - } - } else -#endif /* LWIP_TCP */ - { - msg->err = ERR_CONN; - } - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) -/** - * Join multicast groups for UDP netconns. - * Called from netconn_join_leave_group - * - * @param m the api_msg_msg pointing to the connection - */ -void -lwip_netconn_do_join_leave_group(void *m) -{ - struct api_msg *msg = (struct api_msg*)m; - - if (ERR_IS_FATAL(msg->conn->last_err)) { - msg->err = msg->conn->last_err; - } else { - if (msg->conn->pcb.tcp != NULL) { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { -#if LWIP_UDP -#if LWIP_IPV6 && LWIP_IPV6_MLD - if (NETCONNTYPE_ISIPV6(msg->conn->type)) { - if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { - msg->err = mld6_joingroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), - ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); - } else { - msg->err = mld6_leavegroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), - ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); - } - } - else -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ - { -#if LWIP_IGMP - if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { - msg->err = igmp_joingroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), - ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); - } else { - msg->err = igmp_leavegroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), - ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); - } -#endif /* LWIP_IGMP */ - } -#endif /* LWIP_UDP */ -#if (LWIP_TCP || LWIP_RAW) - } else { - msg->err = ERR_VAL; -#endif /* (LWIP_TCP || LWIP_RAW) */ - } - } else { - msg->err = ERR_CONN; - } - } - TCPIP_APIMSG_ACK(msg); -} -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - -#if LWIP_DNS -/** - * Callback function that is called when DNS name is resolved - * (or on timeout). A waiting application thread is waked up by - * signaling the semaphore. - */ -static void -lwip_netconn_do_dns_found(const char *name, const ip_addr_t *ipaddr, void *arg) -{ - struct dns_api_msg *msg = (struct dns_api_msg*)arg; - - /* we trust the internal implementation to be correct :-) */ - LWIP_UNUSED_ARG(name); - - if (ipaddr == NULL) { - /* timeout or memory error */ - API_EXPR_DEREF(msg->err) = ERR_VAL; - } else { - /* address was resolved */ - API_EXPR_DEREF(msg->err) = ERR_OK; - API_EXPR_DEREF(msg->addr) = *ipaddr; - } - /* wake up the application task waiting in netconn_gethostbyname */ - sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); -} - -/** - * Execute a DNS query - * Called from netconn_gethostbyname - * - * @param arg the dns_api_msg pointing to the query - */ -void -lwip_netconn_do_gethostbyname(void *arg) -{ - struct dns_api_msg *msg = (struct dns_api_msg*)arg; - u8_t addrtype = -#if LWIP_IPV4 && LWIP_IPV6 - msg->dns_addrtype; -#else - LWIP_DNS_ADDRTYPE_DEFAULT; -#endif - - API_EXPR_DEREF(msg->err) = dns_gethostbyname_addrtype(msg->name, - API_EXPR_REF(msg->addr), lwip_netconn_do_dns_found, msg, addrtype); - if (API_EXPR_DEREF(msg->err) != ERR_INPROGRESS) { - /* on error or immediate success, wake up the application - * task waiting in netconn_gethostbyname */ - sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); - } -} -#endif /* LWIP_DNS */ - -#endif /* LWIP_NETCONN */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/err.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/err.c deleted file mode 100644 index c60b51f8a2eed18ad01678e719d208f1bf383cd0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/err.c +++ /dev/null @@ -1,114 +0,0 @@ -/** - * @file - * Error Management module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/err.h" -#include "lwip/def.h" -#include "lwip/sys.h" -#include "errno.h" - -#if !NO_SYS -/** Table to quickly map an lwIP error (err_t) to a socket error - * by using -err as an index */ -static const int err_to_errno_table[] = { - 0, /* ERR_OK 0 No error, everything OK. */ - ENOMEM, /* ERR_MEM -1 Out of memory error. */ - ENOBUFS, /* ERR_BUF -2 Buffer error. */ - EWOULDBLOCK, /* ERR_TIMEOUT -3 Timeout */ - EHOSTUNREACH, /* ERR_RTE -4 Routing problem. */ - EINPROGRESS, /* ERR_INPROGRESS -5 Operation in progress */ - EINVAL, /* ERR_VAL -6 Illegal value. */ - EWOULDBLOCK, /* ERR_WOULDBLOCK -7 Operation would block. */ - EADDRINUSE, /* ERR_USE -8 Address in use. */ - EALREADY, /* ERR_ALREADY -9 Already connecting. */ - EISCONN, /* ERR_ISCONN -10 Conn already established.*/ - ENOTCONN, /* ERR_CONN -11 Not connected. */ - -1, /* ERR_IF -12 Low-level netif error */ - ECONNABORTED, /* ERR_ABRT -13 Connection aborted. */ - ECONNRESET, /* ERR_RST -14 Connection reset. */ - ENOTCONN, /* ERR_CLSD -15 Connection closed. */ - EIO /* ERR_ARG -16 Illegal argument. */ -}; - -int -err_to_errno(err_t err) -{ - if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_to_errno_table))) { - return EIO; - } - return err_to_errno_table[-err]; -} -#endif /* !NO_SYS */ - -#ifdef LWIP_DEBUG - -static const char *err_strerr[] = { - "Ok.", /* ERR_OK 0 */ - "Out of memory error.", /* ERR_MEM -1 */ - "Buffer error.", /* ERR_BUF -2 */ - "Timeout.", /* ERR_TIMEOUT -3 */ - "Routing problem.", /* ERR_RTE -4 */ - "Operation in progress.", /* ERR_INPROGRESS -5 */ - "Illegal value.", /* ERR_VAL -6 */ - "Operation would block.", /* ERR_WOULDBLOCK -7 */ - "Address in use.", /* ERR_USE -8 */ - "Already connecting.", /* ERR_ALREADY -9 */ - "Already connected.", /* ERR_ISCONN -10 */ - "Not connected.", /* ERR_CONN -11 */ - "Low-level netif error.", /* ERR_IF -12 */ - "Connection aborted.", /* ERR_ABRT -13 */ - "Connection reset.", /* ERR_RST -14 */ - "Connection closed.", /* ERR_CLSD -15 */ - "Illegal argument." /* ERR_ARG -16 */ -}; - -/** - * Convert an lwip internal error to a string representation. - * - * @param err an lwip internal err_t - * @return a string representation for err - */ -const char * -lwip_strerr(err_t err) -{ - if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_strerr))) { - return "Unknown error."; - } - return err_strerr[-err]; -} - -#endif /* LWIP_DEBUG */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netbuf.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netbuf.c deleted file mode 100644 index eb250115ff65ace56aceccb9d35160cc1e5f27d3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netbuf.c +++ /dev/null @@ -1,246 +0,0 @@ -/** - * @file - * Network buffer management - * - * @defgroup netbuf Network buffers - * @ingroup netconn - * Network buffer descriptor for @ref netconn. Based on @ref pbuf internally - * to avoid copying data around.\n - * Buffers must not be shared accross multiple threads, all functions except - * netbuf_new() and netbuf_delete() are not thread-safe. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netbuf.h" -#include "lwip/memp.h" - -#include - -/** - * @ingroup netbuf - * Create (allocate) and initialize a new netbuf. - * The netbuf doesn't yet contain a packet buffer! - * - * @return a pointer to a new netbuf - * NULL on lack of memory - */ -struct -netbuf *netbuf_new(void) -{ - struct netbuf *buf; - - buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); - if (buf != NULL) { - memset(buf, 0, sizeof(struct netbuf)); - } - return buf; -} - -/** - * @ingroup netbuf - * Deallocate a netbuf allocated by netbuf_new(). - * - * @param buf pointer to a netbuf allocated by netbuf_new() - */ -void -netbuf_delete(struct netbuf *buf) -{ - if (buf != NULL) { - if (buf->p != NULL) { - pbuf_free(buf->p); - buf->p = buf->ptr = NULL; - } - memp_free(MEMP_NETBUF, buf); - } -} - -/** - * @ingroup netbuf - * Allocate memory for a packet buffer for a given netbuf. - * - * @param buf the netbuf for which to allocate a packet buffer - * @param size the size of the packet buffer to allocate - * @return pointer to the allocated memory - * NULL if no memory could be allocated - */ -void * -netbuf_alloc(struct netbuf *buf, u16_t size) -{ - LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;); - - /* Deallocate any previously allocated memory. */ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); - if (buf->p == NULL) { - return NULL; - } - LWIP_ASSERT("check that first pbuf can hold size", - (buf->p->len >= size)); - buf->ptr = buf->p; - return buf->p->payload; -} - -/** - * @ingroup netbuf - * Free the packet buffer included in a netbuf - * - * @param buf pointer to the netbuf which contains the packet buffer to free - */ -void -netbuf_free(struct netbuf *buf) -{ - LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;); - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = buf->ptr = NULL; -} - -/** - * @ingroup netbuf - * Let a netbuf reference existing (non-volatile) data. - * - * @param buf netbuf which should reference the data - * @param dataptr pointer to the data to reference - * @param size size of the data - * @return ERR_OK if data is referenced - * ERR_MEM if data couldn't be referenced due to lack of memory - */ -err_t -netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size) -{ - LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;); - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); - if (buf->p == NULL) { - buf->ptr = NULL; - return ERR_MEM; - } - ((struct pbuf_rom*)buf->p)->payload = dataptr; - buf->p->len = buf->p->tot_len = size; - buf->ptr = buf->p; - return ERR_OK; -} - -/** - * @ingroup netbuf - * Chain one netbuf to another (@see pbuf_chain) - * - * @param head the first netbuf - * @param tail netbuf to chain after head, freed by this function, may not be reference after returning - */ -void -netbuf_chain(struct netbuf *head, struct netbuf *tail) -{ - LWIP_ERROR("netbuf_chain: invalid head", (head != NULL), return;); - LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;); - pbuf_cat(head->p, tail->p); - head->ptr = head->p; - memp_free(MEMP_NETBUF, tail); -} - -/** - * @ingroup netbuf - * Get the data pointer and length of the data inside a netbuf. - * - * @param buf netbuf to get the data from - * @param dataptr pointer to a void pointer where to store the data pointer - * @param len pointer to an u16_t where the length of the data is stored - * @return ERR_OK if the information was retrieved, - * ERR_BUF on error. - */ -err_t -netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) -{ - LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;); - LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;); - LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;); - - if (buf->ptr == NULL) { - return ERR_BUF; - } - *dataptr = buf->ptr->payload; - *len = buf->ptr->len; - return ERR_OK; -} - -/** - * @ingroup netbuf - * Move the current data pointer of a packet buffer contained in a netbuf - * to the next part. - * The packet buffer itself is not modified. - * - * @param buf the netbuf to modify - * @return -1 if there is no next part - * 1 if moved to the next part but now there is no next part - * 0 if moved to the next part and there are still more parts - */ -s8_t -netbuf_next(struct netbuf *buf) -{ - LWIP_ERROR("netbuf_next: invalid buf", (buf != NULL), return -1;); - if (buf->ptr->next == NULL) { - return -1; - } - buf->ptr = buf->ptr->next; - if (buf->ptr->next == NULL) { - return 1; - } - return 0; -} - -/** - * @ingroup netbuf - * Move the current data pointer of a packet buffer contained in a netbuf - * to the beginning of the packet. - * The packet buffer itself is not modified. - * - * @param buf the netbuf to modify - */ -void -netbuf_first(struct netbuf *buf) -{ - LWIP_ERROR("netbuf_first: invalid buf", (buf != NULL), return;); - buf->ptr = buf->p; -} - -#endif /* LWIP_NETCONN */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netdb.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netdb.c deleted file mode 100644 index ccd9586fda0685d8f8c335ab1587403839b857da..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netdb.c +++ /dev/null @@ -1,413 +0,0 @@ -/** - * @file - * API functions for name resolving - * - * @defgroup netdbapi NETDB API - * @ingroup socket - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ - -#include "lwip/netdb.h" - -#if LWIP_DNS && LWIP_SOCKET - -#include "lwip/err.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/ip_addr.h" -#include "lwip/api.h" -#include "lwip/dns.h" - -#include /* memset */ -#include /* atoi */ - -/** helper struct for gethostbyname_r to access the char* buffer */ -struct gethostbyname_r_helper { - ip_addr_t *addr_list[2]; - ip_addr_t addr; - char *aliases; -}; - -/** h_errno is exported in netdb.h for access by applications. */ -#if LWIP_DNS_API_DECLARE_H_ERRNO -int h_errno; -#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */ - -/** define "hostent" variables storage: 0 if we use a static (but unprotected) - * set of variables for lwip_gethostbyname, 1 if we use a local storage */ -#ifndef LWIP_DNS_API_HOSTENT_STORAGE -#define LWIP_DNS_API_HOSTENT_STORAGE 0 -#endif - -/** define "hostent" variables storage */ -#if LWIP_DNS_API_HOSTENT_STORAGE -#define HOSTENT_STORAGE -#else -#define HOSTENT_STORAGE static -#endif /* LWIP_DNS_API_STATIC_HOSTENT */ - -/** - * Returns an entry containing addresses of address family AF_INET - * for the host with name name. - * Due to dns_gethostbyname limitations, only one address is returned. - * - * @param name the hostname to resolve - * @return an entry containing addresses of address family AF_INET - * for the host with name name - */ -struct hostent* -lwip_gethostbyname(const char *name) -{ - err_t err; - ip_addr_t addr; - - /* buffer variables for lwip_gethostbyname() */ - HOSTENT_STORAGE struct hostent s_hostent; - HOSTENT_STORAGE char *s_aliases; - HOSTENT_STORAGE ip_addr_t s_hostent_addr; - HOSTENT_STORAGE ip_addr_t *s_phostent_addr[2]; - HOSTENT_STORAGE char s_hostname[DNS_MAX_NAME_LENGTH + 1]; - - /* query host IP address */ - err = netconn_gethostbyname(name, &addr); - if (err != ERR_OK) { - LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); - h_errno = HOST_NOT_FOUND; - return NULL; - } - - /* fill hostent */ - s_hostent_addr = addr; - s_phostent_addr[0] = &s_hostent_addr; - s_phostent_addr[1] = NULL; - strncpy(s_hostname, name, DNS_MAX_NAME_LENGTH); - s_hostname[DNS_MAX_NAME_LENGTH] = 0; - s_hostent.h_name = s_hostname; - s_aliases = NULL; - s_hostent.h_aliases = &s_aliases; - s_hostent.h_addrtype = AF_INET; - s_hostent.h_length = sizeof(ip_addr_t); - s_hostent.h_addr_list = (char**)&s_phostent_addr; - -#if DNS_DEBUG - /* dump hostent */ - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name == %s\n", s_hostent.h_name)); - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases == %p\n", (void*)s_hostent.h_aliases)); - /* h_aliases are always empty */ - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype == %d\n", s_hostent.h_addrtype)); - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length == %d\n", s_hostent.h_length)); - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list == %p\n", (void*)s_hostent.h_addr_list)); - if (s_hostent.h_addr_list != NULL) { - u8_t idx; - for (idx=0; s_hostent.h_addr_list[idx]; idx++) { - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i] == %p\n", idx, s_hostent.h_addr_list[idx])); - LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ipaddr_ntoa((ip_addr_t*)s_hostent.h_addr_list[idx]))); - } - } -#endif /* DNS_DEBUG */ - -#if LWIP_DNS_API_HOSTENT_STORAGE - /* this function should return the "per-thread" hostent after copy from s_hostent */ - return sys_thread_hostent(&s_hostent); -#else - return &s_hostent; -#endif /* LWIP_DNS_API_HOSTENT_STORAGE */ -} - -/** - * Thread-safe variant of lwip_gethostbyname: instead of using a static - * buffer, this function takes buffer and errno pointers as arguments - * and uses these for the result. - * - * @param name the hostname to resolve - * @param ret pre-allocated struct where to store the result - * @param buf pre-allocated buffer where to store additional data - * @param buflen the size of buf - * @param result pointer to a hostent pointer that is set to ret on success - * and set to zero on error - * @param h_errnop pointer to an int where to store errors (instead of modifying - * the global h_errno) - * @return 0 on success, non-zero on error, additional error information - * is stored in *h_errnop instead of h_errno to be thread-safe - */ -int -lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, - size_t buflen, struct hostent **result, int *h_errnop) -{ - err_t err; - struct gethostbyname_r_helper *h; - char *hostname; - size_t namelen; - int lh_errno; - - if (h_errnop == NULL) { - /* ensure h_errnop is never NULL */ - h_errnop = &lh_errno; - } - - if (result == NULL) { - /* not all arguments given */ - *h_errnop = EINVAL; - return -1; - } - /* first thing to do: set *result to nothing */ - *result = NULL; - if ((name == NULL) || (ret == NULL) || (buf == NULL)) { - /* not all arguments given */ - *h_errnop = EINVAL; - return -1; - } - - namelen = strlen(name); - if (buflen < (sizeof(struct gethostbyname_r_helper) + namelen + 1 + (MEM_ALIGNMENT - 1))) { - /* buf can't hold the data needed + a copy of name */ - *h_errnop = ERANGE; - return -1; - } - - h = (struct gethostbyname_r_helper*)LWIP_MEM_ALIGN(buf); - hostname = ((char*)h) + sizeof(struct gethostbyname_r_helper); - - /* query host IP address */ - err = netconn_gethostbyname(name, &h->addr); - if (err != ERR_OK) { - LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); - *h_errnop = HOST_NOT_FOUND; - return -1; - } - - /* copy the hostname into buf */ - MEMCPY(hostname, name, namelen); - hostname[namelen] = 0; - - /* fill hostent */ - h->addr_list[0] = &h->addr; - h->addr_list[1] = NULL; - h->aliases = NULL; - ret->h_name = hostname; - ret->h_aliases = &h->aliases; - ret->h_addrtype = AF_INET; - ret->h_length = sizeof(ip_addr_t); - ret->h_addr_list = (char**)&h->addr_list; - - /* set result != NULL */ - *result = ret; - - /* return success */ - return 0; -} - -/** - * Frees one or more addrinfo structures returned by getaddrinfo(), along with - * any additional storage associated with those structures. If the ai_next field - * of the structure is not null, the entire list of structures is freed. - * - * @param ai struct addrinfo to free - */ -void -lwip_freeaddrinfo(struct addrinfo *ai) -{ - struct addrinfo *next; - - while (ai != NULL) { - next = ai->ai_next; - memp_free(MEMP_NETDB, ai); - ai = next; - } -} - -/** - * Translates the name of a service location (for example, a host name) and/or - * a service name and returns a set of socket addresses and associated - * information to be used in creating a socket with which to address the - * specified service. - * Memory for the result is allocated internally and must be freed by calling - * lwip_freeaddrinfo()! - * - * Due to a limitation in dns_gethostbyname, only the first address of a - * host is returned. - * Also, service names are not supported (only port numbers)! - * - * @param nodename descriptive name or address string of the host - * (may be NULL -> local address) - * @param servname port number as string of NULL - * @param hints structure containing input values that set socktype and protocol - * @param res pointer to a pointer where to store the result (set to NULL on failure) - * @return 0 on success, non-zero on failure - * - * @todo: implement AI_V4MAPPED, AI_ADDRCONFIG - */ -int -lwip_getaddrinfo(const char *nodename, const char *servname, - const struct addrinfo *hints, struct addrinfo **res) -{ - err_t err; - ip_addr_t addr; - struct addrinfo *ai; - struct sockaddr_storage *sa = NULL; - int port_nr = 0; - size_t total_size; - size_t namelen = 0; - int ai_family; - - if (res == NULL) { - return EAI_FAIL; - } - *res = NULL; - if ((nodename == NULL) && (servname == NULL)) { - return EAI_NONAME; - } - - if (hints != NULL) { - ai_family = hints->ai_family; - if ((ai_family != AF_UNSPEC) -#if LWIP_IPV4 - && (ai_family != AF_INET) -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - && (ai_family != AF_INET6) -#endif /* LWIP_IPV6 */ - ) { - return EAI_FAMILY; - } - } else { - ai_family = AF_UNSPEC; - } - - if (servname != NULL) { - /* service name specified: convert to port number - * @todo?: currently, only ASCII integers (port numbers) are supported (AI_NUMERICSERV)! */ - port_nr = atoi(servname); - if ((port_nr <= 0) || (port_nr > 0xffff)) { - return EAI_SERVICE; - } - } - - if (nodename != NULL) { - /* service location specified, try to resolve */ - if ((hints != NULL) && (hints->ai_flags & AI_NUMERICHOST)) { - /* no DNS lookup, just parse for an address string */ - if (!ipaddr_aton(nodename, &addr)) { - return EAI_NONAME; - } -#if LWIP_IPV4 && LWIP_IPV6 - if ((IP_IS_V6_VAL(addr) && ai_family == AF_INET) || - (IP_IS_V4_VAL(addr) && ai_family == AF_INET6)) { - return EAI_NONAME; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - } else { -#if LWIP_IPV4 && LWIP_IPV6 - /* AF_UNSPEC: prefer IPv4 */ - u8_t type = NETCONN_DNS_IPV4_IPV6; - if (ai_family == AF_INET) { - type = NETCONN_DNS_IPV4; - } else if (ai_family == AF_INET6) { - type = NETCONN_DNS_IPV6; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - err = netconn_gethostbyname_addrtype(nodename, &addr, type); - if (err != ERR_OK) { - return EAI_FAIL; - } - } - } else { - /* service location specified, use loopback address */ - if ((hints != NULL) && (hints->ai_flags & AI_PASSIVE)) { - ip_addr_set_any(ai_family == AF_INET6, &addr); - } else { - ip_addr_set_loopback(ai_family == AF_INET6, &addr); - } - } - - total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_storage); - if (nodename != NULL) { - namelen = strlen(nodename); - if (namelen > DNS_MAX_NAME_LENGTH) { - /* invalid name length */ - return EAI_FAIL; - } - LWIP_ASSERT("namelen is too long", total_size + namelen + 1 > total_size); - total_size += namelen + 1; - } - /* If this fails, please report to lwip-devel! :-) */ - LWIP_ASSERT("total_size <= NETDB_ELEM_SIZE: please report this!", - total_size <= NETDB_ELEM_SIZE); - ai = (struct addrinfo *)memp_malloc(MEMP_NETDB); - if (ai == NULL) { - return EAI_MEMORY; - } - memset(ai, 0, total_size); - /* cast through void* to get rid of alignment warnings */ - sa = (struct sockaddr_storage *)(void*)((u8_t*)ai + sizeof(struct addrinfo)); - if (IP_IS_V6_VAL(addr)) { -#if LWIP_IPV6 - struct sockaddr_in6 *sa6 = (struct sockaddr_in6*)sa; - /* set up sockaddr */ - inet6_addr_from_ip6addr(&sa6->sin6_addr, ip_2_ip6(&addr)); - sa6->sin6_family = AF_INET6; - sa6->sin6_len = sizeof(struct sockaddr_in6); - sa6->sin6_port = lwip_htons((u16_t)port_nr); - ai->ai_family = AF_INET6; -#endif /* LWIP_IPV6 */ - } else { -#if LWIP_IPV4 - struct sockaddr_in *sa4 = (struct sockaddr_in*)sa; - /* set up sockaddr */ - inet_addr_from_ip4addr(&sa4->sin_addr, ip_2_ip4(&addr)); - sa4->sin_family = AF_INET; - sa4->sin_len = sizeof(struct sockaddr_in); - sa4->sin_port = lwip_htons((u16_t)port_nr); - ai->ai_family = AF_INET; -#endif /* LWIP_IPV4 */ - } - - /* set up addrinfo */ - if (hints != NULL) { - /* copy socktype & protocol from hints if specified */ - ai->ai_socktype = hints->ai_socktype; - ai->ai_protocol = hints->ai_protocol; - } - if (nodename != NULL) { - /* copy nodename to canonname if specified */ - ai->ai_canonname = ((char*)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_storage)); - MEMCPY(ai->ai_canonname, nodename, namelen); - ai->ai_canonname[namelen] = 0; - } - ai->ai_addrlen = sizeof(struct sockaddr_storage); - ai->ai_addr = (struct sockaddr*)sa; - - *res = ai; - - return 0; -} - -#endif /* LWIP_DNS && LWIP_SOCKET */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netifapi.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netifapi.c deleted file mode 100644 index fef05a34dc880eb0ea16f46711effa6a43cf67d3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/netifapi.c +++ /dev/null @@ -1,221 +0,0 @@ -/** - * @file - * Network Interface Sequential API module - * - * @defgroup netifapi NETIF API - * @ingroup sequential_api - * Thread-safe functions to be called from non-TCPIP threads - * - * @defgroup netifapi_netif NETIF related - * @ingroup netifapi - * To be called from non-TCPIP threads - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" - -#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netifapi.h" -#include "lwip/memp.h" -#include "lwip/priv/tcpip_priv.h" - -#define NETIFAPI_VAR_REF(name) API_VAR_REF(name) -#define NETIFAPI_VAR_DECLARE(name) API_VAR_DECLARE(struct netifapi_msg, name) -#define NETIFAPI_VAR_ALLOC(name) API_VAR_ALLOC(struct netifapi_msg, MEMP_NETIFAPI_MSG, name, ERR_MEM) -#define NETIFAPI_VAR_FREE(name) API_VAR_FREE(MEMP_NETIFAPI_MSG, name) - -/** - * Call netif_add() inside the tcpip_thread context. - */ -static err_t -netifapi_do_netif_add(struct tcpip_api_call_data *m) -{ - /* cast through void* to silence alignment warnings. - * We know it works because the structs have been instantiated as struct netifapi_msg */ - struct netifapi_msg *msg = (struct netifapi_msg*)(void*)m; - - if (!netif_add( msg->netif, -#if LWIP_IPV4 - API_EXPR_REF(msg->msg.add.ipaddr), - API_EXPR_REF(msg->msg.add.netmask), - API_EXPR_REF(msg->msg.add.gw), -#endif /* LWIP_IPV4 */ - msg->msg.add.state, - msg->msg.add.init, - msg->msg.add.input)) { - return ERR_IF; - } else { - return ERR_OK; - } -} - -#if LWIP_IPV4 -/** - * Call netif_set_addr() inside the tcpip_thread context. - */ -static err_t -netifapi_do_netif_set_addr(struct tcpip_api_call_data *m) -{ - /* cast through void* to silence alignment warnings. - * We know it works because the structs have been instantiated as struct netifapi_msg */ - struct netifapi_msg *msg = (struct netifapi_msg*)(void*)m; - - netif_set_addr( msg->netif, - API_EXPR_REF(msg->msg.add.ipaddr), - API_EXPR_REF(msg->msg.add.netmask), - API_EXPR_REF(msg->msg.add.gw)); - return ERR_OK; -} -#endif /* LWIP_IPV4 */ - -/** - * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the - * tcpip_thread context. - */ -static err_t -netifapi_do_netif_common(struct tcpip_api_call_data *m) -{ - /* cast through void* to silence alignment warnings. - * We know it works because the structs have been instantiated as struct netifapi_msg */ - struct netifapi_msg *msg = (struct netifapi_msg*)(void*)m; - - if (msg->msg.common.errtfunc != NULL) { - return msg->msg.common.errtfunc(msg->netif); - } else { - msg->msg.common.voidfunc(msg->netif); - return ERR_OK; - } -} - -/** - * @ingroup netifapi_netif - * Call netif_add() in a thread-safe way by running that function inside the - * tcpip_thread context. - * - * @note for params @see netif_add() - */ -err_t -netifapi_netif_add(struct netif *netif, -#if LWIP_IPV4 - const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, -#endif /* LWIP_IPV4 */ - void *state, netif_init_fn init, netif_input_fn input) -{ - err_t err; - NETIFAPI_VAR_DECLARE(msg); - NETIFAPI_VAR_ALLOC(msg); - -#if LWIP_IPV4 - if (ipaddr == NULL) { - ipaddr = IP4_ADDR_ANY4; - } - if (netmask == NULL) { - netmask = IP4_ADDR_ANY4; - } - if (gw == NULL) { - gw = IP4_ADDR_ANY4; - } -#endif /* LWIP_IPV4 */ - - NETIFAPI_VAR_REF(msg).netif = netif; -#if LWIP_IPV4 - NETIFAPI_VAR_REF(msg).msg.add.ipaddr = NETIFAPI_VAR_REF(ipaddr); - NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask); - NETIFAPI_VAR_REF(msg).msg.add.gw = NETIFAPI_VAR_REF(gw); -#endif /* LWIP_IPV4 */ - NETIFAPI_VAR_REF(msg).msg.add.state = state; - NETIFAPI_VAR_REF(msg).msg.add.init = init; - NETIFAPI_VAR_REF(msg).msg.add.input = input; - err = tcpip_api_call(netifapi_do_netif_add, &API_VAR_REF(msg).call); - NETIFAPI_VAR_FREE(msg); - return err; -} - -#if LWIP_IPV4 -/** - * @ingroup netifapi_netif - * Call netif_set_addr() in a thread-safe way by running that function inside the - * tcpip_thread context. - * - * @note for params @see netif_set_addr() - */ -err_t -netifapi_netif_set_addr(struct netif *netif, - const ip4_addr_t *ipaddr, - const ip4_addr_t *netmask, - const ip4_addr_t *gw) -{ - err_t err; - NETIFAPI_VAR_DECLARE(msg); - NETIFAPI_VAR_ALLOC(msg); - - if (ipaddr == NULL) { - ipaddr = IP4_ADDR_ANY4; - } - if (netmask == NULL) { - netmask = IP4_ADDR_ANY4; - } - if (gw == NULL) { - gw = IP4_ADDR_ANY4; - } - - NETIFAPI_VAR_REF(msg).netif = netif; - NETIFAPI_VAR_REF(msg).msg.add.ipaddr = NETIFAPI_VAR_REF(ipaddr); - NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask); - NETIFAPI_VAR_REF(msg).msg.add.gw = NETIFAPI_VAR_REF(gw); - err = tcpip_api_call(netifapi_do_netif_set_addr, &API_VAR_REF(msg).call); - NETIFAPI_VAR_FREE(msg); - return err; -} -#endif /* LWIP_IPV4 */ - -/** - * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe - * way by running that function inside the tcpip_thread context. - * - * @note use only for functions where there is only "netif" parameter. - */ -err_t -netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc, - netifapi_errt_fn errtfunc) -{ - err_t err; - NETIFAPI_VAR_DECLARE(msg); - NETIFAPI_VAR_ALLOC(msg); - - NETIFAPI_VAR_REF(msg).netif = netif; - NETIFAPI_VAR_REF(msg).msg.common.voidfunc = voidfunc; - NETIFAPI_VAR_REF(msg).msg.common.errtfunc = errtfunc; - err = tcpip_api_call(netifapi_do_netif_common, &API_VAR_REF(msg).call); - NETIFAPI_VAR_FREE(msg); - return err; -} - -#endif /* LWIP_NETIF_API */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/sockets.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/sockets.c deleted file mode 100644 index ee9a2f653191f6b52fa211d8228a0e9534c986b5..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/sockets.c +++ /dev/null @@ -1,2977 +0,0 @@ -/** - * @file - * Sockets BSD-Like API module - * - * @defgroup socket Socket API - * @ingroup sequential_api - * BSD-style socket API.\n - * Thread-safe, to be called from non-TCPIP threads only.\n - * Can be activated by defining @ref LWIP_SOCKET to 1.\n - * Header is in posix/sys/socket.h\b - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * Improved by Marc Boucher and David Haas - * - */ - -#include "lwip/opt.h" - -#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sockets.h" -#include "lwip/api.h" -#include "lwip/sys.h" -#include "lwip/igmp.h" -#include "lwip/inet.h" -#include "lwip/tcp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/errno.h" -#include "lwip/priv/tcpip_priv.h" -#include "lwip/priv/api_msg.h" - -#if LWIP_CHECKSUM_ON_COPY -#include "lwip/inet_chksum.h" -#endif - -#include - -/* If the netconn API is not required publicly, then we include the necessary - files here to get the implementation */ -#if !LWIP_NETCONN -#undef LWIP_NETCONN -#define LWIP_NETCONN 1 -#include "api_msg.c" -#include "api_lib.c" -#include "netbuf.c" -#undef LWIP_NETCONN -#define LWIP_NETCONN 0 -#endif - -#if LWIP_IPV4 -#define IP4ADDR_PORT_TO_SOCKADDR(sin, ipaddr, port) do { \ - (sin)->sin_len = sizeof(struct sockaddr_in); \ - (sin)->sin_family = AF_INET; \ - (sin)->sin_port = lwip_htons((port)); \ - inet_addr_from_ip4addr(&(sin)->sin_addr, ipaddr); \ - memset((sin)->sin_zero, 0, SIN_ZERO_LEN); }while(0) -#define SOCKADDR4_TO_IP4ADDR_PORT(sin, ipaddr, port) do { \ - inet_addr_to_ip4addr(ip_2_ip4(ipaddr), &((sin)->sin_addr)); \ - (port) = lwip_ntohs((sin)->sin_port); }while(0) -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -#define IP6ADDR_PORT_TO_SOCKADDR(sin6, ipaddr, port) do { \ - (sin6)->sin6_len = sizeof(struct sockaddr_in6); \ - (sin6)->sin6_family = AF_INET6; \ - (sin6)->sin6_port = lwip_htons((port)); \ - (sin6)->sin6_flowinfo = 0; \ - inet6_addr_from_ip6addr(&(sin6)->sin6_addr, ipaddr); \ - (sin6)->sin6_scope_id = 0; }while(0) -#define SOCKADDR6_TO_IP6ADDR_PORT(sin6, ipaddr, port) do { \ - inet6_addr_to_ip6addr(ip_2_ip6(ipaddr), &((sin6)->sin6_addr)); \ - (port) = lwip_ntohs((sin6)->sin6_port); }while(0) -#endif /* LWIP_IPV6 */ - -#if LWIP_IPV4 && LWIP_IPV6 -static void sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port); - -#define IS_SOCK_ADDR_LEN_VALID(namelen) (((namelen) == sizeof(struct sockaddr_in)) || \ - ((namelen) == sizeof(struct sockaddr_in6))) -#define IS_SOCK_ADDR_TYPE_VALID(name) (((name)->sa_family == AF_INET) || \ - ((name)->sa_family == AF_INET6)) -#define SOCK_ADDR_TYPE_MATCH(name, sock) \ - ((((name)->sa_family == AF_INET) && !(NETCONNTYPE_ISIPV6((sock)->conn->type))) || \ - (((name)->sa_family == AF_INET6) && (NETCONNTYPE_ISIPV6((sock)->conn->type)))) -#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) do { \ - if (IP_IS_V6(ipaddr)) { \ - IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port); \ - } else { \ - IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port); \ - } } while(0) -#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) sockaddr_to_ipaddr_port(sockaddr, ipaddr, &(port)) -#define DOMAIN_TO_NETCONN_TYPE(domain, type) (((domain) == AF_INET) ? \ - (type) : (enum netconn_type)((type) | NETCONN_TYPE_IPV6)) -#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ -#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in6)) -#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET6) -#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 -#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ - IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port) -#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ - SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, port) -#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) -#else /*-> LWIP_IPV4: LWIP_IPV4 && LWIP_IPV6 */ -#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in)) -#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET) -#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 -#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ - IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port) -#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ - SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, port) -#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) -#endif /* LWIP_IPV6 */ - -#define IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) (((name)->sa_family == AF_UNSPEC) || \ - IS_SOCK_ADDR_TYPE_VALID(name)) -#define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \ - SOCK_ADDR_TYPE_MATCH(name, sock)) -#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 4) == 0) - - -#define LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype) do { if ((optlen) < sizeof(opttype)) { return EINVAL; }}while(0) -#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, opttype) do { \ - LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ - if ((sock)->conn == NULL) { return EINVAL; } }while(0) -#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype) do { \ - LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ - if (((sock)->conn == NULL) || ((sock)->conn->pcb.tcp == NULL)) { return EINVAL; } }while(0) -#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, opttype, netconntype) do { \ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype); \ - if (NETCONNTYPE_GROUP(netconn_type((sock)->conn)) != netconntype) { return ENOPROTOOPT; } }while(0) - - -#define LWIP_SETGETSOCKOPT_DATA_VAR_REF(name) API_VAR_REF(name) -#define LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_setgetsockopt_data, name) -#define LWIP_SETGETSOCKOPT_DATA_VAR_FREE(name) API_VAR_FREE(MEMP_SOCKET_SETGETSOCKOPT_DATA, name) -#if LWIP_MPU_COMPATIBLE -#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) do { \ - name = (struct lwip_setgetsockopt_data *)memp_malloc(MEMP_SOCKET_SETGETSOCKOPT_DATA); \ - if (name == NULL) { \ - sock_set_errno(sock, ENOMEM); \ - return -1; \ - } }while(0) -#else /* LWIP_MPU_COMPATIBLE */ -#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) -#endif /* LWIP_MPU_COMPATIBLE */ - -#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD -#define LWIP_SO_SNDRCVTIMEO_OPTTYPE int -#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) (*(int *)(optval) = (val)) -#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((s32_t)*(const int*)(optval)) -#else -#define LWIP_SO_SNDRCVTIMEO_OPTTYPE struct timeval -#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) do { \ - s32_t loc = (val); \ - ((struct timeval *)(optval))->tv_sec = (loc) / 1000U; \ - ((struct timeval *)(optval))->tv_usec = ((loc) % 1000U) * 1000U; }while(0) -#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((((const struct timeval *)(optval))->tv_sec * 1000U) + (((const struct timeval *)(optval))->tv_usec / 1000U)) -#endif - -#define NUM_SOCKETS MEMP_NUM_NETCONN - -#ifndef SOCK_API_SYNC -#define SOCK_API_SYNC 1 -#endif - -/** This is overridable for the rare case where more than 255 threads - * select on the same socket... - */ -#ifndef SELWAIT_T -#define SELWAIT_T u8_t -#endif - -/** Contains all internal pointers and states used for a socket */ -struct lwip_sock { - /** sockets currently are built on netconns, each socket has one netconn */ - struct netconn *conn; - /** data that was left from the previous read */ - void *lastdata; - /** offset in the data that was left from the previous read */ - u16_t lastoffset; - /** number of times data was received, set by event_callback(), - tested by the receive and select functions */ - s16_t rcvevent; - /** number of times data was ACKed (free send buffer), set by event_callback(), - tested by select */ - u16_t sendevent; - /** error happened for this socket, set by event_callback(), tested by select */ - u16_t errevent; - /** last error that occurred on this socket (in fact, all our errnos fit into an u8_t) */ - u8_t err; - /** counter of how many threads are waiting for this socket using select */ - SELWAIT_T select_waiting; -#if SOCK_API_SYNC - /* closing is 0, when the socket is created. It is 1, when the function "close" is called, */ - /* and then send / recv function is not able to be called */ - int closing; - sys_mutex_t mutex_recv; - sys_mutex_t mutex_send; -#endif -}; - -#if LWIP_NETCONN_SEM_PER_THREAD -#define SELECT_SEM_T sys_sem_t* -#define SELECT_SEM_PTR(sem) (sem) -#else /* LWIP_NETCONN_SEM_PER_THREAD */ -#define SELECT_SEM_T sys_sem_t -#define SELECT_SEM_PTR(sem) (&(sem)) -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - -/** Description for a task waiting in select */ -struct lwip_select_cb { - /** Pointer to the next waiting task */ - struct lwip_select_cb *next; - /** Pointer to the previous waiting task */ - struct lwip_select_cb *prev; - /** readset passed to select */ - fd_set *readset; - /** writeset passed to select */ - fd_set *writeset; - /** unimplemented: exceptset passed to select */ - fd_set *exceptset; - /** don't signal the same semaphore twice: set to 1 when signalled */ - int sem_signalled; - /** semaphore to wake up a task waiting for select */ - SELECT_SEM_T sem; -}; - -/** A struct sockaddr replacement that has the same alignment as sockaddr_in/ - * sockaddr_in6 if instantiated. - */ -union sockaddr_aligned { - struct sockaddr sa; -#if LWIP_IPV6 - struct sockaddr_in6 sin6; -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 - struct sockaddr_in sin; -#endif /* LWIP_IPV4 */ -}; - -#if LWIP_IGMP -/* Define the number of IPv4 multicast memberships, default is one per socket */ -#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS -#define LWIP_SOCKET_MAX_MEMBERSHIPS NUM_SOCKETS -#endif - -/* This is to keep track of IP_ADD_MEMBERSHIP calls to drop the membership when - a socket is closed */ -struct lwip_socket_multicast_pair { - /** the socket */ - struct lwip_sock* sock; - /** the interface address */ - ip4_addr_t if_addr; - /** the group address */ - ip4_addr_t multi_addr; -}; - -struct lwip_socket_multicast_pair socket_ipv4_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; - -static int lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); -static void lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); -static void lwip_socket_drop_registered_memberships(int s); -#endif /* LWIP_IGMP */ - -/** The global array of available sockets */ -static struct lwip_sock sockets[NUM_SOCKETS]; -/** The global list of tasks waiting for select */ -static struct lwip_select_cb *select_cb_list; -/** This counter is increased from lwip_select when the list is changed - and checked in event_callback to see if it has changed. */ -static volatile int select_cb_ctr; - -#if LWIP_SOCKET_SET_ERRNO -#ifndef set_errno -#define set_errno(err) do { if (err) { errno = (err); } } while(0) -#endif -#else /* LWIP_SOCKET_SET_ERRNO */ -#define set_errno(err) -#endif /* LWIP_SOCKET_SET_ERRNO */ - -#define sock_set_errno(sk, e) do { \ - const int sockerr = (e); \ - sk->err = (u8_t)sockerr; \ - set_errno(sockerr); \ -} while (0) - - /* add the function for socket API sync between threads */ -#if SOCK_API_SYNC -#define SOCK_DEBUG(level, ...) \ - if (level > 2) printf(__VA_ARGS__); - -#define SOCK_INIT_CLOSING_SIG(sock) do { \ - (sock)->closing = 0; \ - SOCK_DEBUG(1, "SOCK_INIT_CLOSING_SIG:[%d]\n", (sock)->closing); \ - } while (0) - -#define SOC_DEINIT_SYNC(sock) do { \ - sys_mutex_free(&(sock)->mutex_recv); \ - sys_mutex_free(&(sock)->mutex_send); \ - SOCK_DEBUG(1, "SOC_DEINIT_SYNC OK!\n"); \ - } while (0) - -#define SOCK_START_CLOSING(sock) do { \ - (sock)->closing = 1; \ - SOCK_DEBUG(1, "SOCK_START_CLOSING:[%d]\n", (sock)->closing); \ - } while (0) - -#define SOCK_CHECK_NOT_CLOSING(sock) do { \ - if ((sock)->closing) { \ - SOCK_DEBUG(1, "SOCK_CHECK_NOT_CLOSING:[%d]\n", (sock)->closing); \ - return -1; \ - } \ - } while (0) - -#define SOCK_WAIT() do { \ - extern void sys_arch_msleep(int ms); \ - sys_arch_msleep(50); \ - SOCK_DEBUG(1, "SOCK_WAIT_FOR_10MS\n"); \ - } while (0); -/* place lwip_socket */ -#define SOC_INIT_SYNC(sock) do { \ - SOCK_INIT_CLOSING_SIG(sock); \ - if (sys_mutex_new(&(sock)->mutex_recv)) return -1; \ - if (sys_mutex_new(&(sock)->mutex_send)) { \ - sys_mutex_free(&(sock)->mutex_recv); \ - return -1; \ - } \ - SOCK_DEBUG(1, "SOC_INIT_SYNC OK!\n"); \ -} while (0) - -/* place in lwip_recv*/ -#define SOCK_RECV_LOCK(sock) do { \ - SOCK_CHECK_NOT_CLOSING(sock); \ - sys_mutex_lock(&sock->mutex_recv); \ - SOCK_DEBUG(1, "SOCK_RECV_LOCK\n"); \ -} while (0) - -/* place in lwip_recv*/ -#define SOCK_RECV_UNLOCK(sock) do { \ - sys_mutex_unlock(&sock->mutex_recv); \ - SOCK_DEBUG(1, "SOCK_RECV_UNLOCK\n"); \ -} while (0) - -/* place in lwip_send */ -#define SOCK_SEND_LOCK(sock) do { \ - SOCK_CHECK_NOT_CLOSING(sock); \ - sys_mutex_lock(&sock->mutex_send); \ - SOCK_DEBUG(1, "SOCK_SEND_LOCK\n"); \ -} while (0) - -/* place in lwip_send */ -#define SOCK_SEND_UNLOCK(sock) do { \ - sys_mutex_unlock(&sock->mutex_send); \ - SOCK_DEBUG(1, "SOCK_SEND_UNLOCK\n"); \ -} while (0) - -/* place in lwip_close */ -#define SOCK_DEINIT_SYNC(sock) do { \ - SOCK_CHECK_NOT_CLOSING(sock); \ - SOCK_START_CLOSING(sock); \ - if (0 > sock_wait_to_be_idle(sock)) return -1; \ - SOC_DEINIT_SYNC(sock); \ - SOCK_DEBUG(1, "SOCK_WAIT_TO_BE_IDLE\n"); \ -} while (0); - -static int sock_wait_to_be_idle(struct lwip_sock *sock) -{ - int recving = 1, sending = 1; - int count = 10; - - /* wait for 500ms */ - while (count--) { - if (recving) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("sock_wait_to_be_idle: free recv semphore.\n")); - if (!sys_mutex_trylock(&sock->mutex_recv)) recving = 0; - else sys_mbox_trypost(&sock->conn->recvmbox, NULL); - } - - if (sending) { - if (!sys_mutex_trylock(&sock->mutex_send)) sending = 0; - else { - LWIP_DEBUGF(SOCKETS_DEBUG, ("sock_wait_to_be_idle: free send semphore.\n")); - if (sys_sem_valid(&(sock->conn->op_completed))) { - sock->conn->current_msg->err = ERR_OK; - sock->conn->current_msg = NULL; - sock->conn->state = NETCONN_NONE; - sys_sem_signal(&(sock->conn->op_completed)); - } - } - } - - if (!recving && !sending) return 0; - - SOCK_WAIT(); - } - - return count; -} -#else -#define SOC_INIT_SYNC(sock) - -#define SOCK_RECV_LOCK(sock) -#define SOCK_RECV_UNLOCK(sock) -#define SOCK_SEND_LOCK(sock) -#define SOCK_SEND_UNLOCK(sock) - -#define SOCK_DEINIT_SYNC(sock) -#endif - -/* Forward declaration of some functions */ -static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); -#if !LWIP_TCPIP_CORE_LOCKING -static void lwip_getsockopt_callback(void *arg); -static void lwip_setsockopt_callback(void *arg); -#endif -static u8_t lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen); -static u8_t lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen); - -#if LWIP_IPV4 && LWIP_IPV6 -static void -sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port) -{ - if ((sockaddr->sa_family) == AF_INET6) { - SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, *port); - ipaddr->type = IPADDR_TYPE_V6; - } else { - SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, *port); - ipaddr->type = IPADDR_TYPE_V4; - } -} -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -/** LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ -void -lwip_socket_thread_init(void) -{ - netconn_thread_init(); -} - -/** LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ -void -lwip_socket_thread_cleanup(void) -{ - netconn_thread_cleanup(); -} - -/** - * Map a externally used socket index to the internal socket representation. - * - * @param s externally used socket index - * @return struct lwip_sock for the socket or NULL if not found - */ -static struct lwip_sock * -get_socket(int s) -{ - struct lwip_sock *sock; - - s -= LWIP_SOCKET_OFFSET; - - if ((s < 0) || (s >= NUM_SOCKETS)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s + LWIP_SOCKET_OFFSET)); - set_errno(EBADF); - return NULL; - } - - sock = &sockets[s]; - - if (!sock->conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s + LWIP_SOCKET_OFFSET)); - set_errno(EBADF); - return NULL; - } - - return sock; -} - -/** - * Same as get_socket but doesn't set errno - * - * @param s externally used socket index - * @return struct lwip_sock for the socket or NULL if not found - */ -static struct lwip_sock * -tryget_socket(int s) -{ - s -= LWIP_SOCKET_OFFSET; - if ((s < 0) || (s >= NUM_SOCKETS)) { - return NULL; - } - if (!sockets[s].conn) { - return NULL; - } - return &sockets[s]; -} - -/** - * Allocate a new socket for a given netconn. - * - * @param newconn the netconn for which to allocate a socket - * @param accepted 1 if socket has been created by accept(), - * 0 if socket has been created by socket() - * @return the index of the new socket; -1 on error - */ -static int -alloc_socket(struct netconn *newconn, int accepted) -{ - int i; - SYS_ARCH_DECL_PROTECT(lev); - - /* allocate a new socket identifier */ - for (i = 0; i < NUM_SOCKETS; ++i) { - /* Protect socket array */ - SYS_ARCH_PROTECT(lev); - if (!sockets[i].conn && (sockets[i].select_waiting == 0)) { - sockets[i].conn = newconn; - /* The socket is not yet known to anyone, so no need to protect - after having marked it as used. */ - SYS_ARCH_UNPROTECT(lev); - sockets[i].lastdata = NULL; - sockets[i].lastoffset = 0; - sockets[i].rcvevent = 0; - /* TCP sendbuf is empty, but the socket is not yet writable until connected - * (unless it has been created by accept()). */ - sockets[i].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); - sockets[i].errevent = 0; - sockets[i].err = 0; - SOC_INIT_SYNC(&sockets[i]); - return i + LWIP_SOCKET_OFFSET; - } - SYS_ARCH_UNPROTECT(lev); - } - return -1; -} - -/** Free a socket. The socket's netconn must have been - * delete before! - * - * @param sock the socket to free - * @param is_tcp != 0 for TCP sockets, used to free lastdata - */ -static void -free_socket(struct lwip_sock *sock, int is_tcp) -{ - void *lastdata; - - lastdata = sock->lastdata; - sock->lastdata = NULL; - sock->lastoffset = 0; - sock->err = 0; - - /* Protect socket array */ - SYS_ARCH_SET(sock->conn, NULL); - /* don't use 'sock' after this line, as another task might have allocated it */ - - if (lastdata != NULL) { - if (is_tcp) { - pbuf_free((struct pbuf *)lastdata); - } else { - netbuf_delete((struct netbuf *)lastdata); - } - } -} - -/* Below this, the well-known socket functions are implemented. - * Use google.com or opengroup.org to get a good description :-) - * - * Exceptions are documented! - */ - -int -lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) -{ - struct lwip_sock *sock, *nsock; - struct netconn *newconn; - ip_addr_t naddr; - u16_t port = 0; - int newsock; - err_t err; - SYS_ARCH_DECL_PROTECT(lev); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); - sock = get_socket(s); - if (!sock) { - return -1; - } - - if (netconn_is_nonblocking(sock->conn) && (sock->rcvevent <= 0)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s)); - set_errno(EWOULDBLOCK); - return -1; - } - - /* wait for a new connection */ - err = netconn_accept(sock->conn, &newconn); - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err)); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { - sock_set_errno(sock, EOPNOTSUPP); - } else if (err == ERR_CLSD) { - sock_set_errno(sock, EINVAL); - } else { - sock_set_errno(sock, err_to_errno(err)); - } - return -1; - } - LWIP_ASSERT("newconn != NULL", newconn != NULL); - - newsock = alloc_socket(newconn, 1); - if (newsock == -1) { - netconn_delete(newconn); - sock_set_errno(sock, ENFILE); - return -1; - } - LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET)); - LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); - nsock = &sockets[newsock - LWIP_SOCKET_OFFSET]; - - /* See event_callback: If data comes in right away after an accept, even - * though the server task might not have created a new socket yet. - * In that case, newconn->socket is counted down (newconn->socket--), - * so nsock->rcvevent is >= 1 here! - */ - SYS_ARCH_PROTECT(lev); - nsock->rcvevent += (s16_t)(-1 - newconn->socket); - newconn->socket = newsock; - SYS_ARCH_UNPROTECT(lev); - - /* Note that POSIX only requires us to check addr is non-NULL. addrlen must - * not be NULL if addr is valid. - */ - if (addr != NULL) { - union sockaddr_aligned tempaddr; - /* get the IP address and port of the remote host */ - err = netconn_peer(newconn, &naddr, &port); - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err)); - netconn_delete(newconn); - free_socket(nsock, 1); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL); - - IPADDR_PORT_TO_SOCKADDR(&tempaddr, &naddr, port); - if (*addrlen > tempaddr.sa.sa_len) { - *addrlen = tempaddr.sa.sa_len; - } - MEMCPY(addr, &tempaddr, *addrlen); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); - ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); - } else { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d", s, newsock)); - } - - sock_set_errno(sock, 0); - return newsock; -} - -int -lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) -{ - struct lwip_sock *sock; - ip_addr_t local_addr; - u16_t local_port; - err_t err; - - sock = get_socket(s); - if (!sock) { - return -1; - } - - if (!SOCK_ADDR_TYPE_MATCH(name, sock)) { - /* sockaddr does not match socket type (IPv4/IPv6) */ - sock_set_errno(sock, err_to_errno(ERR_VAL)); - return -1; - } - - /* check size, family and alignment of 'name' */ - LWIP_ERROR("lwip_bind: invalid address", (IS_SOCK_ADDR_LEN_VALID(namelen) && - IS_SOCK_ADDR_TYPE_VALID(name) && IS_SOCK_ADDR_ALIGNED(name)), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - LWIP_UNUSED_ARG(namelen); - - SOCKADDR_TO_IPADDR_PORT(name, &local_addr, local_port); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); - ip_addr_debug_print_val(SOCKETS_DEBUG, local_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", local_port)); - -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ - if (IP_IS_V6_VAL(local_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&local_addr))) { - unmap_ipv4_mapped_ipv6(ip_2_ip4(&local_addr), ip_2_ip6(&local_addr)); - IP_SET_TYPE_VAL(local_addr, IPADDR_TYPE_V4); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - err = netconn_bind(sock->conn, &local_addr, local_port); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_close(int s) -{ - struct lwip_sock *sock; - int is_tcp = 0; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); - - sock = get_socket(s); - if (!sock) { - return -1; - } - SOCK_DEINIT_SYNC(sock); - - if (sock->conn != NULL) { - is_tcp = NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP; - } else { - LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata == NULL); - } - -#if LWIP_IGMP - /* drop all possibly joined IGMP memberships */ - lwip_socket_drop_registered_memberships(s); -#endif /* LWIP_IGMP */ - - err = netconn_delete(sock->conn); - if (err != ERR_OK) { - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - free_socket(sock, is_tcp); - set_errno(0); - return 0; -} - -int -lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) -{ - struct lwip_sock *sock; - err_t err; - - sock = get_socket(s); - if (!sock) { - return -1; - } - - if (!SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock)) { - /* sockaddr does not match socket type (IPv4/IPv6) */ - sock_set_errno(sock, err_to_errno(ERR_VAL)); - return -1; - } - - LWIP_UNUSED_ARG(namelen); - if (name->sa_family == AF_UNSPEC) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); - err = netconn_disconnect(sock->conn); - } else { - ip_addr_t remote_addr; - u16_t remote_port; - - /* check size, family and alignment of 'name' */ - LWIP_ERROR("lwip_connect: invalid address", IS_SOCK_ADDR_LEN_VALID(namelen) && - IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) && IS_SOCK_ADDR_ALIGNED(name), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - SOCKADDR_TO_IPADDR_PORT(name, &remote_addr, remote_port); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); - ip_addr_debug_print_val(SOCKETS_DEBUG, remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", remote_port)); - -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ - if (IP_IS_V6_VAL(remote_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&remote_addr))) { - unmap_ipv4_mapped_ipv6(ip_2_ip4(&remote_addr), ip_2_ip6(&remote_addr)); - IP_SET_TYPE_VAL(remote_addr, IPADDR_TYPE_V4); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - err = netconn_connect(sock->conn, &remote_addr, remote_port); - } - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -/** - * Set a socket into listen mode. - * The socket may not have been used for another connection previously. - * - * @param s the socket to set to listening mode - * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1) - * @return 0 on success, non-zero on failure - */ -int -lwip_listen(int s, int backlog) -{ - struct lwip_sock *sock; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); - - sock = get_socket(s); - if (!sock) { - return -1; - } - - /* limit the "backlog" parameter to fit in an u8_t */ - backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff); - - err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { - sock_set_errno(sock, EOPNOTSUPP); - return -1; - } - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_recvfrom(int s, void *mem, size_t len, int flags, - struct sockaddr *from, socklen_t *fromlen) -{ - struct lwip_sock *sock; - void *buf = NULL; - struct pbuf *p; - u16_t buflen, copylen; - int off = 0; - u8_t done = 0; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); - sock = get_socket(s); - if (!sock) { - return -1; - } - - SOCK_RECV_LOCK(sock); - do { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", sock->lastdata)); - /* Check if there is data left from the last recv operation. */ - if (sock->lastdata) { - buf = sock->lastdata; - } else { - /* If this is non-blocking call, then check first */ - if (((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) && - (sock->rcvevent <= 0)) { - if (off > 0) { - /* already received data, return that */ - sock_set_errno(sock, 0); - SOCK_RECV_UNLOCK(sock); - return off; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); - set_errno(EWOULDBLOCK); - SOCK_RECV_UNLOCK(sock); - return -1; - } - - /* No data was left from the previous operation, so we try to get - some from the network. */ - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { - err = netconn_recv_tcp_pbuf(sock->conn, (struct pbuf **)&buf); - } else { - err = netconn_recv(sock->conn, (struct netbuf **)&buf); - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv err=%d, netbuf=%p\n", - err, buf)); - - if (err != ERR_OK) { - if (off > 0) { - if (err == ERR_CLSD) { - /* closed but already received data, ensure select gets the FIN, too */ - event_callback(sock->conn, NETCONN_EVT_RCVPLUS, 0); - } - /* already received data, return that */ - sock_set_errno(sock, 0); - SOCK_RECV_UNLOCK(sock); - return off; - } - /* We should really do some error checking here. */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL, error is \"%s\"!\n", - s, lwip_strerr(err))); - sock_set_errno(sock, err_to_errno(err)); - if (err == ERR_CLSD) { - SOCK_RECV_UNLOCK(sock); - return 0; - } else { - SOCK_RECV_UNLOCK(sock); - return -1; - } - } - LWIP_ASSERT("buf != NULL", buf != NULL); - sock->lastdata = buf; - } - - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { - p = (struct pbuf *)buf; - } else { - p = ((struct netbuf *)buf)->p; - } - buflen = p->tot_len; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%d sock->lastoffset=%"U16_F"\n", - buflen, len, off, sock->lastoffset)); - - buflen -= sock->lastoffset; - - if (len > buflen) { - copylen = buflen; - } else { - copylen = (u16_t)len; - } - - /* copy the contents of the received buffer into - the supplied memory pointer mem */ - pbuf_copy_partial(p, (u8_t*)mem + off, copylen, sock->lastoffset); - - off += copylen; - - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { - LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen); - len -= copylen; - if ((len <= 0) || - (p->flags & PBUF_FLAG_PUSH) || - (sock->rcvevent <= 0) || - ((flags & MSG_PEEK) != 0)) { - done = 1; - } - } else { - done = 1; - } - - /* Check to see from where the data was.*/ - if (done) { -#if !SOCKETS_DEBUG - if (from && fromlen) -#endif /* !SOCKETS_DEBUG */ - { - u16_t port; - ip_addr_t tmpaddr; - ip_addr_t *fromaddr; - union sockaddr_aligned saddr; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { - fromaddr = &tmpaddr; - netconn_getaddr(sock->conn, fromaddr, &port, 0); - } else { - port = netbuf_fromport((struct netbuf *)buf); - fromaddr = netbuf_fromaddr((struct netbuf *)buf); - } - -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ - if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && IP_IS_V4(fromaddr)) { - ip4_2_ipv4_mapped_ipv6(ip_2_ip6(fromaddr), ip_2_ip4(fromaddr)); - IP_SET_TYPE(fromaddr, IPADDR_TYPE_V6); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - IPADDR_PORT_TO_SOCKADDR(&saddr, fromaddr, port); - ip_addr_debug_print(SOCKETS_DEBUG, fromaddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off)); -#if SOCKETS_DEBUG - if (from && fromlen) -#endif /* SOCKETS_DEBUG */ - { - if (*fromlen > saddr.sa.sa_len) { - *fromlen = saddr.sa.sa_len; - } - MEMCPY(from, &saddr, *fromlen); - } - } - } - - /* If we don't peek the incoming message... */ - if ((flags & MSG_PEEK) == 0) { - /* If this is a TCP socket, check if there is data left in the - buffer. If so, it should be saved in the sock structure for next - time around. */ - if ((NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) && (buflen - copylen > 0)) { - sock->lastdata = buf; - sock->lastoffset += copylen; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", buf)); - } else { - sock->lastdata = NULL; - sock->lastoffset = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", buf)); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { - pbuf_free((struct pbuf *)buf); - } else { - netbuf_delete((struct netbuf *)buf); - } - buf = NULL; - } - } - } while (!done); - - sock_set_errno(sock, 0); - SOCK_RECV_UNLOCK(sock); - return off; -} - -int -lwip_read(int s, void *mem, size_t len) -{ - return lwip_recvfrom(s, mem, len, 0, NULL, NULL); -} - -int -lwip_recv(int s, void *mem, size_t len, int flags) -{ - return lwip_recvfrom(s, mem, len, flags, NULL, NULL); -} - -int -lwip_send(int s, const void *data, size_t size, int flags) -{ - struct lwip_sock *sock; - err_t err; - u8_t write_flags; - size_t written; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", - s, data, size, flags)); - - sock = get_socket(s); - if (!sock) { - return -1; - } - - SOCK_SEND_LOCK(sock); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { -#if (LWIP_UDP || LWIP_RAW) - SOCK_SEND_UNLOCK(sock); - return lwip_sendto(s, data, size, flags, NULL, 0); -#else /* (LWIP_UDP || LWIP_RAW) */ - sock_set_errno(sock, err_to_errno(ERR_ARG)); - SOCK_SEND_UNLOCK(sock); - return -1; -#endif /* (LWIP_UDP || LWIP_RAW) */ - } - - write_flags = NETCONN_COPY | - ((flags & MSG_MORE) ? NETCONN_MORE : 0) | - ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); - written = 0; - err = netconn_write_partly(sock->conn, data, size, write_flags, &written); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d written=%"SZT_F"\n", s, err, written)); - sock_set_errno(sock, err_to_errno(err)); - SOCK_SEND_UNLOCK(sock); - return (err == ERR_OK ? (int)written : -1); -} - -int -lwip_sendmsg(int s, const struct msghdr *msg, int flags) -{ - struct lwip_sock *sock; - int i; -#if LWIP_TCP - u8_t write_flags; - size_t written; -#endif - int size = 0; - err_t err = ERR_OK; - - sock = get_socket(s); - if (!sock) { - return -1; - } - - LWIP_ERROR("lwip_sendmsg: invalid msghdr", msg != NULL, - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - LWIP_UNUSED_ARG(msg->msg_control); - LWIP_UNUSED_ARG(msg->msg_controllen); - LWIP_UNUSED_ARG(msg->msg_flags); - LWIP_ERROR("lwip_sendmsg: invalid msghdr iov", (msg->msg_iov != NULL && msg->msg_iovlen != 0), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { -#if LWIP_TCP - write_flags = NETCONN_COPY | - ((flags & MSG_MORE) ? NETCONN_MORE : 0) | - ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); - - for (i = 0; i < msg->msg_iovlen; i++) { - u8_t apiflags = write_flags; - if (i + 1 < msg->msg_iovlen) { - apiflags |= NETCONN_MORE; - } - written = 0; - err = netconn_write_partly(sock->conn, msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len, write_flags, &written); - if (err == ERR_OK) { - size += written; - /* check that the entire IO vector was accepected, if not return a partial write */ - if (written != msg->msg_iov[i].iov_len) - break; - } - /* none of this IO vector was accepted, but previous was, return partial write and conceal ERR_WOULDBLOCK */ - else if (err == ERR_WOULDBLOCK && size > 0) { - err = ERR_OK; - /* let ERR_WOULDBLOCK persist on the netconn since we are returning ERR_OK */ - break; - } else { - size = -1; - break; - } - } - sock_set_errno(sock, err_to_errno(err)); - return size; -#else /* LWIP_TCP */ - sock_set_errno(sock, err_to_errno(ERR_ARG)); - return -1; -#endif /* LWIP_TCP */ - } - /* else, UDP and RAW NETCONNs */ -#if LWIP_UDP || LWIP_RAW - { - struct netbuf *chain_buf; - - LWIP_UNUSED_ARG(flags); - LWIP_ERROR("lwip_sendmsg: invalid msghdr name", (((msg->msg_name == NULL) && (msg->msg_namelen == 0)) || - IS_SOCK_ADDR_LEN_VALID(msg->msg_namelen)) , - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - /* initialize chain buffer with destination */ - chain_buf = netbuf_new(); - if (!chain_buf) { - sock_set_errno(sock, err_to_errno(ERR_MEM)); - return -1; - } - if (msg->msg_name) { - u16_t remote_port; - SOCKADDR_TO_IPADDR_PORT((const struct sockaddr *)msg->msg_name, &chain_buf->addr, remote_port); - netbuf_fromport(chain_buf) = remote_port; - } -#if LWIP_NETIF_TX_SINGLE_PBUF - for (i = 0; i < msg->msg_iovlen; i++) { - size += msg->msg_iov[i].iov_len; - } - /* Allocate a new netbuf and copy the data into it. */ - if (netbuf_alloc(chain_buf, (u16_t)size) == NULL) { - err = ERR_MEM; - } else { - /* flatten the IO vectors */ - size_t offset = 0; - for (i = 0; i < msg->msg_iovlen; i++) { - MEMCPY(&((u8_t*)chain_buf->p->payload)[offset], msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len); - offset += msg->msg_iov[i].iov_len; - } -#if LWIP_CHECKSUM_ON_COPY - { - /* This can be improved by using LWIP_CHKSUM_COPY() and aggregating the checksum for each IO vector */ - u16_t chksum = ~inet_chksum_pbuf(chain_buf->p); - netbuf_set_chksum(chain_buf, chksum); - } -#endif /* LWIP_CHECKSUM_ON_COPY */ - err = ERR_OK; - } -#else /* LWIP_NETIF_TX_SINGLE_PBUF */ - /* create a chained netbuf from the IO vectors. NOTE: we assemble a pbuf chain - manually to avoid having to allocate, chain, and delete a netbuf for each iov */ - for (i = 0; i < msg->msg_iovlen; i++) { - struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); - if (p == NULL) { - err = ERR_MEM; /* let netbuf_delete() cleanup chain_buf */ - break; - } - p->payload = msg->msg_iov[i].iov_base; - LWIP_ASSERT("iov_len < u16_t", msg->msg_iov[i].iov_len <= 0xFFFF); - p->len = p->tot_len = (u16_t)msg->msg_iov[i].iov_len; - /* netbuf empty, add new pbuf */ - if (chain_buf->p == NULL) { - chain_buf->p = chain_buf->ptr = p; - /* add pbuf to existing pbuf chain */ - } else { - pbuf_cat(chain_buf->p, p); - } - } - /* save size of total chain */ - if (err == ERR_OK) { - size = netbuf_len(chain_buf); - } -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - - if (err == ERR_OK) { -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ - if (IP_IS_V6_VAL(chain_buf->addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&chain_buf->addr))) { - unmap_ipv4_mapped_ipv6(ip_2_ip4(&chain_buf->addr), ip_2_ip6(&chain_buf->addr)); - IP_SET_TYPE_VAL(chain_buf->addr, IPADDR_TYPE_V4); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - /* send the data */ - err = netconn_send(sock->conn, chain_buf); - } - - /* deallocated the buffer */ - netbuf_delete(chain_buf); - - sock_set_errno(sock, err_to_errno(err)); - return (err == ERR_OK ? size : -1); - } -#else /* LWIP_UDP || LWIP_RAW */ - sock_set_errno(sock, err_to_errno(ERR_ARG)); - return -1; -#endif /* LWIP_UDP || LWIP_RAW */ -} - -int -lwip_sendto(int s, const void *data, size_t size, int flags, - const struct sockaddr *to, socklen_t tolen) -{ - struct lwip_sock *sock; - err_t err; - u16_t short_size; - u16_t remote_port; - struct netbuf buf; - - sock = get_socket(s); - if (!sock) { - return -1; - } - - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { -#if LWIP_TCP - return lwip_send(s, data, size, flags); -#else /* LWIP_TCP */ - LWIP_UNUSED_ARG(flags); - sock_set_errno(sock, err_to_errno(ERR_ARG)); - return -1; -#endif /* LWIP_TCP */ - } - - /* @todo: split into multiple sendto's? */ - LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff); - short_size = (u16_t)size; - LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || - (IS_SOCK_ADDR_LEN_VALID(tolen) && - IS_SOCK_ADDR_TYPE_VALID(to) && IS_SOCK_ADDR_ALIGNED(to))), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - LWIP_UNUSED_ARG(tolen); - - /* initialize a buffer */ - buf.p = buf.ptr = NULL; -#if LWIP_CHECKSUM_ON_COPY - buf.flags = 0; -#endif /* LWIP_CHECKSUM_ON_COPY */ - if (to) { - SOCKADDR_TO_IPADDR_PORT(to, &buf.addr, remote_port); - } else { - remote_port = 0; - ip_addr_set_any(NETCONNTYPE_ISIPV6(netconn_type(sock->conn)), &buf.addr); - } - netbuf_fromport(&buf) = remote_port; - - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=", - s, data, short_size, flags)); - ip_addr_debug_print(SOCKETS_DEBUG, &buf.addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); - - /* make the buffer point to the data that should be sent */ -#if LWIP_NETIF_TX_SINGLE_PBUF - /* Allocate a new netbuf and copy the data into it. */ - if (netbuf_alloc(&buf, short_size) == NULL) { - err = ERR_MEM; - } else { -#if LWIP_CHECKSUM_ON_COPY - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_RAW) { - u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size); - netbuf_set_chksum(&buf, chksum); - } else -#endif /* LWIP_CHECKSUM_ON_COPY */ - { - MEMCPY(buf.p->payload, data, short_size); - } - err = ERR_OK; - } -#else /* LWIP_NETIF_TX_SINGLE_PBUF */ - err = netbuf_ref(&buf, data, short_size); -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - if (err == ERR_OK) { -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ - if (IP_IS_V6_VAL(buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&buf.addr))) { - unmap_ipv4_mapped_ipv6(ip_2_ip4(&buf.addr), ip_2_ip6(&buf.addr)); - IP_SET_TYPE_VAL(buf.addr, IPADDR_TYPE_V4); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - /* send the data */ - err = netconn_send(sock->conn, &buf); - } - - /* deallocated the buffer */ - netbuf_free(&buf); - - sock_set_errno(sock, err_to_errno(err)); - return (err == ERR_OK ? short_size : -1); -} - -int -lwip_socket(int domain, int type, int protocol) -{ - struct netconn *conn; - int i; - - LWIP_UNUSED_ARG(domain); /* @todo: check this */ - - /* create a netconn */ - switch (type) { - case SOCK_RAW: - conn = netconn_new_with_proto_and_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_RAW), - (u8_t)protocol, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_DGRAM: - conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, - ((protocol == IPPROTO_UDPLITE) ? NETCONN_UDPLITE : NETCONN_UDP)) , - event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_STREAM: - conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_TCP), event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", - domain, type, protocol)); - set_errno(EINVAL); - return -1; - } - - if (!conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); - set_errno(ENOBUFS); - return -1; - } - - i = alloc_socket(conn, 0); - - if (i == -1) { - netconn_delete(conn); - set_errno(ENFILE); - return -1; - } - conn->socket = i; - LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); - set_errno(0); - return i; -} - -int -lwip_write(int s, const void *data, size_t size) -{ - return lwip_send(s, data, size, 0); -} - -int -lwip_writev(int s, const struct iovec *iov, int iovcnt) -{ - struct msghdr msg; - - msg.msg_name = NULL; - msg.msg_namelen = 0; - /* Hack: we have to cast via number to cast from 'const' pointer to non-const. - Blame the opengroup standard for this inconsistency. */ - msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov); - msg.msg_iovlen = iovcnt; - msg.msg_control = NULL; - msg.msg_controllen = 0; - msg.msg_flags = 0; - return lwip_sendmsg(s, &msg, 0); -} - -/** - * Go through the readset and writeset lists and see which socket of the sockets - * set in the sets has events. On return, readset, writeset and exceptset have - * the sockets enabled that had events. - * - * @param maxfdp1 the highest socket index in the sets - * @param readset_in set of sockets to check for read events - * @param writeset_in set of sockets to check for write events - * @param exceptset_in set of sockets to check for error events - * @param readset_out set of sockets that had read events - * @param writeset_out set of sockets that had write events - * @param exceptset_out set os sockets that had error events - * @return number of sockets that had events (read/write/exception) (>= 0) - */ -static int -lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in, - fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out) -{ - int i, nready = 0; - fd_set lreadset, lwriteset, lexceptset; - struct lwip_sock *sock; - SYS_ARCH_DECL_PROTECT(lev); - - FD_ZERO(&lreadset); - FD_ZERO(&lwriteset); - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { - /* if this FD is not in the set, continue */ - if (!(readset_in && FD_ISSET(i, readset_in)) && - !(writeset_in && FD_ISSET(i, writeset_in)) && - !(exceptset_in && FD_ISSET(i, exceptset_in))) { - continue; - } - /* First get the socket's status (protected)... */ - SYS_ARCH_PROTECT(lev); - sock = tryget_socket(i); - if (sock != NULL) { - void* lastdata = sock->lastdata; - s16_t rcvevent = sock->rcvevent; - u16_t sendevent = sock->sendevent; - u16_t errevent = sock->errevent; - SYS_ARCH_UNPROTECT(lev); - - /* ... then examine it: */ - /* See if netconn of this socket is ready for read */ - if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) { - FD_SET(i, &lreadset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); - nready++; - } - /* See if netconn of this socket is ready for write */ - if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) { - FD_SET(i, &lwriteset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); - nready++; - } - /* See if netconn of this socket had an error */ - if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) { - FD_SET(i, &lexceptset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i)); - nready++; - } - } else { - SYS_ARCH_UNPROTECT(lev); - /* continue on to next FD in list */ - } - } - /* copy local sets to the ones provided as arguments */ - *readset_out = lreadset; - *writeset_out = lwriteset; - *exceptset_out = lexceptset; - - LWIP_ASSERT("nready >= 0", nready >= 0); - return nready; -} - -int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout) -{ - u32_t waitres = 0; - int nready; - fd_set lreadset, lwriteset, lexceptset; - u32_t msectimeout; - struct lwip_select_cb select_cb; - int i; - int maxfdp2; -#if LWIP_NETCONN_SEM_PER_THREAD - int waited = 0; -#endif - SYS_ARCH_DECL_PROTECT(lev); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n", - maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, - timeout ? (s32_t)timeout->tv_sec : (s32_t)-1, - timeout ? (s32_t)timeout->tv_usec : (s32_t)-1)); - - /* Go through each socket in each list to count number of sockets which - currently match */ - nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); - - /* If we don't have any current events, then suspend if we are supposed to */ - if (!nready) { - if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); - /* This is OK as the local fdsets are empty and nready is zero, - or we would have returned earlier. */ - goto return_copy_fdsets; - } - - /* None ready: add our semaphore to list: - We don't actually need any dynamic memory. Our entry on the - list is only valid while we are in this function, so it's ok - to use local variables. */ - - select_cb.next = NULL; - select_cb.prev = NULL; - select_cb.readset = readset; - select_cb.writeset = writeset; - select_cb.exceptset = exceptset; - select_cb.sem_signalled = 0; -#if LWIP_NETCONN_SEM_PER_THREAD - select_cb.sem = LWIP_NETCONN_THREAD_SEM_GET(); -#else /* LWIP_NETCONN_SEM_PER_THREAD */ - if (sys_sem_new(&select_cb.sem, 0) != ERR_OK) { - /* failed to create semaphore */ - set_errno(ENOMEM); - return -1; - } -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - /* Protect the select_cb_list */ - SYS_ARCH_PROTECT(lev); - - /* Put this select_cb on top of list */ - select_cb.next = select_cb_list; - if (select_cb_list != NULL) { - select_cb_list->prev = &select_cb; - } - select_cb_list = &select_cb; - /* Increasing this counter tells event_callback that the list has changed. */ - select_cb_ctr++; - - /* Now we can safely unprotect */ - SYS_ARCH_UNPROTECT(lev); - - /* Increase select_waiting for each socket we are interested in */ - maxfdp2 = maxfdp1; - for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { - if ((readset && FD_ISSET(i, readset)) || - (writeset && FD_ISSET(i, writeset)) || - (exceptset && FD_ISSET(i, exceptset))) { - struct lwip_sock *sock; - SYS_ARCH_PROTECT(lev); - sock = tryget_socket(i); - if (sock != NULL) { - sock->select_waiting++; - LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); - } else { - /* Not a valid socket */ - nready = -1; - maxfdp2 = i; - SYS_ARCH_UNPROTECT(lev); - break; - } - SYS_ARCH_UNPROTECT(lev); - } - } - - if (nready >= 0) { - /* Call lwip_selscan again: there could have been events between - the last scan (without us on the list) and putting us on the list! */ - nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); - if (!nready) { - /* Still none ready, just wait to be woken */ - if (timeout == 0) { - /* Wait forever */ - msectimeout = 0; - } else { - msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); - if (msectimeout == 0) { - /* Wait 1ms at least (0 means wait forever) */ - msectimeout = 1; - } - } - - waitres = sys_arch_sem_wait(SELECT_SEM_PTR(select_cb.sem), msectimeout); -#if LWIP_NETCONN_SEM_PER_THREAD - waited = 1; -#endif - } - } - - /* Decrease select_waiting for each socket we are interested in */ - for (i = LWIP_SOCKET_OFFSET; i < maxfdp2; i++) { - if ((readset && FD_ISSET(i, readset)) || - (writeset && FD_ISSET(i, writeset)) || - (exceptset && FD_ISSET(i, exceptset))) { - struct lwip_sock *sock; - SYS_ARCH_PROTECT(lev); - sock = tryget_socket(i); - if (sock != NULL) { - /* for now, handle select_waiting==0... */ - LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); - if (sock->select_waiting > 0) { - sock->select_waiting--; - } - } else { - /* Not a valid socket */ - nready = -1; - } - SYS_ARCH_UNPROTECT(lev); - } - } - /* Take us off the list */ - SYS_ARCH_PROTECT(lev); - if (select_cb.next != NULL) { - select_cb.next->prev = select_cb.prev; - } - if (select_cb_list == &select_cb) { - LWIP_ASSERT("select_cb.prev == NULL", select_cb.prev == NULL); - select_cb_list = select_cb.next; - } else { - LWIP_ASSERT("select_cb.prev != NULL", select_cb.prev != NULL); - select_cb.prev->next = select_cb.next; - } - /* Increasing this counter tells event_callback that the list has changed. */ - select_cb_ctr++; - SYS_ARCH_UNPROTECT(lev); - -#if LWIP_NETCONN_SEM_PER_THREAD - if (select_cb.sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) { - /* don't leave the thread-local semaphore signalled */ - sys_arch_sem_wait(select_cb.sem, 1); - } -#else /* LWIP_NETCONN_SEM_PER_THREAD */ - sys_sem_free(&select_cb.sem); -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - if (nready < 0) { - /* This happens when a socket got closed while waiting */ - set_errno(EBADF); - return -1; - } - - if (waitres == SYS_ARCH_TIMEOUT) { - /* Timeout */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); - /* This is OK as the local fdsets are empty and nready is zero, - or we would have returned earlier. */ - goto return_copy_fdsets; - } - - /* See what's set */ - nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); -return_copy_fdsets: - set_errno(0); - if (readset) { - *readset = lreadset; - } - if (writeset) { - *writeset = lwriteset; - } - if (exceptset) { - *exceptset = lexceptset; - } - return nready; -} - -/** - * Callback registered in the netconn layer for each socket-netconn. - * Processes recvevent (data available) and wakes up tasks waiting for select. - */ -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) -{ - int s; - struct lwip_sock *sock; - struct lwip_select_cb *scb; - int last_select_cb_ctr; - SYS_ARCH_DECL_PROTECT(lev); - - LWIP_UNUSED_ARG(len); - - /* Get socket */ - if (conn) { - s = conn->socket; - if (s < 0) { - /* Data comes in right away after an accept, even though - * the server task might not have created a new socket yet. - * Just count down (or up) if that's the case and we - * will use the data later. Note that only receive events - * can happen before the new socket is set up. */ - SYS_ARCH_PROTECT(lev); - if (conn->socket < 0) { - if (evt == NETCONN_EVT_RCVPLUS) { - conn->socket--; - } - SYS_ARCH_UNPROTECT(lev); - return; - } - s = conn->socket; - SYS_ARCH_UNPROTECT(lev); - } - - sock = get_socket(s); - if (!sock) { - return; - } - } else { - return; - } - - SYS_ARCH_PROTECT(lev); - /* Set event as required */ - switch (evt) { - case NETCONN_EVT_RCVPLUS: - sock->rcvevent++; - break; - case NETCONN_EVT_RCVMINUS: - sock->rcvevent--; - break; - case NETCONN_EVT_SENDPLUS: - sock->sendevent = 1; - break; - case NETCONN_EVT_SENDMINUS: - sock->sendevent = 0; - break; - case NETCONN_EVT_ERROR: - sock->errevent = 1; - break; - default: - LWIP_ASSERT("unknown event", 0); - break; - } - - if (sock->select_waiting == 0) { - /* noone is waiting for this socket, no need to check select_cb_list */ - SYS_ARCH_UNPROTECT(lev); - return; - } - - /* Now decide if anyone is waiting for this socket */ - /* NOTE: This code goes through the select_cb_list list multiple times - ONLY IF a select was actually waiting. We go through the list the number - of waiting select calls + 1. This list is expected to be small. */ - - /* At this point, SYS_ARCH is still protected! */ -again: - for (scb = select_cb_list; scb != NULL; scb = scb->next) { - /* remember the state of select_cb_list to detect changes */ - last_select_cb_ctr = select_cb_ctr; - if (scb->sem_signalled == 0) { - /* semaphore not signalled yet */ - int do_signal = 0; - /* Test this select call for our socket */ - if (sock->rcvevent > 0) { - if (scb->readset && FD_ISSET(s, scb->readset)) { - do_signal = 1; - } - } - if (sock->sendevent != 0) { - if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) { - do_signal = 1; - } - } - if (sock->errevent != 0) { - if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) { - do_signal = 1; - } - } - if (do_signal) { - scb->sem_signalled = 1; - /* Don't call SYS_ARCH_UNPROTECT() before signaling the semaphore, as this might - lead to the select thread taking itself off the list, invalidating the semaphore. */ - sys_sem_signal(SELECT_SEM_PTR(scb->sem)); - } - } - /* unlock interrupts with each step */ - SYS_ARCH_UNPROTECT(lev); - /* this makes sure interrupt protection time is short */ - SYS_ARCH_PROTECT(lev); - if (last_select_cb_ctr != select_cb_ctr) { - /* someone has changed select_cb_list, restart at the beginning */ - goto again; - } - } - SYS_ARCH_UNPROTECT(lev); -} - -/** - * Close one end of a full-duplex connection. - */ -int -lwip_shutdown(int s, int how) -{ - struct lwip_sock *sock; - err_t err; - u8_t shut_rx = 0, shut_tx = 0; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); - - sock = get_socket(s); - if (!sock) { - return -1; - } - SOCK_DEINIT_SYNC(sock); - - if (sock->conn != NULL) { - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { - sock_set_errno(sock, EOPNOTSUPP); - return -1; - } - } else { - sock_set_errno(sock, ENOTCONN); - return -1; - } - - if (how == SHUT_RD) { - shut_rx = 1; - } else if (how == SHUT_WR) { - shut_tx = 1; - } else if (how == SHUT_RDWR) { - shut_rx = 1; - shut_tx = 1; - } else { - sock_set_errno(sock, EINVAL); - return -1; - } - err = netconn_shutdown(sock->conn, shut_rx, shut_tx); - - sock_set_errno(sock, err_to_errno(err)); - return (err == ERR_OK ? 0 : -1); -} - -static int -lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) -{ - struct lwip_sock *sock; - union sockaddr_aligned saddr; - ip_addr_t naddr; - u16_t port; - err_t err; - - sock = get_socket(s); - if (!sock) { - return -1; - } - - /* get the IP address and port */ - err = netconn_getaddr(sock->conn, &naddr, &port, local); - if (err != ERR_OK) { - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ - if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && - IP_IS_V4_VAL(naddr)) { - ip4_2_ipv4_mapped_ipv6(ip_2_ip6(&naddr), ip_2_ip4(&naddr)); - IP_SET_TYPE_VAL(naddr, IPADDR_TYPE_V6); - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - IPADDR_PORT_TO_SOCKADDR(&saddr, &naddr, port); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); - ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", port)); - - if (*namelen > saddr.sa.sa_len) { - *namelen = saddr.sa.sa_len; - } - MEMCPY(name, &saddr, *namelen); - - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) -{ - return lwip_getaddrname(s, name, namelen, 0); -} - -int -lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) -{ - return lwip_getaddrname(s, name, namelen, 1); -} - -int -lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) -{ - u8_t err; - struct lwip_sock *sock = get_socket(s); -#if !LWIP_TCPIP_CORE_LOCKING - LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); -#endif /* !LWIP_TCPIP_CORE_LOCKING */ - - if (!sock) { - return -1; - } - - if ((NULL == optval) || (NULL == optlen)) { - sock_set_errno(sock, EFAULT); - return -1; - } - -#if LWIP_TCPIP_CORE_LOCKING - /* core-locking can just call the -impl function */ - LOCK_TCPIP_CORE(); - err = lwip_getsockopt_impl(s, level, optname, optval, optlen); - UNLOCK_TCPIP_CORE(); - -#else /* LWIP_TCPIP_CORE_LOCKING */ - -#if LWIP_MPU_COMPATIBLE - /* MPU_COMPATIBLE copies the optval data, so check for max size here */ - if (*optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { - sock_set_errno(sock, ENOBUFS); - return -1; - } -#endif /* LWIP_MPU_COMPATIBLE */ - - LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = *optlen; -#if !LWIP_MPU_COMPATIBLE - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.p = optval; -#endif /* !LWIP_MPU_COMPATIBLE */ - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; -#if LWIP_NETCONN_SEM_PER_THREAD - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); -#else - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; -#endif - err = tcpip_callback(lwip_getsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); - if (err != ERR_OK) { - LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); - - /* write back optlen and optval */ - *optlen = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen; -#if LWIP_MPU_COMPATIBLE - MEMCPY(optval, LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen); -#endif /* LWIP_MPU_COMPATIBLE */ - - /* maybe lwip_getsockopt_internal has changed err */ - err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; - LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -#if !LWIP_TCPIP_CORE_LOCKING -/** lwip_getsockopt_callback: only used without CORE_LOCKING - * to get into the tcpip_thread - */ -static void -lwip_getsockopt_callback(void *arg) -{ - struct lwip_setgetsockopt_data *data; - LWIP_ASSERT("arg != NULL", arg != NULL); - data = (struct lwip_setgetsockopt_data*)arg; - - data->err = lwip_getsockopt_impl(data->s, data->level, data->optname, -#if LWIP_MPU_COMPATIBLE - data->optval, -#else /* LWIP_MPU_COMPATIBLE */ - data->optval.p, -#endif /* LWIP_MPU_COMPATIBLE */ - &data->optlen); - - sys_sem_signal((sys_sem_t*)(data->completed_sem)); -} -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -/** lwip_getsockopt_impl: the actual implementation of getsockopt: - * same argument as lwip_getsockopt, either called directly or through callback - */ -static u8_t -lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen) -{ - u8_t err = 0; - struct lwip_sock *sock = tryget_socket(s); - if (!sock) { - return EBADF; - } - - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - -#if LWIP_TCP - case SO_ACCEPTCONN: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); - if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_TCP) { - return ENOPROTOOPT; - } - if ((sock->conn->pcb.tcp != NULL) && (sock->conn->pcb.tcp->state == LISTEN)) { - *(int*)optval = 1; - } else { - *(int*)optval = 0; - } - break; -#endif /* LWIP_TCP */ - - /* The option flags */ - case SO_BROADCAST: - case SO_KEEPALIVE: -#if SO_REUSE - case SO_REUSEADDR: -#endif /* SO_REUSE */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); - *(int*)optval = ip_get_option(sock->conn->pcb.ip, optname); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", - s, optname, (*(int*)optval?"on":"off"))); - break; - - case SO_TYPE: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); - switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) { - case NETCONN_RAW: - *(int*)optval = SOCK_RAW; - break; - case NETCONN_TCP: - *(int*)optval = SOCK_STREAM; - break; - case NETCONN_UDP: - *(int*)optval = SOCK_DGRAM; - break; - default: /* unrecognized socket type */ - *(int*)optval = netconn_type(sock->conn); - LWIP_DEBUGF(SOCKETS_DEBUG, - ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", - s, *(int *)optval)); - } /* switch (netconn_type(sock->conn)) */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", - s, *(int *)optval)); - break; - - case SO_ERROR: - LWIP_SOCKOPT_CHECK_OPTLEN(*optlen, int); - /* only overwrite ERR_OK or temporary errors */ - if (((sock->err == 0) || (sock->err == EINPROGRESS)) && (sock->conn != NULL)) { - sock_set_errno(sock, err_to_errno(sock->conn->last_err)); - } - *(int *)optval = (sock->err == 0xFF ? (int)-1 : (int)sock->err); - sock->err = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", - s, *(int *)optval)); - break; - -#if LWIP_SO_SNDTIMEO - case SO_SNDTIMEO: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); - LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_sendtimeout(sock->conn)); - break; -#endif /* LWIP_SO_SNDTIMEO */ -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); - LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_recvtimeout(sock->conn)); - break; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); - *(int *)optval = netconn_get_recvbufsize(sock->conn); - break; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_SO_LINGER - case SO_LINGER: - { - s16_t conn_linger; - struct linger* linger = (struct linger*)optval; - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, struct linger); - conn_linger = sock->conn->linger; - if (conn_linger >= 0) { - linger->l_onoff = 1; - linger->l_linger = (int)conn_linger; - } else { - linger->l_onoff = 0; - linger->l_linger = 0; - } - } - break; -#endif /* LWIP_SO_LINGER */ -#if LWIP_UDP - case SO_NO_CHECK: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_UDP); -#if LWIP_UDPLITE - if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { - /* this flag is only available for UDP, not for UDP lite */ - return EAFNOSUPPORT; - } -#endif /* LWIP_UDPLITE */ - *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0; - break; -#endif /* LWIP_UDP*/ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - case IP_TTL: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); - *(int*)optval = sock->conn->pcb.ip->ttl; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", - s, *(int *)optval)); - break; - case IP_TOS: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); - *(int*)optval = sock->conn->pcb.ip->tos; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", - s, *(int *)optval)); - break; -#if LWIP_MULTICAST_TX_OPTIONS - case IP_MULTICAST_TTL: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { - return ENOPROTOOPT; - } - *(u8_t*)optval = udp_get_multicast_ttl(sock->conn->pcb.udp); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", - s, *(int *)optval)); - break; - case IP_MULTICAST_IF: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in_addr); - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { - return ENOPROTOOPT; - } - inet_addr_from_ip4addr((struct in_addr*)optval, udp_get_multicast_netif_addr(sock->conn->pcb.udp)); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", - s, *(u32_t *)optval)); - break; - case IP_MULTICAST_LOOP: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); - if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { - *(u8_t*)optval = 1; - } else { - *(u8_t*)optval = 0; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n", - s, *(int *)optval)); - break; -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - /* Special case: all IPPROTO_TCP option take an int */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_TCP); - if (sock->conn->pcb.tcp->state == LISTEN) { - return EINVAL; - } - switch (optname) { - case TCP_NODELAY: - *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", - s, (*(int*)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) = %d\n", - s, *(int *)optval)); - break; - -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) = %d\n", - s, *(int *)optval)); - break; - case TCP_KEEPINTVL: - *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) = %d\n", - s, *(int *)optval)); - break; - case TCP_KEEPCNT: - *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) = %d\n", - s, *(int *)optval)); - break; -#endif /* LWIP_TCP_KEEPALIVE */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_TCP */ - -#if LWIP_IPV6 -/* Level: IPPROTO_IPV6 */ - case IPPROTO_IPV6: - switch (optname) { - case IPV6_V6ONLY: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); - *(int*)optval = (netconn_get_ipv6only(sock->conn) ? 1 : 0); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY) = %d\n", - s, *(int *)optval)); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_IPV6 */ - -#if LWIP_UDP && LWIP_UDPLITE - /* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - /* Special case: all IPPROTO_UDPLITE option take an int */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); - /* If this is no UDP lite socket, ignore any options. */ - if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { - return ENOPROTOOPT; - } - switch (optname) { - case UDPLITE_SEND_CSCOV: - *(int*)optval = sock->conn->pcb.udp->chksum_len_tx; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", - s, (*(int*)optval)) ); - break; - case UDPLITE_RECV_CSCOV: - *(int*)optval = sock->conn->pcb.udp->chksum_len_rx; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", - s, (*(int*)optval)) ); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP */ - /* Level: IPPROTO_RAW */ - case IPPROTO_RAW: - switch (optname) { -#if LWIP_IPV6 && LWIP_RAW - case IPV6_CHECKSUM: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_RAW); - if (sock->conn->pcb.raw->chksum_reqd == 0) { - *(int *)optval = -1; - } else { - *(int *)optval = sock->conn->pcb.raw->chksum_offset; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM) = %d\n", - s, (*(int*)optval)) ); - break; -#endif /* LWIP_IPV6 && LWIP_RAW */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", - s, level, optname)); - err = ENOPROTOOPT; - break; - } /* switch (level) */ - - return err; -} - -int -lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) -{ - u8_t err = 0; - struct lwip_sock *sock = get_socket(s); -#if !LWIP_TCPIP_CORE_LOCKING - LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); -#endif /* !LWIP_TCPIP_CORE_LOCKING */ - - if (!sock) { - return -1; - } - - if (NULL == optval) { - sock_set_errno(sock, EFAULT); - return -1; - } - -#if LWIP_TCPIP_CORE_LOCKING - /* core-locking can just call the -impl function */ - LOCK_TCPIP_CORE(); - err = lwip_setsockopt_impl(s, level, optname, optval, optlen); - UNLOCK_TCPIP_CORE(); - -#else /* LWIP_TCPIP_CORE_LOCKING */ - -#if LWIP_MPU_COMPATIBLE - /* MPU_COMPATIBLE copies the optval data, so check for max size here */ - if (optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { - sock_set_errno(sock, ENOBUFS); - return -1; - } -#endif /* LWIP_MPU_COMPATIBLE */ - - LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = optlen; -#if LWIP_MPU_COMPATIBLE - MEMCPY(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, optval, optlen); -#else /* LWIP_MPU_COMPATIBLE */ - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.pc = (const void*)optval; -#endif /* LWIP_MPU_COMPATIBLE */ - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; -#if LWIP_NETCONN_SEM_PER_THREAD - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); -#else - LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; -#endif - err = tcpip_callback(lwip_setsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); - if (err != ERR_OK) { - LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); - - /* maybe lwip_getsockopt_internal has changed err */ - err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; - LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -#if !LWIP_TCPIP_CORE_LOCKING -/** lwip_setsockopt_callback: only used without CORE_LOCKING - * to get into the tcpip_thread - */ -static void -lwip_setsockopt_callback(void *arg) -{ - struct lwip_setgetsockopt_data *data; - LWIP_ASSERT("arg != NULL", arg != NULL); - data = (struct lwip_setgetsockopt_data*)arg; - - data->err = lwip_setsockopt_impl(data->s, data->level, data->optname, -#if LWIP_MPU_COMPATIBLE - data->optval, -#else /* LWIP_MPU_COMPATIBLE */ - data->optval.pc, -#endif /* LWIP_MPU_COMPATIBLE */ - data->optlen); - - sys_sem_signal((sys_sem_t*)(data->completed_sem)); -} -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -/** lwip_setsockopt_impl: the actual implementation of setsockopt: - * same argument as lwip_setsockopt, either called directly or through callback - */ -static u8_t -lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen) -{ - u8_t err = 0; - struct lwip_sock *sock = tryget_socket(s); - if (!sock) { - return EBADF; - } - - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - - /* SO_ACCEPTCONN is get-only */ - - /* The option flags */ - case SO_BROADCAST: - case SO_KEEPALIVE: -#if SO_REUSE - case SO_REUSEADDR: -#endif /* SO_REUSE */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); - if (*(const int*)optval) { - ip_set_option(sock->conn->pcb.ip, optname); - } else { - ip_reset_option(sock->conn->pcb.ip, optname); - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", - s, optname, (*(const int*)optval?"on":"off"))); - break; - - /* SO_TYPE is get-only */ - /* SO_ERROR is get-only */ - -#if LWIP_SO_SNDTIMEO - case SO_SNDTIMEO: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); - netconn_set_sendtimeout(sock->conn, LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); - break; -#endif /* LWIP_SO_SNDTIMEO */ -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); - netconn_set_recvtimeout(sock->conn, (int)LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); - break; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int); - netconn_set_recvbufsize(sock->conn, *(const int*)optval); - break; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_SO_LINGER - case SO_LINGER: - { - const struct linger* linger = (const struct linger*)optval; - LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct linger); - if (linger->l_onoff) { - int lingersec = linger->l_linger; - if (lingersec < 0) { - return EINVAL; - } - if (lingersec > 0xFFFF) { - lingersec = 0xFFFF; - } - sock->conn->linger = (s16_t)lingersec; - } else { - sock->conn->linger = -1; - } - } - break; -#endif /* LWIP_SO_LINGER */ -#if LWIP_UDP - case SO_NO_CHECK: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP); -#if LWIP_UDPLITE - if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { - /* this flag is only available for UDP, not for UDP lite */ - return EAFNOSUPPORT; - } -#endif /* LWIP_UDPLITE */ - if (*(const int*)optval) { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM); - } else { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM); - } - break; -#endif /* LWIP_UDP */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - case IP_TTL: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); - sock->conn->pcb.ip->ttl = (u8_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", - s, sock->conn->pcb.ip->ttl)); - break; - case IP_TOS: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); - sock->conn->pcb.ip->tos = (u8_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", - s, sock->conn->pcb.ip->tos)); - break; -#if LWIP_MULTICAST_TX_OPTIONS - case IP_MULTICAST_TTL: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); - udp_set_multicast_ttl(sock->conn->pcb.udp, (u8_t)(*(const u8_t*)optval)); - break; - case IP_MULTICAST_IF: - { - ip4_addr_t if_addr; - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in_addr, NETCONN_UDP); - inet_addr_to_ip4addr(&if_addr, (const struct in_addr*)optval); - udp_set_multicast_netif_addr(sock->conn->pcb.udp, &if_addr); - } - break; - case IP_MULTICAST_LOOP: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); - if (*(const u8_t*)optval) { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP); - } else { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP); - } - break; -#endif /* LWIP_MULTICAST_TX_OPTIONS */ -#if LWIP_IGMP - case IP_ADD_MEMBERSHIP: - case IP_DROP_MEMBERSHIP: - { - /* If this is a TCP or a RAW socket, ignore these options. */ - /* @todo: assign membership to this socket so that it is dropped when closing the socket */ - err_t igmp_err; - const struct ip_mreq *imr = (const struct ip_mreq *)optval; - ip4_addr_t if_addr; - ip4_addr_t multi_addr; - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip_mreq, NETCONN_UDP); - inet_addr_to_ip4addr(&if_addr, &imr->imr_interface); - inet_addr_to_ip4addr(&multi_addr, &imr->imr_multiaddr); - if (optname == IP_ADD_MEMBERSHIP) { - if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) { - /* cannot track membership (out of memory) */ - err = ENOMEM; - igmp_err = ERR_OK; - } else { - igmp_err = igmp_joingroup(&if_addr, &multi_addr); - } - } else { - igmp_err = igmp_leavegroup(&if_addr, &multi_addr); - lwip_socket_unregister_membership(s, &if_addr, &multi_addr); - } - if (igmp_err != ERR_OK) { - err = EADDRNOTAVAIL; - } - } - break; -#endif /* LWIP_IGMP */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - /* Special case: all IPPROTO_TCP option take an int */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); - if (sock->conn->pcb.tcp->state == LISTEN) { - return EINVAL; - } - switch (optname) { - case TCP_NODELAY: - if (*(const int*)optval) { - tcp_nagle_disable(sock->conn->pcb.tcp); - } else { - tcp_nagle_enable(sock->conn->pcb.tcp); - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", - s, (*(const int *)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - sock->conn->pcb.tcp->keep_idle = (u32_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_idle)); - break; - -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_idle)); - break; - case TCP_KEEPINTVL: - sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_intvl)); - break; - case TCP_KEEPCNT: - sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(const int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_cnt)); - break; -#endif /* LWIP_TCP_KEEPALIVE */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_TCP*/ - -#if LWIP_IPV6 -/* Level: IPPROTO_IPV6 */ - case IPPROTO_IPV6: - switch (optname) { - case IPV6_V6ONLY: - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); - if (*(const int*)optval) { - netconn_set_ipv6only(sock->conn, 1); - } else { - netconn_set_ipv6only(sock->conn, 0); - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY, ..) -> %d\n", - s, (netconn_get_ipv6only(sock->conn) ? 1 : 0))); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_IPV6 */ - -#if LWIP_UDP && LWIP_UDPLITE - /* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - /* Special case: all IPPROTO_UDPLITE option take an int */ - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); - /* If this is no UDP lite socket, ignore any options. */ - if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { - return ENOPROTOOPT; - } - switch (optname) { - case UDPLITE_SEND_CSCOV: - if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { - /* don't allow illegal values! */ - sock->conn->pcb.udp->chksum_len_tx = 8; - } else { - sock->conn->pcb.udp->chksum_len_tx = (u16_t)*(const int*)optval; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", - s, (*(const int*)optval)) ); - break; - case UDPLITE_RECV_CSCOV: - if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { - /* don't allow illegal values! */ - sock->conn->pcb.udp->chksum_len_rx = 8; - } else { - sock->conn->pcb.udp->chksum_len_rx = (u16_t)*(const int*)optval; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", - s, (*(const int*)optval)) ); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP */ - /* Level: IPPROTO_RAW */ - case IPPROTO_RAW: - switch (optname) { -#if LWIP_IPV6 && LWIP_RAW - case IPV6_CHECKSUM: - /* It should not be possible to disable the checksum generation with ICMPv6 - * as per RFC 3542 chapter 3.1 */ - if(sock->conn->pcb.raw->protocol == IPPROTO_ICMPV6) { - return EINVAL; - } - - LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_RAW); - if (*(const int *)optval < 0) { - sock->conn->pcb.raw->chksum_reqd = 0; - } else if (*(const int *)optval & 1) { - /* Per RFC3542, odd offsets are not allowed */ - return EINVAL; - } else { - sock->conn->pcb.raw->chksum_reqd = 1; - sock->conn->pcb.raw->chksum_offset = (u16_t)*(const int *)optval; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM, ..) -> %d\n", - s, sock->conn->pcb.raw->chksum_reqd)); - break; -#endif /* LWIP_IPV6 && LWIP_RAW */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - break; - } /* switch (optname) */ - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", - s, level, optname)); - err = ENOPROTOOPT; - break; - } /* switch (level) */ - - return err; -} - -int -lwip_ioctl(int s, long cmd, void *argp) -{ - struct lwip_sock *sock = get_socket(s); - u8_t val; -#if LWIP_SO_RCVBUF - u16_t buflen = 0; - int recv_avail; -#endif /* LWIP_SO_RCVBUF */ - - if (!sock) { - return -1; - } - - switch (cmd) { -#if LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE - case FIONREAD: - if (!argp) { - sock_set_errno(sock, EINVAL); - return -1; - } -#if LWIP_FIONREAD_LINUXMODE - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { - struct pbuf *p; - if (sock->lastdata) { - p = ((struct netbuf *)sock->lastdata)->p; - *((int*)argp) = p->tot_len - sock->lastoffset; - } else { - struct netbuf *rxbuf; - err_t err; - if (sock->rcvevent <= 0) { - *((int*)argp) = 0; - } else { - err = netconn_recv(sock->conn, &rxbuf); - if (err != ERR_OK) { - *((int*)argp) = 0; - } else { - sock->lastdata = rxbuf; - sock->lastoffset = 0; - *((int*)argp) = rxbuf->p->tot_len; - } - } - } - return 0; - } -#endif /* LWIP_FIONREAD_LINUXMODE */ - -#if LWIP_SO_RCVBUF - /* we come here if either LWIP_FIONREAD_LINUXMODE==0 or this is a TCP socket */ - SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); - if (recv_avail < 0) { - recv_avail = 0; - } - *((int*)argp) = recv_avail; - - /* Check if there is data left from the last recv operation. /maq 041215 */ - if (sock->lastdata) { - struct pbuf *p = (struct pbuf *)sock->lastdata; - if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { - p = ((struct netbuf *)p)->p; - } - buflen = p->tot_len; - buflen -= sock->lastoffset; - - *((int*)argp) += buflen; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp))); - sock_set_errno(sock, 0); - return 0; -#else /* LWIP_SO_RCVBUF */ - break; -#endif /* LWIP_SO_RCVBUF */ -#endif /* LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE */ - - case (long)FIONBIO: - val = 0; - if (argp && *(u32_t*)argp) { - val = 1; - } - netconn_set_nonblocking(sock->conn, val); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val)); - sock_set_errno(sock, 0); - return 0; - - default: - break; - } /* switch (cmd) */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - return -1; -} - -/** A minimal implementation of fcntl. - * Currently only the commands F_GETFL and F_SETFL are implemented. - * Only the flag O_NONBLOCK is implemented. - */ -int -lwip_fcntl(int s, int cmd, int val) -{ - struct lwip_sock *sock = get_socket(s); - int ret = -1; - - if (!sock) { - return -1; - } - - switch (cmd) { - case F_GETFL: - ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0; - sock_set_errno(sock, 0); - break; - case F_SETFL: - if ((val & ~O_NONBLOCK) == 0) { - /* only O_NONBLOCK, all other bits are zero */ - netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); - ret = 0; - sock_set_errno(sock, 0); - } else { - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - } - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val)); - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - break; - } - return ret; -} - -#if LWIP_IGMP -/** Register a new IGMP membership. On socket close, the membership is dropped automatically. - * - * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). - * - * @return 1 on success, 0 on failure - */ -static int -lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) -{ - struct lwip_sock *sock = get_socket(s); - int i; - - if (!sock) { - return 0; - } - - for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { - if (socket_ipv4_multicast_memberships[i].sock == NULL) { - socket_ipv4_multicast_memberships[i].sock = sock; - ip4_addr_copy(socket_ipv4_multicast_memberships[i].if_addr, *if_addr); - ip4_addr_copy(socket_ipv4_multicast_memberships[i].multi_addr, *multi_addr); - return 1; - } - } - return 0; -} - -/** Unregister a previously registered membership. This prevents dropping the membership - * on socket close. - * - * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). - */ -static void -lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) -{ - struct lwip_sock *sock = get_socket(s); - int i; - - if (!sock) { - return; - } - - for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { - if ((socket_ipv4_multicast_memberships[i].sock == sock) && - ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].if_addr, if_addr) && - ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].multi_addr, multi_addr)) { - socket_ipv4_multicast_memberships[i].sock = NULL; - ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); - ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); - return; - } - } -} - -/** Drop all memberships of a socket that were not dropped explicitly via setsockopt. - * - * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). - */ -static void -lwip_socket_drop_registered_memberships(int s) -{ - struct lwip_sock *sock = get_socket(s); - int i; - - if (!sock) { - return; - } - - for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { - if (socket_ipv4_multicast_memberships[i].sock == sock) { - ip_addr_t multi_addr, if_addr; - ip_addr_copy_from_ip4(multi_addr, socket_ipv4_multicast_memberships[i].multi_addr); - ip_addr_copy_from_ip4(if_addr, socket_ipv4_multicast_memberships[i].if_addr); - socket_ipv4_multicast_memberships[i].sock = NULL; - ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); - ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); - - netconn_join_leave_group(sock->conn, &multi_addr, &if_addr, NETCONN_LEAVE); - } - } -} -#endif /* LWIP_IGMP */ -#endif /* LWIP_SOCKET */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/tcpip.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/tcpip.c deleted file mode 100644 index bdc04ba7f4e1a22621022a52815f8ee500cea688..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/api/tcpip.c +++ /dev/null @@ -1,523 +0,0 @@ -/** - * @file - * Sequential API Main thread module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/priv/tcpip_priv.h" -#include "lwip/sys.h" -#include "lwip/memp.h" -#include "lwip/mem.h" -#include "lwip/init.h" -#include "lwip/ip.h" -#include "lwip/pbuf.h" -#include "lwip/etharp.h" -#include "netif/ethernet.h" -#include "lwip/debug.h" - -#define TCPIP_MSG_VAR_REF(name) API_VAR_REF(name) -#define TCPIP_MSG_VAR_DECLARE(name) API_VAR_DECLARE(struct tcpip_msg, name) -#define TCPIP_MSG_VAR_ALLOC(name) API_VAR_ALLOC(struct tcpip_msg, MEMP_TCPIP_MSG_API, name, ERR_MEM) -#define TCPIP_MSG_VAR_FREE(name) API_VAR_FREE(MEMP_TCPIP_MSG_API, name) - -/* global variables */ -static tcpip_init_done_fn tcpip_init_done; -static void *tcpip_init_done_arg; -static sys_mbox_t mbox; - -#if LWIP_TCPIP_CORE_LOCKING -/** The global semaphore to lock the stack. */ -sys_mutex_t lock_tcpip_core; -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -#if LWIP_TIMERS -/* wait for a message, timeouts are processed while waiting */ -#define TCPIP_MBOX_FETCH(mbox, msg) sys_timeouts_mbox_fetch(mbox, msg) -#else /* LWIP_TIMERS */ -/* wait for a message with timers disabled (e.g. pass a timer-check trigger into tcpip_thread) */ -#define TCPIP_MBOX_FETCH(mbox, msg) sys_mbox_fetch(mbox, msg) -#endif /* LWIP_TIMERS */ - -/** - * The main lwIP thread. This thread has exclusive access to lwIP core functions - * (unless access to them is not locked). Other threads communicate with this - * thread using message boxes. - * - * It also starts all the timers to make sure they are running in the right - * thread context. - * - * @param arg unused argument - */ -static void -tcpip_thread(void *arg) -{ - struct tcpip_msg *msg; - LWIP_UNUSED_ARG(arg); - - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread start\n")); - if (tcpip_init_done != NULL) { - tcpip_init_done(tcpip_init_done_arg); - } - - LOCK_TCPIP_CORE(); - while (1) { /* MAIN Loop */ - UNLOCK_TCPIP_CORE(); - LWIP_TCPIP_THREAD_ALIVE(); - /* wait for a message, timeouts are processed while waiting */ - TCPIP_MBOX_FETCH(&mbox, (void **)&msg); - LOCK_TCPIP_CORE(); - if (msg == NULL) { - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n")); - LWIP_ASSERT("tcpip_thread: invalid message", 0); - continue; - } - switch (msg->type) { -#if !LWIP_TCPIP_CORE_LOCKING - case TCPIP_MSG_API: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); - msg->msg.api_msg.function(msg->msg.api_msg.msg); - break; - case TCPIP_MSG_API_CALL: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API CALL message %p\n", (void *)msg)); - msg->msg.api_call.arg->err = msg->msg.api_call.function(msg->msg.api_call.arg); - sys_sem_signal(msg->msg.api_call.sem); - break; -#endif /* !LWIP_TCPIP_CORE_LOCKING */ - -#if !LWIP_TCPIP_CORE_LOCKING_INPUT - case TCPIP_MSG_INPKT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); - msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif); - memp_free(MEMP_TCPIP_MSG_INPKT, msg); - break; -#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ - -#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS - case TCPIP_MSG_TIMEOUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg)); - sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; - case TCPIP_MSG_UNTIMEOUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg)); - sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; -#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ - - case TCPIP_MSG_CALLBACK: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); - msg->msg.cb.function(msg->msg.cb.ctx); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; - - case TCPIP_MSG_CALLBACK_STATIC: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg)); - msg->msg.cb.function(msg->msg.cb.ctx); - break; - - default: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type)); - LWIP_ASSERT("tcpip_thread: invalid message", 0); - break; - } - } -} - -/** - * Pass a received packet to tcpip_thread for input processing - * - * @param p the received packet - * @param inp the network interface on which the packet was received - * @param input_fn input function to call - */ -err_t -tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn) -{ -#if LWIP_TCPIP_CORE_LOCKING_INPUT - err_t ret; - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_inpkt: PACKET %p/%p\n", (void *)p, (void *)inp)); - LOCK_TCPIP_CORE(); - ret = input_fn(p, inp); - UNLOCK_TCPIP_CORE(); - return ret; -#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */ - struct tcpip_msg *msg; - - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_inpkt: PACKET %p/%p\n", (void *)p, (void *)inp)); - msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT); - if (msg == NULL) { - LWIP_DEBUGF(TCPIP_DEBUG, ("memp malloc fail\n")); - return ERR_MEM; - } - - msg->type = TCPIP_MSG_INPKT; - msg->msg.inp.p = p; - msg->msg.inp.netif = inp; - msg->msg.inp.input_fn = input_fn; - if (sys_mbox_trypost(&mbox, msg) != ERR_OK) { - memp_free(MEMP_TCPIP_MSG_INPKT, msg); - LWIP_DEBUGF(TCPIP_DEBUG, ("mbox trypost fail\n")); - return ERR_MEM; - } - return ERR_OK; -#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ -} - -/** - * @ingroup lwip_os - * Pass a received packet to tcpip_thread for input processing with - * ethernet_input or ip_input. Don't call directly, pass to netif_add() - * and call netif->input(). - * - * @param p the received packet, p->payload pointing to the Ethernet header or - * to an IP header (if inp doesn't have NETIF_FLAG_ETHARP or - * NETIF_FLAG_ETHERNET flags) - * @param inp the network interface on which the packet was received - */ -err_t -tcpip_input(struct pbuf *p, struct netif *inp) -{ -#if LWIP_ETHERNET - if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { - return tcpip_inpkt(p, inp, ethernet_input); - } else -#endif /* LWIP_ETHERNET */ - return tcpip_inpkt(p, inp, ip_input); -} - -/** - * Call a specific function in the thread context of - * tcpip_thread for easy access synchronization. - * A function called in that way may access lwIP core code - * without fearing concurrent access. - * - * @param function the function to call - * @param ctx parameter passed to f - * @param block 1 to block until the request is posted, 0 to non-blocking mode - * @return ERR_OK if the function was called, another err_t if not - */ -err_t -tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block) -{ - struct tcpip_msg *msg; - - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - - msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_CALLBACK; - msg->msg.cb.function = function; - msg->msg.cb.ctx = ctx; - if (block) { - sys_mbox_post(&mbox, msg); - } else { - if (sys_mbox_trypost(&mbox, msg) != ERR_OK) { - memp_free(MEMP_TCPIP_MSG_API, msg); - return ERR_MEM; - } - } - return ERR_OK; -} - -#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS -/** - * call sys_timeout in tcpip_thread - * - * @param msecs time in milliseconds for timeout - * @param h function to be called on timeout - * @param arg argument to pass to timeout function h - * @return ERR_MEM on memory error, ERR_OK otherwise - */ -err_t -tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg) -{ - struct tcpip_msg *msg; - - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - - msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_TIMEOUT; - msg->msg.tmo.msecs = msecs; - msg->msg.tmo.h = h; - msg->msg.tmo.arg = arg; - sys_mbox_post(&mbox, msg); - return ERR_OK; -} - -/** - * call sys_untimeout in tcpip_thread - * - * @param h function to be called on timeout - * @param arg argument to pass to timeout function h - * @return ERR_MEM on memory error, ERR_OK otherwise - */ -err_t -tcpip_untimeout(sys_timeout_handler h, void *arg) -{ - struct tcpip_msg *msg; - - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - - msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_UNTIMEOUT; - msg->msg.tmo.h = h; - msg->msg.tmo.arg = arg; - sys_mbox_post(&mbox, msg); - return ERR_OK; -} -#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ - - -/** - * Sends a message to TCPIP thread to call a function. Caller thread blocks on - * on a provided semaphore, which ist NOT automatically signalled by TCPIP thread, - * this has to be done by the user. - * It is recommended to use LWIP_TCPIP_CORE_LOCKING since this is the way - * with least runtime overhead. - * - * @param fn function to be called from TCPIP thread - * @param apimsg argument to API function - * @param sem semaphore to wait on - * @return ERR_OK if the function was called, another err_t if not - */ -err_t -tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem) -{ -#if LWIP_TCPIP_CORE_LOCKING - LWIP_UNUSED_ARG(sem); - LOCK_TCPIP_CORE(); - fn(apimsg); - UNLOCK_TCPIP_CORE(); - return ERR_OK; -#else /* LWIP_TCPIP_CORE_LOCKING */ - TCPIP_MSG_VAR_DECLARE(msg); - - LWIP_ASSERT("semaphore not initialized", sys_sem_valid(sem)); - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - - TCPIP_MSG_VAR_ALLOC(msg); - TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API; - TCPIP_MSG_VAR_REF(msg).msg.api_msg.function = fn; - TCPIP_MSG_VAR_REF(msg).msg.api_msg.msg = apimsg; - sys_mbox_post(&mbox, &TCPIP_MSG_VAR_REF(msg)); - sys_arch_sem_wait(sem, 0); - TCPIP_MSG_VAR_FREE(msg); - return ERR_OK; -#endif /* LWIP_TCPIP_CORE_LOCKING */ -} - -/** - * Synchronously calls function in TCPIP thread and waits for its completion. - * It is recommended to use LWIP_TCPIP_CORE_LOCKING (preferred) or - * LWIP_NETCONN_SEM_PER_THREAD. - * If not, a semaphore is created and destroyed on every call which is usually - * an expensive/slow operation. - * @param fn Function to call - * @param call Call parameters - * @return Return value from tcpip_api_call_fn - */ -err_t -tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call) -{ -#if LWIP_TCPIP_CORE_LOCKING - err_t err; - LOCK_TCPIP_CORE(); - err = fn(call); - UNLOCK_TCPIP_CORE(); - return err; -#else /* LWIP_TCPIP_CORE_LOCKING */ - TCPIP_MSG_VAR_DECLARE(msg); - -#if !LWIP_NETCONN_SEM_PER_THREAD - err_t err = sys_sem_new(&call->sem, 0); - if (err != ERR_OK) { - return err; - } -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - - TCPIP_MSG_VAR_ALLOC(msg); - TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API_CALL; - TCPIP_MSG_VAR_REF(msg).msg.api_call.arg = call; - TCPIP_MSG_VAR_REF(msg).msg.api_call.function = fn; -#if LWIP_NETCONN_SEM_PER_THREAD - TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = LWIP_NETCONN_THREAD_SEM_GET(); -#else /* LWIP_NETCONN_SEM_PER_THREAD */ - TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = &call->sem; -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - sys_mbox_post(&mbox, &TCPIP_MSG_VAR_REF(msg)); - sys_arch_sem_wait(TCPIP_MSG_VAR_REF(msg).msg.api_call.sem, 0); - TCPIP_MSG_VAR_FREE(msg); - -#if !LWIP_NETCONN_SEM_PER_THREAD - sys_sem_free(&call->sem); -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - return call->err; -#endif /* LWIP_TCPIP_CORE_LOCKING */ -} - -/** - * Allocate a structure for a static callback message and initialize it. - * This is intended to be used to send "static" messages from interrupt context. - * - * @param function the function to call - * @param ctx parameter passed to function - * @return a struct pointer to pass to tcpip_trycallback(). - */ -struct tcpip_callback_msg* -tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx) -{ - struct tcpip_msg *msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return NULL; - } - msg->type = TCPIP_MSG_CALLBACK_STATIC; - msg->msg.cb.function = function; - msg->msg.cb.ctx = ctx; - return (struct tcpip_callback_msg*)msg; -} - -/** - * Free a callback message allocated by tcpip_callbackmsg_new(). - * - * @param msg the message to free - */ -void -tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg) -{ - memp_free(MEMP_TCPIP_MSG_API, msg); -} - -/** - * Try to post a callback-message to the tcpip_thread mbox - * This is intended to be used to send "static" messages from interrupt context. - * - * @param msg pointer to the message to post - * @return sys_mbox_trypost() return code - */ -err_t -tcpip_trycallback(struct tcpip_callback_msg* msg) -{ - LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(mbox)); - return sys_mbox_trypost(&mbox, msg); -} - -/** - * @ingroup lwip_os - * Initialize this module: - * - initialize all sub modules - * - start the tcpip_thread - * - * @param initfunc a function to call when tcpip_thread is running and finished initializing - * @param arg argument to pass to initfunc - */ -void -tcpip_init(tcpip_init_done_fn initfunc, void *arg) -{ - lwip_init(); - - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_init\n")); - tcpip_init_done = initfunc; - tcpip_init_done_arg = arg; - if (sys_mbox_new(&mbox, TCPIP_MBOX_SIZE) != ERR_OK) { - LWIP_ASSERT("failed to create tcpip_thread mbox", 0); - } -#if LWIP_TCPIP_CORE_LOCKING - if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) { - LWIP_ASSERT("failed to create lock_tcpip_core", 0); - } -#endif /* LWIP_TCPIP_CORE_LOCKING */ - - sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); -} - -/** - * Simple callback function used with tcpip_callback to free a pbuf - * (pbuf_free has a wrong signature for tcpip_callback) - * - * @param p The pbuf (chain) to be dereferenced. - */ -static void -pbuf_free_int(void *p) -{ - struct pbuf *q = (struct pbuf *)p; - pbuf_free(q); -} - -/** - * A simple wrapper function that allows you to free a pbuf from interrupt context. - * - * @param p The pbuf (chain) to be dereferenced. - * @return ERR_OK if callback could be enqueued, an err_t if not - */ -err_t -pbuf_free_callback(struct pbuf *p) -{ - return tcpip_callback_with_block(pbuf_free_int, p, 0); -} - -/** - * A simple wrapper function that allows you to free heap memory from - * interrupt context. - * - * @param m the heap memory to free - * @return ERR_OK if callback could be enqueued, an err_t if not - */ -err_t -mem_free_callback(void *m) -{ - return tcpip_callback_with_block(mem_free, m, 0); -} - -#endif /* !NO_SYS */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs.c deleted file mode 100644 index 35b5e3103812c8227687591bb1bcc9656e046470..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/apps/httpd_opts.h" -#include "lwip/def.h" -#include "lwip/apps/fs.h" -#include "fsdata.h" -#include - - -#if HTTPD_USE_CUSTOM_FSDATA -#include "fsdata_custom.c" -#else /* HTTPD_USE_CUSTOM_FSDATA */ -#include "fsdata.c" -#endif /* HTTPD_USE_CUSTOM_FSDATA */ - -/*-----------------------------------------------------------------------------------*/ - -#if LWIP_HTTPD_CUSTOM_FILES -int fs_open_custom(struct fs_file *file, const char *name); -void fs_close_custom(struct fs_file *file); -#if LWIP_HTTPD_FS_ASYNC_READ -u8_t fs_canread_custom(struct fs_file *file); -u8_t fs_wait_read_custom(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg); -int fs_read_async_custom(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg); -#else /* LWIP_HTTPD_FS_ASYNC_READ */ -int fs_read_custom(struct fs_file *file, char *buffer, int count); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -#endif /* LWIP_HTTPD_CUSTOM_FILES */ - -/*-----------------------------------------------------------------------------------*/ -err_t -fs_open(struct fs_file *file, const char *name) -{ - const struct fsdata_file *f; - - if ((file == NULL) || (name == NULL)) { - return ERR_ARG; - } - -#if LWIP_HTTPD_CUSTOM_FILES - if (fs_open_custom(file, name)) { - file->is_custom_file = 1; - return ERR_OK; - } - file->is_custom_file = 0; -#endif /* LWIP_HTTPD_CUSTOM_FILES */ - - for (f = FS_ROOT; f != NULL; f = f->next) { - if (!strcmp(name, (const char *)f->name)) { - file->data = (const char *)f->data; - file->len = f->len; - file->index = f->len; - file->pextension = NULL; - file->flags = f->flags; -#if HTTPD_PRECALCULATED_CHECKSUM - file->chksum_count = f->chksum_count; - file->chksum = f->chksum; -#endif /* HTTPD_PRECALCULATED_CHECKSUM */ -#if LWIP_HTTPD_FILE_STATE - file->state = fs_state_init(file, name); -#endif /* #if LWIP_HTTPD_FILE_STATE */ - return ERR_OK; - } - } - /* file not found */ - return ERR_VAL; -} - -/*-----------------------------------------------------------------------------------*/ -void -fs_close(struct fs_file *file) -{ -#if LWIP_HTTPD_CUSTOM_FILES - if (file->is_custom_file) { - fs_close_custom(file); - } -#endif /* LWIP_HTTPD_CUSTOM_FILES */ -#if LWIP_HTTPD_FILE_STATE - fs_state_free(file, file->state); -#endif /* #if LWIP_HTTPD_FILE_STATE */ - LWIP_UNUSED_ARG(file); -} -/*-----------------------------------------------------------------------------------*/ -#if LWIP_HTTPD_DYNAMIC_FILE_READ -#if LWIP_HTTPD_FS_ASYNC_READ -int -fs_read_async(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg) -#else /* LWIP_HTTPD_FS_ASYNC_READ */ -int -fs_read(struct fs_file *file, char *buffer, int count) -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -{ - int read; - if(file->index == file->len) { - return FS_READ_EOF; - } -#if LWIP_HTTPD_FS_ASYNC_READ - LWIP_UNUSED_ARG(callback_fn); - LWIP_UNUSED_ARG(callback_arg); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -#if LWIP_HTTPD_CUSTOM_FILES - if (file->is_custom_file) { -#if LWIP_HTTPD_FS_ASYNC_READ - return fs_read_async_custom(file, buffer, count, callback_fn, callback_arg); -#else /* LWIP_HTTPD_FS_ASYNC_READ */ - return fs_read_custom(file, buffer, count); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - } -#endif /* LWIP_HTTPD_CUSTOM_FILES */ - - read = file->len - file->index; - if(read > count) { - read = count; - } - - MEMCPY(buffer, (file->data + file->index), read); - file->index += read; - - return(read); -} -#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ -/*-----------------------------------------------------------------------------------*/ -#if LWIP_HTTPD_FS_ASYNC_READ -int -fs_is_file_ready(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg) -{ - if (file != NULL) { -#if LWIP_HTTPD_FS_ASYNC_READ -#if LWIP_HTTPD_CUSTOM_FILES - if (!fs_canread_custom(file)) { - if (fs_wait_read_custom(file, callback_fn, callback_arg)) { - return 0; - } - } -#else /* LWIP_HTTPD_CUSTOM_FILES */ - LWIP_UNUSED_ARG(callback_fn); - LWIP_UNUSED_ARG(callback_arg); -#endif /* LWIP_HTTPD_CUSTOM_FILES */ -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - } - return 1; -} -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -/*-----------------------------------------------------------------------------------*/ -int -fs_bytes_left(struct fs_file *file) -{ - return file->len - file->index; -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/404.html b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/404.html deleted file mode 100644 index 40b343a91e248db0a80862970921c616cb6f6af1..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/404.html +++ /dev/null @@ -1,21 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

404 - Page not found

-

- Sorry, the page you are requesting was not found on this - server. -

- 		-   -
- - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/img/sics.gif b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/img/sics.gif deleted file mode 100644 index 0a4fc7bb07050eec9226ca93bc9ad237f35502c8..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/img/sics.gif and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/index.html b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/index.html deleted file mode 100644 index ab575ef0891887afd23ca8adfaeee39704eeae66..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fs/index.html +++ /dev/null @@ -1,47 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

- The web page you are watching was served by a simple web - server running on top of the lightweight TCP/IP stack lwIP. -

-

- lwIP is an open source implementation of the TCP/IP - protocol suite that was originally written by Adam Dunkels - of the Swedish Institute of Computer Science but now is - being actively developed by a team of developers - distributed world-wide. Since it's release, lwIP has - spurred a lot of interest and has been ported to several - platforms and operating systems. lwIP can be used either - with or without an underlying OS. -

-

- The focus of the lwIP TCP/IP implementation is to reduce - the RAM usage while still having a full scale TCP. This - makes lwIP suitable for use in embedded systems with tens - of kilobytes of free RAM and room for around 40 kilobytes - of code ROM. -

-

- More information about lwIP can be found at the lwIP - homepage at http://savannah.nongnu.org/projects/lwip/ - or at the lwIP wiki at http://lwip.wikia.com/. -

- 		-   -
- - - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.c deleted file mode 100644 index 6170ce6326458384ca36d3ecfc918d6309050335..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.c +++ /dev/null @@ -1,298 +0,0 @@ -#include "lwip/apps/fs.h" -#include "lwip/def.h" -#include "fsdata.h" - - -#define file_NULL (struct fsdata_file *) NULL - - -static const unsigned int dummy_align__img_sics_gif = 0; -static const unsigned char data__img_sics_gif[] = { -/* /img/sics.gif (14 chars) */ -0x2f,0x69,0x6d,0x67,0x2f,0x73,0x69,0x63,0x73,0x2e,0x67,0x69,0x66,0x00,0x00,0x00, - -/* HTTP header */ -/* "HTTP/1.0 200 OK -" (17 bytes) */ -0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, -0x0a, -/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) -" (63 bytes) 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-data__index_html, -data__index_html + 12, -sizeof(data__index_html) - 12, -1, -}}; - -#define FS_ROOT file__index_html -#define FS_NUMFILES 3 - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.h deleted file mode 100644 index ac4548c7857d5acded512da1ace963303a5a41d2..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/fsdata.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_FSDATA_H -#define LWIP_FSDATA_H - -#include "lwip/apps/httpd_opts.h" -#include "lwip/apps/fs.h" - -struct fsdata_file { - const struct fsdata_file *next; - const unsigned char *name; - const unsigned char *data; - int len; - u8_t flags; -#if HTTPD_PRECALCULATED_CHECKSUM - u16_t chksum_count; - const struct fsdata_chksum *chksum; -#endif /* HTTPD_PRECALCULATED_CHECKSUM */ -}; - -#endif /* LWIP_FSDATA_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd.c deleted file mode 100644 index 43195d7c54a3445d13544cfff99f559ab2ab8873..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd.c +++ /dev/null @@ -1,2629 +0,0 @@ -/** - * @file - * LWIP HTTP server implementation - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Simon Goldschmidt - * - */ - -/** - * @defgroup httpd HTTP server - * @ingroup apps - * - * This httpd supports for a - * rudimentary server-side-include facility which will replace tags of the form - * in any file whose extension is .shtml, .shtm or .ssi with - * strings provided by an include handler whose pointer is provided to the - * module via function http_set_ssi_handler(). - * Additionally, a simple common - * gateway interface (CGI) handling mechanism has been added to allow clients - * to hook functions to particular request URIs. - * - * To enable SSI support, define label LWIP_HTTPD_SSI in lwipopts.h. - * To enable CGI support, define label LWIP_HTTPD_CGI in lwipopts.h. - * - * By default, the server assumes that HTTP headers are already present in - * each file stored in the file system. By defining LWIP_HTTPD_DYNAMIC_HEADERS in - * lwipopts.h, this behavior can be changed such that the server inserts the - * headers automatically based on the extension of the file being served. If - * this mode is used, be careful to ensure that the file system image used - * does not already contain the header information. - * - * File system images without headers can be created using the makefsfile - * tool with the -h command line option. - * - * - * Notes about valid SSI tags - * -------------------------- - * - * The following assumptions are made about tags used in SSI markers: - * - * 1. No tag may contain '-' or whitespace characters within the tag name. - * 2. Whitespace is allowed between the tag leadin "". - * 3. The maximum tag name length is LWIP_HTTPD_MAX_TAG_NAME_LEN, currently 8 characters. - * - * Notes on CGI usage - * ------------------ - * - * The simple CGI support offered here works with GET method requests only - * and can handle up to 16 parameters encoded into the URI. The handler - * function may not write directly to the HTTP output but must return a - * filename that the HTTP server will send to the browser as a response to - * the incoming CGI request. - * - * - * - * The list of supported file types is quite short, so if makefsdata complains - * about an unknown extension, make sure to add it (and its doctype) to - * the 'g_psHTTPHeaders' list. - */ -#include "lwip/init.h" -#include "lwip/apps/httpd.h" -#include "lwip/debug.h" -#include "lwip/stats.h" -#include "lwip/apps/fs.h" -#include "httpd_structs.h" -#include "lwip/def.h" -#include "lwip/ip.h" -#include "lwip/tcp.h" - -#include /* memset */ -#include /* atoi */ -#include - -#if LWIP_TCP && LWIP_CALLBACK_API - -/** Minimum length for a valid HTTP/0.9 request: "GET /\r\n" -> 7 bytes */ -#define MIN_REQ_LEN 7 - -#define CRLF "\r\n" -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE -#define HTTP11_CONNECTIONKEEPALIVE "Connection: keep-alive" -#define HTTP11_CONNECTIONKEEPALIVE2 "Connection: Keep-Alive" -#endif - -/** These defines check whether tcp_write has to copy data or not */ - -/** This was TI's check whether to let TCP copy data or not - * \#define HTTP_IS_DATA_VOLATILE(hs) ((hs->file < (char *)0x20000000) ? 0 : TCP_WRITE_FLAG_COPY) - */ -#ifndef HTTP_IS_DATA_VOLATILE -#if LWIP_HTTPD_SSI -/* Copy for SSI files, no copy for non-SSI files */ -#define HTTP_IS_DATA_VOLATILE(hs) ((hs)->ssi ? TCP_WRITE_FLAG_COPY : 0) -#else /* LWIP_HTTPD_SSI */ -/** Default: don't copy if the data is sent from file-system directly */ -#define HTTP_IS_DATA_VOLATILE(hs) (((hs->file != NULL) && (hs->handle != NULL) && (hs->file == \ - (const char*)hs->handle->data + hs->handle->len - hs->left)) \ - ? 0 : TCP_WRITE_FLAG_COPY) -#endif /* LWIP_HTTPD_SSI */ -#endif - -/** Default: headers are sent from ROM */ -#ifndef HTTP_IS_HDR_VOLATILE -#define HTTP_IS_HDR_VOLATILE(hs, ptr) 0 -#endif - -/* Return values for http_send_*() */ -#define HTTP_DATA_TO_SEND_BREAK 2 -#define HTTP_DATA_TO_SEND_CONTINUE 1 -#define HTTP_NO_DATA_TO_SEND 0 - -typedef struct -{ - const char *name; - u8_t shtml; -} default_filename; - -const default_filename g_psDefaultFilenames[] = { - {"/index.shtml", 1 }, - {"/index.ssi", 1 }, - {"/index.shtm", 1 }, - {"/index.html", 0 }, - {"/index.htm", 0 } -}; - -#define NUM_DEFAULT_FILENAMES (sizeof(g_psDefaultFilenames) / \ - sizeof(default_filename)) - -#if LWIP_HTTPD_SUPPORT_REQUESTLIST -/** HTTP request is copied here from pbufs for simple parsing */ -static char httpd_req_buf[LWIP_HTTPD_MAX_REQ_LENGTH+1]; -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - -#if LWIP_HTTPD_SUPPORT_POST -#if LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN > LWIP_HTTPD_MAX_REQUEST_URI_LEN -#define LWIP_HTTPD_URI_BUF_LEN LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN -#endif -#endif -#ifndef LWIP_HTTPD_URI_BUF_LEN -#define LWIP_HTTPD_URI_BUF_LEN LWIP_HTTPD_MAX_REQUEST_URI_LEN -#endif -#if LWIP_HTTPD_URI_BUF_LEN -/* Filename for response file to send when POST is finished or - * search for default files when a directory is requested. */ -static char http_uri_buf[LWIP_HTTPD_URI_BUF_LEN+1]; -#endif - -#if LWIP_HTTPD_DYNAMIC_HEADERS -/* The number of individual strings that comprise the headers sent before each - * requested file. - */ -#define NUM_FILE_HDR_STRINGS 5 -#define HDR_STRINGS_IDX_HTTP_STATUS 0 /* e.g. "HTTP/1.0 200 OK\r\n" */ -#define HDR_STRINGS_IDX_SERVER_NAME 1 /* e.g. "Server: "HTTPD_SERVER_AGENT"\r\n" */ -#define HDR_STRINGS_IDX_CONTENT_LEN_KEPALIVE 2 /* e.g. "Content-Length: xy\r\n" and/or "Connection: keep-alive\r\n" */ -#define HDR_STRINGS_IDX_CONTENT_LEN_NR 3 /* the byte count, when content-length is used */ -#define HDR_STRINGS_IDX_CONTENT_TYPE 4 /* the content type (or default answer content type including default document) */ - -/* The dynamically generated Content-Length buffer needs space for CRLF + NULL */ -#define LWIP_HTTPD_MAX_CONTENT_LEN_OFFSET 3 -#ifndef LWIP_HTTPD_MAX_CONTENT_LEN_SIZE -/* The dynamically generated Content-Length buffer shall be able to work with - ~953 MB (9 digits) */ -#define LWIP_HTTPD_MAX_CONTENT_LEN_SIZE (9 + LWIP_HTTPD_MAX_CONTENT_LEN_OFFSET) -#endif -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ - -#if LWIP_HTTPD_SSI - -#define HTTPD_LAST_TAG_PART 0xFFFF - -enum tag_check_state { - TAG_NONE, /* Not processing an SSI tag */ - TAG_LEADIN, /* Tag lead in "" being processed */ - TAG_SENDING /* Sending tag replacement string */ -}; - -struct http_ssi_state { - const char *parsed; /* Pointer to the first unparsed byte in buf. */ -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - const char *tag_started;/* Pointer to the first opening '<' of the tag. */ -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */ - const char *tag_end; /* Pointer to char after the closing '>' of the tag. */ - u32_t parse_left; /* Number of unparsed bytes in buf. */ - u16_t tag_index; /* Counter used by tag parsing state machine */ - u16_t tag_insert_len; /* Length of insert in string tag_insert */ -#if LWIP_HTTPD_SSI_MULTIPART - u16_t tag_part; /* Counter passed to and changed by tag insertion function to insert multiple times */ -#endif /* LWIP_HTTPD_SSI_MULTIPART */ - u8_t tag_name_len; /* Length of the tag name in string tag_name */ - char tag_name[LWIP_HTTPD_MAX_TAG_NAME_LEN + 1]; /* Last tag name extracted */ - char tag_insert[LWIP_HTTPD_MAX_TAG_INSERT_LEN + 1]; /* Insert string for tag_name */ - enum tag_check_state tag_state; /* State of the tag processor */ -}; -#endif /* LWIP_HTTPD_SSI */ - -struct http_state { -#if LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED - struct http_state *next; -#endif /* LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED */ - struct fs_file file_handle; - struct fs_file *handle; - const char *file; /* Pointer to first unsent byte in buf. */ - - struct tcp_pcb *pcb; -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - struct pbuf *req; -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - -#if LWIP_HTTPD_DYNAMIC_FILE_READ - char *buf; /* File read buffer. */ - int buf_len; /* Size of file read buffer, buf. */ -#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ - u32_t left; /* Number of unsent bytes in buf. */ - u8_t retries; -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - u8_t keepalive; -#endif /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ -#if LWIP_HTTPD_SSI - struct http_ssi_state *ssi; -#endif /* LWIP_HTTPD_SSI */ -#if LWIP_HTTPD_CGI - char *params[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Params extracted from the request URI */ - char *param_vals[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Values for each extracted param */ -#endif /* LWIP_HTTPD_CGI */ -#if LWIP_HTTPD_DYNAMIC_HEADERS - const char *hdrs[NUM_FILE_HDR_STRINGS]; /* HTTP headers to be sent. */ - char hdr_content_len[LWIP_HTTPD_MAX_CONTENT_LEN_SIZE]; - u16_t hdr_pos; /* The position of the first unsent header byte in the - current string */ - u16_t hdr_index; /* The index of the hdr string currently being sent. */ -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ -#if LWIP_HTTPD_TIMING - u32_t time_started; -#endif /* LWIP_HTTPD_TIMING */ -#if LWIP_HTTPD_SUPPORT_POST - u32_t post_content_len_left; -#if LWIP_HTTPD_POST_MANUAL_WND - u32_t unrecved_bytes; - u8_t no_auto_wnd; - u8_t post_finished; -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ -#endif /* LWIP_HTTPD_SUPPORT_POST*/ -}; - -#if HTTPD_USE_MEM_POOL -LWIP_MEMPOOL_DECLARE(HTTPD_STATE, MEMP_NUM_PARALLEL_HTTPD_CONNS, sizeof(struct http_state), "HTTPD_STATE") -#if LWIP_HTTPD_SSI -LWIP_MEMPOOL_DECLARE(HTTPD_SSI_STATE, MEMP_NUM_PARALLEL_HTTPD_SSI_CONNS, sizeof(struct http_ssi_state), "HTTPD_SSI_STATE") -#define HTTP_FREE_SSI_STATE(x) LWIP_MEMPOOL_FREE(HTTPD_SSI_STATE, (x)) -#define HTTP_ALLOC_SSI_STATE() (struct http_ssi_state *)LWIP_MEMPOOL_ALLOC(HTTPD_SSI_STATE) -#endif /* LWIP_HTTPD_SSI */ -#define HTTP_ALLOC_HTTP_STATE() (struct http_state *)LWIP_MEMPOOL_ALLOC(HTTPD_STATE) -#define HTTP_FREE_HTTP_STATE(x) LWIP_MEMPOOL_FREE(HTTPD_STATE, (x)) -#else /* HTTPD_USE_MEM_POOL */ -#define HTTP_ALLOC_HTTP_STATE() (struct http_state *)mem_malloc(sizeof(struct http_state)) -#define HTTP_FREE_HTTP_STATE(x) mem_free(x) -#if LWIP_HTTPD_SSI -#define HTTP_ALLOC_SSI_STATE() (struct http_ssi_state *)mem_malloc(sizeof(struct http_ssi_state)) -#define HTTP_FREE_SSI_STATE(x) mem_free(x) -#endif /* LWIP_HTTPD_SSI */ -#endif /* HTTPD_USE_MEM_POOL */ - -static err_t http_close_conn(struct tcp_pcb *pcb, struct http_state *hs); -static err_t http_close_or_abort_conn(struct tcp_pcb *pcb, struct http_state *hs, u8_t abort_conn); -static err_t http_find_file(struct http_state *hs, const char *uri, int is_09); -static err_t http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri, u8_t tag_check, char* params); -static err_t http_poll(void *arg, struct tcp_pcb *pcb); -static u8_t http_check_eof(struct tcp_pcb *pcb, struct http_state *hs); -#if LWIP_HTTPD_FS_ASYNC_READ -static void http_continue(void *connection); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - -#if LWIP_HTTPD_SSI -/* SSI insert handler function pointer. */ -tSSIHandler g_pfnSSIHandler; -#if !LWIP_HTTPD_SSI_RAW -int g_iNumTags; -const char **g_ppcTags; -#endif /* !LWIP_HTTPD_SSI_RAW */ - -#define LEN_TAG_LEAD_IN 5 -const char * const g_pcTagLeadIn = ""; -#endif /* LWIP_HTTPD_SSI */ - -#if LWIP_HTTPD_CGI -/* CGI handler information */ -const tCGI *g_pCGIs; -int g_iNumCGIs; -int http_cgi_paramcount; -#define http_cgi_params hs->params -#define http_cgi_param_vals hs->param_vals -#elif LWIP_HTTPD_CGI_SSI -char *http_cgi_params[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Params extracted from the request URI */ -char *http_cgi_param_vals[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Values for each extracted param */ -#endif /* LWIP_HTTPD_CGI */ - -#if LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED -/** global list of active HTTP connections, use to kill the oldest when - running out of memory */ -static struct http_state *http_connections; - -static void -http_add_connection(struct http_state *hs) -{ - /* add the connection to the list */ - hs->next = http_connections; - http_connections = hs; -} - -static void -http_remove_connection(struct http_state *hs) -{ - /* take the connection off the list */ - if (http_connections) { - if (http_connections == hs) { - http_connections = hs->next; - } else { - struct http_state *last; - for(last = http_connections; last->next != NULL; last = last->next) { - if (last->next == hs) { - last->next = hs->next; - break; - } - } - } - } -} - -static void -http_kill_oldest_connection(u8_t ssi_required) -{ - struct http_state *hs = http_connections; - struct http_state *hs_free_next = NULL; - while(hs && hs->next) { -#if LWIP_HTTPD_SSI - if (ssi_required) { - if (hs->next->ssi != NULL) { - hs_free_next = hs; - } - } else -#else /* LWIP_HTTPD_SSI */ - LWIP_UNUSED_ARG(ssi_required); -#endif /* LWIP_HTTPD_SSI */ - { - hs_free_next = hs; - } - LWIP_ASSERT("broken list", hs != hs->next); - hs = hs->next; - } - if (hs_free_next != NULL) { - LWIP_ASSERT("hs_free_next->next != NULL", hs_free_next->next != NULL); - LWIP_ASSERT("hs_free_next->next->pcb != NULL", hs_free_next->next->pcb != NULL); - /* send RST when killing a connection because of memory shortage */ - http_close_or_abort_conn(hs_free_next->next->pcb, hs_free_next->next, 1); /* this also unlinks the http_state from the list */ - } -} -#else /* LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED */ - -#define http_add_connection(hs) -#define http_remove_connection(hs) - -#endif /* LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED */ - -#if LWIP_HTTPD_SSI -/** Allocate as struct http_ssi_state. */ -static struct http_ssi_state* -http_ssi_state_alloc(void) -{ - struct http_ssi_state *ret = HTTP_ALLOC_SSI_STATE(); -#if LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED - if (ret == NULL) { - http_kill_oldest_connection(1); - ret = HTTP_ALLOC_SSI_STATE(); - } -#endif /* LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED */ - if (ret != NULL) { - memset(ret, 0, sizeof(struct http_ssi_state)); - } - return ret; -} - -/** Free a struct http_ssi_state. */ -static void -http_ssi_state_free(struct http_ssi_state *ssi) -{ - if (ssi != NULL) { - HTTP_FREE_SSI_STATE(ssi); - } -} -#endif /* LWIP_HTTPD_SSI */ - -/** Initialize a struct http_state. - */ -static void -http_state_init(struct http_state* hs) -{ - /* Initialize the structure. */ - memset(hs, 0, sizeof(struct http_state)); -#if LWIP_HTTPD_DYNAMIC_HEADERS - /* Indicate that the headers are not yet valid */ - hs->hdr_index = NUM_FILE_HDR_STRINGS; -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ -} - -/** Allocate a struct http_state. */ -static struct http_state* -http_state_alloc(void) -{ - struct http_state *ret = HTTP_ALLOC_HTTP_STATE(); -#if LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED - if (ret == NULL) { - http_kill_oldest_connection(0); - ret = HTTP_ALLOC_HTTP_STATE(); - } -#endif /* LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED */ - if (ret != NULL) { - http_state_init(ret); - http_add_connection(ret); - } - return ret; -} - -/** Free a struct http_state. - * Also frees the file data if dynamic. - */ -static void -http_state_eof(struct http_state *hs) -{ - if(hs->handle) { -#if LWIP_HTTPD_TIMING - u32_t ms_needed = sys_now() - hs->time_started; - u32_t needed = LWIP_MAX(1, (ms_needed/100)); - LWIP_DEBUGF(HTTPD_DEBUG_TIMING, ("httpd: needed %"U32_F" ms to send file of %d bytes -> %"U32_F" bytes/sec\n", - ms_needed, hs->handle->len, ((((u32_t)hs->handle->len) * 10) / needed))); -#endif /* LWIP_HTTPD_TIMING */ - fs_close(hs->handle); - hs->handle = NULL; - } -#if LWIP_HTTPD_DYNAMIC_FILE_READ - if (hs->buf != NULL) { - mem_free(hs->buf); - hs->buf = NULL; - } -#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ -#if LWIP_HTTPD_SSI - if (hs->ssi) { - http_ssi_state_free(hs->ssi); - hs->ssi = NULL; - } -#endif /* LWIP_HTTPD_SSI */ -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - if (hs->req) { - pbuf_free(hs->req); - hs->req = NULL; - } -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ -} - -/** Free a struct http_state. - * Also frees the file data if dynamic. - */ -static void -http_state_free(struct http_state *hs) -{ - if (hs != NULL) { - http_state_eof(hs); - http_remove_connection(hs); - HTTP_FREE_HTTP_STATE(hs); - } -} - -/** Call tcp_write() in a loop trying smaller and smaller length - * - * @param pcb tcp_pcb to send - * @param ptr Data to send - * @param length Length of data to send (in/out: on return, contains the - * amount of data sent) - * @param apiflags directly passed to tcp_write - * @return the return value of tcp_write - */ -static err_t -http_write(struct tcp_pcb *pcb, const void* ptr, u16_t *length, u8_t apiflags) -{ - u16_t len, max_len; - err_t err; - LWIP_ASSERT("length != NULL", length != NULL); - len = *length; - if (len == 0) { - return ERR_OK; - } - /* We cannot send more data than space available in the send buffer. */ - max_len = tcp_sndbuf(pcb); - if (max_len < len) { - len = max_len; - } -#ifdef HTTPD_MAX_WRITE_LEN - /* Additional limitation: e.g. don't enqueue more than 2*mss at once */ - max_len = HTTPD_MAX_WRITE_LEN(pcb); - if(len > max_len) { - len = max_len; - } -#endif /* HTTPD_MAX_WRITE_LEN */ - do { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Trying go send %d bytes\n", len)); - err = tcp_write(pcb, ptr, len, apiflags); - if (err == ERR_MEM) { - if ((tcp_sndbuf(pcb) == 0) || - (tcp_sndqueuelen(pcb) >= TCP_SND_QUEUELEN)) { - /* no need to try smaller sizes */ - len = 1; - } else { - len /= 2; - } - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, - ("Send failed, trying less (%d bytes)\n", len)); - } - } while ((err == ERR_MEM) && (len > 1)); - - if (err == ERR_OK) { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Sent %d bytes\n", len)); - *length = len; - } else { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Send failed with err %d (\"%s\")\n", err, lwip_strerr(err))); - *length = 0; - } - -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - /* ensure nagle is normally enabled (only disabled for persistent connections - when all data has been enqueued but the connection stays open for the next - request */ - tcp_nagle_enable(pcb); -#endif - - return err; -} - -/** - * The connection shall be actively closed (using RST to close from fault states). - * Reset the sent- and recv-callbacks. - * - * @param pcb the tcp pcb to reset callbacks - * @param hs connection state to free - */ -static err_t -http_close_or_abort_conn(struct tcp_pcb *pcb, struct http_state *hs, u8_t abort_conn) -{ - err_t err; - LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection %p\n", (void*)pcb)); - -#if LWIP_HTTPD_SUPPORT_POST - if (hs != NULL) { - if ((hs->post_content_len_left != 0) -#if LWIP_HTTPD_POST_MANUAL_WND - || ((hs->no_auto_wnd != 0) && (hs->unrecved_bytes != 0)) -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - ) { - /* make sure the post code knows that the connection is closed */ - http_uri_buf[0] = 0; - httpd_post_finished(hs, http_uri_buf, LWIP_HTTPD_URI_BUF_LEN); - } - } -#endif /* LWIP_HTTPD_SUPPORT_POST*/ - - - tcp_arg(pcb, NULL); - tcp_recv(pcb, NULL); - tcp_err(pcb, NULL); - tcp_poll(pcb, NULL, 0); - tcp_sent(pcb, NULL); - if (hs != NULL) { - http_state_free(hs); - } - - if (abort_conn) { - tcp_abort(pcb); - return ERR_OK; - } - err = tcp_close(pcb); - if (err != ERR_OK) { - LWIP_DEBUGF(HTTPD_DEBUG, ("Error %d closing %p\n", err, (void*)pcb)); - /* error closing, try again later in poll */ - tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL); - } - return err; -} - -/** - * The connection shall be actively closed. - * Reset the sent- and recv-callbacks. - * - * @param pcb the tcp pcb to reset callbacks - * @param hs connection state to free - */ -static err_t -http_close_conn(struct tcp_pcb *pcb, struct http_state *hs) -{ - return http_close_or_abort_conn(pcb, hs, 0); -} - -/** End of file: either close the connection (Connection: close) or - * close the file (Connection: keep-alive) - */ -static void -http_eof(struct tcp_pcb *pcb, struct http_state *hs) -{ - /* HTTP/1.1 persistent connection? (Not supported for SSI) */ -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - if (hs->keepalive) { - http_remove_connection(hs); - - http_state_eof(hs); - http_state_init(hs); - /* restore state: */ - hs->pcb = pcb; - hs->keepalive = 1; - http_add_connection(hs); - /* ensure nagle doesn't interfere with sending all data as fast as possible: */ - tcp_nagle_disable(pcb); - } else -#endif /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ - { - http_close_conn(pcb, hs); - } -} - -#if LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI -/** - * Extract URI parameters from the parameter-part of an URI in the form - * "test.cgi?x=y" @todo: better explanation! - * Pointers to the parameters are stored in hs->param_vals. - * - * @param hs http connection state - * @param params pointer to the NULL-terminated parameter string from the URI - * @return number of parameters extracted - */ -static int -extract_uri_parameters(struct http_state *hs, char *params) -{ - char *pair; - char *equals; - int loop; - - LWIP_UNUSED_ARG(hs); - - /* If we have no parameters at all, return immediately. */ - if(!params || (params[0] == '\0')) { - return(0); - } - - /* Get a pointer to our first parameter */ - pair = params; - - /* Parse up to LWIP_HTTPD_MAX_CGI_PARAMETERS from the passed string and ignore the - * remainder (if any) */ - for(loop = 0; (loop < LWIP_HTTPD_MAX_CGI_PARAMETERS) && pair; loop++) { - - /* Save the name of the parameter */ - http_cgi_params[loop] = pair; - - /* Remember the start of this name=value pair */ - equals = pair; - - /* Find the start of the next name=value pair and replace the delimiter - * with a 0 to terminate the previous pair string. */ - pair = strchr(pair, '&'); - if(pair) { - *pair = '\0'; - pair++; - } else { - /* We didn't find a new parameter so find the end of the URI and - * replace the space with a '\0' */ - pair = strchr(equals, ' '); - if(pair) { - *pair = '\0'; - } - - /* Revert to NULL so that we exit the loop as expected. */ - pair = NULL; - } - - /* Now find the '=' in the previous pair, replace it with '\0' and save - * the parameter value string. */ - equals = strchr(equals, '='); - if(equals) { - *equals = '\0'; - http_cgi_param_vals[loop] = equals + 1; - } else { - http_cgi_param_vals[loop] = NULL; - } - } - - return loop; -} -#endif /* LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI */ - -#if LWIP_HTTPD_SSI -/** - * Insert a tag (found in an shtml in the form of "" into the file. - * The tag's name is stored in ssi->tag_name (NULL-terminated), the replacement - * should be written to hs->tag_insert (up to a length of LWIP_HTTPD_MAX_TAG_INSERT_LEN). - * The amount of data written is stored to ssi->tag_insert_len. - * - * @todo: return tag_insert_len - maybe it can be removed from struct http_state? - * - * @param hs http connection state - */ -static void -get_tag_insert(struct http_state *hs) -{ -#if LWIP_HTTPD_SSI_RAW - const char* tag; -#else /* LWIP_HTTPD_SSI_RAW */ - int tag; -#endif /* LWIP_HTTPD_SSI_RAW */ - size_t len; - struct http_ssi_state *ssi; -#if LWIP_HTTPD_SSI_MULTIPART - u16_t current_tag_part; -#endif /* LWIP_HTTPD_SSI_MULTIPART */ - - LWIP_ASSERT("hs != NULL", hs != NULL); - ssi = hs->ssi; - LWIP_ASSERT("ssi != NULL", ssi != NULL); -#if LWIP_HTTPD_SSI_MULTIPART - current_tag_part = ssi->tag_part; - ssi->tag_part = HTTPD_LAST_TAG_PART; -#endif /* LWIP_HTTPD_SSI_MULTIPART */ -#if LWIP_HTTPD_SSI_RAW - tag = ssi->tag_name; -#endif - - if(g_pfnSSIHandler -#if !LWIP_HTTPD_SSI_RAW - && g_ppcTags && g_iNumTags -#endif /* !LWIP_HTTPD_SSI_RAW */ - ) { - - /* Find this tag in the list we have been provided. */ -#if LWIP_HTTPD_SSI_RAW - { -#else /* LWIP_HTTPD_SSI_RAW */ - for(tag = 0; tag < g_iNumTags; tag++) { - if(strcmp(ssi->tag_name, g_ppcTags[tag]) == 0) -#endif /* LWIP_HTTPD_SSI_RAW */ - { - ssi->tag_insert_len = g_pfnSSIHandler(tag, ssi->tag_insert, - LWIP_HTTPD_MAX_TAG_INSERT_LEN -#if LWIP_HTTPD_SSI_MULTIPART - , current_tag_part, &ssi->tag_part -#endif /* LWIP_HTTPD_SSI_MULTIPART */ -#if LWIP_HTTPD_FILE_STATE - , (hs->handle ? hs->handle->state : NULL) -#endif /* LWIP_HTTPD_FILE_STATE */ - ); -#if LWIP_HTTPD_SSI_RAW - if (ssi->tag_insert_len != HTTPD_SSI_TAG_UNKNOWN) -#endif /* LWIP_HTTPD_SSI_RAW */ - { - return; - } - } - } - } - - /* If we drop out, we were asked to serve a page which contains tags that - * we don't have a handler for. Merely echo back the tags with an error - * marker. */ -#define UNKNOWN_TAG1_TEXT "***UNKNOWN TAG " -#define UNKNOWN_TAG1_LEN 18 -#define UNKNOWN_TAG2_TEXT "***" -#define UNKNOWN_TAG2_LEN 7 - len = LWIP_MIN(sizeof(ssi->tag_name), LWIP_MIN(strlen(ssi->tag_name), - LWIP_HTTPD_MAX_TAG_INSERT_LEN - (UNKNOWN_TAG1_LEN + UNKNOWN_TAG2_LEN))); - MEMCPY(ssi->tag_insert, UNKNOWN_TAG1_TEXT, UNKNOWN_TAG1_LEN); - MEMCPY(&ssi->tag_insert[UNKNOWN_TAG1_LEN], ssi->tag_name, len); - MEMCPY(&ssi->tag_insert[UNKNOWN_TAG1_LEN + len], UNKNOWN_TAG2_TEXT, UNKNOWN_TAG2_LEN); - ssi->tag_insert[UNKNOWN_TAG1_LEN + len + UNKNOWN_TAG2_LEN] = 0; - - len = strlen(ssi->tag_insert); - LWIP_ASSERT("len <= 0xffff", len <= 0xffff); - ssi->tag_insert_len = (u16_t)len; -} -#endif /* LWIP_HTTPD_SSI */ - -#if LWIP_HTTPD_DYNAMIC_HEADERS -/** - * Generate the relevant HTTP headers for the given filename and write - * them into the supplied buffer. - */ -static void -get_http_headers(struct http_state *hs, const char *uri) -{ - size_t content_type; - char *tmp; - char *ext; - char *vars; - u8_t add_content_len; - - /* In all cases, the second header we send is the server identification - so set it here. */ - hs->hdrs[HDR_STRINGS_IDX_SERVER_NAME] = g_psHTTPHeaderStrings[HTTP_HDR_SERVER]; - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_KEPALIVE] = NULL; - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_NR] = NULL; - - /* Is this a normal file or the special case we use to send back the - default "404: Page not found" response? */ - if (uri == NULL) { - hs->hdrs[HDR_STRINGS_IDX_HTTP_STATUS] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND]; -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - if (hs->keepalive) { - hs->hdrs[HDR_STRINGS_IDX_CONTENT_TYPE] = g_psHTTPHeaderStrings[DEFAULT_404_HTML_PERSISTENT]; - } else -#endif - { - hs->hdrs[HDR_STRINGS_IDX_CONTENT_TYPE] = g_psHTTPHeaderStrings[DEFAULT_404_HTML]; - } - - /* Set up to send the first header string. */ - hs->hdr_index = 0; - hs->hdr_pos = 0; - return; - } - /* We are dealing with a particular filename. Look for one other - special case. We assume that any filename with "404" in it must be - indicative of a 404 server error whereas all other files require - the 200 OK header. */ - if (strstr(uri, "404")) { - hs->hdrs[HDR_STRINGS_IDX_HTTP_STATUS] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND]; - } else if (strstr(uri, "400")) { - hs->hdrs[HDR_STRINGS_IDX_HTTP_STATUS] = g_psHTTPHeaderStrings[HTTP_HDR_BAD_REQUEST]; - } else if (strstr(uri, "501")) { - hs->hdrs[HDR_STRINGS_IDX_HTTP_STATUS] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_IMPL]; - } else { - hs->hdrs[HDR_STRINGS_IDX_HTTP_STATUS] = g_psHTTPHeaderStrings[HTTP_HDR_OK]; - } - - /* Determine if the URI has any variables and, if so, temporarily remove - them. */ - vars = strchr(uri, '?'); - if(vars) { - *vars = '\0'; - } - - /* Get a pointer to the file extension. We find this by looking for the - last occurrence of "." in the filename passed. */ - ext = NULL; - tmp = strchr(uri, '.'); - while (tmp) { - ext = tmp + 1; - tmp = strchr(ext, '.'); - } - if (ext != NULL) { - /* Now determine the content type and add the relevant header for that. */ - for (content_type = 0; content_type < NUM_HTTP_HEADERS; content_type++) { - /* Have we found a matching extension? */ - if(!lwip_stricmp(g_psHTTPHeaders[content_type].extension, ext)) { - break; - } - } - } else { - content_type = NUM_HTTP_HEADERS; - } - - /* Reinstate the parameter marker if there was one in the original URI. */ - if (vars) { - *vars = '?'; - } - -#if LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI - /* Does the URL passed have any file extension? If not, we assume it - is a special-case URL used for control state notification and we do - not send any HTTP headers with the response. */ - if (!ext) { - /* Force the header index to a value indicating that all headers - have already been sent. */ - hs->hdr_index = NUM_FILE_HDR_STRINGS; - return; - } -#endif /* LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI */ - add_content_len = 1; - /* Did we find a matching extension? */ - if(content_type < NUM_HTTP_HEADERS) { - /* yes, store it */ - hs->hdrs[HDR_STRINGS_IDX_CONTENT_TYPE] = g_psHTTPHeaders[content_type].content_type; - } else if (!ext) { - /* no, no extension found -> use binary transfer to prevent the browser adding '.txt' on save */ - hs->hdrs[HDR_STRINGS_IDX_CONTENT_TYPE] = HTTP_HDR_APP; - } else { - /* No - use the default, plain text file type. */ - hs->hdrs[HDR_STRINGS_IDX_CONTENT_TYPE] = HTTP_HDR_DEFAULT_TYPE; - } - /* Add content-length header? */ -#if LWIP_HTTPD_SSI - if (hs->ssi != NULL) { - add_content_len = 0; /* @todo: get maximum file length from SSI */ - } else -#endif /* LWIP_HTTPD_SSI */ - if ((hs->handle == NULL) || - ((hs->handle->flags & (FS_FILE_FLAGS_HEADER_INCLUDED|FS_FILE_FLAGS_HEADER_PERSISTENT)) == FS_FILE_FLAGS_HEADER_INCLUDED)) { - add_content_len = 0; - } - if (add_content_len) { - size_t len; - lwip_itoa(hs->hdr_content_len, (size_t)LWIP_HTTPD_MAX_CONTENT_LEN_SIZE, - hs->handle->len); - len = strlen(hs->hdr_content_len); - if (len <= LWIP_HTTPD_MAX_CONTENT_LEN_SIZE - LWIP_HTTPD_MAX_CONTENT_LEN_OFFSET) { - SMEMCPY(&hs->hdr_content_len[len], CRLF "\0", 3); - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_NR] = hs->hdr_content_len; - } else { - add_content_len = 0; - } - } -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - if (add_content_len) { - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_KEPALIVE] = g_psHTTPHeaderStrings[HTTP_HDR_KEEPALIVE_LEN]; - } else { - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_KEPALIVE] = g_psHTTPHeaderStrings[HTTP_HDR_CONN_CLOSE]; - } -#else /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ - if (add_content_len) { - hs->hdrs[HDR_STRINGS_IDX_CONTENT_LEN_KEPALIVE] = g_psHTTPHeaderStrings[HTTP_HDR_CONTENT_LENGTH]; - } -#endif /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ - - /* Set up to send the first header string. */ - hs->hdr_index = 0; - hs->hdr_pos = 0; -} - -/** Sub-function of http_send(): send dynamic headers - * - * @returns: - HTTP_NO_DATA_TO_SEND: no new data has been enqueued - * - HTTP_DATA_TO_SEND_CONTINUE: continue with sending HTTP body - * - HTTP_DATA_TO_SEND_BREAK: data has been enqueued, headers pending, - * so don't send HTTP body yet - */ -static u8_t -http_send_headers(struct tcp_pcb *pcb, struct http_state *hs) -{ - err_t err; - u16_t len; - u8_t data_to_send = HTTP_NO_DATA_TO_SEND; - u16_t hdrlen, sendlen; - - /* How much data can we send? */ - len = tcp_sndbuf(pcb); - sendlen = len; - - while(len && (hs->hdr_index < NUM_FILE_HDR_STRINGS) && sendlen) { - const void *ptr; - u16_t old_sendlen; - u8_t apiflags; - /* How much do we have to send from the current header? */ - hdrlen = (u16_t)strlen(hs->hdrs[hs->hdr_index]); - - /* How much of this can we send? */ - sendlen = (len < (hdrlen - hs->hdr_pos)) ? len : (hdrlen - hs->hdr_pos); - - /* Send this amount of data or as much as we can given memory - * constraints. */ - ptr = (const void *)(hs->hdrs[hs->hdr_index] + hs->hdr_pos); - old_sendlen = sendlen; - apiflags = HTTP_IS_HDR_VOLATILE(hs, ptr); - if (hs->hdr_index == HDR_STRINGS_IDX_CONTENT_LEN_NR) { - /* content-length is always volatile */ - apiflags |= TCP_WRITE_FLAG_COPY; - } - if (hs->hdr_index < NUM_FILE_HDR_STRINGS - 1) { - apiflags |= TCP_WRITE_FLAG_MORE; - } - err = http_write(pcb, ptr, &sendlen, apiflags); - if ((err == ERR_OK) && (old_sendlen != sendlen)) { - /* Remember that we added some more data to be transmitted. */ - data_to_send = HTTP_DATA_TO_SEND_CONTINUE; - } else if (err != ERR_OK) { - /* special case: http_write does not try to send 1 byte */ - sendlen = 0; - } - - /* Fix up the header position for the next time round. */ - hs->hdr_pos += sendlen; - len -= sendlen; - - /* Have we finished sending this string? */ - if(hs->hdr_pos == hdrlen) { - /* Yes - move on to the next one */ - hs->hdr_index++; - /* skip headers that are NULL (not all headers are required) */ - while ((hs->hdr_index < NUM_FILE_HDR_STRINGS) && - (hs->hdrs[hs->hdr_index] == NULL)) { - hs->hdr_index++; - } - hs->hdr_pos = 0; - } - } - - if ((hs->hdr_index >= NUM_FILE_HDR_STRINGS) && (hs->file == NULL)) { - /* When we are at the end of the headers, check for data to send - * instead of waiting for ACK from remote side to continue - * (which would happen when sending files from async read). */ - if(http_check_eof(pcb, hs)) { - data_to_send = HTTP_DATA_TO_SEND_CONTINUE; - } - } - /* If we get here and there are still header bytes to send, we send - * the header information we just wrote immediately. If there are no - * more headers to send, but we do have file data to send, drop through - * to try to send some file data too. */ - if((hs->hdr_index < NUM_FILE_HDR_STRINGS) || !hs->file) { - LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_output\n")); - return HTTP_DATA_TO_SEND_BREAK; - } - return data_to_send; -} -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ - -/** Sub-function of http_send(): end-of-file (or block) is reached, - * either close the file or read the next block (if supported). - * - * @returns: 0 if the file is finished or no data has been read - * 1 if the file is not finished and data has been read - */ -static u8_t -http_check_eof(struct tcp_pcb *pcb, struct http_state *hs) -{ - int bytes_left; -#if LWIP_HTTPD_DYNAMIC_FILE_READ - int count; -#ifdef HTTPD_MAX_WRITE_LEN - int max_write_len; -#endif /* HTTPD_MAX_WRITE_LEN */ -#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ - - /* Do we have a valid file handle? */ - if (hs->handle == NULL) { - /* No - close the connection. */ - http_eof(pcb, hs); - return 0; - } - bytes_left = fs_bytes_left(hs->handle); - if (bytes_left <= 0) { - /* We reached the end of the file so this request is done. */ - LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); - http_eof(pcb, hs); - return 0; - } -#if LWIP_HTTPD_DYNAMIC_FILE_READ - /* Do we already have a send buffer allocated? */ - if(hs->buf) { - /* Yes - get the length of the buffer */ - count = LWIP_MIN(hs->buf_len, bytes_left); - } else { - /* We don't have a send buffer so allocate one now */ - count = tcp_sndbuf(pcb); - if(bytes_left < count) { - count = bytes_left; - } -#ifdef HTTPD_MAX_WRITE_LEN - /* Additional limitation: e.g. don't enqueue more than 2*mss at once */ - max_write_len = HTTPD_MAX_WRITE_LEN(pcb); - if (count > max_write_len) { - count = max_write_len; - } -#endif /* HTTPD_MAX_WRITE_LEN */ - do { - hs->buf = (char*)mem_malloc((mem_size_t)count); - if (hs->buf != NULL) { - hs->buf_len = count; - break; - } - count = count / 2; - } while (count > 100); - - /* Did we get a send buffer? If not, return immediately. */ - if (hs->buf == NULL) { - LWIP_DEBUGF(HTTPD_DEBUG, ("No buff\n")); - return 0; - } - } - - /* Read a block of data from the file. */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Trying to read %d bytes.\n", count)); - -#if LWIP_HTTPD_FS_ASYNC_READ - count = fs_read_async(hs->handle, hs->buf, count, http_continue, hs); -#else /* LWIP_HTTPD_FS_ASYNC_READ */ - count = fs_read(hs->handle, hs->buf, count); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - if (count < 0) { - if (count == FS_READ_DELAYED) { - /* Delayed read, wait for FS to unblock us */ - return 0; - } - /* We reached the end of the file so this request is done. - * @todo: close here for HTTP/1.1 when reading file fails */ - LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); - http_eof(pcb, hs); - return 0; - } - - /* Set up to send the block of data we just read */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Read %d bytes.\n", count)); - hs->left = count; - hs->file = hs->buf; -#if LWIP_HTTPD_SSI - if (hs->ssi) { - hs->ssi->parse_left = count; - hs->ssi->parsed = hs->buf; - } -#endif /* LWIP_HTTPD_SSI */ -#else /* LWIP_HTTPD_DYNAMIC_FILE_READ */ - LWIP_ASSERT("SSI and DYNAMIC_HEADERS turned off but eof not reached", 0); -#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ - return 1; -} - -/** Sub-function of http_send(): This is the normal send-routine for non-ssi files - * - * @returns: - 1: data has been written (so call tcp_ouput) - * - 0: no data has been written (no need to call tcp_output) - */ -static u8_t -http_send_data_nonssi(struct tcp_pcb *pcb, struct http_state *hs) -{ - err_t err; - u16_t len; - u8_t data_to_send = 0; - - /* We are not processing an SHTML file so no tag checking is necessary. - * Just send the data as we received it from the file. */ - len = (u16_t)LWIP_MIN(hs->left, 0xffff); - - err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); - if (err == ERR_OK) { - data_to_send = 1; - hs->file += len; - hs->left -= len; - } - - return data_to_send; -} - -#if LWIP_HTTPD_SSI -/** Sub-function of http_send(): This is the send-routine for ssi files - * - * @returns: - 1: data has been written (so call tcp_ouput) - * - 0: no data has been written (no need to call tcp_output) - */ -static u8_t -http_send_data_ssi(struct tcp_pcb *pcb, struct http_state *hs) -{ - err_t err = ERR_OK; - u16_t len; - u8_t data_to_send = 0; - - struct http_ssi_state *ssi = hs->ssi; - LWIP_ASSERT("ssi != NULL", ssi != NULL); - /* We are processing an SHTML file so need to scan for tags and replace - * them with insert strings. We need to be careful here since a tag may - * straddle the boundary of two blocks read from the file and we may also - * have to split the insert string between two tcp_write operations. */ - - /* How much data could we send? */ - len = tcp_sndbuf(pcb); - - /* Do we have remaining data to send before parsing more? */ - if(ssi->parsed > hs->file) { - len = (u16_t)LWIP_MIN(ssi->parsed - hs->file, 0xffff); - - err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); - if (err == ERR_OK) { - data_to_send = 1; - hs->file += len; - hs->left -= len; - } - - /* If the send buffer is full, return now. */ - if(tcp_sndbuf(pcb) == 0) { - return data_to_send; - } - } - - LWIP_DEBUGF(HTTPD_DEBUG, ("State %d, %d left\n", ssi->tag_state, (int)ssi->parse_left)); - - /* We have sent all the data that was already parsed so continue parsing - * the buffer contents looking for SSI tags. */ - while((ssi->parse_left) && (err == ERR_OK)) { - if (len == 0) { - return data_to_send; - } - switch(ssi->tag_state) { - case TAG_NONE: - /* We are not currently processing an SSI tag so scan for the - * start of the lead-in marker. */ - if(*ssi->parsed == g_pcTagLeadIn[0]) { - /* We found what could be the lead-in for a new tag so change - * state appropriately. */ - ssi->tag_state = TAG_LEADIN; - ssi->tag_index = 1; -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - ssi->tag_started = ssi->parsed; -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */ - } - - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - break; - - case TAG_LEADIN: - /* We are processing the lead-in marker, looking for the start of - * the tag name. */ - - /* Have we reached the end of the leadin? */ - if(ssi->tag_index == LEN_TAG_LEAD_IN) { - ssi->tag_index = 0; - ssi->tag_state = TAG_FOUND; - } else { - /* Have we found the next character we expect for the tag leadin? */ - if(*ssi->parsed == g_pcTagLeadIn[ssi->tag_index]) { - /* Yes - move to the next one unless we have found the complete - * leadin, in which case we start looking for the tag itself */ - ssi->tag_index++; - } else { - /* We found an unexpected character so this is not a tag. Move - * back to idle state. */ - ssi->tag_state = TAG_NONE; - } - - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - } - break; - - case TAG_FOUND: - /* We are reading the tag name, looking for the start of the - * lead-out marker and removing any whitespace found. */ - - /* Remove leading whitespace between the tag leading and the first - * tag name character. */ - if((ssi->tag_index == 0) && ((*ssi->parsed == ' ') || - (*ssi->parsed == '\t') || (*ssi->parsed == '\n') || - (*ssi->parsed == '\r'))) { - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - break; - } - - /* Have we found the end of the tag name? This is signalled by - * us finding the first leadout character or whitespace */ - if((*ssi->parsed == g_pcTagLeadOut[0]) || - (*ssi->parsed == ' ') || (*ssi->parsed == '\t') || - (*ssi->parsed == '\n') || (*ssi->parsed == '\r')) { - - if(ssi->tag_index == 0) { - /* We read a zero length tag so ignore it. */ - ssi->tag_state = TAG_NONE; - } else { - /* We read a non-empty tag so go ahead and look for the - * leadout string. */ - ssi->tag_state = TAG_LEADOUT; - LWIP_ASSERT("ssi->tag_index <= 0xff", ssi->tag_index <= 0xff); - ssi->tag_name_len = (u8_t)ssi->tag_index; - ssi->tag_name[ssi->tag_index] = '\0'; - if(*ssi->parsed == g_pcTagLeadOut[0]) { - ssi->tag_index = 1; - } else { - ssi->tag_index = 0; - } - } - } else { - /* This character is part of the tag name so save it */ - if(ssi->tag_index < LWIP_HTTPD_MAX_TAG_NAME_LEN) { - ssi->tag_name[ssi->tag_index++] = *ssi->parsed; - } else { - /* The tag was too long so ignore it. */ - ssi->tag_state = TAG_NONE; - } - } - - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - - break; - - /* We are looking for the end of the lead-out marker. */ - case TAG_LEADOUT: - /* Remove leading whitespace between the tag leading and the first - * tag leadout character. */ - if((ssi->tag_index == 0) && ((*ssi->parsed == ' ') || - (*ssi->parsed == '\t') || (*ssi->parsed == '\n') || - (*ssi->parsed == '\r'))) { - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - break; - } - - /* Have we found the next character we expect for the tag leadout? */ - if(*ssi->parsed == g_pcTagLeadOut[ssi->tag_index]) { - /* Yes - move to the next one unless we have found the complete - * leadout, in which case we need to call the client to process - * the tag. */ - - /* Move on to the next character in the buffer */ - ssi->parse_left--; - ssi->parsed++; - - if(ssi->tag_index == (LEN_TAG_LEAD_OUT - 1)) { - /* Call the client to ask for the insert string for the - * tag we just found. */ -#if LWIP_HTTPD_SSI_MULTIPART - ssi->tag_part = 0; /* start with tag part 0 */ -#endif /* LWIP_HTTPD_SSI_MULTIPART */ - get_tag_insert(hs); - - /* Next time through, we are going to be sending data - * immediately, either the end of the block we start - * sending here or the insert string. */ - ssi->tag_index = 0; - ssi->tag_state = TAG_SENDING; - ssi->tag_end = ssi->parsed; -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - ssi->parsed = ssi->tag_started; -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ - - /* If there is any unsent data in the buffer prior to the - * tag, we need to send it now. */ - if (ssi->tag_end > hs->file) { - /* How much of the data can we send? */ -#if LWIP_HTTPD_SSI_INCLUDE_TAG - len = (u16_t)LWIP_MIN(ssi->tag_end - hs->file, 0xffff); -#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ - /* we would include the tag in sending */ - len = (u16_t)LWIP_MIN(ssi->tag_started - hs->file, 0xffff); -#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ - - err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); - if (err == ERR_OK) { - data_to_send = 1; -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - if(ssi->tag_started <= hs->file) { - /* pretend to have sent the tag, too */ - len += ssi->tag_end - ssi->tag_started; - } -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ - hs->file += len; - hs->left -= len; - } - } - } else { - ssi->tag_index++; - } - } else { - /* We found an unexpected character so this is not a tag. Move - * back to idle state. */ - ssi->parse_left--; - ssi->parsed++; - ssi->tag_state = TAG_NONE; - } - break; - - /* - * We have found a valid tag and are in the process of sending - * data as a result of that discovery. We send either remaining data - * from the file prior to the insert point or the insert string itself. - */ - case TAG_SENDING: - /* Do we have any remaining file data to send from the buffer prior - * to the tag? */ - if(ssi->tag_end > hs->file) { - /* How much of the data can we send? */ -#if LWIP_HTTPD_SSI_INCLUDE_TAG - len = (u16_t)LWIP_MIN(ssi->tag_end - hs->file, 0xffff); -#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ - LWIP_ASSERT("hs->started >= hs->file", ssi->tag_started >= hs->file); - /* we would include the tag in sending */ - len = (u16_t)LWIP_MIN(ssi->tag_started - hs->file, 0xffff); -#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ - if (len != 0) { - err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); - } else { - err = ERR_OK; - } - if (err == ERR_OK) { - data_to_send = 1; -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - if(ssi->tag_started <= hs->file) { - /* pretend to have sent the tag, too */ - len += ssi->tag_end - ssi->tag_started; - } -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ - hs->file += len; - hs->left -= len; - } - } else { -#if LWIP_HTTPD_SSI_MULTIPART - if(ssi->tag_index >= ssi->tag_insert_len) { - /* Did the last SSIHandler have more to send? */ - if (ssi->tag_part != HTTPD_LAST_TAG_PART) { - /* If so, call it again */ - ssi->tag_index = 0; - get_tag_insert(hs); - } - } -#endif /* LWIP_HTTPD_SSI_MULTIPART */ - - /* Do we still have insert data left to send? */ - if(ssi->tag_index < ssi->tag_insert_len) { - /* We are sending the insert string itself. How much of the - * insert can we send? */ - len = (ssi->tag_insert_len - ssi->tag_index); - - /* Note that we set the copy flag here since we only have a - * single tag insert buffer per connection. If we don't do - * this, insert corruption can occur if more than one insert - * is processed before we call tcp_output. */ - err = http_write(pcb, &(ssi->tag_insert[ssi->tag_index]), &len, - HTTP_IS_TAG_VOLATILE(hs)); - if (err == ERR_OK) { - data_to_send = 1; - ssi->tag_index += len; - /* Don't return here: keep on sending data */ - } - } else { -#if LWIP_HTTPD_SSI_MULTIPART - if (ssi->tag_part == HTTPD_LAST_TAG_PART) -#endif /* LWIP_HTTPD_SSI_MULTIPART */ - { - /* We have sent all the insert data so go back to looking for - * a new tag. */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Everything sent.\n")); - ssi->tag_index = 0; - ssi->tag_state = TAG_NONE; -#if !LWIP_HTTPD_SSI_INCLUDE_TAG - ssi->parsed = ssi->tag_end; -#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ - } - } - break; - default: - break; - } - } - } - - /* If we drop out of the end of the for loop, this implies we must have - * file data to send so send it now. In TAG_SENDING state, we've already - * handled this so skip the send if that's the case. */ - if((ssi->tag_state != TAG_SENDING) && (ssi->parsed > hs->file)) { - len = (u16_t)LWIP_MIN(ssi->parsed - hs->file, 0xffff); - - err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); - if (err == ERR_OK) { - data_to_send = 1; - hs->file += len; - hs->left -= len; - } - } - return data_to_send; -} -#endif /* LWIP_HTTPD_SSI */ - -/** - * Try to send more data on this pcb. - * - * @param pcb the pcb to send data - * @param hs connection state - */ -static u8_t -http_send(struct tcp_pcb *pcb, struct http_state *hs) -{ - u8_t data_to_send = HTTP_NO_DATA_TO_SEND; - - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_send: pcb=%p hs=%p left=%d\n", (void*)pcb, - (void*)hs, hs != NULL ? (int)hs->left : 0)); - -#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND - if (hs->unrecved_bytes != 0) { - return 0; - } -#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ - - /* If we were passed a NULL state structure pointer, ignore the call. */ - if (hs == NULL) { - return 0; - } - -#if LWIP_HTTPD_FS_ASYNC_READ - /* Check if we are allowed to read from this file. - (e.g. SSI might want to delay sending until data is available) */ - if (!fs_is_file_ready(hs->handle, http_continue, hs)) { - return 0; - } -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - -#if LWIP_HTTPD_DYNAMIC_HEADERS - /* Do we have any more header data to send for this file? */ - if (hs->hdr_index < NUM_FILE_HDR_STRINGS) { - data_to_send = http_send_headers(pcb, hs); - if ((data_to_send != HTTP_DATA_TO_SEND_CONTINUE) && - (hs->hdr_index < NUM_FILE_HDR_STRINGS)) { - return data_to_send; - } - } -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ - - /* Have we run out of file data to send? If so, we need to read the next - * block from the file. */ - if (hs->left == 0) { - if (!http_check_eof(pcb, hs)) { - return 0; - } - } - -#if LWIP_HTTPD_SSI - if(hs->ssi) { - data_to_send = http_send_data_ssi(pcb, hs); - } else -#endif /* LWIP_HTTPD_SSI */ - { - data_to_send = http_send_data_nonssi(pcb, hs); - } - - if((hs->left == 0) && (fs_bytes_left(hs->handle) <= 0)) { - /* We reached the end of the file so this request is done. - * This adds the FIN flag right into the last data segment. */ - LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); - http_eof(pcb, hs); - return 0; - } - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("send_data end.\n")); - return data_to_send; -} - -#if LWIP_HTTPD_SUPPORT_EXTSTATUS -/** Initialize a http connection with a file to send for an error message - * - * @param hs http connection state - * @param error_nr HTTP error number - * @return ERR_OK if file was found and hs has been initialized correctly - * another err_t otherwise - */ -static err_t -http_find_error_file(struct http_state *hs, u16_t error_nr) -{ - const char *uri1, *uri2, *uri3; - err_t err; - - if (error_nr == 501) { - uri1 = "/501.html"; - uri2 = "/501.htm"; - uri3 = "/501.shtml"; - } else { - /* 400 (bad request is the default) */ - uri1 = "/400.html"; - uri2 = "/400.htm"; - uri3 = "/400.shtml"; - } - err = fs_open(&hs->file_handle, uri1); - if (err != ERR_OK) { - err = fs_open(&hs->file_handle, uri2); - if (err != ERR_OK) { - err = fs_open(&hs->file_handle, uri3); - if (err != ERR_OK) { - LWIP_DEBUGF(HTTPD_DEBUG, ("Error page for error %"U16_F" not found\n", - error_nr)); - return ERR_ARG; - } - } - } - return http_init_file(hs, &hs->file_handle, 0, NULL, 0, NULL); -} -#else /* LWIP_HTTPD_SUPPORT_EXTSTATUS */ -#define http_find_error_file(hs, error_nr) ERR_ARG -#endif /* LWIP_HTTPD_SUPPORT_EXTSTATUS */ - -/** - * Get the file struct for a 404 error page. - * Tries some file names and returns NULL if none found. - * - * @param uri pointer that receives the actual file name URI - * @return file struct for the error page or NULL no matching file was found - */ -static struct fs_file * -http_get_404_file(struct http_state *hs, const char **uri) -{ - err_t err; - - *uri = "/404.html"; - err = fs_open(&hs->file_handle, *uri); - if (err != ERR_OK) { - /* 404.html doesn't exist. Try 404.htm instead. */ - *uri = "/404.htm"; - err = fs_open(&hs->file_handle, *uri); - if (err != ERR_OK) { - /* 404.htm doesn't exist either. Try 404.shtml instead. */ - *uri = "/404.shtml"; - err = fs_open(&hs->file_handle, *uri); - if (err != ERR_OK) { - /* 404.htm doesn't exist either. Indicate to the caller that it should - * send back a default 404 page. - */ - *uri = NULL; - return NULL; - } - } - } - - return &hs->file_handle; -} - -#if LWIP_HTTPD_SUPPORT_POST -static err_t -http_handle_post_finished(struct http_state *hs) -{ -#if LWIP_HTTPD_POST_MANUAL_WND - /* Prevent multiple calls to httpd_post_finished, since it might have already - been called before from httpd_post_data_recved(). */ - if (hs->post_finished) { - return ERR_OK; - } - hs->post_finished = 1; -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - /* application error or POST finished */ - /* NULL-terminate the buffer */ - http_uri_buf[0] = 0; - httpd_post_finished(hs, http_uri_buf, LWIP_HTTPD_URI_BUF_LEN); - return http_find_file(hs, http_uri_buf, 0); -} - -/** Pass received POST body data to the application and correctly handle - * returning a response document or closing the connection. - * ATTENTION: The application is responsible for the pbuf now, so don't free it! - * - * @param hs http connection state - * @param p pbuf to pass to the application - * @return ERR_OK if passed successfully, another err_t if the response file - * hasn't been found (after POST finished) - */ -static err_t -http_post_rxpbuf(struct http_state *hs, struct pbuf *p) -{ - err_t err; - - if (p != NULL) { - /* adjust remaining Content-Length */ - if (hs->post_content_len_left < p->tot_len) { - hs->post_content_len_left = 0; - } else { - hs->post_content_len_left -= p->tot_len; - } - } -#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND - /* prevent connection being closed if httpd_post_data_recved() is called nested */ - hs->unrecved_bytes++; -#endif - err = httpd_post_receive_data(hs, p); -#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND - hs->unrecved_bytes--; -#endif - if (err != ERR_OK) { - /* Ignore remaining content in case of application error */ - hs->post_content_len_left = 0; - } - if (hs->post_content_len_left == 0) { -#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND - if (hs->unrecved_bytes != 0) { - return ERR_OK; - } -#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ - /* application error or POST finished */ - return http_handle_post_finished(hs); - } - - return ERR_OK; -} - -/** Handle a post request. Called from http_parse_request when method 'POST' - * is found. - * - * @param p The input pbuf (containing the POST header and body). - * @param hs The http connection state. - * @param data HTTP request (header and part of body) from input pbuf(s). - * @param data_len Size of 'data'. - * @param uri The HTTP URI parsed from input pbuf(s). - * @param uri_end Pointer to the end of 'uri' (here, the rest of the HTTP - * header starts). - * @return ERR_OK: POST correctly parsed and accepted by the application. - * ERR_INPROGRESS: POST not completely parsed (no error yet) - * another err_t: Error parsing POST or denied by the application - */ -static err_t -http_post_request(struct pbuf *inp, struct http_state *hs, - char *data, u16_t data_len, char *uri, char *uri_end) -{ - err_t err; - /* search for end-of-header (first double-CRLF) */ - char* crlfcrlf = lwip_strnstr(uri_end + 1, CRLF CRLF, data_len - (uri_end + 1 - data)); - - if (crlfcrlf != NULL) { - /* search for "Content-Length: " */ -#define HTTP_HDR_CONTENT_LEN "Content-Length: " -#define HTTP_HDR_CONTENT_LEN_LEN 16 -#define HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN 10 - char *scontent_len = lwip_strnstr(uri_end + 1, HTTP_HDR_CONTENT_LEN, crlfcrlf - (uri_end + 1)); - if (scontent_len != NULL) { - char *scontent_len_end = lwip_strnstr(scontent_len + HTTP_HDR_CONTENT_LEN_LEN, CRLF, HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN); - if (scontent_len_end != NULL) { - int content_len; - char *content_len_num = scontent_len + HTTP_HDR_CONTENT_LEN_LEN; - content_len = atoi(content_len_num); - if (content_len == 0) { - /* if atoi returns 0 on error, fix this */ - if ((content_len_num[0] != '0') || (content_len_num[1] != '\r')) { - content_len = -1; - } - } - if (content_len >= 0) { - /* adjust length of HTTP header passed to application */ - const char *hdr_start_after_uri = uri_end + 1; - u16_t hdr_len = (u16_t)LWIP_MIN(data_len, crlfcrlf + 4 - data); - u16_t hdr_data_len = (u16_t)LWIP_MIN(data_len, crlfcrlf + 4 - hdr_start_after_uri); - u8_t post_auto_wnd = 1; - http_uri_buf[0] = 0; - /* trim http header */ - *crlfcrlf = 0; - err = httpd_post_begin(hs, uri, hdr_start_after_uri, hdr_data_len, content_len, - http_uri_buf, LWIP_HTTPD_URI_BUF_LEN, &post_auto_wnd); - if (err == ERR_OK) { - /* try to pass in data of the first pbuf(s) */ - struct pbuf *q = inp; - u16_t start_offset = hdr_len; -#if LWIP_HTTPD_POST_MANUAL_WND - hs->no_auto_wnd = !post_auto_wnd; -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - /* set the Content-Length to be received for this POST */ - hs->post_content_len_left = (u32_t)content_len; - - /* get to the pbuf where the body starts */ - while((q != NULL) && (q->len <= start_offset)) { - start_offset -= q->len; - q = q->next; - } - if (q != NULL) { - /* hide the remaining HTTP header */ - pbuf_header(q, -(s16_t)start_offset); -#if LWIP_HTTPD_POST_MANUAL_WND - if (!post_auto_wnd) { - /* already tcp_recved() this data... */ - hs->unrecved_bytes = q->tot_len; - } -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - pbuf_ref(q); - return http_post_rxpbuf(hs, q); - } else if (hs->post_content_len_left == 0) { - q = pbuf_alloc(PBUF_RAW, 0, PBUF_REF); - return http_post_rxpbuf(hs, q); - } else { - return ERR_OK; - } - } else { - /* return file passed from application */ - return http_find_file(hs, http_uri_buf, 0); - } - } else { - LWIP_DEBUGF(HTTPD_DEBUG, ("POST received invalid Content-Length: %s\n", - content_len_num)); - return ERR_ARG; - } - } - } - /* If we come here, headers are fully received (double-crlf), but Content-Length - was not included. Since this is currently the only supported method, we have - to fail in this case! */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Error when parsing Content-Length\n")); - return ERR_ARG; - } - /* if we come here, the POST is incomplete */ -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - return ERR_INPROGRESS; -#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - return ERR_ARG; -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ -} - -#if LWIP_HTTPD_POST_MANUAL_WND -/** A POST implementation can call this function to update the TCP window. - * This can be used to throttle data reception (e.g. when received data is - * programmed to flash and data is received faster than programmed). - * - * @param connection A connection handle passed to httpd_post_begin for which - * httpd_post_finished has *NOT* been called yet! - * @param recved_len Length of data received (for window update) - */ -void httpd_post_data_recved(void *connection, u16_t recved_len) -{ - struct http_state *hs = (struct http_state*)connection; - if (hs != NULL) { - if (hs->no_auto_wnd) { - u16_t len = recved_len; - if (hs->unrecved_bytes >= recved_len) { - hs->unrecved_bytes -= recved_len; - } else { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_LEVEL_WARNING, ("httpd_post_data_recved: recved_len too big\n")); - len = (u16_t)hs->unrecved_bytes; - hs->unrecved_bytes = 0; - } - if (hs->pcb != NULL) { - if (len != 0) { - tcp_recved(hs->pcb, len); - } - if ((hs->post_content_len_left == 0) && (hs->unrecved_bytes == 0)) { - /* finished handling POST */ - http_handle_post_finished(hs); - http_send(hs->pcb, hs); - } - } - } - } -} -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - -#endif /* LWIP_HTTPD_SUPPORT_POST */ - -#if LWIP_HTTPD_FS_ASYNC_READ -/** Try to send more data if file has been blocked before - * This is a callback function passed to fs_read_async(). - */ -static void -http_continue(void *connection) -{ - struct http_state *hs = (struct http_state*)connection; - if (hs && (hs->pcb) && (hs->handle)) { - LWIP_ASSERT("hs->pcb != NULL", hs->pcb != NULL); - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("httpd_continue: try to send more data\n")); - if (http_send(hs->pcb, hs)) { - /* If we wrote anything to be sent, go ahead and send it now. */ - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("tcp_output\n")); - tcp_output(hs->pcb); - } - } -} -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - -/** - * When data has been received in the correct state, try to parse it - * as a HTTP request. - * - * @param inp the received pbuf - * @param hs the connection state - * @param pcb the tcp_pcb which received this packet - * @return ERR_OK if request was OK and hs has been initialized correctly - * ERR_INPROGRESS if request was OK so far but not fully received - * another err_t otherwise - */ -static err_t -http_parse_request(struct pbuf *inp, struct http_state *hs, struct tcp_pcb *pcb) -{ - char *data; - char *crlf; - u16_t data_len; - struct pbuf *p = inp; -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - u16_t clen; -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ -#if LWIP_HTTPD_SUPPORT_POST - err_t err; -#endif /* LWIP_HTTPD_SUPPORT_POST */ - - LWIP_UNUSED_ARG(pcb); /* only used for post */ - LWIP_ASSERT("p != NULL", p != NULL); - LWIP_ASSERT("hs != NULL", hs != NULL); - - if ((hs->handle != NULL) || (hs->file != NULL)) { - LWIP_DEBUGF(HTTPD_DEBUG, ("Received data while sending a file\n")); - /* already sending a file */ - /* @todo: abort? */ - return ERR_USE; - } - -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - - LWIP_DEBUGF(HTTPD_DEBUG, ("Received %"U16_F" bytes\n", p->tot_len)); - - /* first check allowed characters in this pbuf? */ - - /* enqueue the pbuf */ - if (hs->req == NULL) { - LWIP_DEBUGF(HTTPD_DEBUG, ("First pbuf\n")); - hs->req = p; - } else { - LWIP_DEBUGF(HTTPD_DEBUG, ("pbuf enqueued\n")); - pbuf_cat(hs->req, p); - } - /* increase pbuf ref counter as it is freed when we return but we want to - keep it on the req list */ - pbuf_ref(p); - - if (hs->req->next != NULL) { - data_len = LWIP_MIN(hs->req->tot_len, LWIP_HTTPD_MAX_REQ_LENGTH); - pbuf_copy_partial(hs->req, httpd_req_buf, data_len, 0); - data = httpd_req_buf; - } else -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - { - data = (char *)p->payload; - data_len = p->len; - if (p->len != p->tot_len) { - LWIP_DEBUGF(HTTPD_DEBUG, ("Warning: incomplete header due to chained pbufs\n")); - } - } - - /* received enough data for minimal request? */ - if (data_len >= MIN_REQ_LEN) { - /* wait for CRLF before parsing anything */ - crlf = lwip_strnstr(data, CRLF, data_len); - if (crlf != NULL) { -#if LWIP_HTTPD_SUPPORT_POST - int is_post = 0; -#endif /* LWIP_HTTPD_SUPPORT_POST */ - int is_09 = 0; - char *sp1, *sp2; - u16_t left_len, uri_len; - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("CRLF received, parsing request\n")); - /* parse method */ - if (!strncmp(data, "GET ", 4)) { - sp1 = data + 3; - /* received GET request */ - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received GET request\"\n")); -#if LWIP_HTTPD_SUPPORT_POST - } else if (!strncmp(data, "POST ", 5)) { - /* store request type */ - is_post = 1; - sp1 = data + 4; - /* received GET request */ - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received POST request\n")); -#endif /* LWIP_HTTPD_SUPPORT_POST */ - } else { - /* null-terminate the METHOD (pbuf is freed anyway wen returning) */ - data[4] = 0; - /* unsupported method! */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Unsupported request method (not implemented): \"%s\"\n", - data)); - return http_find_error_file(hs, 501); - } - /* if we come here, method is OK, parse URI */ - left_len = (u16_t)(data_len - ((sp1 +1) - data)); - sp2 = lwip_strnstr(sp1 + 1, " ", left_len); -#if LWIP_HTTPD_SUPPORT_V09 - if (sp2 == NULL) { - /* HTTP 0.9: respond with correct protocol version */ - sp2 = lwip_strnstr(sp1 + 1, CRLF, left_len); - is_09 = 1; -#if LWIP_HTTPD_SUPPORT_POST - if (is_post) { - /* HTTP/0.9 does not support POST */ - goto badrequest; - } -#endif /* LWIP_HTTPD_SUPPORT_POST */ - } -#endif /* LWIP_HTTPD_SUPPORT_V09 */ - uri_len = (u16_t)(sp2 - (sp1 + 1)); - if ((sp2 != 0) && (sp2 > sp1)) { - /* wait for CRLFCRLF (indicating end of HTTP headers) before parsing anything */ - if (lwip_strnstr(data, CRLF CRLF, data_len) != NULL) { - char *uri = sp1 + 1; -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - /* This is HTTP/1.0 compatible: for strict 1.1, a connection - would always be persistent unless "close" was specified. */ - if (!is_09 && (lwip_strnstr(data, HTTP11_CONNECTIONKEEPALIVE, data_len) || - lwip_strnstr(data, HTTP11_CONNECTIONKEEPALIVE2, data_len))) { - hs->keepalive = 1; - } else { - hs->keepalive = 0; - } -#endif /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ - /* null-terminate the METHOD (pbuf is freed anyway wen returning) */ - *sp1 = 0; - uri[uri_len] = 0; - LWIP_DEBUGF(HTTPD_DEBUG, ("Received \"%s\" request for URI: \"%s\"\n", - data, uri)); -#if LWIP_HTTPD_SUPPORT_POST - if (is_post) { -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - struct pbuf *q = hs->req; -#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - struct pbuf *q = inp; -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - err = http_post_request(q, hs, data, data_len, uri, sp2); - if (err != ERR_OK) { - /* restore header for next try */ - *sp1 = ' '; - *sp2 = ' '; - uri[uri_len] = ' '; - } - if (err == ERR_ARG) { - goto badrequest; - } - return err; - } else -#endif /* LWIP_HTTPD_SUPPORT_POST */ - { - return http_find_file(hs, uri, is_09); - } - } - } else { - LWIP_DEBUGF(HTTPD_DEBUG, ("invalid URI\n")); - } - } - } - -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - clen = pbuf_clen(hs->req); - if ((hs->req->tot_len <= LWIP_HTTPD_REQ_BUFSIZE) && - (clen <= LWIP_HTTPD_REQ_QUEUELEN)) { - /* request not fully received (too short or CRLF is missing) */ - return ERR_INPROGRESS; - } else -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - { -#if LWIP_HTTPD_SUPPORT_POST -badrequest: -#endif /* LWIP_HTTPD_SUPPORT_POST */ - LWIP_DEBUGF(HTTPD_DEBUG, ("bad request\n")); - /* could not parse request */ - return http_find_error_file(hs, 400); - } -} - -/** Try to find the file specified by uri and, if found, initialize hs - * accordingly. - * - * @param hs the connection state - * @param uri the HTTP header URI - * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response) - * @return ERR_OK if file was found and hs has been initialized correctly - * another err_t otherwise - */ -static err_t -http_find_file(struct http_state *hs, const char *uri, int is_09) -{ - size_t loop; - struct fs_file *file = NULL; - char *params = NULL; - err_t err; -#if LWIP_HTTPD_CGI - int i; -#endif /* LWIP_HTTPD_CGI */ -#if !LWIP_HTTPD_SSI - const -#endif /* !LWIP_HTTPD_SSI */ - /* By default, assume we will not be processing server-side-includes tags */ - u8_t tag_check = 0; - - /* Have we been asked for the default file (in root or a directory) ? */ -#if LWIP_HTTPD_MAX_REQUEST_URI_LEN - size_t uri_len = strlen(uri); - if ((uri_len > 0) && (uri[uri_len-1] == '/') && - ((uri != http_uri_buf) || (uri_len == 1))) { - size_t copy_len = LWIP_MIN(sizeof(http_uri_buf) - 1, uri_len - 1); - if (copy_len > 0) { - MEMCPY(http_uri_buf, uri, copy_len); - http_uri_buf[copy_len] = 0; - } -#else /* LWIP_HTTPD_MAX_REQUEST_URI_LEN */ - if ((uri[0] == '/') && (uri[1] == 0)) { -#endif /* LWIP_HTTPD_MAX_REQUEST_URI_LEN */ - /* Try each of the configured default filenames until we find one - that exists. */ - for (loop = 0; loop < NUM_DEFAULT_FILENAMES; loop++) { - const char* file_name; -#if LWIP_HTTPD_MAX_REQUEST_URI_LEN - if (copy_len > 0) { - size_t len_left = sizeof(http_uri_buf) - copy_len - 1; - if (len_left > 0) { - size_t name_len = strlen(g_psDefaultFilenames[loop].name); - size_t name_copy_len = LWIP_MIN(len_left, name_len); - MEMCPY(&http_uri_buf[copy_len], g_psDefaultFilenames[loop].name, name_copy_len); - } - file_name = http_uri_buf; - } else -#endif /* LWIP_HTTPD_MAX_REQUEST_URI_LEN */ - { - file_name = g_psDefaultFilenames[loop].name; - } - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Looking for %s...\n", file_name)); - err = fs_open(&hs->file_handle, file_name); - if(err == ERR_OK) { - uri = file_name; - file = &hs->file_handle; - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opened.\n")); -#if LWIP_HTTPD_SSI - tag_check = g_psDefaultFilenames[loop].shtml; -#endif /* LWIP_HTTPD_SSI */ - break; - } - } - } - if (file == NULL) { - /* No - we've been asked for a specific file. */ - /* First, isolate the base URI (without any parameters) */ - params = (char *)strchr(uri, '?'); - if (params != NULL) { - /* URI contains parameters. NULL-terminate the base URI */ - *params = '\0'; - params++; - } - -#if LWIP_HTTPD_CGI - http_cgi_paramcount = -1; - /* Does the base URI we have isolated correspond to a CGI handler? */ - if (g_iNumCGIs && g_pCGIs) { - for (i = 0; i < g_iNumCGIs; i++) { - if (strcmp(uri, g_pCGIs[i].pcCGIName) == 0) { - /* - * We found a CGI that handles this URI so extract the - * parameters and call the handler. - */ - http_cgi_paramcount = extract_uri_parameters(hs, params); - uri = g_pCGIs[i].pfnCGIHandler(i, http_cgi_paramcount, hs->params, - hs->param_vals); - break; - } - } - } -#endif /* LWIP_HTTPD_CGI */ - - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opening %s\n", uri)); - - err = fs_open(&hs->file_handle, uri); - if (err == ERR_OK) { - file = &hs->file_handle; - } else { - file = http_get_404_file(hs, &uri); - } -#if LWIP_HTTPD_SSI - if (file != NULL) { - /* See if we have been asked for an shtml file and, if so, - enable tag checking. */ - const char* ext = NULL, *sub; - char* param = (char*)strstr(uri, "?"); - if (param != NULL) { - /* separate uri from parameters for now, set back later */ - *param = 0; - } - sub = uri; - ext = uri; - for (sub = strstr(sub, "."); sub != NULL; sub = strstr(sub, ".")) - { - ext = sub; - sub++; - } - tag_check = 0; - for (loop = 0; loop < NUM_SHTML_EXTENSIONS; loop++) { - if (!lwip_stricmp(ext, g_pcSSIExtensions[loop])) { - tag_check = 1; - break; - } - } - if (param != NULL) { - *param = '?'; - } - } -#endif /* LWIP_HTTPD_SSI */ - } - if (file == NULL) { - /* None of the default filenames exist so send back a 404 page */ - file = http_get_404_file(hs, &uri); - } - return http_init_file(hs, file, is_09, uri, tag_check, params); -} - -/** Initialize a http connection with a file to send (if found). - * Called by http_find_file and http_find_error_file. - * - * @param hs http connection state - * @param file file structure to send (or NULL if not found) - * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response) - * @param uri the HTTP header URI - * @param tag_check enable SSI tag checking - * @param params != NULL if URI has parameters (separated by '?') - * @return ERR_OK if file was found and hs has been initialized correctly - * another err_t otherwise - */ -static err_t -http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri, - u8_t tag_check, char* params) -{ - if (file != NULL) { - /* file opened, initialise struct http_state */ -#if LWIP_HTTPD_SSI - if (tag_check) { - struct http_ssi_state *ssi = http_ssi_state_alloc(); - if (ssi != NULL) { - ssi->tag_index = 0; - ssi->tag_state = TAG_NONE; - ssi->parsed = file->data; - ssi->parse_left = file->len; - ssi->tag_end = file->data; - hs->ssi = ssi; - } - } -#else /* LWIP_HTTPD_SSI */ - LWIP_UNUSED_ARG(tag_check); -#endif /* LWIP_HTTPD_SSI */ - hs->handle = file; - hs->file = file->data; - LWIP_ASSERT("File length must be positive!", (file->len >= 0)); -#if LWIP_HTTPD_CUSTOM_FILES - if (file->is_custom_file && (file->data == NULL)) { - /* custom file, need to read data first (via fs_read_custom) */ - hs->left = 0; - } else -#endif /* LWIP_HTTPD_CUSTOM_FILES */ - { - hs->left = file->len; - } - hs->retries = 0; -#if LWIP_HTTPD_TIMING - hs->time_started = sys_now(); -#endif /* LWIP_HTTPD_TIMING */ -#if !LWIP_HTTPD_DYNAMIC_HEADERS - LWIP_ASSERT("HTTP headers not included in file system", - (hs->handle->flags & FS_FILE_FLAGS_HEADER_INCLUDED) != 0); -#endif /* !LWIP_HTTPD_DYNAMIC_HEADERS */ -#if LWIP_HTTPD_SUPPORT_V09 - if (is_09 && ((hs->handle->flags & FS_FILE_FLAGS_HEADER_INCLUDED) != 0)) { - /* HTTP/0.9 responses are sent without HTTP header, - search for the end of the header. */ - char *file_start = lwip_strnstr(hs->file, CRLF CRLF, hs->left); - if (file_start != NULL) { - size_t diff = file_start + 4 - hs->file; - hs->file += diff; - hs->left -= (u32_t)diff; - } - } -#endif /* LWIP_HTTPD_SUPPORT_V09*/ -#if LWIP_HTTPD_CGI_SSI - if (params != NULL) { - /* URI contains parameters, call generic CGI handler */ - int count; -#if LWIP_HTTPD_CGI - if (http_cgi_paramcount >= 0) { - count = http_cgi_paramcount; - } else -#endif - { - count = extract_uri_parameters(hs, params); - } - httpd_cgi_handler(uri, count, http_cgi_params, http_cgi_param_vals -#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE - , hs->handle->state -#endif /* LWIP_HTTPD_FILE_STATE */ - ); - } -#else /* LWIP_HTTPD_CGI_SSI */ - LWIP_UNUSED_ARG(params); -#endif /* LWIP_HTTPD_CGI_SSI */ - } else { - hs->handle = NULL; - hs->file = NULL; - hs->left = 0; - hs->retries = 0; - } -#if LWIP_HTTPD_DYNAMIC_HEADERS - /* Determine the HTTP headers to send based on the file extension of - * the requested URI. */ - if ((hs->handle == NULL) || ((hs->handle->flags & FS_FILE_FLAGS_HEADER_INCLUDED) == 0)) { - get_http_headers(hs, uri); - } -#else /* LWIP_HTTPD_DYNAMIC_HEADERS */ - LWIP_UNUSED_ARG(uri); -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - if (hs->keepalive) { -#if LWIP_HTTPD_SSI - if (hs->ssi != NULL) { - hs->keepalive = 0; - } else -#endif /* LWIP_HTTPD_SSI */ - { - if ((hs->handle != NULL) && - ((hs->handle->flags & (FS_FILE_FLAGS_HEADER_INCLUDED|FS_FILE_FLAGS_HEADER_PERSISTENT)) == FS_FILE_FLAGS_HEADER_INCLUDED)) { - hs->keepalive = 0; - } - } - } -#endif /* LWIP_HTTPD_SUPPORT_11_KEEPALIVE */ - return ERR_OK; -} - -/** - * The pcb had an error and is already deallocated. - * The argument might still be valid (if != NULL). - */ -static void -http_err(void *arg, err_t err) -{ - struct http_state *hs = (struct http_state *)arg; - LWIP_UNUSED_ARG(err); - - LWIP_DEBUGF(HTTPD_DEBUG, ("http_err: %s", lwip_strerr(err))); - - if (hs != NULL) { - http_state_free(hs); - } -} - -/** - * Data has been sent and acknowledged by the remote host. - * This means that more data can be sent. - */ -static err_t -http_sent(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct http_state *hs = (struct http_state *)arg; - - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_sent %p\n", (void*)pcb)); - - LWIP_UNUSED_ARG(len); - - if (hs == NULL) { - return ERR_OK; - } - - hs->retries = 0; - - http_send(pcb, hs); - - return ERR_OK; -} - -/** - * The poll function is called every 2nd second. - * If there has been no data sent (which resets the retries) in 8 seconds, close. - * If the last portion of a file has not been sent in 2 seconds, close. - * - * This could be increased, but we don't want to waste resources for bad connections. - */ -static err_t -http_poll(void *arg, struct tcp_pcb *pcb) -{ - struct http_state *hs = (struct http_state *)arg; - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: pcb=%p hs=%p pcb_state=%s\n", - (void*)pcb, (void*)hs, tcp_debug_state_str(pcb->state))); - - if (hs == NULL) { - err_t closed; - /* arg is null, close. */ - LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: arg is NULL, close\n")); - closed = http_close_conn(pcb, NULL); - LWIP_UNUSED_ARG(closed); -#if LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR - if (closed == ERR_MEM) { - tcp_abort(pcb); - return ERR_ABRT; - } -#endif /* LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR */ - return ERR_OK; - } else { - hs->retries++; - if (hs->retries == HTTPD_MAX_RETRIES) { - LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: too many retries, close\n")); - http_close_conn(pcb, hs); - return ERR_OK; - } - - /* If this connection has a file open, try to send some more data. If - * it has not yet received a GET request, don't do this since it will - * cause the connection to close immediately. */ - if(hs && (hs->handle)) { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: try to send more data\n")); - if(http_send(pcb, hs)) { - /* If we wrote anything to be sent, go ahead and send it now. */ - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("tcp_output\n")); - tcp_output(pcb); - } - } - } - - return ERR_OK; -} - -/** - * Data has been received on this pcb. - * For HTTP 1.0, this should normally only happen once (if the request fits in one packet). - */ -static err_t -http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct http_state *hs = (struct http_state *)arg; - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: pcb=%p pbuf=%p err=%s\n", (void*)pcb, - (void*)p, lwip_strerr(err))); - - if ((err != ERR_OK) || (p == NULL) || (hs == NULL)) { - /* error or closed by other side? */ - if (p != NULL) { - /* Inform TCP that we have taken the data. */ - tcp_recved(pcb, p->tot_len); - pbuf_free(p); - } - if (hs == NULL) { - /* this should not happen, only to be robust */ - LWIP_DEBUGF(HTTPD_DEBUG, ("Error, http_recv: hs is NULL, close\n")); - } - http_close_conn(pcb, hs); - return ERR_OK; - } - -#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND - if (hs->no_auto_wnd) { - hs->unrecved_bytes += p->tot_len; - } else -#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ - { - /* Inform TCP that we have taken the data. */ - tcp_recved(pcb, p->tot_len); - } - -#if LWIP_HTTPD_SUPPORT_POST - if (hs->post_content_len_left > 0) { - /* reset idle counter when POST data is received */ - hs->retries = 0; - /* this is data for a POST, pass the complete pbuf to the application */ - http_post_rxpbuf(hs, p); - /* pbuf is passed to the application, don't free it! */ - if (hs->post_content_len_left == 0) { - /* all data received, send response or close connection */ - http_send(pcb, hs); - } - return ERR_OK; - } else -#endif /* LWIP_HTTPD_SUPPORT_POST */ - { - if (hs->handle == NULL) { - err_t parsed = http_parse_request(p, hs, pcb); - LWIP_ASSERT("http_parse_request: unexpected return value", parsed == ERR_OK - || parsed == ERR_INPROGRESS ||parsed == ERR_ARG || parsed == ERR_USE); -#if LWIP_HTTPD_SUPPORT_REQUESTLIST - if (parsed != ERR_INPROGRESS) { - /* request fully parsed or error */ - if (hs->req != NULL) { - pbuf_free(hs->req); - hs->req = NULL; - } - } -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - pbuf_free(p); - if (parsed == ERR_OK) { -#if LWIP_HTTPD_SUPPORT_POST - if (hs->post_content_len_left == 0) -#endif /* LWIP_HTTPD_SUPPORT_POST */ - { - LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: data %p len %"S32_F"\n", (const void*)hs->file, hs->left)); - http_send(pcb, hs); - } - } else if (parsed == ERR_ARG) { - /* @todo: close on ERR_USE? */ - http_close_conn(pcb, hs); - } - } else { - LWIP_DEBUGF(HTTPD_DEBUG, ("http_recv: already sending data\n")); - /* already sending but still receiving data, we might want to RST here? */ - pbuf_free(p); - } - } - return ERR_OK; -} - -/** - * A new incoming connection has been accepted. - */ -static err_t -http_accept(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct http_state *hs; - LWIP_UNUSED_ARG(err); - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept %p / %p\n", (void*)pcb, arg)); - - if ((err != ERR_OK) || (pcb == NULL)) { - return ERR_VAL; - } - - /* Set priority */ - tcp_setprio(pcb, HTTPD_TCP_PRIO); - - /* Allocate memory for the structure that holds the state of the - connection - initialized by that function. */ - hs = http_state_alloc(); - if (hs == NULL) { - LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept: Out of memory, RST\n")); - return ERR_MEM; - } - hs->pcb = pcb; - - /* Tell TCP that this is the structure we wish to be passed for our - callbacks. */ - tcp_arg(pcb, hs); - - /* Set up the various callback functions */ - tcp_recv(pcb, http_recv); - tcp_err(pcb, http_err); - tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL); - tcp_sent(pcb, http_sent); - - return ERR_OK; -} - -/** - * @ingroup httpd - * Initialize the httpd: set up a listening PCB and bind it to the defined port - */ -void -httpd_init(void) -{ - struct tcp_pcb *pcb; - err_t err; - -#if HTTPD_USE_MEM_POOL - LWIP_MEMPOOL_INIT(HTTPD_STATE); -#if LWIP_HTTPD_SSI - LWIP_MEMPOOL_INIT(HTTPD_SSI_STATE); -#endif -#endif - LWIP_DEBUGF(HTTPD_DEBUG, ("httpd_init\n")); - - pcb = tcp_new_ip_type(IPADDR_TYPE_ANY); - LWIP_ASSERT("httpd_init: tcp_new failed", pcb != NULL); - tcp_setprio(pcb, HTTPD_TCP_PRIO); - /* set SOF_REUSEADDR here to explicitly bind httpd to multiple interfaces */ - err = tcp_bind(pcb, IP_ANY_TYPE, HTTPD_SERVER_PORT); - LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("httpd_init: tcp_bind failed", err == ERR_OK); - pcb = tcp_listen(pcb); - LWIP_ASSERT("httpd_init: tcp_listen failed", pcb != NULL); - tcp_accept(pcb, http_accept); -} - -#if LWIP_HTTPD_SSI -/** - * Set the SSI handler function. - * - * @param ssi_handler the SSI handler function - * @param tags an array of SSI tag strings to search for in SSI-enabled files - * @param num_tags number of tags in the 'tags' array - */ -void -http_set_ssi_handler(tSSIHandler ssi_handler, const char **tags, int num_tags) -{ - LWIP_DEBUGF(HTTPD_DEBUG, ("http_set_ssi_handler\n")); - - LWIP_ASSERT("no ssi_handler given", ssi_handler != NULL); - g_pfnSSIHandler = ssi_handler; - -#if LWIP_HTTPD_SSI_RAW - LWIP_UNUSED_ARG(tags); - LWIP_UNUSED_ARG(num_tags); -#else /* LWIP_HTTPD_SSI_RAW */ - LWIP_ASSERT("no tags given", tags != NULL); - LWIP_ASSERT("invalid number of tags", num_tags > 0); - - g_ppcTags = tags; - g_iNumTags = num_tags; -#endif /* !LWIP_HTTPD_SSI_RAW */ -} -#endif /* LWIP_HTTPD_SSI */ - -#if LWIP_HTTPD_CGI -/** - * Set an array of CGI filenames/handler functions - * - * @param cgis an array of CGI filenames/handler functions - * @param num_handlers number of elements in the 'cgis' array - */ -void -http_set_cgi_handlers(const tCGI *cgis, int num_handlers) -{ - LWIP_ASSERT("no cgis given", cgis != NULL); - LWIP_ASSERT("invalid number of handlers", num_handlers > 0); - - g_pCGIs = cgis; - g_iNumCGIs = num_handlers; -} -#endif /* LWIP_HTTPD_CGI */ - -#endif /* LWIP_TCP && LWIP_CALLBACK_API */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd_structs.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd_structs.h deleted file mode 100644 index fbd135a8c6a4f981f3184ec37086830c5dd10d64..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/httpd_structs.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef LWIP_HTTPD_STRUCTS_H -#define LWIP_HTTPD_STRUCTS_H - -#include "lwip/apps/httpd.h" - -#if LWIP_HTTPD_DYNAMIC_HEADERS -/** This struct is used for a list of HTTP header strings for various - * filename extensions. */ -typedef struct -{ - const char *extension; - const char *content_type; -} tHTTPHeader; - -/** A list of strings used in HTTP headers (see RFC 1945 HTTP/1.0 and - * RFC 2616 HTTP/1.1 for header field definitions) */ -static const char * const g_psHTTPHeaderStrings[] = -{ - "HTTP/1.0 200 OK\r\n", - "HTTP/1.0 404 File not found\r\n", - "HTTP/1.0 400 Bad Request\r\n", - "HTTP/1.0 501 Not Implemented\r\n", - "HTTP/1.1 200 OK\r\n", - "HTTP/1.1 404 File not found\r\n", - "HTTP/1.1 400 Bad Request\r\n", - "HTTP/1.1 501 Not Implemented\r\n", - "Content-Length: ", - "Connection: Close\r\n", - "Connection: keep-alive\r\n", - "Connection: keep-alive\r\nContent-Length: ", - "Server: "HTTPD_SERVER_AGENT"\r\n", - "\r\n

404: The requested file cannot be found.

\r\n" -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE - ,"Connection: keep-alive\r\nContent-Length: 77\r\n\r\n

404: The requested file cannot be found.

\r\n" -#endif -}; - -/* Indexes into the g_psHTTPHeaderStrings array */ -#define HTTP_HDR_OK 0 /* 200 OK */ -#define HTTP_HDR_NOT_FOUND 1 /* 404 File not found */ -#define HTTP_HDR_BAD_REQUEST 2 /* 400 Bad request */ -#define HTTP_HDR_NOT_IMPL 3 /* 501 Not Implemented */ -#define HTTP_HDR_OK_11 4 /* 200 OK */ -#define HTTP_HDR_NOT_FOUND_11 5 /* 404 File not found */ -#define HTTP_HDR_BAD_REQUEST_11 6 /* 400 Bad request */ -#define HTTP_HDR_NOT_IMPL_11 7 /* 501 Not Implemented */ -#define HTTP_HDR_CONTENT_LENGTH 8 /* Content-Length: (HTTP 1.0)*/ -#define HTTP_HDR_CONN_CLOSE 9 /* Connection: Close (HTTP 1.1) */ -#define HTTP_HDR_CONN_KEEPALIVE 10 /* Connection: keep-alive (HTTP 1.1) */ -#define HTTP_HDR_KEEPALIVE_LEN 11 /* Connection: keep-alive + Content-Length: (HTTP 1.1)*/ -#define HTTP_HDR_SERVER 12 /* Server: HTTPD_SERVER_AGENT */ -#define DEFAULT_404_HTML 13 /* default 404 body */ -#if LWIP_HTTPD_SUPPORT_11_KEEPALIVE -#define DEFAULT_404_HTML_PERSISTENT 14 /* default 404 body, but including Connection: keep-alive */ -#endif - - -#define HTTP_HDR_HTML "Content-type: text/html\r\n\r\n" -#define HTTP_HDR_SSI "Content-type: text/html\r\nExpires: Fri, 10 Apr 2008 14:00:00 GMT\r\nPragma: no-cache\r\n\r\n" -#define HTTP_HDR_GIF "Content-type: image/gif\r\n\r\n" -#define HTTP_HDR_PNG "Content-type: image/png\r\n\r\n" -#define HTTP_HDR_JPG "Content-type: image/jpeg\r\n\r\n" -#define HTTP_HDR_BMP "Content-type: image/bmp\r\n\r\n" -#define HTTP_HDR_ICO "Content-type: image/x-icon\r\n\r\n" -#define HTTP_HDR_APP "Content-type: application/octet-stream\r\n\r\n" -#define HTTP_HDR_JS "Content-type: application/javascript\r\n\r\n" -#define HTTP_HDR_RA "Content-type: application/javascript\r\n\r\n" -#define HTTP_HDR_CSS "Content-type: text/css\r\n\r\n" -#define HTTP_HDR_SWF "Content-type: application/x-shockwave-flash\r\n\r\n" -#define HTTP_HDR_XML "Content-type: text/xml\r\n\r\n" -#define HTTP_HDR_PDF "Content-type: application/pdf\r\n\r\n" -#define HTTP_HDR_JSON "Content-type: application/json\r\n\r\n" - -#define HTTP_HDR_DEFAULT_TYPE "Content-type: text/plain\r\n\r\n" - -/** A list of extension-to-HTTP header strings (see outdated RFC 1700 MEDIA TYPES - * and http://www.iana.org/assignments/media-types for registered content types - * and subtypes) */ -static const tHTTPHeader g_psHTTPHeaders[] = -{ - { "html", HTTP_HDR_HTML}, - { "htm", HTTP_HDR_HTML}, - { "shtml",HTTP_HDR_SSI}, - { "shtm", HTTP_HDR_SSI}, - { "ssi", HTTP_HDR_SSI}, - { "gif", HTTP_HDR_GIF}, - { "png", HTTP_HDR_PNG}, - { "jpg", HTTP_HDR_JPG}, - { "bmp", HTTP_HDR_BMP}, - { "ico", HTTP_HDR_ICO}, - { "class",HTTP_HDR_APP}, - { "cls", HTTP_HDR_APP}, - { "js", HTTP_HDR_JS}, - { "ram", HTTP_HDR_RA}, - { "css", HTTP_HDR_CSS}, - { "swf", HTTP_HDR_SWF}, - { "xml", HTTP_HDR_XML}, - { "xsl", HTTP_HDR_XML}, - { "pdf", HTTP_HDR_PDF}, - { "json", HTTP_HDR_JSON} -}; - -#define NUM_HTTP_HEADERS (sizeof(g_psHTTPHeaders) / sizeof(tHTTPHeader)) - -#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ - -#if LWIP_HTTPD_SSI -static const char * const g_pcSSIExtensions[] = { - ".shtml", ".shtm", ".ssi", ".xml" -}; -#define NUM_SHTML_EXTENSIONS (sizeof(g_pcSSIExtensions) / sizeof(const char *)) -#endif /* LWIP_HTTPD_SSI */ - -#endif /* LWIP_HTTPD_STRUCTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata deleted file mode 100644 index 37b4203e6e1c5dae1086e94702934d465bf1f818..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata +++ /dev/null @@ -1,97 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> fsdata.c"); - -chdir("fs"); -open(FILES, "find . -type f |"); - -while($file = ) { - - # Do not include files in CVS directories nor backup files. - if($file =~ /(CVS|~)/) { - next; - } - - chop($file); - - open(HEADER, "> /tmp/header") || die $!; - if($file =~ /404/) { - print(HEADER "HTTP/1.0 404 File not found\r\n"); - } else { - print(HEADER "HTTP/1.0 200 OK\r\n"); - } - print(HEADER "Server: lwIP/pre-0.6 (http://www.sics.se/~adam/lwip/)\r\n"); - if($file =~ /\.html$/) { - print(HEADER "Content-type: text/html\r\n"); - } elsif($file =~ /\.gif$/) { - print(HEADER "Content-type: image/gif\r\n"); - } elsif($file =~ /\.png$/) { - print(HEADER "Content-type: image/png\r\n"); - } elsif($file =~ /\.jpg$/) { - print(HEADER "Content-type: image/jpeg\r\n"); - } elsif($file =~ /\.class$/) { - print(HEADER "Content-type: application/octet-stream\r\n"); - } elsif($file =~ /\.ram$/) { - print(HEADER "Content-type: audio/x-pn-realaudio\r\n"); - } else { - print(HEADER "Content-type: text/plain\r\n"); - } - print(HEADER "\r\n"); - close(HEADER); - - unless($file =~ /\.plain$/ || $file =~ /cgi/) { - system("cat /tmp/header $file > /tmp/file"); - } else { - system("cp $file /tmp/file"); - } - - open(FILE, "/tmp/file"); - unlink("/tmp/file"); - unlink("/tmp/header"); - - $file =~ s/\.//; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@files, $file); -} - -for($i = 0; $i < @fvars; $i++) { - $file = $files[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define FS_NUMFILES $i\n"); diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata.c deleted file mode 100644 index 46dce5f346f8dec542dd68ad57add16e65dd97ba..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/makefsdata.c +++ /dev/null @@ -1,1033 +0,0 @@ -/** - * makefsdata: Converts a directory structure for use with the lwIP httpd. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jim Pettinato - * Simon Goldschmidt - * - * @todo: - * - take TCP_MSS, LWIP_TCP_TIMESTAMPS and - * PAYLOAD_ALIGN_TYPE/PAYLOAD_ALIGNMENT as arguments - */ - -#include -#include -#ifdef WIN32 -#define WIN32_LEAN_AND_MEAN -#include "windows.h" -#else -#include -#endif -#include -#include -#include -#include - -/** Makefsdata can generate *all* files deflate-compressed (where file size shrinks). - * Since nearly all browsers support this, this is a good way to reduce ROM size. - * To compress the files, "miniz.c" must be downloaded seperately. - */ -#ifndef MAKEFS_SUPPORT_DEFLATE -#define MAKEFS_SUPPORT_DEFLATE 0 -#endif - -#define COPY_BUFSIZE (1024*1024) /* 1 MByte */ - -#if MAKEFS_SUPPORT_DEFLATE -#include "../miniz.c" - -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned int uint; - -#define my_max(a,b) (((a) > (b)) ? (a) : (b)) -#define my_min(a,b) (((a) < (b)) ? (a) : (b)) - -/* COMP_OUT_BUF_SIZE is the size of the output buffer used during compression. - COMP_OUT_BUF_SIZE must be >= 1 and <= OUT_BUF_SIZE */ -#define COMP_OUT_BUF_SIZE COPY_BUFSIZE - -/* OUT_BUF_SIZE is the size of the output buffer used during decompression. - OUT_BUF_SIZE must be a power of 2 >= TINFL_LZ_DICT_SIZE (because the low-level decompressor not only writes, but reads from the output buffer as it decompresses) */ -#define OUT_BUF_SIZE COPY_BUFSIZE -static uint8 s_outbuf[OUT_BUF_SIZE]; -static uint8 s_checkbuf[OUT_BUF_SIZE]; - -/* tdefl_compressor contains all the state needed by the low-level compressor so it's a pretty big struct (~300k). - This example makes it a global vs. putting it on the stack, of course in real-world usage you'll probably malloc() or new it. */ -tdefl_compressor g_deflator; -tinfl_decompressor g_inflator; - -int deflate_level = 10; /* default compression level, can be changed via command line */ -#define USAGE_ARG_DEFLATE " [-defl<:compr_level>]" -#else /* MAKEFS_SUPPORT_DEFLATE */ -#define USAGE_ARG_DEFLATE "" -#endif /* MAKEFS_SUPPORT_DEFLATE */ - -/* Compatibility defines Win32 vs. DOS */ -#ifdef WIN32 - -#define FIND_T WIN32_FIND_DATAA -#define FIND_T_FILENAME(fInfo) (fInfo.cFileName) -#define FIND_T_IS_DIR(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) != 0) -#define FIND_T_IS_FILE(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0) -#define FIND_RET_T HANDLE -#define FINDFIRST_FILE(path, result) FindFirstFileA(path, result) -#define FINDFIRST_DIR(path, result) FindFirstFileA(path, result) -#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result) -#define FINDFIRST_SUCCEEDED(ret) (ret != INVALID_HANDLE_VALUE) -#define FINDNEXT_SUCCEEDED(ret) (ret == TRUE) - -#define GETCWD(path, len) GetCurrentDirectoryA(len, path) -#define CHDIR(path) SetCurrentDirectoryA(path) -#define CHDIR_SUCCEEDED(ret) (ret == TRUE) - -#else - -#define FIND_T struct ffblk -#define FIND_T_FILENAME(fInfo) (fInfo.ff_name) -#define FIND_T_IS_DIR(fInfo) ((fInfo.ff_attrib & FA_DIREC) == FA_DIREC) -#define FIND_T_IS_FILE(fInfo) (1) -#define FIND_RET_T int -#define FINDFIRST_FILE(path, result) findfirst(path, result, FA_ARCH) -#define FINDFIRST_DIR(path, result) findfirst(path, result, FA_DIREC) -#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result) -#define FINDFIRST_SUCCEEDED(ret) (ret == 0) -#define FINDNEXT_SUCCEEDED(ret) (ret == 0) - -#define GETCWD(path, len) getcwd(path, len) -#define CHDIR(path) chdir(path) -#define CHDIR_SUCCEEDED(ret) (ret == 0) - -#endif - -#define NEWLINE "\r\n" -#define NEWLINE_LEN 2 - -/* define this to get the header variables we use to build HTTP headers */ -#define LWIP_HTTPD_DYNAMIC_HEADERS 1 -#define LWIP_HTTPD_SSI 1 -#include "lwip/init.h" -#include "../httpd_structs.h" -#include "lwip/apps/fs.h" - -#include "../core/inet_chksum.c" -#include "../core/def.c" - -/** (Your server name here) */ -const char *serverID = "Server: "HTTPD_SERVER_AGENT"\r\n"; -char serverIDBuffer[1024]; - -/* change this to suit your MEM_ALIGNMENT */ -#define PAYLOAD_ALIGNMENT 4 -/* set this to 0 to prevent aligning payload */ -#define ALIGN_PAYLOAD 1 -/* define this to a type that has the required alignment */ -#define PAYLOAD_ALIGN_TYPE "unsigned int" -static int payload_alingment_dummy_counter = 0; - -#define HEX_BYTES_PER_LINE 16 - -#define MAX_PATH_LEN 256 - -struct file_entry -{ - struct file_entry* next; - const char* filename_c; -}; - -int process_sub(FILE *data_file, FILE *struct_file); -int process_file(FILE *data_file, FILE *struct_file, const char *filename); -int file_write_http_header(FILE *data_file, const char *filename, int file_size, u16_t *http_hdr_len, - u16_t *http_hdr_chksum, u8_t provide_content_len, int is_compressed); -int file_put_ascii(FILE *file, const char *ascii_string, int len, int *i); -int s_put_ascii(char *buf, const char *ascii_string, int len, int *i); -void concat_files(const char *file1, const char *file2, const char *targetfile); -int check_path(char* path, size_t size); - -/* 5 bytes per char + 3 bytes per line */ -static char file_buffer_c[COPY_BUFSIZE * 5 + ((COPY_BUFSIZE / HEX_BYTES_PER_LINE) * 3)]; - -char curSubdir[MAX_PATH_LEN]; -char lastFileVar[MAX_PATH_LEN]; -char hdr_buf[4096]; - -unsigned char processSubs = 1; -unsigned char includeHttpHeader = 1; -unsigned char useHttp11 = 0; -unsigned char supportSsi = 1; -unsigned char precalcChksum = 0; -unsigned char includeLastModified = 0; -#if MAKEFS_SUPPORT_DEFLATE -unsigned char deflateNonSsiFiles = 0; -size_t deflatedBytesReduced = 0; -size_t overallDataBytes = 0; -#endif - -struct file_entry* first_file = NULL; -struct file_entry* last_file = NULL; - -static void print_usage(void) -{ - os_printf(" Usage: htmlgen [targetdir] [-s] [-e] [-i] [-11] [-nossi] [-c] [-f:] [-m] [-svr:]" USAGE_ARG_DEFLATE NEWLINE NEWLINE); - os_printf(" targetdir: relative or absolute path to files to convert" NEWLINE); - os_printf(" switch -s: toggle processing of subdirectories (default is on)" NEWLINE); - os_printf(" switch -e: exclude HTTP header from file (header is created at runtime, default is off)" NEWLINE); - os_printf(" switch -11: include HTTP 1.1 header (1.0 is default)" NEWLINE); - os_printf(" switch -nossi: no support for SSI (cannot calculate Content-Length for SSI)" NEWLINE); - os_printf(" switch -c: precalculate checksums for all pages (default is off)" NEWLINE); - os_printf(" switch -f: target filename (default is \"fsdata.c\")" NEWLINE); - os_printf(" switch -m: include \"Last-Modified\" header based on file time" NEWLINE); - os_printf(" switch -svr: server identifier sent in HTTP response header ('Server' field)" NEWLINE); -#if MAKEFS_SUPPORT_DEFLATE - os_printf(" switch -defl: deflate-compress all non-SSI files (with opt. compr.-level, default=10)" NEWLINE); - os_printf(" ATTENTION: browser has to support \"Content-Encoding: deflate\"!" NEWLINE); -#endif - os_printf(" if targetdir not specified, htmlgen will attempt to" NEWLINE); - os_printf(" process files in subdirectory 'fs'" NEWLINE); -} - -int main(int argc, char *argv[]) -{ - char path[MAX_PATH_LEN]; - char appPath[MAX_PATH_LEN]; - FILE *data_file; - FILE *struct_file; - int filesProcessed; - int i; - char targetfile[MAX_PATH_LEN]; - strcpy(targetfile, "fsdata.c"); - - memset(path, 0, sizeof(path)); - memset(appPath, 0, sizeof(appPath)); - - os_printf(NEWLINE " makefsdata - HTML to C source converter" NEWLINE); - os_printf(" by Jim Pettinato - circa 2003 " NEWLINE); - os_printf(" extended by Simon Goldschmidt - 2009 " NEWLINE NEWLINE); - - strcpy(path, "fs"); - for (i = 1; i < argc; i++) { - if (argv[i] == NULL) { - continue; - } - if (argv[i][0] == '-') { - if (strstr(argv[i], "-svr:") == argv[i]) { - snprintf(serverIDBuffer, sizeof(serverIDBuffer), "Server: %s\r\n", &argv[i][5]); - serverID = serverIDBuffer; - os_printf("Using Server-ID: \"%s\"\n", serverID); - } else if (strstr(argv[i], "-s") == argv[i]) { - processSubs = 0; - } else if (strstr(argv[i], "-e") == argv[i]) { - includeHttpHeader = 0; - } else if (strstr(argv[i], "-11") == argv[i]) { - useHttp11 = 1; - } else if (strstr(argv[i], "-nossi") == argv[i]) { - supportSsi = 0; - } else if (strstr(argv[i], "-c") == argv[i]) { - precalcChksum = 1; - } else if (strstr(argv[i], "-f:") == argv[i]) { - strncpy(targetfile, &argv[i][3], sizeof(targetfile) - 1); - targetfile[sizeof(targetfile) - 1] = 0; - os_printf("Writing to file \"%s\"\n", targetfile); - } else if (strstr(argv[i], "-m") == argv[i]) { - includeLastModified = 1; - } else if (strstr(argv[i], "-defl") == argv[i]) { -#if MAKEFS_SUPPORT_DEFLATE - char* colon = strstr(argv[i], ":"); - if (colon) { - if (colon[1] != 0) { - int defl_level = atoi(&colon[1]); - if ((defl_level >= 0) && (defl_level <= 10)) { - deflate_level = defl_level; - } else { - os_printf("ERROR: deflate level must be [0..10]" NEWLINE); - exit(0); - } - } - } - deflateNonSsiFiles = 1; - os_printf("Deflating all non-SSI files with level %d (but only if size is reduced)" NEWLINE, deflate_level); -#else - os_printf("WARNING: Deflate support is disabled\n"); -#endif - } else if ((strstr(argv[i], "-?")) || (strstr(argv[i], "-h"))) { - print_usage(); - exit(0); - } - } else if ((argv[i][0] == '/') && (argv[i][1] == '?') && (argv[i][2] == 0)) { - print_usage(); - exit(0); - } else { - strncpy(path, argv[i], sizeof(path)-1); - path[sizeof(path)-1] = 0; - } - } - - if (!check_path(path, sizeof(path))) { - os_printf("Invalid path: \"%s\"." NEWLINE, path); - exit(-1); - } - - GETCWD(appPath, MAX_PATH_LEN); - /* if command line param or subdir named 'fs' not found spout usage verbiage */ - if (!CHDIR_SUCCEEDED(CHDIR(path))) { - /* if no subdir named 'fs' (or the one which was given) exists, spout usage verbiage */ - os_printf(" Failed to open directory \"%s\"." NEWLINE NEWLINE, path); - print_usage(); - exit(-1); - } - CHDIR(appPath); - - os_printf("HTTP %sheader will %s statically included." NEWLINE, - (includeHttpHeader ? (useHttp11 ? "1.1 " : "1.0 ") : ""), - (includeHttpHeader ? "be" : "not be")); - - sprintf(curSubdir, ""); /* start off in web page's root directory - relative paths */ - os_printf(" Processing all files in directory %s", path); - if (processSubs) { - os_printf(" and subdirectories..." NEWLINE NEWLINE); - } else { - os_printf("..." NEWLINE NEWLINE); - } - - data_file = fopen("fsdata.tmp", "wb"); - if (data_file == NULL) { - os_printf("Failed to create file \"fsdata.tmp\"\n"); - exit(-1); - } - struct_file = fopen("fshdr.tmp", "wb"); - if (struct_file == NULL) { - os_printf("Failed to create file \"fshdr.tmp\"\n"); - fclose(data_file); - exit(-1); - } - - CHDIR(path); - - fprintf(data_file, "#include \"lwip/apps/fs.h\"" NEWLINE); - fprintf(data_file, "#include \"lwip/def.h\"" NEWLINE); - fprintf(data_file, "#include \"fsdata.h\"" NEWLINE NEWLINE NEWLINE); - - fprintf(data_file, "#define file_NULL (struct fsdata_file *) NULL" NEWLINE NEWLINE NEWLINE); - /* define FS_FILE_FLAGS_HEADER_INCLUDED to 1 if not defined (compatibility with older httpd/fs) */ - fprintf(data_file, "#ifndef FS_FILE_FLAGS_HEADER_INCLUDED" NEWLINE "#define FS_FILE_FLAGS_HEADER_INCLUDED 1" NEWLINE "#endif" NEWLINE); - /* define FS_FILE_FLAGS_HEADER_PERSISTENT to 0 if not defined (compatibility with older httpd/fs: wasn't supported back then) */ - fprintf(data_file, "#ifndef FS_FILE_FLAGS_HEADER_PERSISTENT" NEWLINE "#define FS_FILE_FLAGS_HEADER_PERSISTENT 0" NEWLINE "#endif" NEWLINE); - - /* define alignment defines */ -#if ALIGN_PAYLOAD - fprintf(data_file, "/* FSDATA_FILE_ALIGNMENT: 0=off, 1=by variable, 2=by include */" NEWLINE "#ifndef FSDATA_FILE_ALIGNMENT" NEWLINE "#define FSDATA_FILE_ALIGNMENT 0" NEWLINE "#endif" NEWLINE); -#endif - fprintf(data_file, "#ifndef FSDATA_ALIGN_PRE" NEWLINE "#define FSDATA_ALIGN_PRE" NEWLINE "#endif" NEWLINE); - fprintf(data_file, "#ifndef FSDATA_ALIGN_POST" NEWLINE "#define FSDATA_ALIGN_POST" NEWLINE "#endif" NEWLINE); -#if ALIGN_PAYLOAD - fprintf(data_file, "#if FSDATA_FILE_ALIGNMENT==2" NEWLINE "#include \"fsdata_alignment.h\"" NEWLINE "#endif" NEWLINE); -#endif - - sprintf(lastFileVar, "NULL"); - - filesProcessed = process_sub(data_file, struct_file); - - /* data_file now contains all of the raw data.. now append linked list of - * file header structs to allow embedded app to search for a file name */ - fprintf(data_file, NEWLINE NEWLINE); - fprintf(struct_file, "#define FS_ROOT file_%s" NEWLINE, lastFileVar); - fprintf(struct_file, "#define FS_NUMFILES %d" NEWLINE NEWLINE, filesProcessed); - - fclose(data_file); - fclose(struct_file); - - CHDIR(appPath); - /* append struct_file to data_file */ - os_printf(NEWLINE "Creating target file..." NEWLINE NEWLINE); - concat_files("fsdata.tmp", "fshdr.tmp", targetfile); - - /* if succeeded, delete the temporary files */ - if (remove("fsdata.tmp") != 0) { - os_printf("Warning: failed to delete fsdata.tmp\n"); - } - if (remove("fshdr.tmp") != 0) { - os_printf("Warning: failed to delete fshdr.tmp\n"); - } - - os_printf(NEWLINE "Processed %d files - done." NEWLINE, filesProcessed); -#if MAKEFS_SUPPORT_DEFLATE - if (deflateNonSsiFiles) { - os_printf("(Deflated total byte reduction: %d bytes -> %d bytes (%.02f%%)" NEWLINE, - (int)overallDataBytes, (int)deflatedBytesReduced, (float)((deflatedBytesReduced*100.0)/overallDataBytes)); - } -#endif - os_printf(NEWLINE); - - while (first_file != NULL) { - struct file_entry* fe = first_file; - first_file = fe->next; - os_free(fe); - } - - return 0; -} - -int check_path(char* path, size_t size) -{ - size_t slen; - if (path[0] == 0) { - /* empty */ - return 0; - } - slen = strlen(path); - if (slen >= size) { - /* not NULL-terminated */ - return 0; - } - while ((slen > 0) && ((path[slen] == '\\') || (path[slen] == '/'))) { - /* path should not end with trailing backslash */ - path[slen] = 0; - slen--; - } - if (slen == 0) { - return 0; - } - return 1; -} - -static void copy_file(const char *filename_in, FILE *fout) -{ - FILE *fin; - size_t len; - void* buf; - fin = fopen(filename_in, "rb"); - if (fin == NULL) { - os_printf("Failed to open file \"%s\"\n", filename_in); - exit(-1); - } - buf = os_malloc(COPY_BUFSIZE); - while ((len = fread(buf, 1, COPY_BUFSIZE, fin)) > 0) { - fwrite(buf, 1, len, fout); - } - os_free(buf); - fclose(fin); -} - -void concat_files(const char *file1, const char *file2, const char *targetfile) -{ - FILE *fout; - fout = fopen(targetfile, "wb"); - if (fout == NULL) { - os_printf("Failed to open file \"%s\"\n", targetfile); - exit(-1); - } - copy_file(file1, fout); - copy_file(file2, fout); - fclose(fout); -} - -int process_sub(FILE *data_file, FILE *struct_file) -{ - FIND_T fInfo; - FIND_RET_T fret; - int filesProcessed = 0; - - if (processSubs) { - /* process subs recursively */ - size_t sublen = strlen(curSubdir); - size_t freelen = sizeof(curSubdir) - sublen - 1; - LWIP_ASSERT("sublen < sizeof(curSubdir)", sublen < sizeof(curSubdir)); - fret = FINDFIRST_DIR("*", &fInfo); - if (FINDFIRST_SUCCEEDED(fret)) { - do { - const char *curName = FIND_T_FILENAME(fInfo); - if ((curName[0] == '.') || (strcmp(curName, "CVS") == 0)) { - continue; - } - if (!FIND_T_IS_DIR(fInfo)) { - continue; - } - if (freelen > 0) { - CHDIR(curName); - strncat(curSubdir, "/", freelen); - strncat(curSubdir, curName, freelen - 1); - curSubdir[sizeof(curSubdir) - 1] = 0; - os_printf("processing subdirectory %s/..." NEWLINE, curSubdir); - filesProcessed += process_sub(data_file, struct_file); - CHDIR(".."); - curSubdir[sublen] = 0; - } else { - os_printf("WARNING: cannot process sub due to path length restrictions: \"%s/%s\"\n", curSubdir, curName); - } - } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo))); - } - } - - fret = FINDFIRST_FILE("*.*", &fInfo); - if (FINDFIRST_SUCCEEDED(fret)) { - /* at least one file in directory */ - do { - if (FIND_T_IS_FILE(fInfo)) { - const char *curName = FIND_T_FILENAME(fInfo); - os_printf("processing %s/%s..." NEWLINE, curSubdir, curName); - if (process_file(data_file, struct_file, curName) < 0) { - os_printf(NEWLINE "Error... aborting" NEWLINE); - return -1; - } - filesProcessed++; - } - } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo))); - } - return filesProcessed; -} - -u8_t* get_file_data(const char* filename, int* file_size, int can_be_compressed, int* is_compressed) -{ - FILE *inFile; - size_t fsize = 0; - u8_t* buf; - size_t r; - int rs; - inFile = fopen(filename, "rb"); - if (inFile == NULL) { - os_printf("Failed to open file \"%s\"\n", filename); - exit(-1); - } - fseek(inFile, 0, SEEK_END); - rs = ftell(inFile); - if (rs < 0) { - os_printf("ftell failed with %d\n", errno); - exit(-1); - } - fsize = (size_t)rs; - fseek(inFile, 0, SEEK_SET); - buf = (u8_t*)os_malloc(fsize); - LWIP_ASSERT("buf != NULL", buf != NULL); - r = fread(buf, 1, fsize, inFile); - *file_size = fsize; - *is_compressed = 0; -#if MAKEFS_SUPPORT_DEFLATE - overallDataBytes += fsize; - if (deflateNonSsiFiles) { - if (can_be_compressed) { - if (fsize < OUT_BUF_SIZE) { - u8_t* ret_buf; - tdefl_status status; - size_t in_bytes = fsize; - size_t out_bytes = OUT_BUF_SIZE; - const void *next_in = buf; - void *next_out = s_outbuf; - /* create tdefl() compatible flags (we have to compose the low-level flags ourselves, or use tdefl_create_comp_flags_from_zip_params() but that means MINIZ_NO_ZLIB_APIS can't be defined). */ - mz_uint comp_flags = s_tdefl_num_probes[MZ_MIN(10, deflate_level)] | ((deflate_level <= 3) ? TDEFL_GREEDY_PARSING_FLAG : 0); - if (!deflate_level) { - comp_flags |= TDEFL_FORCE_ALL_RAW_BLOCKS; - } - status = tdefl_init(&g_deflator, NULL, NULL, comp_flags); - if (status != TDEFL_STATUS_OKAY) { - os_printf("tdefl_init() failed!\n"); - exit(-1); - } - memset(s_outbuf, 0, sizeof(s_outbuf)); - status = tdefl_compress(&g_deflator, next_in, &in_bytes, next_out, &out_bytes, TDEFL_FINISH); - if (status != TDEFL_STATUS_DONE) { - os_printf("deflate failed: %d\n", status); - exit(-1); - } - LWIP_ASSERT("out_bytes <= COPY_BUFSIZE", out_bytes <= OUT_BUF_SIZE); - if (out_bytes < fsize) { - ret_buf = (u8_t*)os_malloc(out_bytes); - LWIP_ASSERT("ret_buf != NULL", ret_buf != NULL); - memcpy(ret_buf, s_outbuf, out_bytes); - { - /* sanity-check compression be inflating and comparing to the original */ - tinfl_status dec_status; - tinfl_decompressor inflator; - size_t dec_in_bytes = out_bytes; - size_t dec_out_bytes = OUT_BUF_SIZE; - next_out = s_checkbuf; - - tinfl_init(&inflator); - memset(s_checkbuf, 0, sizeof(s_checkbuf)); - dec_status = tinfl_decompress(&inflator, (const mz_uint8 *)ret_buf, &dec_in_bytes, s_checkbuf, (mz_uint8 *)next_out, &dec_out_bytes, 0); - LWIP_ASSERT("tinfl_decompress failed", dec_status == TINFL_STATUS_DONE); - LWIP_ASSERT("tinfl_decompress size mismatch", fsize == dec_out_bytes); - LWIP_ASSERT("decompressed memcmp failed", !memcmp(s_checkbuf, buf, fsize)); - } - /* free original buffer, use compressed data + size */ - os_free(buf); - buf = ret_buf; - *file_size = out_bytes; - os_printf(" - deflate: %d bytes -> %d bytes (%.02f%%)" NEWLINE, (int)fsize, (int)out_bytes, (float)((out_bytes*100.0)/fsize)); - deflatedBytesReduced += (size_t)(fsize - out_bytes); - *is_compressed = 1; - } else { - os_printf(" - uncompressed: (would be %d bytes larger using deflate)" NEWLINE, (int)(out_bytes - fsize)); - } - } else { - os_printf(" - uncompressed: (file is larger than deflate bufer)" NEWLINE); - } - } else { - os_printf(" - SSI file, cannot be compressed" NEWLINE); - } - } -#else - LWIP_UNUSED_ARG(can_be_compressed); -#endif - fclose(inFile); - return buf; -} - -void process_file_data(FILE* data_file, u8_t* file_data, size_t file_size) -{ - size_t written, i, src_off=0; - - size_t off = 0; - for (i = 0; i < file_size; i++) { - LWIP_ASSERT("file_buffer_c overflow", off < sizeof(file_buffer_c) - 5); - sprintf(&file_buffer_c[off], "0x%02.2x,", file_data[i]); - off += 5; - if ((++src_off % HEX_BYTES_PER_LINE) == 0) { - LWIP_ASSERT("file_buffer_c overflow", off < sizeof(file_buffer_c) - NEWLINE_LEN); - memcpy(&file_buffer_c[off], NEWLINE, NEWLINE_LEN); - off += NEWLINE_LEN; - } - if (off + 20 >= sizeof(file_buffer_c)) { - written = fwrite(file_buffer_c, 1, off, data_file); - LWIP_ASSERT("written == off", written == off); - off = 0; - } - } - written = fwrite(file_buffer_c, 1, off, data_file); - LWIP_ASSERT("written == off", written == off); -} - -int write_checksums(FILE *struct_file, const char *varname, - u16_t hdr_len, u16_t hdr_chksum, const u8_t* file_data, size_t file_size) -{ - int chunk_size = TCP_MSS; - int offset, src_offset; - size_t len; - int i = 0; -#if LWIP_TCP_TIMESTAMPS - /* when timestamps are used, usable space is 12 bytes less per segment */ - chunk_size -= 12; -#endif - - fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE); - fprintf(struct_file, "const struct fsdata_chksum chksums_%s[] = {" NEWLINE, varname); - - if (hdr_len > 0) { - /* add checksum for HTTP header */ - fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, 0, hdr_chksum, hdr_len); - i++; - } - src_offset = 0; - for (offset = hdr_len; ; offset += len) { - unsigned short chksum; - void* data = (void*)&file_data[src_offset]; - len = LWIP_MIN(chunk_size, (int)file_size - src_offset); - if (len == 0) { - break; - } - chksum = ~inet_chksum(data, (u16_t)len); - /* add checksum for data */ - fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, offset, chksum, len); - i++; - } - fprintf(struct_file, "};" NEWLINE); - fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE); - return i; -} - -static int is_valid_char_for_c_var(char x) -{ - if (((x >= 'A') && (x <= 'Z')) || - ((x >= 'a') && (x <= 'z')) || - ((x >= '0') && (x <= '9')) || - (x == '_')) { - return 1; - } - return 0; -} - -static void fix_filename_for_c(char* qualifiedName, size_t max_len) -{ - struct file_entry* f; - size_t len = strlen(qualifiedName); - char *new_name = (char*)os_malloc(len + 2); - int filename_ok; - int cnt = 0; - size_t i; - if (len + 3 == max_len) { - os_printf("File name too long: \"%s\"\n", qualifiedName); - exit(-1); - } - strcpy(new_name, qualifiedName); - for (i = 0; i < len; i++) { - if (!is_valid_char_for_c_var(new_name[i])) { - new_name[i] = '_'; - } - } - do { - filename_ok = 1; - for (f = first_file; f != NULL; f = f->next) { - if (!strcmp(f->filename_c, new_name)) { - filename_ok = 0; - cnt++; - /* try next unique file name */ - sprintf(&new_name[len], "%d", cnt); - break; - } - } - } while (!filename_ok && (cnt < 999)); - if (!filename_ok) { - os_printf("Failed to get unique file name: \"%s\"\n", qualifiedName); - exit(-1); - } - strcpy(qualifiedName, new_name); - os_free(new_name); -} - -static void register_filename(const char* qualifiedName) -{ - struct file_entry* fe = (struct file_entry*)os_malloc(sizeof(struct file_entry)); - fe->filename_c = strdup(qualifiedName); - fe->next = NULL; - if (first_file == NULL) { - first_file = last_file = fe; - } else { - last_file->next = fe; - last_file = fe; - } -} - -int is_ssi_file(const char* filename) -{ - size_t loop; - for (loop = 0; loop < NUM_SHTML_EXTENSIONS; loop++) { - if (strstr(filename, g_pcSSIExtensions[loop])) { - return 1; - } - } - return 0; -} - -int process_file(FILE *data_file, FILE *struct_file, const char *filename) -{ - char varname[MAX_PATH_LEN]; - int i = 0; - char qualifiedName[MAX_PATH_LEN]; - int file_size; - u16_t http_hdr_chksum = 0; - u16_t http_hdr_len = 0; - int chksum_count = 0; - u8_t flags = 0; - const char* flags_str; - u8_t has_content_len; - u8_t* file_data; - int is_compressed = 0; - - /* create qualified name (@todo: prepend slash or not?) */ - sprintf(qualifiedName,"%s/%s", curSubdir, filename); - /* create C variable name */ - strcpy(varname, qualifiedName); - /* convert slashes & dots to underscores */ - fix_filename_for_c(varname, MAX_PATH_LEN); - register_filename(varname); -#if ALIGN_PAYLOAD - /* to force even alignment of array, type 1 */ - fprintf(data_file, "#if FSDATA_FILE_ALIGNMENT==1" NEWLINE); - fprintf(data_file, "static const " PAYLOAD_ALIGN_TYPE " dummy_align_%s = %d;" NEWLINE, varname, payload_alingment_dummy_counter++); - fprintf(data_file, "#endif" NEWLINE); -#endif /* ALIGN_PAYLOAD */ - fprintf(data_file, "static const unsigned char FSDATA_ALIGN_PRE data_%s[] FSDATA_ALIGN_POST = {" NEWLINE, varname); - /* encode source file name (used by file system, not returned to browser) */ - fprintf(data_file, "/* %s (%d chars) */" NEWLINE, qualifiedName, strlen(qualifiedName)+1); - file_put_ascii(data_file, qualifiedName, strlen(qualifiedName)+1, &i); -#if ALIGN_PAYLOAD - /* pad to even number of bytes to assure payload is on aligned boundary */ - while(i % PAYLOAD_ALIGNMENT != 0) { - fprintf(data_file, "0x%02.2x,", 0); - i++; - } -#endif /* ALIGN_PAYLOAD */ - fprintf(data_file, NEWLINE); - - has_content_len = !is_ssi_file(filename); - file_data = get_file_data(filename, &file_size, includeHttpHeader && has_content_len, &is_compressed); - if (includeHttpHeader) { - file_write_http_header(data_file, filename, file_size, &http_hdr_len, &http_hdr_chksum, has_content_len, is_compressed); - flags = FS_FILE_FLAGS_HEADER_INCLUDED; - if (has_content_len) { - flags |= FS_FILE_FLAGS_HEADER_PERSISTENT; - } - } - if (precalcChksum) { - chksum_count = write_checksums(struct_file, varname, http_hdr_len, http_hdr_chksum, file_data, file_size); - } - - /* build declaration of struct fsdata_file in temp file */ - fprintf(struct_file, "const struct fsdata_file file_%s[] = { {" NEWLINE, varname); - fprintf(struct_file, "file_%s," NEWLINE, lastFileVar); - fprintf(struct_file, "data_%s," NEWLINE, varname); - fprintf(struct_file, "data_%s + %d," NEWLINE, varname, i); - fprintf(struct_file, "sizeof(data_%s) - %d," NEWLINE, varname, i); - switch(flags) - { - case(FS_FILE_FLAGS_HEADER_INCLUDED): - flags_str = "FS_FILE_FLAGS_HEADER_INCLUDED"; - break; - case(FS_FILE_FLAGS_HEADER_PERSISTENT): - flags_str = "FS_FILE_FLAGS_HEADER_PERSISTENT"; - break; - case(FS_FILE_FLAGS_HEADER_INCLUDED | FS_FILE_FLAGS_HEADER_PERSISTENT): - flags_str = "FS_FILE_FLAGS_HEADER_INCLUDED | FS_FILE_FLAGS_HEADER_PERSISTENT"; - break; - default: - flags_str = "0"; - break; - } - fprintf(struct_file, "%s," NEWLINE, flags_str); - if (precalcChksum) { - fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE); - fprintf(struct_file, "%d, chksums_%s," NEWLINE, chksum_count, varname); - fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE); - } - fprintf(struct_file, "}};" NEWLINE NEWLINE); - strcpy(lastFileVar, varname); - - /* write actual file contents */ - i = 0; - fprintf(data_file, NEWLINE "/* raw file data (%d bytes) */" NEWLINE, file_size); - process_file_data(data_file, file_data, file_size); - fprintf(data_file, "};" NEWLINE NEWLINE); - os_free(file_data); - return 0; -} - -int file_write_http_header(FILE *data_file, const char *filename, int file_size, u16_t *http_hdr_len, - u16_t *http_hdr_chksum, u8_t provide_content_len, int is_compressed) -{ - int i = 0; - int response_type = HTTP_HDR_OK; - const char* file_type; - const char *cur_string; - size_t cur_len; - int written = 0; - size_t hdr_len = 0; - u16_t acc; - const char *file_ext; - int j; - u8_t provide_last_modified = includeLastModified; - - memset(hdr_buf, 0, sizeof(hdr_buf)); - - if (useHttp11) { - response_type = HTTP_HDR_OK_11; - } - - fprintf(data_file, NEWLINE "/* HTTP header */"); - if (strstr(filename, "404") == filename) { - response_type = HTTP_HDR_NOT_FOUND; - if (useHttp11) { - response_type = HTTP_HDR_NOT_FOUND_11; - } - } else if (strstr(filename, "400") == filename) { - response_type = HTTP_HDR_BAD_REQUEST; - if (useHttp11) { - response_type = HTTP_HDR_BAD_REQUEST_11; - } - } else if (strstr(filename, "501") == filename) { - response_type = HTTP_HDR_NOT_IMPL; - if (useHttp11) { - response_type = HTTP_HDR_NOT_IMPL_11; - } - } - cur_string = g_psHTTPHeaderStrings[response_type]; - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - i = 0; - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - } - - cur_string = serverID; - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - i = 0; - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - } - - file_ext = filename; - if (file_ext != NULL) { - while(strstr(file_ext, ".") != NULL) { - file_ext = strstr(file_ext, "."); - file_ext++; - } - } - if ((file_ext == NULL) || (*file_ext == 0)) { - os_printf("failed to get extension for file \"%s\", using default.\n", filename); - file_type = HTTP_HDR_DEFAULT_TYPE; - } else { - file_type = NULL; - for (j = 0; j < NUM_HTTP_HEADERS; j++) { - if (!strcmp(file_ext, g_psHTTPHeaders[j].extension)) { - file_type = g_psHTTPHeaders[j].content_type; - break; - } - } - if (file_type == NULL) { - os_printf("failed to get file type for extension \"%s\", using default.\n", file_ext); - file_type = HTTP_HDR_DEFAULT_TYPE; - } - } - - /* Content-Length is used for persistent connections in HTTP/1.1 but also for - download progress in older versions - @todo: just use a big-enough buffer and let the HTTPD send spaces? */ - if (provide_content_len) { - char intbuf[MAX_PATH_LEN]; - int content_len = file_size; - memset(intbuf, 0, sizeof(intbuf)); - cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONTENT_LENGTH]; - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s%d\r\n\" (%d+ bytes) */" NEWLINE, cur_string, content_len, cur_len+2); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - } - - _itoa(content_len, intbuf, 10); - strcat(intbuf, "\r\n"); - cur_len = strlen(intbuf); - written += file_put_ascii(data_file, intbuf, cur_len, &i); - i = 0; - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], intbuf, cur_len); - hdr_len += cur_len; - } - } - if (provide_last_modified) { - char modbuf[256]; - struct stat stat_data; - struct tm* t; - memset(modbuf, 0, sizeof(modbuf)); - memset(&stat_data, 0, sizeof(stat_data)); - cur_string = modbuf; - strcpy(modbuf, "Last-Modified: "); - if (stat(filename, &stat_data) != 0) { - os_printf("stat(%s) failed with error %d\n", filename, errno); - exit(-1); - } - t = gmtime(&stat_data.st_mtime); - if (t == NULL) { - os_printf("gmtime() failed with error %d\n", errno); - exit(-1); - } - strftime(&modbuf[15], sizeof(modbuf)-15, "%a, %d %b %Y %H:%M:%S GMT", t); - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\"\r\n\" (%d+ bytes) */" NEWLINE, cur_string, cur_len+2); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - } - - modbuf[0] = 0; - strcat(modbuf, "\r\n"); - cur_len = strlen(modbuf); - written += file_put_ascii(data_file, modbuf, cur_len, &i); - i = 0; - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], modbuf, cur_len); - hdr_len += cur_len; - } - } - - /* HTTP/1.1 implements persistent connections */ - if (useHttp11) { - if (provide_content_len) { - cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONN_KEEPALIVE]; - } else { - /* no Content-Length available, so a persistent connection is no possible - because the client does not know the data length */ - cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONN_CLOSE]; - } - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - i = 0; - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - } - } - -#if MAKEFS_SUPPORT_DEFLATE - if (is_compressed) { - /* tell the client about the deflate encoding */ - LWIP_ASSERT("error", deflateNonSsiFiles); - cur_string = "Content-Encoding: deflate\r\n"; - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - i = 0; - } -#else - LWIP_UNUSED_ARG(is_compressed); -#endif - - /* write content-type, ATTENTION: this includes the double-CRLF! */ - cur_string = file_type; - cur_len = strlen(cur_string); - fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); - written += file_put_ascii(data_file, cur_string, cur_len, &i); - i = 0; - - /* ATTENTION: headers are done now (double-CRLF has been written!) */ - - if (precalcChksum) { - memcpy(&hdr_buf[hdr_len], cur_string, cur_len); - hdr_len += cur_len; - - LWIP_ASSERT("hdr_len <= 0xffff", hdr_len <= 0xffff); - LWIP_ASSERT("strlen(hdr_buf) == hdr_len", strlen(hdr_buf) == hdr_len); - acc = ~inet_chksum(hdr_buf, (u16_t)hdr_len); - *http_hdr_len = (u16_t)hdr_len; - *http_hdr_chksum = acc; - } - - return written; -} - -int file_put_ascii(FILE *file, const char* ascii_string, int len, int *i) -{ - int x; - for (x = 0; x < len; x++) { - unsigned char cur = ascii_string[x]; - fprintf(file, "0x%02.2x,", cur); - if ((++(*i) % HEX_BYTES_PER_LINE) == 0) { - fprintf(file, NEWLINE); - } - } - return len; -} - -int s_put_ascii(char *buf, const char *ascii_string, int len, int *i) -{ - int x; - int idx = 0; - for (x = 0; x < len; x++) { - unsigned char cur = ascii_string[x]; - sprintf(&buf[idx], "0x%02.2x,", cur); - idx += 5; - if ((++(*i) % HEX_BYTES_PER_LINE) == 0) { - sprintf(&buf[idx], NEWLINE); - idx += NEWLINE_LEN; - } - } - return len; -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/readme.txt b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/readme.txt deleted file mode 100644 index 3768585ef9228d43d059b5d06373cb8d87191776..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/httpd/makefsdata/readme.txt +++ /dev/null @@ -1,13 +0,0 @@ -This directory contains a script ('makefsdata') to create C code suitable for -httpd for given html pages (or other files) in a directory. - -There is also a plain C console application doing the same and extended a bit. - -Usage: htmlgen [targetdir] [-s] [-i]s - targetdir: relative or absolute path to files to convert - switch -s: toggle processing of subdirectories (default is on) - switch -e: exclude HTTP header from file (header is created at runtime, default is on) - switch -11: include HTTP 1.1 header (1.0 is default) - - if targetdir not specified, makefsdata will attempt to - process files in subdirectory 'fs'. diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/lwiperf/lwiperf.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/lwiperf/lwiperf.c deleted file mode 100644 index efabe478e36f45fac03c0ab2e2eba6f05685b66d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/lwiperf/lwiperf.c +++ /dev/null @@ -1,661 +0,0 @@ -/** - * @file - * lwIP iPerf server implementation - */ - -/** - * @defgroup iperf Iperf server - * @ingroup apps - * - * This is a simple performance measuring server to check your bandwith using - * iPerf2 on a PC as client. - * It is currently a minimal implementation providing an IPv4 TCP server only. - * - * @todo: implement UDP mode and IPv6 - */ - -/* - * Copyright (c) 2014 Simon Goldschmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - */ - -#include "lwip/apps/lwiperf.h" - -#include "lwip/tcp.h" -#include "lwip/sys.h" - -#include - -/* Currently, only TCP-over-IPv4 is implemented (does iperf support IPv6 anyway?) */ -#if LWIP_IPV4 && LWIP_TCP && LWIP_CALLBACK_API - -/** Specify the idle timeout (in seconds) after that the test fails */ -#ifndef LWIPERF_TCP_MAX_IDLE_SEC -#define LWIPERF_TCP_MAX_IDLE_SEC 10U -#endif -#if LWIPERF_TCP_MAX_IDLE_SEC > 255 -#error LWIPERF_TCP_MAX_IDLE_SEC must fit into an u8_t -#endif - -/* File internal memory allocation (struct lwiperf_*): this defaults to - the heap */ -#ifndef LWIPERF_ALLOC -#define LWIPERF_ALLOC(type) mem_malloc(sizeof(type)) -#define LWIPERF_FREE(type, item) mem_free(item) -#endif - -/** If this is 1, check that received data has the correct format */ -#ifndef LWIPERF_CHECK_RX_DATA -#define LWIPERF_CHECK_RX_DATA 0 -#endif - -/** This is the Iperf settings struct sent from the client */ -typedef struct _lwiperf_settings { -#define LWIPERF_FLAGS_ANSWER_TEST 0x80000000 -#define LWIPERF_FLAGS_ANSWER_NOW 0x00000001 - u32_t flags; - u32_t num_threads; /* unused for now */ - u32_t remote_port; - u32_t buffer_len; /* unused for now */ - u32_t win_band; /* TCP window / UDP rate: unused for now */ - u32_t amount; /* pos. value: bytes?; neg. values: time (unit is 10ms: 1/100 second) */ -} lwiperf_settings_t; - -/** Basic connection handle */ -struct _lwiperf_state_base; -typedef struct _lwiperf_state_base lwiperf_state_base_t; -struct _lwiperf_state_base { - /* 1=tcp, 0=udp */ - u8_t tcp; - /* 1=server, 0=client */ - u8_t server; - lwiperf_state_base_t* next; - lwiperf_state_base_t* related_server_state; -}; - -/** Connection handle for a TCP iperf session */ -typedef struct _lwiperf_state_tcp { - lwiperf_state_base_t base; - struct tcp_pcb* server_pcb; - struct tcp_pcb* conn_pcb; - u32_t time_started; - lwiperf_report_fn report_fn; - void* report_arg; - u8_t poll_count; - u8_t next_num; - u32_t bytes_transferred; - lwiperf_settings_t settings; - u8_t have_settings_buf; -} lwiperf_state_tcp_t; - -/** List of active iperf sessions */ -static lwiperf_state_base_t* lwiperf_all_connections; -/** A const buffer to send from: we want to measure sending, not copying! */ -static const u8_t lwiperf_txbuf_const[1600] = { - '0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9', - '0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9', - 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'0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9', - '0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9', - '0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9', -}; - -static err_t lwiperf_tcp_poll(void *arg, struct tcp_pcb *tpcb); -static void lwiperf_tcp_err(void *arg, err_t err); - -/** Add an iperf session to the 'active' list */ -static void -lwiperf_list_add(lwiperf_state_base_t* item) -{ - if (lwiperf_all_connections == NULL) { - lwiperf_all_connections = item; - } else { - item = lwiperf_all_connections; - } -} - -/** Remove an iperf session from the 'active' list */ -static void -lwiperf_list_remove(lwiperf_state_base_t* item) -{ - lwiperf_state_base_t* prev = NULL; - lwiperf_state_base_t* iter; - for (iter = lwiperf_all_connections; iter != NULL; prev = iter, iter = iter->next) { - if (iter == item) { - if (prev == NULL) { - lwiperf_all_connections = iter->next; - } else { - prev->next = item; - } - /* @debug: ensure this item is listed only once */ - for (iter = iter->next; iter != NULL; iter = iter->next) { - LWIP_ASSERT("duplicate entry", iter != item); - } - break; - } - } -} - -/** Call the report function of an iperf tcp session */ -static void -lwip_tcp_conn_report(lwiperf_state_tcp_t* conn, enum lwiperf_report_type report_type) -{ - if ((conn != NULL) && (conn->report_fn != NULL)) { - u32_t now, duration_ms, bandwidth_kbitpsec; - now = sys_now(); - duration_ms = now - conn->time_started; - if (duration_ms == 0) { - bandwidth_kbitpsec = 0; - } else { - bandwidth_kbitpsec = (conn->bytes_transferred / duration_ms) * 8U; - } - conn->report_fn(conn->report_arg, report_type, - &conn->conn_pcb->local_ip, conn->conn_pcb->local_port, - &conn->conn_pcb->remote_ip, conn->conn_pcb->remote_port, - conn->bytes_transferred, duration_ms, bandwidth_kbitpsec); - } -} - -/** Close an iperf tcp session */ -static void -lwiperf_tcp_close(lwiperf_state_tcp_t* conn, enum lwiperf_report_type report_type) -{ - err_t err; - - lwip_tcp_conn_report(conn, report_type); - lwiperf_list_remove(&conn->base); - if (conn->conn_pcb != NULL) { - tcp_arg(conn->conn_pcb, NULL); - tcp_poll(conn->conn_pcb, NULL, 0); - tcp_sent(conn->conn_pcb, NULL); - tcp_recv(conn->conn_pcb, NULL); - tcp_err(conn->conn_pcb, NULL); - err = tcp_close(conn->conn_pcb); - if (err != ERR_OK) { - /* don't want to wait for free memory here... */ - tcp_abort(conn->conn_pcb); - } - } else { - /* no conn pcb, this is the server pcb */ - err = tcp_close(conn->server_pcb); - LWIP_ASSERT("error", err != ERR_OK); - } - LWIPERF_FREE(lwiperf_state_tcp_t, conn); -} - -/** Try to send more data on an iperf tcp session */ -static err_t -lwiperf_tcp_client_send_more(lwiperf_state_tcp_t* conn) -{ - int send_more; - err_t err; - u16_t txlen; - u16_t txlen_max; - void* txptr; - u8_t apiflags; - - LWIP_ASSERT("conn invalid", (conn != NULL) && conn->base.tcp && (conn->base.server == 0)); - - do { - send_more = 0; - if (conn->settings.amount & PP_HTONL(0x80000000)) { - /* this session is time-limited */ - u32_t now = sys_now(); - u32_t diff_ms = now - conn->time_started; - u32_t time = (u32_t)-(s32_t)lwip_htonl(conn->settings.amount); - u32_t time_ms = time * 10; - if (diff_ms >= time_ms) { - /* time specified by the client is over -> close the connection */ - lwiperf_tcp_close(conn, LWIPERF_TCP_DONE_CLIENT); - return ERR_OK; - } - } else { - /* this session is byte-limited */ - u32_t amount_bytes = lwip_htonl(conn->settings.amount); - /* @todo: this can send up to 1*MSS more than requested... */ - if (amount_bytes >= conn->bytes_transferred) { - /* all requested bytes transferred -> close the connection */ - lwiperf_tcp_close(conn, LWIPERF_TCP_DONE_CLIENT); - return ERR_OK; - } - } - - if (conn->bytes_transferred < 24) { - /* transmit the settings a first time */ - txptr = &((u8_t*)&conn->settings)[conn->bytes_transferred]; - txlen_max = (u16_t)(24 - conn->bytes_transferred); - apiflags = TCP_WRITE_FLAG_COPY; - } else if (conn->bytes_transferred < 48) { - /* transmit the settings a second time */ - txptr = &((u8_t*)&conn->settings)[conn->bytes_transferred - 24]; - txlen_max = (u16_t)(48 - conn->bytes_transferred); - apiflags = TCP_WRITE_FLAG_COPY | TCP_WRITE_FLAG_MORE; - send_more = 1; - } else { - /* transmit data */ - /* @todo: every x bytes, transmit the settings again */ - txptr = LWIP_CONST_CAST(void*, &lwiperf_txbuf_const[conn->bytes_transferred % 10]); - txlen_max = TCP_MSS; - if (conn->bytes_transferred == 48) { /* @todo: fix this for intermediate settings, too */ - txlen_max = TCP_MSS - 24; - } - apiflags = 0; /* no copying needed */ - send_more = 1; - } - txlen = txlen_max; - do { - err = tcp_write(conn->conn_pcb, txptr, txlen, apiflags); - if (err == ERR_MEM) { - txlen /= 2; - } - } while ((err == ERR_MEM) && (txlen >= (TCP_MSS/2))); - - if (err == ERR_OK) { - conn->bytes_transferred += txlen; - } else { - send_more = 0; - } - } while(send_more); - - tcp_output(conn->conn_pcb); - return ERR_OK; -} - -/** TCP sent callback, try to send more data */ -static err_t -lwiperf_tcp_client_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) -{ - lwiperf_state_tcp_t* conn = (lwiperf_state_tcp_t*)arg; - /* @todo: check 'len' (e.g. to time ACK of all data)? for now, we just send more... */ - LWIP_ASSERT("invalid conn", conn->conn_pcb == tpcb); - LWIP_UNUSED_ARG(tpcb); - LWIP_UNUSED_ARG(len); - - conn->poll_count = 0; - - return lwiperf_tcp_client_send_more(conn); -} - -/** TCP connected callback (active connection), send data now */ -static err_t -lwiperf_tcp_client_connected(void *arg, struct tcp_pcb *tpcb, err_t err) -{ - lwiperf_state_tcp_t* conn = (lwiperf_state_tcp_t*)arg; - LWIP_ASSERT("invalid conn", conn->conn_pcb == tpcb); - LWIP_UNUSED_ARG(tpcb); - if (err != ERR_OK) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_REMOTE); - return ERR_OK; - } - conn->poll_count = 0; - conn->time_started = sys_now(); - return lwiperf_tcp_client_send_more(conn); -} - -/** Start TCP connection back to the client (either parallel or after the - * receive test has finished. - */ -static err_t -lwiperf_tx_start(lwiperf_state_tcp_t* conn) -{ - err_t err; - lwiperf_state_tcp_t* client_conn; - struct tcp_pcb* newpcb; - ip_addr_t remote_addr; - u16_t remote_port; - - client_conn = (lwiperf_state_tcp_t*)LWIPERF_ALLOC(lwiperf_state_tcp_t); - if (client_conn == NULL) { - return ERR_MEM; - } - newpcb = tcp_new(); - if (newpcb == NULL) { - LWIPERF_FREE(lwiperf_state_tcp_t, client_conn); - return ERR_MEM; - } - - MEMCPY(client_conn, conn, sizeof(lwiperf_state_tcp_t)); - client_conn->base.server = 0; - client_conn->server_pcb = NULL; - client_conn->conn_pcb = newpcb; - client_conn->time_started = sys_now(); /* @todo: set this again on 'connected' */ - client_conn->poll_count = 0; - client_conn->next_num = 4; /* initial nr is '4' since the header has 24 byte */ - client_conn->bytes_transferred = 0; - client_conn->settings.flags = 0; /* prevent the remote side starting back as client again */ - - tcp_arg(newpcb, client_conn); - tcp_sent(newpcb, lwiperf_tcp_client_sent); - tcp_poll(newpcb, lwiperf_tcp_poll, 2U); - tcp_err(newpcb, lwiperf_tcp_err); - - ip_addr_copy(remote_addr, conn->conn_pcb->remote_ip); - remote_port = (u16_t)lwip_htonl(client_conn->settings.remote_port); - - err = tcp_connect(newpcb, &remote_addr, remote_port, lwiperf_tcp_client_connected); - if (err != ERR_OK) { - lwiperf_tcp_close(client_conn, LWIPERF_TCP_ABORTED_LOCAL); - return err; - } - lwiperf_list_add(&client_conn->base); - return ERR_OK; -} - -/** Receive data on an iperf tcp session */ -static err_t -lwiperf_tcp_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) -{ - u8_t tmp; - u16_t tot_len; - u32_t packet_idx; - struct pbuf* q; - lwiperf_state_tcp_t* conn = (lwiperf_state_tcp_t*)arg; - - LWIP_ASSERT("pcb mismatch", conn->conn_pcb == tpcb); - LWIP_UNUSED_ARG(tpcb); - - if (err != ERR_OK) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_REMOTE); - return ERR_OK; - } - if (p == NULL) { - /* connection closed -> test done */ - if ((conn->settings.flags & PP_HTONL(LWIPERF_FLAGS_ANSWER_TEST|LWIPERF_FLAGS_ANSWER_NOW)) == - PP_HTONL(LWIPERF_FLAGS_ANSWER_TEST)) { - /* client requested transmission after end of test */ - lwiperf_tx_start(conn); - } - lwiperf_tcp_close(conn, LWIPERF_TCP_DONE_SERVER); - return ERR_OK; - } - tot_len = p->tot_len; - - conn->poll_count = 0; - - if ((!conn->have_settings_buf) || ((conn->bytes_transferred -24) % (1024*128) == 0)) { - /* wait for 24-byte header */ - if (p->tot_len < sizeof(lwiperf_settings_t)) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL_DATAERROR); - pbuf_free(p); - return ERR_VAL; - } - if (!conn->have_settings_buf) { - if (pbuf_copy_partial(p, &conn->settings, sizeof(lwiperf_settings_t), 0) != sizeof(lwiperf_settings_t)) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL); - pbuf_free(p); - return ERR_VAL; - } - conn->have_settings_buf = 1; - if ((conn->settings.flags & PP_HTONL(LWIPERF_FLAGS_ANSWER_TEST|LWIPERF_FLAGS_ANSWER_NOW)) == - PP_HTONL(LWIPERF_FLAGS_ANSWER_TEST|LWIPERF_FLAGS_ANSWER_NOW)) { - /* client requested parallel transmission test */ - err_t err2 = lwiperf_tx_start(conn); - if (err2 != ERR_OK) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL_TXERROR); - pbuf_free(p); - return err2; - } - } - } else { - if (pbuf_memcmp(p, 0, &conn->settings, sizeof(lwiperf_settings_t)) != 0) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL_DATAERROR); - pbuf_free(p); - return ERR_VAL; - } - } - conn->bytes_transferred += sizeof(lwiperf_settings_t); - if (conn->bytes_transferred <= 24) { - conn->time_started = sys_now(); - tcp_recved(tpcb, p->tot_len); - pbuf_free(p); - return ERR_OK; - } - conn->next_num = 4; /* 24 bytes received... */ - tmp = pbuf_header(p, -24); - LWIP_ASSERT("pbuf_header failed", tmp == 0); - } - - packet_idx = 0; - for (q = p; q != NULL; q = q->next) { -#if LWIPERF_CHECK_RX_DATA - const u8_t* payload = (const u8_t*)q->payload; - u16_t i; - for (i = 0; i < q->len; i++) { - u8_t val = payload[i]; - u8_t num = val - '0'; - if (num == conn->next_num) { - conn->next_num++; - if (conn->next_num == 10) { - conn->next_num = 0; - } - } else { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL_DATAERROR); - pbuf_free(p); - return ERR_VAL; - } - } -#endif - packet_idx += q->len; - } - LWIP_ASSERT("count mismatch", packet_idx == p->tot_len); - conn->bytes_transferred += packet_idx; - tcp_recved(tpcb, tot_len); - pbuf_free(p); - return ERR_OK; -} - -/** Error callback, iperf tcp session aborted */ -static void -lwiperf_tcp_err(void *arg, err_t err) -{ - lwiperf_state_tcp_t* conn = (lwiperf_state_tcp_t*)arg; - LWIP_UNUSED_ARG(err); - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_REMOTE); -} - -/** TCP poll callback, try to send more data */ -static err_t -lwiperf_tcp_poll(void *arg, struct tcp_pcb *tpcb) -{ - lwiperf_state_tcp_t* conn = (lwiperf_state_tcp_t*)arg; - LWIP_ASSERT("pcb mismatch", conn->conn_pcb == tpcb); - LWIP_UNUSED_ARG(tpcb); - if (++conn->poll_count >= LWIPERF_TCP_MAX_IDLE_SEC) { - lwiperf_tcp_close(conn, LWIPERF_TCP_ABORTED_LOCAL); - return ERR_OK; /* lwiperf_tcp_close frees conn */ - } - - if (!conn->base.server) { - lwiperf_tcp_client_send_more(conn); - } - - return ERR_OK; -} - -/** This is called when a new client connects for an iperf tcp session */ -static err_t -lwiperf_tcp_accept(void *arg, struct tcp_pcb *newpcb, err_t err) -{ - lwiperf_state_tcp_t *s, *conn; - if ((err != ERR_OK) || (newpcb == NULL) || (arg == NULL)) { - return ERR_VAL; - } - - s = (lwiperf_state_tcp_t*)arg; - conn = (lwiperf_state_tcp_t*)LWIPERF_ALLOC(lwiperf_state_tcp_t); - if (conn == NULL) { - return ERR_MEM; - } - memset(conn, 0, sizeof(lwiperf_state_tcp_t)); - conn->base.tcp = 1; - conn->base.server = 1; - conn->base.related_server_state = &s->base; - conn->server_pcb = s->server_pcb; - conn->conn_pcb = newpcb; - conn->time_started = sys_now(); - conn->report_fn = s->report_fn; - conn->report_arg = s->report_arg; - - /* setup the tcp rx connection */ - tcp_arg(newpcb, conn); - tcp_recv(newpcb, lwiperf_tcp_recv); - tcp_poll(newpcb, lwiperf_tcp_poll, 2U); - tcp_err(conn->conn_pcb, lwiperf_tcp_err); - - lwiperf_list_add(&conn->base); - return ERR_OK; -} - -/** - * @ingroup iperf - * Start a TCP iperf server on the default TCP port (5001) and listen for - * incoming connections from iperf clients. - * - * @returns a connection handle that can be used to abort the server - * by calling @ref lwiperf_abort() - */ -void* -lwiperf_start_tcp_server_default(lwiperf_report_fn report_fn, void* report_arg) -{ - return lwiperf_start_tcp_server(IP_ADDR_ANY, LWIPERF_TCP_PORT_DEFAULT, - report_fn, report_arg); -} - -/** - * @ingroup iperf - * Start a TCP iperf server on a specific IP address and port and listen for - * incoming connections from iperf clients. - * - * @returns a connection handle that can be used to abort the server - * by calling @ref lwiperf_abort() - */ -void* -lwiperf_start_tcp_server(const ip_addr_t* local_addr, u16_t local_port, - lwiperf_report_fn report_fn, void* report_arg) -{ - err_t err; - struct tcp_pcb* pcb; - lwiperf_state_tcp_t* s; - - if (local_addr == NULL) { - return NULL; - } - - s = (lwiperf_state_tcp_t*)LWIPERF_ALLOC(lwiperf_state_tcp_t); - if (s == NULL) { - return NULL; - } - memset(s, 0, sizeof(lwiperf_state_tcp_t)); - s->base.tcp = 1; - s->base.server = 1; - s->report_fn = report_fn; - s->report_arg = report_arg; - - pcb = tcp_new(); - if (pcb != NULL) { - err = tcp_bind(pcb, local_addr, local_port); - if (err == ERR_OK) { - s->server_pcb = tcp_listen_with_backlog(pcb, 1); - } - } - if (s->server_pcb == NULL) { - if (pcb != NULL) { - tcp_close(pcb); - } - LWIPERF_FREE(lwiperf_state_tcp_t, s); - return NULL; - } - pcb = NULL; - - tcp_arg(s->server_pcb, s); - tcp_accept(s->server_pcb, lwiperf_tcp_accept); - - lwiperf_list_add(&s->base); - return s; -} - -/** - * @ingroup iperf - * Abort an iperf session (handle returned by lwiperf_start_tcp_server*()) - */ -void -lwiperf_abort(void* lwiperf_session) -{ - lwiperf_state_base_t* i, *dealloc, *last = NULL; - - for (i = lwiperf_all_connections; i != NULL; ) { - if ((i == lwiperf_session) || (i->related_server_state == lwiperf_session)) { - dealloc = i; - i = i->next; - if (last != NULL) { - last->next = i; - } - LWIPERF_FREE(lwiperf_state_tcp_t, dealloc); /* @todo: type? */ - } else { - last = i; - i = i->next; - } - } -} - -#endif /* LWIP_IPV4 && LWIP_TCP && LWIP_CALLBACK_API */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mdns/mdns.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mdns/mdns.c deleted file mode 100644 index 14334fc856b8f59fbc3da0c36521a69f6f84d990..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mdns/mdns.c +++ /dev/null @@ -1,2028 +0,0 @@ -/** - * @file - * MDNS responder implementation - * - * @defgroup mdns MDNS - * @ingroup apps - * - * RFC 6762 - Multicast DNS\n - * RFC 6763 - DNS-Based Service Discovery\n - * - * @verbinclude mdns.txt - * - * Things left to implement: - * ------------------------- - * - * - Probing/conflict resolution - * - Sending goodbye messages (zero ttl) - shutdown, DHCP lease about to expire, DHCP turned off... - * - Checking that source address of unicast requests are on the same network - * - Limiting multicast responses to 1 per second per resource record - * - Fragmenting replies if required - * - Subscribe to netif address/link change events and act on them (currently needs to be done manually) - * - Handling multi-packet known answers - * - Individual known answer detection for all local IPv6 addresses - * - Dynamic size of outgoing packet - */ - -/* - * Copyright (c) 2015 Verisure Innovation AB - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ - -#include "lwip/apps/mdns.h" -#include "lwip/apps/mdns_priv.h" -#include "lwip/netif.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/mem.h" -#include "lwip/prot/dns.h" - -#include - -#if LWIP_MDNS_RESPONDER - -#if (LWIP_IPV4 && !LWIP_IGMP) - #error "If you want to use MDNS with IPv4, you have to define LWIP_IGMP=1 in your lwipopts.h" -#endif -#if (LWIP_IPV6 && !LWIP_IPV6_MLD) -#error "If you want to use MDNS with IPv6, you have to define LWIP_IPV6_MLD=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP) - #error "If you want to use MDNS, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif - -#if LWIP_IPV4 -#include "lwip/igmp.h" -/* IPv4 multicast group 224.0.0.251 */ -static const ip_addr_t v4group = DNS_MQUERY_IPV4_GROUP_INIT; -#endif - -#if LWIP_IPV6 -#include "lwip/mld6.h" -/* IPv6 multicast group FF02::FB */ -static const ip_addr_t v6group = DNS_MQUERY_IPV6_GROUP_INIT; -#endif - -#define MDNS_PORT 5353 -#define MDNS_TTL 255 - -/* Stored offsets to beginning of domain names - * Used for compression. - */ -#define NUM_DOMAIN_OFFSETS 10 -#define DOMAIN_JUMP_SIZE 2 -#define DOMAIN_JUMP 0xc000 - -static u8_t mdns_netif_client_id; -static struct udp_pcb *mdns_pcb; - -#define NETIF_TO_HOST(netif) (struct mdns_host*)(netif_get_client_data(netif, mdns_netif_client_id)) - -#define TOPDOMAIN_LOCAL "local" - -#define REVERSE_PTR_TOPDOMAIN "arpa" -#define REVERSE_PTR_V4_DOMAIN "in-addr" -#define REVERSE_PTR_V6_DOMAIN "ip6" - -#define SRV_PRIORITY 0 -#define SRV_WEIGHT 0 - -/* Payload size allocated for each outgoing UDP packet */ -#define OUTPACKET_SIZE 500 - -/* Lookup from hostname -> IPv4 */ -#define REPLY_HOST_A 0x01 -/* Lookup from IPv4/v6 -> hostname */ -#define REPLY_HOST_PTR_V4 0x02 -/* Lookup from hostname -> IPv6 */ -#define REPLY_HOST_AAAA 0x04 -/* Lookup from hostname -> IPv6 */ -#define REPLY_HOST_PTR_V6 0x08 - -/* Lookup for service types */ -#define REPLY_SERVICE_TYPE_PTR 0x10 -/* Lookup for instances of service */ -#define REPLY_SERVICE_NAME_PTR 0x20 -/* Lookup for location of service instance */ -#define REPLY_SERVICE_SRV 0x40 -/* Lookup for text info on service instance */ -#define REPLY_SERVICE_TXT 0x80 - -static const char *dnssd_protos[] = { - "_udp", /* DNSSD_PROTO_UDP */ - "_tcp", /* DNSSD_PROTO_TCP */ -}; - -/** Description of a service */ -struct mdns_service { - /** TXT record to answer with */ - struct mdns_domain txtdata; - /** Name of service, like 'myweb' */ - char name[MDNS_LABEL_MAXLEN + 1]; - /** Type of service, like '_http' */ - char service[MDNS_LABEL_MAXLEN + 1]; - /** Callback function and userdata - * to update txtdata buffer */ - service_get_txt_fn_t txt_fn; - void *txt_userdata; - /** TTL in seconds of SRV/TXT replies */ - u32_t dns_ttl; - /** Protocol, TCP or UDP */ - u16_t proto; - /** Port of the service */ - u16_t port; -}; - -/** Description of a host/netif */ -struct mdns_host { - /** Hostname */ - char name[MDNS_LABEL_MAXLEN + 1]; - /** Pointer to services */ - struct mdns_service *services[MDNS_MAX_SERVICES]; - /** TTL in seconds of A/AAAA/PTR replies */ - u32_t dns_ttl; -}; - -/** Information about received packet */ -struct mdns_packet { - /** Sender IP/port */ - ip_addr_t source_addr; - u16_t source_port; - /** If packet was received unicast */ - u16_t recv_unicast; - /** Netif that received the packet */ - struct netif *netif; - /** Packet data */ - struct pbuf *pbuf; - /** Current parsing offset in packet */ - u16_t parse_offset; - /** Identifier. Used in legacy queries */ - u16_t tx_id; - /** Number of questions in packet, - * read from packet header */ - u16_t questions; - /** Number of unparsed questions */ - u16_t questions_left; - /** Number of answers in packet, - * (sum of normal, authorative and additional answers) - * read from packet header */ - u16_t answers; - /** Number of unparsed answers */ - u16_t answers_left; -}; - -/** Information about outgoing packet */ -struct mdns_outpacket { - /** Netif to send the packet on */ - struct netif *netif; - /** Packet data */ - struct pbuf *pbuf; - /** Current write offset in packet */ - u16_t write_offset; - /** Identifier. Used in legacy queries */ - u16_t tx_id; - /** Destination IP/port if sent unicast */ - ip_addr_t dest_addr; - u16_t dest_port; - /** Number of questions written */ - u16_t questions; - /** Number of normal answers written */ - u16_t answers; - /** Number of additional answers written */ - u16_t additional; - /** Offsets for written domain names in packet. - * Used for compression */ - u16_t domain_offsets[NUM_DOMAIN_OFFSETS]; - /** If all answers in packet should set cache_flush bit */ - u8_t cache_flush; - /** If reply should be sent unicast */ - u8_t unicast_reply; - /** If legacy query. (tx_id needed, and write - * question again in reply before answer) */ - u8_t legacy_query; - /* Reply bitmask for host information */ - u8_t host_replies; - /* Bitmask for which reverse IPv6 hosts to answer */ - u8_t host_reverse_v6_replies; - /* Reply bitmask per service */ - u8_t serv_replies[MDNS_MAX_SERVICES]; -}; - -/** Domain, type and class. - * Shared between questions and answers */ -struct mdns_rr_info { - struct mdns_domain domain; - u16_t type; - u16_t klass; -}; - -struct mdns_question { - struct mdns_rr_info info; - /** unicast reply requested */ - u16_t unicast; -}; - -struct mdns_answer { - struct mdns_rr_info info; - /** cache flush command bit */ - u16_t cache_flush; - /* Validity time in seconds */ - u32_t ttl; - /** Length of variable answer */ - u16_t rd_length; - /** Offset of start of variable answer in packet */ - u16_t rd_offset; -}; - -/** - * Add a label part to a domain - * @param domain The domain to add a label to - * @param label The label to add, like <hostname>, 'local', 'com' or '' - * @param len The length of the label - * @return ERR_OK on success, an err_t otherwise if label too long - */ -err_t -mdns_domain_add_label(struct mdns_domain *domain, const char *label, u8_t len) -{ - if (len > MDNS_LABEL_MAXLEN) { - return ERR_VAL; - } - if (len > 0 && (1 + len + domain->length >= MDNS_DOMAIN_MAXLEN)) { - return ERR_VAL; - } - /* Allow only zero marker on last byte */ - if (len == 0 && (1 + domain->length > MDNS_DOMAIN_MAXLEN)) { - return ERR_VAL; - } - domain->name[domain->length] = len; - domain->length++; - if (len) { - MEMCPY(&domain->name[domain->length], label, len); - domain->length += len; - } - return ERR_OK; -} - -/** - * Internal readname function with max 6 levels of recursion following jumps - * while decompressing name - */ -static u16_t -mdns_readname_loop(struct pbuf *p, u16_t offset, struct mdns_domain *domain, unsigned depth) -{ - u8_t c; - - do { - if (depth > 5) { - /* Too many jumps */ - return MDNS_READNAME_ERROR; - } - - c = pbuf_get_at(p, offset); - offset++; - - /* is this a compressed label? */ - if((c & 0xc0) == 0xc0) { - u16_t jumpaddr; - if (offset >= p->tot_len) { - /* Make sure both jump bytes fit in the packet */ - return MDNS_READNAME_ERROR; - } - jumpaddr = (((c & 0x3f) << 8) | (pbuf_get_at(p, offset) & 0xff)); - offset++; - if (jumpaddr >= SIZEOF_DNS_HDR && jumpaddr < p->tot_len) { - u16_t res; - /* Recursive call, maximum depth will be checked */ - res = mdns_readname_loop(p, jumpaddr, domain, depth + 1); - /* Dont return offset since new bytes were not read (jumped to somewhere in packet) */ - if (res == MDNS_READNAME_ERROR) { - return res; - } - } else { - return MDNS_READNAME_ERROR; - } - break; - } - - /* normal label */ - if (c <= MDNS_LABEL_MAXLEN) { - u8_t label[MDNS_LABEL_MAXLEN]; - err_t res; - - if (c + domain->length >= MDNS_DOMAIN_MAXLEN) { - return MDNS_READNAME_ERROR; - } - if (c != 0) { - if (pbuf_copy_partial(p, label, c, offset) != c) { - return MDNS_READNAME_ERROR; - } - offset += c; - } - res = mdns_domain_add_label(domain, (char *) label, c); - if (res != ERR_OK) { - return MDNS_READNAME_ERROR; - } - } else { - /* bad length byte */ - return MDNS_READNAME_ERROR; - } - } while (c != 0); - - return offset; -} - -/** - * Read possibly compressed domain name from packet buffer - * @param p The packet - * @param offset start position of domain name in packet - * @param domain The domain name destination - * @return The new offset after the domain, or MDNS_READNAME_ERROR - * if reading failed - */ -u16_t -mdns_readname(struct pbuf *p, u16_t offset, struct mdns_domain *domain) -{ - memset(domain, 0, sizeof(struct mdns_domain)); - return mdns_readname_loop(p, offset, domain, 0); -} - -/** - * Print domain name to debug output - * @param domain The domain name - */ -static void -mdns_domain_debug_print(struct mdns_domain *domain) -{ - u8_t *src = domain->name; - u8_t i; - - while (*src) { - u8_t label_len = *src; - src++; - for (i = 0; i < label_len; i++) { - LWIP_DEBUGF(MDNS_DEBUG, ("%c", src[i])); - } - src += label_len; - LWIP_DEBUGF(MDNS_DEBUG, (".")); - } -} - -/** - * Return 1 if contents of domains match (case-insensitive) - * @param a Domain name to compare 1 - * @param b Domain name to compare 2 - * @return 1 if domains are equal ignoring case, 0 otherwise - */ -int -mdns_domain_eq(struct mdns_domain *a, struct mdns_domain *b) -{ - u8_t *ptra, *ptrb; - u8_t len; - int res; - - if (a->length != b->length) { - return 0; - } - - ptra = a->name; - ptrb = b->name; - while (*ptra && *ptrb && ptra < &a->name[a->length]) { - if (*ptra != *ptrb) { - return 0; - } - len = *ptra; - ptra++; - ptrb++; - res = lwip_strnicmp((char *) ptra, (char *) ptrb, len); - if (res != 0) { - return 0; - } - ptra += len; - ptrb += len; - } - if (*ptra != *ptrb && ptra < &a->name[a->length]) { - return 0; - } - return 1; -} - -/** - * Call user supplied function to setup TXT data - * @param service The service to build TXT record for - */ -static void -mdns_prepare_txtdata(struct mdns_service *service) -{ - memset(&service->txtdata, 0, sizeof(struct mdns_domain)); - if (service->txt_fn) { - service->txt_fn(service, service->txt_userdata); - } -} - -#if LWIP_IPV4 -/** - * Build domain for reverse lookup of IPv4 address - * like 12.0.168.192.in-addr.arpa. for 192.168.0.12 - * @param domain Where to write the domain name - * @param addr Pointer to an IPv4 address to encode - * @return ERR_OK if domain was written, an err_t otherwise - */ -static err_t -mdns_build_reverse_v4_domain(struct mdns_domain *domain, const ip4_addr_t *addr) -{ - int i; - err_t res; - const u8_t *ptr; - if (!domain || !addr) { - return ERR_ARG; - } - memset(domain, 0, sizeof(struct mdns_domain)); - ptr = (const u8_t *) addr; - for (i = sizeof(ip4_addr_t) - 1; i >= 0; i--) { - char buf[4]; - u8_t val = ptr[i]; - - lwip_itoa(buf, sizeof(buf), val); - res = mdns_domain_add_label(domain, buf, (u8_t)strlen(buf)); - LWIP_ERROR("mdns_build_reverse_v4_domain: Failed to add label", (res == ERR_OK), return res); - } - res = mdns_domain_add_label(domain, REVERSE_PTR_V4_DOMAIN, (u8_t)(sizeof(REVERSE_PTR_V4_DOMAIN)-1)); - LWIP_ERROR("mdns_build_reverse_v4_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, REVERSE_PTR_TOPDOMAIN, (u8_t)(sizeof(REVERSE_PTR_TOPDOMAIN)-1)); - LWIP_ERROR("mdns_build_reverse_v4_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, NULL, 0); - LWIP_ERROR("mdns_build_reverse_v4_domain: Failed to add label", (res == ERR_OK), return res); - - return ERR_OK; -} -#endif - -#if LWIP_IPV6 -/** - * Build domain for reverse lookup of IP address - * like b.a.9.8.7.6.5.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.8.b.d.0.1.0.0.2.ip6.arpa. for 2001:db8::567:89ab - * @param domain Where to write the domain name - * @param addr Pointer to an IPv6 address to encode - * @return ERR_OK if domain was written, an err_t otherwise - */ -static err_t -mdns_build_reverse_v6_domain(struct mdns_domain *domain, const ip6_addr_t *addr) -{ - int i; - err_t res; - const u8_t *ptr; - if (!domain || !addr) { - return ERR_ARG; - } - memset(domain, 0, sizeof(struct mdns_domain)); - ptr = (const u8_t *) addr; - for (i = sizeof(ip6_addr_t) - 1; i >= 0; i--) { - char buf; - u8_t byte = ptr[i]; - int j; - for (j = 0; j < 2; j++) { - if ((byte & 0x0F) < 0xA) { - buf = '0' + (byte & 0x0F); - } else { - buf = 'a' + (byte & 0x0F) - 0xA; - } - res = mdns_domain_add_label(domain, &buf, sizeof(buf)); - LWIP_ERROR("mdns_build_reverse_v6_domain: Failed to add label", (res == ERR_OK), return res); - byte >>= 4; - } - } - res = mdns_domain_add_label(domain, REVERSE_PTR_V6_DOMAIN, (u8_t)(sizeof(REVERSE_PTR_V6_DOMAIN)-1)); - LWIP_ERROR("mdns_build_reverse_v6_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, REVERSE_PTR_TOPDOMAIN, (u8_t)(sizeof(REVERSE_PTR_TOPDOMAIN)-1)); - LWIP_ERROR("mdns_build_reverse_v6_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, NULL, 0); - LWIP_ERROR("mdns_build_reverse_v6_domain: Failed to add label", (res == ERR_OK), return res); - - return ERR_OK; -} -#endif - -/* Add .local. to domain */ -static err_t -mdns_add_dotlocal(struct mdns_domain *domain) -{ - err_t res = mdns_domain_add_label(domain, TOPDOMAIN_LOCAL, (u8_t)(sizeof(TOPDOMAIN_LOCAL)-1)); - LWIP_ERROR("mdns_add_dotlocal: Failed to add label", (res == ERR_OK), return res); - return mdns_domain_add_label(domain, NULL, 0); -} - -/** - * Build the .local. domain name - * @param domain Where to write the domain name - * @param mdns TMDNS netif descriptor. - * @return ERR_OK if domain .local. was written, an err_t otherwise - */ -static err_t -mdns_build_host_domain(struct mdns_domain *domain, struct mdns_host *mdns) -{ - err_t res; - memset(domain, 0, sizeof(struct mdns_domain)); - LWIP_ERROR("mdns_build_host_domain: mdns != NULL", (mdns != NULL), return ERR_VAL); - res = mdns_domain_add_label(domain, mdns->name, (u8_t)strlen(mdns->name)); - LWIP_ERROR("mdns_build_host_domain: Failed to add label", (res == ERR_OK), return res); - return mdns_add_dotlocal(domain); -} - -/** - * Build the lookup-all-services special DNS-SD domain name - * @param domain Where to write the domain name - * @return ERR_OK if domain _services._dns-sd._udp.local. was written, an err_t otherwise - */ -static err_t -mdns_build_dnssd_domain(struct mdns_domain *domain) -{ - err_t res; - memset(domain, 0, sizeof(struct mdns_domain)); - res = mdns_domain_add_label(domain, "_services", (u8_t)(sizeof("_services")-1)); - LWIP_ERROR("mdns_build_dnssd_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, "_dns-sd", (u8_t)(sizeof("_dns-sd")-1)); - LWIP_ERROR("mdns_build_dnssd_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, dnssd_protos[DNSSD_PROTO_UDP], (u8_t)strlen(dnssd_protos[DNSSD_PROTO_UDP])); - LWIP_ERROR("mdns_build_dnssd_domain: Failed to add label", (res == ERR_OK), return res); - return mdns_add_dotlocal(domain); -} - -/** - * Build domain name for a service - * @param domain Where to write the domain name - * @param service The service struct, containing service name, type and protocol - * @param include_name Whether to include the service name in the domain - * @return ERR_OK if domain was written. If service name is included, - * ...local. will be written, otherwise ..local. - * An err_t is returned on error. - */ -static err_t -mdns_build_service_domain(struct mdns_domain *domain, struct mdns_service *service, int include_name) -{ - err_t res; - memset(domain, 0, sizeof(struct mdns_domain)); - if (include_name) { - res = mdns_domain_add_label(domain, service->name, (u8_t)strlen(service->name)); - LWIP_ERROR("mdns_build_service_domain: Failed to add label", (res == ERR_OK), return res); - } - res = mdns_domain_add_label(domain, service->service, (u8_t)strlen(service->service)); - LWIP_ERROR("mdns_build_service_domain: Failed to add label", (res == ERR_OK), return res); - res = mdns_domain_add_label(domain, dnssd_protos[service->proto], (u8_t)strlen(dnssd_protos[service->proto])); - LWIP_ERROR("mdns_build_service_domain: Failed to add label", (res == ERR_OK), return res); - return mdns_add_dotlocal(domain); -} - -/** - * Check which replies we should send for a host/netif based on question - * @param netif The network interface that received the question - * @param rr Domain/type/class from a question - * @param reverse_v6_reply Bitmask of which IPv6 addresses to send reverse PTRs for - * if reply bit has REPLY_HOST_PTR_V6 set - * @return Bitmask of which replies to send - */ -static int -check_host(struct netif *netif, struct mdns_rr_info *rr, u8_t *reverse_v6_reply) -{ - err_t res; - int replies = 0; - struct mdns_domain mydomain; - - LWIP_UNUSED_ARG(reverse_v6_reply); /* if ipv6 is disabled */ - - if (rr->klass != DNS_RRCLASS_IN && rr->klass != DNS_RRCLASS_ANY) { - /* Invalid class */ - return replies; - } - - /* Handle PTR for our addresses */ - if (rr->type == DNS_RRTYPE_PTR || rr->type == DNS_RRTYPE_ANY) { -#if LWIP_IPV6 - int i; - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) { - res = mdns_build_reverse_v6_domain(&mydomain, netif_ip6_addr(netif, i)); - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain)) { - replies |= REPLY_HOST_PTR_V6; - /* Mark which addresses where requested */ - if (reverse_v6_reply) { - *reverse_v6_reply |= (1 << i); - } - } - } - } -#endif -#if LWIP_IPV4 - if (!ip4_addr_isany_val(*netif_ip4_addr(netif))) { - res = mdns_build_reverse_v4_domain(&mydomain, netif_ip4_addr(netif)); - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain)) { - replies |= REPLY_HOST_PTR_V4; - } - } -#endif - } - - res = mdns_build_host_domain(&mydomain, NETIF_TO_HOST(netif)); - /* Handle requests for our hostname */ - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain)) { - /* TODO return NSEC if unsupported protocol requested */ -#if LWIP_IPV4 - if (!ip4_addr_isany_val(*netif_ip4_addr(netif)) - && (rr->type == DNS_RRTYPE_A || rr->type == DNS_RRTYPE_ANY)) { - replies |= REPLY_HOST_A; - } -#endif -#if LWIP_IPV6 - if (rr->type == DNS_RRTYPE_AAAA || rr->type == DNS_RRTYPE_ANY) { - replies |= REPLY_HOST_AAAA; - } -#endif - } - - return replies; -} - -/** - * Check which replies we should send for a service based on question - * @param service A registered MDNS service - * @param rr Domain/type/class from a question - * @return Bitmask of which replies to send - */ -static int -check_service(struct mdns_service *service, struct mdns_rr_info *rr) -{ - err_t res; - int replies = 0; - struct mdns_domain mydomain; - - if (rr->klass != DNS_RRCLASS_IN && rr->klass != DNS_RRCLASS_ANY) { - /* Invalid class */ - return 0; - } - - res = mdns_build_dnssd_domain(&mydomain); - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain) && - (rr->type == DNS_RRTYPE_PTR || rr->type == DNS_RRTYPE_ANY)) { - /* Request for all service types */ - replies |= REPLY_SERVICE_TYPE_PTR; - } - - res = mdns_build_service_domain(&mydomain, service, 0); - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain) && - (rr->type == DNS_RRTYPE_PTR || rr->type == DNS_RRTYPE_ANY)) { - /* Request for the instance of my service */ - replies |= REPLY_SERVICE_NAME_PTR; - } - - res = mdns_build_service_domain(&mydomain, service, 1); - if (res == ERR_OK && mdns_domain_eq(&rr->domain, &mydomain)) { - /* Request for info about my service */ - if (rr->type == DNS_RRTYPE_SRV || rr->type == DNS_RRTYPE_ANY) { - replies |= REPLY_SERVICE_SRV; - } - if (rr->type == DNS_RRTYPE_TXT || rr->type == DNS_RRTYPE_ANY) { - replies |= REPLY_SERVICE_TXT; - } - } - - return replies; -} - -/** - * Return bytes needed to write before jump for best result of compressing supplied domain - * against domain in outpacket starting at specified offset. - * If a match is found, offset is updated to where to jump to - * @param pbuf Pointer to pbuf with the partially constructed DNS packet - * @param offset Start position of a domain written earlier. If this location is suitable - * for compression, the pointer is updated to where in the domain to jump to. - * @param domain The domain to write - * @return Number of bytes to write of the new domain before writing a jump to the offset. - * If compression can not be done against this previous domain name, the full new - * domain length is returned. - */ -u16_t -mdns_compress_domain(struct pbuf *pbuf, u16_t *offset, struct mdns_domain *domain) -{ - struct mdns_domain target; - u16_t target_end; - u8_t target_len; - u8_t writelen = 0; - u8_t *ptr; - if (pbuf == NULL) { - return domain->length; - } - target_end = mdns_readname(pbuf, *offset, &target); - if (target_end == MDNS_READNAME_ERROR) { - return domain->length; - } - target_len = (u8_t)(target_end - *offset); - ptr = domain->name; - while (writelen < domain->length) { - u8_t domainlen = (u8_t)(domain->length - writelen); - u8_t labellen; - if (domainlen <= target.length && domainlen > DOMAIN_JUMP_SIZE) { - /* Compare domains if target is long enough, and we have enough left of the domain */ - u8_t targetpos = (u8_t)(target.length - domainlen); - if ((targetpos + DOMAIN_JUMP_SIZE) >= target_len) { - /* We are checking at or beyond a jump in the original, stop looking */ - break; - } - if (target.length >= domainlen && - memcmp(&domain->name[writelen], &target.name[targetpos], domainlen) == 0) { - *offset += targetpos; - return writelen; - } - } - /* Skip to next label in domain */ - labellen = *ptr; - writelen += 1 + labellen; - ptr += 1 + labellen; - } - /* Nothing found */ - return domain->length; -} - -/** - * Write domain to outpacket. Compression will be attempted, - * unless domain->skip_compression is set. - * @param outpkt The outpacket to write to - * @param domain The domain name to write - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_write_domain(struct mdns_outpacket *outpkt, struct mdns_domain *domain) -{ - int i; - err_t res; - u16_t writelen = domain->length; - u16_t jump_offset = 0; - u16_t jump; - - if (!domain->skip_compression) { - for (i = 0; i < NUM_DOMAIN_OFFSETS; ++i) { - u16_t offset = outpkt->domain_offsets[i]; - if (offset) { - u16_t len = mdns_compress_domain(outpkt->pbuf, &offset, domain); - if (len < writelen) { - writelen = len; - jump_offset = offset; - } - } - } - } - - if (writelen) { - /* Write uncompressed part of name */ - res = pbuf_take_at(outpkt->pbuf, domain->name, writelen, outpkt->write_offset); - if (res != ERR_OK) { - return res; - } - - /* Store offset of this new domain */ - for (i = 0; i < NUM_DOMAIN_OFFSETS; ++i) { - if (outpkt->domain_offsets[i] == 0) { - outpkt->domain_offsets[i] = outpkt->write_offset; - break; - } - } - - outpkt->write_offset += writelen; - } - if (jump_offset) { - /* Write jump */ - jump = lwip_htons(DOMAIN_JUMP | jump_offset); - res = pbuf_take_at(outpkt->pbuf, &jump, DOMAIN_JUMP_SIZE, outpkt->write_offset); - if (res != ERR_OK) { - return res; - } - outpkt->write_offset += DOMAIN_JUMP_SIZE; - } - return ERR_OK; -} - -/** - * Write a question to an outpacket - * A question contains domain, type and class. Since an answer also starts with these fields this function is also - * called from mdns_add_answer(). - * @param outpkt The outpacket to write to - * @param domain The domain name the answer is for - * @param type The DNS type of the answer (like 'AAAA', 'SRV') - * @param klass The DNS type of the answer (like 'IN') - * @param unicast If highest bit in class should be set, to instruct the responder to - * reply with a unicast packet - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_add_question(struct mdns_outpacket *outpkt, struct mdns_domain *domain, u16_t type, u16_t klass, u16_t unicast) -{ - u16_t question_len; - u16_t field16; - err_t res; - - if (!outpkt->pbuf) { - /* If no pbuf is active, allocate one */ - outpkt->pbuf = pbuf_alloc(PBUF_TRANSPORT, OUTPACKET_SIZE, PBUF_RAM); - if (!outpkt->pbuf) { - return ERR_MEM; - } - outpkt->write_offset = SIZEOF_DNS_HDR; - } - - /* Worst case calculation. Domain string might be compressed */ - question_len = domain->length + sizeof(type) + sizeof(klass); - if (outpkt->write_offset + question_len > outpkt->pbuf->tot_len) { - /* No space */ - return ERR_MEM; - } - - /* Write name */ - res = mdns_write_domain(outpkt, domain); - if (res != ERR_OK) { - return res; - } - - /* Write type */ - field16 = lwip_htons(type); - res = pbuf_take_at(outpkt->pbuf, &field16, sizeof(field16), outpkt->write_offset); - if (res != ERR_OK) { - return res; - } - outpkt->write_offset += sizeof(field16); - - /* Write class */ - if (unicast) { - klass |= 0x8000; - } - field16 = lwip_htons(klass); - res = pbuf_take_at(outpkt->pbuf, &field16, sizeof(field16), outpkt->write_offset); - if (res != ERR_OK) { - return res; - } - outpkt->write_offset += sizeof(field16); - - return ERR_OK; -} - -/** - * Write answer to reply packet. - * buf or answer_domain can be null. The rd_length written will be buf_length + - * size of (compressed) domain. Most uses will need either buf or answer_domain, - * special case is SRV that starts with 3 u16 and then a domain name. - * @param reply The outpacket to write to - * @param domain The domain name the answer is for - * @param type The DNS type of the answer (like 'AAAA', 'SRV') - * @param klass The DNS type of the answer (like 'IN') - * @param cache_flush If highest bit in class should be set, to instruct receiver that - * this reply replaces any earlier answer for this domain/type/class - * @param ttl Validity time in seconds to send out for IP address data in DNS replies - * @param buf Pointer to buffer of answer data - * @param buf_length Length of variable data - * @param answer_domain A domain to write after any buffer data as answer - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_add_answer(struct mdns_outpacket *reply, struct mdns_domain *domain, u16_t type, u16_t klass, u16_t cache_flush, - u32_t ttl, const u8_t *buf, size_t buf_length, struct mdns_domain *answer_domain) -{ - u16_t answer_len; - u16_t field16; - u16_t rdlen_offset; - u16_t answer_offset; - u32_t field32; - err_t res; - - if (!reply->pbuf) { - /* If no pbuf is active, allocate one */ - reply->pbuf = pbuf_alloc(PBUF_TRANSPORT, OUTPACKET_SIZE, PBUF_RAM); - if (!reply->pbuf) { - return ERR_MEM; - } - reply->write_offset = SIZEOF_DNS_HDR; - } - - /* Worst case calculation. Domain strings might be compressed */ - answer_len = domain->length + sizeof(type) + sizeof(klass) + sizeof(ttl) + sizeof(field16)/*rd_length*/; - if (buf) { - answer_len += (u16_t)buf_length; - } - if (answer_domain) { - answer_len += answer_domain->length; - } - if (reply->write_offset + answer_len > reply->pbuf->tot_len) { - /* No space */ - return ERR_MEM; - } - - /* Answer starts with same data as question, then more fields */ - mdns_add_question(reply, domain, type, klass, cache_flush); - - /* Write TTL */ - field32 = lwip_htonl(ttl); - res = pbuf_take_at(reply->pbuf, &field32, sizeof(field32), reply->write_offset); - if (res != ERR_OK) { - return res; - } - reply->write_offset += sizeof(field32); - - /* Store offsets and skip forward to the data */ - rdlen_offset = reply->write_offset; - reply->write_offset += sizeof(field16); - answer_offset = reply->write_offset; - - if (buf) { - /* Write static data */ - res = pbuf_take_at(reply->pbuf, buf, (u16_t)buf_length, reply->write_offset); - if (res != ERR_OK) { - return res; - } - reply->write_offset += (u16_t)buf_length; - } - - if (answer_domain) { - /* Write name answer (compressed if possible) */ - res = mdns_write_domain(reply, answer_domain); - if (res != ERR_OK) { - return res; - } - } - - /* Write rd_length after when we know the answer size */ - field16 = lwip_htons(reply->write_offset - answer_offset); - res = pbuf_take_at(reply->pbuf, &field16, sizeof(field16), rdlen_offset); - - return res; -} - -/** - * Helper function for mdns_read_question/mdns_read_answer - * Reads a domain, type and class from the packet - * @param pkt The MDNS packet to read from. The parse_offset field will be - * incremented to point to the next unparsed byte. - * @param info The struct to fill with domain, type and class - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_read_rr_info(struct mdns_packet *pkt, struct mdns_rr_info *info) -{ - u16_t field16, copied; - pkt->parse_offset = mdns_readname(pkt->pbuf, pkt->parse_offset, &info->domain); - if (pkt->parse_offset == MDNS_READNAME_ERROR) { - return ERR_VAL; - } - - copied = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), pkt->parse_offset); - if (copied != sizeof(field16)) { - return ERR_VAL; - } - pkt->parse_offset += copied; - info->type = lwip_ntohs(field16); - - copied = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), pkt->parse_offset); - if (copied != sizeof(field16)) { - return ERR_VAL; - } - pkt->parse_offset += copied; - info->klass = lwip_ntohs(field16); - - return ERR_OK; -} - -/** - * Read a question from the packet. - * All questions have to be read before the answers. - * @param pkt The MDNS packet to read from. The questions_left field will be decremented - * and the parse_offset will be updated. - * @param question The struct to fill with question data - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_read_question(struct mdns_packet *pkt, struct mdns_question *question) -{ - /* Safety check */ - if (pkt->pbuf->tot_len < pkt->parse_offset) { - return ERR_VAL; - } - - if (pkt->questions_left) { - err_t res; - pkt->questions_left--; - - memset(question, 0, sizeof(struct mdns_question)); - res = mdns_read_rr_info(pkt, &question->info); - if (res != ERR_OK) { - return res; - } - - /* Extract unicast flag from class field */ - question->unicast = question->info.klass & 0x8000; - question->info.klass &= 0x7FFF; - - return ERR_OK; - } - return ERR_VAL; -} - -/** - * Read an answer from the packet - * The variable length reply is not copied, its pbuf offset and length is stored instead. - * @param pkt The MDNS packet to read. The answers_left field will be decremented and - * the parse_offset will be updated. - * @param answer The struct to fill with answer data - * @return ERR_OK on success, an err_t otherwise - */ -static err_t -mdns_read_answer(struct mdns_packet *pkt, struct mdns_answer *answer) -{ - /* Read questions first */ - if (pkt->questions_left) { - return ERR_VAL; - } - - /* Safety check */ - if (pkt->pbuf->tot_len < pkt->parse_offset) { - return ERR_VAL; - } - - if (pkt->answers_left) { - u16_t copied, field16; - u32_t ttl; - err_t res; - pkt->answers_left--; - - memset(answer, 0, sizeof(struct mdns_answer)); - res = mdns_read_rr_info(pkt, &answer->info); - if (res != ERR_OK) { - return res; - } - - /* Extract cache_flush flag from class field */ - answer->cache_flush = answer->info.klass & 0x8000; - answer->info.klass &= 0x7FFF; - - copied = pbuf_copy_partial(pkt->pbuf, &ttl, sizeof(ttl), pkt->parse_offset); - if (copied != sizeof(ttl)) { - return ERR_VAL; - } - pkt->parse_offset += copied; - answer->ttl = lwip_ntohl(ttl); - - copied = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), pkt->parse_offset); - if (copied != sizeof(field16)) { - return ERR_VAL; - } - pkt->parse_offset += copied; - answer->rd_length = lwip_ntohs(field16); - - answer->rd_offset = pkt->parse_offset; - pkt->parse_offset += answer->rd_length; - - return ERR_OK; - } - return ERR_VAL; -} - -#if LWIP_IPV4 -/** Write an IPv4 address (A) RR to outpacket */ -static err_t -mdns_add_a_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct netif *netif) -{ - struct mdns_domain host; - mdns_build_host_domain(&host, NETIF_TO_HOST(netif)); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with A record\n")); - return mdns_add_answer(reply, &host, DNS_RRTYPE_A, DNS_RRCLASS_IN, cache_flush, (NETIF_TO_HOST(netif))->dns_ttl, (const u8_t *) netif_ip4_addr(netif), sizeof(ip4_addr_t), NULL); -} - -/** Write a 4.3.2.1.in-addr.arpa -> hostname.local PTR RR to outpacket */ -static err_t -mdns_add_hostv4_ptr_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct netif *netif) -{ - struct mdns_domain host, revhost; - mdns_build_host_domain(&host, NETIF_TO_HOST(netif)); - mdns_build_reverse_v4_domain(&revhost, netif_ip4_addr(netif)); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with v4 PTR record\n")); - return mdns_add_answer(reply, &revhost, DNS_RRTYPE_PTR, DNS_RRCLASS_IN, cache_flush, (NETIF_TO_HOST(netif))->dns_ttl, NULL, 0, &host); -} -#endif - -#if LWIP_IPV6 -/** Write an IPv6 address (AAAA) RR to outpacket */ -static err_t -mdns_add_aaaa_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct netif *netif, int addrindex) -{ - struct mdns_domain host; - mdns_build_host_domain(&host, NETIF_TO_HOST(netif)); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with AAAA record\n")); - return mdns_add_answer(reply, &host, DNS_RRTYPE_AAAA, DNS_RRCLASS_IN, cache_flush, (NETIF_TO_HOST(netif))->dns_ttl, (const u8_t *) netif_ip6_addr(netif, addrindex), sizeof(ip6_addr_t), NULL); -} - -/** Write a x.y.z.ip6.arpa -> hostname.local PTR RR to outpacket */ -static err_t -mdns_add_hostv6_ptr_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct netif *netif, int addrindex) -{ - struct mdns_domain host, revhost; - mdns_build_host_domain(&host, NETIF_TO_HOST(netif)); - mdns_build_reverse_v6_domain(&revhost, netif_ip6_addr(netif, addrindex)); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with v6 PTR record\n")); - return mdns_add_answer(reply, &revhost, DNS_RRTYPE_PTR, DNS_RRCLASS_IN, cache_flush, (NETIF_TO_HOST(netif))->dns_ttl, NULL, 0, &host); -} -#endif - -/** Write an all-services -> servicetype PTR RR to outpacket */ -static err_t -mdns_add_servicetype_ptr_answer(struct mdns_outpacket *reply, struct mdns_service *service) -{ - struct mdns_domain service_type, service_dnssd; - mdns_build_service_domain(&service_type, service, 0); - mdns_build_dnssd_domain(&service_dnssd); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with service type PTR record\n")); - return mdns_add_answer(reply, &service_dnssd, DNS_RRTYPE_PTR, DNS_RRCLASS_IN, 0, service->dns_ttl, NULL, 0, &service_type); -} - -/** Write a servicetype -> servicename PTR RR to outpacket */ -static err_t -mdns_add_servicename_ptr_answer(struct mdns_outpacket *reply, struct mdns_service *service) -{ - struct mdns_domain service_type, service_instance; - mdns_build_service_domain(&service_type, service, 0); - mdns_build_service_domain(&service_instance, service, 1); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with service name PTR record\n")); - return mdns_add_answer(reply, &service_type, DNS_RRTYPE_PTR, DNS_RRCLASS_IN, 0, service->dns_ttl, NULL, 0, &service_instance); -} - -/** Write a SRV RR to outpacket */ -static err_t -mdns_add_srv_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct mdns_host *mdns, struct mdns_service *service) -{ - struct mdns_domain service_instance, srvhost; - u16_t srvdata[3]; - mdns_build_service_domain(&service_instance, service, 1); - mdns_build_host_domain(&srvhost, mdns); - if (reply->legacy_query) { - /* RFC 6762 section 18.14: - * In legacy unicast responses generated to answer legacy queries, - * name compression MUST NOT be performed on SRV records. - */ - srvhost.skip_compression = 1; - } - srvdata[0] = lwip_htons(SRV_PRIORITY); - srvdata[1] = lwip_htons(SRV_WEIGHT); - srvdata[2] = lwip_htons(service->port); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with SRV record\n")); - return mdns_add_answer(reply, &service_instance, DNS_RRTYPE_SRV, DNS_RRCLASS_IN, cache_flush, service->dns_ttl, - (const u8_t *) &srvdata, sizeof(srvdata), &srvhost); -} - -/** Write a TXT RR to outpacket */ -static err_t -mdns_add_txt_answer(struct mdns_outpacket *reply, u16_t cache_flush, struct mdns_service *service) -{ - struct mdns_domain service_instance; - mdns_build_service_domain(&service_instance, service, 1); - mdns_prepare_txtdata(service); - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Responding with TXT record\n")); - return mdns_add_answer(reply, &service_instance, DNS_RRTYPE_TXT, DNS_RRCLASS_IN, cache_flush, service->dns_ttl, - (u8_t *) &service->txtdata.name, service->txtdata.length, NULL); -} - -/** - * Setup outpacket as a reply to the incoming packet - */ -static void -mdns_init_outpacket(struct mdns_outpacket *out, struct mdns_packet *in) -{ - memset(out, 0, sizeof(struct mdns_outpacket)); - out->cache_flush = 1; - out->netif = in->netif; - - /* Copy source IP/port to use when responding unicast, or to choose - * which pcb to use for multicast (IPv4/IPv6) - */ - SMEMCPY(&out->dest_addr, &in->source_addr, sizeof(ip_addr_t)); - out->dest_port = in->source_port; - - if (in->source_port != MDNS_PORT) { - out->unicast_reply = 1; - out->cache_flush = 0; - if (in->questions == 1) { - out->legacy_query = 1; - out->tx_id = in->tx_id; - } - } - - if (in->recv_unicast) { - out->unicast_reply = 1; - } -} - -/** - * Send chosen answers as a reply - * - * Add all selected answers (first write will allocate pbuf) - * Add additional answers based on the selected answers - * Send the packet - */ -static void -mdns_send_outpacket(struct mdns_outpacket *outpkt) -{ - struct mdns_service *service; - err_t res; - int i; - struct mdns_host* mdns = NETIF_TO_HOST(outpkt->netif); - - /* Write answers to host questions */ -#if LWIP_IPV4 - if (outpkt->host_replies & REPLY_HOST_A) { - res = mdns_add_a_answer(outpkt, outpkt->cache_flush, outpkt->netif); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - if (outpkt->host_replies & REPLY_HOST_PTR_V4) { - res = mdns_add_hostv4_ptr_answer(outpkt, outpkt->cache_flush, outpkt->netif); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } -#endif -#if LWIP_IPV6 - if (outpkt->host_replies & REPLY_HOST_AAAA) { - int addrindex; - for (addrindex = 0; addrindex < LWIP_IPV6_NUM_ADDRESSES; ++addrindex) { - if (ip6_addr_isvalid(netif_ip6_addr_state(outpkt->netif, addrindex))) { - res = mdns_add_aaaa_answer(outpkt, outpkt->cache_flush, outpkt->netif, addrindex); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - } - } - if (outpkt->host_replies & REPLY_HOST_PTR_V6) { - u8_t rev_addrs = outpkt->host_reverse_v6_replies; - int addrindex = 0; - while (rev_addrs) { - if (rev_addrs & 1) { - res = mdns_add_hostv6_ptr_answer(outpkt, outpkt->cache_flush, outpkt->netif, addrindex); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - addrindex++; - rev_addrs >>= 1; - } - } -#endif - - /* Write answers to service questions */ - for (i = 0; i < MDNS_MAX_SERVICES; ++i) { - service = mdns->services[i]; - if (!service) { - continue; - } - - if (outpkt->serv_replies[i] & REPLY_SERVICE_TYPE_PTR) { - res = mdns_add_servicetype_ptr_answer(outpkt, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - - if (outpkt->serv_replies[i] & REPLY_SERVICE_NAME_PTR) { - res = mdns_add_servicename_ptr_answer(outpkt, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - - if (outpkt->serv_replies[i] & REPLY_SERVICE_SRV) { - res = mdns_add_srv_answer(outpkt, outpkt->cache_flush, mdns, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - - if (outpkt->serv_replies[i] & REPLY_SERVICE_TXT) { - res = mdns_add_txt_answer(outpkt, outpkt->cache_flush, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->answers++; - } - } - - /* All answers written, add additional RRs */ - for (i = 0; i < MDNS_MAX_SERVICES; ++i) { - service = mdns->services[i]; - if (!service) { - continue; - } - - if (outpkt->serv_replies[i] & REPLY_SERVICE_NAME_PTR) { - /* Our service instance requested, include SRV & TXT - * if they are already not requested. */ - if (!(outpkt->serv_replies[i] & REPLY_SERVICE_SRV)) { - res = mdns_add_srv_answer(outpkt, outpkt->cache_flush, mdns, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->additional++; - } - - if (!(outpkt->serv_replies[i] & REPLY_SERVICE_TXT)) { - res = mdns_add_txt_answer(outpkt, outpkt->cache_flush, service); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->additional++; - } - } - - /* If service instance, SRV, record or an IP address is requested, - * supply all addresses for the host - */ - if ((outpkt->serv_replies[i] & (REPLY_SERVICE_NAME_PTR | REPLY_SERVICE_SRV)) || - (outpkt->host_replies & (REPLY_HOST_A | REPLY_HOST_AAAA))) { -#if LWIP_IPV6 - if (!(outpkt->host_replies & REPLY_HOST_AAAA)) { - int addrindex; - for (addrindex = 0; addrindex < LWIP_IPV6_NUM_ADDRESSES; ++addrindex) { - if (ip6_addr_isvalid(netif_ip6_addr_state(outpkt->netif, addrindex))) { - res = mdns_add_aaaa_answer(outpkt, outpkt->cache_flush, outpkt->netif, addrindex); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->additional++; - } - } - } -#endif -#if LWIP_IPV4 - if (!(outpkt->host_replies & REPLY_HOST_A)) { - res = mdns_add_a_answer(outpkt, outpkt->cache_flush, outpkt->netif); - if (res != ERR_OK) { - goto cleanup; - } - outpkt->additional++; - } -#endif - } - } - - if (outpkt->pbuf) { - const ip_addr_t *mcast_destaddr; - struct dns_hdr hdr; - - /* Write header */ - memset(&hdr, 0, sizeof(hdr)); - hdr.flags1 = DNS_FLAG1_RESPONSE | DNS_FLAG1_AUTHORATIVE; - hdr.numanswers = lwip_htons(outpkt->answers); - hdr.numextrarr = lwip_htons(outpkt->additional); - if (outpkt->legacy_query) { - hdr.numquestions = lwip_htons(1); - hdr.id = lwip_htons(outpkt->tx_id); - } - pbuf_take(outpkt->pbuf, &hdr, sizeof(hdr)); - - /* Shrink packet */ - pbuf_realloc(outpkt->pbuf, outpkt->write_offset); - - if (IP_IS_V6_VAL(outpkt->dest_addr)) { -#if LWIP_IPV6 - mcast_destaddr = &v6group; -#endif - } else { -#if LWIP_IPV4 - mcast_destaddr = &v4group; -#endif - } - /* Send created packet */ - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Sending packet, len=%d, unicast=%d\n", outpkt->write_offset, outpkt->unicast_reply)); - if (outpkt->unicast_reply) { - udp_sendto_if(mdns_pcb, outpkt->pbuf, &outpkt->dest_addr, outpkt->dest_port, outpkt->netif); - } else { - udp_sendto_if(mdns_pcb, outpkt->pbuf, mcast_destaddr, MDNS_PORT, outpkt->netif); - } - } - -cleanup: - if (outpkt->pbuf) { - pbuf_free(outpkt->pbuf); - outpkt->pbuf = NULL; - } -} - -/** - * Send unsolicited answer containing all our known data - * @param netif The network interface to send on - * @param destination The target address to send to (usually multicast address) - */ -static void -mdns_announce(struct netif *netif, const ip_addr_t *destination) -{ - struct mdns_outpacket announce; - int i; - struct mdns_host* mdns = NETIF_TO_HOST(netif); - - memset(&announce, 0, sizeof(announce)); - announce.netif = netif; - announce.cache_flush = 1; -#if LWIP_IPV4 - if (!ip4_addr_isany_val(*netif_ip4_addr(netif))) - announce.host_replies = REPLY_HOST_A | REPLY_HOST_PTR_V4; -#endif -#if LWIP_IPV6 - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) { - announce.host_replies |= REPLY_HOST_AAAA | REPLY_HOST_PTR_V6; - announce.host_reverse_v6_replies |= (1 << i); - } - } -#endif - - for (i = 0; i < MDNS_MAX_SERVICES; i++) { - struct mdns_service *serv = mdns->services[i]; - if (serv) { - announce.serv_replies[i] = REPLY_SERVICE_TYPE_PTR | REPLY_SERVICE_NAME_PTR | - REPLY_SERVICE_SRV | REPLY_SERVICE_TXT; - } - } - - announce.dest_port = MDNS_PORT; - SMEMCPY(&announce.dest_addr, destination, sizeof(announce.dest_addr)); - mdns_send_outpacket(&announce); -} - -/** - * Handle question MDNS packet - * 1. Parse all questions and set bits what answers to send - * 2. Clear pending answers if known answers are supplied - * 3. Put chosen answers in new packet and send as reply - */ -static void -mdns_handle_question(struct mdns_packet *pkt) -{ - struct mdns_service *service; - struct mdns_outpacket reply; - int replies = 0; - int i; - err_t res; - struct mdns_host* mdns = NETIF_TO_HOST(pkt->netif); - - mdns_init_outpacket(&reply, pkt); - - while (pkt->questions_left) { - struct mdns_question q; - - res = mdns_read_question(pkt, &q); - if (res != ERR_OK) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Failed to parse question, skipping query packet\n")); - return; - } - - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Query for domain ")); - mdns_domain_debug_print(&q.info.domain); - LWIP_DEBUGF(MDNS_DEBUG, (" type %d class %d\n", q.info.type, q.info.klass)); - - if (q.unicast) { - /* Reply unicast if any question is unicast */ - reply.unicast_reply = 1; - } - - reply.host_replies |= check_host(pkt->netif, &q.info, &reply.host_reverse_v6_replies); - replies |= reply.host_replies; - - for (i = 0; i < MDNS_MAX_SERVICES; ++i) { - service = mdns->services[i]; - if (!service) { - continue; - } - reply.serv_replies[i] |= check_service(service, &q.info); - replies |= reply.serv_replies[i]; - } - - if (replies && reply.legacy_query) { - /* Add question to reply packet (legacy packet only has 1 question) */ - res = mdns_add_question(&reply, &q.info.domain, q.info.type, q.info.klass, 0); - if (res != ERR_OK) { - goto cleanup; - } - } - } - - /* Handle known answers */ - while (pkt->answers_left) { - struct mdns_answer ans; - u8_t rev_v6; - int match; - - res = mdns_read_answer(pkt, &ans); - if (res != ERR_OK) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Failed to parse answer, skipping query packet\n")); - goto cleanup; - } - - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Known answer for domain ")); - mdns_domain_debug_print(&ans.info.domain); - LWIP_DEBUGF(MDNS_DEBUG, (" type %d class %d\n", ans.info.type, ans.info.klass)); - - - if (ans.info.type == DNS_RRTYPE_ANY || ans.info.klass == DNS_RRCLASS_ANY) { - /* Skip known answers for ANY type & class */ - continue; - } - - rev_v6 = 0; - match = reply.host_replies & check_host(pkt->netif, &ans.info, &rev_v6); - if (match && (ans.ttl > (mdns->dns_ttl / 2))) { - /* The RR in the known answer matches an RR we are planning to send, - * and the TTL is less than half gone. - * If the payload matches we should not send that answer. - */ - if (ans.info.type == DNS_RRTYPE_PTR) { - /* Read domain and compare */ - struct mdns_domain known_ans, my_ans; - u16_t len; - len = mdns_readname(pkt->pbuf, ans.rd_offset, &known_ans); - res = mdns_build_host_domain(&my_ans, mdns); - if (len != MDNS_READNAME_ERROR && res == ERR_OK && mdns_domain_eq(&known_ans, &my_ans)) { -#if LWIP_IPV4 - if (match & REPLY_HOST_PTR_V4) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: v4 PTR\n")); - reply.host_replies &= ~REPLY_HOST_PTR_V4; - } -#endif -#if LWIP_IPV6 - if (match & REPLY_HOST_PTR_V6) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: v6 PTR\n")); - reply.host_reverse_v6_replies &= ~rev_v6; - if (reply.host_reverse_v6_replies == 0) { - reply.host_replies &= ~REPLY_HOST_PTR_V6; - } - } -#endif - } - } else if (match & REPLY_HOST_A) { -#if LWIP_IPV4 - if (ans.rd_length == sizeof(ip4_addr_t) && - pbuf_memcmp(pkt->pbuf, ans.rd_offset, netif_ip4_addr(pkt->netif), ans.rd_length) == 0) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: A\n")); - reply.host_replies &= ~REPLY_HOST_A; - } -#endif - } else if (match & REPLY_HOST_AAAA) { -#if LWIP_IPV6 - if (ans.rd_length == sizeof(ip6_addr_t) && - /* TODO this clears all AAAA responses if first addr is set as known */ - pbuf_memcmp(pkt->pbuf, ans.rd_offset, netif_ip6_addr(pkt->netif, 0), ans.rd_length) == 0) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: AAAA\n")); - reply.host_replies &= ~REPLY_HOST_AAAA; - } -#endif - } - } - - for (i = 0; i < MDNS_MAX_SERVICES; ++i) { - service = mdns->services[i]; - if (!service) { - continue; - } - match = reply.serv_replies[i] & check_service(service, &ans.info); - if (match && (ans.ttl > (service->dns_ttl / 2))) { - /* The RR in the known answer matches an RR we are planning to send, - * and the TTL is less than half gone. - * If the payload matches we should not send that answer. - */ - if (ans.info.type == DNS_RRTYPE_PTR) { - /* Read domain and compare */ - struct mdns_domain known_ans, my_ans; - u16_t len; - len = mdns_readname(pkt->pbuf, ans.rd_offset, &known_ans); - if (len != MDNS_READNAME_ERROR) { - if (match & REPLY_SERVICE_TYPE_PTR) { - res = mdns_build_service_domain(&my_ans, service, 0); - if (res == ERR_OK && mdns_domain_eq(&known_ans, &my_ans)) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: service type PTR\n")); - reply.serv_replies[i] &= ~REPLY_SERVICE_TYPE_PTR; - } - } - if (match & REPLY_SERVICE_NAME_PTR) { - res = mdns_build_service_domain(&my_ans, service, 1); - if (res == ERR_OK && mdns_domain_eq(&known_ans, &my_ans)) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: service name PTR\n")); - reply.serv_replies[i] &= ~REPLY_SERVICE_NAME_PTR; - } - } - } - } else if (match & REPLY_SERVICE_SRV) { - /* Read and compare to my SRV record */ - u16_t field16, len, read_pos; - struct mdns_domain known_ans, my_ans; - read_pos = ans.rd_offset; - do { - /* Check priority field */ - len = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), read_pos); - if (len != sizeof(field16) || lwip_ntohs(field16) != SRV_PRIORITY) { - break; - } - read_pos += len; - /* Check weight field */ - len = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), read_pos); - if (len != sizeof(field16) || lwip_ntohs(field16) != SRV_WEIGHT) { - break; - } - read_pos += len; - /* Check port field */ - len = pbuf_copy_partial(pkt->pbuf, &field16, sizeof(field16), read_pos); - if (len != sizeof(field16) || lwip_ntohs(field16) != service->port) { - break; - } - read_pos += len; - /* Check host field */ - len = mdns_readname(pkt->pbuf, read_pos, &known_ans); - mdns_build_host_domain(&my_ans, mdns); - if (len == MDNS_READNAME_ERROR || !mdns_domain_eq(&known_ans, &my_ans)) { - break; - } - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: SRV\n")); - reply.serv_replies[i] &= ~REPLY_SERVICE_SRV; - } while (0); - } else if (match & REPLY_SERVICE_TXT) { - mdns_prepare_txtdata(service); - if (service->txtdata.length == ans.rd_length && - pbuf_memcmp(pkt->pbuf, ans.rd_offset, service->txtdata.name, ans.rd_length) == 0) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Skipping known answer: TXT\n")); - reply.serv_replies[i] &= ~REPLY_SERVICE_TXT; - } - } - } - } - } - - mdns_send_outpacket(&reply); - -cleanup: - if (reply.pbuf) { - /* This should only happen if we fail to alloc/write question for legacy query */ - pbuf_free(reply.pbuf); - reply.pbuf = NULL; - } -} - -/** - * Handle response MDNS packet - * Only prints debug for now. Will need more code to do conflict resolution. - */ -static void -mdns_handle_response(struct mdns_packet *pkt) -{ - /* Ignore all questions */ - while (pkt->questions_left) { - struct mdns_question q; - err_t res; - - res = mdns_read_question(pkt, &q); - if (res != ERR_OK) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Failed to parse question, skipping response packet\n")); - return; - } - } - - while (pkt->answers_left) { - struct mdns_answer ans; - err_t res; - - res = mdns_read_answer(pkt, &ans); - if (res != ERR_OK) { - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Failed to parse answer, skipping response packet\n")); - return; - } - - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Answer for domain ")); - mdns_domain_debug_print(&ans.info.domain); - LWIP_DEBUGF(MDNS_DEBUG, (" type %d class %d\n", ans.info.type, ans.info.klass)); - } -} - -/** - * Receive input function for MDNS packets. - * Handles both IPv4 and IPv6 UDP pcbs. - */ -static void -mdns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - struct dns_hdr hdr; - struct mdns_packet packet; - struct netif *recv_netif = ip_current_input_netif(); - u16_t offset = 0; - - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(pcb); - - LWIP_DEBUGF(MDNS_DEBUG, ("MDNS: Received IPv%d MDNS packet, len %d\n", IP_IS_V6(addr)? 6 : 4, p->tot_len)); - - if (NETIF_TO_HOST(recv_netif) == NULL) { - /* From netif not configured for MDNS */ - goto dealloc; - } - - if (pbuf_copy_partial(p, &hdr, SIZEOF_DNS_HDR, offset) < SIZEOF_DNS_HDR) { - /* Too small */ - goto dealloc; - } - offset += SIZEOF_DNS_HDR; - - if (DNS_HDR_GET_OPCODE(&hdr)) { - /* Ignore non-standard queries in multicast packets (RFC 6762, section 18.3) */ - goto dealloc; - } - - memset(&packet, 0, sizeof(packet)); - SMEMCPY(&packet.source_addr, addr, sizeof(packet.source_addr)); - packet.source_port = port; - packet.netif = recv_netif; - packet.pbuf = p; - packet.parse_offset = offset; - packet.tx_id = lwip_ntohs(hdr.id); - packet.questions = packet.questions_left = lwip_ntohs(hdr.numquestions); - packet.answers = packet.answers_left = lwip_ntohs(hdr.numanswers) + lwip_ntohs(hdr.numauthrr) + lwip_ntohs(hdr.numextrarr); - -#if LWIP_IPV6 - if (IP_IS_V6(ip_current_dest_addr())) { - if (!ip_addr_cmp(ip_current_dest_addr(), &v6group)) { - packet.recv_unicast = 1; - } - } -#endif -#if LWIP_IPV4 - if (!IP_IS_V6(ip_current_dest_addr())) { - if (!ip_addr_cmp(ip_current_dest_addr(), &v4group)) { - packet.recv_unicast = 1; - } - } -#endif - - if (hdr.flags1 & DNS_FLAG1_RESPONSE) { - mdns_handle_response(&packet); - } else { - mdns_handle_question(&packet); - } - -dealloc: - pbuf_free(p); -} - -/** - * @ingroup mdns - * Initiate MDNS responder. Will open UDP sockets on port 5353 - */ -void -mdns_resp_init(void) -{ - err_t res; - - mdns_pcb = udp_new_ip_type(IPADDR_TYPE_ANY); - LWIP_ASSERT("Failed to allocate pcb", mdns_pcb != NULL); -#if LWIP_MULTICAST_TX_OPTIONS - udp_set_multicast_ttl(mdns_pcb, MDNS_TTL); -#else - mdns_pcb->ttl = MDNS_TTL; -#endif - res = udp_bind(mdns_pcb, IP_ANY_TYPE, MDNS_PORT); - LWIP_UNUSED_ARG(res); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("Failed to bind pcb", res == ERR_OK); - udp_recv(mdns_pcb, mdns_recv, NULL); - - mdns_netif_client_id = netif_alloc_client_data_id(); -} - -/** - * @ingroup mdns - * Announce IP settings have changed on netif. - * Call this in your callback registered by netif_set_status_callback(). - * This function may go away in the future when netif supports registering - * multiple callback functions. - * @param netif The network interface where settings have changed. - */ -void -mdns_resp_netif_settings_changed(struct netif *netif) -{ - LWIP_ERROR("mdns_resp_netif_ip_changed: netif != NULL", (netif != NULL), return); - - if (NETIF_TO_HOST(netif) == NULL) { - return; - } - - /* Announce on IPv6 and IPv4 */ -#if LWIP_IPV6 - mdns_announce(netif, IP6_ADDR_ANY); -#endif -#if LWIP_IPV4 - mdns_announce(netif, IP4_ADDR_ANY); -#endif -} - -/** - * @ingroup mdns - * Activate MDNS responder for a network interface and send announce packets. - * @param netif The network interface to activate. - * @param hostname Name to use. Queries for <hostname>.local will be answered - * with the IP addresses of the netif. The hostname will be copied, the - * given pointer can be on the stack. - * @param dns_ttl Validity time in seconds to send out for IP address data in DNS replies - * @return ERR_OK if netif was added, an err_t otherwise - */ -err_t -mdns_resp_add_netif(struct netif *netif, const char *hostname, u32_t dns_ttl) -{ - err_t res; - struct mdns_host* mdns; - - LWIP_ERROR("mdns_resp_add_netif: netif != NULL", (netif != NULL), return ERR_VAL); - LWIP_ERROR("mdns_resp_add_netif: Hostname too long", (strlen(hostname) <= MDNS_LABEL_MAXLEN), return ERR_VAL); - - LWIP_ASSERT("mdns_resp_add_netif: Double add", NETIF_TO_HOST(netif) == NULL); - mdns = (struct mdns_host *) mem_malloc(sizeof(struct mdns_host)); - LWIP_ERROR("mdns_resp_add_netif: Alloc failed", (mdns != NULL), return ERR_MEM); - - netif_set_client_data(netif, mdns_netif_client_id, mdns); - - memset(mdns, 0, sizeof(struct mdns_host)); - MEMCPY(&mdns->name, hostname, LWIP_MIN(MDNS_LABEL_MAXLEN, strlen(hostname))); - mdns->dns_ttl = dns_ttl; - - /* Join multicast groups */ -#if LWIP_IPV4 - res = igmp_joingroup_netif(netif, ip_2_ip4(&v4group)); - if (res != ERR_OK) { - goto cleanup; - } -#endif -#if LWIP_IPV6 - res = mld6_joingroup_netif(netif, ip_2_ip6(&v6group)); - if (res != ERR_OK) { - goto cleanup; - } -#endif - - mdns_resp_netif_settings_changed(netif); - return ERR_OK; - -cleanup: - mem_free(mdns); - netif_set_client_data(netif, mdns_netif_client_id, NULL); - return res; -} - -/** - * @ingroup mdns - * Stop responding to MDNS queries on this interface, leave multicast groups, - * and free the helper structure and any of its services. - * @param netif The network interface to remove. - * @return ERR_OK if netif was removed, an err_t otherwise - */ -err_t -mdns_resp_remove_netif(struct netif *netif) -{ - int i; - struct mdns_host* mdns; - - LWIP_ASSERT("mdns_resp_remove_netif: Null pointer", netif); - mdns = NETIF_TO_HOST(netif); - LWIP_ERROR("mdns_resp_remove_netif: Not an active netif", (mdns != NULL), return ERR_VAL); - - for (i = 0; i < MDNS_MAX_SERVICES; i++) { - struct mdns_service *service = mdns->services[i]; - if (service) { - mem_free(service); - } - } - - /* Leave multicast groups */ -#if LWIP_IPV4 - igmp_leavegroup_netif(netif, ip_2_ip4(&v4group)); -#endif -#if LWIP_IPV6 - mld6_leavegroup_netif(netif, ip_2_ip6(&v6group)); -#endif - - mem_free(mdns); - netif_set_client_data(netif, mdns_netif_client_id, NULL); - return ERR_OK; -} - -/** - * @ingroup mdns - * Add a service to the selected network interface. - * @param netif The network interface to publish this service on - * @param name The name of the service - * @param service The service type, like "_http" - * @param proto The service protocol, DNSSD_PROTO_TCP for TCP ("_tcp") and DNSSD_PROTO_UDP - * for others ("_udp") - * @param port The port the service listens to - * @param dns_ttl Validity time in seconds to send out for service data in DNS replies - * @param txt_fn Callback to get TXT data. Will be called each time a TXT reply is created to - * allow dynamic replies. - * @param txt_data Userdata pointer for txt_fn - * @return ERR_OK if the service was added to the netif, an err_t otherwise - */ -err_t -mdns_resp_add_service(struct netif *netif, const char *name, const char *service, enum mdns_sd_proto proto, u16_t port, u32_t dns_ttl, service_get_txt_fn_t txt_fn, void *txt_data) -{ - int i; - int slot = -1; - struct mdns_service *srv; - struct mdns_host* mdns; - - LWIP_ASSERT("mdns_resp_add_service: netif != NULL", netif); - mdns = NETIF_TO_HOST(netif); - LWIP_ERROR("mdns_resp_add_service: Not an mdns netif", (mdns != NULL), return ERR_VAL); - - LWIP_ERROR("mdns_resp_add_service: Name too long", (strlen(name) <= MDNS_LABEL_MAXLEN), return ERR_VAL); - LWIP_ERROR("mdns_resp_add_service: Service too long", (strlen(service) <= MDNS_LABEL_MAXLEN), return ERR_VAL); - LWIP_ERROR("mdns_resp_add_service: Bad proto (need TCP or UDP)", (proto == DNSSD_PROTO_TCP || proto == DNSSD_PROTO_UDP), return ERR_VAL); - - for (i = 0; i < MDNS_MAX_SERVICES; i++) { - if (mdns->services[i] == NULL) { - slot = i; - break; - } - } - LWIP_ERROR("mdns_resp_add_service: Service list full (increase MDNS_MAX_SERVICES)", (slot >= 0), return ERR_MEM); - - srv = (struct mdns_service*)mem_malloc(sizeof(struct mdns_service)); - LWIP_ERROR("mdns_resp_add_service: Alloc failed", (srv != NULL), return ERR_MEM); - - memset(srv, 0, sizeof(struct mdns_service)); - - MEMCPY(&srv->name, name, LWIP_MIN(MDNS_LABEL_MAXLEN, strlen(name))); - MEMCPY(&srv->service, service, LWIP_MIN(MDNS_LABEL_MAXLEN, strlen(service))); - srv->txt_fn = txt_fn; - srv->txt_userdata = txt_data; - srv->proto = (u16_t)proto; - srv->port = port; - srv->dns_ttl = dns_ttl; - - mdns->services[slot] = srv; - - /* Announce on IPv6 and IPv4 */ -#if LWIP_IPV6 - mdns_announce(netif, IP6_ADDR_ANY); -#endif -#if LWIP_IPV4 - mdns_announce(netif, IP4_ADDR_ANY); -#endif - - return ERR_OK; -} - -/** - * @ingroup mdns - * Call this function from inside the service_get_txt_fn_t callback to add text data. - * Buffer for TXT data is 256 bytes, and each field is prefixed with a length byte. - * @param service The service provided to the get_txt callback - * @param txt String to add to the TXT field. - * @param txt_len Length of string - * @return ERR_OK if the string was added to the reply, an err_t otherwise - */ -err_t -mdns_resp_add_service_txtitem(struct mdns_service *service, const char *txt, u8_t txt_len) -{ - LWIP_ASSERT("mdns_resp_add_service_txtitem: service != NULL", service); - - /* Use a mdns_domain struct to store txt chunks since it is the same encoding */ - return mdns_domain_add_label(&service->txtdata, txt, txt_len); -} - -#endif /* LWIP_MDNS_RESPONDER */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mqtt/mqtt.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mqtt/mqtt.c deleted file mode 100644 index a0e77b9719d2226a12cdbc4e7bd0814df872b4f3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/mqtt/mqtt.c +++ /dev/null @@ -1,1341 +0,0 @@ -/** - * @file - * MQTT client - * - * @defgroup mqtt MQTT client - * @ingroup apps - * @verbinclude mqtt_client.txt - */ - -/* - * Copyright (c) 2016 Erik Andersson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack - * - * Author: Erik Andersson - * - * - * @todo: - * - Handle large outgoing payloads for PUBLISH messages - * - Fix restriction of a single topic in each (UN)SUBSCRIBE message (protocol has support for multiple topics) - * - Add support for legacy MQTT protocol version - * - * Please coordinate changes and requests with Erik Andersson - * Erik Andersson - * - */ -#include "lwip/apps/mqtt.h" -#include "lwip/timeouts.h" -#include "lwip/ip_addr.h" -#include "lwip/mem.h" -#include "lwip/err.h" -#include "lwip/pbuf.h" -#include "lwip/tcp.h" -#include - -#if LWIP_TCP && LWIP_CALLBACK_API - -/** - * MQTT_DEBUG: Default is off. - */ -#if !defined MQTT_DEBUG || defined __DOXYGEN__ -#define MQTT_DEBUG LWIP_DBG_OFF -#endif - -#define MQTT_DEBUG_TRACE (MQTT_DEBUG | LWIP_DBG_TRACE) -#define MQTT_DEBUG_STATE (MQTT_DEBUG | LWIP_DBG_STATE) -#define MQTT_DEBUG_WARN (MQTT_DEBUG | LWIP_DBG_LEVEL_WARNING) -#define MQTT_DEBUG_WARN_STATE (MQTT_DEBUG | LWIP_DBG_LEVEL_WARNING | LWIP_DBG_STATE) -#define MQTT_DEBUG_SERIOUS (MQTT_DEBUG | LWIP_DBG_LEVEL_SERIOUS) - -static void mqtt_cyclic_timer(void *arg); - -/** - * MQTT client connection states - */ -enum { - TCP_DISCONNECTED, - TCP_CONNECTING, - MQTT_CONNECTING, - MQTT_CONNECTED -}; - -/** - * MQTT control message types - */ -enum mqtt_message_type { - MQTT_MSG_TYPE_CONNECT = 1, - MQTT_MSG_TYPE_CONNACK = 2, - MQTT_MSG_TYPE_PUBLISH = 3, - MQTT_MSG_TYPE_PUBACK = 4, - MQTT_MSG_TYPE_PUBREC = 5, - MQTT_MSG_TYPE_PUBREL = 6, - MQTT_MSG_TYPE_PUBCOMP = 7, - MQTT_MSG_TYPE_SUBSCRIBE = 8, - MQTT_MSG_TYPE_SUBACK = 9, - MQTT_MSG_TYPE_UNSUBSCRIBE = 10, - MQTT_MSG_TYPE_UNSUBACK = 11, - MQTT_MSG_TYPE_PINGREQ = 12, - MQTT_MSG_TYPE_PINGRESP = 13, - MQTT_MSG_TYPE_DISCONNECT = 14 -}; - -/** Helpers to extract control packet type and qos from first byte in fixed header */ -#define MQTT_CTL_PACKET_TYPE(fixed_hdr_byte0) ((fixed_hdr_byte0 & 0xf0) >> 4) -#define MQTT_CTL_PACKET_QOS(fixed_hdr_byte0) ((fixed_hdr_byte0 & 0x6) >> 1) - -/** - * MQTT connect flags, only used in CONNECT message - */ -enum mqtt_connect_flag { - MQTT_CONNECT_FLAG_USERNAME = 1 << 7, - MQTT_CONNECT_FLAG_PASSWORD = 1 << 6, - MQTT_CONNECT_FLAG_WILL_RETAIN = 1 << 5, - MQTT_CONNECT_FLAG_WILL = 1 << 2, - MQTT_CONNECT_FLAG_CLEAN_SESSION = 1 << 1 -}; - - -#if defined(LWIP_DEBUG) -static const char * const mqtt_message_type_str[15] = -{ - "UNDEFINED", - "CONNECT", - "CONNACK", - "PUBLISH", - "PUBACK", - "PUBREC", - "PUBREL", - "PUBCOMP", - "SUBSCRIBE", - "SUBACK", - "UNSUBSCRIBE", - "UNSUBACK", - "PINGREQ", - "PINGRESP", - "DISCONNECT" -}; - -/** - * Message type value to string - * @param msg_type see enum mqtt_message_type - * - * @return Control message type text string - */ -static const char * -mqtt_msg_type_to_str(u8_t msg_type) -{ - if (msg_type >= LWIP_ARRAYSIZE(mqtt_message_type_str)) { - msg_type = 0; - } - return mqtt_message_type_str[msg_type]; -} - -#endif - - -/** - * Generate MQTT packet identifier - * @param client MQTT client - * @return New packet identifier, range 1 to 65535 - */ -static u16_t -msg_generate_packet_id(mqtt_client_t *client) -{ - client->pkt_id_seq++; - if (client->pkt_id_seq == 0) { - client->pkt_id_seq++; - } - return client->pkt_id_seq; -} - -/*--------------------------------------------------------------------------------------------------------------------- */ -/* Output ring buffer */ - - -#define MQTT_RINGBUF_IDX_MASK ((MQTT_OUTPUT_RINGBUF_SIZE) - 1) - -/** Add single item to ring buffer */ -#define mqtt_ringbuf_put(rb, item) ((rb)->buf)[(rb)->put++ & MQTT_RINGBUF_IDX_MASK] = (item) - -/** Return number of bytes in ring buffer */ -#define mqtt_ringbuf_len(rb) ((u16_t)((rb)->put - (rb)->get)) - -/** Return number of bytes free in ring buffer */ -#define mqtt_ringbuf_free(rb) (MQTT_OUTPUT_RINGBUF_SIZE - mqtt_ringbuf_len(rb)) - -/** Return number of bytes possible to read without wrapping around */ -#define mqtt_ringbuf_linear_read_length(rb) LWIP_MIN(mqtt_ringbuf_len(rb), (MQTT_OUTPUT_RINGBUF_SIZE - ((rb)->get & MQTT_RINGBUF_IDX_MASK))) - -/** Return pointer to ring buffer get position */ -#define mqtt_ringbuf_get_ptr(rb) (&(rb)->buf[(rb)->get & MQTT_RINGBUF_IDX_MASK]) - -#define mqtt_ringbuf_advance_get_idx(rb, len) ((rb)->get += (len)) - - -/** - * Try send as many bytes as possible from output ring buffer - * @param rb Output ring buffer - * @param tpcb TCP connection handle - */ -static void -mqtt_output_send(struct mqtt_ringbuf_t *rb, struct tcp_pcb *tpcb) -{ - err_t err; - u8_t wrap = 0; - u16_t ringbuf_lin_len = mqtt_ringbuf_linear_read_length(rb); - u16_t send_len = tcp_sndbuf(tpcb); - LWIP_ASSERT("mqtt_output_send: tpcb != NULL", tpcb != NULL); - - if (send_len == 0 || ringbuf_lin_len == 0) { - return; - } - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_output_send: tcp_sndbuf: %d bytes, ringbuf_linear_available: %d, get %d, put %d\n", - send_len, ringbuf_lin_len, ((rb)->get & MQTT_RINGBUF_IDX_MASK), ((rb)->put & MQTT_RINGBUF_IDX_MASK))); - - if (send_len > ringbuf_lin_len) { - /* Space in TCP output buffer is larger than available in ring buffer linear portion */ - send_len = ringbuf_lin_len; - /* Wrap around if more data in ring buffer after linear portion */ - wrap = (mqtt_ringbuf_len(rb) > ringbuf_lin_len); - } - err = tcp_write(tpcb, mqtt_ringbuf_get_ptr(rb), send_len, TCP_WRITE_FLAG_COPY | (wrap ? TCP_WRITE_FLAG_MORE : 0)); - if ((err == ERR_OK) && wrap) { - mqtt_ringbuf_advance_get_idx(rb, send_len); - /* Use the lesser one of ring buffer linear length and TCP send buffer size */ - send_len = LWIP_MIN(tcp_sndbuf(tpcb), mqtt_ringbuf_linear_read_length(rb)); - err = tcp_write(tpcb, mqtt_ringbuf_get_ptr(rb), send_len, TCP_WRITE_FLAG_COPY); - } - - if (err == ERR_OK) { - mqtt_ringbuf_advance_get_idx(rb, send_len); - /* Flush */ - tcp_output(tpcb); - } else { - LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_output_send: Send failed with err %d (\"%s\")\n", err, lwip_strerr(err))); - } -} - - - -/*--------------------------------------------------------------------------------------------------------------------- */ -/* Request queue */ - -/** - * Create request item - * @param r_objs Pointer to request objects - * @param pkt_id Packet identifier of request - * @param cb Packet callback to call when requests lifetime ends - * @param arg Parameter following callback - * @return Request or NULL if failed to create - */ -static struct mqtt_request_t * -mqtt_create_request(struct mqtt_request_t *r_objs, u16_t pkt_id, mqtt_request_cb_t cb, void *arg) -{ - struct mqtt_request_t *r = NULL; - u8_t n; - LWIP_ASSERT("mqtt_create_request: r_objs != NULL", r_objs != NULL); - for (n = 0; n < MQTT_REQ_MAX_IN_FLIGHT; n++) { - /* Item point to itself if not in use */ - if (r_objs[n].next == &r_objs[n]) { - r = &r_objs[n]; - r->next = NULL; - r->cb = cb; - r->arg = arg; - r->pkt_id = pkt_id; - break; - } - } - return r; -} - - -/** - * Append request to pending request queue - * @param tail Pointer to request queue tail pointer - * @param r Request to append - */ -static void -mqtt_append_request(struct mqtt_request_t **tail, struct mqtt_request_t *r) -{ - struct mqtt_request_t *head = NULL; - s16_t time_before = 0; - struct mqtt_request_t *iter; - - LWIP_ASSERT("mqtt_append_request: tail != NULL", tail != NULL); - - /* Iterate trough queue to find head, and count total timeout time */ - for (iter = *tail; iter != NULL; iter = iter->next) { - time_before += iter->timeout_diff; - head = iter; - } - - LWIP_ASSERT("mqtt_append_request: time_before <= MQTT_REQ_TIMEOUT", time_before <= MQTT_REQ_TIMEOUT); - r->timeout_diff = MQTT_REQ_TIMEOUT - time_before; - if (head == NULL) { - *tail = r; - } else { - head->next = r; - } -} - - -/** - * Delete request item - * @param r Request item to delete - */ -static void -mqtt_delete_request(struct mqtt_request_t *r) -{ - if (r != NULL) { - r->next = r; - } -} - -/** - * Remove a request item with a specific packet identifier from request queue - * @param tail Pointer to request queue tail pointer - * @param pkt_id Packet identifier of request to take - * @return Request item if found, NULL if not - */ -static struct mqtt_request_t * -mqtt_take_request(struct mqtt_request_t **tail, u16_t pkt_id) -{ - struct mqtt_request_t *iter = NULL, *prev = NULL; - LWIP_ASSERT("mqtt_take_request: tail != NULL", tail != NULL); - /* Search all request for pkt_id */ - for (iter = *tail; iter != NULL; iter = iter->next) { - if (iter->pkt_id == pkt_id) { - break; - } - prev = iter; - } - - /* If request was found */ - if (iter != NULL) { - /* unchain */ - if (prev == NULL) { - *tail= iter->next; - } else { - prev->next = iter->next; - } - /* If exists, add remaining timeout time for the request to next */ - if (iter->next != NULL) { - iter->next->timeout_diff += iter->timeout_diff; - } - iter->next = NULL; - } - return iter; -} - -/** - * Handle requests timeout - * @param tail Pointer to request queue tail pointer - * @param t Time since last call in seconds - */ -static void -mqtt_request_time_elapsed(struct mqtt_request_t **tail, u8_t t) -{ - struct mqtt_request_t *r = *tail; - LWIP_ASSERT("mqtt_request_time_elapsed: tail != NULL", tail != NULL); - while (t > 0 && r != NULL) { - if (t >= r->timeout_diff) { - t -= (u8_t)r->timeout_diff; - /* Unchain */ - *tail = r->next; - /* Notify upper layer about timeout */ - if (r->cb != NULL) { - r->cb(r->arg, ERR_TIMEOUT); - } - mqtt_delete_request(r); - /* Tail might be be modified in callback, so re-read it in every iteration */ - r = *(struct mqtt_request_t * const volatile *)tail; - } else { - r->timeout_diff -= t; - t = 0; - } - } -} - -/** - * Free all request items - * @param tail Pointer to request queue tail pointer - */ -static void -mqtt_clear_requests(struct mqtt_request_t **tail) -{ - struct mqtt_request_t *iter, *next; - LWIP_ASSERT("mqtt_clear_requests: tail != NULL", tail != NULL); - for (iter = *tail; iter != NULL; iter = next) { - next = iter->next; - mqtt_delete_request(iter); - } - *tail = NULL; -} -/** - * Initialize all request items - * @param r_objs Pointer to request objects - */ -static void -mqtt_init_requests(struct mqtt_request_t *r_objs) -{ - u8_t n; - LWIP_ASSERT("mqtt_init_requests: r_objs != NULL", r_objs != NULL); - for (n = 0; n < MQTT_REQ_MAX_IN_FLIGHT; n++) { - /* Item pointing to itself indicates unused */ - r_objs[n].next = &r_objs[n]; - } -} - -/*--------------------------------------------------------------------------------------------------------------------- */ -/* Output message build helpers */ - - -static void -mqtt_output_append_u8(struct mqtt_ringbuf_t *rb, u8_t value) -{ - mqtt_ringbuf_put(rb, value); -} - -static -void mqtt_output_append_u16(struct mqtt_ringbuf_t *rb, u16_t value) -{ - mqtt_ringbuf_put(rb, value >> 8); - mqtt_ringbuf_put(rb, value & 0xff); -} - -static void -mqtt_output_append_buf(struct mqtt_ringbuf_t *rb, const void *data, u16_t length) -{ - u16_t n; - for (n = 0; n < length; n++) { - mqtt_ringbuf_put(rb, ((const u8_t *)data)[n]); - } -} - -static void -mqtt_output_append_string(struct mqtt_ringbuf_t *rb, const char *str, u16_t length) -{ - u16_t n; - mqtt_ringbuf_put(rb, length >> 8); - mqtt_ringbuf_put(rb, length & 0xff); - for (n = 0; n < length; n++) { - mqtt_ringbuf_put(rb, str[n]); - } -} - -/** - * Append fixed header - * @param rb Output ring buffer - * @param msg_type see enum mqtt_message_type - * @param dup MQTT DUP flag - * @param qos MQTT QoS field - * @param retain MQTT retain flag - * @param r_length Remaining length after fixed header - */ - -static void -mqtt_output_append_fixed_header(struct mqtt_ringbuf_t *rb, u8_t msg_type, u8_t dup, - u8_t qos, u8_t retain, u16_t r_length) -{ - /* Start with control byte */ - mqtt_output_append_u8(rb, (((msg_type & 0x0f) << 4) | ((dup & 1) << 3) | ((qos & 3) << 1) | (retain & 1))); - /* Encode remaining length field */ - do { - mqtt_output_append_u8(rb, (r_length & 0x7f) | (r_length >= 128 ? 0x80 : 0)); - r_length >>= 7; - } while (r_length > 0); -} - - -/** - * Check output buffer space - * @param rb Output ring buffer - * @param r_length Remaining length after fixed header - * @return 1 if message will fit, 0 if not enough buffer space - */ -static u8_t -mqtt_output_check_space(struct mqtt_ringbuf_t *rb, u16_t r_length) -{ - /* Start with length of type byte + remaining length */ - u16_t total_len = 1 + r_length; - - LWIP_ASSERT("mqtt_output_check_space: rb != NULL", rb != NULL); - - /* Calculate number of required bytes to contain the remaining bytes field and add to total*/ - do { - total_len++; - r_length >>= 7; - } while (r_length > 0); - - return (total_len <= mqtt_ringbuf_free(rb)); -} - - -/** - * Close connection to server - * @param client MQTT client - * @param reason Reason for disconnection - */ -static void -mqtt_close(mqtt_client_t *client, mqtt_connection_status_t reason) -{ - LWIP_ASSERT("mqtt_close: client != NULL", client != NULL); - - /* Bring down TCP connection if not already done */ - if (client->conn != NULL) { - err_t res; - tcp_recv(client->conn, NULL); - tcp_err(client->conn, NULL); - tcp_sent(client->conn, NULL); - res = tcp_close(client->conn); - if (res != ERR_OK) { - tcp_abort(client->conn); - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_close: Close err=%s\n", lwip_strerr(res))); - } - client->conn = NULL; - } - - /* Remove all pending requests */ - mqtt_clear_requests(&client->pend_req_queue); - /* Stop cyclic timer */ - sys_untimeout(mqtt_cyclic_timer, client); - - /* Notify upper layer of disconnection if changed state */ - if (client->conn_state != TCP_DISCONNECTED) { - - client->conn_state = TCP_DISCONNECTED; - if (client->connect_cb != NULL) { - client->connect_cb(client, client->connect_arg, reason); - } - } -} - - -/** - * Interval timer, called every MQTT_CYCLIC_TIMER_INTERVAL seconds in MQTT_CONNECTING and MQTT_CONNECTED states - * @param arg MQTT client - */ -static void -mqtt_cyclic_timer(void *arg) -{ - u8_t restart_timer = 1; - mqtt_client_t *client = (mqtt_client_t *)arg; - LWIP_ASSERT("mqtt_cyclic_timer: client != NULL", client != NULL); - - if (client->conn_state == MQTT_CONNECTING) { - client->cyclic_tick++; - if ((client->cyclic_tick * MQTT_CYCLIC_TIMER_INTERVAL) >= MQTT_CONNECT_TIMOUT) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_cyclic_timer: CONNECT attempt to server timed out\n")); - /* Disconnect TCP */ - mqtt_close(client, MQTT_CONNECT_TIMEOUT); - restart_timer = 0; - } - } else if (client->conn_state == MQTT_CONNECTED) { - /* Handle timeout for pending requests */ - mqtt_request_time_elapsed(&client->pend_req_queue, MQTT_CYCLIC_TIMER_INTERVAL); - - /* keep_alive > 0 means keep alive functionality shall be used */ - if (client->keep_alive > 0) { - - client->server_watchdog++; - /* If reception from server has been idle for 1.5*keep_alive time, server is considered unresponsive */ - if ((client->server_watchdog * MQTT_CYCLIC_TIMER_INTERVAL) > (client->keep_alive + client->keep_alive/2)) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_cyclic_timer: Server incoming keep-alive timeout\n")); - mqtt_close(client, MQTT_CONNECT_TIMEOUT); - restart_timer = 0; - } - - /* If time for a keep alive message to be sent, transmission has been idle for keep_alive time */ - if ((client->cyclic_tick * MQTT_CYCLIC_TIMER_INTERVAL) >= client->keep_alive) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_cyclic_timer: Sending keep-alive message to server\n")); - if (mqtt_output_check_space(&client->output, 0) != 0) { - mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_PINGREQ, 0, 0, 0, 0); - client->cyclic_tick = 0; - } - } else { - client->cyclic_tick++; - } - } - } else { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_cyclic_timer: Timer should not be running in state %d\n", client->conn_state)); - restart_timer = 0; - } - if (restart_timer) { - sys_timeout(MQTT_CYCLIC_TIMER_INTERVAL*1000, mqtt_cyclic_timer, arg); - } -} - - -/** - * Send PUBACK, PUBREC or PUBREL response message - * @param client MQTT client - * @param msg PUBACK, PUBREC or PUBREL - * @param pkt_id Packet identifier - * @param qos QoS value - * @return ERR_OK if successful, ERR_MEM if out of memory - */ -static err_t -pub_ack_rec_rel_response(mqtt_client_t *client, u8_t msg, u16_t pkt_id, u8_t qos) -{ - err_t err = ERR_OK; - if (mqtt_output_check_space(&client->output, 2)) { - mqtt_output_append_fixed_header(&client->output, msg, 0, qos, 0, 2); - mqtt_output_append_u16(&client->output, pkt_id); - mqtt_output_send(&client->output, client->conn); - } else { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("pub_ack_rec_rel_response: OOM creating response: %s with pkt_id: %d\n", - mqtt_msg_type_to_str(msg), pkt_id)); - err = ERR_MEM; - } - return err; -} - -/** - * Subscribe response from server - * @param r Matching request - * @param result Result code from server - */ -static void -mqtt_incomming_suback(struct mqtt_request_t *r, u8_t result) -{ - if (r->cb != NULL) { - r->cb(r->arg, result < 3 ? ERR_OK : ERR_ABRT); - } -} - - -/** - * Complete MQTT message received or buffer full - * @param client MQTT client - * @param fixed_hdr_idx header index - * @param length length received part - * @param remaining_length Remaining length of complete message - */ -static mqtt_connection_status_t - mqtt_message_received(mqtt_client_t *client, u8_t fixed_hdr_idx, u16_t length, u32_t remaining_length) -{ - mqtt_connection_status_t res = MQTT_CONNECT_ACCEPTED; - - u8_t *var_hdr_payload = client->rx_buffer + fixed_hdr_idx; - - /* Control packet type */ - u8_t pkt_type = MQTT_CTL_PACKET_TYPE(client->rx_buffer[0]); - u16_t pkt_id = 0; - - if (pkt_type == MQTT_MSG_TYPE_CONNACK) { - if (client->conn_state == MQTT_CONNECTING) { - /* Get result code from CONNACK */ - res = (mqtt_connection_status_t)var_hdr_payload[1]; - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_message_received: Connect response code %d\n", res)); - if (res == MQTT_CONNECT_ACCEPTED) { - /* Reset cyclic_tick when changing to connected state */ - client->cyclic_tick = 0; - client->conn_state = MQTT_CONNECTED; - /* Notify upper layer */ - if (client->connect_cb != 0) { - client->connect_cb(client, client->connect_arg, res); - } - } - } else { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_message_received: Received CONNACK in connected state\n")); - } - } else if (pkt_type == MQTT_MSG_TYPE_PINGRESP) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,( "mqtt_message_received: Received PINGRESP from server\n")); - - } else if (pkt_type == MQTT_MSG_TYPE_PUBLISH) { - u16_t payload_offset = 0; - u16_t payload_length = length; - u8_t qos = MQTT_CTL_PACKET_QOS(client->rx_buffer[0]); - - if (client->msg_idx <= MQTT_VAR_HEADER_BUFFER_LEN) { - /* Should have topic and pkt id*/ - uint8_t *topic; - uint16_t after_topic; - u8_t bkp; - u16_t topic_len = var_hdr_payload[0]; - topic_len = (topic_len << 8) + (u16_t)(var_hdr_payload[1]); - - topic = var_hdr_payload + 2; - after_topic = 2 + topic_len; - /* Check length, add one byte even for QoS 0 so that zero termination will fit */ - if ((after_topic + (qos? 2 : 1)) > length) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_message_received: Receive buffer can not fit topic + pkt_id\n")); - goto out_disconnect; - } - - /* id for QoS 1 and 2 */ - if (qos > 0) { - client->inpub_pkt_id = ((u16_t)var_hdr_payload[after_topic] << 8) + (u16_t)var_hdr_payload[after_topic + 1]; - after_topic += 2; - } else { - client->inpub_pkt_id = 0; - } - /* Take backup of byte after topic */ - bkp = topic[topic_len]; - /* Zero terminate string */ - topic[topic_len] = 0; - /* Payload data remaining in receive buffer */ - payload_length = length - after_topic; - payload_offset = after_topic; - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_incomming_publish: Received message with QoS %d at topic: %s, payload length %d\n", - qos, topic, remaining_length + payload_length)); - if (client->pub_cb != NULL) { - client->pub_cb(client->inpub_arg, (const char *)topic, remaining_length + payload_length); - } - /* Restore byte after topic */ - topic[topic_len] = bkp; - } - if (payload_length > 0 || remaining_length == 0) { - client->data_cb(client->inpub_arg, var_hdr_payload + payload_offset, payload_length, remaining_length == 0 ? MQTT_DATA_FLAG_LAST : 0); - /* Reply if QoS > 0 */ - if (remaining_length == 0 && qos > 0) { - /* Send PUBACK for QoS 1 or PUBREC for QoS 2 */ - u8_t resp_msg = (qos == 1) ? MQTT_MSG_TYPE_PUBACK : MQTT_MSG_TYPE_PUBREC; - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_incomming_publish: Sending publish response: %s with pkt_id: %d\n", - mqtt_msg_type_to_str(resp_msg), client->inpub_pkt_id)); - pub_ack_rec_rel_response(client, resp_msg, client->inpub_pkt_id, 0); - } - } - } else { - /* Get packet identifier */ - pkt_id = (u16_t)var_hdr_payload[0] << 8; - pkt_id |= (u16_t)var_hdr_payload[1]; - if (pkt_id == 0) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_message_received: Got message with illegal packet identifier: 0\n")); - goto out_disconnect; - } - if (pkt_type == MQTT_MSG_TYPE_PUBREC) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_message_received: PUBREC, sending PUBREL with pkt_id: %d\n",pkt_id)); - pub_ack_rec_rel_response(client, MQTT_MSG_TYPE_PUBREL, pkt_id, 1); - - } else if (pkt_type == MQTT_MSG_TYPE_PUBREL) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_message_received: PUBREL, sending PUBCOMP response with pkt_id: %d\n",pkt_id)); - pub_ack_rec_rel_response(client, MQTT_MSG_TYPE_PUBCOMP, pkt_id, 0); - - } else if (pkt_type == MQTT_MSG_TYPE_SUBACK || pkt_type == MQTT_MSG_TYPE_UNSUBACK || - pkt_type == MQTT_MSG_TYPE_PUBCOMP || pkt_type == MQTT_MSG_TYPE_PUBACK) { - struct mqtt_request_t *r = mqtt_take_request(&client->pend_req_queue, pkt_id); - if (r != NULL) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_message_received: %s response with id %d\n", mqtt_msg_type_to_str(pkt_type), pkt_id)); - if (pkt_type == MQTT_MSG_TYPE_SUBACK) { - if (length < 3) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_message_received: To small SUBACK packet\n")); - goto out_disconnect; - } else { - mqtt_incomming_suback(r, var_hdr_payload[2]); - } - } else if (r->cb != NULL) { - r->cb(r->arg, ERR_OK); - } - mqtt_delete_request(r); - } else { - LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received %s reply, with wrong pkt_id: %d\n", mqtt_msg_type_to_str(pkt_type), pkt_id)); - } - } else { - LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received unknown message type: %d\n", pkt_type)); - goto out_disconnect; - } - } - return res; -out_disconnect: - return MQTT_CONNECT_DISCONNECTED; -} - - -/** - * MQTT incoming message parser - * @param client MQTT client - * @param p PBUF chain of received data - * @return Connection status - */ -static mqtt_connection_status_t -mqtt_parse_incoming(mqtt_client_t *client, struct pbuf *p) -{ - u16_t in_offset = 0; - u32_t msg_rem_len = 0; - u8_t fixed_hdr_idx = 0; - u8_t b = 0; - - while (p->tot_len > in_offset) { - if ((fixed_hdr_idx < 2) || ((b & 0x80) != 0)) { - - if (fixed_hdr_idx < client->msg_idx) { - b = client->rx_buffer[fixed_hdr_idx]; - } else { - b = pbuf_get_at(p, in_offset++); - client->rx_buffer[client->msg_idx++] = b; - } - fixed_hdr_idx++; - - if (fixed_hdr_idx >= 2) { - msg_rem_len |= (u32_t)(b & 0x7f) << ((fixed_hdr_idx - 2) * 7); - if ((b & 0x80) == 0) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_parse_incoming: Remaining length after fixed header: %d\n", msg_rem_len)); - if (msg_rem_len == 0) { - /* Complete message with no extra headers of payload received */ - mqtt_message_received(client, fixed_hdr_idx, 0, 0); - client->msg_idx = 0; - fixed_hdr_idx = 0; - } else { - /* Bytes remaining in message */ - msg_rem_len = (msg_rem_len + fixed_hdr_idx) - client->msg_idx; - } - } - } - } else { - u16_t cpy_len, cpy_start, buffer_space; - - cpy_start = (client->msg_idx - fixed_hdr_idx) % (MQTT_VAR_HEADER_BUFFER_LEN - fixed_hdr_idx) + fixed_hdr_idx; - - /* Allow to copy the lesser one of available length in input data or bytes remaining in message */ - cpy_len = (u16_t)LWIP_MIN((u16_t)(p->tot_len - in_offset), msg_rem_len); - - /* Limit to available space in buffer */ - buffer_space = MQTT_VAR_HEADER_BUFFER_LEN - cpy_start; - if (cpy_len > buffer_space) { - cpy_len = buffer_space; - } - pbuf_copy_partial(p, client->rx_buffer+cpy_start, cpy_len, in_offset); - - /* Advance get and put indexes */ - client->msg_idx += cpy_len; - in_offset += cpy_len; - msg_rem_len -= cpy_len; - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_parse_incoming: msg_idx: %d, cpy_len: %d, remaining %d\n", client->msg_idx, cpy_len, msg_rem_len)); - if (msg_rem_len == 0 || cpy_len == buffer_space) { - /* Whole message received or buffer is full */ - mqtt_connection_status_t res = mqtt_message_received(client, fixed_hdr_idx, (cpy_start + cpy_len) - fixed_hdr_idx, msg_rem_len); - if (res != MQTT_CONNECT_ACCEPTED) { - return res; - } - if (msg_rem_len == 0) { - /* Reset parser state */ - client->msg_idx = 0; - /* msg_tot_len = 0; */ - fixed_hdr_idx = 0; - } - } - } - } - return MQTT_CONNECT_ACCEPTED; -} - - -/** - * TCP received callback function. @see tcp_recv_fn - * @param arg MQTT client - * @param p PBUF chain of received data - * @param err Passed as return value if not ERR_OK - * @return ERR_OK or err passed into callback - */ -static err_t -mqtt_tcp_recv_cb(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - mqtt_client_t *client = (mqtt_client_t *)arg; - LWIP_ASSERT("mqtt_tcp_recv_cb: client != NULL", client != NULL); - LWIP_ASSERT("mqtt_tcp_recv_cb: client->conn == pcb", client->conn == pcb); - - if (p == NULL) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_tcp_recv_cb: Recv pbuf=NULL, remote has closed connection\n")); - mqtt_close(client, MQTT_CONNECT_DISCONNECTED); - } else { - mqtt_connection_status_t res; - if (err != ERR_OK) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_tcp_recv_cb: Recv err=%d\n", err)); - pbuf_free(p); - return err; - } - - /* Tell remote that data has been received */ - tcp_recved(pcb, p->tot_len); - res = mqtt_parse_incoming(client, p); - pbuf_free(p); - - if (res != MQTT_CONNECT_ACCEPTED) { - mqtt_close(client, res); - } - /* If keep alive functionality is used */ - if (client->keep_alive != 0) { - /* Reset server alive watchdog */ - client->server_watchdog = 0; - } - - } - return ERR_OK; -} - - -/** - * TCP data sent callback function. @see tcp_sent_fn - * @param arg MQTT client - * @param tpcb TCP connection handle - * @param len Number of bytes sent - * @return ERR_OK - */ -static err_t -mqtt_tcp_sent_cb(void *arg, struct tcp_pcb *tpcb, u16_t len) -{ - mqtt_client_t *client = (mqtt_client_t *)arg; - - LWIP_UNUSED_ARG(tpcb); - LWIP_UNUSED_ARG(len); - - if (client->conn_state == MQTT_CONNECTED) { - struct mqtt_request_t *r; - - /* Reset keep-alive send timer and server watchdog */ - client->cyclic_tick = 0; - client->server_watchdog = 0; - /* QoS 0 publish has no response from server, so call its callbacks here */ - while ((r = mqtt_take_request(&client->pend_req_queue, 0)) != NULL) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_tcp_sent_cb: Calling QoS 0 publish complete callback\n")); - if (r->cb != NULL) { - r->cb(r->arg, ERR_OK); - } - mqtt_delete_request(r); - } - /* Try send any remaining buffers from output queue */ - mqtt_output_send(&client->output, client->conn); - } - return ERR_OK; -} - -/** - * TCP error callback function. @see tcp_err_fn - * @param arg MQTT client - * @param err Error encountered - */ -static void -mqtt_tcp_err_cb(void *arg, err_t err) -{ - mqtt_client_t *client = (mqtt_client_t *)arg; - LWIP_UNUSED_ARG(err); /* only used for debug output */ - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_tcp_err_cb: TCP error callback: error %d, arg: %p\n", err, arg)); - LWIP_ASSERT("mqtt_tcp_err_cb: client != NULL", client != NULL); - /* Set conn to null before calling close as pcb is already deallocated*/ - client->conn = 0; - mqtt_close(client, MQTT_CONNECT_DISCONNECTED); -} - -/** - * TCP poll callback function. @see tcp_poll_fn - * @param arg MQTT client - * @param tpcb TCP connection handle - * @return err ERR_OK - */ -static err_t -mqtt_tcp_poll_cb(void *arg, struct tcp_pcb *tpcb) -{ - mqtt_client_t *client = (mqtt_client_t *)arg; - if (client->conn_state == MQTT_CONNECTED) { - /* Try send any remaining buffers from output queue */ - mqtt_output_send(&client->output, tpcb); - } - return ERR_OK; -} - -/** - * TCP connect callback function. @see tcp_connected_fn - * @param arg MQTT client - * @param err Always ERR_OK, mqtt_tcp_err_cb is called in case of error - * @return ERR_OK - */ -static err_t -mqtt_tcp_connect_cb(void *arg, struct tcp_pcb *tpcb, err_t err) -{ - mqtt_client_t* client = (mqtt_client_t *)arg; - - if (err != ERR_OK) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_tcp_connect_cb: TCP connect error %d\n", err)); - return err; - } - - /* Initiate receiver state */ - client->msg_idx = 0; - - /* Setup TCP callbacks */ - tcp_recv(tpcb, mqtt_tcp_recv_cb); - tcp_sent(tpcb, mqtt_tcp_sent_cb); - tcp_poll(tpcb, mqtt_tcp_poll_cb, 2); - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_tcp_connect_cb: TCP connection established to server\n")); - /* Enter MQTT connect state */ - client->conn_state = MQTT_CONNECTING; - - /* Start cyclic timer */ - sys_timeout(MQTT_CYCLIC_TIMER_INTERVAL*1000, mqtt_cyclic_timer, client); - client->cyclic_tick = 0; - - /* Start transmission from output queue, connect message is the first one out*/ - mqtt_output_send(&client->output, client->conn); - - return ERR_OK; -} - - - -/*---------------------------------------------------------------------------------------------------- */ -/* Public API */ - - -/** - * @ingroup mqtt - * MQTT publish function. - * @param client MQTT client - * @param topic Publish topic string - * @param payload Data to publish (NULL is allowed) - * @param payload_length: Length of payload (0 is allowed) - * @param qos Quality of service, 0 1 or 2 - * @param retain MQTT retain flag - * @param cb Callback to call when publish is complete or has timed out - * @param arg User supplied argument to publish callback - * @return ERR_OK if successful - * ERR_CONN if client is disconnected - * ERR_MEM if short on memory - */ -err_t -mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain, - mqtt_request_cb_t cb, void *arg) -{ - struct mqtt_request_t *r; - u16_t pkt_id; - size_t topic_strlen; - size_t total_len; - u16_t topic_len; - u16_t remaining_length; - - LWIP_ASSERT("mqtt_publish: client != NULL", client); - LWIP_ASSERT("mqtt_publish: topic != NULL", topic); - LWIP_ERROR("mqtt_publish: TCP disconnected", (client->conn_state != TCP_DISCONNECTED), return ERR_CONN); - - topic_strlen = strlen(topic); - LWIP_ERROR("mqtt_publish: topic length overflow", (topic_strlen <= (0xFFFF - 2)), return ERR_ARG); - topic_len = (u16_t)topic_strlen; - total_len = 2 + topic_len + payload_length; - LWIP_ERROR("mqtt_publish: total length overflow", (total_len <= 0xFFFF), return ERR_ARG); - remaining_length = (u16_t)total_len; - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_publish: Publish with payload length %d to topic \"%s\"\n", payload_length, topic)); - - if (qos > 0) { - remaining_length += 2; - /* Generate pkt_id id for QoS1 and 2 */ - pkt_id = msg_generate_packet_id(client); - } else { - /* Use reserved value pkt_id 0 for QoS 0 in request handle */ - pkt_id = 0; - } - - r = mqtt_create_request(client->req_list, pkt_id, cb, arg); - if (r == NULL) { - return ERR_MEM; - } - - if (mqtt_output_check_space(&client->output, remaining_length) == 0) { - mqtt_delete_request(r); - return ERR_MEM; - } - /* Append fixed header */ - mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_PUBLISH, 0, qos, retain, remaining_length); - - /* Append Topic */ - mqtt_output_append_string(&client->output, topic, topic_len); - - /* Append packet if for QoS 1 and 2*/ - if (qos > 0) { - mqtt_output_append_u16(&client->output, pkt_id); - } - - /* Append optional publish payload */ - if ((payload != NULL) && (payload_length > 0)) { - mqtt_output_append_buf(&client->output, payload, payload_length); - } - - mqtt_append_request(&client->pend_req_queue, r); - mqtt_output_send(&client->output, client->conn); - return ERR_OK; -} - - -/** - * @ingroup mqtt - * MQTT subscribe/unsubscribe function. - * @param client MQTT client - * @param topic topic to subscribe to - * @param qos Quality of service, 0 1 or 2 (only used for subscribe) - * @param cb Callback to call when subscribe/unsubscribe reponse is received - * @param arg User supplied argument to publish callback - * @param sub 1 for subscribe, 0 for unsubscribe - * @return ERR_OK if successful, @see err_t enum for other results - */ -err_t -mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub) -{ - size_t topic_strlen; - size_t total_len; - u16_t topic_len; - u16_t remaining_length; - u16_t pkt_id; - struct mqtt_request_t *r; - - LWIP_ASSERT("mqtt_sub_unsub: client != NULL", client); - LWIP_ASSERT("mqtt_sub_unsub: topic != NULL", topic); - - topic_strlen = strlen(topic); - LWIP_ERROR("mqtt_sub_unsub: topic length overflow", (topic_strlen <= (0xFFFF - 2)), return ERR_ARG); - topic_len = (u16_t)topic_strlen; - /* Topic string, pkt_id, qos for subscribe */ - total_len = topic_len + 2 + 2 + (sub != 0); - LWIP_ERROR("mqtt_sub_unsub: total length overflow", (total_len <= 0xFFFF), return ERR_ARG); - remaining_length = (u16_t)total_len; - - LWIP_ASSERT("mqtt_sub_unsub: qos < 3", qos < 3); - if (client->conn_state == TCP_DISCONNECTED) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_sub_unsub: Can not (un)subscribe in disconnected state\n")); - return ERR_CONN; - } - - pkt_id = msg_generate_packet_id(client); - r = mqtt_create_request(client->req_list, pkt_id, cb, arg); - if (r == NULL) { - return ERR_MEM; - } - - if (mqtt_output_check_space(&client->output, remaining_length) == 0) { - mqtt_delete_request(r); - return ERR_MEM; - } - - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_sub_unsub: Client (un)subscribe to topic \"%s\", id: %d\n", topic, pkt_id)); - - mqtt_output_append_fixed_header(&client->output, sub ? MQTT_MSG_TYPE_SUBSCRIBE : MQTT_MSG_TYPE_UNSUBSCRIBE, 0, 1, 0, remaining_length); - /* Packet id */ - mqtt_output_append_u16(&client->output, pkt_id); - /* Topic */ - mqtt_output_append_string(&client->output, topic, topic_len); - /* QoS */ - if (sub != 0) { - mqtt_output_append_u8(&client->output, LWIP_MIN(qos, 2)); - } - - mqtt_append_request(&client->pend_req_queue, r); - mqtt_output_send(&client->output, client->conn); - return ERR_OK; -} - - -/** - * @ingroup mqtt - * Set callback to handle incoming publish requests from server - * @param client MQTT client - * @param pub_cb Callback invoked when publish starts, contain topic and total length of payload - * @param data_cb Callback for each fragment of payload that arrives - * @param arg User supplied argument to both callbacks - */ -void -mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t pub_cb, - mqtt_incoming_data_cb_t data_cb, void *arg) -{ - LWIP_ASSERT("mqtt_set_inpub_callback: client != NULL", client != NULL); - client->data_cb = data_cb; - client->pub_cb = pub_cb; - client->inpub_arg = arg; -} - -/** - * @ingroup mqtt - * Create a new MQTT client instance - * @return Pointer to instance on success, NULL otherwise - */ -mqtt_client_t * -mqtt_client_new(void) -{ - mqtt_client_t *client = (mqtt_client_t *)mem_malloc(sizeof(mqtt_client_t)); - if (client != NULL) { - memset(client, 0, sizeof(mqtt_client_t)); - } - return client; -} - - -/** - * @ingroup mqtt - * Connect to MQTT server - * @param client MQTT client - * @param ip_addr Server IP - * @param port Server port - * @param cb Connection state change callback - * @param arg User supplied argument to connection callback - * @param client_info Client identification and connection options - * @return ERR_OK if successful, @see err_t enum for other results - */ -err_t -mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ip_addr, u16_t port, mqtt_connection_cb_t cb, void *arg, - const struct mqtt_connect_client_info_t *client_info) -{ - err_t err; - size_t len; - u16_t client_id_length; - /* Length is the sum of 2+"MQTT", protocol level, flags and keep alive */ - u16_t remaining_length = 2 + 4 + 1 + 1 + 2; - u8_t flags = 0, will_topic_len = 0, will_msg_len = 0; - - LWIP_ASSERT("mqtt_client_connect: client != NULL", client != NULL); - LWIP_ASSERT("mqtt_client_connect: ip_addr != NULL", ip_addr != NULL); - LWIP_ASSERT("mqtt_client_connect: client_info != NULL", client_info != NULL); - LWIP_ASSERT("mqtt_client_connect: client_info->client_id != NULL", client_info->client_id != NULL); - - if (client->conn_state != TCP_DISCONNECTED) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_client_connect: Already connected\n")); - return ERR_ISCONN; - } - - /* Wipe clean */ - memset(client, 0, sizeof(mqtt_client_t)); - client->connect_arg = arg; - client->connect_cb = cb; - client->keep_alive = client_info->keep_alive; - mqtt_init_requests(client->req_list); - - /* Build connect message */ - if (client_info->will_topic != NULL && client_info->will_msg != NULL) { - flags |= MQTT_CONNECT_FLAG_WILL; - flags |= (client_info->will_qos & 3) << 3; - if (client_info->will_retain) { - flags |= MQTT_CONNECT_FLAG_WILL_RETAIN; - } - len = strlen(client_info->will_topic); - LWIP_ERROR("mqtt_client_connect: client_info->will_topic length overflow", len <= 0xFF, return ERR_VAL); - LWIP_ERROR("mqtt_client_connect: client_info->will_topic length must be > 0", len > 0, return ERR_VAL); - will_topic_len = (u8_t)len; - len = strlen(client_info->will_msg); - LWIP_ERROR("mqtt_client_connect: client_info->will_msg length overflow", len <= 0xFF, return ERR_VAL); - will_msg_len = (u8_t)len; - len = remaining_length + 2 + will_topic_len + 2 + will_msg_len; - LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); - remaining_length = (u16_t)len; - } - - /* Don't complicate things, always connect using clean session */ - flags |= MQTT_CONNECT_FLAG_CLEAN_SESSION; - - len = strlen(client_info->client_id); - LWIP_ERROR("mqtt_client_connect: client_info->client_id length overflow", len <= 0xFFFF, return ERR_VAL); - client_id_length = (u16_t)len; - len = remaining_length + 2 + client_id_length; - LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); - remaining_length = (u16_t)len; - - if (mqtt_output_check_space(&client->output, remaining_length) == 0) { - return ERR_MEM; - } - - client->conn = tcp_new(); - if (client->conn == NULL) { - return ERR_MEM; - } - - /* Set arg pointer for callbacks */ - tcp_arg(client->conn, client); - /* Any local address, pick random local port number */ - err = tcp_bind(client->conn, IP_ADDR_ANY, 0); - if (err != ERR_OK) { - LWIP_DEBUGF(MQTT_DEBUG_WARN,("mqtt_client_connect: Error binding to local ip/port, %d\n", err)); - goto tcp_fail; - } - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_client_connect: Connecting to host: %s at port:%"U16_F"\n", ipaddr_ntoa(ip_addr), port)); - - /* Connect to server */ - err = tcp_connect(client->conn, ip_addr, port, mqtt_tcp_connect_cb); - if (err != ERR_OK) { - LWIP_DEBUGF(MQTT_DEBUG_TRACE,("mqtt_client_connect: Error connecting to remote ip/port, %d\n", err)); - goto tcp_fail; - } - /* Set error callback */ - tcp_err(client->conn, mqtt_tcp_err_cb); - client->conn_state = TCP_CONNECTING; - - /* Append fixed header */ - mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_CONNECT, 0, 0, 0, remaining_length); - /* Append Protocol string */ - mqtt_output_append_string(&client->output, "MQTT", 4); - /* Append Protocol level */ - mqtt_output_append_u8(&client->output, 4); - /* Append connect flags */ - mqtt_output_append_u8(&client->output, flags); - /* Append keep-alive */ - mqtt_output_append_u16(&client->output, client_info->keep_alive); - /* Append client id */ - mqtt_output_append_string(&client->output, client_info->client_id, client_id_length); - /* Append will message if used */ - if ((flags & MQTT_CONNECT_FLAG_WILL) != 0) { - mqtt_output_append_string(&client->output, client_info->will_topic, will_topic_len); - mqtt_output_append_string(&client->output, client_info->will_msg, will_msg_len); - } - return ERR_OK; - -tcp_fail: - tcp_abort(client->conn); - client->conn = NULL; - return err; -} - - -/** - * @ingroup mqtt - * Disconnect from MQTT server - * @param client MQTT client - */ -void -mqtt_disconnect(mqtt_client_t *client) -{ - LWIP_ASSERT("mqtt_disconnect: client != NULL", client); - /* If connection in not already closed */ - if (client->conn_state != TCP_DISCONNECTED) { - /* Set conn_state before calling mqtt_close to prevent callback from being called */ - client->conn_state = TCP_DISCONNECTED; - mqtt_close(client, (mqtt_connection_status_t)0); - } -} - -/** - * @ingroup mqtt - * Check connection with server - * @param client MQTT client - * @return 1 if connected to server, 0 otherwise - */ -u8_t -mqtt_client_is_connected(mqtt_client_t *client) -{ - LWIP_ASSERT("mqtt_client_is_connected: client != NULL", client); - return client->conn_state == MQTT_CONNECTED; -} - -#endif /* LWIP_TCP && LWIP_CALLBACK_API */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/netbiosns/netbiosns.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/netbiosns/netbiosns.c deleted file mode 100644 index 2dfbe6590107ffd65520aacf84baf396b89156ea..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/netbiosns/netbiosns.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - * @file - * NetBIOS name service responder - */ - -/** - * @defgroup netbiosns NETBIOS responder - * @ingroup apps - * - * This is an example implementation of a NetBIOS name server. - * It responds to name queries for a configurable name. - * Name resolving is not supported. - * - * Note that the device doesn't broadcast it's own name so can't - * detect duplicate names! - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/apps/netbiosns.h" - -#if LWIP_IPV4 && LWIP_UDP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/udp.h" -#include "lwip/netif.h" - -#include - -/** default port number for "NetBIOS Name service */ -#define NETBIOS_PORT 137 - -/** size of a NetBIOS name */ -#define NETBIOS_NAME_LEN 16 - -/** The Time-To-Live for NetBIOS name responds (in seconds) - * Default is 300000 seconds (3 days, 11 hours, 20 minutes) */ -#define NETBIOS_NAME_TTL 300000u - -/** NetBIOS header flags */ -#define NETB_HFLAG_RESPONSE 0x8000U -#define NETB_HFLAG_OPCODE 0x7800U -#define NETB_HFLAG_OPCODE_NAME_QUERY 0x0000U -#define NETB_HFLAG_AUTHORATIVE 0x0400U -#define NETB_HFLAG_TRUNCATED 0x0200U -#define NETB_HFLAG_RECURS_DESIRED 0x0100U -#define NETB_HFLAG_RECURS_AVAILABLE 0x0080U -#define NETB_HFLAG_BROADCAST 0x0010U -#define NETB_HFLAG_REPLYCODE 0x0008U -#define NETB_HFLAG_REPLYCODE_NOERROR 0x0000U - -/** NetBIOS name flags */ -#define NETB_NFLAG_UNIQUE 0x8000U -#define NETB_NFLAG_NODETYPE 0x6000U -#define NETB_NFLAG_NODETYPE_HNODE 0x6000U -#define NETB_NFLAG_NODETYPE_MNODE 0x4000U -#define NETB_NFLAG_NODETYPE_PNODE 0x2000U -#define NETB_NFLAG_NODETYPE_BNODE 0x0000U - -/** NetBIOS message header */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct netbios_hdr { - PACK_STRUCT_FIELD(u16_t trans_id); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FIELD(u16_t questions); - PACK_STRUCT_FIELD(u16_t answerRRs); - PACK_STRUCT_FIELD(u16_t authorityRRs); - PACK_STRUCT_FIELD(u16_t additionalRRs); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** NetBIOS message name part */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct netbios_name_hdr { - PACK_STRUCT_FLD_8(u8_t nametype); - PACK_STRUCT_FLD_8(u8_t encname[(NETBIOS_NAME_LEN*2)+1]); - PACK_STRUCT_FIELD(u16_t type); - PACK_STRUCT_FIELD(u16_t cls); - PACK_STRUCT_FIELD(u32_t ttl); - PACK_STRUCT_FIELD(u16_t datalen); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FLD_S(ip4_addr_p_t addr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** NetBIOS message */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct netbios_resp -{ - struct netbios_hdr resp_hdr; - struct netbios_name_hdr resp_name; -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef NETBIOS_LWIP_NAME -#define NETBIOS_LOCAL_NAME NETBIOS_LWIP_NAME -#else -static char netbiosns_local_name[NETBIOS_NAME_LEN]; -#define NETBIOS_LOCAL_NAME netbiosns_local_name -#endif - -struct udp_pcb *netbiosns_pcb; - -/** Decode a NetBIOS name (from packet to string) */ -static int -netbiosns_name_decode(char *name_enc, char *name_dec, int name_dec_len) -{ - char *pname; - char cname; - char cnbname; - int idx = 0; - - LWIP_UNUSED_ARG(name_dec_len); - - /* Start decoding netbios name. */ - pname = name_enc; - for (;;) { - /* Every two characters of the first level-encoded name - * turn into one character in the decoded name. */ - cname = *pname; - if (cname == '\0') - break; /* no more characters */ - if (cname == '.') - break; /* scope ID follows */ - if (cname < 'A' || cname > 'Z') { - /* Not legal. */ - return -1; - } - cname -= 'A'; - cnbname = cname << 4; - pname++; - - cname = *pname; - if (cname == '\0' || cname == '.') { - /* No more characters in the name - but we're in - * the middle of a pair. Not legal. */ - return -1; - } - if (cname < 'A' || cname > 'Z') { - /* Not legal. */ - return -1; - } - cname -= 'A'; - cnbname |= cname; - pname++; - - /* Do we have room to store the character? */ - if (idx < NETBIOS_NAME_LEN) { - /* Yes - store the character. */ - name_dec[idx++] = (cnbname!=' '?cnbname:'\0'); - } - } - - return 0; -} - -#if 0 /* function currently unused */ -/** Encode a NetBIOS name (from string to packet) - currently unused because - we don't ask for names. */ -static int -netbiosns_name_encode(char *name_enc, char *name_dec, int name_dec_len) -{ - char *pname; - char cname; - unsigned char ucname; - int idx = 0; - - /* Start encoding netbios name. */ - pname = name_enc; - - for (;;) { - /* Every two characters of the first level-encoded name - * turn into one character in the decoded name. */ - cname = *pname; - if (cname == '\0') - break; /* no more characters */ - if (cname == '.') - break; /* scope ID follows */ - if ((cname < 'A' || cname > 'Z') && (cname < '0' || cname > '9')) { - /* Not legal. */ - return -1; - } - - /* Do we have room to store the character? */ - if (idx >= name_dec_len) { - return -1; - } - - /* Yes - store the character. */ - ucname = cname; - name_dec[idx++] = ('A'+((ucname>>4) & 0x0F)); - name_dec[idx++] = ('A'+( ucname & 0x0F)); - pname++; - } - - /* Fill with "space" coding */ - for (;idx < name_dec_len - 1;) { - name_dec[idx++] = 'C'; - name_dec[idx++] = 'A'; - } - - /* Terminate string */ - name_dec[idx] = '\0'; - - return 0; -} -#endif /* 0 */ - -/** NetBIOS Name service recv callback */ -static void -netbiosns_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - LWIP_UNUSED_ARG(arg); - - /* if packet is valid */ - if (p != NULL) { - char netbios_name[NETBIOS_NAME_LEN+1]; - struct netbios_hdr* netbios_hdr = (struct netbios_hdr*)p->payload; - struct netbios_name_hdr* netbios_name_hdr = (struct netbios_name_hdr*)(netbios_hdr+1); - - /* we only answer if we got a default interface */ - if (netif_default != NULL) { - /* @todo: do we need to check answerRRs/authorityRRs/additionalRRs? */ - /* if the packet is a NetBIOS name query question */ - if (((netbios_hdr->flags & PP_NTOHS(NETB_HFLAG_OPCODE)) == PP_NTOHS(NETB_HFLAG_OPCODE_NAME_QUERY)) && - ((netbios_hdr->flags & PP_NTOHS(NETB_HFLAG_RESPONSE)) == 0) && - (netbios_hdr->questions == PP_NTOHS(1))) { - /* decode the NetBIOS name */ - netbiosns_name_decode((char*)(netbios_name_hdr->encname), netbios_name, sizeof(netbios_name)); - /* if the packet is for us */ - if (lwip_strnicmp(netbios_name, NETBIOS_LOCAL_NAME, sizeof(NETBIOS_LOCAL_NAME)) == 0) { - struct pbuf *q; - struct netbios_resp *resp; - - q = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct netbios_resp), PBUF_RAM); - if (q != NULL) { - resp = (struct netbios_resp*)q->payload; - - /* prepare NetBIOS header response */ - resp->resp_hdr.trans_id = netbios_hdr->trans_id; - resp->resp_hdr.flags = PP_HTONS(NETB_HFLAG_RESPONSE | - NETB_HFLAG_OPCODE_NAME_QUERY | - NETB_HFLAG_AUTHORATIVE | - NETB_HFLAG_RECURS_DESIRED); - resp->resp_hdr.questions = 0; - resp->resp_hdr.answerRRs = PP_HTONS(1); - resp->resp_hdr.authorityRRs = 0; - resp->resp_hdr.additionalRRs = 0; - - /* prepare NetBIOS header datas */ - MEMCPY( resp->resp_name.encname, netbios_name_hdr->encname, sizeof(netbios_name_hdr->encname)); - resp->resp_name.nametype = netbios_name_hdr->nametype; - resp->resp_name.type = netbios_name_hdr->type; - resp->resp_name.cls = netbios_name_hdr->cls; - resp->resp_name.ttl = PP_HTONL(NETBIOS_NAME_TTL); - resp->resp_name.datalen = PP_HTONS(sizeof(resp->resp_name.flags)+sizeof(resp->resp_name.addr)); - resp->resp_name.flags = PP_HTONS(NETB_NFLAG_NODETYPE_BNODE); - ip4_addr_copy(resp->resp_name.addr, *netif_ip4_addr(netif_default)); - - /* send the NetBIOS response */ - udp_sendto(upcb, q, addr, port); - - /* free the "reference" pbuf */ - pbuf_free(q); - } - } - } - } - /* free the pbuf */ - pbuf_free(p); - } -} - -/** - * @ingroup netbiosns - * Init netbios responder - */ -void -netbiosns_init(void) -{ -#ifdef NETBIOS_LWIP_NAME - LWIP_ASSERT("NetBIOS name is too long!", strlen(NETBIOS_LWIP_NAME) < NETBIOS_NAME_LEN); -#endif - - netbiosns_pcb = udp_new_ip_type(IPADDR_TYPE_ANY); - if (netbiosns_pcb != NULL) { - /* we have to be allowed to send broadcast packets! */ - ip_set_option(netbiosns_pcb, SOF_BROADCAST); - udp_bind(netbiosns_pcb, IP_ANY_TYPE, NETBIOS_PORT); - udp_recv(netbiosns_pcb, netbiosns_recv, netbiosns_pcb); - } -} - -#ifndef NETBIOS_LWIP_NAME -/** - * @ingroup netbiosns - * Set netbios name. ATTENTION: the hostname must be less than 15 characters! - */ -void -netbiosns_set_name(const char* hostname) -{ - size_t copy_len = strlen(hostname); - LWIP_ASSERT("NetBIOS name is too long!", copy_len < NETBIOS_NAME_LEN); - if (copy_len >= NETBIOS_NAME_LEN) { - copy_len = NETBIOS_NAME_LEN - 1; - } - MEMCPY(netbiosns_local_name, hostname, copy_len + 1); -} -#endif - -/** - * @ingroup netbiosns - * Stop netbios responder - */ -void -netbiosns_stop(void) -{ - if (netbiosns_pcb != NULL) { - udp_remove(netbiosns_pcb); - netbiosns_pcb = NULL; - } -} - -#endif /* LWIP_IPV4 && LWIP_UDP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/ping/ping.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/ping/ping.c deleted file mode 100644 index 6726381d8dc19d6160eef6390ef76198ae209810..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/ping/ping.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * File : ping.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2012-04-01 Bernard first version - * 2018-01-25 armink Add ping domain name - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -/** - * PING_DEBUG: Enable debugging for PING. - */ -#ifndef PING_DEBUG -#define PING_DEBUG LWIP_DBG_ON -#endif - -/** ping receive timeout - in milliseconds */ -#define PING_RCV_TIMEO 2000 -/** ping delay - in milliseconds */ -#define PING_DELAY 1000 - -/** ping identifier - must fit on a u16_t */ -#ifndef PING_ID -#define PING_ID 0xAFAF -#endif - -/** ping additional data size to include in the packet */ -#ifndef PING_DATA_SIZE -#define PING_DATA_SIZE 32 -#endif - -/* ping variables */ -static u16_t ping_seq_num; -struct _ip_addr -{ - uint8_t addr0, addr1, addr2, addr3; -}; - -/** Prepare a echo ICMP request */ -static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len) -{ - size_t i; - size_t data_len = len - sizeof(struct icmp_echo_hdr); - - ICMPH_TYPE_SET(iecho, ICMP_ECHO); - ICMPH_CODE_SET(iecho, 0); - iecho->chksum = 0; - iecho->id = PING_ID; - iecho->seqno = htons(++ping_seq_num); - - /* fill the additional data buffer with some data */ - for (i = 0; i < data_len; i++) - { - ((char*) iecho)[sizeof(struct icmp_echo_hdr) + i] = (char) i; - } - - iecho->chksum = inet_chksum(iecho, len); -} - -/* Ping using the socket ip */ -static err_t ping_send(int s, ip_addr_t *addr, int size) -{ - int err; - struct icmp_echo_hdr *iecho; - struct sockaddr_in to; - int ping_size = sizeof(struct icmp_echo_hdr) + size; - LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff); - - iecho = (struct icmp_echo_hdr *)mem_malloc((mem_size_t)ping_size); - if (!iecho) { - return ERR_MEM; - } - ping_prepare_echo(iecho, (u16_t) ping_size); - - to.sin_len = sizeof(to); - to.sin_family = AF_INET; - to.sin_addr.s_addr = addr->addr; - - err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*) &to, sizeof(to)); - mem_free(iecho); - - return (err == ping_size ? ERR_OK : ERR_VAL); -} - -static int ping_recv(int s, int *ttl) -{ - char buf[64]; - int fromlen = sizeof(struct sockaddr_in), len; - struct sockaddr_in from; - struct ip_hdr *iphdr; - struct icmp_echo_hdr *iecho; - - while ((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*) &from, (socklen_t*) &fromlen)) > 0) - { - if (len >= (int)(sizeof(struct ip_hdr) + sizeof(struct icmp_echo_hdr))) - { - iphdr = (struct ip_hdr *) buf; - iecho = (struct icmp_echo_hdr *) (buf + (IPH_HL(iphdr) * 4)); - if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num))) - { - *ttl = iphdr->_ttl; - return len; - } - } - } - - return len; -} - -int ping(char* target_name, uint32_t times, size_t size) -{ - int s, ttl=0, recv_len; - struct timeval timeout = { PING_RCV_TIMEO / 1000, PING_RCV_TIMEO % 1000 }; - ip_addr_t target_addr; - uint32_t send_times; - uint32_t recv_start_tick; - struct addrinfo hint, *res = NULL; - struct sockaddr_in *h = NULL; - struct in_addr ina; - - send_times = 0; - ping_seq_num = 0; - - if (size == 0) - { - size = PING_DATA_SIZE; - } - - memset(&hint, 0, sizeof(hint)); - /* convert URL to IP */ - if (lwip_getaddrinfo(target_name, NULL, &hint, &res) != 0) - { - LWIP_DEBUGF( PING_DEBUG, ("ping: unknown host\n")); - return -1; - } - memcpy(&h, &res->ai_addr, sizeof(struct sockaddr_in *)); - memcpy(&ina, &h->sin_addr, sizeof(ina)); - lwip_freeaddrinfo(res); - if (inet_aton(inet_ntoa(ina), &target_addr) == 0) - { - LWIP_DEBUGF( PING_DEBUG, ("ping: unknown host\n")); - return -1; - } - /* new a socket */ - if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) - { - LWIP_DEBUGF( PING_DEBUG, ("ping: create socket failed\n")); - return -1; - } - - lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(struct timeval)); - - while (1) - { - if (ping_send(s, &target_addr, size) == ERR_OK) - { - recv_start_tick = sys_now(); - - if ((recv_len = ping_recv(s, &ttl)) >= 0) - { - LWIP_DEBUGF( PING_DEBUG, ("%d bytes from %s icmp_seq=%d ttl=%d time=%d ticks\n", recv_len, inet_ntoa(ina), send_times, - ttl, sys_now() - recv_start_tick)); - } - else - { - LWIP_DEBUGF( PING_DEBUG, ("From %s icmp_seq=%d timeout\n", inet_ntoa(ina), send_times)); - } - } - else - { - LWIP_DEBUGF( PING_DEBUG, ("Send %s - error\n", inet_ntoa(ina))); - } - - send_times++; - if (send_times >= times) - { - /* send ping times reached, stop */ - break; - } - sys_msleep(PING_DELAY); - } - - lwip_close(s); - - return 0; -} -// eof diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.c deleted file mode 100644 index f35b760462b0bfd9b00ffdb2e285395be0d1c89b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.c +++ /dev/null @@ -1,749 +0,0 @@ -/** - * @file - * Abstract Syntax Notation One (ISO 8824, 8825) encoding - * - * @todo not optimised (yet), favor correctness over speed, favor speed over size - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "snmp_asn1.h" - -#define PBUF_OP_EXEC(code) \ - if ((code) != ERR_OK) { \ - return ERR_BUF; \ - } - -/** - * Encodes a TLV into a pbuf stream. - * - * @param pbuf_stream points to a pbuf stream - * @param tlv TLV to encode - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_ans1_enc_tlv(struct snmp_pbuf_stream* pbuf_stream, struct snmp_asn1_tlv* tlv) -{ - u8_t data; - u8_t length_bytes_required; - - /* write type */ - if ((tlv->type & SNMP_ASN1_DATATYPE_MASK) == SNMP_ASN1_DATATYPE_EXTENDED) { - /* extended format is not used by SNMP so we do not accept those values */ - return ERR_ARG; - } - if (tlv->type_len != 0) { - /* any other value as auto is not accepted for type (we always use one byte because extended syntax is prohibited) */ - return ERR_ARG; - } - - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, tlv->type)); - tlv->type_len = 1; - - /* write length */ - if (tlv->value_len <= 127) { - length_bytes_required = 1; - } else if (tlv->value_len <= 255) { - length_bytes_required = 2; - } else { - length_bytes_required = 3; - } - - /* check for forced min length */ - if (tlv->length_len > 0) { - if (tlv->length_len < length_bytes_required) { - /* unable to code requested length in requested number of bytes */ - return ERR_ARG; - } - - length_bytes_required = tlv->length_len; - } else { - tlv->length_len = length_bytes_required; - } - - if (length_bytes_required > 1) { - /* multi byte representation required */ - length_bytes_required--; - data = 0x80 | length_bytes_required; /* extended length definition, 1 length byte follows */ - - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, data)); - - while (length_bytes_required > 1) { - if (length_bytes_required == 2) { - /* append high byte */ - data = (u8_t)(tlv->value_len >> 8); - } else { - /* append leading 0x00 */ - data = 0x00; - } - - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, data)); - length_bytes_required--; - } - } - - /* append low byte */ - data = (u8_t)(tlv->value_len & 0xFF); - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, data)); - - return ERR_OK; -} - -/** - * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg. - * - * @param pbuf_stream points to a pbuf stream - * @param raw_len raw data length - * @param raw points raw data - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_raw(struct snmp_pbuf_stream* pbuf_stream, const u8_t *raw, u16_t raw_len) -{ - PBUF_OP_EXEC(snmp_pbuf_stream_writebuf(pbuf_stream, raw, raw_len)); - - return ERR_OK; -} - -/** - * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg. - * - * @param pbuf_stream points to a pbuf stream - * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) - * @param value is the host order u32_t value to be encoded - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - * - * @see snmp_asn1_enc_u32t_cnt() - */ -err_t -snmp_asn1_enc_u32t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, u32_t value) -{ - if (octets_needed > 5) { - return ERR_ARG; - } - if (octets_needed == 5) { - /* not enough bits in 'value' add leading 0x00 */ - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, 0x00)); - octets_needed--; - } - - while (octets_needed > 1) { - octets_needed--; - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)(value >> (octets_needed << 3)))); - } - - /* (only) one least significant octet */ - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)value)); - - return ERR_OK; -} - -/** - * Encodes u64_t (counter64) into a pbuf chained ASN1 msg. - * - * @param pbuf_stream points to a pbuf stream - * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) - * @param value is the host order u32_t value to be encoded - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - * - * @see snmp_asn1_enc_u64t_cnt() - */ -err_t -snmp_asn1_enc_u64t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, const u32_t* value) -{ - if (octets_needed > 9) { - return ERR_ARG; - } - if (octets_needed == 9) { - /* not enough bits in 'value' add leading 0x00 */ - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, 0x00)); - octets_needed--; - } - - while (octets_needed > 4) { - octets_needed--; - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)(*value >> ((octets_needed-4) << 3)))); - } - - /* skip to low u32 */ - value++; - - while (octets_needed > 1) { - octets_needed--; - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)(*value >> (octets_needed << 3)))); - } - - /* always write at least one octet (also in case of value == 0) */ - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)(*value))); - - return ERR_OK; -} - -/** - * Encodes s32_t integer into a pbuf chained ASN1 msg. - * - * @param pbuf_stream points to a pbuf stream - * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt()) - * @param value is the host order s32_t value to be encoded - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - * - * @see snmp_asn1_enc_s32t_cnt() - */ -err_t -snmp_asn1_enc_s32t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, s32_t value) -{ - while (octets_needed > 1) { - octets_needed--; - - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)(value >> (octets_needed << 3)))); - } - - /* (only) one least significant octet */ - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)value)); - - return ERR_OK; -} - -/** - * Encodes object identifier into a pbuf chained ASN1 msg. - * - * @param pbuf_stream points to a pbuf stream - * @param oid points to object identifier array - * @param oid_len object identifier array length - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_oid(struct snmp_pbuf_stream* pbuf_stream, const u32_t *oid, u16_t oid_len) -{ - if (oid_len > 1) { - /* write compressed first two sub id's */ - u32_t compressed_byte = ((oid[0] * 40) + oid[1]); - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)compressed_byte)); - oid_len -= 2; - oid += 2; - } else { - /* @bug: allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression?? */ - /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */ - return ERR_ARG; - } - - while (oid_len > 0) { - u32_t sub_id; - u8_t shift, tail; - - oid_len--; - sub_id = *oid; - tail = 0; - shift = 28; - while (shift > 0) { - u8_t code; - - code = (u8_t)(sub_id >> shift); - if ((code != 0) || (tail != 0)) { - tail = 1; - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, code | 0x80)); - } - shift -= 7; - } - PBUF_OP_EXEC(snmp_pbuf_stream_write(pbuf_stream, (u8_t)sub_id & 0x7F)); - - /* proceed to next sub-identifier */ - oid++; - } - return ERR_OK; -} - -/** - * Returns octet count for length. - * - * @param length parameter length - * @param octets_needed points to the return value - */ -void -snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed) -{ - if (length < 0x80U) { - *octets_needed = 1; - } else if (length < 0x100U) { - *octets_needed = 2; - } else { - *octets_needed = 3; - } -} - -/** - * Returns octet count for an u32_t. - * - * @param value value to be encoded - * @param octets_needed points to the return value - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -void -snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed) -{ - if (value < 0x80UL) { - *octets_needed = 1; - } else if (value < 0x8000UL) { - *octets_needed = 2; - } else if (value < 0x800000UL) { - *octets_needed = 3; - } else if (value < 0x80000000UL) { - *octets_needed = 4; - } else { - *octets_needed = 5; - } -} - -/** - * Returns octet count for an u64_t. - * - * @param value value to be encoded - * @param octets_needed points to the return value - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -void -snmp_asn1_enc_u64t_cnt(const u32_t *value, u16_t *octets_needed) -{ - /* check if high u32 is 0 */ - if (*value == 0x00) { - /* only low u32 is important */ - value++; - snmp_asn1_enc_u32t_cnt(*value, octets_needed); - } else { - /* low u32 does not matter for length determination */ - snmp_asn1_enc_u32t_cnt(*value, octets_needed); - *octets_needed = *octets_needed + 4; /* add the 4 bytes of low u32 */ - } -} - -/** - * Returns octet count for an s32_t. - * - * @param value value to be encoded - * @param octets_needed points to the return value - * - * @note ASN coded integers are _always_ signed. - */ -void -snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed) -{ - if (value < 0) { - value = ~value; - } - if (value < 0x80L) { - *octets_needed = 1; - } else if (value < 0x8000L) { - *octets_needed = 2; - } else if (value < 0x800000L) { - *octets_needed = 3; - } else { - *octets_needed = 4; - } -} - -/** - * Returns octet count for an object identifier. - * - * @param oid points to object identifier array - * @param oid_len object identifier array length - * @param octets_needed points to the return value - */ -void -snmp_asn1_enc_oid_cnt(const u32_t *oid, u16_t oid_len, u16_t *octets_needed) -{ - u32_t sub_id; - - *octets_needed = 0; - if (oid_len > 1) { - /* compressed prefix in one octet */ - (*octets_needed)++; - oid_len -= 2; - oid += 2; - } - while (oid_len > 0) { - oid_len--; - sub_id = *oid; - - sub_id >>= 7; - (*octets_needed)++; - while (sub_id > 0) { - sub_id >>= 7; - (*octets_needed)++; - } - oid++; - } -} - -/** - * Decodes a TLV from a pbuf stream. - * - * @param pbuf_stream points to a pbuf stream - * @param tlv returns decoded TLV - * @return ERR_OK if successful, ERR_VAL if we can't decode - */ -err_t -snmp_asn1_dec_tlv(struct snmp_pbuf_stream* pbuf_stream, struct snmp_asn1_tlv* tlv) -{ - u8_t data; - - /* decode type first */ - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - tlv->type = data; - - if ((tlv->type & SNMP_ASN1_DATATYPE_MASK) == SNMP_ASN1_DATATYPE_EXTENDED) { - /* extended format is not used by SNMP so we do not accept those values */ - return ERR_VAL; - } - tlv->type_len = 1; - - /* now, decode length */ - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - - if (data < 0x80) { /* short form */ - tlv->length_len = 1; - tlv->value_len = data; - } else if (data > 0x80) { /* long form */ - u8_t length_bytes = data - 0x80; - tlv->length_len = length_bytes + 1; /* this byte + defined number of length bytes following */ - tlv->value_len = 0; - - while (length_bytes > 0) { - /* we only support up to u16.maxvalue-1 (2 bytes) but have to accept leading zero bytes */ - if (tlv->value_len > 0xFF) { - return ERR_VAL; - } - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - tlv->value_len <<= 8; - tlv->value_len |= data; - - /* take care for special value used for indefinite length */ - if (tlv->value_len == 0xFFFF) { - return ERR_VAL; - } - - length_bytes--; - } - } else { /* data == 0x80 indefinite length form */ - /* (not allowed for SNMP; RFC 1157, 3.2.2) */ - return ERR_VAL; - } - - return ERR_OK; -} - -/** - * Decodes positive integer (counter, gauge, timeticks) into u32_t. - * - * @param pbuf_stream points to a pbuf stream - * @param len length of the coded integer field - * @param value return host order integer - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) decode - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -err_t -snmp_asn1_dec_u32t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t *value) -{ - u8_t data; - - if ((len > 0) && (len <= 5)) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - - /* expecting sign bit to be zero, only unsigned please! */ - if (((len == 5) && (data == 0x00)) || ((len < 5) && ((data & 0x80) == 0))) { - *value = data; - len--; - - while (len > 0) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - - *value <<= 8; - *value |= data; - } - - return ERR_OK; - } - } - - return ERR_VAL; -} - -/** - * Decodes large positive integer (counter64) into 2x u32_t. - * - * @param pbuf_stream points to a pbuf stream - * @param len length of the coded integer field - * @param value return host order integer - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) decode - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -err_t -snmp_asn1_dec_u64t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t *value) -{ - u8_t data; - - if (len <= 4) { - /* high u32 is 0 */ - *value = 0; - /* directly skip to low u32 */ - value++; - } - - if ((len > 0) && (len <= 9)) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - - /* expecting sign bit to be zero, only unsigned please! */ - if (((len == 9) && (data == 0x00)) || ((len < 9) && ((data & 0x80) == 0))) { - *value = data; - len--; - - while (len > 0) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - - if (len == 4) { - /* skip to low u32 */ - value++; - *value = 0; - } else { - *value <<= 8; - } - - *value |= data; - len--; - } - - return ERR_OK; - } - } - - return ERR_VAL; -} - -/** - * Decodes integer into s32_t. - * - * @param pbuf_stream points to a pbuf stream - * @param len length of the coded integer field - * @param value return host order integer - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) decode - * - * @note ASN coded integers are _always_ signed! - */ -err_t -snmp_asn1_dec_s32t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, s32_t *value) -{ -#if BYTE_ORDER == LITTLE_ENDIAN - u8_t *lsb_ptr = (u8_t*)value; -#endif -#if BYTE_ORDER == BIG_ENDIAN - u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1; -#endif - u8_t sign; - u8_t data; - - if ((len > 0) && (len < 5)) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - - if (data & 0x80) { - /* negative, start from -1 */ - *value = -1; - sign = 1; - *lsb_ptr &= data; - } else { - /* positive, start from 0 */ - *value = 0; - sign = 0; - *lsb_ptr |= data; - } - - /* OR/AND octets with value */ - while (len > 0) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - -#if BYTE_ORDER == LITTLE_ENDIAN - *value <<= 8; -#endif -#if BYTE_ORDER == BIG_ENDIAN - *value >>= 8; -#endif - - if (sign) { - *lsb_ptr |= 255; - *lsb_ptr &= data; - } else { - *lsb_ptr |= data; - } - } - - return ERR_OK; - } - - return ERR_VAL; -} - -/** - * Decodes object identifier from incoming message into array of u32_t. - * - * @param pbuf_stream points to a pbuf stream - * @param len length of the coded object identifier - * @param oid return decoded object identifier - * @param oid_len return decoded object identifier length - * @param oid_max_len size of oid buffer - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_oid(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t* oid, u8_t* oid_len, u8_t oid_max_len) -{ - u32_t *oid_ptr; - u8_t data; - - *oid_len = 0; - oid_ptr = oid; - if (len > 0) { - if (oid_max_len < 2) { - return ERR_MEM; - } - - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - - /* first compressed octet */ - if (data == 0x2B) { - /* (most) common case 1.3 (iso.org) */ - *oid_ptr = 1; - oid_ptr++; - *oid_ptr = 3; - oid_ptr++; - } else if (data < 40) { - *oid_ptr = 0; - oid_ptr++; - *oid_ptr = data; - oid_ptr++; - } else if (data < 80) { - *oid_ptr = 1; - oid_ptr++; - *oid_ptr = data - 40; - oid_ptr++; - } else { - *oid_ptr = 2; - oid_ptr++; - *oid_ptr = data - 80; - oid_ptr++; - } - *oid_len = 2; - } else { - /* accepting zero length identifiers e.g. for getnext operation. uncommon but valid */ - return ERR_OK; - } - - while ((len > 0) && (*oid_len < oid_max_len)) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - - if ((data & 0x80) == 0x00) { - /* sub-identifier uses single octet */ - *oid_ptr = data; - } else { - /* sub-identifier uses multiple octets */ - u32_t sub_id = (data & ~0x80); - while ((len > 0) && ((data & 0x80) != 0)) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, &data)); - len--; - - sub_id = (sub_id << 7) + (data & ~0x80); - } - - if ((data & 0x80) != 0) { - /* "more bytes following" bit still set at end of len */ - return ERR_VAL; - } - *oid_ptr = sub_id; - } - oid_ptr++; - (*oid_len)++; - } - - if (len > 0) { - /* OID to long to fit in our buffer */ - return ERR_MEM; - } - - return ERR_OK; -} - -/** - * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding) - * from incoming message into array. - * - * @param pbuf_stream points to a pbuf stream - * @param len length of the coded raw data (zero is valid, e.g. empty string!) - * @param buf return raw bytes - * @param buf_len returns length of the raw return value - * @param buf_max_len buffer size - * @return ERR_OK if successful, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_raw(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u8_t *buf, u16_t* buf_len, u16_t buf_max_len) -{ - if (len > buf_max_len) { - /* not enough dst space */ - return ERR_MEM; - } - *buf_len = len; - - while (len > 0) { - PBUF_OP_EXEC(snmp_pbuf_stream_read(pbuf_stream, buf)); - buf++; - len--; - } - - return ERR_OK; -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.h deleted file mode 100644 index ec50d8c9e3cb67e4843e73dfe65b811c1873ca51..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_asn1.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file - * Abstract Syntax Notation One (ISO 8824, 8825) codec. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel - * Elias Oenal - */ - -#ifndef LWIP_HDR_APPS_SNMP_ASN1_H -#define LWIP_HDR_APPS_SNMP_ASN1_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP - -#include "lwip/err.h" -#include "lwip/apps/snmp_core.h" -#include "snmp_pbuf_stream.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define SNMP_ASN1_TLV_INDEFINITE_LENGTH 0x80 - -#define SNMP_ASN1_CLASS_MASK 0xC0 -#define SNMP_ASN1_CONTENTTYPE_MASK 0x20 -#define SNMP_ASN1_DATATYPE_MASK 0x1F -#define SNMP_ASN1_DATATYPE_EXTENDED 0x1F /* DataType indicating that datatype is encoded in following bytes */ - -/* context specific (SNMP) tags (from SNMP spec. RFC1157) */ -#define SNMP_ASN1_CONTEXT_PDU_GET_REQ 0 -#define SNMP_ASN1_CONTEXT_PDU_GET_NEXT_REQ 1 -#define SNMP_ASN1_CONTEXT_PDU_GET_RESP 2 -#define SNMP_ASN1_CONTEXT_PDU_SET_REQ 3 -#define SNMP_ASN1_CONTEXT_PDU_TRAP 4 -#define SNMP_ASN1_CONTEXT_PDU_GET_BULK_REQ 5 - -#define SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_OBJECT 0 -#define SNMP_ASN1_CONTEXT_VARBIND_END_OF_MIB_VIEW 2 - -struct snmp_asn1_tlv -{ - u8_t type; /* only U8 because extended types are not specified by SNMP */ - u8_t type_len; /* encoded length of 'type' field (normally 1) */ - u8_t length_len; /* indicates how many bytes are required to encode the 'value_len' field */ - u16_t value_len; /* encoded length of the value */ -}; -#define SNMP_ASN1_TLV_HDR_LENGTH(tlv) ((tlv).type_len + (tlv).length_len) -#define SNMP_ASN1_TLV_LENGTH(tlv) ((tlv).type_len + (tlv).length_len + (tlv).value_len) -#define SNMP_ASN1_SET_TLV_PARAMS(tlv, type_, length_len_, value_len_) do { (tlv).type = (type_); (tlv).type_len = 0; (tlv).length_len = (length_len_); (tlv).value_len = (value_len_); } while (0); - -err_t snmp_asn1_dec_tlv(struct snmp_pbuf_stream* pbuf_stream, struct snmp_asn1_tlv* tlv); -err_t snmp_asn1_dec_u32t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t *value); -err_t snmp_asn1_dec_u64t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t *value); -err_t snmp_asn1_dec_s32t(struct snmp_pbuf_stream *pbuf_stream, u16_t len, s32_t *value); -err_t snmp_asn1_dec_oid(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u32_t* oid, u8_t* oid_len, u8_t oid_max_len); -err_t snmp_asn1_dec_raw(struct snmp_pbuf_stream *pbuf_stream, u16_t len, u8_t *buf, u16_t* buf_len, u16_t buf_max_len); - -err_t snmp_ans1_enc_tlv(struct snmp_pbuf_stream* pbuf_stream, struct snmp_asn1_tlv* tlv); - -void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); -void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); -void snmp_asn1_enc_u64t_cnt(const u32_t *value, u16_t *octets_needed); -void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); -void snmp_asn1_enc_oid_cnt(const u32_t *oid, u16_t oid_len, u16_t *octets_needed); -err_t snmp_asn1_enc_oid(struct snmp_pbuf_stream* pbuf_stream, const u32_t *oid, u16_t oid_len); -err_t snmp_asn1_enc_s32t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, s32_t value); -err_t snmp_asn1_enc_u32t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, u32_t value); -err_t snmp_asn1_enc_u64t(struct snmp_pbuf_stream* pbuf_stream, u16_t octets_needed, const u32_t* value); -err_t snmp_asn1_enc_raw(struct snmp_pbuf_stream* pbuf_stream, const u8_t *raw, u16_t raw_len); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* LWIP_HDR_APPS_SNMP_ASN1_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core.c deleted file mode 100644 index c0418336171cc4ae07efbd2140f04db27a4d3bf3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core.c +++ /dev/null @@ -1,1349 +0,0 @@ -/** - * @file - * MIB tree access/construction functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel -*/ - -/** - * @defgroup snmp SNMPv2c agent - * @ingroup apps - * SNMPv2c compatible agent\n - * There is also a MIB compiler and a MIB viewer in lwIP contrib repository - * (lwip-contrib/apps/LwipMibCompiler).\n - * The agent implements the most important MIB2 MIBs including IPv6 support - * (interfaces, UDP, TCP, SNMP, ICMP, SYSTEM). IP MIB is an older version - * whithout IPv6 statistics (TODO).\n - * Rewritten by Martin Hentschel and - * Dirk Ziegelmeier \n - * Work on SNMPv3 has started, but is not finished.\n - * - * 0 Agent Capabilities - * ==================== - * - * Features: - * --------- - * - SNMPv2c support. - * - Low RAM usage - no memory pools, stack only. - * - MIB2 implementation is separated from SNMP stack. - * - Support for multiple MIBs (snmp_set_mibs() call) - e.g. for private MIB. - * - Simple and generic API for MIB implementation. - * - Comfortable node types and helper functions for scalar arrays and tables. - * - Counter64, bit and truthvalue datatype support. - * - Callbacks for SNMP writes e.g. to implement persistency. - * - Runs on two APIs: RAW and netconn. - * - Async API is gone - the stack now supports netconn API instead, - * so blocking operations can be done in MIB calls. - * SNMP runs in a worker thread when netconn API is used. - * - Simplified thread sync support for MIBs - useful when MIBs - * need to access variables shared with other threads where no locking is - * possible. Used in MIB2 to access lwIP stats from lwIP thread. - * - * MIB compiler (code generator): - * ------------------------------ - * - Provided in lwIP contrib repository. - * - Written in C#. MIB viewer used Windows Forms. - * - Developed on Windows with Visual Studio 2010. - * - Can be compiled and used on all platforms with http://www.monodevelop.com/. - * - Based on a heavily modified version of of SharpSnmpLib (a4bd05c6afb4) - * (https://sharpsnmplib.codeplex.com/SourceControl/network/forks/Nemo157/MIBParserUpdate). - * - MIB parser, C file generation framework and LWIP code generation are cleanly - * separated, which means the code may be useful as a base for code generation - * of other SNMP agents. - * - * Notes: - * ------ - * - Stack and MIB compiler were used to implement a Profinet device. - * Compiled/implemented MIBs: LLDP-MIB, LLDP-EXT-DOT3-MIB, LLDP-EXT-PNO-MIB. - * - * SNMPv1 per RFC1157 and SNMPv2c per RFC 3416 - * ------------------------------------------- - * Note the S in SNMP stands for "Simple". Note that "Simple" is - * relative. SNMP is simple compared to the complex ISO network - * management protocols CMIP (Common Management Information Protocol) - * and CMOT (CMip Over Tcp). - * - * MIB II - * ------ - * The standard lwIP stack management information base. - * This is a required MIB, so this is always enabled. - * The groups EGP, CMOT and transmission are disabled by default. - * - * Most mib-2 objects are not writable except: - * sysName, sysLocation, sysContact, snmpEnableAuthenTraps. - * Writing to or changing the ARP and IP address and route - * tables is not possible. - * - * Note lwIP has a very limited notion of IP routing. It currently - * doen't have a route table and doesn't have a notion of the U,G,H flags. - * Instead lwIP uses the interface list with only one default interface - * acting as a single gateway interface (G) for the default route. - * - * The agent returns a "virtual table" with the default route 0.0.0.0 - * for the default interface and network routes (no H) for each - * network interface in the netif_list. - * All routes are considered to be up (U). - * - * Loading additional MIBs - * ----------------------- - * MIBs can only be added in compile-time, not in run-time. - * - * - * 1 Building the Agent - * ==================== - * First of all you'll need to add the following define - * to your local lwipopts.h: - * \#define LWIP_SNMP 1 - * - * and add the source files your makefile. - * - * Note you'll might need to adapt you network driver to update - * the mib2 variables for your interface. - * - * 2 Running the Agent - * =================== - * The following function calls must be made in your program to - * actually get the SNMP agent running. - * - * Before starting the agent you should supply pointers - * for sysContact, sysLocation, and snmpEnableAuthenTraps. - * You can do this by calling - * - * - snmp_mib2_set_syscontact() - * - snmp_mib2_set_syslocation() - * - snmp_set_auth_traps_enabled() - * - * You can register a callback which is called on successful write access: - * snmp_set_write_callback(). - * - * Additionally you may want to set - * - * - snmp_mib2_set_sysdescr() - * - snmp_set_device_enterprise_oid() - * - snmp_mib2_set_sysname() - * - * Also before starting the agent you need to setup - * one or more trap destinations using these calls: - * - * - snmp_trap_dst_enable() - * - snmp_trap_dst_ip_set() - * - * If you need more than MIB2, set the MIBs you want to use - * by snmp_set_mibs(). - * - * Finally, enable the agent by calling snmp_init() - * - * @defgroup snmp_core Core - * @ingroup snmp - * - * @defgroup snmp_traps Traps - * @ingroup snmp - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "snmp_core_priv.h" -#include "lwip/netif.h" -#include - - -#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0)) - #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_SNMP) - #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif - -struct snmp_statistics snmp_stats; -static const struct snmp_obj_id snmp_device_enterprise_oid_default = {SNMP_DEVICE_ENTERPRISE_OID_LEN, SNMP_DEVICE_ENTERPRISE_OID}; -static const struct snmp_obj_id* snmp_device_enterprise_oid = &snmp_device_enterprise_oid_default; - -const u32_t snmp_zero_dot_zero_values[] = { 0, 0 }; -const struct snmp_obj_id_const_ref snmp_zero_dot_zero = { LWIP_ARRAYSIZE(snmp_zero_dot_zero_values), snmp_zero_dot_zero_values }; - - -#if SNMP_LWIP_MIB2 -#include "lwip/apps/snmp_mib2.h" -static const struct snmp_mib* const default_mibs[] = { &mib2 }; -static u8_t snmp_num_mibs = 1; -#else -static const struct snmp_mib* const default_mibs[] = { NULL }; -static u8_t snmp_num_mibs = 0; -#endif - -/* List of known mibs */ -static struct snmp_mib const * const *snmp_mibs = default_mibs; - -/** - * @ingroup snmp_core - * Sets the MIBs to use. - * Example: call snmp_set_mibs() as follows: - * static const struct snmp_mib *my_snmp_mibs[] = { - * &mib2, - * &private_mib - * }; - * snmp_set_mibs(my_snmp_mibs, LWIP_ARRAYSIZE(my_snmp_mibs)); - */ -void -snmp_set_mibs(const struct snmp_mib **mibs, u8_t num_mibs) -{ - LWIP_ASSERT("mibs pointer must be != NULL", (mibs != NULL)); - LWIP_ASSERT("num_mibs pointer must be != 0", (num_mibs != 0)); - snmp_mibs = mibs; - snmp_num_mibs = num_mibs; -} - -/** - * @ingroup snmp_core - * 'device enterprise oid' is used for 'device OID' field in trap PDU's (for identification of generating device) - * as well as for value returned by MIB-2 'sysObjectID' field (if internal MIB2 implementation is used). - * The 'device enterprise oid' shall point to an OID located under 'private-enterprises' branch (1.3.6.1.4.1.XXX). If a vendor - * wants to provide a custom object there, he has to get its own enterprise oid from IANA (http://www.iana.org). It - * is not allowed to use LWIP enterprise ID! - * In order to identify a specific device it is recommended to create a dedicated OID for each device type under its own - * enterprise oid. - * e.g. - * device a > 1.3.6.1.4.1.XXX(ent-oid).1(devices).1(device a) - * device b > 1.3.6.1.4.1.XXX(ent-oid).1(devices).2(device b) - * for more details see description of 'sysObjectID' field in RFC1213-MIB - */ -void snmp_set_device_enterprise_oid(const struct snmp_obj_id* device_enterprise_oid) -{ - if (device_enterprise_oid == NULL) { - snmp_device_enterprise_oid = &snmp_device_enterprise_oid_default; - } else { - snmp_device_enterprise_oid = device_enterprise_oid; - } -} - -/** - * @ingroup snmp_core - * Get 'device enterprise oid' - */ -const struct snmp_obj_id* snmp_get_device_enterprise_oid(void) -{ - return snmp_device_enterprise_oid; -} - -#if LWIP_IPV4 -/** - * Conversion from InetAddressIPv4 oid to lwIP ip4_addr - * @param oid points to u32_t ident[4] input - * @param ip points to output struct - */ -u8_t -snmp_oid_to_ip4(const u32_t *oid, ip4_addr_t *ip) -{ - if ((oid[0] > 0xFF) || - (oid[1] > 0xFF) || - (oid[2] > 0xFF) || - (oid[3] > 0xFF)) { - ip4_addr_copy(*ip, *IP4_ADDR_ANY4); - return 0; - } - - IP4_ADDR(ip, oid[0], oid[1], oid[2], oid[3]); - return 1; -} - -/** - * Convert ip4_addr to InetAddressIPv4 (no InetAddressType) - * @param ip points to input struct - * @param oid points to u32_t ident[4] output - */ -void -snmp_ip4_to_oid(const ip4_addr_t *ip, u32_t *oid) -{ - oid[0] = ip4_addr1(ip); - oid[1] = ip4_addr2(ip); - oid[2] = ip4_addr3(ip); - oid[3] = ip4_addr4(ip); -} -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -/** - * Conversion from InetAddressIPv6 oid to lwIP ip6_addr - * @param oid points to u32_t oid[16] input - * @param ip points to output struct - */ -u8_t -snmp_oid_to_ip6(const u32_t *oid, ip6_addr_t *ip) -{ - if ((oid[0] > 0xFF) || - (oid[1] > 0xFF) || - (oid[2] > 0xFF) || - (oid[3] > 0xFF) || - (oid[4] > 0xFF) || - (oid[5] > 0xFF) || - (oid[6] > 0xFF) || - (oid[7] > 0xFF) || - (oid[8] > 0xFF) || - (oid[9] > 0xFF) || - (oid[10] > 0xFF) || - (oid[11] > 0xFF) || - (oid[12] > 0xFF) || - (oid[13] > 0xFF) || - (oid[14] > 0xFF) || - (oid[15] > 0xFF)) { - ip6_addr_set_any(ip); - return 0; - } - - ip->addr[0] = (oid[0] << 24) | (oid[1] << 16) | (oid[2] << 8) | (oid[3] << 0); - ip->addr[1] = (oid[4] << 24) | (oid[5] << 16) | (oid[6] << 8) | (oid[7] << 0); - ip->addr[2] = (oid[8] << 24) | (oid[9] << 16) | (oid[10] << 8) | (oid[11] << 0); - ip->addr[3] = (oid[12] << 24) | (oid[13] << 16) | (oid[14] << 8) | (oid[15] << 0); - return 1; -} - -/** - * Convert ip6_addr to InetAddressIPv6 (no InetAddressType) - * @param ip points to input struct - * @param oid points to u32_t ident[16] output - */ -void -snmp_ip6_to_oid(const ip6_addr_t *ip, u32_t *oid) -{ - oid[0] = (ip->addr[0] & 0xFF000000) >> 24; - oid[1] = (ip->addr[0] & 0x00FF0000) >> 16; - oid[2] = (ip->addr[0] & 0x0000FF00) >> 8; - oid[3] = (ip->addr[0] & 0x000000FF) >> 0; - oid[4] = (ip->addr[1] & 0xFF000000) >> 24; - oid[5] = (ip->addr[1] & 0x00FF0000) >> 16; - oid[6] = (ip->addr[1] & 0x0000FF00) >> 8; - oid[7] = (ip->addr[1] & 0x000000FF) >> 0; - oid[8] = (ip->addr[2] & 0xFF000000) >> 24; - oid[9] = (ip->addr[2] & 0x00FF0000) >> 16; - oid[10] = (ip->addr[2] & 0x0000FF00) >> 8; - oid[11] = (ip->addr[2] & 0x000000FF) >> 0; - oid[12] = (ip->addr[3] & 0xFF000000) >> 24; - oid[13] = (ip->addr[3] & 0x00FF0000) >> 16; - oid[14] = (ip->addr[3] & 0x0000FF00) >> 8; - oid[15] = (ip->addr[3] & 0x000000FF) >> 0; -} -#endif /* LWIP_IPV6 */ - -#if LWIP_IPV4 || LWIP_IPV6 -/** - * Convert to InetAddressType+InetAddress+InetPortNumber - * @param ip IP address - * @param port Port - * @param oid OID - * @return OID length - */ -u8_t -snmp_ip_port_to_oid(const ip_addr_t *ip, u16_t port, u32_t *oid) -{ - u8_t idx; - - idx = snmp_ip_to_oid(ip, oid); - oid[idx] = port; - idx++; - - return idx; -} - -/** - * Convert to InetAddressType+InetAddress - * @param ip IP address - * @param oid OID - * @return OID length - */ -u8_t -snmp_ip_to_oid(const ip_addr_t *ip, u32_t *oid) -{ - if (IP_IS_ANY_TYPE_VAL(*ip)) { - oid[0] = 0; /* any */ - oid[1] = 0; /* no IP OIDs follow */ - return 2; - } else if (IP_IS_V6(ip)) { -#if LWIP_IPV6 - oid[0] = 2; /* ipv6 */ - oid[1] = 16; /* 16 InetAddressIPv6 OIDs follow */ - snmp_ip6_to_oid(ip_2_ip6(ip), &oid[2]); - return 18; -#else /* LWIP_IPV6 */ - return 0; -#endif /* LWIP_IPV6 */ - } else { -#if LWIP_IPV4 - oid[0] = 1; /* ipv4 */ - oid[1] = 4; /* 4 InetAddressIPv4 OIDs follow */ - snmp_ip4_to_oid(ip_2_ip4(ip), &oid[2]); - return 6; -#else /* LWIP_IPV4 */ - return 0; -#endif /* LWIP_IPV4 */ - } -} - -/** - * Convert from InetAddressType+InetAddress to ip_addr_t - * @param oid OID - * @param oid_len OID length - * @param ip IP address - * @return Parsed OID length - */ -u8_t -snmp_oid_to_ip(const u32_t *oid, u8_t oid_len, ip_addr_t *ip) -{ - /* InetAddressType */ - if (oid_len < 1) { - return 0; - } - - if (oid[0] == 0) { /* any */ - /* 1x InetAddressType, 1x OID len */ - if (oid_len < 2) { - return 0; - } - if (oid[1] != 0) { - return 0; - } - - memset(ip, 0, sizeof(*ip)); - IP_SET_TYPE(ip, IPADDR_TYPE_ANY); - - return 2; - } else if (oid[0] == 1) { /* ipv4 */ -#if LWIP_IPV4 - /* 1x InetAddressType, 1x OID len, 4x InetAddressIPv4 */ - if (oid_len < 6) { - return 0; - } - - /* 4x ipv4 OID */ - if (oid[1] != 4) { - return 0; - } - - IP_SET_TYPE(ip, IPADDR_TYPE_V4); - if (!snmp_oid_to_ip4(&oid[2], ip_2_ip4(ip))) { - return 0; - } - - return 6; -#else /* LWIP_IPV4 */ - return 0; -#endif /* LWIP_IPV4 */ - } else if (oid[0] == 2) { /* ipv6 */ -#if LWIP_IPV6 - /* 1x InetAddressType, 1x OID len, 16x InetAddressIPv6 */ - if (oid_len < 18) { - return 0; - } - - /* 16x ipv6 OID */ - if (oid[1] != 16) { - return 0; - } - - IP_SET_TYPE(ip, IPADDR_TYPE_V6); - if (!snmp_oid_to_ip6(&oid[2], ip_2_ip6(ip))) { - return 0; - } - - return 18; -#else /* LWIP_IPV6 */ - return 0; -#endif /* LWIP_IPV6 */ - } else { /* unsupported InetAddressType */ - return 0; - } -} - -/** - * Convert from InetAddressType+InetAddress+InetPortNumber to ip_addr_t and u16_t - * @param oid OID - * @param oid_len OID length - * @param ip IP address - * @param port Port - * @return Parsed OID length - */ -u8_t -snmp_oid_to_ip_port(const u32_t *oid, u8_t oid_len, ip_addr_t *ip, u16_t *port) -{ - u8_t idx = 0; - - /* InetAddressType + InetAddress */ - idx += snmp_oid_to_ip(&oid[idx], oid_len-idx, ip); - if (idx == 0) { - return 0; - } - - /* InetPortNumber */ - if (oid_len < (idx+1)) { - return 0; - } - if (oid[idx] > 0xffff) { - return 0; - } - *port = (u16_t)oid[idx]; - idx++; - - return idx; -} - -#endif /* LWIP_IPV4 || LWIP_IPV6 */ - -/** - * Assign an OID to struct snmp_obj_id - * @param target Assignment target - * @param oid OID - * @param oid_len OID length - */ -void -snmp_oid_assign(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len) -{ - LWIP_ASSERT("oid_len <= LWIP_SNMP_OBJ_ID_LEN", oid_len <= SNMP_MAX_OBJ_ID_LEN); - - target->len = oid_len; - - if (oid_len > 0) { - MEMCPY(target->id, oid, oid_len * sizeof(u32_t)); - } -} - -/** - * Prefix an OID to OID in struct snmp_obj_id - * @param target Assignment target to prefix - * @param oid OID - * @param oid_len OID length - */ -void -snmp_oid_prefix(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len) -{ - LWIP_ASSERT("target->len + oid_len <= LWIP_SNMP_OBJ_ID_LEN", (target->len + oid_len) <= SNMP_MAX_OBJ_ID_LEN); - - if (oid_len > 0) { - /* move existing OID to make room at the beginning for OID to insert */ - int i; - for (i = target->len-1; i>=0; i--) { - target->id[i + oid_len] = target->id[i]; - } - - /* paste oid at the beginning */ - MEMCPY(target->id, oid, oid_len * sizeof(u32_t)); - } -} - -/** - * Combine two OIDs into struct snmp_obj_id - * @param target Assignmet target - * @param oid1 OID 1 - * @param oid1_len OID 1 length - * @param oid2 OID 2 - * @param oid2_len OID 2 length - */ -void -snmp_oid_combine(struct snmp_obj_id* target, const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len) -{ - snmp_oid_assign(target, oid1, oid1_len); - snmp_oid_append(target, oid2, oid2_len); -} - -/** - * Append OIDs to struct snmp_obj_id - * @param target Assignment target to append to - * @param oid OID - * @param oid_len OID length - */ -void -snmp_oid_append(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len) -{ - LWIP_ASSERT("offset + oid_len <= LWIP_SNMP_OBJ_ID_LEN", (target->len + oid_len) <= SNMP_MAX_OBJ_ID_LEN); - - if (oid_len > 0) { - MEMCPY(&target->id[target->len], oid, oid_len * sizeof(u32_t)); - target->len += oid_len; - } -} - -/** - * Compare two OIDs - * @param oid1 OID 1 - * @param oid1_len OID 1 length - * @param oid2 OID 2 - * @param oid2_len OID 2 length - * @return -1: OID1<OID2 1: OID1 >OID2 0: equal - */ -s8_t -snmp_oid_compare(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len) -{ - u8_t level = 0; - LWIP_ASSERT("'oid1' param must not be NULL or 'oid1_len' param be 0!", (oid1 != NULL) || (oid1_len == 0)); - LWIP_ASSERT("'oid2' param must not be NULL or 'oid2_len' param be 0!", (oid2 != NULL) || (oid2_len == 0)); - - while ((level < oid1_len) && (level < oid2_len)) { - if (*oid1 < *oid2) { - return -1; - } - if (*oid1 > *oid2) { - return 1; - } - - level++; - oid1++; - oid2++; - } - - /* common part of both OID's is equal, compare length */ - if (oid1_len < oid2_len) { - return -1; - } - if (oid1_len > oid2_len) { - return 1; - } - - /* they are equal */ - return 0; -} - - -/** - * Check of two OIDs are equal - * @param oid1 OID 1 - * @param oid1_len OID 1 length - * @param oid2 OID 2 - * @param oid2_len OID 2 length - * @return 1: equal 0: non-equal - */ -u8_t -snmp_oid_equal(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len) -{ - return (snmp_oid_compare(oid1, oid1_len, oid2, oid2_len) == 0)? 1 : 0; -} - -/** - * Convert netif to interface index - * @param netif netif - * @return index - */ -u8_t -netif_to_num(const struct netif *netif) -{ - u8_t result = 0; - struct netif *netif_iterator = netif_list; - - while (netif_iterator != NULL) { - result++; - - if (netif_iterator == netif) { - return result; - } - - netif_iterator = netif_iterator->next; - } - - LWIP_ASSERT("netif not found in netif_list", 0); - return 0; -} - -static const struct snmp_mib* -snmp_get_mib_from_oid(const u32_t *oid, u8_t oid_len) -{ - const u32_t* list_oid; - const u32_t* searched_oid; - u8_t i, l; - - u8_t max_match_len = 0; - const struct snmp_mib* matched_mib = NULL; - - LWIP_ASSERT("'oid' param must not be NULL!", (oid != NULL)); - - if (oid_len == 0) { - return NULL; - } - - for (i = 0; i < snmp_num_mibs; i++) { - LWIP_ASSERT("MIB array not initialized correctly", (snmp_mibs[i] != NULL)); - LWIP_ASSERT("MIB array not initialized correctly - base OID is NULL", (snmp_mibs[i]->base_oid != NULL)); - - if (oid_len >= snmp_mibs[i]->base_oid_len) { - l = snmp_mibs[i]->base_oid_len; - list_oid = snmp_mibs[i]->base_oid; - searched_oid = oid; - - while (l > 0) { - if (*list_oid != *searched_oid) { - break; - } - - l--; - list_oid++; - searched_oid++; - } - - if ((l == 0) && (snmp_mibs[i]->base_oid_len > max_match_len)) { - max_match_len = snmp_mibs[i]->base_oid_len; - matched_mib = snmp_mibs[i]; - } - } - } - - return matched_mib; -} - -static const struct snmp_mib* -snmp_get_next_mib(const u32_t *oid, u8_t oid_len) -{ - u8_t i; - const struct snmp_mib* next_mib = NULL; - - LWIP_ASSERT("'oid' param must not be NULL!", (oid != NULL)); - - if (oid_len == 0) { - return NULL; - } - - for (i = 0; i < snmp_num_mibs; i++) { - if (snmp_mibs[i]->base_oid != NULL) { - /* check if mib is located behind starting point */ - if (snmp_oid_compare(snmp_mibs[i]->base_oid, snmp_mibs[i]->base_oid_len, oid, oid_len) > 0) { - if ((next_mib == NULL) || - (snmp_oid_compare(snmp_mibs[i]->base_oid, snmp_mibs[i]->base_oid_len, - next_mib->base_oid, next_mib->base_oid_len) < 0)) { - next_mib = snmp_mibs[i]; - } - } - } - } - - return next_mib; -} - -static const struct snmp_mib* -snmp_get_mib_between(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len) -{ - const struct snmp_mib* next_mib = snmp_get_next_mib(oid1, oid1_len); - - LWIP_ASSERT("'oid2' param must not be NULL!", (oid2 != NULL)); - LWIP_ASSERT("'oid2_len' param must be greater than 0!", (oid2_len > 0)); - - if (next_mib != NULL) { - if (snmp_oid_compare(next_mib->base_oid, next_mib->base_oid_len, oid2, oid2_len) < 0) { - return next_mib; - } - } - - return NULL; -} - -u8_t -snmp_get_node_instance_from_oid(const u32_t *oid, u8_t oid_len, struct snmp_node_instance* node_instance) -{ - u8_t result = SNMP_ERR_NOSUCHOBJECT; - const struct snmp_mib *mib; - const struct snmp_node *mn = NULL; - - mib = snmp_get_mib_from_oid(oid, oid_len); - if (mib != NULL) { - u8_t oid_instance_len; - - mn = snmp_mib_tree_resolve_exact(mib, oid, oid_len, &oid_instance_len); - if ((mn != NULL) && (mn->node_type != SNMP_NODE_TREE)) { - /* get instance */ - const struct snmp_leaf_node* leaf_node = (const struct snmp_leaf_node*)(const void*)mn; - - node_instance->node = mn; - snmp_oid_assign(&node_instance->instance_oid, oid + (oid_len - oid_instance_len), oid_instance_len); - - result = leaf_node->get_instance( - oid, - oid_len - oid_instance_len, - node_instance); - -#ifdef LWIP_DEBUG - if (result == SNMP_ERR_NOERROR) { - if (((node_instance->access & SNMP_NODE_INSTANCE_ACCESS_READ) != 0) && (node_instance->get_value == NULL)) { - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP inconsistent access: node is readable but no get_value function is specified\n")); - } - if (((node_instance->access & SNMP_NODE_INSTANCE_ACCESS_WRITE) != 0) && (node_instance->set_value == NULL)) { - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP inconsistent access: node is writable but no set_value and/or set_test function is specified\n")); - } - } -#endif - } - } - - return result; -} - -u8_t -snmp_get_next_node_instance_from_oid(const u32_t *oid, u8_t oid_len, snmp_validate_node_instance_method validate_node_instance_method, void* validate_node_instance_arg, struct snmp_obj_id* node_oid, struct snmp_node_instance* node_instance) -{ - const struct snmp_mib *mib; - const struct snmp_node *mn = NULL; - const u32_t* start_oid = NULL; - u8_t start_oid_len = 0; - - /* resolve target MIB from passed OID */ - mib = snmp_get_mib_from_oid(oid, oid_len); - if (mib == NULL) { - /* passed OID does not reference any known MIB, start at the next closest MIB */ - mib = snmp_get_next_mib(oid, oid_len); - - if (mib != NULL) { - start_oid = mib->base_oid; - start_oid_len = mib->base_oid_len; - } - } else { - start_oid = oid; - start_oid_len = oid_len; - } - - /* resolve target node from MIB, skip to next MIB if no suitable node is found in current MIB */ - while ((mib != NULL) && (mn == NULL)) { - u8_t oid_instance_len; - - /* check if OID directly references a node inside current MIB, in this case we have to ask this node for the next instance */ - mn = snmp_mib_tree_resolve_exact(mib, start_oid, start_oid_len, &oid_instance_len); - if (mn != NULL) { - snmp_oid_assign(node_oid, start_oid, start_oid_len - oid_instance_len); /* set oid to node */ - snmp_oid_assign(&node_instance->instance_oid, start_oid + (start_oid_len - oid_instance_len), oid_instance_len); /* set (relative) instance oid */ - } else { - /* OID does not reference a node, search for the next closest node inside MIB; set instance_oid.len to zero because we want the first instance of this node */ - mn = snmp_mib_tree_resolve_next(mib, start_oid, start_oid_len, node_oid); - node_instance->instance_oid.len = 0; - } - - /* validate the node; if the node has no further instance or the returned instance is invalid, search for the next in MIB and validate again */ - node_instance->node = mn; - while (mn != NULL) { - u8_t result; - - /* clear fields which may have values from previous loops */ - node_instance->asn1_type = 0; - node_instance->access = SNMP_NODE_INSTANCE_NOT_ACCESSIBLE; - node_instance->get_value = NULL; - node_instance->set_test = NULL; - node_instance->set_value = NULL; - node_instance->release_instance = NULL; - node_instance->reference.ptr = NULL; - node_instance->reference_len = 0; - - result = ((const struct snmp_leaf_node*)(const void*)mn)->get_next_instance( - node_oid->id, - node_oid->len, - node_instance); - - if (result == SNMP_ERR_NOERROR) { -#ifdef LWIP_DEBUG - if (((node_instance->access & SNMP_NODE_INSTANCE_ACCESS_READ) != 0) && (node_instance->get_value == NULL)) { - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP inconsistent access: node is readable but no get_value function is specified\n")); - } - if (((node_instance->access & SNMP_NODE_INSTANCE_ACCESS_WRITE) != 0) && (node_instance->set_value == NULL)) { - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP inconsistent access: node is writable but no set_value function is specified\n")); - } -#endif - - /* validate node because the node may be not accessible for example (but let the caller decide what is valid */ - if ((validate_node_instance_method == NULL) || - (validate_node_instance_method(node_instance, validate_node_instance_arg) == SNMP_ERR_NOERROR)) { - /* node_oid "returns" the full result OID (including the instance part) */ - snmp_oid_append(node_oid, node_instance->instance_oid.id, node_instance->instance_oid.len); - break; - } - - if (node_instance->release_instance != NULL) { - node_instance->release_instance(node_instance); - } - /* - the instance itself is not valid, ask for next instance from same node. - we don't have to change any variables because node_instance->instance_oid is used as input (starting point) - as well as output (resulting next OID), so we have to simply call get_next_instance method again - */ - } else { - if (node_instance->release_instance != NULL) { - node_instance->release_instance(node_instance); - } - - /* the node has no further instance, skip to next node */ - mn = snmp_mib_tree_resolve_next(mib, node_oid->id, node_oid->len, &node_instance->instance_oid); /* misuse node_instance->instance_oid as tmp buffer */ - if (mn != NULL) { - /* prepare for next loop */ - snmp_oid_assign(node_oid, node_instance->instance_oid.id, node_instance->instance_oid.len); - node_instance->instance_oid.len = 0; - node_instance->node = mn; - } - } - } - - if (mn != NULL) { - /* - we found a suitable next node, - now we have to check if a inner MIB is located between the searched OID and the resulting OID. - this is possible because MIB's may be located anywhere in the global tree, that means also in - the subtree of another MIB (e.g. if searched OID is .2 and resulting OID is .4, then another - MIB having .3 as root node may exist) - */ - const struct snmp_mib *intermediate_mib; - intermediate_mib = snmp_get_mib_between(start_oid, start_oid_len, node_oid->id, node_oid->len); - - if (intermediate_mib != NULL) { - /* search for first node inside intermediate mib in next loop */ - if (node_instance->release_instance != NULL) { - node_instance->release_instance(node_instance); - } - - mn = NULL; - mib = intermediate_mib; - start_oid = mib->base_oid; - start_oid_len = mib->base_oid_len; - } - /* else { we found out target node } */ - } else { - /* - there is no further (suitable) node inside this MIB, search for the next MIB with following priority - 1. search for inner MIB's (whose root is located inside tree of current MIB) - 2. search for surrouding MIB's (where the current MIB is the inner MIB) and continue there if any - 3. take the next closest MIB (not being related to the current MIB) - */ - const struct snmp_mib *next_mib; - next_mib = snmp_get_next_mib(start_oid, start_oid_len); /* returns MIB's related to point 1 and 3 */ - - /* is the found MIB an inner MIB? (point 1) */ - if ((next_mib != NULL) && (next_mib->base_oid_len > mib->base_oid_len) && - (snmp_oid_compare(next_mib->base_oid, mib->base_oid_len, mib->base_oid, mib->base_oid_len) == 0)) { - /* yes it is -> continue at inner MIB */ - mib = next_mib; - start_oid = mib->base_oid; - start_oid_len = mib->base_oid_len; - } else { - /* check if there is a surrounding mib where to continue (point 2) (only possible if OID length > 1) */ - if (mib->base_oid_len > 1) { - mib = snmp_get_mib_from_oid(mib->base_oid, mib->base_oid_len - 1); - - if (mib == NULL) { - /* no surrounding mib, use next mib encountered above (point 3) */ - mib = next_mib; - - if (mib != NULL) { - start_oid = mib->base_oid; - start_oid_len = mib->base_oid_len; - } - } - /* else { start_oid stays the same because we want to continue from current offset in surrounding mib (point 2) } */ - } - } - } - } - - if (mib == NULL) { - /* loop is only left when mib == null (error) or mib_node != NULL (success) */ - return SNMP_ERR_ENDOFMIBVIEW; - } - - return SNMP_ERR_NOERROR; -} - -/** - * Searches tree for the supplied object identifier. - * - */ -const struct snmp_node * -snmp_mib_tree_resolve_exact(const struct snmp_mib *mib, const u32_t *oid, u8_t oid_len, u8_t* oid_instance_len) -{ - const struct snmp_node* const* node = &mib->root_node; - u8_t oid_offset = mib->base_oid_len; - - while ((oid_offset < oid_len) && ((*node)->node_type == SNMP_NODE_TREE)) { - /* search for matching sub node */ - u32_t subnode_oid = *(oid + oid_offset); - - u32_t i = (*(const struct snmp_tree_node* const*)node)->subnode_count; - node = (*(const struct snmp_tree_node* const*)node)->subnodes; - while ((i > 0) && ((*node)->oid != subnode_oid)) { - node++; - i--; - } - - if (i == 0) { - /* no matching subnode found */ - return NULL; - } - - oid_offset++; - } - - if ((*node)->node_type != SNMP_NODE_TREE) { - /* we found a leaf node */ - *oid_instance_len = oid_len - oid_offset; - return (*node); - } - - return NULL; -} - -const struct snmp_node* -snmp_mib_tree_resolve_next(const struct snmp_mib *mib, const u32_t *oid, u8_t oid_len, struct snmp_obj_id* oidret) -{ - u8_t oid_offset = mib->base_oid_len; - const struct snmp_node* const* node; - const struct snmp_tree_node* node_stack[SNMP_MAX_OBJ_ID_LEN]; - s32_t nsi = 0; /* NodeStackIndex */ - u32_t subnode_oid; - - if (mib->root_node->node_type != SNMP_NODE_TREE) { - /* a next operation on a mib with only a leaf node will always return NULL because there is no other node */ - return NULL; - } - - /* first build node stack related to passed oid (as far as possible), then go backwards to determine the next node */ - node_stack[nsi] = (const struct snmp_tree_node*)(const void*)mib->root_node; - while (oid_offset < oid_len) { - /* search for matching sub node */ - u32_t i = node_stack[nsi]->subnode_count; - node = node_stack[nsi]->subnodes; - - subnode_oid = *(oid + oid_offset); - - while ((i > 0) && ((*node)->oid != subnode_oid)) { - node++; - i--; - } - - if ((i == 0) || ((*node)->node_type != SNMP_NODE_TREE)) { - /* no (matching) tree-subnode found */ - break; - } - nsi++; - node_stack[nsi] = (const struct snmp_tree_node*)(const void*)(*node); - - oid_offset++; - } - - - if (oid_offset >= oid_len) { - /* passed oid references a tree node -> return first useable sub node of it */ - subnode_oid = 0; - } else { - subnode_oid = *(oid + oid_offset) + 1; - } - - while (nsi >= 0) { - const struct snmp_node* subnode = NULL; - - /* find next node on current level */ - s32_t i = node_stack[nsi]->subnode_count; - node = node_stack[nsi]->subnodes; - while (i > 0) { - if ((*node)->oid == subnode_oid) { - subnode = *node; - break; - } else if (((*node)->oid > subnode_oid) && ((subnode == NULL) || ((*node)->oid < subnode->oid))) { - subnode = *node; - } - - node++; - i--; - } - - if (subnode == NULL) { - /* no further node found on this level, go one level up and start searching with index of current node*/ - subnode_oid = node_stack[nsi]->node.oid + 1; - nsi--; - } else { - if (subnode->node_type == SNMP_NODE_TREE) { - /* next is a tree node, go into it and start searching */ - nsi++; - node_stack[nsi] = (const struct snmp_tree_node*)(const void*)subnode; - subnode_oid = 0; - } else { - /* we found a leaf node -> fill oidret and return it */ - snmp_oid_assign(oidret, mib->base_oid, mib->base_oid_len); - i = 1; - while (i <= nsi) { - oidret->id[oidret->len] = node_stack[i]->node.oid; - oidret->len++; - i++; - } - - oidret->id[oidret->len] = subnode->oid; - oidret->len++; - - return subnode; - } - } - } - - return NULL; -} - -/** initialize struct next_oid_state using this function before passing it to next_oid_check */ -void -snmp_next_oid_init(struct snmp_next_oid_state *state, - const u32_t *start_oid, u8_t start_oid_len, - u32_t *next_oid_buf, u8_t next_oid_max_len) -{ - state->start_oid = start_oid; - state->start_oid_len = start_oid_len; - state->next_oid = next_oid_buf; - state->next_oid_len = 0; - state->next_oid_max_len = next_oid_max_len; - state->status = SNMP_NEXT_OID_STATUS_NO_MATCH; -} - -/** checks if the passed incomplete OID may be a possible candidate for snmp_next_oid_check(); -this methid is intended if the complete OID is not yet known but it is very expensive to build it up, -so it is possible to test the starting part before building up the complete oid and pass it to snmp_next_oid_check()*/ -u8_t -snmp_next_oid_precheck(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len) -{ - if (state->status != SNMP_NEXT_OID_STATUS_BUF_TO_SMALL) { - u8_t start_oid_len = (oid_len < state->start_oid_len) ? oid_len : state->start_oid_len; - - /* check passed OID is located behind start offset */ - if (snmp_oid_compare(oid, oid_len, state->start_oid, start_oid_len) >= 0) { - /* check if new oid is located closer to start oid than current closest oid */ - if ((state->status == SNMP_NEXT_OID_STATUS_NO_MATCH) || - (snmp_oid_compare(oid, oid_len, state->next_oid, state->next_oid_len) < 0)) { - return 1; - } - } - } - - return 0; -} - -/** checks the passed OID if it is a candidate to be the next one (get_next); returns !=0 if passed oid is currently closest, otherwise 0 */ -u8_t -snmp_next_oid_check(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len, void* reference) -{ - /* do not overwrite a fail result */ - if (state->status != SNMP_NEXT_OID_STATUS_BUF_TO_SMALL) { - /* check passed OID is located behind start offset */ - if (snmp_oid_compare(oid, oid_len, state->start_oid, state->start_oid_len) > 0) { - /* check if new oid is located closer to start oid than current closest oid */ - if ((state->status == SNMP_NEXT_OID_STATUS_NO_MATCH) || - (snmp_oid_compare(oid, oid_len, state->next_oid, state->next_oid_len) < 0)) { - if (oid_len <= state->next_oid_max_len) { - MEMCPY(state->next_oid, oid, oid_len * sizeof(u32_t)); - state->next_oid_len = oid_len; - state->status = SNMP_NEXT_OID_STATUS_SUCCESS; - state->reference = reference; - return 1; - } else { - state->status = SNMP_NEXT_OID_STATUS_BUF_TO_SMALL; - } - } - } - } - - return 0; -} - -u8_t -snmp_oid_in_range(const u32_t *oid_in, u8_t oid_len, const struct snmp_oid_range *oid_ranges, u8_t oid_ranges_len) -{ - u8_t i; - - if (oid_len != oid_ranges_len) { - return 0; - } - - for (i = 0; i < oid_ranges_len; i++) { - if ((oid_in[i] < oid_ranges[i].min) || (oid_in[i] > oid_ranges[i].max)) { - return 0; - } - } - - return 1; -} - -snmp_err_t -snmp_set_test_ok(struct snmp_node_instance* instance, u16_t value_len, void* value) -{ - LWIP_UNUSED_ARG(instance); - LWIP_UNUSED_ARG(value_len); - LWIP_UNUSED_ARG(value); - - return SNMP_ERR_NOERROR; -} - -/** - * Decodes BITS pseudotype value from ASN.1 OctetString. - * - * @note Because BITS pseudo type is encoded as OCTET STRING, it cannot directly - * be encoded/decoded by the agent. Instead call this function as required from - * get/test/set methods. - * - * @param buf points to a buffer holding the ASN1 octet string - * @param buf_len length of octet string - * @param bit_value decoded Bit value with Bit0 == LSB - * @return ERR_OK if successful, ERR_ARG if bit value contains more than 32 bit - */ -err_t -snmp_decode_bits(const u8_t *buf, u32_t buf_len, u32_t *bit_value) -{ - u8_t b; - u8_t bits_processed = 0; - *bit_value = 0; - - while (buf_len > 0) { - /* any bit set in this byte? */ - if (*buf != 0x00) { - if (bits_processed >= 32) { - /* accept more than 4 bytes, but only when no bits are set */ - return ERR_VAL; - } - - b = *buf; - do { - if (b & 0x80) { - *bit_value |= (1 << bits_processed); - } - bits_processed++; - b <<= 1; - } - while ((bits_processed & 0x07) != 0); /* &0x07 -> % 8 */ - } else { - bits_processed += 8; - } - - buf_len--; - buf++; - } - - return ERR_OK; -} - -err_t -snmp_decode_truthvalue(const s32_t *asn1_value, u8_t *bool_value) -{ - /* defined by RFC1443: - TruthValue ::= TEXTUAL-CONVENTION - STATUS current - DESCRIPTION - "Represents a boolean value." - SYNTAX INTEGER { true(1), false(2) } - */ - - if ((asn1_value == NULL) || (bool_value == NULL)) { - return ERR_ARG; - } - - if (*asn1_value == 1) { - *bool_value = 1; - } else if (*asn1_value == 2) { - *bool_value = 0; - } else { - return ERR_VAL; - } - - return ERR_OK; -} - -/** - * Encodes BITS pseudotype value into ASN.1 OctetString. - * - * @note Because BITS pseudo type is encoded as OCTET STRING, it cannot directly - * be encoded/decoded by the agent. Instead call this function as required from - * get/test/set methods. - * - * @param buf points to a buffer where the resulting ASN1 octet string is stored to - * @param buf_len max length of the bufffer - * @param bit_value Bit value to encode with Bit0 == LSB - * @param bit_count Number of possible bits for the bit value (according to rfc we have to send all bits independant from their truth value) - * @return number of bytes used from buffer to store the resulting OctetString - */ -u8_t -snmp_encode_bits(u8_t *buf, u32_t buf_len, u32_t bit_value, u8_t bit_count) -{ - u8_t len = 0; - u8_t min_bytes = (bit_count + 7) >> 3; /* >>3 -> / 8 */ - - while ((buf_len > 0) && (bit_value != 0x00)) { - s8_t i = 7; - *buf = 0x00; - while (i >= 0) { - if (bit_value & 0x01) { - *buf |= 0x01; - } - - if (i > 0) { - *buf <<= 1; - } - - bit_value >>= 1; - i--; - } - - buf++; - buf_len--; - len++; - } - - if (len < min_bytes) { - buf += len; - buf_len -= len; - - while ((len < min_bytes) && (buf_len > 0)) { - *buf = 0x00; - buf++; - buf_len--; - len++; - } - } - - return len; -} - -u8_t -snmp_encode_truthvalue(s32_t *asn1_value, u32_t bool_value) -{ - /* defined by RFC1443: - TruthValue ::= TEXTUAL-CONVENTION - STATUS current - DESCRIPTION - "Represents a boolean value." - SYNTAX INTEGER { true(1), false(2) } - */ - - if (asn1_value == NULL) { - return 0; - } - - if (bool_value) { - *asn1_value = 1; /* defined by RFC1443 */ - } else { - *asn1_value = 2; /* defined by RFC1443 */ - } - - return sizeof(s32_t); -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core_priv.h deleted file mode 100644 index 5552177d747c753b458b93707300368cf98590c3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_core_priv.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#ifndef LWIP_HDR_APPS_SNMP_CORE_PRIV_H -#define LWIP_HDR_APPS_SNMP_CORE_PRIV_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp_core.h" -#include "snmp_asn1.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* (outdated) SNMPv1 error codes - * shall not be used by MIBS anymore, nevertheless required from core for properly answering a v1 request - */ -#define SNMP_ERR_NOSUCHNAME 2 -#define SNMP_ERR_BADVALUE 3 -#define SNMP_ERR_READONLY 4 -/* error codes which are internal and shall not be used by MIBS - * shall not be used by MIBS anymore, nevertheless required from core for properly answering a v1 request - */ -#define SNMP_ERR_TOOBIG 1 -#define SNMP_ERR_AUTHORIZATIONERROR 16 -#define SNMP_ERR_NOSUCHOBJECT SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_OBJECT -#define SNMP_ERR_ENDOFMIBVIEW SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_END_OF_MIB_VIEW - - -const struct snmp_node* snmp_mib_tree_resolve_exact(const struct snmp_mib *mib, const u32_t *oid, u8_t oid_len, u8_t* oid_instance_len); -const struct snmp_node* snmp_mib_tree_resolve_next(const struct snmp_mib *mib, const u32_t *oid, u8_t oid_len, struct snmp_obj_id* oidret); - -typedef u8_t (*snmp_validate_node_instance_method)(struct snmp_node_instance*, void*); - -u8_t snmp_get_node_instance_from_oid(const u32_t *oid, u8_t oid_len, struct snmp_node_instance* node_instance); -u8_t snmp_get_next_node_instance_from_oid(const u32_t *oid, u8_t oid_len, snmp_validate_node_instance_method validate_node_instance_method, void* validate_node_instance_arg, struct snmp_obj_id* node_oid, struct snmp_node_instance* node_instance); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* LWIP_HDR_APPS_SNMP_CORE_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2.c deleted file mode 100644 index 9d8c43c108ad8bb61e999ae8971cd689aa0eab23..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2.c +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -/** - * @defgroup snmp_mib2 MIB2 - * @ingroup snmp - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP && SNMP_LWIP_MIB2 /* don't build if not configured for use in lwipopts.h */ - -#if !LWIP_STATS -#error LWIP_SNMP MIB2 needs LWIP_STATS (for MIB2) -#endif -#if !MIB2_STATS -#error LWIP_SNMP MIB2 needs MIB2_STATS (for MIB2) -#endif - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_scalar.h" - -#if SNMP_USE_NETCONN -#include "lwip/tcpip.h" -#include "lwip/priv/tcpip_priv.h" -void -snmp_mib2_lwip_synchronizer(snmp_threadsync_called_fn fn, void* arg) -{ -#if LWIP_TCPIP_CORE_LOCKING - LOCK_TCPIP_CORE(); - fn(arg); - UNLOCK_TCPIP_CORE(); -#else - tcpip_callback(fn, arg); -#endif -} - -struct snmp_threadsync_instance snmp_mib2_lwip_locks; -#endif - -/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */ -/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */ -/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */ - -/* --- mib-2 .1.3.6.1.2.1 ----------------------------------------------------- */ -extern const struct snmp_scalar_array_node snmp_mib2_snmp_root; -extern const struct snmp_tree_node snmp_mib2_udp_root; -extern const struct snmp_tree_node snmp_mib2_tcp_root; -extern const struct snmp_scalar_array_node snmp_mib2_icmp_root; -extern const struct snmp_tree_node snmp_mib2_interface_root; -extern const struct snmp_scalar_array_node snmp_mib2_system_node; -extern const struct snmp_tree_node snmp_mib2_at_root; -extern const struct snmp_tree_node snmp_mib2_ip_root; - -static const struct snmp_node* const mib2_nodes[] = { - &snmp_mib2_system_node.node.node, - &snmp_mib2_interface_root.node, -#if LWIP_ARP && LWIP_IPV4 - &snmp_mib2_at_root.node, -#endif /* LWIP_ARP && LWIP_IPV4 */ -#if LWIP_IPV4 - &snmp_mib2_ip_root.node, -#endif /* LWIP_IPV4 */ -#if LWIP_ICMP - &snmp_mib2_icmp_root.node.node, -#endif /* LWIP_ICMP */ -#if LWIP_TCP - &snmp_mib2_tcp_root.node, -#endif /* LWIP_TCP */ -#if LWIP_UDP - &snmp_mib2_udp_root.node, -#endif /* LWIP_UDP */ - &snmp_mib2_snmp_root.node.node -}; - -static const struct snmp_tree_node mib2_root = SNMP_CREATE_TREE_NODE(1, mib2_nodes); - -static const u32_t mib2_base_oid_arr[] = { 1,3,6,1,2,1 }; -const struct snmp_mib mib2 = SNMP_MIB_CREATE(mib2_base_oid_arr, &mib2_root.node); - -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_icmp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_icmp.c deleted file mode 100644 index 995bd320a5d7db902e0d30ee47f34b148640895d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_icmp.c +++ /dev/null @@ -1,182 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) ICMP objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/icmp.h" -#include "lwip/stats.h" - -#if LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_ICMP - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - -/* --- icmp .1.3.6.1.2.1.5 ----------------------------------------------------- */ - -static s16_t -icmp_get_value(const struct snmp_scalar_array_node_def *node, void *value) -{ - u32_t *uint_ptr = (u32_t*)value; - - switch (node->oid) { - case 1: /* icmpInMsgs */ - *uint_ptr = STATS_GET(mib2.icmpinmsgs); - return sizeof(*uint_ptr); - case 2: /* icmpInErrors */ - *uint_ptr = STATS_GET(mib2.icmpinerrors); - return sizeof(*uint_ptr); - case 3: /* icmpInDestUnreachs */ - *uint_ptr = STATS_GET(mib2.icmpindestunreachs); - return sizeof(*uint_ptr); - case 4: /* icmpInTimeExcds */ - *uint_ptr = STATS_GET(mib2.icmpintimeexcds); - return sizeof(*uint_ptr); - case 5: /* icmpInParmProbs */ - *uint_ptr = STATS_GET(mib2.icmpinparmprobs); - return sizeof(*uint_ptr); - case 6: /* icmpInSrcQuenchs */ - *uint_ptr = STATS_GET(mib2.icmpinsrcquenchs); - return sizeof(*uint_ptr); - case 7: /* icmpInRedirects */ - *uint_ptr = STATS_GET(mib2.icmpinredirects); - return sizeof(*uint_ptr); - case 8: /* icmpInEchos */ - *uint_ptr = STATS_GET(mib2.icmpinechos); - return sizeof(*uint_ptr); - case 9: /* icmpInEchoReps */ - *uint_ptr = STATS_GET(mib2.icmpinechoreps); - return sizeof(*uint_ptr); - case 10: /* icmpInTimestamps */ - *uint_ptr = STATS_GET(mib2.icmpintimestamps); - return sizeof(*uint_ptr); - case 11: /* icmpInTimestampReps */ - *uint_ptr = STATS_GET(mib2.icmpintimestampreps); - return sizeof(*uint_ptr); - case 12: /* icmpInAddrMasks */ - *uint_ptr = STATS_GET(mib2.icmpinaddrmasks); - return sizeof(*uint_ptr); - case 13: /* icmpInAddrMaskReps */ - *uint_ptr = STATS_GET(mib2.icmpinaddrmaskreps); - return sizeof(*uint_ptr); - case 14: /* icmpOutMsgs */ - *uint_ptr = STATS_GET(mib2.icmpoutmsgs); - return sizeof(*uint_ptr); - case 15: /* icmpOutErrors */ - *uint_ptr = STATS_GET(mib2.icmpouterrors); - return sizeof(*uint_ptr); - case 16: /* icmpOutDestUnreachs */ - *uint_ptr = STATS_GET(mib2.icmpoutdestunreachs); - return sizeof(*uint_ptr); - case 17: /* icmpOutTimeExcds */ - *uint_ptr = STATS_GET(mib2.icmpouttimeexcds); - return sizeof(*uint_ptr); - case 18: /* icmpOutParmProbs: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 19: /* icmpOutSrcQuenchs: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 20: /* icmpOutRedirects: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 21: /* icmpOutEchos */ - *uint_ptr = STATS_GET(mib2.icmpoutechos); - return sizeof(*uint_ptr); - case 22: /* icmpOutEchoReps */ - *uint_ptr = STATS_GET(mib2.icmpoutechoreps); - return sizeof(*uint_ptr); - case 23: /* icmpOutTimestamps: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 24: /* icmpOutTimestampReps: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 25: /* icmpOutAddrMasks: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - case 26: /* icmpOutAddrMaskReps: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_value(): unknown id: %"S32_F"\n", node->oid)); - break; - } - - return 0; -} - - -static const struct snmp_scalar_array_node_def icmp_nodes[] = { - { 1, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 2, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 3, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 4, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 5, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 6, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 7, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 8, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - { 9, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {10, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {11, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {12, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {13, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {14, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {15, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {16, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {17, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {18, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {19, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {20, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {21, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {22, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {23, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {24, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {25, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, - {26, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY} -}; - -const struct snmp_scalar_array_node snmp_mib2_icmp_root = SNMP_SCALAR_CREATE_ARRAY_NODE(5, icmp_nodes, icmp_get_value, NULL, NULL); - -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_ICMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_interfaces.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_interfaces.c deleted file mode 100644 index 979b5073ea663bb5a8794980599607807776f10c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_interfaces.c +++ /dev/null @@ -1,375 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) INTERFACES objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/netif.h" -#include "lwip/stats.h" - -#include - -#if LWIP_SNMP && SNMP_LWIP_MIB2 - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - - -/* --- interfaces .1.3.6.1.2.1.2 ----------------------------------------------------- */ - -static s16_t -interfaces_get_value(struct snmp_node_instance* instance, void* value) -{ - if (instance->node->oid == 1) { - s32_t *sint_ptr = (s32_t*)value; - s32_t num_netifs = 0; - - struct netif *netif = netif_list; - while (netif != NULL) { - num_netifs++; - netif = netif->next; - } - - *sint_ptr = num_netifs; - return sizeof(*sint_ptr); - } - - return 0; -} - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range interfaces_Table_oid_ranges[] = { - { 1, 0xff } /* netif->num is u8_t */ -}; - -static const u8_t iftable_ifOutQLen = 0; - -static const u8_t iftable_ifOperStatus_up = 1; -static const u8_t iftable_ifOperStatus_down = 2; - -static const u8_t iftable_ifAdminStatus_up = 1; -static const u8_t iftable_ifAdminStatus_lowerLayerDown = 7; -static const u8_t iftable_ifAdminStatus_down = 2; - -static snmp_err_t -interfaces_Table_get_cell_instance(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, struct snmp_node_instance* cell_instance) -{ - u32_t ifIndex; - struct netif *netif; - - LWIP_UNUSED_ARG(column); - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, interfaces_Table_oid_ranges, LWIP_ARRAYSIZE(interfaces_Table_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get netif index from incoming OID */ - ifIndex = row_oid[0]; - - /* find netif with index */ - netif = netif_list; - while (netif != NULL) { - if (netif_to_num(netif) == ifIndex) { - /* store netif pointer for subsequent operations (get/test/set) */ - cell_instance->reference.ptr = netif; - return SNMP_ERR_NOERROR; - } - netif = netif->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -interfaces_Table_get_next_cell_instance(const u32_t* column, struct snmp_obj_id* row_oid, struct snmp_node_instance* cell_instance) -{ - struct netif *netif; - struct snmp_next_oid_state state; - u32_t result_temp[LWIP_ARRAYSIZE(interfaces_Table_oid_ranges)]; - - LWIP_UNUSED_ARG(column); - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(interfaces_Table_oid_ranges)); - - /* iterate over all possible OIDs to find the next one */ - netif = netif_list; - while (netif != NULL) { - u32_t test_oid[LWIP_ARRAYSIZE(interfaces_Table_oid_ranges)]; - test_oid[0] = netif_to_num(netif); - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(interfaces_Table_oid_ranges), netif); - - netif = netif->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* store netif pointer for subsequent operations (get/test/set) */ - cell_instance->reference.ptr = /* (struct netif*) */state.reference; - return SNMP_ERR_NOERROR; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static s16_t -interfaces_Table_get_value(struct snmp_node_instance* instance, void* value) -{ - struct netif *netif = (struct netif*)instance->reference.ptr; - u32_t* value_u32 = (u32_t*)value; - s32_t* value_s32 = (s32_t*)value; - u16_t value_len; - - switch (SNMP_TABLE_GET_COLUMN_FROM_OID(instance->instance_oid.id)) - { - case 1: /* ifIndex */ - *value_s32 = netif_to_num(netif); - value_len = sizeof(*value_s32); - break; - case 2: /* ifDescr */ - value_len = sizeof(netif->name); - MEMCPY(value, netif->name, value_len); - break; - case 3: /* ifType */ - *value_s32 = netif->link_type; - value_len = sizeof(*value_s32); - break; - case 4: /* ifMtu */ - *value_s32 = netif->mtu; - value_len = sizeof(*value_s32); - break; - case 5: /* ifSpeed */ - *value_u32 = netif->link_speed; - value_len = sizeof(*value_u32); - break; - case 6: /* ifPhysAddress */ - value_len = sizeof(netif->hwaddr); - MEMCPY(value, &netif->hwaddr, value_len); - break; - case 7: /* ifAdminStatus */ - if (netif_is_up(netif)) { - *value_s32 = iftable_ifOperStatus_up; - } else { - *value_s32 = iftable_ifOperStatus_down; - } - value_len = sizeof(*value_s32); - break; - case 8: /* ifOperStatus */ - if (netif_is_up(netif)) { - if (netif_is_link_up(netif)) { - *value_s32 = iftable_ifAdminStatus_up; - } else { - *value_s32 = iftable_ifAdminStatus_lowerLayerDown; - } - } else { - *value_s32 = iftable_ifAdminStatus_down; - } - value_len = sizeof(*value_s32); - break; - case 9: /* ifLastChange */ - *value_u32 = netif->ts; - value_len = sizeof(*value_u32); - break; - case 10: /* ifInOctets */ - *value_u32 = netif->mib2_counters.ifinoctets; - value_len = sizeof(*value_u32); - break; - case 11: /* ifInUcastPkts */ - *value_u32 = netif->mib2_counters.ifinucastpkts; - value_len = sizeof(*value_u32); - break; - case 12: /* ifInNUcastPkts */ - *value_u32 = netif->mib2_counters.ifinnucastpkts; - value_len = sizeof(*value_u32); - break; - case 13: /* ifInDiscards */ - *value_u32 = netif->mib2_counters.ifindiscards; - value_len = sizeof(*value_u32); - break; - case 14: /* ifInErrors */ - *value_u32 = netif->mib2_counters.ifinerrors; - value_len = sizeof(*value_u32); - break; - case 15: /* ifInUnkownProtos */ - *value_u32 = netif->mib2_counters.ifinunknownprotos; - value_len = sizeof(*value_u32); - break; - case 16: /* ifOutOctets */ - *value_u32 = netif->mib2_counters.ifoutoctets; - value_len = sizeof(*value_u32); - break; - case 17: /* ifOutUcastPkts */ - *value_u32 = netif->mib2_counters.ifoutucastpkts; - value_len = sizeof(*value_u32); - break; - case 18: /* ifOutNUcastPkts */ - *value_u32 = netif->mib2_counters.ifoutnucastpkts; - value_len = sizeof(*value_u32); - break; - case 19: /* ifOutDiscarts */ - *value_u32 = netif->mib2_counters.ifoutdiscards; - value_len = sizeof(*value_u32); - break; - case 20: /* ifOutErrors */ - *value_u32 = netif->mib2_counters.ifouterrors; - value_len = sizeof(*value_u32); - break; - case 21: /* ifOutQLen */ - *value_u32 = iftable_ifOutQLen; - value_len = sizeof(*value_u32); - break; - /** @note returning zeroDotZero (0.0) no media specific MIB support */ - case 22: /* ifSpecific */ - value_len = snmp_zero_dot_zero.len * sizeof(u32_t); - MEMCPY(value, snmp_zero_dot_zero.id, value_len); - break; - default: - return 0; - } - - return value_len; -} - -#if !SNMP_SAFE_REQUESTS - -static snmp_err_t -interfaces_Table_set_test(struct snmp_node_instance* instance, u16_t len, void *value) -{ - s32_t *sint_ptr = (s32_t*)value; - - /* stack should never call this method for another column, - because all other columns are set to readonly */ - LWIP_ASSERT("Invalid column", (SNMP_TABLE_GET_COLUMN_FROM_OID(instance->instance_oid.id) == 7)); - LWIP_UNUSED_ARG(len); - - if (*sint_ptr == 1 || *sint_ptr == 2) { - return SNMP_ERR_NOERROR; - } - - return SNMP_ERR_WRONGVALUE; -} - -static snmp_err_t -interfaces_Table_set_value(struct snmp_node_instance* instance, u16_t len, void *value) -{ - struct netif *netif = (struct netif*)instance->reference.ptr; - s32_t *sint_ptr = (s32_t*)value; - - /* stack should never call this method for another column, - because all other columns are set to readonly */ - LWIP_ASSERT("Invalid column", (SNMP_TABLE_GET_COLUMN_FROM_OID(instance->instance_oid.id) == 7)); - LWIP_UNUSED_ARG(len); - - if (*sint_ptr == 1) { - netif_set_up(netif); - } else if (*sint_ptr == 2) { - netif_set_down(netif); - } - - return SNMP_ERR_NOERROR; -} - -#endif /* SNMP_SAFE_REQUESTS */ - -static const struct snmp_scalar_node interfaces_Number = SNMP_SCALAR_CREATE_NODE_READONLY(1, SNMP_ASN1_TYPE_INTEGER, interfaces_get_value); - -static const struct snmp_table_col_def interfaces_Table_columns[] = { - { 1, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifIndex */ - { 2, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifDescr */ - { 3, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifType */ - { 4, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifMtu */ - { 5, SNMP_ASN1_TYPE_GAUGE, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifSpeed */ - { 6, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifPhysAddress */ -#if !SNMP_SAFE_REQUESTS - { 7, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_WRITE }, /* ifAdminStatus */ -#else - { 7, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifAdminStatus */ -#endif - { 8, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOperStatus */ - { 9, SNMP_ASN1_TYPE_TIMETICKS, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifLastChange */ - { 10, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInOctets */ - { 11, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInUcastPkts */ - { 12, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInNUcastPkts */ - { 13, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInDiscarts */ - { 14, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInErrors */ - { 15, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifInUnkownProtos */ - { 16, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutOctets */ - { 17, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutUcastPkts */ - { 18, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutNUcastPkts */ - { 19, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutDiscarts */ - { 20, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutErrors */ - { 21, SNMP_ASN1_TYPE_GAUGE, SNMP_NODE_INSTANCE_READ_ONLY }, /* ifOutQLen */ - { 22, SNMP_ASN1_TYPE_OBJECT_ID, SNMP_NODE_INSTANCE_READ_ONLY } /* ifSpecific */ -}; - -#if !SNMP_SAFE_REQUESTS -static const struct snmp_table_node interfaces_Table = SNMP_TABLE_CREATE( - 2, interfaces_Table_columns, - interfaces_Table_get_cell_instance, interfaces_Table_get_next_cell_instance, - interfaces_Table_get_value, interfaces_Table_set_test, interfaces_Table_set_value); -#else -static const struct snmp_table_node interfaces_Table = SNMP_TABLE_CREATE( - 2, interfaces_Table_columns, - interfaces_Table_get_cell_instance, interfaces_Table_get_next_cell_instance, - interfaces_Table_get_value, NULL, NULL); -#endif - -/* the following nodes access variables in LWIP stack from SNMP worker thread and must therefore be synced to LWIP (TCPIP) thread */ -CREATE_LWIP_SYNC_NODE(1, interfaces_Number) -CREATE_LWIP_SYNC_NODE(2, interfaces_Table) - -static const struct snmp_node* const interface_nodes[] = { - &SYNC_NODE_NAME(interfaces_Number).node.node, - &SYNC_NODE_NAME(interfaces_Table).node.node -}; - -const struct snmp_tree_node snmp_mib2_interface_root = SNMP_CREATE_TREE_NODE(2, interface_nodes); - -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_ip.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_ip.c deleted file mode 100644 index 4f05180a39625328a1c19fbaa9d9fbc95e9a653b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_ip.c +++ /dev/null @@ -1,743 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) IP objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/stats.h" -#include "lwip/netif.h" -#include "lwip/ip.h" -#include "lwip/etharp.h" - -#if LWIP_SNMP && SNMP_LWIP_MIB2 - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - -#if LWIP_IPV4 -/* --- ip .1.3.6.1.2.1.4 ----------------------------------------------------- */ - -static s16_t -ip_get_value(struct snmp_node_instance* instance, void* value) -{ - s32_t* sint_ptr = (s32_t*)value; - u32_t* uint_ptr = (u32_t*)value; - - switch (instance->node->oid) { - case 1: /* ipForwarding */ -#if IP_FORWARD - /* forwarding */ - *sint_ptr = 1; -#else - /* not-forwarding */ - *sint_ptr = 2; -#endif - return sizeof(*sint_ptr); - case 2: /* ipDefaultTTL */ - *sint_ptr = IP_DEFAULT_TTL; - return sizeof(*sint_ptr); - case 3: /* ipInReceives */ - *uint_ptr = STATS_GET(mib2.ipinreceives); - return sizeof(*uint_ptr); - case 4: /* ipInHdrErrors */ - *uint_ptr = STATS_GET(mib2.ipinhdrerrors); - return sizeof(*uint_ptr); - case 5: /* ipInAddrErrors */ - *uint_ptr = STATS_GET(mib2.ipinaddrerrors); - return sizeof(*uint_ptr); - case 6: /* ipForwDatagrams */ - *uint_ptr = STATS_GET(mib2.ipforwdatagrams); - return sizeof(*uint_ptr); - case 7: /* ipInUnknownProtos */ - *uint_ptr = STATS_GET(mib2.ipinunknownprotos); - return sizeof(*uint_ptr); - case 8: /* ipInDiscards */ - *uint_ptr = STATS_GET(mib2.ipindiscards); - return sizeof(*uint_ptr); - case 9: /* ipInDelivers */ - *uint_ptr = STATS_GET(mib2.ipindelivers); - return sizeof(*uint_ptr); - case 10: /* ipOutRequests */ - *uint_ptr = STATS_GET(mib2.ipoutrequests); - return sizeof(*uint_ptr); - case 11: /* ipOutDiscards */ - *uint_ptr = STATS_GET(mib2.ipoutdiscards); - return sizeof(*uint_ptr); - case 12: /* ipOutNoRoutes */ - *uint_ptr = STATS_GET(mib2.ipoutnoroutes); - return sizeof(*uint_ptr); - case 13: /* ipReasmTimeout */ -#if IP_REASSEMBLY - *sint_ptr = IP_REASS_MAXAGE; -#else - *sint_ptr = 0; -#endif - return sizeof(*sint_ptr); - case 14: /* ipReasmReqds */ - *uint_ptr = STATS_GET(mib2.ipreasmreqds); - return sizeof(*uint_ptr); - case 15: /* ipReasmOKs */ - *uint_ptr = STATS_GET(mib2.ipreasmoks); - return sizeof(*uint_ptr); - case 16: /* ipReasmFails */ - *uint_ptr = STATS_GET(mib2.ipreasmfails); - return sizeof(*uint_ptr); - case 17: /* ipFragOKs */ - *uint_ptr = STATS_GET(mib2.ipfragoks); - return sizeof(*uint_ptr); - case 18: /* ipFragFails */ - *uint_ptr = STATS_GET(mib2.ipfragfails); - return sizeof(*uint_ptr); - case 19: /* ipFragCreates */ - *uint_ptr = STATS_GET(mib2.ipfragcreates); - return sizeof(*uint_ptr); - case 23: /* ipRoutingDiscards: not supported -> always 0 */ - *uint_ptr = 0; - return sizeof(*uint_ptr); - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_value(): unknown id: %"S32_F"\n", instance->node->oid)); - break; - } - - return 0; -} - -/** - * Test ip object value before setting. - * - * @param instance node instance - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value from. - * - * @note we allow set if the value matches the hardwired value, - * otherwise return badvalue. - */ -static snmp_err_t -ip_set_test(struct snmp_node_instance* instance, u16_t len, void *value) -{ - snmp_err_t ret = SNMP_ERR_WRONGVALUE; - s32_t *sint_ptr = (s32_t*)value; - - LWIP_UNUSED_ARG(len); - switch (instance->node->oid) { - case 1: /* ipForwarding */ -#if IP_FORWARD - /* forwarding */ - if (*sint_ptr == 1) -#else - /* not-forwarding */ - if (*sint_ptr == 2) -#endif - { - ret = SNMP_ERR_NOERROR; - } - break; - case 2: /* ipDefaultTTL */ - if (*sint_ptr == IP_DEFAULT_TTL) { - ret = SNMP_ERR_NOERROR; - } - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_set_test(): unknown id: %"S32_F"\n", instance->node->oid)); - break; - } - - return ret; -} - -static snmp_err_t -ip_set_value(struct snmp_node_instance* instance, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(instance); - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value); - /* nothing to do here because in set_test we only accept values being the same as our own stored value -> no need to store anything */ - return SNMP_ERR_NOERROR; -} - -/* --- ipAddrTable --- */ - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range ip_AddrTable_oid_ranges[] = { - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff } /* IP D */ -}; - -static snmp_err_t -ip_AddrTable_get_cell_value_core(struct netif *netif, const u32_t* column, union snmp_variant_value* value, u32_t* value_len) -{ - LWIP_UNUSED_ARG(value_len); - - switch (*column) { - case 1: /* ipAdEntAddr */ - value->u32 = netif_ip4_addr(netif)->addr; - break; - case 2: /* ipAdEntIfIndex */ - value->u32 = netif_to_num(netif); - break; - case 3: /* ipAdEntNetMask */ - value->u32 = netif_ip4_netmask(netif)->addr; - break; - case 4: /* ipAdEntBcastAddr */ - /* lwIP oddity, there's no broadcast - address in the netif we can rely on */ - value->u32 = IPADDR_BROADCAST & 1; - break; - case 5: /* ipAdEntReasmMaxSize */ -#if IP_REASSEMBLY - /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs, - * but only if receiving one fragmented packet at a time. - * The current solution is to calculate for 2 simultaneous packets... - */ - value->u32 = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) * - (PBUF_POOL_BUFSIZE - PBUF_LINK_ENCAPSULATION_HLEN - PBUF_LINK_HLEN - IP_HLEN))); -#else - /** @todo returning MTU would be a bad thing and - returning a wild guess like '576' isn't good either */ - value->u32 = 0; -#endif - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -ip_AddrTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip4_addr_t ip; - struct netif *netif; - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, ip_AddrTable_oid_ranges, LWIP_ARRAYSIZE(ip_AddrTable_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get IP from incoming OID */ - snmp_oid_to_ip4(&row_oid[0], &ip); /* we know it succeeds because of oid_in_range check above */ - - /* find netif with requested ip */ - netif = netif_list; - while (netif != NULL) { - if (ip4_addr_cmp(&ip, netif_ip4_addr(netif))) { - /* fill in object properties */ - return ip_AddrTable_get_cell_value_core(netif, column, value, value_len); - } - - netif = netif->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -ip_AddrTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct netif *netif; - struct snmp_next_oid_state state; - u32_t result_temp[LWIP_ARRAYSIZE(ip_AddrTable_oid_ranges)]; - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(ip_AddrTable_oid_ranges)); - - /* iterate over all possible OIDs to find the next one */ - netif = netif_list; - while (netif != NULL) { - u32_t test_oid[LWIP_ARRAYSIZE(ip_AddrTable_oid_ranges)]; - snmp_ip4_to_oid(netif_ip4_addr(netif), &test_oid[0]); - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(ip_AddrTable_oid_ranges), netif); - - netif = netif->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return ip_AddrTable_get_cell_value_core((struct netif*)state.reference, column, value, value_len); - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -/* --- ipRouteTable --- */ - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range ip_RouteTable_oid_ranges[] = { - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff }, /* IP D */ -}; - -static snmp_err_t -ip_RouteTable_get_cell_value_core(struct netif *netif, u8_t default_route, const u32_t* column, union snmp_variant_value* value, u32_t* value_len) -{ - switch (*column) { - case 1: /* ipRouteDest */ - if (default_route) { - /* default rte has 0.0.0.0 dest */ - value->u32 = IP4_ADDR_ANY4->addr; - } else { - /* netifs have netaddress dest */ - ip4_addr_t tmp; - ip4_addr_get_network(&tmp, netif_ip4_addr(netif), netif_ip4_netmask(netif)); - value->u32 = tmp.addr; - } - break; - case 2: /* ipRouteIfIndex */ - value->u32 = netif_to_num(netif); - break; - case 3: /* ipRouteMetric1 */ - if (default_route) { - value->s32 = 1; /* default */ - } else { - value->s32 = 0; /* normal */ - } - break; - case 4: /* ipRouteMetric2 */ - case 5: /* ipRouteMetric3 */ - case 6: /* ipRouteMetric4 */ - value->s32 = -1; /* none */ - break; - case 7: /* ipRouteNextHop */ - if (default_route) { - /* default rte: gateway */ - value->u32 = netif_ip4_gw(netif)->addr; - } else { - /* other rtes: netif ip_addr */ - value->u32 = netif_ip4_addr(netif)->addr; - } - break; - case 8: /* ipRouteType */ - if (default_route) { - /* default rte is indirect */ - value->u32 = 4; /* indirect */ - } else { - /* other rtes are direct */ - value->u32 = 3; /* direct */ - } - break; - case 9: /* ipRouteProto */ - /* locally defined routes */ - value->u32 = 2; /* local */ - break; - case 10: /* ipRouteAge */ - /* @todo (sysuptime - timestamp last change) / 100 */ - value->u32 = 0; - break; - case 11: /* ipRouteMask */ - if (default_route) { - /* default rte use 0.0.0.0 mask */ - value->u32 = IP4_ADDR_ANY4->addr; - } else { - /* other rtes use netmask */ - value->u32 = netif_ip4_netmask(netif)->addr; - } - break; - case 12: /* ipRouteMetric5 */ - value->s32 = -1; /* none */ - break; - case 13: /* ipRouteInfo */ - value->const_ptr = snmp_zero_dot_zero.id; - *value_len = snmp_zero_dot_zero.len * sizeof(u32_t); - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -ip_RouteTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip4_addr_t test_ip; - struct netif *netif; - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, ip_RouteTable_oid_ranges, LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get IP and port from incoming OID */ - snmp_oid_to_ip4(&row_oid[0], &test_ip); /* we know it succeeds because of oid_in_range check above */ - - /* default route is on default netif */ - if (ip4_addr_isany_val(test_ip) && (netif_default != NULL)) { - /* fill in object properties */ - return ip_RouteTable_get_cell_value_core(netif_default, 1, column, value, value_len); - } - - /* find netif with requested route */ - netif = netif_list; - while (netif != NULL) { - ip4_addr_t dst; - ip4_addr_get_network(&dst, netif_ip4_addr(netif), netif_ip4_netmask(netif)); - - if (ip4_addr_cmp(&dst, &test_ip)) { - /* fill in object properties */ - return ip_RouteTable_get_cell_value_core(netif, 0, column, value, value_len); - } - - netif = netif->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -ip_RouteTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct netif *netif; - struct snmp_next_oid_state state; - u32_t result_temp[LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges)]; - u32_t test_oid[LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges)]; - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges)); - - /* check default route */ - if (netif_default != NULL) { - snmp_ip4_to_oid(IP4_ADDR_ANY4, &test_oid[0]); - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges), netif_default); - } - - /* iterate over all possible OIDs to find the next one */ - netif = netif_list; - while (netif != NULL) { - ip4_addr_t dst; - ip4_addr_get_network(&dst, netif_ip4_addr(netif), netif_ip4_netmask(netif)); - - /* check generated OID: is it a candidate for the next one? */ - if (!ip4_addr_isany_val(dst)) { - snmp_ip4_to_oid(&dst, &test_oid[0]); - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(ip_RouteTable_oid_ranges), netif); - } - - netif = netif->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - ip4_addr_t dst; - snmp_oid_to_ip4(&result_temp[0], &dst); - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return ip_RouteTable_get_cell_value_core((struct netif*)state.reference, ip4_addr_isany_val(dst), column, value, value_len); - } else { - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; - } -} - -#if LWIP_ARP && LWIP_IPV4 -/* --- ipNetToMediaTable --- */ - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range ip_NetToMediaTable_oid_ranges[] = { - { 1, 0xff }, /* IfIndex */ - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff } /* IP D */ -}; - -static snmp_err_t -ip_NetToMediaTable_get_cell_value_core(u8_t arp_table_index, const u32_t* column, union snmp_variant_value* value, u32_t* value_len) -{ - ip4_addr_t *ip; - struct netif *netif; - struct eth_addr *ethaddr; - - etharp_get_entry(arp_table_index, &ip, &netif, ðaddr); - - /* value */ - switch (*column) { - case 1: /* atIfIndex / ipNetToMediaIfIndex */ - value->u32 = netif_to_num(netif); - break; - case 2: /* atPhysAddress / ipNetToMediaPhysAddress */ - value->ptr = ethaddr; - *value_len = sizeof(*ethaddr); - break; - case 3: /* atNetAddress / ipNetToMediaNetAddress */ - value->u32 = ip->addr; - break; - case 4: /* ipNetToMediaType */ - value->u32 = 3; /* dynamic*/ - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -ip_NetToMediaTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip4_addr_t ip_in; - u8_t netif_index; - u8_t i; - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, ip_NetToMediaTable_oid_ranges, LWIP_ARRAYSIZE(ip_NetToMediaTable_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get IP from incoming OID */ - netif_index = (u8_t)row_oid[0]; - snmp_oid_to_ip4(&row_oid[1], &ip_in); /* we know it succeeds because of oid_in_range check above */ - - /* find requested entry */ - for (i=0; iid, row_oid->len, result_temp, LWIP_ARRAYSIZE(ip_NetToMediaTable_oid_ranges)); - - /* iterate over all possible OIDs to find the next one */ - for (i=0; i - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_scalar.h" - -#if LWIP_SNMP && SNMP_LWIP_MIB2 - -#define MIB2_AUTH_TRAPS_ENABLED 1 -#define MIB2_AUTH_TRAPS_DISABLED 2 - -/* --- snmp .1.3.6.1.2.1.11 ----------------------------------------------------- */ -static s16_t -snmp_get_value(const struct snmp_scalar_array_node_def *node, void *value) -{ - u32_t *uint_ptr = (u32_t*)value; - switch (node->oid) { - case 1: /* snmpInPkts */ - *uint_ptr = snmp_stats.inpkts; - break; - case 2: /* snmpOutPkts */ - *uint_ptr = snmp_stats.outpkts; - break; - case 3: /* snmpInBadVersions */ - *uint_ptr = snmp_stats.inbadversions; - break; - case 4: /* snmpInBadCommunityNames */ - *uint_ptr = snmp_stats.inbadcommunitynames; - break; - case 5: /* snmpInBadCommunityUses */ - *uint_ptr = snmp_stats.inbadcommunityuses; - break; - case 6: /* snmpInASNParseErrs */ - *uint_ptr = snmp_stats.inasnparseerrs; - break; - case 8: /* snmpInTooBigs */ - *uint_ptr = snmp_stats.intoobigs; - break; - case 9: /* snmpInNoSuchNames */ - *uint_ptr = snmp_stats.innosuchnames; - break; - case 10: /* snmpInBadValues */ - *uint_ptr = snmp_stats.inbadvalues; - break; - case 11: /* snmpInReadOnlys */ - *uint_ptr = snmp_stats.inreadonlys; - break; - case 12: /* snmpInGenErrs */ - *uint_ptr = snmp_stats.ingenerrs; - break; - case 13: /* snmpInTotalReqVars */ - *uint_ptr = snmp_stats.intotalreqvars; - break; - case 14: /* snmpInTotalSetVars */ - *uint_ptr = snmp_stats.intotalsetvars; - break; - case 15: /* snmpInGetRequests */ - *uint_ptr = snmp_stats.ingetrequests; - break; - case 16: /* snmpInGetNexts */ - *uint_ptr = snmp_stats.ingetnexts; - break; - case 17: /* snmpInSetRequests */ - *uint_ptr = snmp_stats.insetrequests; - break; - case 18: /* snmpInGetResponses */ - *uint_ptr = snmp_stats.ingetresponses; - break; - case 19: /* snmpInTraps */ - *uint_ptr = snmp_stats.intraps; - break; - case 20: /* snmpOutTooBigs */ - *uint_ptr = snmp_stats.outtoobigs; - break; - case 21: /* snmpOutNoSuchNames */ - *uint_ptr = snmp_stats.outnosuchnames; - break; - case 22: /* snmpOutBadValues */ - *uint_ptr = snmp_stats.outbadvalues; - break; - case 24: /* snmpOutGenErrs */ - *uint_ptr = snmp_stats.outgenerrs; - break; - case 25: /* snmpOutGetRequests */ - *uint_ptr = snmp_stats.outgetrequests; - break; - case 26: /* snmpOutGetNexts */ - *uint_ptr = snmp_stats.outgetnexts; - break; - case 27: /* snmpOutSetRequests */ - *uint_ptr = snmp_stats.outsetrequests; - break; - case 28: /* snmpOutGetResponses */ - *uint_ptr = snmp_stats.outgetresponses; - break; - case 29: /* snmpOutTraps */ - *uint_ptr = snmp_stats.outtraps; - break; - case 30: /* snmpEnableAuthenTraps */ - if (snmp_get_auth_traps_enabled() == SNMP_AUTH_TRAPS_DISABLED) { - *uint_ptr = MIB2_AUTH_TRAPS_DISABLED; - } else { - *uint_ptr = MIB2_AUTH_TRAPS_ENABLED; - } - break; - case 31: /* snmpSilentDrops */ - *uint_ptr = 0; /* not supported */ - break; - case 32: /* snmpProxyDrops */ - *uint_ptr = 0; /* not supported */ - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_value(): unknown id: %"S32_F"\n", node->oid)); - return 0; - } - - return sizeof(*uint_ptr); -} - -static snmp_err_t -snmp_set_test(const struct snmp_scalar_array_node_def *node, u16_t len, void *value) -{ - snmp_err_t ret = SNMP_ERR_WRONGVALUE; - LWIP_UNUSED_ARG(len); - - if (node->oid == 30) { - /* snmpEnableAuthenTraps */ - s32_t *sint_ptr = (s32_t*)value; - - /* we should have writable non-volatile mem here */ - if ((*sint_ptr == MIB2_AUTH_TRAPS_DISABLED) || (*sint_ptr == MIB2_AUTH_TRAPS_ENABLED)) { - ret = SNMP_ERR_NOERROR; - } - } - return ret; -} - -static snmp_err_t -snmp_set_value(const struct snmp_scalar_array_node_def *node, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(len); - - if (node->oid == 30) { - /* snmpEnableAuthenTraps */ - s32_t *sint_ptr = (s32_t*)value; - if (*sint_ptr == MIB2_AUTH_TRAPS_DISABLED) { - snmp_set_auth_traps_enabled(SNMP_AUTH_TRAPS_DISABLED); - } else { - snmp_set_auth_traps_enabled(SNMP_AUTH_TRAPS_ENABLED); - } - } - - return SNMP_ERR_NOERROR; -} - -/* the following nodes access variables in SNMP stack (snmp_stats) from SNMP worker thread -> OK, no sync needed */ -static const struct snmp_scalar_array_node_def snmp_nodes[] = { - { 1, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInPkts */ - { 2, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutPkts */ - { 3, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInBadVersions */ - { 4, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInBadCommunityNames */ - { 5, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInBadCommunityUses */ - { 6, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInASNParseErrs */ - { 8, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInTooBigs */ - { 9, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInNoSuchNames */ - {10, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInBadValues */ - {11, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInReadOnlys */ - {12, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInGenErrs */ - {13, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInTotalReqVars */ - {14, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInTotalSetVars */ - {15, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInGetRequests */ - {16, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInGetNexts */ - {17, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInSetRequests */ - {18, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInGetResponses */ - {19, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpInTraps */ - {20, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutTooBigs */ - {21, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutNoSuchNames */ - {22, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutBadValues */ - {24, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutGenErrs */ - {25, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutGetRequests */ - {26, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutGetNexts */ - {27, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutSetRequests */ - {28, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutGetResponses */ - {29, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpOutTraps */ - {30, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_WRITE}, /* snmpEnableAuthenTraps */ - {31, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY}, /* snmpSilentDrops */ - {32, SNMP_ASN1_TYPE_COUNTER, SNMP_NODE_INSTANCE_READ_ONLY} /* snmpProxyDrops */ -}; - -const struct snmp_scalar_array_node snmp_mib2_snmp_root = SNMP_SCALAR_CREATE_ARRAY_NODE(11, snmp_nodes, snmp_get_value, snmp_set_test, snmp_set_value); - -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_system.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_system.c deleted file mode 100644 index 90e57805d248a2a0d502f45c494d5adb4a83d9dd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_system.c +++ /dev/null @@ -1,377 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) SYSTEM objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/sys.h" - -#include - -#if LWIP_SNMP && SNMP_LWIP_MIB2 - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - -/* --- system .1.3.6.1.2.1.1 ----------------------------------------------------- */ - -/** mib-2.system.sysDescr */ -static const u8_t sysdescr_default[] = SNMP_LWIP_MIB2_SYSDESC; -static const u8_t* sysdescr = sysdescr_default; -static const u16_t* sysdescr_len = NULL; /* use strlen for determining len */ - -/** mib-2.system.sysContact */ -static const u8_t syscontact_default[] = SNMP_LWIP_MIB2_SYSCONTACT; -static const u8_t* syscontact = syscontact_default; -static const u16_t* syscontact_len = NULL; /* use strlen for determining len */ -static u8_t* syscontact_wr = NULL; /* if writable, points to the same buffer as syscontact (required for correct constness) */ -static u16_t* syscontact_wr_len = NULL; /* if writable, points to the same buffer as syscontact_len (required for correct constness) */ -static u16_t syscontact_bufsize = 0; /* 0=not writable */ - -/** mib-2.system.sysName */ -static const u8_t sysname_default[] = SNMP_LWIP_MIB2_SYSNAME; -static const u8_t* sysname = sysname_default; -static const u16_t* sysname_len = NULL; /* use strlen for determining len */ -static u8_t* sysname_wr = NULL; /* if writable, points to the same buffer as sysname (required for correct constness) */ -static u16_t* sysname_wr_len = NULL; /* if writable, points to the same buffer as sysname_len (required for correct constness) */ -static u16_t sysname_bufsize = 0; /* 0=not writable */ - -/** mib-2.system.sysLocation */ -static const u8_t syslocation_default[] = SNMP_LWIP_MIB2_SYSLOCATION; -static const u8_t* syslocation = syslocation_default; -static const u16_t* syslocation_len = NULL; /* use strlen for determining len */ -static u8_t* syslocation_wr = NULL; /* if writable, points to the same buffer as syslocation (required for correct constness) */ -static u16_t* syslocation_wr_len = NULL; /* if writable, points to the same buffer as syslocation_len (required for correct constness) */ -static u16_t syslocation_bufsize = 0; /* 0=not writable */ - -/** - * @ingroup snmp_mib2 - * Initializes sysDescr pointers. - * - * @param str if non-NULL then copy str pointer - * @param len points to string length, excluding zero terminator - */ -void -snmp_mib2_set_sysdescr(const u8_t *str, const u16_t *len) -{ - if (str != NULL) { - sysdescr = str; - sysdescr_len = len; - } -} - -/** - * @ingroup snmp_mib2 - * Initializes sysContact pointers - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator. - * if set to NULL it is assumed that ocstr is NULL-terminated. - * @param bufsize size of the buffer in bytes. - * (this is required because the buffer can be overwritten by snmp-set) - * if ocstrlen is NULL buffer needs space for terminating 0 byte. - * otherwise complete buffer is used for string. - * if bufsize is set to 0, the value is regarded as read-only. - */ -void -snmp_mib2_set_syscontact(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize) -{ - if (ocstr != NULL) { - syscontact = ocstr; - syscontact_wr = ocstr; - syscontact_len = ocstrlen; - syscontact_wr_len = ocstrlen; - syscontact_bufsize = bufsize; - } -} - -/** - * @ingroup snmp_mib2 - * see \ref snmp_mib2_set_syscontact but set pointer to readonly memory - */ -void -snmp_mib2_set_syscontact_readonly(const u8_t *ocstr, const u16_t *ocstrlen) -{ - if (ocstr != NULL) { - syscontact = ocstr; - syscontact_len = ocstrlen; - syscontact_wr = NULL; - syscontact_wr_len = NULL; - syscontact_bufsize = 0; - } -} - - -/** - * @ingroup snmp_mib2 - * Initializes sysName pointers - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator. - * if set to NULL it is assumed that ocstr is NULL-terminated. - * @param bufsize size of the buffer in bytes. - * (this is required because the buffer can be overwritten by snmp-set) - * if ocstrlen is NULL buffer needs space for terminating 0 byte. - * otherwise complete buffer is used for string. - * if bufsize is set to 0, the value is regarded as read-only. - */ -void -snmp_mib2_set_sysname(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize) -{ - if (ocstr != NULL) { - sysname = ocstr; - sysname_wr = ocstr; - sysname_len = ocstrlen; - sysname_wr_len = ocstrlen; - sysname_bufsize = bufsize; - } -} - -/** - * @ingroup snmp_mib2 - * see \ref snmp_mib2_set_sysname but set pointer to readonly memory - */ -void -snmp_mib2_set_sysname_readonly(const u8_t *ocstr, const u16_t *ocstrlen) -{ - if (ocstr != NULL) { - sysname = ocstr; - sysname_len = ocstrlen; - sysname_wr = NULL; - sysname_wr_len = NULL; - sysname_bufsize = 0; - } -} - -/** - * @ingroup snmp_mib2 - * Initializes sysLocation pointers - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator. - * if set to NULL it is assumed that ocstr is NULL-terminated. - * @param bufsize size of the buffer in bytes. - * (this is required because the buffer can be overwritten by snmp-set) - * if ocstrlen is NULL buffer needs space for terminating 0 byte. - * otherwise complete buffer is used for string. - * if bufsize is set to 0, the value is regarded as read-only. - */ -void -snmp_mib2_set_syslocation(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize) -{ - if (ocstr != NULL) { - syslocation = ocstr; - syslocation_wr = ocstr; - syslocation_len = ocstrlen; - syslocation_wr_len = ocstrlen; - syslocation_bufsize = bufsize; - } -} - -/** - * @ingroup snmp_mib2 - * see \ref snmp_mib2_set_syslocation but set pointer to readonly memory - */ -void -snmp_mib2_set_syslocation_readonly(const u8_t *ocstr, const u16_t *ocstrlen) -{ - if (ocstr != NULL) { - syslocation = ocstr; - syslocation_len = ocstrlen; - syslocation_wr = NULL; - syslocation_wr_len = NULL; - syslocation_bufsize = 0; - } -} - - -static s16_t -system_get_value(const struct snmp_scalar_array_node_def *node, void *value) -{ - const u8_t* var = NULL; - const s16_t* var_len; - u16_t result; - - switch (node->oid) { - case 1: /* sysDescr */ - var = sysdescr; - var_len = (const s16_t*)sysdescr_len; - break; - case 2: /* sysObjectID */ - { - const struct snmp_obj_id* dev_enterprise_oid = snmp_get_device_enterprise_oid(); - MEMCPY(value, dev_enterprise_oid->id, dev_enterprise_oid->len * sizeof(u32_t)); - return dev_enterprise_oid->len * sizeof(u32_t); - } - case 3: /* sysUpTime */ - MIB2_COPY_SYSUPTIME_TO((u32_t*)value); - return sizeof(u32_t); - case 4: /* sysContact */ - var = syscontact; - var_len = (const s16_t*)syscontact_len; - break; - case 5: /* sysName */ - var = sysname; - var_len = (const s16_t*)sysname_len; - break; - case 6: /* sysLocation */ - var = syslocation; - var_len = (const s16_t*)syslocation_len; - break; - case 7: /* sysServices */ - *(s32_t*)value = SNMP_SYSSERVICES; - return sizeof(s32_t); - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_value(): unknown id: %"S32_F"\n", node->oid)); - return 0; - } - - /* handle string values (OID 1,4,5 and 6) */ - LWIP_ASSERT("", (value != NULL)); - if (var_len == NULL) { - result = (s16_t)strlen((const char*)var); - } else { - result = *var_len; - } - MEMCPY(value, var, result); - return result; -} - -static snmp_err_t -system_set_test(const struct snmp_scalar_array_node_def *node, u16_t len, void *value) -{ - snmp_err_t ret = SNMP_ERR_WRONGVALUE; - const u16_t* var_bufsize = NULL; - const u16_t* var_wr_len; - - LWIP_UNUSED_ARG(value); - - switch (node->oid) { - case 4: /* sysContact */ - var_bufsize = &syscontact_bufsize; - var_wr_len = syscontact_wr_len; - break; - case 5: /* sysName */ - var_bufsize = &sysname_bufsize; - var_wr_len = sysname_wr_len; - break; - case 6: /* sysLocation */ - var_bufsize = &syslocation_bufsize; - var_wr_len = syslocation_wr_len; - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_set_test(): unknown id: %"S32_F"\n", node->oid)); - return ret; - } - - /* check if value is writable at all */ - if (*var_bufsize > 0) { - if (var_wr_len == NULL) { - /* we have to take the terminating 0 into account */ - if (len < *var_bufsize) { - ret = SNMP_ERR_NOERROR; - } - } else { - if (len <= *var_bufsize) { - ret = SNMP_ERR_NOERROR; - } - } - } else { - ret = SNMP_ERR_NOTWRITABLE; - } - - return ret; -} - -static snmp_err_t -system_set_value(const struct snmp_scalar_array_node_def *node, u16_t len, void *value) -{ - u8_t* var_wr = NULL; - u16_t* var_wr_len; - - switch (node->oid) { - case 4: /* sysContact */ - var_wr = syscontact_wr; - var_wr_len = syscontact_wr_len; - break; - case 5: /* sysName */ - var_wr = sysname_wr; - var_wr_len = sysname_wr_len; - break; - case 6: /* sysLocation */ - var_wr = syslocation_wr; - var_wr_len = syslocation_wr_len; - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_set_value(): unknown id: %"S32_F"\n", node->oid)); - return SNMP_ERR_GENERROR; - } - - /* no need to check size of target buffer, this was already done in set_test method */ - LWIP_ASSERT("", var_wr != NULL); - MEMCPY(var_wr, value, len); - - if (var_wr_len == NULL) { - /* add terminating 0 */ - var_wr[len] = 0; - } else { - *var_wr_len = len; - } - - return SNMP_ERR_NOERROR; -} - -static const struct snmp_scalar_array_node_def system_nodes[] = { - {1, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_ONLY}, /* sysDescr */ - {2, SNMP_ASN1_TYPE_OBJECT_ID, SNMP_NODE_INSTANCE_READ_ONLY}, /* sysObjectID */ - {3, SNMP_ASN1_TYPE_TIMETICKS, SNMP_NODE_INSTANCE_READ_ONLY}, /* sysUpTime */ - {4, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_WRITE}, /* sysContact */ - {5, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_WRITE}, /* sysName */ - {6, SNMP_ASN1_TYPE_OCTET_STRING, SNMP_NODE_INSTANCE_READ_WRITE}, /* sysLocation */ - {7, SNMP_ASN1_TYPE_INTEGER, SNMP_NODE_INSTANCE_READ_ONLY} /* sysServices */ -}; - -const struct snmp_scalar_array_node snmp_mib2_system_node = SNMP_SCALAR_CREATE_ARRAY_NODE(1, system_nodes, system_get_value, system_set_test, system_set_value); - -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_tcp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_tcp.c deleted file mode 100644 index 21f6965662c68c2482d8d82eeb0a14078686f9a4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_tcp.c +++ /dev/null @@ -1,594 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) TCP objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/tcp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/stats.h" - -#include - -#if LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_TCP - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - -/* --- tcp .1.3.6.1.2.1.6 ----------------------------------------------------- */ - -static s16_t -tcp_get_value(struct snmp_node_instance* instance, void* value) -{ - u32_t *uint_ptr = (u32_t*)value; - s32_t *sint_ptr = (s32_t*)value; - - switch (instance->node->oid) { - case 1: /* tcpRtoAlgorithm, vanj(4) */ - *sint_ptr = 4; - return sizeof(*sint_ptr); - case 2: /* tcpRtoMin */ - /* @todo not the actual value, a guess, - needs to be calculated */ - *sint_ptr = 1000; - return sizeof(*sint_ptr); - case 3: /* tcpRtoMax */ - /* @todo not the actual value, a guess, - needs to be calculated */ - *sint_ptr = 60000; - return sizeof(*sint_ptr); - case 4: /* tcpMaxConn */ - *sint_ptr = MEMP_NUM_TCP_PCB; - return sizeof(*sint_ptr); - case 5: /* tcpActiveOpens */ - *uint_ptr = STATS_GET(mib2.tcpactiveopens); - return sizeof(*uint_ptr); - case 6: /* tcpPassiveOpens */ - *uint_ptr = STATS_GET(mib2.tcppassiveopens); - return sizeof(*uint_ptr); - case 7: /* tcpAttemptFails */ - *uint_ptr = STATS_GET(mib2.tcpattemptfails); - return sizeof(*uint_ptr); - case 8: /* tcpEstabResets */ - *uint_ptr = STATS_GET(mib2.tcpestabresets); - return sizeof(*uint_ptr); - case 9: /* tcpCurrEstab */ - { - u16_t tcpcurrestab = 0; - struct tcp_pcb *pcb = tcp_active_pcbs; - while (pcb != NULL) { - if ((pcb->state == ESTABLISHED) || - (pcb->state == CLOSE_WAIT)) { - tcpcurrestab++; - } - pcb = pcb->next; - } - *uint_ptr = tcpcurrestab; - } - return sizeof(*uint_ptr); - case 10: /* tcpInSegs */ - *uint_ptr = STATS_GET(mib2.tcpinsegs); - return sizeof(*uint_ptr); - case 11: /* tcpOutSegs */ - *uint_ptr = STATS_GET(mib2.tcpoutsegs); - return sizeof(*uint_ptr); - case 12: /* tcpRetransSegs */ - *uint_ptr = STATS_GET(mib2.tcpretranssegs); - return sizeof(*uint_ptr); - case 14: /* tcpInErrs */ - *uint_ptr = STATS_GET(mib2.tcpinerrs); - return sizeof(*uint_ptr); - case 15: /* tcpOutRsts */ - *uint_ptr = STATS_GET(mib2.tcpoutrsts); - return sizeof(*uint_ptr); - case 17: /* tcpHCInSegs */ - memset(value, 0, 2*sizeof(u32_t)); /* not supported */ - return 2*sizeof(u32_t); - case 18: /* tcpHCOutSegs */ - memset(value, 0, 2*sizeof(u32_t)); /* not supported */ - return 2*sizeof(u32_t); - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_value(): unknown id: %"S32_F"\n", instance->node->oid)); - break; - } - - return 0; -} - -/* --- tcpConnTable --- */ - -#if LWIP_IPV4 - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range tcp_ConnTable_oid_ranges[] = { - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff }, /* IP D */ - { 0, 0xffff }, /* Port */ - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff }, /* IP D */ - { 0, 0xffff } /* Port */ -}; - -static snmp_err_t -tcp_ConnTable_get_cell_value_core(struct tcp_pcb *pcb, const u32_t* column, union snmp_variant_value* value, u32_t* value_len) -{ - LWIP_UNUSED_ARG(value_len); - - /* value */ - switch (*column) { - case 1: /* tcpConnState */ - value->u32 = pcb->state + 1; - break; - case 2: /* tcpConnLocalAddress */ - value->u32 = ip_2_ip4(&pcb->local_ip)->addr; - break; - case 3: /* tcpConnLocalPort */ - value->u32 = pcb->local_port; - break; - case 4: /* tcpConnRemAddress */ - if (pcb->state == LISTEN) { - value->u32 = IP4_ADDR_ANY4->addr; - } else { - value->u32 = ip_2_ip4(&pcb->remote_ip)->addr; - } - break; - case 5: /* tcpConnRemPort */ - if (pcb->state == LISTEN) { - value->u32 = 0; - } else { - value->u32 = pcb->remote_port; - } - break; - default: - LWIP_ASSERT("invalid id", 0); - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -tcp_ConnTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - u8_t i; - ip4_addr_t local_ip; - ip4_addr_t remote_ip; - u16_t local_port; - u16_t remote_port; - struct tcp_pcb *pcb; - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, tcp_ConnTable_oid_ranges, LWIP_ARRAYSIZE(tcp_ConnTable_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get IPs and ports from incoming OID */ - snmp_oid_to_ip4(&row_oid[0], &local_ip); /* we know it succeeds because of oid_in_range check above */ - local_port = (u16_t)row_oid[4]; - snmp_oid_to_ip4(&row_oid[5], &remote_ip); /* we know it succeeds because of oid_in_range check above */ - remote_port = (u16_t)row_oid[9]; - - /* find tcp_pcb with requested ips and ports */ - for (i = 0; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { - pcb = *tcp_pcb_lists[i]; - - while (pcb != NULL) { - /* do local IP and local port match? */ - if (IP_IS_V4_VAL(pcb->local_ip) && - ip4_addr_cmp(&local_ip, ip_2_ip4(&pcb->local_ip)) && (local_port == pcb->local_port)) { - - /* PCBs in state LISTEN are not connected and have no remote_ip or remote_port */ - if (pcb->state == LISTEN) { - if (ip4_addr_cmp(&remote_ip, IP4_ADDR_ANY4) && (remote_port == 0)) { - /* fill in object properties */ - return tcp_ConnTable_get_cell_value_core(pcb, column, value, value_len); - } - } else { - if (IP_IS_V4_VAL(pcb->remote_ip) && - ip4_addr_cmp(&remote_ip, ip_2_ip4(&pcb->remote_ip)) && (remote_port == pcb->remote_port)) { - /* fill in object properties */ - return tcp_ConnTable_get_cell_value_core(pcb, column, value, value_len); - } - } - } - - pcb = pcb->next; - } - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -tcp_ConnTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - u8_t i; - struct tcp_pcb *pcb; - struct snmp_next_oid_state state; - u32_t result_temp[LWIP_ARRAYSIZE(tcp_ConnTable_oid_ranges)]; - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(tcp_ConnTable_oid_ranges)); - - /* iterate over all possible OIDs to find the next one */ - for (i = 0; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { - pcb = *tcp_pcb_lists[i]; - while (pcb != NULL) { - u32_t test_oid[LWIP_ARRAYSIZE(tcp_ConnTable_oid_ranges)]; - - if (IP_IS_V4_VAL(pcb->local_ip)) { - snmp_ip4_to_oid(ip_2_ip4(&pcb->local_ip), &test_oid[0]); - test_oid[4] = pcb->local_port; - - /* PCBs in state LISTEN are not connected and have no remote_ip or remote_port */ - if (pcb->state == LISTEN) { - snmp_ip4_to_oid(IP4_ADDR_ANY4, &test_oid[5]); - test_oid[9] = 0; - } else { - if (IP_IS_V6_VAL(pcb->remote_ip)) { /* should never happen */ - continue; - } - snmp_ip4_to_oid(ip_2_ip4(&pcb->remote_ip), &test_oid[5]); - test_oid[9] = pcb->remote_port; - } - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(tcp_ConnTable_oid_ranges), pcb); - } - - pcb = pcb->next; - } - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return tcp_ConnTable_get_cell_value_core((struct tcp_pcb*)state.reference, column, value, value_len); - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -#endif /* LWIP_IPV4 */ - -/* --- tcpConnectionTable --- */ - -static snmp_err_t -tcp_ConnectionTable_get_cell_value_core(const u32_t* column, struct tcp_pcb *pcb, union snmp_variant_value* value) -{ - /* all items except tcpConnectionState and tcpConnectionProcess are declared as not-accessible */ - switch (*column) { - case 7: /* tcpConnectionState */ - value->u32 = pcb->state + 1; - break; - case 8: /* tcpConnectionProcess */ - value->u32 = 0; /* not supported */ - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -tcp_ConnectionTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip_addr_t local_ip, remote_ip; - u16_t local_port, remote_port; - struct tcp_pcb *pcb; - u8_t idx = 0; - u8_t i; - struct tcp_pcb ** const tcp_pcb_nonlisten_lists[] = {&tcp_bound_pcbs, &tcp_active_pcbs, &tcp_tw_pcbs}; - - LWIP_UNUSED_ARG(value_len); - - /* tcpConnectionLocalAddressType + tcpConnectionLocalAddress + tcpConnectionLocalPort */ - idx += snmp_oid_to_ip_port(&row_oid[idx], row_oid_len-idx, &local_ip, &local_port); - if (idx == 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* tcpConnectionRemAddressType + tcpConnectionRemAddress + tcpConnectionRemPort */ - idx += snmp_oid_to_ip_port(&row_oid[idx], row_oid_len-idx, &remote_ip, &remote_port); - if (idx == 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* find tcp_pcb with requested ip and port*/ - for (i = 0; i < LWIP_ARRAYSIZE(tcp_pcb_nonlisten_lists); i++) { - pcb = *tcp_pcb_nonlisten_lists[i]; - - while (pcb != NULL) { - if (ip_addr_cmp(&local_ip, &pcb->local_ip) && - (local_port == pcb->local_port) && - ip_addr_cmp(&remote_ip, &pcb->remote_ip) && - (remote_port == pcb->remote_port)) { - /* fill in object properties */ - return tcp_ConnectionTable_get_cell_value_core(column, pcb, value); - } - pcb = pcb->next; - } - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -tcp_ConnectionTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct tcp_pcb *pcb; - struct snmp_next_oid_state state; - /* 1x tcpConnectionLocalAddressType + 1x OID len + 16x tcpConnectionLocalAddress + 1x tcpConnectionLocalPort - * 1x tcpConnectionRemAddressType + 1x OID len + 16x tcpConnectionRemAddress + 1x tcpConnectionRemPort */ - u32_t result_temp[38]; - u8_t i; - struct tcp_pcb ** const tcp_pcb_nonlisten_lists[] = {&tcp_bound_pcbs, &tcp_active_pcbs, &tcp_tw_pcbs}; - - LWIP_UNUSED_ARG(value_len); - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(result_temp)); - - /* iterate over all possible OIDs to find the next one */ - for (i = 0; i < LWIP_ARRAYSIZE(tcp_pcb_nonlisten_lists); i++) { - pcb = *tcp_pcb_nonlisten_lists[i]; - - while (pcb != NULL) { - u8_t idx = 0; - u32_t test_oid[LWIP_ARRAYSIZE(result_temp)]; - - /* tcpConnectionLocalAddressType + tcpConnectionLocalAddress + tcpConnectionLocalPort */ - idx += snmp_ip_port_to_oid(&pcb->local_ip, pcb->local_port, &test_oid[idx]); - - /* tcpConnectionRemAddressType + tcpConnectionRemAddress + tcpConnectionRemPort */ - idx += snmp_ip_port_to_oid(&pcb->remote_ip, pcb->remote_port, &test_oid[idx]); - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, idx, pcb); - - pcb = pcb->next; - } - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return tcp_ConnectionTable_get_cell_value_core(column, (struct tcp_pcb*)state.reference, value); - } else { - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; - } -} - -/* --- tcpListenerTable --- */ - -static snmp_err_t -tcp_ListenerTable_get_cell_value_core(const u32_t* column, union snmp_variant_value* value) -{ - /* all items except tcpListenerProcess are declared as not-accessible */ - switch (*column) { - case 4: /* tcpListenerProcess */ - value->u32 = 0; /* not supported */ - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -tcp_ListenerTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip_addr_t local_ip; - u16_t local_port; - struct tcp_pcb_listen *pcb; - u8_t idx = 0; - - LWIP_UNUSED_ARG(value_len); - - /* tcpListenerLocalAddressType + tcpListenerLocalAddress + tcpListenerLocalPort */ - idx += snmp_oid_to_ip_port(&row_oid[idx], row_oid_len-idx, &local_ip, &local_port); - if (idx == 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* find tcp_pcb with requested ip and port*/ - pcb = tcp_listen_pcbs.listen_pcbs; - while (pcb != NULL) { - if (ip_addr_cmp(&local_ip, &pcb->local_ip) && - (local_port == pcb->local_port)) { - /* fill in object properties */ - return tcp_ListenerTable_get_cell_value_core(column, value); - } - pcb = pcb->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -tcp_ListenerTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct tcp_pcb_listen *pcb; - struct snmp_next_oid_state state; - /* 1x tcpListenerLocalAddressType + 1x OID len + 16x tcpListenerLocalAddress + 1x tcpListenerLocalPort */ - u32_t result_temp[19]; - - LWIP_UNUSED_ARG(value_len); - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(result_temp)); - - /* iterate over all possible OIDs to find the next one */ - pcb = tcp_listen_pcbs.listen_pcbs; - while (pcb != NULL) { - u8_t idx = 0; - u32_t test_oid[LWIP_ARRAYSIZE(result_temp)]; - - /* tcpListenerLocalAddressType + tcpListenerLocalAddress + tcpListenerLocalPort */ - idx += snmp_ip_port_to_oid(&pcb->local_ip, pcb->local_port, &test_oid[idx]); - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, idx, NULL); - - pcb = pcb->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return tcp_ListenerTable_get_cell_value_core(column, value); - } else { - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; - } -} - -static const struct snmp_scalar_node tcp_RtoAlgorithm = SNMP_SCALAR_CREATE_NODE_READONLY(1, SNMP_ASN1_TYPE_INTEGER, tcp_get_value); -static const struct snmp_scalar_node tcp_RtoMin = SNMP_SCALAR_CREATE_NODE_READONLY(2, SNMP_ASN1_TYPE_INTEGER, tcp_get_value); -static const struct snmp_scalar_node tcp_RtoMax = SNMP_SCALAR_CREATE_NODE_READONLY(3, SNMP_ASN1_TYPE_INTEGER, tcp_get_value); -static const struct snmp_scalar_node tcp_MaxConn = SNMP_SCALAR_CREATE_NODE_READONLY(4, SNMP_ASN1_TYPE_INTEGER, tcp_get_value); -static const struct snmp_scalar_node tcp_ActiveOpens = SNMP_SCALAR_CREATE_NODE_READONLY(5, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_PassiveOpens = SNMP_SCALAR_CREATE_NODE_READONLY(6, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_AttemptFails = SNMP_SCALAR_CREATE_NODE_READONLY(7, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_EstabResets = SNMP_SCALAR_CREATE_NODE_READONLY(8, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_CurrEstab = SNMP_SCALAR_CREATE_NODE_READONLY(9, SNMP_ASN1_TYPE_GAUGE, tcp_get_value); -static const struct snmp_scalar_node tcp_InSegs = SNMP_SCALAR_CREATE_NODE_READONLY(10, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_OutSegs = SNMP_SCALAR_CREATE_NODE_READONLY(11, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_RetransSegs = SNMP_SCALAR_CREATE_NODE_READONLY(12, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_InErrs = SNMP_SCALAR_CREATE_NODE_READONLY(14, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_OutRsts = SNMP_SCALAR_CREATE_NODE_READONLY(15, SNMP_ASN1_TYPE_COUNTER, tcp_get_value); -static const struct snmp_scalar_node tcp_HCInSegs = SNMP_SCALAR_CREATE_NODE_READONLY(17, SNMP_ASN1_TYPE_COUNTER64, tcp_get_value); -static const struct snmp_scalar_node tcp_HCOutSegs = SNMP_SCALAR_CREATE_NODE_READONLY(18, SNMP_ASN1_TYPE_COUNTER64, tcp_get_value); - -#if LWIP_IPV4 -static const struct snmp_table_simple_col_def tcp_ConnTable_columns[] = { - { 1, SNMP_ASN1_TYPE_INTEGER, SNMP_VARIANT_VALUE_TYPE_U32 }, /* tcpConnState */ - { 2, SNMP_ASN1_TYPE_IPADDR, SNMP_VARIANT_VALUE_TYPE_U32 }, /* tcpConnLocalAddress */ - { 3, SNMP_ASN1_TYPE_INTEGER, SNMP_VARIANT_VALUE_TYPE_U32 }, /* tcpConnLocalPort */ - { 4, SNMP_ASN1_TYPE_IPADDR, SNMP_VARIANT_VALUE_TYPE_U32 }, /* tcpConnRemAddress */ - { 5, SNMP_ASN1_TYPE_INTEGER, SNMP_VARIANT_VALUE_TYPE_U32 } /* tcpConnRemPort */ -}; - -static const struct snmp_table_simple_node tcp_ConnTable = SNMP_TABLE_CREATE_SIMPLE(13, tcp_ConnTable_columns, tcp_ConnTable_get_cell_value, tcp_ConnTable_get_next_cell_instance_and_value); -#endif /* LWIP_IPV4 */ - -static const struct snmp_table_simple_col_def tcp_ConnectionTable_columns[] = { - /* all items except tcpConnectionState and tcpConnectionProcess are declared as not-accessible */ - { 7, SNMP_ASN1_TYPE_INTEGER, SNMP_VARIANT_VALUE_TYPE_U32 }, /* tcpConnectionState */ - { 8, SNMP_ASN1_TYPE_UNSIGNED32, SNMP_VARIANT_VALUE_TYPE_U32 } /* tcpConnectionProcess */ -}; - -static const struct snmp_table_simple_node tcp_ConnectionTable = SNMP_TABLE_CREATE_SIMPLE(19, tcp_ConnectionTable_columns, tcp_ConnectionTable_get_cell_value, tcp_ConnectionTable_get_next_cell_instance_and_value); - - -static const struct snmp_table_simple_col_def tcp_ListenerTable_columns[] = { - /* all items except tcpListenerProcess are declared as not-accessible */ - { 4, SNMP_ASN1_TYPE_UNSIGNED32, SNMP_VARIANT_VALUE_TYPE_U32 } /* tcpListenerProcess */ -}; - -static const struct snmp_table_simple_node tcp_ListenerTable = SNMP_TABLE_CREATE_SIMPLE(20, tcp_ListenerTable_columns, tcp_ListenerTable_get_cell_value, tcp_ListenerTable_get_next_cell_instance_and_value); - -/* the following nodes access variables in LWIP stack from SNMP worker thread and must therefore be synced to LWIP (TCPIP) thread */ -CREATE_LWIP_SYNC_NODE( 1, tcp_RtoAlgorithm) -CREATE_LWIP_SYNC_NODE( 2, tcp_RtoMin) -CREATE_LWIP_SYNC_NODE( 3, tcp_RtoMax) -CREATE_LWIP_SYNC_NODE( 4, tcp_MaxConn) -CREATE_LWIP_SYNC_NODE( 5, tcp_ActiveOpens) -CREATE_LWIP_SYNC_NODE( 6, tcp_PassiveOpens) -CREATE_LWIP_SYNC_NODE( 7, tcp_AttemptFails) -CREATE_LWIP_SYNC_NODE( 8, tcp_EstabResets) -CREATE_LWIP_SYNC_NODE( 9, tcp_CurrEstab) -CREATE_LWIP_SYNC_NODE(10, tcp_InSegs) -CREATE_LWIP_SYNC_NODE(11, tcp_OutSegs) -CREATE_LWIP_SYNC_NODE(12, tcp_RetransSegs) -#if LWIP_IPV4 -CREATE_LWIP_SYNC_NODE(13, tcp_ConnTable) -#endif /* LWIP_IPV4 */ -CREATE_LWIP_SYNC_NODE(14, tcp_InErrs) -CREATE_LWIP_SYNC_NODE(15, tcp_OutRsts) -CREATE_LWIP_SYNC_NODE(17, tcp_HCInSegs) -CREATE_LWIP_SYNC_NODE(18, tcp_HCOutSegs) -CREATE_LWIP_SYNC_NODE(19, tcp_ConnectionTable) -CREATE_LWIP_SYNC_NODE(20, tcp_ListenerTable) - -static const struct snmp_node* const tcp_nodes[] = { - &SYNC_NODE_NAME(tcp_RtoAlgorithm).node.node, - &SYNC_NODE_NAME(tcp_RtoMin).node.node, - &SYNC_NODE_NAME(tcp_RtoMax).node.node, - &SYNC_NODE_NAME(tcp_MaxConn).node.node, - &SYNC_NODE_NAME(tcp_ActiveOpens).node.node, - &SYNC_NODE_NAME(tcp_PassiveOpens).node.node, - &SYNC_NODE_NAME(tcp_AttemptFails).node.node, - &SYNC_NODE_NAME(tcp_EstabResets).node.node, - &SYNC_NODE_NAME(tcp_CurrEstab).node.node, - &SYNC_NODE_NAME(tcp_InSegs).node.node, - &SYNC_NODE_NAME(tcp_OutSegs).node.node, - &SYNC_NODE_NAME(tcp_RetransSegs).node.node, -#if LWIP_IPV4 - &SYNC_NODE_NAME(tcp_ConnTable).node.node, -#endif /* LWIP_IPV4 */ - &SYNC_NODE_NAME(tcp_InErrs).node.node, - &SYNC_NODE_NAME(tcp_OutRsts).node.node, - &SYNC_NODE_NAME(tcp_HCInSegs).node.node, - &SYNC_NODE_NAME(tcp_HCOutSegs).node.node, - &SYNC_NODE_NAME(tcp_ConnectionTable).node.node, - &SYNC_NODE_NAME(tcp_ListenerTable).node.node -}; - -const struct snmp_tree_node snmp_mib2_tcp_root = SNMP_CREATE_TREE_NODE(6, tcp_nodes); -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_TCP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_udp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_udp.c deleted file mode 100644 index 6a983df20bbaa3a85d1e2ff11f99ecbda402cdf3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_mib2_udp.c +++ /dev/null @@ -1,357 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) UDP objects and functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - * Christiaan Simons - */ - -#include "lwip/snmp.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_mib2.h" -#include "lwip/apps/snmp_table.h" -#include "lwip/apps/snmp_scalar.h" -#include "lwip/udp.h" -#include "lwip/stats.h" - -#include - -#if LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_UDP - -#if SNMP_USE_NETCONN -#define SYNC_NODE_NAME(node_name) node_name ## _synced -#define CREATE_LWIP_SYNC_NODE(oid, node_name) \ - static const struct snmp_threadsync_node node_name ## _synced = SNMP_CREATE_THREAD_SYNC_NODE(oid, &node_name.node, &snmp_mib2_lwip_locks); -#else -#define SYNC_NODE_NAME(node_name) node_name -#define CREATE_LWIP_SYNC_NODE(oid, node_name) -#endif - -/* --- udp .1.3.6.1.2.1.7 ----------------------------------------------------- */ - -static s16_t -udp_get_value(struct snmp_node_instance* instance, void* value) -{ - u32_t *uint_ptr = (u32_t*)value; - - switch (instance->node->oid) { - case 1: /* udpInDatagrams */ - *uint_ptr = STATS_GET(mib2.udpindatagrams); - return sizeof(*uint_ptr); - case 2: /* udpNoPorts */ - *uint_ptr = STATS_GET(mib2.udpnoports); - return sizeof(*uint_ptr); - case 3: /* udpInErrors */ - *uint_ptr = STATS_GET(mib2.udpinerrors); - return sizeof(*uint_ptr); - case 4: /* udpOutDatagrams */ - *uint_ptr = STATS_GET(mib2.udpoutdatagrams); - return sizeof(*uint_ptr); - case 8: /* udpHCInDatagrams */ - memset(value, 0, 2*sizeof(u32_t)); /* not supported */ - return 2*sizeof(u32_t); - case 9: /* udpHCOutDatagrams */ - memset(value, 0, 2*sizeof(u32_t)); /* not supported */ - return 2*sizeof(u32_t); - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_value(): unknown id: %"S32_F"\n", instance->node->oid)); - break; - } - - return 0; -} - -/* --- udpEndpointTable --- */ - -static snmp_err_t -udp_endpointTable_get_cell_value_core(const u32_t* column, union snmp_variant_value* value) -{ - /* all items except udpEndpointProcess are declared as not-accessible */ - switch (*column) { - case 8: /* udpEndpointProcess */ - value->u32 = 0; /* not supported */ - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -udp_endpointTable_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip_addr_t local_ip, remote_ip; - u16_t local_port, remote_port; - struct udp_pcb *pcb; - u8_t idx = 0; - - LWIP_UNUSED_ARG(value_len); - - /* udpEndpointLocalAddressType + udpEndpointLocalAddress + udpEndpointLocalPort */ - idx += snmp_oid_to_ip_port(&row_oid[idx], row_oid_len-idx, &local_ip, &local_port); - if (idx == 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* udpEndpointRemoteAddressType + udpEndpointRemoteAddress + udpEndpointRemotePort */ - idx += snmp_oid_to_ip_port(&row_oid[idx], row_oid_len-idx, &remote_ip, &remote_port); - if (idx == 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* udpEndpointInstance */ - if (row_oid_len < (idx+1)) { - return SNMP_ERR_NOSUCHINSTANCE; - } - if (row_oid[idx] != 0) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* find udp_pcb with requested ip and port*/ - pcb = udp_pcbs; - while (pcb != NULL) { - if (ip_addr_cmp(&local_ip, &pcb->local_ip) && - (local_port == pcb->local_port) && - ip_addr_cmp(&remote_ip, &pcb->remote_ip) && - (remote_port == pcb->remote_port)) { - /* fill in object properties */ - return udp_endpointTable_get_cell_value_core(column, value); - } - pcb = pcb->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -udp_endpointTable_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct udp_pcb *pcb; - struct snmp_next_oid_state state; - /* 1x udpEndpointLocalAddressType + 1x OID len + 16x udpEndpointLocalAddress + 1x udpEndpointLocalPort + - * 1x udpEndpointRemoteAddressType + 1x OID len + 16x udpEndpointRemoteAddress + 1x udpEndpointRemotePort + - * 1x udpEndpointInstance = 39 - */ - u32_t result_temp[39]; - - LWIP_UNUSED_ARG(value_len); - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(result_temp)); - - /* iterate over all possible OIDs to find the next one */ - pcb = udp_pcbs; - while (pcb != NULL) { - u32_t test_oid[LWIP_ARRAYSIZE(result_temp)]; - u8_t idx = 0; - - /* udpEndpointLocalAddressType + udpEndpointLocalAddress + udpEndpointLocalPort */ - idx += snmp_ip_port_to_oid(&pcb->local_ip, pcb->local_port, &test_oid[idx]); - - /* udpEndpointRemoteAddressType + udpEndpointRemoteAddress + udpEndpointRemotePort */ - idx += snmp_ip_port_to_oid(&pcb->remote_ip, pcb->remote_port, &test_oid[idx]); - - test_oid[idx] = 0; /* udpEndpointInstance */ - idx++; - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, idx, NULL); - - pcb = pcb->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return udp_endpointTable_get_cell_value_core(column, value); - } else { - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; - } -} - -/* --- udpTable --- */ - -#if LWIP_IPV4 - -/* list of allowed value ranges for incoming OID */ -static const struct snmp_oid_range udp_Table_oid_ranges[] = { - { 0, 0xff }, /* IP A */ - { 0, 0xff }, /* IP B */ - { 0, 0xff }, /* IP C */ - { 0, 0xff }, /* IP D */ - { 1, 0xffff } /* Port */ -}; - -static snmp_err_t -udp_Table_get_cell_value_core(struct udp_pcb *pcb, const u32_t* column, union snmp_variant_value* value, u32_t* value_len) -{ - LWIP_UNUSED_ARG(value_len); - - switch (*column) { - case 1: /* udpLocalAddress */ - /* set reference to PCB local IP and return a generic node that copies IP4 addresses */ - value->u32 = ip_2_ip4(&pcb->local_ip)->addr; - break; - case 2: /* udpLocalPort */ - /* set reference to PCB local port and return a generic node that copies u16_t values */ - value->u32 = pcb->local_port; - break; - default: - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static snmp_err_t -udp_Table_get_cell_value(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len) -{ - ip4_addr_t ip; - u16_t port; - struct udp_pcb *pcb; - - /* check if incoming OID length and if values are in plausible range */ - if (!snmp_oid_in_range(row_oid, row_oid_len, udp_Table_oid_ranges, LWIP_ARRAYSIZE(udp_Table_oid_ranges))) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - /* get IP and port from incoming OID */ - snmp_oid_to_ip4(&row_oid[0], &ip); /* we know it succeeds because of oid_in_range check above */ - port = (u16_t)row_oid[4]; - - /* find udp_pcb with requested ip and port*/ - pcb = udp_pcbs; - while (pcb != NULL) { - if (IP_IS_V4_VAL(pcb->local_ip)) { - if (ip4_addr_cmp(&ip, ip_2_ip4(&pcb->local_ip)) && (port == pcb->local_port)) { - /* fill in object properties */ - return udp_Table_get_cell_value_core(pcb, column, value, value_len); - } - } - pcb = pcb->next; - } - - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; -} - -static snmp_err_t -udp_Table_get_next_cell_instance_and_value(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len) -{ - struct udp_pcb *pcb; - struct snmp_next_oid_state state; - u32_t result_temp[LWIP_ARRAYSIZE(udp_Table_oid_ranges)]; - - /* init struct to search next oid */ - snmp_next_oid_init(&state, row_oid->id, row_oid->len, result_temp, LWIP_ARRAYSIZE(udp_Table_oid_ranges)); - - /* iterate over all possible OIDs to find the next one */ - pcb = udp_pcbs; - while (pcb != NULL) { - u32_t test_oid[LWIP_ARRAYSIZE(udp_Table_oid_ranges)]; - - if (IP_IS_V4_VAL(pcb->local_ip)) { - snmp_ip4_to_oid(ip_2_ip4(&pcb->local_ip), &test_oid[0]); - test_oid[4] = pcb->local_port; - - /* check generated OID: is it a candidate for the next one? */ - snmp_next_oid_check(&state, test_oid, LWIP_ARRAYSIZE(udp_Table_oid_ranges), pcb); - } - - pcb = pcb->next; - } - - /* did we find a next one? */ - if (state.status == SNMP_NEXT_OID_STATUS_SUCCESS) { - snmp_oid_assign(row_oid, state.next_oid, state.next_oid_len); - /* fill in object properties */ - return udp_Table_get_cell_value_core((struct udp_pcb*)state.reference, column, value, value_len); - } else { - /* not found */ - return SNMP_ERR_NOSUCHINSTANCE; - } -} - -#endif /* LWIP_IPV4 */ - -static const struct snmp_scalar_node udp_inDatagrams = SNMP_SCALAR_CREATE_NODE_READONLY(1, SNMP_ASN1_TYPE_COUNTER, udp_get_value); -static const struct snmp_scalar_node udp_noPorts = SNMP_SCALAR_CREATE_NODE_READONLY(2, SNMP_ASN1_TYPE_COUNTER, udp_get_value); -static const struct snmp_scalar_node udp_inErrors = SNMP_SCALAR_CREATE_NODE_READONLY(3, SNMP_ASN1_TYPE_COUNTER, udp_get_value); -static const struct snmp_scalar_node udp_outDatagrams = SNMP_SCALAR_CREATE_NODE_READONLY(4, SNMP_ASN1_TYPE_COUNTER, udp_get_value); -static const struct snmp_scalar_node udp_HCInDatagrams = SNMP_SCALAR_CREATE_NODE_READONLY(8, SNMP_ASN1_TYPE_COUNTER64, udp_get_value); -static const struct snmp_scalar_node udp_HCOutDatagrams = SNMP_SCALAR_CREATE_NODE_READONLY(9, SNMP_ASN1_TYPE_COUNTER64, udp_get_value); - -#if LWIP_IPV4 -static const struct snmp_table_simple_col_def udp_Table_columns[] = { - { 1, SNMP_ASN1_TYPE_IPADDR, SNMP_VARIANT_VALUE_TYPE_U32 }, /* udpLocalAddress */ - { 2, SNMP_ASN1_TYPE_INTEGER, SNMP_VARIANT_VALUE_TYPE_U32 } /* udpLocalPort */ -}; -static const struct snmp_table_simple_node udp_Table = SNMP_TABLE_CREATE_SIMPLE(5, udp_Table_columns, udp_Table_get_cell_value, udp_Table_get_next_cell_instance_and_value); -#endif /* LWIP_IPV4 */ - -static const struct snmp_table_simple_col_def udp_endpointTable_columns[] = { - /* all items except udpEndpointProcess are declared as not-accessible */ - { 8, SNMP_ASN1_TYPE_UNSIGNED32, SNMP_VARIANT_VALUE_TYPE_U32 } /* udpEndpointProcess */ -}; - -static const struct snmp_table_simple_node udp_endpointTable = SNMP_TABLE_CREATE_SIMPLE(7, udp_endpointTable_columns, udp_endpointTable_get_cell_value, udp_endpointTable_get_next_cell_instance_and_value); - -/* the following nodes access variables in LWIP stack from SNMP worker thread and must therefore be synced to LWIP (TCPIP) thread */ -CREATE_LWIP_SYNC_NODE(1, udp_inDatagrams) -CREATE_LWIP_SYNC_NODE(2, udp_noPorts) -CREATE_LWIP_SYNC_NODE(3, udp_inErrors) -CREATE_LWIP_SYNC_NODE(4, udp_outDatagrams) -#if LWIP_IPV4 -CREATE_LWIP_SYNC_NODE(5, udp_Table) -#endif /* LWIP_IPV4 */ -CREATE_LWIP_SYNC_NODE(7, udp_endpointTable) -CREATE_LWIP_SYNC_NODE(8, udp_HCInDatagrams) -CREATE_LWIP_SYNC_NODE(9, udp_HCOutDatagrams) - -static const struct snmp_node* const udp_nodes[] = { - &SYNC_NODE_NAME(udp_inDatagrams).node.node, - &SYNC_NODE_NAME(udp_noPorts).node.node, - &SYNC_NODE_NAME(udp_inErrors).node.node, - &SYNC_NODE_NAME(udp_outDatagrams).node.node, -#if LWIP_IPV4 - &SYNC_NODE_NAME(udp_Table).node.node, -#endif /* LWIP_IPV4 */ - &SYNC_NODE_NAME(udp_endpointTable).node.node, - &SYNC_NODE_NAME(udp_HCInDatagrams).node.node, - &SYNC_NODE_NAME(udp_HCOutDatagrams).node.node -}; - -const struct snmp_tree_node snmp_mib2_udp_root = SNMP_CREATE_TREE_NODE(7, udp_nodes); -#endif /* LWIP_SNMP && SNMP_LWIP_MIB2 && LWIP_UDP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.c deleted file mode 100644 index 0cb7ca997cad6c9b15b50160e3b14658982996e4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.c +++ /dev/null @@ -1,1668 +0,0 @@ -/** - * @file - * SNMP message processing (RFC1157). - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel - * Elias Oenal - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "snmp_msg.h" -#include "snmp_asn1.h" -#include "snmp_core_priv.h" -#include "lwip/ip_addr.h" -#include "lwip/stats.h" - -#if LWIP_SNMP_V3 -#include "lwip/apps/snmpv3.h" -#include "snmpv3_priv.h" -#ifdef LWIP_SNMPV3_INCLUDE_ENGINE -#include LWIP_SNMPV3_INCLUDE_ENGINE -#endif -#endif - -#include - -/* public (non-static) constants */ -/** SNMP community string */ -const char *snmp_community = SNMP_COMMUNITY; -/** SNMP community string for write access */ -const char *snmp_community_write = SNMP_COMMUNITY_WRITE; -/** SNMP community string for sending traps */ -const char *snmp_community_trap = SNMP_COMMUNITY_TRAP; - -snmp_write_callback_fct snmp_write_callback = NULL; -void* snmp_write_callback_arg = NULL; - -/** - * @ingroup snmp_core - * Returns current SNMP community string. - * @return current SNMP community string - */ -const char * -snmp_get_community(void) -{ - return snmp_community; -} - -/** - * @ingroup snmp_core - * Sets SNMP community string. - * The string itself (its storage) must be valid throughout the whole life of - * program (or until it is changed to sth else). - * - * @param community is a pointer to new community string - */ -void -snmp_set_community(const char * const community) -{ - LWIP_ASSERT("community string is too long!", strlen(community) <= SNMP_MAX_COMMUNITY_STR_LEN); - snmp_community = community; -} - -/** - * @ingroup snmp_core - * Returns current SNMP write-access community string. - * @return current SNMP write-access community string - */ -const char * -snmp_get_community_write(void) -{ - return snmp_community_write; -} - -/** - * @ingroup snmp_traps - * Returns current SNMP community string used for sending traps. - * @return current SNMP community string used for sending traps - */ -const char * -snmp_get_community_trap(void) -{ - return snmp_community_trap; -} - -/** - * @ingroup snmp_core - * Sets SNMP community string for write-access. - * The string itself (its storage) must be valid throughout the whole life of - * program (or until it is changed to sth else). - * - * @param community is a pointer to new write-access community string - */ -void -snmp_set_community_write(const char * const community) -{ - LWIP_ASSERT("community string must not be NULL", community != NULL); - LWIP_ASSERT("community string is too long!", strlen(community) <= SNMP_MAX_COMMUNITY_STR_LEN); - snmp_community_write = community; -} - -/** - * @ingroup snmp_traps - * Sets SNMP community string used for sending traps. - * The string itself (its storage) must be valid throughout the whole life of - * program (or until it is changed to sth else). - * - * @param community is a pointer to new trap community string - */ -void -snmp_set_community_trap(const char * const community) -{ - LWIP_ASSERT("community string is too long!", strlen(community) <= SNMP_MAX_COMMUNITY_STR_LEN); - snmp_community_trap = community; -} - -/** - * @ingroup snmp_core - * Callback fired on every successful write access - */ -void -snmp_set_write_callback(snmp_write_callback_fct write_callback, void* callback_arg) -{ - snmp_write_callback = write_callback; - snmp_write_callback_arg = callback_arg; -} - -/* ----------------------------------------------------------------------- */ -/* forward declarations */ -/* ----------------------------------------------------------------------- */ - -static err_t snmp_process_get_request(struct snmp_request *request); -static err_t snmp_process_getnext_request(struct snmp_request *request); -static err_t snmp_process_getbulk_request(struct snmp_request *request); -static err_t snmp_process_set_request(struct snmp_request *request); - -static err_t snmp_parse_inbound_frame(struct snmp_request *request); -static err_t snmp_prepare_outbound_frame(struct snmp_request *request); -static err_t snmp_complete_outbound_frame(struct snmp_request *request); -static void snmp_execute_write_callbacks(struct snmp_request *request); - - -/* ----------------------------------------------------------------------- */ -/* implementation */ -/* ----------------------------------------------------------------------- */ - -void -snmp_receive(void *handle, struct pbuf *p, const ip_addr_t *source_ip, u16_t port) -{ - err_t err; - struct snmp_request request; - - memset(&request, 0, sizeof(request)); - request.handle = handle; - request.source_ip = source_ip; - request.source_port = port; - request.inbound_pbuf = p; - - snmp_stats.inpkts++; - - err = snmp_parse_inbound_frame(&request); - if (err == ERR_OK) { - err = snmp_prepare_outbound_frame(&request); - if (err == ERR_OK) { - - if (request.error_status == SNMP_ERR_NOERROR) { - /* only process frame if we do not already have an error to return (e.g. all readonly) */ - if (request.request_type == SNMP_ASN1_CONTEXT_PDU_GET_REQ) { - err = snmp_process_get_request(&request); - } else if (request.request_type == SNMP_ASN1_CONTEXT_PDU_GET_NEXT_REQ) { - err = snmp_process_getnext_request(&request); - } else if (request.request_type == SNMP_ASN1_CONTEXT_PDU_GET_BULK_REQ) { - err = snmp_process_getbulk_request(&request); - } else if (request.request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ) { - err = snmp_process_set_request(&request); - } - } - - if (err == ERR_OK) { - err = snmp_complete_outbound_frame(&request); - - if (err == ERR_OK) { - err = snmp_sendto(request.handle, request.outbound_pbuf, request.source_ip, request.source_port); - - if ((request.request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ) - && (request.error_status == SNMP_ERR_NOERROR) - && (snmp_write_callback != NULL)) { - /* raise write notification for all written objects */ - snmp_execute_write_callbacks(&request); - } - } - } - } - - if (request.outbound_pbuf != NULL) { - pbuf_free(request.outbound_pbuf); - } - } -} - -static u8_t -snmp_msg_getnext_validate_node_inst(struct snmp_node_instance* node_instance, void* validate_arg) -{ - if (((node_instance->access & SNMP_NODE_INSTANCE_ACCESS_READ) != SNMP_NODE_INSTANCE_ACCESS_READ) || (node_instance->get_value == NULL)) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - if ((node_instance->asn1_type == SNMP_ASN1_TYPE_COUNTER64) && (((struct snmp_request*)validate_arg)->version == SNMP_VERSION_1)) { - /* according to RFC 2089 skip Counter64 objects in GetNext requests from v1 clients */ - return SNMP_ERR_NOSUCHINSTANCE; - } - - return SNMP_ERR_NOERROR; -} - -static void -snmp_process_varbind(struct snmp_request *request, struct snmp_varbind *vb, u8_t get_next) -{ - err_t err; - struct snmp_node_instance node_instance; - memset(&node_instance, 0, sizeof(node_instance)); - - if (get_next) { - struct snmp_obj_id result_oid; - request->error_status = snmp_get_next_node_instance_from_oid(vb->oid.id, vb->oid.len, snmp_msg_getnext_validate_node_inst, request, &result_oid, &node_instance); - - if (request->error_status == SNMP_ERR_NOERROR) { - snmp_oid_assign(&vb->oid, result_oid.id, result_oid.len); - } - } else { - request->error_status = snmp_get_node_instance_from_oid(vb->oid.id, vb->oid.len, &node_instance); - - if (request->error_status == SNMP_ERR_NOERROR) { - /* use 'getnext_validate' method for validation to avoid code duplication (some checks have to be executed here) */ - request->error_status = snmp_msg_getnext_validate_node_inst(&node_instance, request); - - if (request->error_status != SNMP_ERR_NOERROR) { - if (node_instance.release_instance != NULL) { - node_instance.release_instance(&node_instance); - } - } - } - } - - if (request->error_status != SNMP_ERR_NOERROR) { - if (request->error_status >= SNMP_VARBIND_EXCEPTION_OFFSET) { - if ((request->version == SNMP_VERSION_2c) || request->version == SNMP_VERSION_3) { - /* in SNMP v2c a varbind related exception is stored in varbind and not in frame header */ - vb->type = (SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_CLASS_CONTEXT | (request->error_status & SNMP_VARBIND_EXCEPTION_MASK)); - vb->value_len = 0; - - err = snmp_append_outbound_varbind(&(request->outbound_pbuf_stream), vb); - if (err == ERR_OK) { - /* we stored the exception in varbind -> go on */ - request->error_status = SNMP_ERR_NOERROR; - } else if (err == ERR_BUF) { - request->error_status = SNMP_ERR_TOOBIG; - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } - } else { - /* according to RFC 1157/1905, all other errors only return genError */ - request->error_status = SNMP_ERR_GENERROR; - } - } else { - s16_t len = node_instance.get_value(&node_instance, vb->value); - vb->type = node_instance.asn1_type; - - if(len >= 0) { - vb->value_len = (u16_t)len; /* cast is OK because we checked >= 0 above */ - - LWIP_ASSERT("SNMP_MAX_VALUE_SIZE is configured too low", (vb->value_len & ~SNMP_GET_VALUE_RAW_DATA) <= SNMP_MAX_VALUE_SIZE); - err = snmp_append_outbound_varbind(&request->outbound_pbuf_stream, vb); - - if (err == ERR_BUF) { - request->error_status = SNMP_ERR_TOOBIG; - } else if (err != ERR_OK) { - request->error_status = SNMP_ERR_GENERROR; - } - } else { - request->error_status = SNMP_ERR_GENERROR; - } - - if (node_instance.release_instance != NULL) { - node_instance.release_instance(&node_instance); - } - } -} - - -/** - * Service an internal or external event for SNMP GET. - * - * @param request points to the associated message process state - */ -static err_t -snmp_process_get_request(struct snmp_request *request) -{ - snmp_vb_enumerator_err_t err; - struct snmp_varbind vb; - vb.value = request->value_buffer; - - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP get request\n")); - - while (request->error_status == SNMP_ERR_NOERROR) { - err = snmp_vb_enumerator_get_next(&request->inbound_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_OK) { - if ((vb.type == SNMP_ASN1_TYPE_NULL) && (vb.value_len == 0)) { - snmp_process_varbind(request, &vb, 0); - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } else if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else if (err == SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) { - /* malformed ASN.1, don't answer */ - return ERR_ARG; - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } - - return ERR_OK; -} - -/** - * Service an internal or external event for SNMP GET. - * - * @param request points to the associated message process state - */ -static err_t -snmp_process_getnext_request(struct snmp_request *request) -{ - snmp_vb_enumerator_err_t err; - struct snmp_varbind vb; - vb.value = request->value_buffer; - - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP get-next request\n")); - - while (request->error_status == SNMP_ERR_NOERROR) { - err = snmp_vb_enumerator_get_next(&request->inbound_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_OK) { - if ((vb.type == SNMP_ASN1_TYPE_NULL) && (vb.value_len == 0)) { - snmp_process_varbind(request, &vb, 1); - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } else if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else if (err == SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) { - /* malformed ASN.1, don't answer */ - return ERR_ARG; - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } - - return ERR_OK; -} - -/** - * Service an internal or external event for SNMP GETBULKT. - * - * @param request points to the associated message process state - */ -static err_t -snmp_process_getbulk_request(struct snmp_request *request) -{ - snmp_vb_enumerator_err_t err; - s32_t non_repeaters = request->non_repeaters; - s32_t repetitions; - u16_t repetition_offset = 0; - struct snmp_varbind_enumerator repetition_varbind_enumerator; - struct snmp_varbind vb; - vb.value = request->value_buffer; - - if (SNMP_LWIP_GETBULK_MAX_REPETITIONS > 0) { - repetitions = LWIP_MIN(request->max_repetitions, SNMP_LWIP_GETBULK_MAX_REPETITIONS); - } else { - repetitions = request->max_repetitions; - } - - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP get-bulk request\n")); - - /* process non repeaters and first repetition */ - while (request->error_status == SNMP_ERR_NOERROR) { - if (non_repeaters == 0) { - repetition_offset = request->outbound_pbuf_stream.offset; - - if (repetitions == 0) { - /* do not resolve repeaters when repetitions is set to 0 */ - break; - } - repetitions--; - } - - err = snmp_vb_enumerator_get_next(&request->inbound_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else if (err == SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) { - /* malformed ASN.1, don't answer */ - return ERR_ARG; - } else if ((err != SNMP_VB_ENUMERATOR_ERR_OK) || (vb.type != SNMP_ASN1_TYPE_NULL) || (vb.value_len != 0)) { - request->error_status = SNMP_ERR_GENERROR; - } else { - snmp_process_varbind(request, &vb, 1); - non_repeaters--; - } - } - - /* process repetitions > 1 */ - while ((request->error_status == SNMP_ERR_NOERROR) && (repetitions > 0) && (request->outbound_pbuf_stream.offset != repetition_offset)) { - - u8_t all_endofmibview = 1; - - snmp_vb_enumerator_init(&repetition_varbind_enumerator, request->outbound_pbuf, repetition_offset, request->outbound_pbuf_stream.offset - repetition_offset); - repetition_offset = request->outbound_pbuf_stream.offset; /* for next loop */ - - while (request->error_status == SNMP_ERR_NOERROR) { - vb.value = NULL; /* do NOT decode value (we enumerate outbound buffer here, so all varbinds have values assigned) */ - err = snmp_vb_enumerator_get_next(&repetition_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_OK) { - vb.value = request->value_buffer; - snmp_process_varbind(request, &vb, 1); - - if (request->error_status != SNMP_ERR_NOERROR) { - /* already set correct error-index (here it cannot be taken from inbound varbind enumerator) */ - request->error_index = request->non_repeaters + repetition_varbind_enumerator.varbind_count; - } else if (vb.type != (SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTEXT_VARBIND_END_OF_MIB_VIEW)) { - all_endofmibview = 0; - } - } else if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else { - LWIP_DEBUGF(SNMP_DEBUG, ("Very strange, we cannot parse the varbind output that we created just before!")); - request->error_status = SNMP_ERR_GENERROR; - request->error_index = request->non_repeaters + repetition_varbind_enumerator.varbind_count; - } - } - - if ((request->error_status == SNMP_ERR_NOERROR) && all_endofmibview) { - /* stop when all varbinds in a loop return EndOfMibView */ - break; - } - - repetitions--; - } - - if (request->error_status == SNMP_ERR_TOOBIG) { - /* for GetBulk it is ok, if not all requested variables fit into the response -> just return the varbinds added so far */ - request->error_status = SNMP_ERR_NOERROR; - } - - return ERR_OK; -} - -/** - * Service an internal or external event for SNMP SET. - * - * @param request points to the associated message process state - */ -static err_t -snmp_process_set_request(struct snmp_request *request) -{ - snmp_vb_enumerator_err_t err; - struct snmp_varbind vb; - vb.value = request->value_buffer; - - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP set request\n")); - - /* perform set test on all objects */ - while (request->error_status == SNMP_ERR_NOERROR) { - err = snmp_vb_enumerator_get_next(&request->inbound_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_OK) { - struct snmp_node_instance node_instance; - memset(&node_instance, 0, sizeof(node_instance)); - - request->error_status = snmp_get_node_instance_from_oid(vb.oid.id, vb.oid.len, &node_instance); - if (request->error_status == SNMP_ERR_NOERROR) { - if (node_instance.asn1_type != vb.type) { - request->error_status = SNMP_ERR_WRONGTYPE; - } else if (((node_instance.access & SNMP_NODE_INSTANCE_ACCESS_WRITE) != SNMP_NODE_INSTANCE_ACCESS_WRITE) || (node_instance.set_value == NULL)) { - request->error_status = SNMP_ERR_NOTWRITABLE; - } else { - if (node_instance.set_test != NULL) { - request->error_status = node_instance.set_test(&node_instance, vb.value_len, vb.value); - } - } - - if (node_instance.release_instance != NULL) { - node_instance.release_instance(&node_instance); - } - } - } else if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else if (err == SNMP_VB_ENUMERATOR_ERR_INVALIDLENGTH) { - request->error_status = SNMP_ERR_WRONGLENGTH; - } else if (err == SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) { - /* malformed ASN.1, don't answer */ - return ERR_ARG; - } else { - request->error_status = SNMP_ERR_GENERROR; - } - } - - /* perform real set operation on all objects */ - if (request->error_status == SNMP_ERR_NOERROR) { - snmp_vb_enumerator_init(&request->inbound_varbind_enumerator, request->inbound_pbuf, request->inbound_varbind_offset, request->inbound_varbind_len); - while (request->error_status == SNMP_ERR_NOERROR) { - err = snmp_vb_enumerator_get_next(&request->inbound_varbind_enumerator, &vb); - if (err == SNMP_VB_ENUMERATOR_ERR_OK) { - struct snmp_node_instance node_instance; - memset(&node_instance, 0, sizeof(node_instance)); - request->error_status = snmp_get_node_instance_from_oid(vb.oid.id, vb.oid.len, &node_instance); - if (request->error_status == SNMP_ERR_NOERROR) { - if (node_instance.set_value(&node_instance, vb.value_len, vb.value) != SNMP_ERR_NOERROR) { - if (request->inbound_varbind_enumerator.varbind_count == 1) { - request->error_status = SNMP_ERR_COMMITFAILED; - } else { - /* we cannot undo the set operations done so far */ - request->error_status = SNMP_ERR_UNDOFAILED; - } - } - - if (node_instance.release_instance != NULL) { - node_instance.release_instance(&node_instance); - } - } - } else if (err == SNMP_VB_ENUMERATOR_ERR_EOVB) { - /* no more varbinds in request */ - break; - } else { - /* first time enumerating varbinds work but second time not, although nothing should have changed in between ??? */ - request->error_status = SNMP_ERR_GENERROR; - } - } - } - - return ERR_OK; -} - -#define PARSE_EXEC(code, retValue) \ - if ((code) != ERR_OK) { \ - LWIP_DEBUGF(SNMP_DEBUG, ("Malformed ASN.1 detected.\n")); \ - snmp_stats.inasnparseerrs++; \ - return retValue; \ - } - -#define PARSE_ASSERT(cond, retValue) \ - if (!(cond)) { \ - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP parse assertion failed!: " # cond)); \ - snmp_stats.inasnparseerrs++; \ - return retValue; \ - } - -#define BUILD_EXEC(code, retValue) \ - if ((code) != ERR_OK) { \ - LWIP_DEBUGF(SNMP_DEBUG, ("SNMP error during creation of outbound frame!: " # code)); \ - return retValue; \ - } - -#define IF_PARSE_EXEC(code) PARSE_EXEC(code, ERR_ARG) -#define IF_PARSE_ASSERT(code) PARSE_ASSERT(code, ERR_ARG) - -/** - * Checks and decodes incoming SNMP message header, logs header errors. - * - * @param request points to the current message request state return - * @return - * - ERR_OK SNMP header is sane and accepted - * - ERR_VAL SNMP header is either malformed or rejected - */ -static err_t -snmp_parse_inbound_frame(struct snmp_request *request) -{ - struct snmp_pbuf_stream pbuf_stream; - struct snmp_asn1_tlv tlv; - s32_t parent_tlv_value_len; - s32_t s32_value; - err_t err; - - IF_PARSE_EXEC(snmp_pbuf_stream_init(&pbuf_stream, request->inbound_pbuf, 0, request->inbound_pbuf->tot_len)); - - /* decode main container consisting of version, community and PDU */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT((tlv.type == SNMP_ASN1_TYPE_SEQUENCE) && (tlv.value_len == pbuf_stream.length)); - parent_tlv_value_len = tlv.value_len; - - /* decode version */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - if ((s32_value != SNMP_VERSION_1) && - (s32_value != SNMP_VERSION_2c) -#if LWIP_SNMP_V3 - && (s32_value != SNMP_VERSION_3) -#endif - ) - { - /* unsupported SNMP version */ - snmp_stats.inbadversions++; - return ERR_ARG; - } - request->version = (u8_t)s32_value; - -#if LWIP_SNMP_V3 - if (request->version == SNMP_VERSION_3) { - u16_t u16_value; - u16_t inbound_msgAuthenticationParameters_offset; - - /* SNMPv3 doesn't use communities */ - /* @todo: Differentiate read/write access */ - strcpy((char*)request->community, snmp_community); - request->community_strlen = (u16_t)strlen(snmp_community); - - /* RFC3414 globalData */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_SEQUENCE); - parent_tlv_value_len -= SNMP_ASN1_TLV_HDR_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - /* decode msgID */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - request->msg_id = s32_value; - - /* decode msgMaxSize */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - request->msg_max_size = s32_value; - - /* decode msgFlags */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - request->msg_flags = (u8_t)s32_value; - - /* decode msgSecurityModel */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - request->msg_security_model = s32_value; - - /* RFC3414 msgSecurityParameters - * The User-based Security Model defines the contents of the OCTET - * STRING as a SEQUENCE. - * - * We skip the protective dummy OCTET STRING header - * to access the SEQUENCE header. - */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_HDR_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - /* msgSecurityParameters SEQUENCE header */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_SEQUENCE); - parent_tlv_value_len -= SNMP_ASN1_TLV_HDR_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - /* decode msgAuthoritativeEngineID */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->msg_authoritative_engine_id, - &u16_value, SNMP_V3_MAX_ENGINE_ID_LENGTH)); - request->msg_authoritative_engine_id_len = (u8_t)u16_value; - - /* msgAuthoritativeEngineBoots */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->msg_authoritative_engine_boots)); - - /* msgAuthoritativeEngineTime */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->msg_authoritative_engine_time)); - /* @todo: Implement time window checking */ - - /* msgUserName */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->msg_user_name, - &u16_value, SNMP_V3_MAX_USER_LENGTH)); - request->msg_user_name_len = (u8_t)u16_value; - /* @todo: Implement unknown user error response */ - IF_PARSE_EXEC(snmpv3_get_user((char*)request->msg_user_name, NULL, NULL, NULL, NULL)); - - /* msgAuthenticationParameters */ - memset(request->msg_authentication_parameters, 0, SNMP_V3_MAX_AUTH_PARAM_LENGTH); - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - /* Remember position */ - inbound_msgAuthenticationParameters_offset = pbuf_stream.offset; - LWIP_UNUSED_ARG(inbound_msgAuthenticationParameters_offset); - /* Read auth parameters */ - IF_PARSE_ASSERT(tlv.value_len <= SNMP_V3_MAX_AUTH_PARAM_LENGTH); - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->msg_authentication_parameters, - &u16_value, tlv.value_len)); - -#if LWIP_SNMP_V3_CRYPTO - if (request->msg_flags & SNMP_V3_AUTH_FLAG) { - const u8_t zero_arr[SNMP_V3_MAX_AUTH_PARAM_LENGTH] = { 0 }; - u8_t key[20]; - u8_t algo; - u8_t hmac[LWIP_MAX(SNMP_V3_SHA_LEN, SNMP_V3_MD5_LEN)]; - struct snmp_pbuf_stream auth_stream; - - /* Rewind stream */ - IF_PARSE_EXEC(snmp_pbuf_stream_init(&pbuf_stream, request->inbound_pbuf, 0, request->inbound_pbuf->tot_len)); - IF_PARSE_EXEC(snmp_pbuf_stream_seek_abs(&pbuf_stream, inbound_msgAuthenticationParameters_offset)); - /* Set auth parameters to zero for verification */ - IF_PARSE_EXEC(snmp_asn1_enc_raw(&pbuf_stream, zero_arr, tlv.value_len)); - - /* Verify authentication */ - IF_PARSE_EXEC(snmp_pbuf_stream_init(&auth_stream, request->inbound_pbuf, 0, request->inbound_pbuf->tot_len)); - - IF_PARSE_EXEC(snmpv3_get_user((char*)request->msg_user_name, &algo, key, NULL, NULL)); - IF_PARSE_EXEC(snmpv3_auth(&auth_stream, request->inbound_pbuf->tot_len, key, algo, hmac)); - /* @todo: Implement error response */ - IF_PARSE_EXEC(memcmp(request->msg_authentication_parameters, hmac, SNMP_V3_MAX_AUTH_PARAM_LENGTH)); - } -#else - /* Ungraceful exit if we encounter cryptography and don't support it. - * @todo: Implement error response - */ - IF_PARSE_ASSERT(!(request->msg_flags & (SNMP_V3_AUTH_FLAG | SNMP_V3_PRIV_FLAG))); -#endif - - /* msgPrivacyParameters */ - memset(request->msg_privacy_parameters, 0, SNMP_V3_MAX_PRIV_PARAM_LENGTH); - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->msg_privacy_parameters, - &u16_value, SNMP_V3_MAX_PRIV_PARAM_LENGTH)); - -#if LWIP_SNMP_V3_CRYPTO - /* Decrypt message */ - if (request->msg_flags & SNMP_V3_PRIV_FLAG) { - u8_t key[20]; - u8_t algo; - - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_HDR_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmpv3_get_user((char*)request->msg_user_name, NULL, NULL, &algo, key)); - IF_PARSE_EXEC(snmpv3_crypt(&pbuf_stream, tlv.value_len, key, - request->msg_privacy_parameters, request->msg_authoritative_engine_boots, - request->msg_authoritative_engine_time, algo, SNMP_V3_PRIV_MODE_DECRYPT)); - } -#endif - - /* Scoped PDU - * Encryption context - */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_SEQUENCE); - parent_tlv_value_len -= SNMP_ASN1_TLV_HDR_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - /* contextEngineID */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->context_engine_id, - &u16_value, SNMP_V3_MAX_ENGINE_ID_LENGTH)); - request->context_engine_id_len = (u8_t)u16_value; - - /* contextName */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->context_name, - &u16_value, SNMP_V3_MAX_ENGINE_ID_LENGTH)); - request->context_name_len = (u8_t)u16_value; - } else -#endif - { - /* decode community */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_OCTET_STRING); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - err = snmp_asn1_dec_raw(&pbuf_stream, tlv.value_len, request->community, &request->community_strlen, SNMP_MAX_COMMUNITY_STR_LEN); - if (err == ERR_MEM) { - /* community string does not fit in our buffer -> its too long -> its invalid */ - request->community_strlen = 0; - snmp_pbuf_stream_seek(&pbuf_stream, tlv.value_len); - } else { - IF_PARSE_ASSERT(err == ERR_OK); - } - /* add zero terminator */ - request->community[request->community_strlen] = 0; - } - - /* decode PDU type (next container level) */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.value_len <= pbuf_stream.length); - request->inbound_padding_len = pbuf_stream.length - tlv.value_len; - parent_tlv_value_len = tlv.value_len; - - /* validate PDU type */ - switch(tlv.type) { - case (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_GET_REQ): - /* GetRequest PDU */ - snmp_stats.ingetrequests++; - break; - case (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_GET_NEXT_REQ): - /* GetNextRequest PDU */ - snmp_stats.ingetnexts++; - break; - case (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_GET_BULK_REQ): - /* GetBulkRequest PDU */ - if (request->version < SNMP_VERSION_2c) { - /* RFC2089: invalid, drop packet */ - return ERR_ARG; - } - break; - case (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_SET_REQ): - /* SetRequest PDU */ - snmp_stats.insetrequests++; - break; - default: - /* unsupported input PDU for this agent (no parse error) */ - LWIP_DEBUGF(SNMP_DEBUG, ("Unknown/Invalid SNMP PDU type received: %d", tlv.type)); \ - return ERR_ARG; - break; - } - request->request_type = tlv.type & SNMP_ASN1_DATATYPE_MASK; - - /* validate community (do this after decoding PDU type because we don't want to increase 'inbadcommunitynames' for wrong frame types */ - if (request->community_strlen == 0) { - /* community string was too long or really empty*/ - snmp_stats.inbadcommunitynames++; - snmp_authfail_trap(); - return ERR_ARG; - } else if (request->request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ) { - if (snmp_community_write[0] == 0) { - /* our write community is empty, that means all our objects are readonly */ - request->error_status = SNMP_ERR_NOTWRITABLE; - request->error_index = 1; - } else if (strncmp(snmp_community_write, (const char*)request->community, SNMP_MAX_COMMUNITY_STR_LEN) != 0) { - /* community name does not match */ - snmp_stats.inbadcommunitynames++; - snmp_authfail_trap(); - return ERR_ARG; - } - } else { - if (strncmp(snmp_community, (const char*)request->community, SNMP_MAX_COMMUNITY_STR_LEN) != 0) { - /* community name does not match */ - snmp_stats.inbadcommunitynames++; - snmp_authfail_trap(); - return ERR_ARG; - } - } - - /* decode request ID */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->request_id)); - - /* decode error status / non-repeaters */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - if (request->request_type == SNMP_ASN1_CONTEXT_PDU_GET_BULK_REQ) { - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->non_repeaters)); - if (request->non_repeaters < 0) { - /* RFC 1905, 4.2.3 */ - request->non_repeaters = 0; - } - } else { - /* only check valid value, don't touch 'request->error_status', maybe a response error status was already set to above; */ - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &s32_value)); - IF_PARSE_ASSERT(s32_value == SNMP_ERR_NOERROR); - } - - /* decode error index / max-repetitions */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT(tlv.type == SNMP_ASN1_TYPE_INTEGER); - parent_tlv_value_len -= SNMP_ASN1_TLV_LENGTH(tlv); - IF_PARSE_ASSERT(parent_tlv_value_len > 0); - - if (request->request_type == SNMP_ASN1_CONTEXT_PDU_GET_BULK_REQ) { - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->max_repetitions)); - if (request->max_repetitions < 0) { - /* RFC 1905, 4.2.3 */ - request->max_repetitions = 0; - } - } else { - IF_PARSE_EXEC(snmp_asn1_dec_s32t(&pbuf_stream, tlv.value_len, &request->error_index)); - IF_PARSE_ASSERT(s32_value == 0); - } - - /* decode varbind-list type (next container level) */ - IF_PARSE_EXEC(snmp_asn1_dec_tlv(&pbuf_stream, &tlv)); - IF_PARSE_ASSERT((tlv.type == SNMP_ASN1_TYPE_SEQUENCE) && (tlv.value_len <= pbuf_stream.length)); - - request->inbound_varbind_offset = pbuf_stream.offset; - request->inbound_varbind_len = pbuf_stream.length - request->inbound_padding_len; - snmp_vb_enumerator_init(&(request->inbound_varbind_enumerator), request->inbound_pbuf, request->inbound_varbind_offset, request->inbound_varbind_len); - - return ERR_OK; -} - -#define OF_BUILD_EXEC(code) BUILD_EXEC(code, ERR_ARG) - -static err_t -snmp_prepare_outbound_frame(struct snmp_request *request) -{ - struct snmp_asn1_tlv tlv; - struct snmp_pbuf_stream* pbuf_stream = &(request->outbound_pbuf_stream); - - /* try allocating pbuf(s) for maximum response size */ - request->outbound_pbuf = pbuf_alloc(PBUF_TRANSPORT, 1472, PBUF_RAM); - if (request->outbound_pbuf == NULL) { - return ERR_MEM; - } - - snmp_pbuf_stream_init(pbuf_stream, request->outbound_pbuf, 0, request->outbound_pbuf->tot_len); - - /* 'Message' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, 0); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - - /* version */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(request->version, &tlv.value_len); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - OF_BUILD_EXEC( snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->version) ); - -#if LWIP_SNMP_V3 - if (request->version < SNMP_VERSION_3) { -#endif - /* community */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, request->community_strlen); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - OF_BUILD_EXEC( snmp_asn1_enc_raw(pbuf_stream, request->community, request->community_strlen) ); -#if LWIP_SNMP_V3 - } else { - const char* id; - - /* globalData */ - request->outbound_msg_global_data_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 1, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - /* msgID */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 1); - snmp_asn1_enc_s32t_cnt(request->msg_id, &tlv.value_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->msg_id)); - - /* msgMaxSize */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 1); - snmp_asn1_enc_s32t_cnt(request->msg_max_size, &tlv.value_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->msg_max_size)); - - /* msgFlags */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, 1); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, &request->msg_flags, 1)); - - /* msgSecurityModel */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 1); - snmp_asn1_enc_s32t_cnt(request->msg_security_model, &tlv.value_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->msg_security_model)); - - /* end of msgGlobalData */ - request->outbound_msg_global_data_end = pbuf_stream->offset; - - /* msgSecurityParameters */ - request->outbound_msg_security_parameters_str_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 1, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - request->outbound_msg_security_parameters_seq_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 1, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - /* msgAuthoritativeEngineID */ - snmpv3_get_engine_id(&id, &request->msg_authoritative_engine_id_len); - MEMCPY(request->msg_authoritative_engine_id, id, request->msg_authoritative_engine_id_len); - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, request->msg_authoritative_engine_id_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->msg_authoritative_engine_id, request->msg_authoritative_engine_id_len)); - - request->msg_authoritative_engine_time = snmpv3_get_engine_time(); - request->msg_authoritative_engine_boots = snmpv3_get_engine_boots(); - - /* msgAuthoritativeEngineBoots */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(request->msg_authoritative_engine_boots, &tlv.value_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->msg_authoritative_engine_boots)); - - /* msgAuthoritativeEngineTime */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(request->msg_authoritative_engine_time, &tlv.value_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->msg_authoritative_engine_time)); - - /* msgUserName */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, request->msg_user_name_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->msg_user_name, request->msg_user_name_len)); - -#if LWIP_SNMP_V3_CRYPTO - /* msgAuthenticationParameters */ - if (request->msg_flags & SNMP_V3_AUTH_FLAG) { - memset(request->msg_authentication_parameters, 0, SNMP_V3_MAX_AUTH_PARAM_LENGTH); - request->outbound_msg_authentication_parameters_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 1, SNMP_V3_MAX_AUTH_PARAM_LENGTH); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->msg_authentication_parameters, SNMP_V3_MAX_AUTH_PARAM_LENGTH)); - } else -#endif - { - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - } - -#if LWIP_SNMP_V3_CRYPTO - /* msgPrivacyParameters */ - if (request->msg_flags & SNMP_V3_PRIV_FLAG) { - snmpv3_build_priv_param(request->msg_privacy_parameters); - - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, SNMP_V3_MAX_PRIV_PARAM_LENGTH); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->msg_privacy_parameters, SNMP_V3_MAX_PRIV_PARAM_LENGTH)); - } else -#endif - { - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - } - - /* End of msgSecurityParameters, so we can calculate the length of this sequence later */ - request->outbound_msg_security_parameters_end = pbuf_stream->offset; - -#if LWIP_SNMP_V3_CRYPTO - /* For encryption we have to encapsulate the payload in an octet string */ - if (request->msg_flags & SNMP_V3_PRIV_FLAG) { - request->outbound_scoped_pdu_string_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 3, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - } -#endif - /* Scoped PDU - * Encryption context - */ - request->outbound_scoped_pdu_seq_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, 0); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - /* contextEngineID */ - snmpv3_get_engine_id(&id, &request->context_engine_id_len); - MEMCPY(request->context_engine_id, id, request->context_engine_id_len); - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, request->context_engine_id_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->context_engine_id, request->context_engine_id_len)); - - /* contextName */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, request->context_name_len); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, request->context_name, request->context_name_len)); - } -#endif - - /* 'PDU' sequence */ - request->outbound_pdu_offset = pbuf_stream->offset; - SNMP_ASN1_SET_TLV_PARAMS(tlv, (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_GET_RESP), 3, 0); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - - /* request ID */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(request->request_id, &tlv.value_len); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - OF_BUILD_EXEC( snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, request->request_id) ); - - /* error status */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 1); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - request->outbound_error_status_offset = pbuf_stream->offset; - OF_BUILD_EXEC( snmp_pbuf_stream_write(pbuf_stream, 0) ); - - /* error index */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 1); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - request->outbound_error_index_offset = pbuf_stream->offset; - OF_BUILD_EXEC( snmp_pbuf_stream_write(pbuf_stream, 0) ); - - /* 'VarBindList' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, 0); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(pbuf_stream, &tlv) ); - - request->outbound_varbind_offset = pbuf_stream->offset; - - return ERR_OK; -} - -/** Calculate the length of a varbind list */ -err_t -snmp_varbind_length(struct snmp_varbind *varbind, struct snmp_varbind_len *len) -{ - /* calculate required lengths */ - snmp_asn1_enc_oid_cnt(varbind->oid.id, varbind->oid.len, &len->oid_value_len); - snmp_asn1_enc_length_cnt(len->oid_value_len, &len->oid_len_len); - - if (varbind->value_len == 0) { - len->value_value_len = 0; - } else if (varbind->value_len & SNMP_GET_VALUE_RAW_DATA) { - len->value_value_len = varbind->value_len & (~SNMP_GET_VALUE_RAW_DATA); - } else { - switch (varbind->type) { - case SNMP_ASN1_TYPE_INTEGER: - if (varbind->value_len != sizeof (s32_t)) { - return ERR_VAL; - } - snmp_asn1_enc_s32t_cnt(*((s32_t*) varbind->value), &len->value_value_len); - break; - case SNMP_ASN1_TYPE_COUNTER: - case SNMP_ASN1_TYPE_GAUGE: - case SNMP_ASN1_TYPE_TIMETICKS: - if (varbind->value_len != sizeof (u32_t)) { - return ERR_VAL; - } - snmp_asn1_enc_u32t_cnt(*((u32_t*) varbind->value), &len->value_value_len); - break; - case SNMP_ASN1_TYPE_OCTET_STRING: - case SNMP_ASN1_TYPE_IPADDR: - case SNMP_ASN1_TYPE_OPAQUE: - len->value_value_len = varbind->value_len; - break; - case SNMP_ASN1_TYPE_NULL: - if (varbind->value_len != 0) { - return ERR_VAL; - } - len->value_value_len = 0; - break; - case SNMP_ASN1_TYPE_OBJECT_ID: - if ((varbind->value_len & 0x03) != 0) { - return ERR_VAL; - } - snmp_asn1_enc_oid_cnt((u32_t*) varbind->value, varbind->value_len >> 2, &len->value_value_len); - break; - case SNMP_ASN1_TYPE_COUNTER64: - if (varbind->value_len != (2 * sizeof (u32_t))) { - return ERR_VAL; - } - snmp_asn1_enc_u64t_cnt((u32_t*) varbind->value, &len->value_value_len); - break; - default: - /* unsupported type */ - return ERR_VAL; - } - } - snmp_asn1_enc_length_cnt(len->value_value_len, &len->value_len_len); - - len->vb_value_len = 1 + len->oid_len_len + len->oid_value_len + 1 + len->value_len_len + len->value_value_len; - snmp_asn1_enc_length_cnt(len->vb_value_len, &len->vb_len_len); - - return ERR_OK; -} - -#define OVB_BUILD_EXEC(code) BUILD_EXEC(code, ERR_ARG) - -err_t -snmp_append_outbound_varbind(struct snmp_pbuf_stream *pbuf_stream, struct snmp_varbind* varbind) -{ - struct snmp_asn1_tlv tlv; - struct snmp_varbind_len len; - err_t err; - - err = snmp_varbind_length(varbind, &len); - - if (err != ERR_OK) { - return err; - } - - /* check length already before adding first data because in case of GetBulk, - * data added so far is returned and therefore no partial data shall be added - */ - if ((1 + len.vb_len_len + len.vb_value_len) > pbuf_stream->length) { - return ERR_BUF; - } - - /* 'VarBind' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, len.vb_len_len, len.vb_value_len); - OVB_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - /* VarBind OID */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OBJECT_ID, len.oid_len_len, len.oid_value_len); - OVB_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - OVB_BUILD_EXEC(snmp_asn1_enc_oid(pbuf_stream, varbind->oid.id, varbind->oid.len)); - - /* VarBind value */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, varbind->type, len.value_len_len, len.value_value_len); - OVB_BUILD_EXEC(snmp_ans1_enc_tlv(pbuf_stream, &tlv)); - - if (len.value_value_len > 0) { - if (varbind->value_len & SNMP_GET_VALUE_RAW_DATA) { - OVB_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, (u8_t*) varbind->value, len.value_value_len)); - } else { - switch (varbind->type) { - case SNMP_ASN1_TYPE_INTEGER: - OVB_BUILD_EXEC(snmp_asn1_enc_s32t(pbuf_stream, len.value_value_len, *((s32_t*) varbind->value))); - break; - case SNMP_ASN1_TYPE_COUNTER: - case SNMP_ASN1_TYPE_GAUGE: - case SNMP_ASN1_TYPE_TIMETICKS: - OVB_BUILD_EXEC(snmp_asn1_enc_u32t(pbuf_stream, len.value_value_len, *((u32_t*) varbind->value))); - break; - case SNMP_ASN1_TYPE_OCTET_STRING: - case SNMP_ASN1_TYPE_IPADDR: - case SNMP_ASN1_TYPE_OPAQUE: - OVB_BUILD_EXEC(snmp_asn1_enc_raw(pbuf_stream, (u8_t*) varbind->value, len.value_value_len)); - len.value_value_len = varbind->value_len; - break; - case SNMP_ASN1_TYPE_OBJECT_ID: - OVB_BUILD_EXEC(snmp_asn1_enc_oid(pbuf_stream, (u32_t*) varbind->value, varbind->value_len / sizeof (u32_t))); - break; - case SNMP_ASN1_TYPE_COUNTER64: - OVB_BUILD_EXEC(snmp_asn1_enc_u64t(pbuf_stream, len.value_value_len, (u32_t*) varbind->value)); - break; - default: - LWIP_ASSERT("Unknown variable type", 0); - break; - } - } - } - - return ERR_OK; -} - -static err_t -snmp_complete_outbound_frame(struct snmp_request *request) -{ - struct snmp_asn1_tlv tlv; - u16_t frame_size; - u8_t outbound_padding = 0; - - if (request->version == SNMP_VERSION_1) { - if (request->error_status != SNMP_ERR_NOERROR) { - /* map v2c error codes to v1 compliant error code (according to RFC 2089) */ - switch (request->error_status) { - /* mapping of implementation specific "virtual" error codes - * (during processing of frame we already stored them in error_status field, - * so no need to check all varbinds here for those exceptions as suggested by RFC) */ - case SNMP_ERR_NOSUCHINSTANCE: - case SNMP_ERR_NOSUCHOBJECT: - case SNMP_ERR_ENDOFMIBVIEW: - request->error_status = SNMP_ERR_NOSUCHNAME; - break; - /* mapping according to RFC */ - case SNMP_ERR_WRONGVALUE: - case SNMP_ERR_WRONGENCODING: - case SNMP_ERR_WRONGTYPE: - case SNMP_ERR_WRONGLENGTH: - case SNMP_ERR_INCONSISTENTVALUE: - request->error_status = SNMP_ERR_BADVALUE; - break; - case SNMP_ERR_NOACCESS: - case SNMP_ERR_NOTWRITABLE: - case SNMP_ERR_NOCREATION: - case SNMP_ERR_INCONSISTENTNAME: - case SNMP_ERR_AUTHORIZATIONERROR: - request->error_status = SNMP_ERR_NOSUCHNAME; - break; - case SNMP_ERR_RESOURCEUNAVAILABLE: - case SNMP_ERR_COMMITFAILED: - case SNMP_ERR_UNDOFAILED: - default: - request->error_status = SNMP_ERR_GENERROR; - break; - } - } - } else { - if (request->request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ) { - /* map error codes to according to RFC 1905 (4.2.5. The SetRequest-PDU) return 'NotWritable' for unknown OIDs) */ - switch (request->error_status) { - case SNMP_ERR_NOSUCHINSTANCE: - case SNMP_ERR_NOSUCHOBJECT: - case SNMP_ERR_ENDOFMIBVIEW: - request->error_status = SNMP_ERR_NOTWRITABLE; - break; - default: - break; - } - } - - if (request->error_status >= SNMP_VARBIND_EXCEPTION_OFFSET) { - /* should never occur because v2 frames store exceptions directly inside varbinds and not as frame error_status */ - LWIP_DEBUGF(SNMP_DEBUG, ("snmp_complete_outbound_frame() > Found v2 request with varbind exception code stored as error status!\n")); - return ERR_ARG; - } - } - - if ((request->error_status != SNMP_ERR_NOERROR) || (request->request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ)) { - /* all inbound vars are returned in response without any modification for error responses and successful set requests*/ - struct snmp_pbuf_stream inbound_stream; - OF_BUILD_EXEC( snmp_pbuf_stream_init(&inbound_stream, request->inbound_pbuf, request->inbound_varbind_offset, request->inbound_varbind_len) ); - OF_BUILD_EXEC( snmp_pbuf_stream_init(&(request->outbound_pbuf_stream), request->outbound_pbuf, request->outbound_varbind_offset, request->outbound_pbuf->tot_len - request->outbound_varbind_offset) ); - snmp_pbuf_stream_writeto(&inbound_stream, &(request->outbound_pbuf_stream), 0); - } - - frame_size = request->outbound_pbuf_stream.offset; - -#if LWIP_SNMP_V3 && LWIP_SNMP_V3_CRYPTO - /* Calculate padding for encryption */ - if (request->version == SNMP_VERSION_3 && (request->msg_flags & SNMP_V3_PRIV_FLAG)) { - u8_t i; - outbound_padding = (8 - (u8_t)((frame_size - request->outbound_scoped_pdu_seq_offset) & 0x07)) & 0x07; - for (i = 0; i < outbound_padding; i++) { - snmp_pbuf_stream_write(&request->outbound_pbuf_stream, 0); - } - } -#endif - - /* complete missing length in 'Message' sequence ; 'Message' tlv is located at the beginning (offset 0) */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, frame_size + outbound_padding - 1 - 3); /* - type - length_len(fixed, see snmp_prepare_outbound_frame()) */ - OF_BUILD_EXEC( snmp_pbuf_stream_init(&(request->outbound_pbuf_stream), request->outbound_pbuf, 0, request->outbound_pbuf->tot_len) ); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv) ); - -#if LWIP_SNMP_V3 - if (request->version == SNMP_VERSION_3) { - /* complete missing length in 'globalData' sequence */ - /* - type - length_len(fixed, see snmp_prepare_outbound_frame()) */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 1, request->outbound_msg_global_data_end - - request->outbound_msg_global_data_offset - 1 - 1); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_msg_global_data_offset)); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv)); - - /* complete missing length in 'msgSecurityParameters' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 1, request->outbound_msg_security_parameters_end - - request->outbound_msg_security_parameters_str_offset - 1 - 1); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_msg_security_parameters_str_offset)); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv)); - - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 1, request->outbound_msg_security_parameters_end - - request->outbound_msg_security_parameters_seq_offset - 1 - 1); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_msg_security_parameters_seq_offset)); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv)); - - /* complete missing length in scoped PDU sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, frame_size - request->outbound_scoped_pdu_seq_offset - 1 - 3); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_scoped_pdu_seq_offset)); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv)); - } -#endif - - /* complete missing length in 'PDU' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_GET_RESP), 3, - frame_size - request->outbound_pdu_offset - 1 - 3); /* - type - length_len(fixed, see snmp_prepare_outbound_frame()) */ - OF_BUILD_EXEC( snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_pdu_offset) ); - OF_BUILD_EXEC( snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv) ); - - /* process and encode final error status */ - if (request->error_status != 0) { - u16_t len; - snmp_asn1_enc_s32t_cnt(request->error_status, &len); - if (len != 1) { - /* error, we only reserved one byte for it */ - return ERR_ARG; - } - OF_BUILD_EXEC( snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_error_status_offset) ); - OF_BUILD_EXEC( snmp_asn1_enc_s32t(&(request->outbound_pbuf_stream), len, request->error_status) ); - - /* for compatibility to v1, log statistics; in v2 (RFC 1907) these statistics are obsoleted */ - switch (request->error_status) { - case SNMP_ERR_TOOBIG: - snmp_stats.outtoobigs++; - break; - case SNMP_ERR_NOSUCHNAME: - snmp_stats.outnosuchnames++; - break; - case SNMP_ERR_BADVALUE: - snmp_stats.outbadvalues++; - break; - case SNMP_ERR_GENERROR: - default: - snmp_stats.outgenerrs++; - break; - } - - if (request->error_status == SNMP_ERR_TOOBIG) { - request->error_index = 0; /* defined by RFC 1157 */ - } else if (request->error_index == 0) { - /* set index to varbind where error occured (if not already set before, e.g. during GetBulk processing) */ - request->error_index = request->inbound_varbind_enumerator.varbind_count; - } - } else { - if (request->request_type == SNMP_ASN1_CONTEXT_PDU_SET_REQ) { - snmp_stats.intotalsetvars += request->inbound_varbind_enumerator.varbind_count; - } else { - snmp_stats.intotalreqvars += request->inbound_varbind_enumerator.varbind_count; - } - } - - /* encode final error index*/ - if (request->error_index != 0) { - u16_t len; - snmp_asn1_enc_s32t_cnt(request->error_index, &len); - if (len != 1) { - /* error, we only reserved one byte for it */ - return ERR_VAL; - } - OF_BUILD_EXEC( snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_error_index_offset) ); - OF_BUILD_EXEC( snmp_asn1_enc_s32t(&(request->outbound_pbuf_stream), len, request->error_index) ); - } - - /* complete missing length in 'VarBindList' sequence ; 'VarBindList' tlv is located directly before varbind offset */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 3, frame_size - request->outbound_varbind_offset); - OF_BUILD_EXEC( snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_varbind_offset - 1 - 3) ); /* - type - length_len(fixed, see snmp_prepare_outbound_frame()) */ - OF_BUILD_EXEC( snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv) ); - - /* Authenticate response */ -#if LWIP_SNMP_V3 && LWIP_SNMP_V3_CRYPTO - /* Encrypt response */ - if (request->version == SNMP_VERSION_3 && (request->msg_flags & SNMP_V3_PRIV_FLAG)) { - u8_t key[20]; - u8_t algo; - - /* complete missing length in PDU sequence */ - OF_BUILD_EXEC(snmp_pbuf_stream_init(&request->outbound_pbuf_stream, request->outbound_pbuf, 0, request->outbound_pbuf->tot_len)); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&(request->outbound_pbuf_stream), request->outbound_scoped_pdu_string_offset)); - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 3, frame_size + outbound_padding - - request->outbound_scoped_pdu_string_offset - 1 - 3); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&(request->outbound_pbuf_stream), &tlv)); - - OF_BUILD_EXEC(snmpv3_get_user((char*)request->msg_user_name, NULL, NULL, &algo, key)); - - OF_BUILD_EXEC(snmpv3_crypt(&request->outbound_pbuf_stream, tlv.value_len, key, - request->msg_privacy_parameters, request->msg_authoritative_engine_boots, - request->msg_authoritative_engine_time, algo, SNMP_V3_PRIV_MODE_ENCRYPT)); - } - - if (request->version == SNMP_VERSION_3 && (request->msg_flags & SNMP_V3_AUTH_FLAG)) { - u8_t key[20]; - u8_t algo; - u8_t hmac[20]; - - OF_BUILD_EXEC(snmpv3_get_user((char*)request->msg_user_name, &algo, key, NULL, NULL)); - OF_BUILD_EXEC(snmp_pbuf_stream_init(&(request->outbound_pbuf_stream), - request->outbound_pbuf, 0, request->outbound_pbuf->tot_len)); - OF_BUILD_EXEC(snmpv3_auth(&request->outbound_pbuf_stream, frame_size + outbound_padding, key, algo, hmac)); - - MEMCPY(request->msg_authentication_parameters, hmac, SNMP_V3_MAX_AUTH_PARAM_LENGTH); - OF_BUILD_EXEC(snmp_pbuf_stream_init(&request->outbound_pbuf_stream, - request->outbound_pbuf, 0, request->outbound_pbuf->tot_len)); - OF_BUILD_EXEC(snmp_pbuf_stream_seek_abs(&request->outbound_pbuf_stream, - request->outbound_msg_authentication_parameters_offset)); - - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 1, SNMP_V3_MAX_AUTH_PARAM_LENGTH); - OF_BUILD_EXEC(snmp_ans1_enc_tlv(&request->outbound_pbuf_stream, &tlv)); - OF_BUILD_EXEC(snmp_asn1_enc_raw(&request->outbound_pbuf_stream, - request->msg_authentication_parameters, SNMP_V3_MAX_AUTH_PARAM_LENGTH)); - } -#endif - - pbuf_realloc(request->outbound_pbuf, frame_size + outbound_padding); - - snmp_stats.outgetresponses++; - snmp_stats.outpkts++; - - return ERR_OK; -} - -static void -snmp_execute_write_callbacks(struct snmp_request *request) -{ - struct snmp_varbind_enumerator inbound_varbind_enumerator; - struct snmp_varbind vb; - - snmp_vb_enumerator_init(&inbound_varbind_enumerator, request->inbound_pbuf, request->inbound_varbind_offset, request->inbound_varbind_len); - vb.value = NULL; /* do NOT decode value (we enumerate outbound buffer here, so all varbinds have values assigned, which we don't need here) */ - - while (snmp_vb_enumerator_get_next(&inbound_varbind_enumerator, &vb) == SNMP_VB_ENUMERATOR_ERR_OK) { - snmp_write_callback(vb.oid.id, vb.oid.len, snmp_write_callback_arg); - } -} - - -/* ----------------------------------------------------------------------- */ -/* VarBind enumerator methods */ -/* ----------------------------------------------------------------------- */ - -void -snmp_vb_enumerator_init(struct snmp_varbind_enumerator* enumerator, struct pbuf* p, u16_t offset, u16_t length) -{ - snmp_pbuf_stream_init(&(enumerator->pbuf_stream), p, offset, length); - enumerator->varbind_count = 0; -} - -#define VB_PARSE_EXEC(code) PARSE_EXEC(code, SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) -#define VB_PARSE_ASSERT(code) PARSE_ASSERT(code, SNMP_VB_ENUMERATOR_ERR_ASN1ERROR) - -snmp_vb_enumerator_err_t -snmp_vb_enumerator_get_next(struct snmp_varbind_enumerator* enumerator, struct snmp_varbind* varbind) -{ - struct snmp_asn1_tlv tlv; - u16_t varbind_len; - err_t err; - - if (enumerator->pbuf_stream.length == 0) - { - return SNMP_VB_ENUMERATOR_ERR_EOVB; - } - enumerator->varbind_count++; - - /* decode varbind itself (parent container of a varbind) */ - VB_PARSE_EXEC(snmp_asn1_dec_tlv(&(enumerator->pbuf_stream), &tlv)); - VB_PARSE_ASSERT((tlv.type == SNMP_ASN1_TYPE_SEQUENCE) && (tlv.value_len <= enumerator->pbuf_stream.length)); - varbind_len = tlv.value_len; - - /* decode varbind name (object id) */ - VB_PARSE_EXEC(snmp_asn1_dec_tlv(&(enumerator->pbuf_stream), &tlv)); - VB_PARSE_ASSERT((tlv.type == SNMP_ASN1_TYPE_OBJECT_ID) && (SNMP_ASN1_TLV_LENGTH(tlv) < varbind_len) && (tlv.value_len < enumerator->pbuf_stream.length)); - - VB_PARSE_EXEC(snmp_asn1_dec_oid(&(enumerator->pbuf_stream), tlv.value_len, varbind->oid.id, &(varbind->oid.len), SNMP_MAX_OBJ_ID_LEN)); - varbind_len -= SNMP_ASN1_TLV_LENGTH(tlv); - - /* decode varbind value (object id) */ - VB_PARSE_EXEC(snmp_asn1_dec_tlv(&(enumerator->pbuf_stream), &tlv)); - VB_PARSE_ASSERT((SNMP_ASN1_TLV_LENGTH(tlv) == varbind_len) && (tlv.value_len <= enumerator->pbuf_stream.length)); - varbind->type = tlv.type; - - /* shall the value be decoded ? */ - if (varbind->value != NULL) { - switch (varbind->type) { - case SNMP_ASN1_TYPE_INTEGER: - VB_PARSE_EXEC(snmp_asn1_dec_s32t(&(enumerator->pbuf_stream), tlv.value_len, (s32_t*)varbind->value)); - varbind->value_len = sizeof(s32_t*); - break; - case SNMP_ASN1_TYPE_COUNTER: - case SNMP_ASN1_TYPE_GAUGE: - case SNMP_ASN1_TYPE_TIMETICKS: - VB_PARSE_EXEC(snmp_asn1_dec_u32t(&(enumerator->pbuf_stream), tlv.value_len, (u32_t*)varbind->value)); - varbind->value_len = sizeof(u32_t*); - break; - case SNMP_ASN1_TYPE_OCTET_STRING: - case SNMP_ASN1_TYPE_OPAQUE: - err = snmp_asn1_dec_raw(&(enumerator->pbuf_stream), tlv.value_len, (u8_t*)varbind->value, &varbind->value_len, SNMP_MAX_VALUE_SIZE); - if (err == ERR_MEM) { - return SNMP_VB_ENUMERATOR_ERR_INVALIDLENGTH; - } - VB_PARSE_ASSERT(err == ERR_OK); - break; - case SNMP_ASN1_TYPE_NULL: - varbind->value_len = 0; - break; - case SNMP_ASN1_TYPE_OBJECT_ID: - /* misuse tlv.length_len as OID_length transporter */ - err = snmp_asn1_dec_oid(&(enumerator->pbuf_stream), tlv.value_len, (u32_t*)varbind->value, &tlv.length_len, SNMP_MAX_OBJ_ID_LEN); - if (err == ERR_MEM) { - return SNMP_VB_ENUMERATOR_ERR_INVALIDLENGTH; - } - VB_PARSE_ASSERT(err == ERR_OK); - varbind->value_len = tlv.length_len * sizeof(u32_t); - break; - case SNMP_ASN1_TYPE_IPADDR: - if (tlv.value_len == 4) { - /* must be exactly 4 octets! */ - VB_PARSE_EXEC(snmp_asn1_dec_raw(&(enumerator->pbuf_stream), tlv.value_len, (u8_t*)varbind->value, &varbind->value_len, SNMP_MAX_VALUE_SIZE)); - } else { - VB_PARSE_ASSERT(0); - } - break; - case SNMP_ASN1_TYPE_COUNTER64: - VB_PARSE_EXEC(snmp_asn1_dec_u64t(&(enumerator->pbuf_stream), tlv.value_len, (u32_t*)varbind->value)); - varbind->value_len = 2 * sizeof(u32_t*); - break; - default: - VB_PARSE_ASSERT(0); - break; - } - } else { - snmp_pbuf_stream_seek(&(enumerator->pbuf_stream), tlv.value_len); - varbind->value_len = tlv.value_len; - } - - return SNMP_VB_ENUMERATOR_ERR_OK; -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.h deleted file mode 100644 index 2d01ef36eb919debed2f11e79953f4631148e65a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_msg.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - * @file - * SNMP Agent message handling structures (internal API, do not use in client code). - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel - * Elias Oenal - */ - -#ifndef LWIP_HDR_APPS_SNMP_MSG_H -#define LWIP_HDR_APPS_SNMP_MSG_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP - -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "snmp_pbuf_stream.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" - -#if LWIP_SNMP_V3 -#include "snmpv3_priv.h" -#endif - - -#ifdef __cplusplus -extern "C" { -#endif - -/* The listen port of the SNMP agent. Clients have to make their requests to - this port. Most standard clients won't work if you change this! */ -#ifndef SNMP_IN_PORT -#define SNMP_IN_PORT 161 -#endif -/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't - work if you change this! */ -#ifndef SNMP_TRAP_PORT -#define SNMP_TRAP_PORT 162 -#endif - -/* version defines used in PDU */ -#define SNMP_VERSION_1 0 -#define SNMP_VERSION_2c 1 -#define SNMP_VERSION_3 3 - -struct snmp_varbind_enumerator -{ - struct snmp_pbuf_stream pbuf_stream; - u16_t varbind_count; -}; - -typedef enum { - SNMP_VB_ENUMERATOR_ERR_OK = 0, - SNMP_VB_ENUMERATOR_ERR_EOVB = 1, - SNMP_VB_ENUMERATOR_ERR_ASN1ERROR = 2, - SNMP_VB_ENUMERATOR_ERR_INVALIDLENGTH = 3 -} snmp_vb_enumerator_err_t; - -void snmp_vb_enumerator_init(struct snmp_varbind_enumerator* enumerator, struct pbuf* p, u16_t offset, u16_t length); -snmp_vb_enumerator_err_t snmp_vb_enumerator_get_next(struct snmp_varbind_enumerator* enumerator, struct snmp_varbind* varbind); - -struct snmp_request -{ - /* Communication handle */ - void *handle; - /* source IP address */ - const ip_addr_t *source_ip; - /* source UDP port */ - u16_t source_port; - /* incoming snmp version */ - u8_t version; - /* community name (zero terminated) */ - u8_t community[SNMP_MAX_COMMUNITY_STR_LEN + 1]; - /* community string length (exclusive zero term) */ - u16_t community_strlen; - /* request type */ - u8_t request_type; - /* request ID */ - s32_t request_id; - /* error status */ - s32_t error_status; - /* error index */ - s32_t error_index; - /* non-repeaters (getBulkRequest (SNMPv2c)) */ - s32_t non_repeaters; - /* max-repetitions (getBulkRequest (SNMPv2c)) */ - s32_t max_repetitions; - -#if LWIP_SNMP_V3 - s32_t msg_id; - s32_t msg_max_size; - u8_t msg_flags; - s32_t msg_security_model; - u8_t msg_authoritative_engine_id[SNMP_V3_MAX_ENGINE_ID_LENGTH]; - u8_t msg_authoritative_engine_id_len; - s32_t msg_authoritative_engine_boots; - s32_t msg_authoritative_engine_time; - u8_t msg_user_name[SNMP_V3_MAX_USER_LENGTH]; - u8_t msg_user_name_len; - u8_t msg_authentication_parameters[SNMP_V3_MAX_AUTH_PARAM_LENGTH]; - u8_t msg_privacy_parameters[SNMP_V3_MAX_PRIV_PARAM_LENGTH]; - u8_t context_engine_id[SNMP_V3_MAX_ENGINE_ID_LENGTH]; - u8_t context_engine_id_len; - u8_t context_name[SNMP_V3_MAX_ENGINE_ID_LENGTH]; - u8_t context_name_len; -#endif - - struct pbuf *inbound_pbuf; - struct snmp_varbind_enumerator inbound_varbind_enumerator; - u16_t inbound_varbind_offset; - u16_t inbound_varbind_len; - u16_t inbound_padding_len; - - struct pbuf *outbound_pbuf; - struct snmp_pbuf_stream outbound_pbuf_stream; - u16_t outbound_pdu_offset; - u16_t outbound_error_status_offset; - u16_t outbound_error_index_offset; - u16_t outbound_varbind_offset; -#if LWIP_SNMP_V3 - u16_t outbound_msg_global_data_offset; - u16_t outbound_msg_global_data_end; - u16_t outbound_msg_security_parameters_str_offset; - u16_t outbound_msg_security_parameters_seq_offset; - u16_t outbound_msg_security_parameters_end; - u16_t outbound_msg_authentication_parameters_offset; - u16_t outbound_scoped_pdu_seq_offset; - u16_t outbound_scoped_pdu_string_offset; -#endif - - u8_t value_buffer[SNMP_MAX_VALUE_SIZE]; -}; - -/** A helper struct keeping length information about varbinds */ -struct snmp_varbind_len -{ - u8_t vb_len_len; - u16_t vb_value_len; - u8_t oid_len_len; - u16_t oid_value_len; - u8_t value_len_len; - u16_t value_value_len; -}; - -/** Agent community string */ -extern const char *snmp_community; -/** Agent community string for write access */ -extern const char *snmp_community_write; -/** handle for sending traps */ -extern void* snmp_traps_handle; - -void snmp_receive(void *handle, struct pbuf *p, const ip_addr_t *source_ip, u16_t port); -err_t snmp_sendto(void *handle, struct pbuf *p, const ip_addr_t *dst, u16_t port); -u8_t snmp_get_local_ip_for_dst(void* handle, const ip_addr_t *dst, ip_addr_t *result); -err_t snmp_varbind_length(struct snmp_varbind *varbind, struct snmp_varbind_len *len); -err_t snmp_append_outbound_varbind(struct snmp_pbuf_stream *pbuf_stream, struct snmp_varbind* varbind); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* LWIP_HDR_APPS_SNMP_MSG_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_netconn.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_netconn.c deleted file mode 100644 index 24c3e2653169311213202f96f57623247f754e7f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_netconn.c +++ /dev/null @@ -1,121 +0,0 @@ -/** - * @file - * SNMP netconn frontend. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP && SNMP_USE_NETCONN - -#include -#include "lwip/api.h" -#include "lwip/ip.h" -#include "lwip/udp.h" -#include "snmp_msg.h" -#include "lwip/sys.h" - -/** SNMP netconn API worker thread */ -static void -snmp_netconn_thread(void *arg) -{ - struct netconn *conn; - struct netbuf *buf; - err_t err; - LWIP_UNUSED_ARG(arg); - - /* Bind to SNMP port with default IP address */ -#if LWIP_IPV6 - conn = netconn_new(NETCONN_UDP_IPV6); - netconn_bind(conn, IP6_ADDR_ANY, SNMP_IN_PORT); -#else /* LWIP_IPV6 */ - conn = netconn_new(NETCONN_UDP); - netconn_bind(conn, IP4_ADDR_ANY, SNMP_IN_PORT); -#endif /* LWIP_IPV6 */ - LWIP_ERROR("snmp_netconn: invalid conn", (conn != NULL), return;); - - snmp_traps_handle = conn; - - do { - err = netconn_recv(conn, &buf); - - if (err == ERR_OK) { - snmp_receive(conn, buf->p, &buf->addr, buf->port); - } - - if (buf != NULL) { - netbuf_delete(buf); - } - } while(1); -} - -err_t -snmp_sendto(void *handle, struct pbuf *p, const ip_addr_t *dst, u16_t port) -{ - err_t result; - struct netbuf buf; - - memset(&buf, 0, sizeof(buf)); - buf.p = p; - result = netconn_sendto((struct netconn*)handle, &buf, dst, port); - - return result; -} - -u8_t -snmp_get_local_ip_for_dst(void* handle, const ip_addr_t *dst, ip_addr_t *result) -{ - struct netconn* conn = (struct netconn*)handle; - struct netif *dst_if; - const ip_addr_t* dst_ip; - - LWIP_UNUSED_ARG(conn); /* unused in case of IPV4 only configuration */ - - ip_route_get_local_ip(&conn->pcb.udp->local_ip, dst, dst_if, dst_ip); - - if ((dst_if != NULL) && (dst_ip != NULL)) { - ip_addr_copy(*result, *dst_ip); - return 1; - } else { - return 0; - } -} - -/** - * Starts SNMP Agent. - */ -void -snmp_init(void) -{ - sys_thread_new("snmp_netconn", snmp_netconn_thread, NULL, SNMP_STACK_SIZE, SNMP_THREAD_PRIO); -} - -#endif /* LWIP_SNMP && SNMP_USE_NETCONN */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.c deleted file mode 100644 index 3c1217d710be90cc09979e31b3fabfdc4f306f79..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * @file - * SNMP pbuf stream wrapper implementation (internal API, do not use in client code). - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "snmp_pbuf_stream.h" -#include "lwip/def.h" -#include - -err_t -snmp_pbuf_stream_init(struct snmp_pbuf_stream* pbuf_stream, struct pbuf* p, u16_t offset, u16_t length) -{ - pbuf_stream->offset = offset; - pbuf_stream->length = length; - pbuf_stream->pbuf = p; - - return ERR_OK; -} - -err_t -snmp_pbuf_stream_read(struct snmp_pbuf_stream* pbuf_stream, u8_t* data) -{ - if (pbuf_stream->length == 0) { - return ERR_BUF; - } - - if (pbuf_copy_partial(pbuf_stream->pbuf, data, 1, pbuf_stream->offset) == 0) { - return ERR_BUF; - } - - pbuf_stream->offset++; - pbuf_stream->length--; - - return ERR_OK; -} - -err_t -snmp_pbuf_stream_write(struct snmp_pbuf_stream* pbuf_stream, u8_t data) -{ - return snmp_pbuf_stream_writebuf(pbuf_stream, &data, 1); -} - -err_t -snmp_pbuf_stream_writebuf(struct snmp_pbuf_stream* pbuf_stream, const void* buf, u16_t buf_len) -{ - if (pbuf_stream->length < buf_len) { - return ERR_BUF; - } - - if (pbuf_take_at(pbuf_stream->pbuf, buf, buf_len, pbuf_stream->offset) != ERR_OK) { - return ERR_BUF; - } - - pbuf_stream->offset += buf_len; - pbuf_stream->length -= buf_len; - - return ERR_OK; -} - -err_t -snmp_pbuf_stream_writeto(struct snmp_pbuf_stream* pbuf_stream, struct snmp_pbuf_stream* target_pbuf_stream, u16_t len) -{ - - if ((pbuf_stream == NULL) || (target_pbuf_stream == NULL)) { - return ERR_ARG; - } - if ((len > pbuf_stream->length) || (len > target_pbuf_stream->length)) { - return ERR_ARG; - } - - if (len == 0) { - len = LWIP_MIN(pbuf_stream->length, target_pbuf_stream->length); - } - - while (len > 0) { - u16_t chunk_len; - err_t err; - u16_t target_offset; - struct pbuf* pbuf = pbuf_skip(pbuf_stream->pbuf, pbuf_stream->offset, &target_offset); - - if ((pbuf == NULL) || (pbuf->len == 0)) { - return ERR_BUF; - } - - chunk_len = LWIP_MIN(len, pbuf->len); - err = snmp_pbuf_stream_writebuf(target_pbuf_stream, &((u8_t*)pbuf->payload)[target_offset], chunk_len); - if (err != ERR_OK) { - return err; - } - - pbuf_stream->offset += chunk_len; - pbuf_stream->length -= chunk_len; - len -= chunk_len; - } - - return ERR_OK; -} - -err_t -snmp_pbuf_stream_seek(struct snmp_pbuf_stream* pbuf_stream, s32_t offset) -{ - if ((offset < 0) || (offset > pbuf_stream->length)) { - /* we cannot seek backwards or forward behind stream end */ - return ERR_ARG; - } - - pbuf_stream->offset += (u16_t)offset; - pbuf_stream->length -= (u16_t)offset; - - return ERR_OK; -} - -err_t -snmp_pbuf_stream_seek_abs(struct snmp_pbuf_stream* pbuf_stream, u32_t offset) -{ - s32_t rel_offset = offset - pbuf_stream->offset; - return snmp_pbuf_stream_seek(pbuf_stream, rel_offset); -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.h deleted file mode 100644 index 9778de774e6b38e958d68262ea787619cb804c3e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_pbuf_stream.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file - * SNMP pbuf stream wrapper (internal API, do not use in client code). - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#ifndef LWIP_HDR_APPS_SNMP_PBUF_STREAM_H -#define LWIP_HDR_APPS_SNMP_PBUF_STREAM_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP - -#include "lwip/err.h" -#include "lwip/pbuf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct snmp_pbuf_stream -{ - struct pbuf* pbuf; - u16_t offset; - u16_t length; -}; - -err_t snmp_pbuf_stream_init(struct snmp_pbuf_stream* pbuf_stream, struct pbuf* p, u16_t offset, u16_t length); -err_t snmp_pbuf_stream_read(struct snmp_pbuf_stream* pbuf_stream, u8_t* data); -err_t snmp_pbuf_stream_write(struct snmp_pbuf_stream* pbuf_stream, u8_t data); -err_t snmp_pbuf_stream_writebuf(struct snmp_pbuf_stream* pbuf_stream, const void* buf, u16_t buf_len); -err_t snmp_pbuf_stream_writeto(struct snmp_pbuf_stream* pbuf_stream, struct snmp_pbuf_stream* target_pbuf_stream, u16_t len); -err_t snmp_pbuf_stream_seek(struct snmp_pbuf_stream* pbuf_stream, s32_t offset); -err_t snmp_pbuf_stream_seek_abs(struct snmp_pbuf_stream* pbuf_stream, u32_t offset); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* LWIP_HDR_APPS_SNMP_PBUF_STREAM_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_raw.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_raw.c deleted file mode 100644 index 4a40864fc9d20c17e2ead5eee8866dcb7e6bc894..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_raw.c +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * SNMP RAW API frontend. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - */ - -#include "lwip/apps/snmp_opts.h" -#include "lwip/ip_addr.h" - -#if LWIP_SNMP && SNMP_USE_RAW - -#include "lwip/udp.h" -#include "lwip/ip.h" -#include "snmp_msg.h" - -/* lwIP UDP receive callback function */ -static void -snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - LWIP_UNUSED_ARG(arg); - - snmp_receive(pcb, p, addr, port); - - pbuf_free(p); -} - -err_t -snmp_sendto(void *handle, struct pbuf *p, const ip_addr_t *dst, u16_t port) -{ - return udp_sendto((struct udp_pcb*)handle, p, dst, port); -} - -u8_t -snmp_get_local_ip_for_dst(void* handle, const ip_addr_t *dst, ip_addr_t *result) -{ - struct udp_pcb* udp_pcb = (struct udp_pcb*)handle; - struct netif *dst_if; - const ip_addr_t* dst_ip; - - LWIP_UNUSED_ARG(udp_pcb); /* unused in case of IPV4 only configuration */ - - ip_route_get_local_ip(&udp_pcb->local_ip, dst, dst_if, dst_ip); - - if ((dst_if != NULL) && (dst_ip != NULL)) { - ip_addr_copy(*result, *dst_ip); - return 1; - } else { - return 0; - } -} - -/** - * @ingroup snmp_core - * Starts SNMP Agent. - * Allocates UDP pcb and binds it to IP_ANY_TYPE port 161. - */ -void -snmp_init(void) -{ - err_t err; - - struct udp_pcb *snmp_pcb = udp_new_ip_type(IPADDR_TYPE_ANY); - LWIP_ERROR("snmp_raw: no PCB", (snmp_pcb != NULL), return;); - - snmp_traps_handle = snmp_pcb; - - udp_recv(snmp_pcb, snmp_recv, (void *)SNMP_IN_PORT); - err = udp_bind(snmp_pcb, IP_ANY_TYPE, SNMP_IN_PORT); - LWIP_ERROR("snmp_raw: Unable to bind PCB", (err == ERR_OK), return;); -} - -#endif /* LWIP_SNMP && SNMP_USE_RAW */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_scalar.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_scalar.c deleted file mode 100644 index 136c9eccd0aff71ee91aae17277739f947fd6d67..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_scalar.c +++ /dev/null @@ -1,220 +0,0 @@ -/** - * @file - * SNMP scalar node support implementation. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp_scalar.h" -#include "lwip/apps/snmp_core.h" - -static s16_t snmp_scalar_array_get_value(struct snmp_node_instance* instance, void* value); -static snmp_err_t snmp_scalar_array_set_test(struct snmp_node_instance* instance, u16_t value_len, void* value); -static snmp_err_t snmp_scalar_array_set_value(struct snmp_node_instance* instance, u16_t value_len, void* value); - -snmp_err_t -snmp_scalar_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - const struct snmp_scalar_node* scalar_node = (const struct snmp_scalar_node*)(const void*)instance->node; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - /* scalar only has one dedicated instance: .0 */ - if ((instance->instance_oid.len != 1) || (instance->instance_oid.id[0] != 0)) { - return SNMP_ERR_NOSUCHINSTANCE; - } - - instance->access = scalar_node->access; - instance->asn1_type = scalar_node->asn1_type; - instance->get_value = scalar_node->get_value; - instance->set_test = scalar_node->set_test; - instance->set_value = scalar_node->set_value; - return SNMP_ERR_NOERROR; -} - -snmp_err_t -snmp_scalar_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - /* because our only instance is .0 we can only return a next instance if no instance oid is passed */ - if (instance->instance_oid.len == 0) { - instance->instance_oid.len = 1; - instance->instance_oid.id[0] = 0; - - return snmp_scalar_get_instance(root_oid, root_oid_len, instance); - } - - return SNMP_ERR_NOSUCHINSTANCE; -} - - -snmp_err_t -snmp_scalar_array_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - if ((instance->instance_oid.len == 2) && (instance->instance_oid.id[1] == 0)) { - const struct snmp_scalar_array_node* array_node = (const struct snmp_scalar_array_node*)(const void*)instance->node; - const struct snmp_scalar_array_node_def* array_node_def = array_node->array_nodes; - u32_t i = 0; - - while (i < array_node->array_node_count) { - if (array_node_def->oid == instance->instance_oid.id[0]) { - break; - } - - array_node_def++; - i++; - } - - if (i < array_node->array_node_count) { - instance->access = array_node_def->access; - instance->asn1_type = array_node_def->asn1_type; - instance->get_value = snmp_scalar_array_get_value; - instance->set_test = snmp_scalar_array_set_test; - instance->set_value = snmp_scalar_array_set_value; - instance->reference.const_ptr = array_node_def; - - return SNMP_ERR_NOERROR; - } - } - - return SNMP_ERR_NOSUCHINSTANCE; -} - -snmp_err_t -snmp_scalar_array_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - const struct snmp_scalar_array_node* array_node = (const struct snmp_scalar_array_node*)(const void*)instance->node; - const struct snmp_scalar_array_node_def* array_node_def = array_node->array_nodes; - const struct snmp_scalar_array_node_def* result = NULL; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - if ((instance->instance_oid.len == 0) && (array_node->array_node_count > 0)) { - /* return node with lowest OID */ - u16_t i = 0; - - result = array_node_def; - array_node_def++; - - for (i = 1; i < array_node->array_node_count; i++) { - if (array_node_def->oid < result->oid) { - result = array_node_def; - } - array_node_def++; - } - } else if (instance->instance_oid.len >= 1) { - if (instance->instance_oid.len == 1) { - /* if we have the requested OID we return its instance, otherwise we search for the next available */ - u16_t i = 0; - while (i < array_node->array_node_count) { - if (array_node_def->oid == instance->instance_oid.id[0]) { - result = array_node_def; - break; - } - - array_node_def++; - i++; - } - } - if (result == NULL) { - u32_t oid_dist = 0xFFFFFFFFUL; - u16_t i = 0; - array_node_def = array_node->array_nodes; /* may be already at the end when if case before was executed without result -> reinitialize to start */ - while (i < array_node->array_node_count) { - if ((array_node_def->oid > instance->instance_oid.id[0]) && - ((u32_t)(array_node_def->oid - instance->instance_oid.id[0]) < oid_dist)) { - result = array_node_def; - oid_dist = array_node_def->oid - instance->instance_oid.id[0]; - } - - array_node_def++; - i++; - } - } - } - - if (result == NULL) { - /* nothing to return */ - return SNMP_ERR_NOSUCHINSTANCE; - } - - instance->instance_oid.len = 2; - instance->instance_oid.id[0] = result->oid; - instance->instance_oid.id[1] = 0; - - instance->access = result->access; - instance->asn1_type = result->asn1_type; - instance->get_value = snmp_scalar_array_get_value; - instance->set_test = snmp_scalar_array_set_test; - instance->set_value = snmp_scalar_array_set_value; - instance->reference.const_ptr = result; - - return SNMP_ERR_NOERROR; -} - -static s16_t -snmp_scalar_array_get_value(struct snmp_node_instance* instance, void* value) -{ - const struct snmp_scalar_array_node* array_node = (const struct snmp_scalar_array_node*)(const void*)instance->node; - const struct snmp_scalar_array_node_def* array_node_def = (const struct snmp_scalar_array_node_def*)instance->reference.const_ptr; - - return array_node->get_value(array_node_def, value); -} - -static snmp_err_t -snmp_scalar_array_set_test(struct snmp_node_instance* instance, u16_t value_len, void* value) -{ - const struct snmp_scalar_array_node* array_node = (const struct snmp_scalar_array_node*)(const void*)instance->node; - const struct snmp_scalar_array_node_def* array_node_def = (const struct snmp_scalar_array_node_def*)instance->reference.const_ptr; - - return array_node->set_test(array_node_def, value_len, value); -} - -static snmp_err_t -snmp_scalar_array_set_value(struct snmp_node_instance* instance, u16_t value_len, void* value) -{ - const struct snmp_scalar_array_node* array_node = (const struct snmp_scalar_array_node*)(const void*)instance->node; - const struct snmp_scalar_array_node_def* array_node_def = (const struct snmp_scalar_array_node_def*)instance->reference.const_ptr; - - return array_node->set_value(array_node_def, value_len, value); -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_table.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_table.c deleted file mode 100644 index 63ca5956330e2e2825f812379cff3b0809689a28..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_table.c +++ /dev/null @@ -1,343 +0,0 @@ -/** - * @file - * SNMP table support implementation. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp_core.h" -#include "lwip/apps/snmp_table.h" -#include - -snmp_err_t snmp_table_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - snmp_err_t ret = SNMP_ERR_NOSUCHINSTANCE; - const struct snmp_table_node* table_node = (const struct snmp_table_node*)(const void*)instance->node; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - /* check min. length (fixed row entry definition, column, row instance oid with at least one entry */ - /* fixed row entry always has oid 1 */ - if ((instance->instance_oid.len >= 3) && (instance->instance_oid.id[0] == 1)) { - /* search column */ - const struct snmp_table_col_def* col_def = table_node->columns; - u16_t i = table_node->column_count; - while (i > 0) { - if (col_def->index == instance->instance_oid.id[1]) { - break; - } - - col_def++; - i--; - } - - if (i > 0) { - /* everything may be overwritten by get_cell_instance_method() in order to implement special handling for single columns/cells */ - instance->asn1_type = col_def->asn1_type; - instance->access = col_def->access; - instance->get_value = table_node->get_value; - instance->set_test = table_node->set_test; - instance->set_value = table_node->set_value; - - ret = table_node->get_cell_instance( - &(instance->instance_oid.id[1]), - &(instance->instance_oid.id[2]), - instance->instance_oid.len-2, - instance); - } - } - - return ret; -} - -snmp_err_t snmp_table_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - const struct snmp_table_node* table_node = (const struct snmp_table_node*)(const void*)instance->node; - const struct snmp_table_col_def* col_def; - struct snmp_obj_id row_oid; - u32_t column = 0; - snmp_err_t result; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - /* check that first part of id is 0 or 1, referencing fixed row entry */ - if ((instance->instance_oid.len > 0) && (instance->instance_oid.id[0] > 1)) { - return SNMP_ERR_NOSUCHINSTANCE; - } - if (instance->instance_oid.len > 1) { - column = instance->instance_oid.id[1]; - } - if (instance->instance_oid.len > 2) { - snmp_oid_assign(&row_oid, &(instance->instance_oid.id[2]), instance->instance_oid.len - 2); - } else { - row_oid.len = 0; - } - - instance->get_value = table_node->get_value; - instance->set_test = table_node->set_test; - instance->set_value = table_node->set_value; - - /* resolve column and value */ - do { - u16_t i; - const struct snmp_table_col_def* next_col_def = NULL; - col_def = table_node->columns; - - for (i = 0; i < table_node->column_count; i++) { - if (col_def->index == column) { - next_col_def = col_def; - break; - } else if ((col_def->index > column) && ((next_col_def == NULL) || (col_def->index < next_col_def->index))) { - next_col_def = col_def; - } - col_def++; - } - - if (next_col_def == NULL) { - /* no further column found */ - return SNMP_ERR_NOSUCHINSTANCE; - } - - instance->asn1_type = next_col_def->asn1_type; - instance->access = next_col_def->access; - - result = table_node->get_next_cell_instance( - &next_col_def->index, - &row_oid, - instance); - - if (result == SNMP_ERR_NOERROR) { - col_def = next_col_def; - break; - } - - row_oid.len = 0; /* reset row_oid because we switch to next column and start with the first entry there */ - column = next_col_def->index + 1; - } while (1); - - /* build resulting oid */ - instance->instance_oid.len = 2; - instance->instance_oid.id[0] = 1; - instance->instance_oid.id[1] = col_def->index; - snmp_oid_append(&instance->instance_oid, row_oid.id, row_oid.len); - - return SNMP_ERR_NOERROR; -} - - -snmp_err_t snmp_table_simple_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - snmp_err_t ret = SNMP_ERR_NOSUCHINSTANCE; - const struct snmp_table_simple_node* table_node = (const struct snmp_table_simple_node*)(const void*)instance->node; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - /* check min. length (fixed row entry definition, column, row instance oid with at least one entry */ - /* fixed row entry always has oid 1 */ - if ((instance->instance_oid.len >= 3) && (instance->instance_oid.id[0] == 1)) { - ret = table_node->get_cell_value( - &(instance->instance_oid.id[1]), - &(instance->instance_oid.id[2]), - instance->instance_oid.len-2, - &instance->reference, - &instance->reference_len); - - if (ret == SNMP_ERR_NOERROR) { - /* search column */ - const struct snmp_table_simple_col_def* col_def = table_node->columns; - u32_t i = table_node->column_count; - while (i > 0) { - if (col_def->index == instance->instance_oid.id[1]) { - break; - } - - col_def++; - i--; - } - - if (i > 0) { - instance->asn1_type = col_def->asn1_type; - instance->access = SNMP_NODE_INSTANCE_READ_ONLY; - instance->set_test = NULL; - instance->set_value = NULL; - - switch (col_def->data_type) { - case SNMP_VARIANT_VALUE_TYPE_U32: - instance->get_value = snmp_table_extract_value_from_u32ref; - break; - case SNMP_VARIANT_VALUE_TYPE_S32: - instance->get_value = snmp_table_extract_value_from_s32ref; - break; - case SNMP_VARIANT_VALUE_TYPE_PTR: /* fall through */ - case SNMP_VARIANT_VALUE_TYPE_CONST_PTR: - instance->get_value = snmp_table_extract_value_from_refconstptr; - break; - default: - LWIP_DEBUGF(SNMP_DEBUG, ("snmp_table_simple_get_instance(): unknown column data_type: %d\n", col_def->data_type)); - return SNMP_ERR_GENERROR; - } - - ret = SNMP_ERR_NOERROR; - } else { - ret = SNMP_ERR_NOSUCHINSTANCE; - } - } - } - - return ret; -} - -snmp_err_t snmp_table_simple_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - const struct snmp_table_simple_node* table_node = (const struct snmp_table_simple_node*)(const void*)instance->node; - const struct snmp_table_simple_col_def* col_def; - struct snmp_obj_id row_oid; - u32_t column = 0; - snmp_err_t result; - - LWIP_UNUSED_ARG(root_oid); - LWIP_UNUSED_ARG(root_oid_len); - - /* check that first part of id is 0 or 1, referencing fixed row entry */ - if ((instance->instance_oid.len > 0) && (instance->instance_oid.id[0] > 1)) { - return SNMP_ERR_NOSUCHINSTANCE; - } - if (instance->instance_oid.len > 1) { - column = instance->instance_oid.id[1]; - } - if (instance->instance_oid.len > 2) { - snmp_oid_assign(&row_oid, &(instance->instance_oid.id[2]), instance->instance_oid.len - 2); - } else { - row_oid.len = 0; - } - - /* resolve column and value */ - do { - u32_t i; - const struct snmp_table_simple_col_def* next_col_def = NULL; - col_def = table_node->columns; - - for (i = 0; i < table_node->column_count; i++) { - if (col_def->index == column) { - next_col_def = col_def; - break; - } else if ((col_def->index > column) && ((next_col_def == NULL) || - (col_def->index < next_col_def->index))) { - next_col_def = col_def; - } - col_def++; - } - - if (next_col_def == NULL) { - /* no further column found */ - return SNMP_ERR_NOSUCHINSTANCE; - } - - result = table_node->get_next_cell_instance_and_value( - &next_col_def->index, - &row_oid, - &instance->reference, - &instance->reference_len); - - if (result == SNMP_ERR_NOERROR) { - col_def = next_col_def; - break; - } - - row_oid.len = 0; /* reset row_oid because we switch to next column and start with the first entry there */ - column = next_col_def->index + 1; - } - while (1); - - instance->asn1_type = col_def->asn1_type; - instance->access = SNMP_NODE_INSTANCE_READ_ONLY; - instance->set_test = NULL; - instance->set_value = NULL; - - switch (col_def->data_type) { - case SNMP_VARIANT_VALUE_TYPE_U32: - instance->get_value = snmp_table_extract_value_from_u32ref; - break; - case SNMP_VARIANT_VALUE_TYPE_S32: - instance->get_value = snmp_table_extract_value_from_s32ref; - break; - case SNMP_VARIANT_VALUE_TYPE_PTR: /* fall through */ - case SNMP_VARIANT_VALUE_TYPE_CONST_PTR: - instance->get_value = snmp_table_extract_value_from_refconstptr; - break; - default: - LWIP_DEBUGF(SNMP_DEBUG, ("snmp_table_simple_get_instance(): unknown column data_type: %d\n", col_def->data_type)); - return SNMP_ERR_GENERROR; - } - - /* build resulting oid */ - instance->instance_oid.len = 2; - instance->instance_oid.id[0] = 1; - instance->instance_oid.id[1] = col_def->index; - snmp_oid_append(&instance->instance_oid, row_oid.id, row_oid.len); - - return SNMP_ERR_NOERROR; -} - - -s16_t -snmp_table_extract_value_from_s32ref(struct snmp_node_instance* instance, void* value) -{ - s32_t *dst = (s32_t*)value; - *dst = instance->reference.s32; - return sizeof(*dst); -} - -s16_t -snmp_table_extract_value_from_u32ref(struct snmp_node_instance* instance, void* value) -{ - u32_t *dst = (u32_t*)value; - *dst = instance->reference.u32; - return sizeof(*dst); -} - -s16_t -snmp_table_extract_value_from_refconstptr(struct snmp_node_instance* instance, void* value) -{ - MEMCPY(value, instance->reference.const_ptr, instance->reference_len); - return (u16_t)instance->reference_len; -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_threadsync.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_threadsync.c deleted file mode 100644 index 204f265dc8dd71879bf695b51dfea1c934f1eeac..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_threadsync.c +++ /dev/null @@ -1,219 +0,0 @@ -/** - * @file - * SNMP thread synchronization implementation. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dirk Ziegelmeier - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP && (NO_SYS == 0) /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp_threadsync.h" -#include "lwip/apps/snmp_core.h" -#include "lwip/sys.h" -#include - -static void -call_synced_function(struct threadsync_data *call_data, snmp_threadsync_called_fn fn) -{ - sys_mutex_lock(&call_data->threadsync_node->instance->sem_usage_mutex); - call_data->threadsync_node->instance->sync_fn(fn, call_data); - sys_sem_wait(&call_data->threadsync_node->instance->sem); - sys_mutex_unlock(&call_data->threadsync_node->instance->sem_usage_mutex); -} - -static void -threadsync_get_value_synced(void *ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - - call_data->retval.s16 = call_data->proxy_instance.get_value(&call_data->proxy_instance, call_data->arg1.value); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static s16_t -threadsync_get_value(struct snmp_node_instance* instance, void* value) -{ - struct threadsync_data *call_data = (struct threadsync_data*)instance->reference.ptr; - - call_data->arg1.value = value; - call_synced_function(call_data, threadsync_get_value_synced); - - return call_data->retval.s16; -} - -static void -threadsync_set_test_synced(void *ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - - call_data->retval.err = call_data->proxy_instance.set_test(&call_data->proxy_instance, call_data->arg2.len, call_data->arg1.value); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static snmp_err_t -threadsync_set_test(struct snmp_node_instance* instance, u16_t len, void *value) -{ - struct threadsync_data *call_data = (struct threadsync_data*)instance->reference.ptr; - - call_data->arg1.value = value; - call_data->arg2.len = len; - call_synced_function(call_data, threadsync_set_test_synced); - - return call_data->retval.err; -} - -static void -threadsync_set_value_synced(void *ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - - call_data->retval.err = call_data->proxy_instance.set_value(&call_data->proxy_instance, call_data->arg2.len, call_data->arg1.value); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static snmp_err_t -threadsync_set_value(struct snmp_node_instance* instance, u16_t len, void *value) -{ - struct threadsync_data *call_data = (struct threadsync_data*)instance->reference.ptr; - - call_data->arg1.value = value; - call_data->arg2.len = len; - call_synced_function(call_data, threadsync_set_value_synced); - - return call_data->retval.err; -} - -static void -threadsync_release_instance_synced(void* ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - - call_data->proxy_instance.release_instance(&call_data->proxy_instance); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static void -threadsync_release_instance(struct snmp_node_instance *instance) -{ - struct threadsync_data *call_data = (struct threadsync_data*)instance->reference.ptr; - - if (call_data->proxy_instance.release_instance != NULL) { - call_synced_function(call_data, threadsync_release_instance_synced); - } -} - -static void -get_instance_synced(void* ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - const struct snmp_leaf_node *leaf = (const struct snmp_leaf_node*)(const void*)call_data->proxy_instance.node; - - call_data->retval.err = leaf->get_instance(call_data->arg1.root_oid, call_data->arg2.root_oid_len, &call_data->proxy_instance); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static void -get_next_instance_synced(void* ctx) -{ - struct threadsync_data *call_data = (struct threadsync_data*)ctx; - const struct snmp_leaf_node *leaf = (const struct snmp_leaf_node*)(const void*)call_data->proxy_instance.node; - - call_data->retval.err = leaf->get_next_instance(call_data->arg1.root_oid, call_data->arg2.root_oid_len, &call_data->proxy_instance); - - sys_sem_signal(&call_data->threadsync_node->instance->sem); -} - -static snmp_err_t -do_sync(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance, snmp_threadsync_called_fn fn) -{ - const struct snmp_threadsync_node *threadsync_node = (const struct snmp_threadsync_node*)(const void*)instance->node; - struct threadsync_data *call_data = &threadsync_node->instance->data; - - if (threadsync_node->node.node.oid != threadsync_node->target->node.oid) { - LWIP_DEBUGF(SNMP_DEBUG, ("Sync node OID does not match target node OID")); - return SNMP_ERR_NOSUCHINSTANCE; - } - - memset(&call_data->proxy_instance, 0, sizeof(call_data->proxy_instance)); - - instance->reference.ptr = call_data; - snmp_oid_assign(&call_data->proxy_instance.instance_oid, instance->instance_oid.id, instance->instance_oid.len); - - call_data->proxy_instance.node = &threadsync_node->target->node; - call_data->threadsync_node = threadsync_node; - - call_data->arg1.root_oid = root_oid; - call_data->arg2.root_oid_len = root_oid_len; - call_synced_function(call_data, fn); - - if (call_data->retval.err == SNMP_ERR_NOERROR) { - instance->access = call_data->proxy_instance.access; - instance->asn1_type = call_data->proxy_instance.asn1_type; - instance->release_instance = threadsync_release_instance; - instance->get_value = (call_data->proxy_instance.get_value != NULL)? threadsync_get_value : NULL; - instance->set_value = (call_data->proxy_instance.set_value != NULL)? threadsync_set_value : NULL; - instance->set_test = (call_data->proxy_instance.set_test != NULL)? threadsync_set_test : NULL; - snmp_oid_assign(&instance->instance_oid, call_data->proxy_instance.instance_oid.id, call_data->proxy_instance.instance_oid.len); - } - - return call_data->retval.err; -} - -snmp_err_t -snmp_threadsync_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - return do_sync(root_oid, root_oid_len, instance, get_instance_synced); -} - -snmp_err_t -snmp_threadsync_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance) -{ - return do_sync(root_oid, root_oid_len, instance, get_next_instance_synced); -} - -/** Initializes thread synchronization instance */ -void snmp_threadsync_init(struct snmp_threadsync_instance *instance, snmp_threadsync_synchronizer_fn sync_fn) -{ - err_t err = sys_mutex_new(&instance->sem_usage_mutex); - LWIP_ASSERT("Failed to set up mutex", err == ERR_OK); - err = sys_sem_new(&instance->sem, 0); - LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("Failed to set up semaphore", err == ERR_OK); - instance->sync_fn = sync_fn; -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_traps.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_traps.c deleted file mode 100644 index 0d2df64991b8e2050cb9c5842f57c0501e4db84c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmp_traps.c +++ /dev/null @@ -1,445 +0,0 @@ -/** - * @file - * SNMPv1 traps implementation. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * Christiaan Simons - * - */ - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include - -#include "lwip/snmp.h" -#include "lwip/sys.h" -#include "lwip/apps/snmp.h" -#include "lwip/apps/snmp_core.h" -#include "snmp_msg.h" -#include "snmp_asn1.h" -#include "snmp_core_priv.h" - -struct snmp_msg_trap -{ - /* source enterprise ID (sysObjectID) */ - const struct snmp_obj_id *enterprise; - /* source IP address, raw network order format */ - ip_addr_t sip; - /* generic trap code */ - u32_t gen_trap; - /* specific trap code */ - u32_t spc_trap; - /* timestamp */ - u32_t ts; - /* snmp_version */ - u32_t snmp_version; - - /* output trap lengths used in ASN encoding */ - /* encoding pdu length */ - u16_t pdulen; - /* encoding community length */ - u16_t comlen; - /* encoding sequence length */ - u16_t seqlen; - /* encoding varbinds sequence length */ - u16_t vbseqlen; -}; - -static u16_t snmp_trap_varbind_sum(struct snmp_msg_trap *trap, struct snmp_varbind *varbinds); -static u16_t snmp_trap_header_sum(struct snmp_msg_trap *trap, u16_t vb_len); -static void snmp_trap_header_enc(struct snmp_msg_trap *trap, struct snmp_pbuf_stream *pbuf_stream); -static void snmp_trap_varbind_enc(struct snmp_msg_trap *trap, struct snmp_pbuf_stream *pbuf_stream, struct snmp_varbind *varbinds); - -/** Agent community string for sending traps */ -extern const char *snmp_community_trap; - -void* snmp_traps_handle; - -struct snmp_trap_dst -{ - /* destination IP address in network order */ - ip_addr_t dip; - /* set to 0 when disabled, >0 when enabled */ - u8_t enable; -}; -static struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS]; - -static u8_t snmp_auth_traps_enabled = 0; - -/** - * @ingroup snmp_traps - * Sets enable switch for this trap destination. - * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 - * @param enable switch if 0 destination is disabled >0 enabled. - */ -void -snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) -{ - if (dst_idx < SNMP_TRAP_DESTINATIONS) { - trap_dst[dst_idx].enable = enable; - } -} - -/** - * @ingroup snmp_traps - * Sets IPv4 address for this trap destination. - * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 - * @param dst IPv4 address in host order. - */ -void -snmp_trap_dst_ip_set(u8_t dst_idx, const ip_addr_t *dst) -{ - if (dst_idx < SNMP_TRAP_DESTINATIONS) { - ip_addr_set(&trap_dst[dst_idx].dip, dst); - } -} - -/** - * @ingroup snmp_traps - * Enable/disable authentication traps - */ -void -snmp_set_auth_traps_enabled(u8_t enable) -{ - snmp_auth_traps_enabled = enable; -} - -/** - * @ingroup snmp_traps - * Get authentication traps enabled state - */ -u8_t -snmp_get_auth_traps_enabled(void) -{ - return snmp_auth_traps_enabled; -} - - -/** - * @ingroup snmp_traps - * Sends a generic or enterprise specific trap message. - * - * @param eoid points to enterprise object identifier - * @param generic_trap is the trap code - * @param specific_trap used for enterprise traps when generic_trap == 6 - * @param varbinds linked list of varbinds to be sent - * @return ERR_OK when success, ERR_MEM if we're out of memory - * - * @note the use of the enterprise identifier field - * is per RFC1215. - * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps - * and .iso.org.dod.internet.private.enterprises.yourenterprise - * (sysObjectID) for specific traps. - */ -err_t -snmp_send_trap(const struct snmp_obj_id* eoid, s32_t generic_trap, s32_t specific_trap, struct snmp_varbind *varbinds) -{ - struct snmp_msg_trap trap_msg; - struct snmp_trap_dst *td; - struct pbuf *p; - u16_t i, tot_len; - err_t err = ERR_OK; - - trap_msg.snmp_version = 0; - - for (i = 0, td = &trap_dst[0]; i < SNMP_TRAP_DESTINATIONS; i++, td++) { - if ((td->enable != 0) && !ip_addr_isany(&td->dip)) { - /* lookup current source address for this dst */ - if (snmp_get_local_ip_for_dst(snmp_traps_handle, &td->dip, &trap_msg.sip)) { - if (eoid == NULL) { - trap_msg.enterprise = snmp_get_device_enterprise_oid(); - } else { - trap_msg.enterprise = eoid; - } - - trap_msg.gen_trap = generic_trap; - if (generic_trap == SNMP_GENTRAP_ENTERPRISE_SPECIFIC) { - trap_msg.spc_trap = specific_trap; - } else { - trap_msg.spc_trap = 0; - } - - MIB2_COPY_SYSUPTIME_TO(&trap_msg.ts); - - /* pass 0, calculate length fields */ - tot_len = snmp_trap_varbind_sum(&trap_msg, varbinds); - tot_len = snmp_trap_header_sum(&trap_msg, tot_len); - - /* allocate pbuf(s) */ - p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_RAM); - if (p != NULL) { - struct snmp_pbuf_stream pbuf_stream; - snmp_pbuf_stream_init(&pbuf_stream, p, 0, tot_len); - - /* pass 1, encode packet ino the pbuf(s) */ - snmp_trap_header_enc(&trap_msg, &pbuf_stream); - snmp_trap_varbind_enc(&trap_msg, &pbuf_stream, varbinds); - - snmp_stats.outtraps++; - snmp_stats.outpkts++; - - /** send to the TRAP destination */ - snmp_sendto(snmp_traps_handle, p, &td->dip, SNMP_TRAP_PORT); - pbuf_free(p); - } else { - err = ERR_MEM; - } - } else { - /* routing error */ - err = ERR_RTE; - } - } - } - return err; -} - -/** - * @ingroup snmp_traps - * Send generic SNMP trap - */ -err_t -snmp_send_trap_generic(s32_t generic_trap) -{ - static const struct snmp_obj_id oid = { 7, { 1, 3, 6, 1, 2, 1, 11 } }; - return snmp_send_trap(&oid, generic_trap, 0, NULL); -} - -/** - * @ingroup snmp_traps - * Send specific SNMP trap with variable bindings - */ -err_t -snmp_send_trap_specific(s32_t specific_trap, struct snmp_varbind *varbinds) -{ - return snmp_send_trap(NULL, SNMP_GENTRAP_ENTERPRISE_SPECIFIC, specific_trap, varbinds); -} - -/** - * @ingroup snmp_traps - * Send coldstart trap - */ -void -snmp_coldstart_trap(void) -{ - snmp_send_trap_generic(SNMP_GENTRAP_COLDSTART); -} - -/** - * @ingroup snmp_traps - * Send authentication failure trap (used internally by agent) - */ -void -snmp_authfail_trap(void) -{ - if (snmp_auth_traps_enabled != 0) { - snmp_send_trap_generic(SNMP_GENTRAP_AUTH_FAILURE); - } -} - -static u16_t -snmp_trap_varbind_sum(struct snmp_msg_trap *trap, struct snmp_varbind *varbinds) -{ - struct snmp_varbind *varbind; - u16_t tot_len; - u8_t tot_len_len; - - tot_len = 0; - varbind = varbinds; - while (varbind != NULL) { - struct snmp_varbind_len len; - - if (snmp_varbind_length(varbind, &len) == ERR_OK) { - tot_len += 1 + len.vb_len_len + len.vb_value_len; - } - - varbind = varbind->next; - } - - trap->vbseqlen = tot_len; - snmp_asn1_enc_length_cnt(trap->vbseqlen, &tot_len_len); - tot_len += 1 + tot_len_len; - - return tot_len; -} - -/** - * Sums trap header field lengths from tail to head and - * returns trap_header_lengths for second encoding pass. - * - * @param trap Trap message - * @param vb_len varbind-list length - * @return the required length for encoding the trap header - */ -static u16_t -snmp_trap_header_sum(struct snmp_msg_trap *trap, u16_t vb_len) -{ - u16_t tot_len; - u16_t len; - u8_t lenlen; - - tot_len = vb_len; - - snmp_asn1_enc_u32t_cnt(trap->ts, &len); - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - snmp_asn1_enc_s32t_cnt(trap->spc_trap, &len); - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - snmp_asn1_enc_s32t_cnt(trap->gen_trap, &len); - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - if (IP_IS_V6_VAL(trap->sip)) { -#if LWIP_IPV6 - len = sizeof(ip_2_ip6(&trap->sip)->addr); -#endif - } else { -#if LWIP_IPV4 - len = sizeof(ip_2_ip4(&trap->sip)->addr); -#endif - } - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - snmp_asn1_enc_oid_cnt(trap->enterprise->id, trap->enterprise->len, &len); - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - trap->pdulen = tot_len; - snmp_asn1_enc_length_cnt(trap->pdulen, &lenlen); - tot_len += 1 + lenlen; - - trap->comlen = (u16_t)LWIP_MIN(strlen(snmp_community_trap), 0xFFFF); - snmp_asn1_enc_length_cnt(trap->comlen, &lenlen); - tot_len += 1 + lenlen + trap->comlen; - - snmp_asn1_enc_s32t_cnt(trap->snmp_version, &len); - snmp_asn1_enc_length_cnt(len, &lenlen); - tot_len += 1 + len + lenlen; - - trap->seqlen = tot_len; - snmp_asn1_enc_length_cnt(trap->seqlen, &lenlen); - tot_len += 1 + lenlen; - - return tot_len; -} - -static void -snmp_trap_varbind_enc(struct snmp_msg_trap *trap, struct snmp_pbuf_stream *pbuf_stream, struct snmp_varbind *varbinds) -{ - struct snmp_asn1_tlv tlv; - struct snmp_varbind *varbind; - - varbind = varbinds; - - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 0, trap->vbseqlen); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - - while (varbind != NULL) { - snmp_append_outbound_varbind(pbuf_stream, varbind); - - varbind = varbind->next; - } -} - -/** - * Encodes trap header from head to tail. - */ -static void -snmp_trap_header_enc(struct snmp_msg_trap *trap, struct snmp_pbuf_stream *pbuf_stream) -{ - struct snmp_asn1_tlv tlv; - - /* 'Message' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_SEQUENCE, 0, trap->seqlen); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - - /* version */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(trap->snmp_version, &tlv.value_len); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, trap->snmp_version); - - /* community */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OCTET_STRING, 0, trap->comlen); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_raw(pbuf_stream, (const u8_t *)snmp_community_trap, trap->comlen); - - /* 'PDU' sequence */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, (SNMP_ASN1_CLASS_CONTEXT | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_CONTEXT_PDU_TRAP), 0, trap->pdulen); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - - /* object ID */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_OBJECT_ID, 0, 0); - snmp_asn1_enc_oid_cnt(trap->enterprise->id, trap->enterprise->len, &tlv.value_len); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_oid(pbuf_stream, trap->enterprise->id, trap->enterprise->len); - - /* IP addr */ - if (IP_IS_V6_VAL(trap->sip)) { -#if LWIP_IPV6 - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_IPADDR, 0, sizeof(ip_2_ip6(&trap->sip)->addr)); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_raw(pbuf_stream, (const u8_t *)&ip_2_ip6(&trap->sip)->addr, sizeof(ip_2_ip6(&trap->sip)->addr)); -#endif - } else { -#if LWIP_IPV4 - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_IPADDR, 0, sizeof(ip_2_ip4(&trap->sip)->addr)); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_raw(pbuf_stream, (const u8_t *)&ip_2_ip4(&trap->sip)->addr, sizeof(ip_2_ip4(&trap->sip)->addr)); -#endif - } - - /* trap length */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(trap->gen_trap, &tlv.value_len); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, trap->gen_trap); - - /* specific trap */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_INTEGER, 0, 0); - snmp_asn1_enc_s32t_cnt(trap->spc_trap, &tlv.value_len); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, trap->spc_trap); - - /* timestamp */ - SNMP_ASN1_SET_TLV_PARAMS(tlv, SNMP_ASN1_TYPE_TIMETICKS, 0, 0); - snmp_asn1_enc_s32t_cnt(trap->ts, &tlv.value_len); - snmp_ans1_enc_tlv(pbuf_stream, &tlv); - snmp_asn1_enc_s32t(pbuf_stream, tlv.value_len, trap->ts); -} - -#endif /* LWIP_SNMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3.c deleted file mode 100644 index 69fb3a0aafa5bec4a2c5e1bb137218928c71476a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * @file - * Additional SNMPv3 functionality RFC3414 and RFC3826. - */ - -/* - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Elias Oenal - */ - -#include "snmpv3_priv.h" -#include "lwip/apps/snmpv3.h" -#include "lwip/sys.h" -#include - -#if LWIP_SNMP && LWIP_SNMP_V3 - -#ifdef LWIP_SNMPV3_INCLUDE_ENGINE -#include LWIP_SNMPV3_INCLUDE_ENGINE -#endif - -#define SNMP_MAX_TIME_BOOT 2147483647UL - -/** Call this if engine has been changed. Has to reset boots, see below */ -void -snmpv3_engine_id_changed(void) -{ - snmpv3_set_engine_boots(0); -} - -/** According to RFC3414 2.2.2. - * - * The number of times that the SNMP engine has - * (re-)initialized itself since snmpEngineID - * was last configured. - */ -u32_t -snmpv3_get_engine_boots_internal(void) -{ - if (snmpv3_get_engine_boots() == 0 || - snmpv3_get_engine_boots() < SNMP_MAX_TIME_BOOT) { - return snmpv3_get_engine_boots(); - } - - snmpv3_set_engine_boots(SNMP_MAX_TIME_BOOT); - return snmpv3_get_engine_boots(); -} - -/** RFC3414 2.2.2. - * - * Once the timer reaches 2147483647 it gets reset to zero and the - * engine boot ups get incremented. - */ -u32_t -snmpv3_get_engine_time_internal(void) -{ - if (snmpv3_get_engine_time() >= SNMP_MAX_TIME_BOOT) { - snmpv3_reset_engine_time(); - - if (snmpv3_get_engine_boots() < SNMP_MAX_TIME_BOOT - 1) { - snmpv3_set_engine_boots(snmpv3_get_engine_boots() + 1); - } else { - snmpv3_set_engine_boots(SNMP_MAX_TIME_BOOT); - } - } - - return snmpv3_get_engine_time(); -} - -#if LWIP_SNMP_V3_CRYPTO - -/* This function ignores the byte order suggestion in RFC3414 - * since it simply doesn't influence the effectiveness of an IV. - * - * Implementing RFC3826 priv param algorithm if LWIP_RAND is available. - * - * @todo: This is a potential thread safety issue. - */ -err_t -snmpv3_build_priv_param(u8_t* priv_param) -{ -#ifdef LWIP_RAND /* Based on RFC3826 */ - static u8_t init; - static u32_t priv1, priv2; - - /* Lazy initialisation */ - if (init == 0) { - init = 1; - priv1 = LWIP_RAND(); - priv2 = LWIP_RAND(); - } - - SMEMCPY(&priv_param[0], &priv1, sizeof(priv1)); - SMEMCPY(&priv_param[4], &priv2, sizeof(priv2)); - - /* Emulate 64bit increment */ - priv1++; - if (!priv1) { /* Overflow */ - priv2++; - } -#else /* Based on RFC3414 */ - static u32_t ctr; - u32_t boots = LWIP_SNMPV3_GET_ENGINE_BOOTS(); - SMEMCPY(&priv_param[0], &boots, 4); - SMEMCPY(&priv_param[4], &ctr, 4); - ctr++; -#endif - return ERR_OK; -} -#endif /* LWIP_SNMP_V3_CRYPTO */ - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_dummy.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_dummy.c deleted file mode 100644 index bdfe8449940c7c6672d827290462f803594ae5be..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_dummy.c +++ /dev/null @@ -1,145 +0,0 @@ -/** - * @file - * Dummy SNMPv3 functions. - */ - -/* - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Elias Oenal - * Dirk Ziegelmeier - */ - -#include "lwip/apps/snmpv3.h" -#include "snmpv3_priv.h" -#include -#include "lwip/err.h" - -#if LWIP_SNMP && LWIP_SNMP_V3 - -/** - * @param username is a pointer to a string. - * @param auth_algo is a pointer to u8_t. The implementation has to set this if user was found. - * @param auth_key is a pointer to a pointer to a string. Implementation has to set this if user was found. - * @param priv_algo is a pointer to u8_t. The implementation has to set this if user was found. - * @param priv_key is a pointer to a pointer to a string. Implementation has to set this if user was found. - */ -err_t -snmpv3_get_user(const char* username, u8_t *auth_algo, u8_t *auth_key, u8_t *priv_algo, u8_t *priv_key) -{ - const char* engine_id; - u8_t engine_id_len; - - if(strlen(username) == 0) { - return ERR_OK; - } - - if(memcmp(username, "lwip", 4) != 0) { - return ERR_VAL; - } - - snmpv3_get_engine_id(&engine_id, &engine_id_len); - - if(auth_key != NULL) { - snmpv3_password_to_key_sha((const u8_t*)"maplesyrup", 10, - (const u8_t*)engine_id, engine_id_len, - auth_key); - *auth_algo = SNMP_V3_AUTH_ALGO_SHA; - } - if(priv_key != NULL) { - snmpv3_password_to_key_sha((const u8_t*)"maplesyrup", 10, - (const u8_t*)engine_id, engine_id_len, - priv_key); - *priv_algo = SNMP_V3_PRIV_ALGO_DES; - } - return ERR_OK; -} - -/** - * Get engine ID from persistence - * @param id - * @param len - */ -void -snmpv3_get_engine_id(const char **id, u8_t *len) -{ - *id = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02"; - *len = 12; -} - -/** - * Store engine ID in persistence - * @param id - * @param len - */ -err_t -snmpv3_set_engine_id(const char *id, u8_t len) -{ - LWIP_UNUSED_ARG(id); - LWIP_UNUSED_ARG(len); - return ERR_OK; -} - -/** - * Get engine boots from persistence. Must be increased on each boot. - * @return - */ -u32_t -snmpv3_get_engine_boots(void) -{ - return 0; -} - -/** - * Store engine boots in persistence - * @param boots - */ -void -snmpv3_set_engine_boots(u32_t boots) -{ - LWIP_UNUSED_ARG(boots); -} - -/** - * RFC3414 2.2.2. - * Once the timer reaches 2147483647 it gets reset to zero and the - * engine boot ups get incremented. - */ -u32_t -snmpv3_get_engine_time(void) -{ - return 0; -} - -/** - * Reset current engine time to 0 - */ -void -snmpv3_reset_engine_time(void) -{ -} - -#endif /* LWIP_SNMP && LWIP_SNMP_V3 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_mbedtls.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_mbedtls.c deleted file mode 100644 index 0b1eefb87e10397eacd13a52d1688da689a446bb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_mbedtls.c +++ /dev/null @@ -1,331 +0,0 @@ -/** - * @file - * SNMPv3 crypto/auth functions implemented for ARM mbedtls. - */ - -/* - * Copyright (c) 2016 Elias Oenal and Dirk Ziegelmeier. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Elias Oenal - * Dirk Ziegelmeier - */ - -#include "lwip/apps/snmpv3.h" -#include "snmpv3_priv.h" -#include "lwip/arch.h" -#include "snmp_msg.h" -#include "lwip/sys.h" -#include - -#if LWIP_SNMP && LWIP_SNMP_V3 && LWIP_SNMP_V3_MBEDTLS - -#include "mbedtls/md.h" -#include "mbedtls/cipher.h" - -#include "mbedtls/md5.h" -#include "mbedtls/sha1.h" - -err_t -snmpv3_auth(struct snmp_pbuf_stream* stream, u16_t length, - const u8_t* key, u8_t algo, u8_t* hmac_out) -{ - u32_t i; - u8_t key_len; - const mbedtls_md_info_t *md_info; - mbedtls_md_context_t ctx; - struct snmp_pbuf_stream read_stream; - snmp_pbuf_stream_init(&read_stream, stream->pbuf, stream->offset, stream->length); - - if (algo == SNMP_V3_AUTH_ALGO_MD5) { - md_info = mbedtls_md_info_from_type(MBEDTLS_MD_MD5); - key_len = SNMP_V3_MD5_LEN; - } else if (algo == SNMP_V3_AUTH_ALGO_SHA) { - md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA1); - key_len = SNMP_V3_SHA_LEN; - } else { - return ERR_ARG; - } - - mbedtls_md_init(&ctx); - if(mbedtls_md_setup(&ctx, md_info, 1) != 0) { - return ERR_ARG; - } - - if (mbedtls_md_hmac_starts(&ctx, key, key_len) != 0) { - goto free_md; - } - - for (i = 0; i < length; i++) { - u8_t byte; - - if (snmp_pbuf_stream_read(&read_stream, &byte)) { - goto free_md; - } - - if (mbedtls_md_hmac_update(&ctx, &byte, 1) != 0) { - goto free_md; - } - } - - if (mbedtls_md_hmac_finish(&ctx, hmac_out) != 0) { - goto free_md; - } - - mbedtls_md_free(&ctx); - return ERR_OK; - -free_md: - mbedtls_md_free(&ctx); - return ERR_ARG; -} - -#if LWIP_SNMP_V3_CRYPTO - -err_t -snmpv3_crypt(struct snmp_pbuf_stream* stream, u16_t length, - const u8_t* key, const u8_t* priv_param, const u32_t engine_boots, - const u32_t engine_time, u8_t algo, u8_t mode) -{ - size_t i; - mbedtls_cipher_context_t ctx; - const mbedtls_cipher_info_t *cipher_info; - - struct snmp_pbuf_stream read_stream; - struct snmp_pbuf_stream write_stream; - snmp_pbuf_stream_init(&read_stream, stream->pbuf, stream->offset, stream->length); - snmp_pbuf_stream_init(&write_stream, stream->pbuf, stream->offset, stream->length); - mbedtls_cipher_init(&ctx); - - if (algo == SNMP_V3_PRIV_ALGO_DES) { - u8_t iv_local[8]; - u8_t out_bytes[8]; - size_t out_len; - - /* RFC 3414 mandates padding for DES */ - if ((length & 0x07) != 0) { - return ERR_ARG; - } - - cipher_info = mbedtls_cipher_info_from_type(MBEDTLS_CIPHER_DES_CBC); - if(mbedtls_cipher_setup(&ctx, cipher_info) != 0) { - return ERR_ARG; - } - if(mbedtls_cipher_set_padding_mode(&ctx, MBEDTLS_PADDING_NONE) != 0) { - return ERR_ARG; - } - if(mbedtls_cipher_setkey(&ctx, key, 8*8, (mode == SNMP_V3_PRIV_MODE_ENCRYPT)? MBEDTLS_ENCRYPT : MBEDTLS_DECRYPT) != 0) { - goto error; - } - - /* Prepare IV */ - for (i = 0; i < LWIP_ARRAYSIZE(iv_local); i++) { - iv_local[i] = priv_param[i] ^ key[i + 8]; - } - if(mbedtls_cipher_set_iv(&ctx, iv_local, LWIP_ARRAYSIZE(iv_local)) != 0) { - goto error; - } - - for (i = 0; i < length; i += 8) { - size_t j; - u8_t in_bytes[8]; - out_len = LWIP_ARRAYSIZE(out_bytes) ; - - for (j = 0; j < LWIP_ARRAYSIZE(in_bytes); j++) { - snmp_pbuf_stream_read(&read_stream, &in_bytes[j]); - } - - if(mbedtls_cipher_update(&ctx, in_bytes, LWIP_ARRAYSIZE(in_bytes), out_bytes, &out_len) != 0) { - goto error; - } - - snmp_pbuf_stream_writebuf(&write_stream, out_bytes, out_len); - } - - out_len = LWIP_ARRAYSIZE(out_bytes); - if(mbedtls_cipher_finish(&ctx, out_bytes, &out_len) != 0) { - goto error; - } - snmp_pbuf_stream_writebuf(&write_stream, out_bytes, out_len); - } else if (algo == SNMP_V3_PRIV_ALGO_AES) { - u8_t iv_local[16]; - - cipher_info = mbedtls_cipher_info_from_type(MBEDTLS_CIPHER_AES_128_CFB128); - if(mbedtls_cipher_setup(&ctx, cipher_info) != 0) { - return ERR_ARG; - } - if(mbedtls_cipher_setkey(&ctx, key, 16*8, (mode == SNMP_V3_PRIV_MODE_ENCRYPT)? MBEDTLS_ENCRYPT : MBEDTLS_DECRYPT) != 0) { - goto error; - } - - /* - * IV is the big endian concatenation of boots, - * uptime and priv param - see RFC3826. - */ - iv_local[0 + 0] = (engine_boots >> 24) & 0xFF; - iv_local[0 + 1] = (engine_boots >> 16) & 0xFF; - iv_local[0 + 2] = (engine_boots >> 8) & 0xFF; - iv_local[0 + 3] = (engine_boots >> 0) & 0xFF; - iv_local[4 + 0] = (engine_time >> 24) & 0xFF; - iv_local[4 + 1] = (engine_time >> 16) & 0xFF; - iv_local[4 + 2] = (engine_time >> 8) & 0xFF; - iv_local[4 + 3] = (engine_time >> 0) & 0xFF; - SMEMCPY(iv_local + 8, priv_param, 8); - if(mbedtls_cipher_set_iv(&ctx, iv_local, LWIP_ARRAYSIZE(iv_local)) != 0) { - goto error; - } - - for (i = 0; i < length; i++) { - u8_t in_byte; - u8_t out_byte; - size_t out_len = sizeof(out_byte); - - snmp_pbuf_stream_read(&read_stream, &in_byte); - if(mbedtls_cipher_update(&ctx, &in_byte, sizeof(in_byte), &out_byte, &out_len) != 0) { - goto error; - } - snmp_pbuf_stream_write(&write_stream, out_byte); - } - } else { - return ERR_ARG; - } - - mbedtls_cipher_free(&ctx); - return ERR_OK; - -error: - mbedtls_cipher_free(&ctx); - return ERR_OK; -} - -#endif /* LWIP_SNMP_V3_CRYPTO */ - -/* A.2.1. Password to Key Sample Code for MD5 */ -void -snmpv3_password_to_key_md5( - const u8_t *password, /* IN */ - u8_t passwordlen, /* IN */ - const u8_t *engineID, /* IN - pointer to snmpEngineID */ - u8_t engineLength,/* IN - length of snmpEngineID */ - u8_t *key) /* OUT - pointer to caller 16-octet buffer */ -{ - mbedtls_md5_context MD; - u8_t *cp, password_buf[64]; - u32_t password_index = 0; - u8_t i; - u32_t count = 0; - - mbedtls_md5_init(&MD); /* initialize MD5 */ - mbedtls_md5_starts(&MD); - - /**********************************************/ - /* Use while loop until we've done 1 Megabyte */ - /**********************************************/ - while (count < 1048576) { - cp = password_buf; - for (i = 0; i < 64; i++) { - /*************************************************/ - /* Take the next octet of the password, wrapping */ - /* to the beginning of the password as necessary.*/ - /*************************************************/ - *cp++ = password[password_index++ % passwordlen]; - } - mbedtls_md5_update(&MD, password_buf, 64); - count += 64; - } - mbedtls_md5_finish(&MD, key); /* tell MD5 we're done */ - - /*****************************************************/ - /* Now localize the key with the engineID and pass */ - /* through MD5 to produce final key */ - /* May want to ensure that engineLength <= 32, */ - /* otherwise need to use a buffer larger than 64 */ - /*****************************************************/ - SMEMCPY(password_buf, key, 16); - MEMCPY(password_buf + 16, engineID, engineLength); - SMEMCPY(password_buf + 16 + engineLength, key, 16); - - mbedtls_md5_starts(&MD); - mbedtls_md5_update(&MD, password_buf, 32 + engineLength); - mbedtls_md5_finish(&MD, key); - - mbedtls_md5_free(&MD); - return; -} - -/* A.2.2. Password to Key Sample Code for SHA */ -void -snmpv3_password_to_key_sha( - const u8_t *password, /* IN */ - u8_t passwordlen, /* IN */ - const u8_t *engineID, /* IN - pointer to snmpEngineID */ - u8_t engineLength,/* IN - length of snmpEngineID */ - u8_t *key) /* OUT - pointer to caller 20-octet buffer */ -{ - mbedtls_sha1_context SH; - u8_t *cp, password_buf[72]; - u32_t password_index = 0; - u8_t i; - u32_t count = 0; - - mbedtls_sha1_init(&SH); /* initialize SHA */ - mbedtls_sha1_starts(&SH); - - /**********************************************/ - /* Use while loop until we've done 1 Megabyte */ - /**********************************************/ - while (count < 1048576) { - cp = password_buf; - for (i = 0; i < 64; i++) { - /*************************************************/ - /* Take the next octet of the password, wrapping */ - /* to the beginning of the password as necessary.*/ - /*************************************************/ - *cp++ = password[password_index++ % passwordlen]; - } - mbedtls_sha1_update(&SH, password_buf, 64); - count += 64; - } - mbedtls_sha1_finish(&SH, key); /* tell SHA we're done */ - - /*****************************************************/ - /* Now localize the key with the engineID and pass */ - /* through SHA to produce final key */ - /* May want to ensure that engineLength <= 32, */ - /* otherwise need to use a buffer larger than 72 */ - /*****************************************************/ - SMEMCPY(password_buf, key, 20); - MEMCPY(password_buf + 20, engineID, engineLength); - SMEMCPY(password_buf + 20 + engineLength, key, 20); - - mbedtls_sha1_starts(&SH); - mbedtls_sha1_update(&SH, password_buf, 40 + engineLength); - mbedtls_sha1_finish(&SH, key); - - mbedtls_sha1_free(&SH); - return; -} - -#endif /* LWIP_SNMP && LWIP_SNMP_V3 && LWIP_SNMP_V3_MBEDTLS */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_priv.h deleted file mode 100644 index b87666da9935a873e02de7a1df8253dc31cfb40e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/snmp/snmpv3_priv.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * @file - * Additional SNMPv3 functionality RFC3414 and RFC3826 (internal API, do not use in client code). - */ - -/* - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Elias Oenal - */ - -#ifndef LWIP_HDR_APPS_SNMP_V3_PRIV_H -#define LWIP_HDR_APPS_SNMP_V3_PRIV_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP && LWIP_SNMP_V3 - -#include "snmp_pbuf_stream.h" - -/* According to RFC 3411 */ -#define SNMP_V3_MAX_ENGINE_ID_LENGTH 32 -#define SNMP_V3_MAX_USER_LENGTH 32 - -#define SNMP_V3_MAX_AUTH_PARAM_LENGTH 12 -#define SNMP_V3_MAX_PRIV_PARAM_LENGTH 8 - -#define SNMP_V3_AUTH_FLAG 0x01 -#define SNMP_V3_PRIV_FLAG 0x02 - -#define SNMP_V3_MD5_LEN 16 -#define SNMP_V3_SHA_LEN 20 - -u32_t snmpv3_get_engine_boots_internal(void); -u32_t snmpv3_get_engine_time_internal(void); -err_t snmpv3_auth(struct snmp_pbuf_stream* stream, u16_t length, const u8_t* key, u8_t algo, u8_t* hmac_out); -err_t snmpv3_crypt(struct snmp_pbuf_stream* stream, u16_t length, const u8_t* key, - const u8_t* priv_param, const u32_t engine_boots, const u32_t engine_time, u8_t algo, u8_t mode); -err_t snmpv3_build_priv_param(u8_t* priv_param); - -#endif - -#endif /* LWIP_HDR_APPS_SNMP_V3_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/sntp/sntp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/sntp/sntp.c deleted file mode 100644 index 71b2abedb8fb69fd353e3f928d4cc3c50d42b8be..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/sntp/sntp.c +++ /dev/null @@ -1,727 +0,0 @@ -/** - * @file - * SNTP client module - */ - -/* - * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Frédéric Bernon, Simon Goldschmidt - */ - - -/** - * @defgroup sntp SNTP - * @ingroup apps - * - * This is simple "SNTP" client for the lwIP raw API. - * It is a minimal implementation of SNTPv4 as specified in RFC 4330. - * - * For a list of some public NTP servers, see this link : - * http://support.ntp.org/bin/view/Servers/NTPPoolServers - * - * @todo: - * - set/change servers at runtime - * - complete SNTP_CHECK_RESPONSE checks 3 and 4 - */ - -#include "lwip/apps/sntp.h" - -#include "lwip/opt.h" -#include "lwip/timeouts.h" -#include "lwip/udp.h" -#include "lwip/dns.h" -#include "lwip/ip_addr.h" -#include "lwip/pbuf.h" -#include "lwip/dhcp.h" - -#include -#include - -#if LWIP_UDP - -/* Handle support for more than one server via SNTP_MAX_SERVERS */ -#if SNTP_MAX_SERVERS > 1 -#define SNTP_SUPPORT_MULTIPLE_SERVERS 1 -#else /* NTP_MAX_SERVERS > 1 */ -#define SNTP_SUPPORT_MULTIPLE_SERVERS 0 -#endif /* NTP_MAX_SERVERS > 1 */ - -#if (SNTP_UPDATE_DELAY < 15000) && !defined(SNTP_SUPPRESS_DELAY_CHECK) -#error "SNTPv4 RFC 4330 enforces a minimum update time of 15 seconds (define SNTP_SUPPRESS_DELAY_CHECK to disable this error)!" -#endif - -/* Configure behaviour depending on microsecond or second precision */ -#ifdef SNTP_SET_SYSTEM_TIME_US -#define SNTP_CALC_TIME_US 1 -#define SNTP_RECEIVE_TIME_SIZE 2 -#else -#define SNTP_SET_SYSTEM_TIME_US(sec, us) -#define SNTP_CALC_TIME_US 0 -#define SNTP_RECEIVE_TIME_SIZE 1 -#endif - - -/* the various debug levels for this file */ -#define SNTP_DEBUG_TRACE (SNTP_DEBUG | LWIP_DBG_TRACE) -#define SNTP_DEBUG_STATE (SNTP_DEBUG | LWIP_DBG_STATE) -#define SNTP_DEBUG_WARN (SNTP_DEBUG | LWIP_DBG_LEVEL_WARNING) -#define SNTP_DEBUG_WARN_STATE (SNTP_DEBUG | LWIP_DBG_LEVEL_WARNING | LWIP_DBG_STATE) -#define SNTP_DEBUG_SERIOUS (SNTP_DEBUG | LWIP_DBG_LEVEL_SERIOUS) - -#define SNTP_ERR_KOD 1 - -/* SNTP protocol defines */ -#define SNTP_MSG_LEN 48 - -#define SNTP_OFFSET_LI_VN_MODE 0 -#define SNTP_LI_MASK 0xC0 -#define SNTP_LI_NO_WARNING 0x00 -#define SNTP_LI_LAST_MINUTE_61_SEC 0x01 -#define SNTP_LI_LAST_MINUTE_59_SEC 0x02 -#define SNTP_LI_ALARM_CONDITION 0x03 /* (clock not synchronized) */ - -#define SNTP_VERSION_MASK 0x38 -#define SNTP_VERSION (4/* NTP Version 4*/<<3) - -#define SNTP_MODE_MASK 0x07 -#define SNTP_MODE_CLIENT 0x03 -#define SNTP_MODE_SERVER 0x04 -#define SNTP_MODE_BROADCAST 0x05 - -#define SNTP_OFFSET_STRATUM 1 -#define SNTP_STRATUM_KOD 0x00 - -#define SNTP_OFFSET_ORIGINATE_TIME 24 -#define SNTP_OFFSET_RECEIVE_TIME 32 -#define SNTP_OFFSET_TRANSMIT_TIME 40 - -/* number of seconds between 1900 and 1970 (MSB=1)*/ -#define DIFF_SEC_1900_1970 (2208988800UL) -/* number of seconds between 1970 and Feb 7, 2036 (6:28:16 UTC) (MSB=0) */ -#define DIFF_SEC_1970_2036 (2085978496UL) - -/** - * SNTP packet format (without optional fields) - * Timestamps are coded as 64 bits: - * - 32 bits seconds since Jan 01, 1970, 00:00 - * - 32 bits seconds fraction (0-padded) - * For future use, if the MSB in the seconds part is set, seconds are based - * on Feb 07, 2036, 06:28:16. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct sntp_msg { - PACK_STRUCT_FLD_8(u8_t li_vn_mode); - PACK_STRUCT_FLD_8(u8_t stratum); - PACK_STRUCT_FLD_8(u8_t poll); - PACK_STRUCT_FLD_8(u8_t precision); - PACK_STRUCT_FIELD(u32_t root_delay); - PACK_STRUCT_FIELD(u32_t root_dispersion); - PACK_STRUCT_FIELD(u32_t reference_identifier); - PACK_STRUCT_FIELD(u32_t reference_timestamp[2]); - PACK_STRUCT_FIELD(u32_t originate_timestamp[2]); - PACK_STRUCT_FIELD(u32_t receive_timestamp[2]); - PACK_STRUCT_FIELD(u32_t transmit_timestamp[2]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* function prototypes */ -static void sntp_request(void *arg); - -/** The operating mode */ -static u8_t sntp_opmode; - -/** The UDP pcb used by the SNTP client */ -static struct udp_pcb* sntp_pcb; -/** Names/Addresses of servers */ -struct sntp_server { -#if SNTP_SERVER_DNS - char* name; -#endif /* SNTP_SERVER_DNS */ - ip_addr_t addr; -}; -static struct sntp_server sntp_servers[SNTP_MAX_SERVERS]; - -#if SNTP_GET_SERVERS_FROM_DHCP -static u8_t sntp_set_servers_from_dhcp; -#endif /* SNTP_GET_SERVERS_FROM_DHCP */ -#if SNTP_SUPPORT_MULTIPLE_SERVERS -/** The currently used server (initialized to 0) */ -static u8_t sntp_current_server; -#else /* SNTP_SUPPORT_MULTIPLE_SERVERS */ -#define sntp_current_server 0 -#endif /* SNTP_SUPPORT_MULTIPLE_SERVERS */ - -#if SNTP_RETRY_TIMEOUT_EXP -#define SNTP_RESET_RETRY_TIMEOUT() sntp_retry_timeout = SNTP_RETRY_TIMEOUT -/** Retry time, initialized with SNTP_RETRY_TIMEOUT and doubled with each retry. */ -static u32_t sntp_retry_timeout; -#else /* SNTP_RETRY_TIMEOUT_EXP */ -#define SNTP_RESET_RETRY_TIMEOUT() -#define sntp_retry_timeout SNTP_RETRY_TIMEOUT -#endif /* SNTP_RETRY_TIMEOUT_EXP */ - -#if SNTP_CHECK_RESPONSE >= 1 -/** Saves the last server address to compare with response */ -static ip_addr_t sntp_last_server_address; -#endif /* SNTP_CHECK_RESPONSE >= 1 */ - -#if SNTP_CHECK_RESPONSE >= 2 -/** Saves the last timestamp sent (which is sent back by the server) - * to compare against in response */ -static u32_t sntp_last_timestamp_sent[2]; -#endif /* SNTP_CHECK_RESPONSE >= 2 */ - -/** - * SNTP processing of received timestamp - */ -static void -sntp_process(u32_t *receive_timestamp) -{ - /* convert SNTP time (1900-based) to unix GMT time (1970-based) - * if MSB is 0, SNTP time is 2036-based! - */ - u32_t rx_secs = lwip_ntohl(receive_timestamp[0]); - int is_1900_based = ((rx_secs & 0x80000000) != 0); - u32_t t = is_1900_based ? (rx_secs - DIFF_SEC_1900_1970) : (rx_secs + DIFF_SEC_1970_2036); - time_t tim = t; - -#if SNTP_CALC_TIME_US - u32_t us = lwip_ntohl(receive_timestamp[1]) / 4295; - SNTP_SET_SYSTEM_TIME_US(t, us); - /* display local time from GMT time */ - LWIP_DEBUGF(SNTP_DEBUG_TRACE, ("sntp_process: %s, %"U32_F" us", ctime(&tim), us)); - -#else /* SNTP_CALC_TIME_US */ - - /* change system time and/or the update the RTC clock */ - SNTP_SET_SYSTEM_TIME(t); - /* display local time from GMT time */ - LWIP_DEBUGF(SNTP_DEBUG_TRACE, ("sntp_process: %s", ctime(&tim))); -#endif /* SNTP_CALC_TIME_US */ - LWIP_UNUSED_ARG(tim); -} - -/** - * Initialize request struct to be sent to server. - */ -static void -sntp_initialize_request(struct sntp_msg *req) -{ - memset(req, 0, SNTP_MSG_LEN); - req->li_vn_mode = SNTP_LI_NO_WARNING | SNTP_VERSION | SNTP_MODE_CLIENT; - -#if SNTP_CHECK_RESPONSE >= 2 - { - u32_t sntp_time_sec, sntp_time_us; - /* fill in transmit timestamp and save it in 'sntp_last_timestamp_sent' */ - SNTP_GET_SYSTEM_TIME(sntp_time_sec, sntp_time_us); - sntp_last_timestamp_sent[0] = lwip_htonl(sntp_time_sec + DIFF_SEC_1900_1970); - req->transmit_timestamp[0] = sntp_last_timestamp_sent[0]; - /* we send/save us instead of fraction to be faster... */ - sntp_last_timestamp_sent[1] = lwip_htonl(sntp_time_us); - req->transmit_timestamp[1] = sntp_last_timestamp_sent[1]; - } -#endif /* SNTP_CHECK_RESPONSE >= 2 */ -} - -/** - * Retry: send a new request (and increase retry timeout). - * - * @param arg is unused (only necessary to conform to sys_timeout) - */ -static void -sntp_retry(void* arg) -{ - LWIP_UNUSED_ARG(arg); - - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_retry: Next request will be sent in %"U32_F" ms\n", - sntp_retry_timeout)); - - /* set up a timer to send a retry and increase the retry delay */ - sys_timeout(sntp_retry_timeout, sntp_request, NULL); - -#if SNTP_RETRY_TIMEOUT_EXP - { - u32_t new_retry_timeout; - /* increase the timeout for next retry */ - new_retry_timeout = sntp_retry_timeout << 1; - /* limit to maximum timeout and prevent overflow */ - if ((new_retry_timeout <= SNTP_RETRY_TIMEOUT_MAX) && - (new_retry_timeout > sntp_retry_timeout)) { - sntp_retry_timeout = new_retry_timeout; - } - } -#endif /* SNTP_RETRY_TIMEOUT_EXP */ -} - -#if SNTP_SUPPORT_MULTIPLE_SERVERS -/** - * If Kiss-of-Death is received (or another packet parsing error), - * try the next server or retry the current server and increase the retry - * timeout if only one server is available. - * (implicitly, SNTP_MAX_SERVERS > 1) - * - * @param arg is unused (only necessary to conform to sys_timeout) - */ -static void -sntp_try_next_server(void* arg) -{ - u8_t old_server, i; - LWIP_UNUSED_ARG(arg); - - old_server = sntp_current_server; - for (i = 0; i < SNTP_MAX_SERVERS - 1; i++) { - sntp_current_server++; - if (sntp_current_server >= SNTP_MAX_SERVERS) { - sntp_current_server = 0; - } - if (!ip_addr_isany(&sntp_servers[sntp_current_server].addr) -#if SNTP_SERVER_DNS - || (sntp_servers[sntp_current_server].name != NULL) -#endif - ) { - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_try_next_server: Sending request to server %"U16_F"\n", - (u16_t)sntp_current_server)); - /* new server: reset retry timeout */ - SNTP_RESET_RETRY_TIMEOUT(); - /* instantly send a request to the next server */ - sntp_request(NULL); - return; - } - } - /* no other valid server found */ - sntp_current_server = old_server; - sntp_retry(NULL); -} -#else /* SNTP_SUPPORT_MULTIPLE_SERVERS */ -/* Always retry on error if only one server is supported */ -#define sntp_try_next_server sntp_retry -#endif /* SNTP_SUPPORT_MULTIPLE_SERVERS */ - -/** UDP recv callback for the sntp pcb */ -static void -sntp_recv(void *arg, struct udp_pcb* pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - u8_t mode; - u8_t stratum; - u32_t receive_timestamp[SNTP_RECEIVE_TIME_SIZE]; - err_t err; - - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(pcb); - - /* packet received: stop retry timeout */ - sys_untimeout(sntp_try_next_server, NULL); - sys_untimeout(sntp_request, NULL); - - err = ERR_ARG; -#if SNTP_CHECK_RESPONSE >= 1 - /* check server address and port */ - if (((sntp_opmode != SNTP_OPMODE_POLL) || ip_addr_cmp(addr, &sntp_last_server_address)) && - (port == SNTP_PORT)) -#else /* SNTP_CHECK_RESPONSE >= 1 */ - LWIP_UNUSED_ARG(addr); - LWIP_UNUSED_ARG(port); -#endif /* SNTP_CHECK_RESPONSE >= 1 */ - { - /* process the response */ - if (p->tot_len == SNTP_MSG_LEN) { - pbuf_copy_partial(p, &mode, 1, SNTP_OFFSET_LI_VN_MODE); - mode &= SNTP_MODE_MASK; - /* if this is a SNTP response... */ - if (((sntp_opmode == SNTP_OPMODE_POLL) && (mode == SNTP_MODE_SERVER)) || - ((sntp_opmode == SNTP_OPMODE_LISTENONLY) && (mode == SNTP_MODE_BROADCAST))) { - pbuf_copy_partial(p, &stratum, 1, SNTP_OFFSET_STRATUM); - if (stratum == SNTP_STRATUM_KOD) { - /* Kiss-of-death packet. Use another server or increase UPDATE_DELAY. */ - err = SNTP_ERR_KOD; - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_recv: Received Kiss-of-Death\n")); - } else { -#if SNTP_CHECK_RESPONSE >= 2 - /* check originate_timetamp against sntp_last_timestamp_sent */ - u32_t originate_timestamp[2]; - pbuf_copy_partial(p, &originate_timestamp, 8, SNTP_OFFSET_ORIGINATE_TIME); - if ((originate_timestamp[0] != sntp_last_timestamp_sent[0]) || - (originate_timestamp[1] != sntp_last_timestamp_sent[1])) - { - LWIP_DEBUGF(SNTP_DEBUG_WARN, ("sntp_recv: Invalid originate timestamp in response\n")); - } else -#endif /* SNTP_CHECK_RESPONSE >= 2 */ - /* @todo: add code for SNTP_CHECK_RESPONSE >= 3 and >= 4 here */ - { - /* correct answer */ - err = ERR_OK; - pbuf_copy_partial(p, &receive_timestamp, SNTP_RECEIVE_TIME_SIZE * 4, SNTP_OFFSET_TRANSMIT_TIME); - } - } - } else { - LWIP_DEBUGF(SNTP_DEBUG_WARN, ("sntp_recv: Invalid mode in response: %"U16_F"\n", (u16_t)mode)); - /* wait for correct response */ - err = ERR_TIMEOUT; - } - } else { - LWIP_DEBUGF(SNTP_DEBUG_WARN, ("sntp_recv: Invalid packet length: %"U16_F"\n", p->tot_len)); - } - } -#if SNTP_CHECK_RESPONSE >= 1 - else { - /* packet from wrong remote address or port, wait for correct response */ - err = ERR_TIMEOUT; - } -#endif /* SNTP_CHECK_RESPONSE >= 1 */ - pbuf_free(p); - if (err == ERR_OK) { - sntp_process(receive_timestamp); - - /* Set up timeout for next request (only if poll response was received)*/ - if (sntp_opmode == SNTP_OPMODE_POLL) { - /* Correct response, reset retry timeout */ - SNTP_RESET_RETRY_TIMEOUT(); - - sys_timeout((u32_t)SNTP_UPDATE_DELAY, sntp_request, NULL); - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_recv: Scheduled next time request: %"U32_F" ms\n", - (u32_t)SNTP_UPDATE_DELAY)); - } - } else if (err != ERR_TIMEOUT) { - /* Errors are only processed in case of an explicit poll response */ - if (sntp_opmode == SNTP_OPMODE_POLL) { - if (err == SNTP_ERR_KOD) { - /* Kiss-of-death packet. Use another server or increase UPDATE_DELAY. */ - sntp_try_next_server(NULL); - } else { - /* another error, try the same server again */ - sntp_retry(NULL); - } - } - } -} - -/** Actually send an sntp request to a server. - * - * @param server_addr resolved IP address of the SNTP server - */ -static void -sntp_send_request(const ip_addr_t *server_addr) -{ - struct pbuf* p; - p = pbuf_alloc(PBUF_TRANSPORT, SNTP_MSG_LEN, PBUF_RAM); - if (p != NULL) { - struct sntp_msg *sntpmsg = (struct sntp_msg *)p->payload; - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_send_request: Sending request to server\n")); - /* initialize request message */ - sntp_initialize_request(sntpmsg); - /* send request */ - udp_sendto(sntp_pcb, p, server_addr, SNTP_PORT); - /* free the pbuf after sending it */ - pbuf_free(p); - /* set up receive timeout: try next server or retry on timeout */ - sys_timeout((u32_t)SNTP_RECV_TIMEOUT, sntp_try_next_server, NULL); -#if SNTP_CHECK_RESPONSE >= 1 - /* save server address to verify it in sntp_recv */ - ip_addr_set(&sntp_last_server_address, server_addr); -#endif /* SNTP_CHECK_RESPONSE >= 1 */ - } else { - LWIP_DEBUGF(SNTP_DEBUG_SERIOUS, ("sntp_send_request: Out of memory, trying again in %"U32_F" ms\n", - (u32_t)SNTP_RETRY_TIMEOUT)); - /* out of memory: set up a timer to send a retry */ - sys_timeout((u32_t)SNTP_RETRY_TIMEOUT, sntp_request, NULL); - } -} - -#if SNTP_SERVER_DNS -/** - * DNS found callback when using DNS names as server address. - */ -static void -sntp_dns_found(const char* hostname, const ip_addr_t *ipaddr, void *arg) -{ - LWIP_UNUSED_ARG(hostname); - LWIP_UNUSED_ARG(arg); - - if (ipaddr != NULL) { - /* Address resolved, send request */ - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_dns_found: Server address resolved, sending request\n")); - sntp_send_request(ipaddr); - } else { - /* DNS resolving failed -> try another server */ - LWIP_DEBUGF(SNTP_DEBUG_WARN_STATE, ("sntp_dns_found: Failed to resolve server address resolved, trying next server\n")); - sntp_try_next_server(NULL); - } -} -#endif /* SNTP_SERVER_DNS */ - -/** - * Send out an sntp request. - * - * @param arg is unused (only necessary to conform to sys_timeout) - */ -static void -sntp_request(void *arg) -{ - ip_addr_t sntp_server_address; - err_t err; - - LWIP_UNUSED_ARG(arg); - - /* initialize SNTP server address */ -#if SNTP_SERVER_DNS - if (sntp_servers[sntp_current_server].name) { - /* always resolve the name and rely on dns-internal caching & timeout */ - ip_addr_set_zero(&sntp_servers[sntp_current_server].addr); - err = dns_gethostbyname(sntp_servers[sntp_current_server].name, &sntp_server_address, - sntp_dns_found, NULL); - if (err == ERR_INPROGRESS) { - /* DNS request sent, wait for sntp_dns_found being called */ - LWIP_DEBUGF(SNTP_DEBUG_STATE, ("sntp_request: Waiting for server address to be resolved.\n")); - return; - } else if (err == ERR_OK) { - sntp_servers[sntp_current_server].addr = sntp_server_address; - } - } else -#endif /* SNTP_SERVER_DNS */ - { - sntp_server_address = sntp_servers[sntp_current_server].addr; - err = (ip_addr_isany_val(sntp_server_address)) ? ERR_ARG : ERR_OK; - } - - if (err == ERR_OK) { - LWIP_DEBUGF(SNTP_DEBUG_TRACE, ("sntp_request: current server address is %s\n", - ipaddr_ntoa(&sntp_server_address))); - sntp_send_request(&sntp_server_address); - } else { - /* address conversion failed, try another server */ - LWIP_DEBUGF(SNTP_DEBUG_WARN_STATE, ("sntp_request: Invalid server address, trying next server.\n")); - sys_timeout((u32_t)SNTP_RETRY_TIMEOUT, sntp_try_next_server, NULL); - } -} - -/** - * @ingroup sntp - * Initialize this module. - * Send out request instantly or after SNTP_STARTUP_DELAY(_FUNC). - */ -void -sntp_init(void) -{ -#ifdef SNTP_SERVER_ADDRESS -#if SNTP_SERVER_DNS - sntp_setservername(0, SNTP_SERVER_ADDRESS); -#else -#error SNTP_SERVER_ADDRESS string not supported SNTP_SERVER_DNS==0 -#endif -#endif /* SNTP_SERVER_ADDRESS */ - - if (sntp_pcb == NULL) { - sntp_pcb = udp_new_ip_type(IPADDR_TYPE_ANY); - LWIP_ASSERT("Failed to allocate udp pcb for sntp client", sntp_pcb != NULL); - if (sntp_pcb != NULL) { - udp_recv(sntp_pcb, sntp_recv, NULL); - - if (sntp_opmode == SNTP_OPMODE_POLL) { - SNTP_RESET_RETRY_TIMEOUT(); -#if SNTP_STARTUP_DELAY - sys_timeout((u32_t)SNTP_STARTUP_DELAY_FUNC, sntp_request, NULL); -#else - sntp_request(NULL); -#endif - } else if (sntp_opmode == SNTP_OPMODE_LISTENONLY) { - ip_set_option(sntp_pcb, SOF_BROADCAST); - udp_bind(sntp_pcb, IP_ANY_TYPE, SNTP_PORT); - } - } - } -} - -/** - * @ingroup sntp - * Stop this module. - */ -void -sntp_stop(void) -{ - if (sntp_pcb != NULL) { - sys_untimeout(sntp_request, NULL); - sys_untimeout(sntp_try_next_server, NULL); - udp_remove(sntp_pcb); - sntp_pcb = NULL; - } -} - -/** - * @ingroup sntp - * Get enabled state. - */ -u8_t sntp_enabled(void) -{ - return (sntp_pcb != NULL)? 1 : 0; -} - -/** - * @ingroup sntp - * Sets the operating mode. - * @param operating_mode one of the available operating modes - */ -void -sntp_setoperatingmode(u8_t operating_mode) -{ - LWIP_ASSERT("Invalid operating mode", operating_mode <= SNTP_OPMODE_LISTENONLY); - LWIP_ASSERT("Operating mode must not be set while SNTP client is running", sntp_pcb == NULL); - sntp_opmode = operating_mode; -} - -/** - * @ingroup sntp - * Gets the operating mode. - */ -u8_t -sntp_getoperatingmode(void) -{ - return sntp_opmode; -} - -#if SNTP_GET_SERVERS_FROM_DHCP -/** - * Config SNTP server handling by IP address, name, or DHCP; clear table - * @param set_servers_from_dhcp enable or disable getting server addresses from dhcp - */ -void -sntp_servermode_dhcp(int set_servers_from_dhcp) -{ - u8_t new_mode = set_servers_from_dhcp ? 1 : 0; - if (sntp_set_servers_from_dhcp != new_mode) { - sntp_set_servers_from_dhcp = new_mode; - } -} -#endif /* SNTP_GET_SERVERS_FROM_DHCP */ - -/** - * @ingroup sntp - * Initialize one of the NTP servers by IP address - * - * @param idx the index of the NTP server to set must be < SNTP_MAX_SERVERS - * @param server IP address of the NTP server to set - */ -void -sntp_setserver(u8_t idx, const ip_addr_t *server) -{ - if (idx < SNTP_MAX_SERVERS) { - if (server != NULL) { - sntp_servers[idx].addr = (*server); - } else { - ip_addr_set_zero(&sntp_servers[idx].addr); - } -#if SNTP_SERVER_DNS - sntp_servers[idx].name = NULL; -#endif - } -} - -#if LWIP_DHCP && SNTP_GET_SERVERS_FROM_DHCP -/** - * Initialize one of the NTP servers by IP address, required by DHCP - * - * @param numdns the index of the NTP server to set must be < SNTP_MAX_SERVERS - * @param dnsserver IP address of the NTP server to set - */ -void -dhcp_set_ntp_servers(u8_t num, const ip4_addr_t *server) -{ - LWIP_DEBUGF(SNTP_DEBUG_TRACE, ("sntp: %s %u.%u.%u.%u as NTP server #%u via DHCP\n", - (sntp_set_servers_from_dhcp ? "Got" : "Rejected"), - ip4_addr1(server), ip4_addr2(server), ip4_addr3(server), ip4_addr4(server), num)); - if (sntp_set_servers_from_dhcp && num) { - u8_t i; - for (i = 0; (i < num) && (i < SNTP_MAX_SERVERS); i++) { - ip_addr_t addr; - ip_addr_copy_from_ip4(addr, server[i]); - sntp_setserver(i, &addr); - } - for (i = num; i < SNTP_MAX_SERVERS; i++) { - sntp_setserver(i, NULL); - } - } -} -#endif /* LWIP_DHCP && SNTP_GET_SERVERS_FROM_DHCP */ - -/** - * @ingroup sntp - * Obtain one of the currently configured by IP address (or DHCP) NTP servers - * - * @param idx the index of the NTP server - * @return IP address of the indexed NTP server or "ip_addr_any" if the NTP - * server has not been configured by address (or at all). - */ -const ip_addr_t* -sntp_getserver(u8_t idx) -{ - if (idx < SNTP_MAX_SERVERS) { - return &sntp_servers[idx].addr; - } - return IP_ADDR_ANY; -} - -#if SNTP_SERVER_DNS -/** - * Initialize one of the NTP servers by name - * - * @param numdns the index of the NTP server to set must be < SNTP_MAX_SERVERS - * @param dnsserver DNS name of the NTP server to set, to be resolved at contact time - */ -void -sntp_setservername(u8_t idx, char *server) -{ - if (idx < SNTP_MAX_SERVERS) { - sntp_servers[idx].name = server; - } -} - -/** - * Obtain one of the currently configured by name NTP servers. - * - * @param numdns the index of the NTP server - * @return IP address of the indexed NTP server or NULL if the NTP - * server has not been configured by name (or at all) - */ -char * -sntp_getservername(u8_t idx) -{ - if (idx < SNTP_MAX_SERVERS) { - return sntp_servers[idx].name; - } - return NULL; -} -#endif /* SNTP_SERVER_DNS */ - -#endif /* LWIP_UDP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/tftp/tftp_server.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/tftp/tftp_server.c deleted file mode 100644 index 243b0924bd18d0a8faba0b2a41f322e5b2a714cd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/apps/tftp/tftp_server.c +++ /dev/null @@ -1,417 +0,0 @@ -/****************************************************************//** - * - * @file tftp_server.c - * - * @author Logan Gunthorpe - * Dirk Ziegelmeier - * - * @brief Trivial File Transfer Protocol (RFC 1350) - * - * Copyright (c) Deltatee Enterprises Ltd. 2013 - * All rights reserved. - * - ********************************************************************/ - -/* - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Logan Gunthorpe - * Dirk Ziegelmeier - * - */ - -/** - * @defgroup tftp TFTP server - * @ingroup apps - * - * This is simple TFTP server for the lwIP raw API. - */ - -#include "lwip/apps/tftp_server.h" - -#if LWIP_UDP - -#include "lwip/udp.h" -#include "lwip/timeouts.h" -#include "lwip/debug.h" - -#define TFTP_MAX_PAYLOAD_SIZE 512 -#define TFTP_HEADER_LENGTH 4 - -#define TFTP_RRQ 1 -#define TFTP_WRQ 2 -#define TFTP_DATA 3 -#define TFTP_ACK 4 -#define TFTP_ERROR 5 - -enum tftp_error { - TFTP_ERROR_FILE_NOT_FOUND = 1, - TFTP_ERROR_ACCESS_VIOLATION = 2, - TFTP_ERROR_DISK_FULL = 3, - TFTP_ERROR_ILLEGAL_OPERATION = 4, - TFTP_ERROR_UNKNOWN_TRFR_ID = 5, - TFTP_ERROR_FILE_EXISTS = 6, - TFTP_ERROR_NO_SUCH_USER = 7 -}; - -#include - -struct tftp_state { - const struct tftp_context *ctx; - void *handle; - struct pbuf *last_data; - struct udp_pcb *upcb; - ip_addr_t addr; - u16_t port; - int timer; - int last_pkt; - u16_t blknum; - u8_t retries; - u8_t mode_write; -}; - -static struct tftp_state tftp_state; - -static void tftp_tmr(void* arg); - -static void -close_handle(void) -{ - tftp_state.port = 0; - ip_addr_set_any(0, &tftp_state.addr); - - if(tftp_state.last_data != NULL) { - pbuf_free(tftp_state.last_data); - tftp_state.last_data = NULL; - } - - sys_untimeout(tftp_tmr, NULL); - - if (tftp_state.handle) { - tftp_state.ctx->close(tftp_state.handle); - tftp_state.handle = NULL; - LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: closing\n")); - } -} - -static void -send_error(const ip_addr_t *addr, u16_t port, enum tftp_error code, const char *str) -{ - int str_length = strlen(str); - struct pbuf* p; - u16_t* payload; - - p = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(TFTP_HEADER_LENGTH + str_length + 1), PBUF_RAM); - if(p == NULL) { - return; - } - - payload = (u16_t*) p->payload; - payload[0] = PP_HTONS(TFTP_ERROR); - payload[1] = lwip_htons(code); - MEMCPY(&payload[2], str, str_length + 1); - - udp_sendto(tftp_state.upcb, p, addr, port); - pbuf_free(p); -} - -static void -send_ack(u16_t blknum) -{ - struct pbuf* p; - u16_t* payload; - - p = pbuf_alloc(PBUF_TRANSPORT, TFTP_HEADER_LENGTH, PBUF_RAM); - if(p == NULL) { - return; - } - payload = (u16_t*) p->payload; - - payload[0] = PP_HTONS(TFTP_ACK); - payload[1] = lwip_htons(blknum); - udp_sendto(tftp_state.upcb, p, &tftp_state.addr, tftp_state.port); - pbuf_free(p); -} - -static void -resend_data(void) -{ - struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, tftp_state.last_data->len, PBUF_RAM); - if(p == NULL) { - return; - } - - if(pbuf_copy(p, tftp_state.last_data) != ERR_OK) { - pbuf_free(p); - return; - } - - udp_sendto(tftp_state.upcb, p, &tftp_state.addr, tftp_state.port); - pbuf_free(p); -} - -static void -send_data(void) -{ - u16_t *payload; - int ret; - - if(tftp_state.last_data != NULL) { - pbuf_free(tftp_state.last_data); - } - - tftp_state.last_data = pbuf_alloc(PBUF_TRANSPORT, TFTP_HEADER_LENGTH + TFTP_MAX_PAYLOAD_SIZE, PBUF_RAM); - if(tftp_state.last_data == NULL) { - return; - } - - payload = (u16_t *) tftp_state.last_data->payload; - payload[0] = PP_HTONS(TFTP_DATA); - payload[1] = lwip_htons(tftp_state.blknum); - - ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE); - if (ret < 0) { - send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occured while reading the file."); - close_handle(); - return; - } - - pbuf_realloc(tftp_state.last_data, (u16_t)(TFTP_HEADER_LENGTH + ret)); - resend_data(); -} - -static void -recv(void *arg, struct udp_pcb *upcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - u16_t *sbuf = (u16_t *) p->payload; - int opcode; - - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(upcb); - - if (((tftp_state.port != 0) && (port != tftp_state.port)) || - (!ip_addr_isany_val(tftp_state.addr) && !ip_addr_cmp(&tftp_state.addr, addr))) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Only one connection at a time is supported"); - pbuf_free(p); - return; - } - - opcode = sbuf[0]; - - tftp_state.last_pkt = tftp_state.timer; - tftp_state.retries = 0; - - switch (opcode) { - case PP_HTONS(TFTP_RRQ): /* fall through */ - case PP_HTONS(TFTP_WRQ): - { - const char tftp_null = 0; - char filename[TFTP_MAX_FILENAME_LEN]; - char mode[TFTP_MAX_MODE_LEN]; - u16_t filename_end_offset; - u16_t mode_end_offset; - - if(tftp_state.handle != NULL) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Only one connection at a time is supported"); - break; - } - - sys_timeout(TFTP_TIMER_MSECS, tftp_tmr, NULL); - - /* find \0 in pbuf -> end of filename string */ - filename_end_offset = pbuf_memfind(p, &tftp_null, sizeof(tftp_null), 2); - if((u16_t)(filename_end_offset-2) > sizeof(filename)) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Filename too long/not NULL terminated"); - break; - } - pbuf_copy_partial(p, filename, filename_end_offset-2, 2); - - /* find \0 in pbuf -> end of mode string */ - mode_end_offset = pbuf_memfind(p, &tftp_null, sizeof(tftp_null), filename_end_offset+1); - if((u16_t)(mode_end_offset-filename_end_offset) > sizeof(mode)) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Mode too long/not NULL terminated"); - break; - } - pbuf_copy_partial(p, mode, mode_end_offset-filename_end_offset, filename_end_offset+1); - - tftp_state.handle = tftp_state.ctx->open(filename, mode, opcode == PP_HTONS(TFTP_WRQ)); - tftp_state.blknum = 1; - - if (!tftp_state.handle) { - send_error(addr, port, TFTP_ERROR_FILE_NOT_FOUND, "Unable to open requested file."); - break; - } - - LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: %s request from ", (opcode == PP_HTONS(TFTP_WRQ)) ? "write" : "read")); - ip_addr_debug_print(TFTP_DEBUG | LWIP_DBG_STATE, addr); - LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, (" for '%s' mode '%s'\n", filename, mode)); - - ip_addr_copy(tftp_state.addr, *addr); - tftp_state.port = port; - - if (opcode == PP_HTONS(TFTP_WRQ)) { - tftp_state.mode_write = 1; - send_ack(0); - } else { - tftp_state.mode_write = 0; - send_data(); - } - - break; - } - - case PP_HTONS(TFTP_DATA): - { - int ret; - u16_t blknum; - - if (tftp_state.handle == NULL) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "No connection"); - break; - } - - if (tftp_state.mode_write != 1) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Not a write connection"); - break; - } - - blknum = lwip_ntohs(sbuf[1]); - pbuf_header(p, -TFTP_HEADER_LENGTH); - - ret = tftp_state.ctx->write(tftp_state.handle, p); - if (ret < 0) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "error writing file"); - close_handle(); - } else { - send_ack(blknum); - } - - if (p->tot_len < TFTP_MAX_PAYLOAD_SIZE) { - close_handle(); - } - break; - } - - case PP_HTONS(TFTP_ACK): - { - u16_t blknum; - int lastpkt; - - if (tftp_state.handle == NULL) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "No connection"); - break; - } - - if (tftp_state.mode_write != 0) { - send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Not a read connection"); - break; - } - - blknum = lwip_ntohs(sbuf[1]); - if (blknum != tftp_state.blknum) { - send_error(addr, port, TFTP_ERROR_UNKNOWN_TRFR_ID, "Wrong block number"); - break; - } - - lastpkt = 0; - - if (tftp_state.last_data != NULL) { - lastpkt = tftp_state.last_data->tot_len != (TFTP_MAX_PAYLOAD_SIZE + TFTP_HEADER_LENGTH); - } - - if (!lastpkt) { - tftp_state.blknum++; - send_data(); - } else { - close_handle(); - } - - break; - } - - default: - send_error(addr, port, TFTP_ERROR_ILLEGAL_OPERATION, "Unknown operation"); - break; - } - - pbuf_free(p); -} - -static void -tftp_tmr(void* arg) -{ - LWIP_UNUSED_ARG(arg); - - tftp_state.timer++; - - if (tftp_state.handle == NULL) { - return; - } - - sys_timeout(TFTP_TIMER_MSECS, tftp_tmr, NULL); - - if ((tftp_state.timer - tftp_state.last_pkt) > (TFTP_TIMEOUT_MSECS / TFTP_TIMER_MSECS)) { - if ((tftp_state.last_data != NULL) && (tftp_state.retries < TFTP_MAX_RETRIES)) { - LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: timeout, retrying\n")); - resend_data(); - tftp_state.retries++; - } else { - LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: timeout\n")); - close_handle(); - } - } -} - -/** @ingroup tftp - * Initialize TFTP server. - * @param ctx TFTP callback struct - */ -err_t -tftp_init(const struct tftp_context *ctx) -{ - err_t ret; - - struct udp_pcb *pcb = udp_new_ip_type(IPADDR_TYPE_ANY); - if (pcb == NULL) { - return ERR_MEM; - } - - ret = udp_bind(pcb, IP_ANY_TYPE, TFTP_PORT); - if (ret != ERR_OK) { - udp_remove(pcb); - return ret; - } - - tftp_state.handle = NULL; - tftp_state.port = 0; - tftp_state.ctx = ctx; - tftp_state.timer = 0; - tftp_state.last_data = NULL; - tftp_state.upcb = pcb; - - udp_recv(pcb, recv, NULL); - - return ERR_OK; -} - -#endif /* LWIP_UDP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/def.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/def.c deleted file mode 100644 index 8125313f41ce358b63f8fb19584f9d8e2438fd53..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/def.c +++ /dev/null @@ -1,222 +0,0 @@ -/** - * @file - * Common functions used throughout the stack. - * - * These are reference implementations of the byte swapping functions. - * Again with the aim of being simple, correct and fully portable. - * Byte swapping is the second thing you would want to optimize. You will - * need to port it to your architecture and in your cc.h: - * - * \#define lwip_htons(x) your_htons - * \#define lwip_htonl(x) your_htonl - * - * Note lwip_ntohs() and lwip_ntohl() are merely references to the htonx counterparts. - * - * If you \#define them to htons() and htonl(), you should - * \#define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS to prevent lwIP from - * defining htonx/ntohx compatibility macros. - - * @defgroup sys_nonstandard Non-standard functions - * @ingroup sys_layer - * lwIP provides default implementations for non-standard functions. - * These can be mapped to OS functions to reduce code footprint if desired. - * All defines related to this section must not be placed in lwipopts.h, - * but in arch/cc.h! - * These options cannot be \#defined in lwipopts.h since they are not options - * of lwIP itself, but options of the lwIP port to your system. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ - -#include "lwip/opt.h" -#include "lwip/def.h" - -#include - -#if BYTE_ORDER == LITTLE_ENDIAN - -#if !defined(lwip_htons) -/** - * Convert an u16_t from host- to network byte order. - * - * @param n u16_t in host byte order - * @return n in network byte order - */ -u16_t -lwip_htons(u16_t n) -{ - return (u16_t)PP_HTONS(n); -} -#endif /* lwip_htons */ - -#if !defined(lwip_htonl) -/** - * Convert an u32_t from host- to network byte order. - * - * @param n u32_t in host byte order - * @return n in network byte order - */ -u32_t -lwip_htonl(u32_t n) -{ - return (u32_t)PP_HTONL(n); -} -#endif /* lwip_htonl */ - -#endif /* BYTE_ORDER == LITTLE_ENDIAN */ - -#ifndef lwip_strnstr -/** - * @ingroup sys_nonstandard - * lwIP default implementation for strnstr() non-standard function. - * This can be \#defined to strnstr() depending on your platform port. - */ -char* -lwip_strnstr(const char* buffer, const char* token, size_t n) -{ - const char* p; - size_t tokenlen = strlen(token); - if (tokenlen == 0) { - return LWIP_CONST_CAST(char *, buffer); - } - for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) { - if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) { - return LWIP_CONST_CAST(char *, p); - } - } - return NULL; -} -#endif - -#ifndef lwip_stricmp -/** - * @ingroup sys_nonstandard - * lwIP default implementation for stricmp() non-standard function. - * This can be \#defined to stricmp() depending on your platform port. - */ -int -lwip_stricmp(const char* str1, const char* str2) -{ - char c1, c2; - - do { - c1 = *str1++; - c2 = *str2++; - if (c1 != c2) { - char c1_upc = c1 | 0x20; - if ((c1_upc >= 'a') && (c1_upc <= 'z')) { - /* characters are not equal an one is in the alphabet range: - downcase both chars and check again */ - char c2_upc = c2 | 0x20; - if (c1_upc != c2_upc) { - /* still not equal */ - /* don't care for < or > */ - return 1; - } - } else { - /* characters are not equal but none is in the alphabet range */ - return 1; - } - } - } while (c1 != 0); - return 0; -} -#endif - -#ifndef lwip_strnicmp -/** - * @ingroup sys_nonstandard - * lwIP default implementation for strnicmp() non-standard function. - * This can be \#defined to strnicmp() depending on your platform port. - */ -int -lwip_strnicmp(const char* str1, const char* str2, size_t len) -{ - char c1, c2; - - do { - c1 = *str1++; - c2 = *str2++; - if (c1 != c2) { - char c1_upc = c1 | 0x20; - if ((c1_upc >= 'a') && (c1_upc <= 'z')) { - /* characters are not equal an one is in the alphabet range: - downcase both chars and check again */ - char c2_upc = c2 | 0x20; - if (c1_upc != c2_upc) { - /* still not equal */ - /* don't care for < or > */ - return 1; - } - } else { - /* characters are not equal but none is in the alphabet range */ - return 1; - } - } - } while (len-- && c1 != 0); - return 0; -} -#endif - -#ifndef lwip_itoa -/** - * @ingroup sys_nonstandard - * lwIP default implementation for itoa() non-standard function. - * This can be \#defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform port. - */ -void -lwip_itoa(char* result, size_t bufsize, int number) -{ - const int base = 10; - char* ptr = result, *ptr1 = result, tmp_char; - int tmp_value; - LWIP_UNUSED_ARG(bufsize); - - do { - tmp_value = number; - number /= base; - *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz"[35 + (tmp_value - number * base)]; - } while(number); - - /* Apply negative sign */ - if (tmp_value < 0) { - *ptr++ = '-'; - } - *ptr-- = '\0'; - while(ptr1 < ptr) { - tmp_char = *ptr; - *ptr--= *ptr1; - *ptr1++ = tmp_char; - } -} -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/dns.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/dns.c deleted file mode 100644 index 6837d76f0b88cfffc9d422b33fe6a96b38616346..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/dns.c +++ /dev/null @@ -1,1581 +0,0 @@ -/** - * @file - * DNS - host name to IP address resolver. - * - * @defgroup dns DNS - * @ingroup callbackstyle_api - * - * Implements a DNS host name to IP address resolver. - * - * The lwIP DNS resolver functions are used to lookup a host name and - * map it to a numerical IP address. It maintains a list of resolved - * hostnames that can be queried with the dns_lookup() function. - * New hostnames can be resolved using the dns_query() function. - * - * The lwIP version of the resolver also adds a non-blocking version of - * gethostbyname() that will work with a raw API application. This function - * checks for an IP address string first and converts it if it is valid. - * gethostbyname() then does a dns_lookup() to see if the name is - * already in the table. If so, the IP is returned. If not, a query is - * issued and the function returns with a ERR_INPROGRESS status. The app - * using the dns client must then go into a waiting state. - * - * Once a hostname has been resolved (or found to be non-existent), - * the resolver code calls a specified callback function (which - * must be implemented by the module that uses the resolver). - * - * Multicast DNS queries are supported for names ending on ".local". - * However, only "One-Shot Multicast DNS Queries" are supported (RFC 6762 - * chapter 5.1), this is not a fully compliant implementation of continuous - * mDNS querying! - * - * All functions must be called from TCPIP thread. - * - * @see @ref netconn_common for thread-safe access. - */ - -/* - * Port to lwIP from uIP - * by Jim Pettinato April 2007 - * - * security fixes and more by Simon Goldschmidt - * - * uIP version Copyright (c) 2002-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*----------------------------------------------------------------------------- - * RFC 1035 - Domain names - implementation and specification - * RFC 2181 - Clarifications to the DNS Specification - *----------------------------------------------------------------------------*/ - -/** @todo: define good default values (rfc compliance) */ -/** @todo: improve answer parsing, more checkings... */ -/** @todo: check RFC1035 - 7.3. Processing responses */ -/** @todo: one-shot mDNS: dual-stack fallback to another IP version */ - -/*----------------------------------------------------------------------------- - * Includes - *----------------------------------------------------------------------------*/ - -#include "lwip/opt.h" - -#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/udp.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/dns.h" -#include "lwip/prot/dns.h" - -#include - -/** Random generator function to create random TXIDs and source ports for queries */ -#ifndef DNS_RAND_TXID -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_XID) != 0) -#define DNS_RAND_TXID LWIP_RAND -#else -static u16_t dns_txid; -#define DNS_RAND_TXID() (++dns_txid) -#endif -#endif - -/** Limits the source port to be >= 1024 by default */ -#ifndef DNS_PORT_ALLOWED -#define DNS_PORT_ALLOWED(port) ((port) >= 1024) -#endif - -/** DNS maximum number of retries when asking for a name, before "timeout". */ -#ifndef DNS_MAX_RETRIES -#define DNS_MAX_RETRIES 4 -#endif - -/** DNS resource record max. TTL (one week as default) */ -#ifndef DNS_MAX_TTL -#define DNS_MAX_TTL 604800 -#elif DNS_MAX_TTL > 0x7FFFFFFF -#error DNS_MAX_TTL must be a positive 32-bit value -#endif - -#if DNS_TABLE_SIZE > 255 -#error DNS_TABLE_SIZE must fit into an u8_t -#endif -#if DNS_MAX_SERVERS > 255 -#error DNS_MAX_SERVERS must fit into an u8_t -#endif - -/* The number of parallel requests (i.e. calls to dns_gethostbyname - * that cannot be answered from the DNS table. - * This is set to the table size by default. - */ -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) -#ifndef DNS_MAX_REQUESTS -#define DNS_MAX_REQUESTS DNS_TABLE_SIZE -#else -#if DNS_MAX_REQUESTS > 255 -#error DNS_MAX_REQUESTS must fit into an u8_t -#endif -#endif -#else -/* In this configuration, both arrays have to have the same size and are used - * like one entry (used/free) */ -#define DNS_MAX_REQUESTS DNS_TABLE_SIZE -#endif - -/* The number of UDP source ports used in parallel */ -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) -#ifndef DNS_MAX_SOURCE_PORTS -#define DNS_MAX_SOURCE_PORTS DNS_MAX_REQUESTS -#else -#if DNS_MAX_SOURCE_PORTS > 255 -#error DNS_MAX_SOURCE_PORTS must fit into an u8_t -#endif -#endif -#else -#ifdef DNS_MAX_SOURCE_PORTS -#undef DNS_MAX_SOURCE_PORTS -#endif -#define DNS_MAX_SOURCE_PORTS 1 -#endif - -#if LWIP_IPV4 && LWIP_IPV6 -#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) (((t) == LWIP_DNS_ADDRTYPE_IPV6_IPV4) || ((t) == LWIP_DNS_ADDRTYPE_IPV6)) -#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) (IP_IS_V6_VAL(ip) ? LWIP_DNS_ADDRTYPE_IS_IPV6(t) : (!LWIP_DNS_ADDRTYPE_IS_IPV6(t))) -#define LWIP_DNS_ADDRTYPE_ARG(x) , x -#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) x -#define LWIP_DNS_SET_ADDRTYPE(x, y) do { x = y; } while(0) -#else -#if LWIP_IPV6 -#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 1 -#else -#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 0 -#endif -#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) 1 -#define LWIP_DNS_ADDRTYPE_ARG(x) -#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) 0 -#define LWIP_DNS_SET_ADDRTYPE(x, y) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#if LWIP_DNS_SUPPORT_MDNS_QUERIES -#define LWIP_DNS_ISMDNS_ARG(x) , x -#else -#define LWIP_DNS_ISMDNS_ARG(x) -#endif - -/** DNS query message structure. - No packing needed: only used locally on the stack. */ -struct dns_query { - /* DNS query record starts with either a domain name or a pointer - to a name already present somewhere in the packet. */ - u16_t type; - u16_t cls; -}; -#define SIZEOF_DNS_QUERY 4 - -/** DNS answer message structure. - No packing needed: only used locally on the stack. */ -struct dns_answer { - /* DNS answer record starts with either a domain name or a pointer - to a name already present somewhere in the packet. */ - u16_t type; - u16_t cls; - u32_t ttl; - u16_t len; -}; -#define SIZEOF_DNS_ANSWER 10 -/* maximum allowed size for the struct due to non-packed */ -#define SIZEOF_DNS_ANSWER_ASSERT 12 - -/* DNS table entry states */ -typedef enum { - DNS_STATE_UNUSED = 0, - DNS_STATE_NEW = 1, - DNS_STATE_ASKING = 2, - DNS_STATE_DONE = 3 -} dns_state_enum_t; - -/** DNS table entry */ -struct dns_table_entry { - u32_t ttl; - ip_addr_t ipaddr; - u16_t txid; - u8_t state; - u8_t server_idx; - u8_t tmr; - u8_t retries; - u8_t seqno; -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) - u8_t pcb_idx; -#endif - char name[DNS_MAX_NAME_LENGTH]; -#if LWIP_IPV4 && LWIP_IPV6 - u8_t reqaddrtype; -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - u8_t is_mdns; -#endif -}; - -/** DNS request table entry: used when dns_gehostbyname cannot answer the - * request from the DNS table */ -struct dns_req_entry { - /* pointer to callback on DNS query done */ - dns_found_callback found; - /* argument passed to the callback function */ - void *arg; -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) - u8_t dns_table_idx; -#endif -#if LWIP_IPV4 && LWIP_IPV6 - u8_t reqaddrtype; -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -}; - -#if DNS_LOCAL_HOSTLIST - -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -/** Local host-list. For hostnames in this list, no - * external name resolution is performed */ -static struct local_hostlist_entry *local_hostlist_dynamic; -#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -/** Defining this allows the local_hostlist_static to be placed in a different - * linker section (e.g. FLASH) */ -#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE -#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static -#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */ -/** Defining this allows the local_hostlist_static to be placed in a different - * linker section (e.g. FLASH) */ -#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST -#define DNS_LOCAL_HOSTLIST_STORAGE_POST -#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */ -DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[] - DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT; - -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -static void dns_init_local(void); -static err_t dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)); -#endif /* DNS_LOCAL_HOSTLIST */ - - -/* forward declarations */ -static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); -static void dns_check_entries(void); -static void dns_call_found(u8_t idx, ip_addr_t* addr); - -/*----------------------------------------------------------------------------- - * Globals - *----------------------------------------------------------------------------*/ - -/* DNS variables */ -static struct udp_pcb *dns_pcbs[DNS_MAX_SOURCE_PORTS]; - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) -static u8_t dns_last_pcb_idx; -#endif - -static u8_t dns_seqno; -static struct dns_table_entry dns_table[DNS_TABLE_SIZE]; -static struct dns_req_entry dns_requests[DNS_MAX_REQUESTS]; -static ip_addr_t dns_servers[DNS_MAX_SERVERS]; - -#if LWIP_IPV4 -const ip_addr_t dns_mquery_v4group = DNS_MQUERY_IPV4_GROUP_INIT; -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 -const ip_addr_t dns_mquery_v6group = DNS_MQUERY_IPV6_GROUP_INIT; -#endif /* LWIP_IPV6 */ - -/** - * Initialize the resolver: set up the UDP pcb and configure the default server - * (if DNS_SERVER_ADDRESS is set). - */ -void -dns_init(void) -{ -#ifdef DNS_SERVER_ADDRESS - /* initialize default DNS server address */ - ip_addr_t dnsserver; - DNS_SERVER_ADDRESS(&dnsserver); - dns_setserver(0, &dnsserver); -#endif /* DNS_SERVER_ADDRESS */ - - LWIP_ASSERT("sanity check SIZEOF_DNS_QUERY", - sizeof(struct dns_query) == SIZEOF_DNS_QUERY); - LWIP_ASSERT("sanity check SIZEOF_DNS_ANSWER", - sizeof(struct dns_answer) <= SIZEOF_DNS_ANSWER_ASSERT); - - LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n")); - - /* if dns client not yet initialized... */ -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0) - if (dns_pcbs[0] == NULL) { - dns_pcbs[0] = udp_new_ip_type(IPADDR_TYPE_ANY); - LWIP_ASSERT("dns_pcbs[0] != NULL", dns_pcbs[0] != NULL); - - /* initialize DNS table not needed (initialized to zero since it is a - * global variable) */ - LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0", - DNS_STATE_UNUSED == 0); - - /* initialize DNS client */ - udp_bind(dns_pcbs[0], IP_ANY_TYPE, 0); - udp_recv(dns_pcbs[0], dns_recv, NULL); - } -#endif - -#if DNS_LOCAL_HOSTLIST - dns_init_local(); -#endif -} - -/** - * @ingroup dns - * Initialize one of the DNS servers. - * - * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS - * @param dnsserver IP address of the DNS server to set - */ -void -dns_setserver(u8_t numdns, const ip_addr_t *dnsserver) -{ - if (numdns < DNS_MAX_SERVERS) - { - if (dnsserver != NULL) { - dns_servers[numdns] = (*dnsserver); - } else { - dns_servers[numdns] = *IP_ADDR_ANY; - } - } -} - -/** - * @ingroup dns - * Obtain one of the currently configured DNS server. - * - * @param numdns the index of the DNS server - * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS - * server has not been configured. - */ -const ip_addr_t* dns_getserver(u8_t numdns) -{ - if (numdns < DNS_MAX_SERVERS) { - return &dns_servers[numdns]; - } else { - return IP_ADDR_ANY; - } -} - -/** - * The DNS resolver client timer - handle retries and timeouts and should - * be called every DNS_TMR_INTERVAL milliseconds (every second by default). - */ -void dns_tmr(void) -{ - os_null_printf(DNS_DEBUG, ("dns_tmr: dns_check_entries\n")); - dns_check_entries(); -} - -#if DNS_LOCAL_HOSTLIST -static void -dns_init_local(void) -{ -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) - size_t i; - struct local_hostlist_entry *entry; - /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */ - struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT; - size_t namelen; - for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_init); i++) { - struct local_hostlist_entry *init_entry = &local_hostlist_init[i]; - LWIP_ASSERT("invalid host name (NULL)", init_entry->name != NULL); - namelen = strlen(init_entry->name); - LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); - entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); - LWIP_ASSERT("mem-error in dns_init_local", entry != NULL); - if (entry != NULL) { - char* entry_name = (char*)entry + sizeof(struct local_hostlist_entry); - MEMCPY(entry_name, init_entry->name, namelen); - entry_name[namelen] = 0; - entry->name = entry_name; - entry->addr = init_entry->addr; - entry->next = local_hostlist_dynamic; - local_hostlist_dynamic = entry; - } - } -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */ -} - -/** - * @ingroup dns - * Iterate the local host-list for a hostname. - * - * @param iterator_fn a function that is called for every entry in the local host-list - * @param iterator_arg 3rd argument passed to iterator_fn - * @return the number of entries in the local host-list - */ -size_t -dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg) -{ - size_t i; -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC - struct local_hostlist_entry *entry = local_hostlist_dynamic; - i = 0; - while (entry != NULL) { - if (iterator_fn != NULL) { - iterator_fn(entry->name, &entry->addr, iterator_arg); - } - i++; - entry = entry->next; - } -#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) { - if (iterator_fn != NULL) { - iterator_fn(local_hostlist_static[i].name, &local_hostlist_static[i].addr, iterator_arg); - } - } -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - return i; -} - -/** - * @ingroup dns - * Scans the local host-list for a hostname. - * - * @param hostname Hostname to look for in the local host-list - * @param addr the first IP address for the hostname in the local host-list or - * IPADDR_NONE if not found. - * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 (ATTENTION: no fallback here!) - * - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 (ATTENTION: no fallback here!) - * - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only - * - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only - * @return ERR_OK if found, ERR_ARG if not found - */ -err_t -dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype) -{ - LWIP_UNUSED_ARG(dns_addrtype); - return dns_lookup_local(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)); -} - -/* Internal implementation for dns_local_lookup and dns_lookup */ -static err_t -dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)) -{ -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC - struct local_hostlist_entry *entry = local_hostlist_dynamic; - while (entry != NULL) { - if ((lwip_stricmp(entry->name, hostname) == 0) && - LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, entry->addr)) { - if (addr) { - ip_addr_copy(*addr, entry->addr); - } - return ERR_OK; - } - entry = entry->next; - } -#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - size_t i; - for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) { - if ((lwip_stricmp(local_hostlist_static[i].name, hostname) == 0) && - LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, local_hostlist_static[i].addr)) { - if (addr) { - ip_addr_copy(*addr, local_hostlist_static[i].addr); - } - return ERR_OK; - } - } -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - return ERR_ARG; -} - -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -/** - * @ingroup dns - * Remove all entries from the local host-list for a specific hostname - * and/or IP address - * - * @param hostname hostname for which entries shall be removed from the local - * host-list - * @param addr address for which entries shall be removed from the local host-list - * @return the number of removed entries - */ -int -dns_local_removehost(const char *hostname, const ip_addr_t *addr) -{ - int removed = 0; - struct local_hostlist_entry *entry = local_hostlist_dynamic; - struct local_hostlist_entry *last_entry = NULL; - while (entry != NULL) { - if (((hostname == NULL) || !lwip_stricmp(entry->name, hostname)) && - ((addr == NULL) || ip_addr_cmp(&entry->addr, addr))) { - struct local_hostlist_entry *free_entry; - if (last_entry != NULL) { - last_entry->next = entry->next; - } else { - local_hostlist_dynamic = entry->next; - } - free_entry = entry; - entry = entry->next; - memp_free(MEMP_LOCALHOSTLIST, free_entry); - removed++; - } else { - last_entry = entry; - entry = entry->next; - } - } - return removed; -} - -/** - * @ingroup dns - * Add a hostname/IP address pair to the local host-list. - * Duplicates are not checked. - * - * @param hostname hostname of the new entry - * @param addr IP address of the new entry - * @return ERR_OK if succeeded or ERR_MEM on memory error - */ -err_t -dns_local_addhost(const char *hostname, const ip_addr_t *addr) -{ - struct local_hostlist_entry *entry; - size_t namelen; - char* entry_name; - LWIP_ASSERT("invalid host name (NULL)", hostname != NULL); - namelen = strlen(hostname); - LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); - entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); - if (entry == NULL) { - return ERR_MEM; - } - entry_name = (char*)entry + sizeof(struct local_hostlist_entry); - MEMCPY(entry_name, hostname, namelen); - entry_name[namelen] = 0; - entry->name = entry_name; - ip_addr_copy(entry->addr, *addr); - entry->next = local_hostlist_dynamic; - local_hostlist_dynamic = entry; - return ERR_OK; -} -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/ -#endif /* DNS_LOCAL_HOSTLIST */ - -/** - * @ingroup dns - * Look up a hostname in the array of known hostnames. - * - * @note This function only looks in the internal array of known - * hostnames, it does not send out a query for the hostname if none - * was found. The function dns_enqueue() can be used to send a query - * for a hostname. - * - * @param name the hostname to look up - * @param addr the hostname's IP address, as u32_t (instead of ip_addr_t to - * better check for failure: != IPADDR_NONE) or IPADDR_NONE if the hostname - * was not found in the cached dns_table. - * @return ERR_OK if found, ERR_ARG if not found - */ -static err_t -dns_lookup(const char *name, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)) -{ - u8_t i; - -#if DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) -#endif /* DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) */ - -#if DNS_LOCAL_HOSTLIST - if (dns_lookup_local(name, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) { - return ERR_OK; - } -#endif /* DNS_LOCAL_HOSTLIST */ - -#ifdef DNS_LOOKUP_LOCAL_EXTERN - if (DNS_LOOKUP_LOCAL_EXTERN(name, addr, LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(dns_addrtype)) == ERR_OK) { - return ERR_OK; - } -#endif /* DNS_LOOKUP_LOCAL_EXTERN */ - - /* Walk through name list, return entry if found. If not, return NULL. */ - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - if ((dns_table[i].state == DNS_STATE_DONE) && - (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0) && - LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, dns_table[i].ipaddr)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name)); - ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr)); - LWIP_DEBUGF(DNS_DEBUG, ("\n")); - if (addr) { - ip_addr_copy(*addr, dns_table[i].ipaddr); - } - return ERR_OK; - } - } - - return ERR_ARG; -} - -/** - * Compare the "dotted" name "query" with the encoded name "response" - * to make sure an answer from the DNS server matches the current dns_table - * entry (otherwise, answers might arrive late for hostname not on the list - * any more). - * - * @param query hostname (not encoded) from the dns_table - * @param p pbuf containing the encoded hostname in the DNS response - * @param start_offset offset into p where the name starts - * @return 0xFFFF: names differ, other: names equal -> offset behind name - */ -static u16_t -dns_compare_name(const char *query, struct pbuf* p, u16_t start_offset) -{ - int n; - u16_t response_offset = start_offset; - - do { - n = pbuf_try_get_at(p, response_offset++); - if (n < 0) { - return 0xFFFF; - } - /** @see RFC 1035 - 4.1.4. Message compression */ - if ((n & 0xc0) == 0xc0) { - /* Compressed name: cannot be equal since we don't send them */ - return 0xFFFF; - } else { - /* Not compressed name */ - while (n > 0) { - int c = pbuf_try_get_at(p, response_offset); - if (c < 0) { - return 0xFFFF; - } - if ((*query) != (u8_t)c) { - return 0xFFFF; - } - ++response_offset; - ++query; - --n; - } - ++query; - } - n = pbuf_try_get_at(p, response_offset); - if (n < 0) { - return 0xFFFF; - } - } while (n != 0); - - return response_offset + 1; -} - -/** - * Walk through a compact encoded DNS name and return the end of the name. - * - * @param p pbuf containing the name - * @param query_idx start index into p pointing to encoded DNS name in the DNS server response - * @return index to end of the name - */ -static u16_t -dns_skip_name(struct pbuf* p, u16_t query_idx) -{ - int n; - u16_t offset = query_idx; - - do { - n = pbuf_try_get_at(p, offset++); - if (n < 0) { - return 0xFFFF; - } - /** @see RFC 1035 - 4.1.4. Message compression */ - if ((n & 0xc0) == 0xc0) { - /* Compressed name: since we only want to skip it (not check it), stop here */ - break; - } else { - /* Not compressed name */ - if (offset + n >= p->tot_len) { - return 0xFFFF; - } - offset = (u16_t)(offset + n); - } - n = pbuf_try_get_at(p, offset); - if (n < 0) { - return 0xFFFF; - } - } while (n != 0); - - return offset + 1; -} - -/** - * Send a DNS query packet. - * - * @param idx the DNS table entry index for which to send a request - * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise - */ -static err_t -dns_send(u8_t idx) -{ - err_t err; - struct dns_hdr hdr; - struct dns_query qry; - struct pbuf *p; - u16_t query_idx, copy_len; - const char *hostname, *hostname_part; - u8_t n; - u8_t pcb_idx; - struct dns_table_entry* entry = &dns_table[idx]; - - LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n", - (u16_t)(entry->server_idx), entry->name)); - LWIP_ASSERT("dns server out of array", entry->server_idx < DNS_MAX_SERVERS); - if (ip_addr_isany_val(dns_servers[entry->server_idx]) -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - && !entry->is_mdns -#endif - ) { - /* DNS server not valid anymore, e.g. PPP netif has been shut down */ - /* call specified callback function if provided */ - dns_call_found(idx, NULL); - /* flush this entry */ - entry->state = DNS_STATE_UNUSED; - return ERR_OK; - } - - /* if here, we have either a new query or a retry on a previous query to process */ - p = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(SIZEOF_DNS_HDR + strlen(entry->name) + 2 + - SIZEOF_DNS_QUERY), PBUF_RAM); - if (p != NULL) { - const ip_addr_t* dst; - u16_t dst_port; - /* fill dns header */ - memset(&hdr, 0, SIZEOF_DNS_HDR); - hdr.id = lwip_htons(entry->txid); - hdr.flags1 = DNS_FLAG1_RD; - hdr.numquestions = PP_HTONS(1); - pbuf_take(p, &hdr, SIZEOF_DNS_HDR); - hostname = entry->name; - --hostname; - - /* convert hostname into suitable query format. */ - query_idx = SIZEOF_DNS_HDR; - do { - ++hostname; - hostname_part = hostname; - for (n = 0; *hostname != '.' && *hostname != 0; ++hostname) { - ++n; - } - copy_len = (u16_t)(hostname - hostname_part); - pbuf_put_at(p, query_idx, n); - pbuf_take_at(p, hostname_part, copy_len, query_idx + 1); - query_idx += n + 1; - } while (*hostname != 0); - pbuf_put_at(p, query_idx, 0); - query_idx++; - - /* fill dns query */ - if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) { - qry.type = PP_HTONS(DNS_RRTYPE_AAAA); - } else { - qry.type = PP_HTONS(DNS_RRTYPE_A); - } - qry.cls = PP_HTONS(DNS_RRCLASS_IN); - pbuf_take_at(p, &qry, SIZEOF_DNS_QUERY, query_idx); - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) - pcb_idx = entry->pcb_idx; -#else - pcb_idx = 0; -#endif - /* send dns packet */ - LWIP_DEBUGF(DNS_DEBUG, ("sending DNS request ID %d for name \"%s\" to server %d\r\n", - entry->txid, entry->name, entry->server_idx)); -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - if (entry->is_mdns) { - dst_port = DNS_MQUERY_PORT; -#if LWIP_IPV6 - if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) - { - dst = &dns_mquery_v6group; - } -#endif -#if LWIP_IPV4 && LWIP_IPV6 - else -#endif -#if LWIP_IPV4 - { - dst = &dns_mquery_v4group; - } -#endif - } else -#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ - { - dst_port = DNS_SERVER_PORT; - dst = &dns_servers[entry->server_idx]; - } - err = udp_sendto(dns_pcbs[pcb_idx], p, dst, dst_port); - - /* free pbuf */ - pbuf_free(p); - } else { - err = ERR_MEM; - } - - return err; -} - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) -static struct udp_pcb* -dns_alloc_random_port(void) -{ - err_t err; - struct udp_pcb* ret; - - ret = udp_new_ip_type(IPADDR_TYPE_ANY); - if (ret == NULL) { - /* out of memory, have to reuse an existing pcb */ - return NULL; - } - - do { - u16_t port = (u16_t)DNS_RAND_TXID(); - if (!DNS_PORT_ALLOWED(port)) { - /* this port is not allowed, try again */ - err = ERR_USE; - continue; - } - err = udp_bind(ret, IP_ANY_TYPE, port); - } while (err == ERR_USE); - - if (err != ERR_OK) { - udp_remove(ret); - return NULL; - } - - udp_recv(ret, dns_recv, NULL); - - return ret; -} - -/** - * dns_alloc_pcb() - allocates a new pcb (or reuses an existing one) to be used - * for sending a request - * - * @return an index into dns_pcbs - */ -static u8_t -dns_alloc_pcb(void) -{ - u8_t i; - u8_t idx; - - for (i = 0; i < DNS_MAX_SOURCE_PORTS; i++) { - if (dns_pcbs[i] == NULL) { - break; - } - } - if (i < DNS_MAX_SOURCE_PORTS) { - dns_pcbs[i] = dns_alloc_random_port(); - if (dns_pcbs[i] != NULL) { - /* succeeded */ - dns_last_pcb_idx = i; - return i; - } - } - /* if we come here, creating a new UDP pcb failed, so we have to use - an already existing one */ - for (i = 0, idx = dns_last_pcb_idx + 1; i < DNS_MAX_SOURCE_PORTS; i++, idx++) { - if (idx >= DNS_MAX_SOURCE_PORTS) { - idx = 0; - } - if (dns_pcbs[idx] != NULL) { - dns_last_pcb_idx = idx; - return idx; - } - } - return DNS_MAX_SOURCE_PORTS; -} -#endif /* ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) */ - -/** - * dns_call_found() - call the found callback and check if there are duplicate - * entries for the given hostname. If there are any, their found callback will - * be called and they will be removed. - * - * @param idx dns table index of the entry that is resolved or removed - * @param addr IP address for the hostname (or NULL on error or memory shortage) - */ -static void -dns_call_found(u8_t idx, ip_addr_t* addr) -{ -#if ((LWIP_DNS_SECURE & (LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)) != 0) - u8_t i; -#endif - -#if LWIP_IPV4 && LWIP_IPV6 - if (addr != NULL) { - /* check that address type matches the request and adapt the table entry */ - if (IP_IS_V6_VAL(*addr)) { - LWIP_ASSERT("invalid response", LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype)); - dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6; - } else { - LWIP_ASSERT("invalid response", !LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype)); - dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4; - } - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) - for (i = 0; i < DNS_MAX_REQUESTS; i++) { - if (dns_requests[i].found && (dns_requests[i].dns_table_idx == idx)) { - (*dns_requests[i].found)(dns_table[idx].name, addr, dns_requests[i].arg); - /* flush this entry */ - dns_requests[i].found = NULL; - } - } -#else - if (dns_requests[idx].found) { - (*dns_requests[idx].found)(dns_table[idx].name, addr, dns_requests[idx].arg); - } - dns_requests[idx].found = NULL; -#endif -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) - /* close the pcb used unless other request are using it */ - for (i = 0; i < DNS_MAX_REQUESTS; i++) { - if (i == idx) { - continue; /* only check other requests */ - } - if (dns_table[i].state == DNS_STATE_ASKING) { - if (dns_table[i].pcb_idx == dns_table[idx].pcb_idx) { - /* another request is still using the same pcb */ - dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; - break; - } - } - } - if (dns_table[idx].pcb_idx < DNS_MAX_SOURCE_PORTS) { - /* if we come here, the pcb is not used any more and can be removed */ - udp_remove(dns_pcbs[dns_table[idx].pcb_idx]); - dns_pcbs[dns_table[idx].pcb_idx] = NULL; - dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; - } -#endif -} - -/* Create a query transmission ID that is unique for all outstanding queries */ -static u16_t -dns_create_txid(void) -{ - u16_t txid; - u8_t i; - -again: - txid = (u16_t)DNS_RAND_TXID(); - - /* check whether the ID is unique */ - for (i = 0; i < DNS_TABLE_SIZE; i++) { - if ((dns_table[i].state == DNS_STATE_ASKING) && - (dns_table[i].txid == txid)) { - /* ID already used by another pending query */ - goto again; - } - } - - return txid; -} - -/** - * dns_check_entry() - see if entry has not yet been queried and, if so, sends out a query. - * Check an entry in the dns_table: - * - send out query for new entries - * - retry old pending entries on timeout (also with different servers) - * - remove completed entries from the table if their TTL has expired - * - * @param i index of the dns_table entry to check - */ -static void -dns_check_entry(u8_t i) -{ - err_t err; - struct dns_table_entry *entry = &dns_table[i]; - - LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE); - - switch (entry->state) { - case DNS_STATE_NEW: - /* initialize new entry */ - entry->txid = dns_create_txid(); - entry->state = DNS_STATE_ASKING; - entry->server_idx = 0; - entry->tmr = 1; - entry->retries = 0; - - /* send DNS packet for this entry */ - err = dns_send(i); - if (err != ERR_OK) { - LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, - ("dns_send returned error: %s\n", lwip_strerr(err))); - } - break; - case DNS_STATE_ASKING: - if (--entry->tmr == 0) { - if (++entry->retries == DNS_MAX_RETRIES) { - if ((entry->server_idx + 1 < DNS_MAX_SERVERS) && !ip_addr_isany_val(dns_servers[entry->server_idx + 1]) -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - && !entry->is_mdns -#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ - ) { - /* change of server */ - entry->server_idx++; - entry->tmr = 1; - entry->retries = 0; - } else { - LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", entry->name)); - /* call specified callback function if provided */ - dns_call_found(i, NULL); - /* flush this entry */ - entry->state = DNS_STATE_UNUSED; - break; - } - } else { - /* wait longer for the next retry */ - entry->tmr = entry->retries; - } - - /* send DNS packet for this entry */ - err = dns_send(i); - if (err != ERR_OK) { - LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, - ("dns_send returned error: %s\n", lwip_strerr(err))); - } - } - break; - case DNS_STATE_DONE: - /* if the time to live is nul */ - if ((entry->ttl == 0) || (--entry->ttl == 0)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", entry->name)); - /* flush this entry, there cannot be any related pending entries in this state */ - entry->state = DNS_STATE_UNUSED; - } - break; - case DNS_STATE_UNUSED: - /* nothing to do */ - break; - default: - LWIP_ASSERT("unknown dns_table entry state:", 0); - break; - } -} - -/** - * Call dns_check_entry for each entry in dns_table - check all entries. - */ -static void -dns_check_entries(void) -{ - u8_t i; - - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - dns_check_entry(i); - } -} - -/** - * Save TTL and call dns_call_found for correct response. - */ -static void -dns_correct_response(u8_t idx, u32_t ttl) -{ - struct dns_table_entry *entry = &dns_table[idx]; - - entry->state = DNS_STATE_DONE; - - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", entry->name)); - ip_addr_debug_print(DNS_DEBUG, (&(entry->ipaddr))); - LWIP_DEBUGF(DNS_DEBUG, ("\n")); - - /* read the answer resource record's TTL, and maximize it if needed */ - entry->ttl = ttl; - if (entry->ttl > DNS_MAX_TTL) { - entry->ttl = DNS_MAX_TTL; - } - dns_call_found(idx, &entry->ipaddr); - - if (entry->ttl == 0) { - /* RFC 883, page 29: "Zero values are - interpreted to mean that the RR can only be used for the - transaction in progress, and should not be cached." - -> flush this entry now */ - /* entry reused during callback? */ - if (entry->state == DNS_STATE_DONE) { - entry->state = DNS_STATE_UNUSED; - } - } -} -/** - * Receive input function for DNS response packets arriving for the dns UDP pcb. - */ -static void -dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - u8_t i; - u16_t txid; - u16_t res_idx; - struct dns_hdr hdr; - struct dns_answer ans; - struct dns_query qry; - u16_t nquestions, nanswers; - - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(port); - - /* is the dns message big enough ? */ - if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n")); - /* free pbuf and return */ - goto memerr; - } - - /* copy dns payload inside static buffer for processing */ - if (pbuf_copy_partial(p, &hdr, SIZEOF_DNS_HDR, 0) == SIZEOF_DNS_HDR) { - /* Match the ID in the DNS header with the name table. */ - txid = lwip_htons(hdr.id); - for (i = 0; i < DNS_TABLE_SIZE; i++) { - const struct dns_table_entry *entry = &dns_table[i]; - if ((entry->state == DNS_STATE_ASKING) && - (entry->txid == txid)) { - - /* We only care about the question(s) and the answers. The authrr - and the extrarr are simply discarded. */ - nquestions = lwip_htons(hdr.numquestions); - nanswers = lwip_htons(hdr.numanswers); - - /* Check for correct response. */ - if ((hdr.flags1 & DNS_FLAG1_RESPONSE) == 0) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": not a response\n", entry->name)); - goto memerr; /* ignore this packet */ - } - if (nquestions != 1) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); - goto memerr; /* ignore this packet */ - } - -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - if (!entry->is_mdns) -#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ - { - /* Check whether response comes from the same network address to which the - question was sent. (RFC 5452) */ - if (!ip_addr_cmp(addr, &dns_servers[entry->server_idx])) { - goto memerr; /* ignore this packet */ - } - } - - /* Check if the name in the "question" part match with the name in the entry and - skip it if equal. */ - res_idx = dns_compare_name(entry->name, p, SIZEOF_DNS_HDR); - if (res_idx == 0xFFFF) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); - goto memerr; /* ignore this packet */ - } - - /* check if "question" part matches the request */ - if (pbuf_copy_partial(p, &qry, SIZEOF_DNS_QUERY, res_idx) != SIZEOF_DNS_QUERY) { - goto memerr; /* ignore this packet */ - } - if ((qry.cls != PP_HTONS(DNS_RRCLASS_IN)) || - (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_AAAA))) || - (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_A)))) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); - goto memerr; /* ignore this packet */ - } - /* skip the rest of the "question" part */ - res_idx += SIZEOF_DNS_QUERY; - - /* Check for error. If so, call callback to inform. */ - if (hdr.flags2 & DNS_FLAG2_ERR_MASK) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", entry->name)); - } else { - while ((nanswers > 0) && (res_idx < p->tot_len)) { - /* skip answer resource record's host name */ - res_idx = dns_skip_name(p, res_idx); - if (res_idx == 0xFFFF) { - goto memerr; /* ignore this packet */ - } - - /* Check for IP address type and Internet class. Others are discarded. */ - if (pbuf_copy_partial(p, &ans, SIZEOF_DNS_ANSWER, res_idx) != SIZEOF_DNS_ANSWER) { - goto memerr; /* ignore this packet */ - } - res_idx += SIZEOF_DNS_ANSWER; - - if (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) { -#if LWIP_IPV4 - if ((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.len == PP_HTONS(sizeof(ip4_addr_t)))) { -#if LWIP_IPV4 && LWIP_IPV6 - if (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - { - ip4_addr_t ip4addr; - /* read the IP address after answer resource record's header */ - if (pbuf_copy_partial(p, &ip4addr, sizeof(ip4_addr_t), res_idx) != sizeof(ip4_addr_t)) { - goto memerr; /* ignore this packet */ - } - ip_addr_copy_from_ip4(dns_table[i].ipaddr, ip4addr); - pbuf_free(p); - /* handle correct response */ - dns_correct_response(i, lwip_ntohl(ans.ttl)); - return; - } - } -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - if ((ans.type == PP_HTONS(DNS_RRTYPE_AAAA)) && (ans.len == PP_HTONS(sizeof(ip6_addr_t)))) { -#if LWIP_IPV4 && LWIP_IPV6 - if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - { - ip6_addr_t ip6addr; - /* read the IP address after answer resource record's header */ - if (pbuf_copy_partial(p, &ip6addr, sizeof(ip6_addr_t), res_idx) != sizeof(ip6_addr_t)) { - goto memerr; /* ignore this packet */ - } - ip_addr_copy_from_ip6(dns_table[i].ipaddr, ip6addr); - pbuf_free(p); - /* handle correct response */ - dns_correct_response(i, lwip_ntohl(ans.ttl)); - return; - } - } -#endif /* LWIP_IPV6 */ - } - /* skip this answer */ - if ((int)(res_idx + lwip_htons(ans.len)) > 0xFFFF) { - goto memerr; /* ignore this packet */ - } - res_idx += lwip_htons(ans.len); - --nanswers; - } -#if LWIP_IPV4 && LWIP_IPV6 - if ((entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) || - (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) { - if (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) { - /* IPv4 failed, try IPv6 */ - dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6; - } else { - /* IPv6 failed, try IPv4 */ - dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4; - } - pbuf_free(p); - dns_table[i].state = DNS_STATE_NEW; - dns_check_entry(i); - return; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", entry->name)); - } - /* call callback to indicate error, clean up memory and return */ - pbuf_free(p); - dns_call_found(i, NULL); - dns_table[i].state = DNS_STATE_UNUSED; - return; - } - } - } - -memerr: - /* deallocate memory and return */ - pbuf_free(p); - return; -} - -/** - * Queues a new hostname to resolve and sends out a DNS query for that hostname - * - * @param name the hostname that is to be queried - * @param hostnamelen length of the hostname - * @param found a callback function to be called on success, failure or timeout - * @param callback_arg argument to pass to the callback function - * @return err_t return code. - */ -static err_t -dns_enqueue(const char *name, size_t hostnamelen, dns_found_callback found, - void *callback_arg LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype) LWIP_DNS_ISMDNS_ARG(u8_t is_mdns)) -{ - u8_t i; - u8_t lseq, lseqi; - struct dns_table_entry *entry = NULL; - size_t namelen; - struct dns_req_entry* req; - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) - u8_t r; - /* check for duplicate entries */ - for (i = 0; i < DNS_TABLE_SIZE; i++) { - if ((dns_table[i].state == DNS_STATE_ASKING) && - (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0)) { -#if LWIP_IPV4 && LWIP_IPV6 - if (dns_table[i].reqaddrtype != dns_addrtype) { - /* requested address types don't match - this can lead to 2 concurrent requests, but mixing the address types - for the same host should not be that common */ - continue; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - /* this is a duplicate entry, find a free request entry */ - for (r = 0; r < DNS_MAX_REQUESTS; r++) { - if (dns_requests[r].found == 0) { - dns_requests[r].found = found; - dns_requests[r].arg = callback_arg; - dns_requests[r].dns_table_idx = i; - LWIP_DNS_SET_ADDRTYPE(dns_requests[r].reqaddrtype, dns_addrtype); - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": duplicate request\n", name)); - return ERR_INPROGRESS; - } - } - } - } - /* no duplicate entries found */ -#endif - - /* search an unused entry, or the oldest one */ - lseq = 0; - lseqi = DNS_TABLE_SIZE; - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - entry = &dns_table[i]; - /* is it an unused entry ? */ - if (entry->state == DNS_STATE_UNUSED) { - break; - } - /* check if this is the oldest completed entry */ - if (entry->state == DNS_STATE_DONE) { - u8_t age = dns_seqno - entry->seqno; - if (age > lseq) { - lseq = age; - lseqi = i; - } - } - } - - /* if we don't have found an unused entry, use the oldest completed one */ - if (i == DNS_TABLE_SIZE) { - if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) { - /* no entry can be used now, table is full */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name)); - return ERR_MEM; - } else { - /* use the oldest completed one */ - i = lseqi; - entry = &dns_table[i]; - } - } - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) - /* find a free request entry */ - req = NULL; - for (r = 0; r < DNS_MAX_REQUESTS; r++) { - if (dns_requests[r].found == NULL) { - req = &dns_requests[r]; - break; - } - } - if (req == NULL) { - /* no request entry can be used now, table is full */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS request entries table is full\n", name)); - return ERR_MEM; - } - req->dns_table_idx = i; -#else - /* in this configuration, the entry index is the same as the request index */ - req = &dns_requests[i]; -#endif - - /* use this entry */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i))); - - /* fill the entry */ - entry->state = DNS_STATE_NEW; - entry->seqno = dns_seqno; - LWIP_DNS_SET_ADDRTYPE(entry->reqaddrtype, dns_addrtype); - LWIP_DNS_SET_ADDRTYPE(req->reqaddrtype, dns_addrtype); - req->found = found; - req->arg = callback_arg; - namelen = LWIP_MIN(hostnamelen, DNS_MAX_NAME_LENGTH-1); - MEMCPY(entry->name, name, namelen); - entry->name[namelen] = 0; - -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) - entry->pcb_idx = dns_alloc_pcb(); - if (entry->pcb_idx >= DNS_MAX_SOURCE_PORTS) { - /* failed to get a UDP pcb */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": failed to allocate a pcb\n", name)); - entry->state = DNS_STATE_UNUSED; - req->found = NULL; - return ERR_MEM; - } - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS pcb %"U16_F"\n", name, (u16_t)(entry->pcb_idx))); -#endif - -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - entry->is_mdns = is_mdns; -#endif - - dns_seqno ++; - - /* force to send query without waiting timer */ - dns_check_entry(i); - - /* dns query is enqueued */ - return ERR_INPROGRESS; -} - -/** - * @ingroup dns - * Resolve a hostname (string) into an IP address. - * NON-BLOCKING callback version for use with raw API!!! - * - * Returns immediately with one of err_t return codes: - * - ERR_OK if hostname is a valid IP address string or the host - * name is already in the local names table. - * - ERR_INPROGRESS enqueue a request to be sent to the DNS server - * for resolution if no errors are present. - * - ERR_ARG: dns client not initialized or invalid hostname - * - * @param hostname the hostname that is to be queried - * @param addr pointer to a ip_addr_t where to store the address if it is already - * cached in the dns_table (only valid if ERR_OK is returned!) - * @param found a callback function to be called on success, failure or timeout (only if - * ERR_INPROGRESS is returned!) - * @param callback_arg argument to pass to the callback function - * @return a err_t return code. - */ -err_t -dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found, - void *callback_arg) -{ - return dns_gethostbyname_addrtype(hostname, addr, found, callback_arg, LWIP_DNS_ADDRTYPE_DEFAULT); -} - -/** - * @ingroup dns - * Like dns_gethostbyname, but returned address type can be controlled: - * @param hostname the hostname that is to be queried - * @param addr pointer to a ip_addr_t where to store the address if it is already - * cached in the dns_table (only valid if ERR_OK is returned!) - * @param found a callback function to be called on success, failure or timeout (only if - * ERR_INPROGRESS is returned!) - * @param callback_arg argument to pass to the callback function - * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 first, try IPv6 if IPv4 fails only - * - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 first, try IPv4 if IPv6 fails only - * - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only - * - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only - */ -err_t -dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, dns_found_callback found, - void *callback_arg, u8_t dns_addrtype) -{ - size_t hostnamelen; -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - u8_t is_mdns; -#endif - /* not initialized or no valid server yet, or invalid addr pointer - * or invalid hostname or invalid hostname length */ - if ((addr == NULL) || - (!hostname) || (!hostname[0])) { - return ERR_ARG; - } -#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0) - if (dns_pcbs[0] == NULL) { - return ERR_ARG; - } -#endif - - hostnamelen = strlen(hostname); - if (hostnamelen >= DNS_MAX_NAME_LENGTH) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_gethostbyname: name too long to resolve")); - return ERR_ARG; - } - -#if LWIP_HAVE_LOOPIF - if (strcmp(hostname, "localhost") == 0) { - ip_addr_set_loopback(LWIP_DNS_ADDRTYPE_IS_IPV6(dns_addrtype), addr); - return ERR_OK; - } -#endif /* LWIP_HAVE_LOOPIF */ - - /* host name already in octet notation? set ip addr and return ERR_OK */ - if (ipaddr_aton(hostname, addr)) { -#if LWIP_IPV4 && LWIP_IPV6 - if ((IP_IS_V6(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV4)) || - (IP_IS_V4(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV6))) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - { - return ERR_OK; - } - } - /* already have this address cached? */ - if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) { - return ERR_OK; - } -#if LWIP_IPV4 && LWIP_IPV6 - if ((dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) || (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) { - /* fallback to 2nd IP type and try again to lookup */ - u8_t fallback; - if (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) { - fallback = LWIP_DNS_ADDRTYPE_IPV6; - } else { - fallback = LWIP_DNS_ADDRTYPE_IPV4; - } - if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(fallback)) == ERR_OK) { - return ERR_OK; - } - } -#else /* LWIP_IPV4 && LWIP_IPV6 */ - LWIP_UNUSED_ARG(dns_addrtype); -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#if LWIP_DNS_SUPPORT_MDNS_QUERIES - if (strstr(hostname, ".local") == &hostname[hostnamelen] - 6) { - is_mdns = 1; - } else { - is_mdns = 0; - } - - if (!is_mdns) -#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ - { - /* prevent calling found callback if no server is set, return error instead */ - if (ip_addr_isany_val(dns_servers[0])) { - return ERR_VAL; - } - } - - /* queue query with specified callback */ - return dns_enqueue(hostname, hostnamelen, found, callback_arg LWIP_DNS_ADDRTYPE_ARG(dns_addrtype) - LWIP_DNS_ISMDNS_ARG(is_mdns)); -} - -#endif /* LWIP_DNS */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/inet_chksum.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/inet_chksum.c deleted file mode 100644 index 917f3e4f1aacebdb222c4cc280b19b6b654fedaa..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/inet_chksum.c +++ /dev/null @@ -1,609 +0,0 @@ -/** - * @file - * Incluse internet checksum functions.\n - * - * These are some reference implementations of the checksum algorithm, with the - * aim of being simple, correct and fully portable. Checksumming is the - * first thing you would want to optimize for your platform. If you create - * your own version, link it in and in your cc.h put: - * - * \#define LWIP_CHKSUM your_checksum_routine - * - * Or you can select from the implementations below by defining - * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/inet_chksum.h" -#include "lwip/def.h" -#include "lwip/ip_addr.h" - -#include - -#ifndef LWIP_CHKSUM -# define LWIP_CHKSUM lwip_standard_chksum -# ifndef LWIP_CHKSUM_ALGORITHM -# define LWIP_CHKSUM_ALGORITHM 2 -# endif -u16_t lwip_standard_chksum(const void *dataptr, int len); -#endif -/* If none set: */ -#ifndef LWIP_CHKSUM_ALGORITHM -# define LWIP_CHKSUM_ALGORITHM 0 -#endif - -#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */ -/** - * lwip checksum - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * @note accumulator size limits summable length to 64k - * @note host endianess is irrelevant (p3 RFC1071) - */ -u16_t -lwip_standard_chksum(const void *dataptr, int len) -{ - u32_t acc; - u16_t src; - const u8_t *octetptr; - - acc = 0; - /* dataptr may be at odd or even addresses */ - octetptr = (const u8_t*)dataptr; - while (len > 1) { - /* declare first octet as most significant - thus assume network order, ignoring host order */ - src = (*octetptr) << 8; - octetptr++; - /* declare second octet as least significant */ - src |= (*octetptr); - octetptr++; - acc += src; - len -= 2; - } - if (len > 0) { - /* accumulate remaining octet */ - src = (*octetptr) << 8; - acc += src; - } - /* add deferred carry bits */ - acc = (acc >> 16) + (acc & 0x0000ffffUL); - if ((acc & 0xffff0000UL) != 0) { - acc = (acc >> 16) + (acc & 0x0000ffffUL); - } - /* This maybe a little confusing: reorder sum using lwip_htons() - instead of lwip_ntohs() since it has a little less call overhead. - The caller must invert bits for Internet sum ! */ - return lwip_htons((u16_t)acc); -} -#endif - -#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */ -/* - * Curt McDowell - * Broadcom Corp. - * csm@broadcom.com - * - * IP checksum two bytes at a time with support for - * unaligned buffer. - * Works for len up to and including 0x20000. - * by Curt McDowell, Broadcom Corp. 12/08/2005 - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - */ -u16_t -lwip_standard_chksum(const void *dataptr, int len) -{ - const u8_t *pb = (const u8_t *)dataptr; - const u16_t *ps; - u16_t t = 0; - u32_t sum = 0; - int odd = ((mem_ptr_t)pb & 1); - - /* Get aligned to u16_t */ - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - /* Add the bulk of the data */ - ps = (const u16_t *)(const void *)pb; - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* Consume left-over byte, if any */ - if (len > 0) { - ((u8_t *)&t)[0] = *(const u8_t *)ps; - } - - /* Add end bytes */ - sum += t; - - /* Fold 32-bit sum to 16 bits - calling this twice is probably faster than if statements... */ - sum = FOLD_U32T(sum); - sum = FOLD_U32T(sum); - - /* Swap if alignment was odd */ - if (odd) { - sum = SWAP_BYTES_IN_WORD(sum); - } - - return (u16_t)sum; -} -#endif - -#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */ -/** - * An optimized checksum routine. Basically, it uses loop-unrolling on - * the checksum loop, treating the head and tail bytes specially, whereas - * the inner loop acts on 8 bytes at a time. - * - * @arg start of buffer to be checksummed. May be an odd byte address. - * @len number of bytes in the buffer to be checksummed. - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * by Curt McDowell, Broadcom Corp. December 8th, 2005 - */ -u16_t -lwip_standard_chksum(const void *dataptr, int len) -{ - const u8_t *pb = (const u8_t *)dataptr; - const u16_t *ps; - u16_t t = 0; - const u32_t *pl; - u32_t sum = 0, tmp; - /* starts at odd byte address? */ - int odd = ((mem_ptr_t)pb & 1); - - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - ps = (const u16_t *)(const void*)pb; - - if (((mem_ptr_t)ps & 3) && len > 1) { - sum += *ps++; - len -= 2; - } - - pl = (const u32_t *)(const void*)ps; - - while (len > 7) { - tmp = sum + *pl++; /* ping */ - if (tmp < sum) { - tmp++; /* add back carry */ - } - - sum = tmp + *pl++; /* pong */ - if (sum < tmp) { - sum++; /* add back carry */ - } - - len -= 8; - } - - /* make room in upper bits */ - sum = FOLD_U32T(sum); - - ps = (const u16_t *)pl; - - /* 16-bit aligned word remaining? */ - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* dangling tail byte remaining? */ - if (len > 0) { /* include odd byte */ - ((u8_t *)&t)[0] = *(const u8_t *)ps; - } - - sum += t; /* add end bytes */ - - /* Fold 32-bit sum to 16 bits - calling this twice is probably faster than if statements... */ - sum = FOLD_U32T(sum); - sum = FOLD_U32T(sum); - - if (odd) { - sum = SWAP_BYTES_IN_WORD(sum); - } - - return (u16_t)sum; -} -#endif - -/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */ -static u16_t -inet_cksum_pseudo_base(struct pbuf *p, u8_t proto, u16_t proto_len, u32_t acc) -{ - struct pbuf *q; - u8_t swapped = 0; - - /* iterate through all pbuf in chain */ - for (q = p; q != NULL; q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - acc += LWIP_CHKSUM(q->payload, q->len); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - /* just executing this next line is probably faster that the if statement needed - to check whether we really need to execute it, and does no harm */ - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - - acc += (u32_t)lwip_htons((u16_t)proto); - acc += (u32_t)lwip_htons(proto_len); - - /* Fold 32-bit sum to 16 bits - calling this twice is probably faster than if statements... */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} - -#if LWIP_IPV4 -/* inet_chksum_pseudo: - * - * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * IP addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip4_addr_t *src, const ip4_addr_t *dest) -{ - u32_t acc; - u32_t addr; - - addr = ip4_addr_get_u32(src); - acc = (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - addr = ip4_addr_get_u32(dest); - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - /* fold down to 16 bits */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - - return inet_cksum_pseudo_base(p, proto, proto_len, acc); -} -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -/** - * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain. - * IPv6 addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param proto ipv6 protocol/next header (used for checksum of pseudo header) - * @param proto_len length of the ipv6 payload (used for checksum of pseudo header) - * @param src source ipv6 address (used for checksum of pseudo header) - * @param dest destination ipv6 address (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip6_addr_t *src, const ip6_addr_t *dest) -{ - u32_t acc = 0; - u32_t addr; - u8_t addr_part; - - for (addr_part = 0; addr_part < 4; addr_part++) { - addr = src->addr[addr_part]; - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - addr = dest->addr[addr_part]; - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - } - /* fold down to 16 bits */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - - return inet_cksum_pseudo_base(p, proto, proto_len, acc); -} -#endif /* LWIP_IPV6 */ - -/* ip_chksum_pseudo: - * - * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * IP addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip_addr_t *src, const ip_addr_t *dest) -{ -#if LWIP_IPV6 - if (IP_IS_V6(dest)) { - return ip6_chksum_pseudo(p, proto, proto_len, ip_2_ip6(src), ip_2_ip6(dest)); - } -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 && LWIP_IPV6 - else -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -#if LWIP_IPV4 - { - return inet_chksum_pseudo(p, proto, proto_len, ip_2_ip4(src), ip_2_ip4(dest)); - } -#endif /* LWIP_IPV4 */ -} - -/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */ -static u16_t -inet_cksum_pseudo_partial_base(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, u32_t acc) -{ - struct pbuf *q; - u8_t swapped = 0; - u16_t chklen; - - /* iterate through all pbuf in chain */ - for (q = p; (q != NULL) && (chksum_len > 0); q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - chklen = q->len; - if (chklen > chksum_len) { - chklen = chksum_len; - } - acc += LWIP_CHKSUM(q->payload, chklen); - chksum_len -= chklen; - LWIP_ASSERT("delete me", chksum_len < 0x7fff); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - /* fold the upper bit down */ - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - - acc += (u32_t)lwip_htons((u16_t)proto); - acc += (u32_t)lwip_htons(proto_len); - - /* Fold 32-bit sum to 16 bits - calling this twice is probably faster than if statements... */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} - -#if LWIP_IPV4 -/* inet_chksum_pseudo_partial: - * - * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * IP addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest) -{ - u32_t acc; - u32_t addr; - - addr = ip4_addr_get_u32(src); - acc = (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - addr = ip4_addr_get_u32(dest); - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - /* fold down to 16 bits */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - - return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc); -} -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -/** - * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain. - * IPv6 addresses are expected to be in network byte order. Will only compute for a - * portion of the payload. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param proto ipv6 protocol/next header (used for checksum of pseudo header) - * @param proto_len length of the ipv6 payload (used for checksum of pseudo header) - * @param chksum_len number of payload bytes used to compute chksum - * @param src source ipv6 address (used for checksum of pseudo header) - * @param dest destination ipv6 address (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest) -{ - u32_t acc = 0; - u32_t addr; - u8_t addr_part; - - for (addr_part = 0; addr_part < 4; addr_part++) { - addr = src->addr[addr_part]; - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - addr = dest->addr[addr_part]; - acc += (addr & 0xffffUL); - acc += ((addr >> 16) & 0xffffUL); - } - /* fold down to 16 bits */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - - return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc); -} -#endif /* LWIP_IPV6 */ - -/* ip_chksum_pseudo_partial: - * - * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest) -{ -#if LWIP_IPV6 - if (IP_IS_V6(dest)) { - return ip6_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip6(src), ip_2_ip6(dest)); - } -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 && LWIP_IPV6 - else -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -#if LWIP_IPV4 - { - return inet_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip4(src), ip_2_ip4(dest)); - } -#endif /* LWIP_IPV4 */ -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarily for IP - * and ICMP. - * - * @param dataptr start of the buffer to calculate the checksum (no alignment needed) - * @param len length of the buffer to calculate the checksum - * @return checksum (as u16_t) to be saved directly in the protocol header - */ - -u16_t -inet_chksum(const void *dataptr, u16_t len) -{ - return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len); -} - -/** - * Calculate a checksum over a chain of pbufs (without pseudo-header, much like - * inet_chksum only pbufs are used). - * - * @param p pbuf chain over that the checksum should be calculated - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for (q = p; q != NULL; q = q->next) { - acc += LWIP_CHKSUM(q->payload, q->len); - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - return (u16_t)~(acc & 0xffffUL); -} - -/* These are some implementations for LWIP_CHKSUM_COPY, which copies data - * like MEMCPY but generates a checksum at the same time. Since this is a - * performance-sensitive function, you might want to create your own version - * in assembly targeted at your hardware by defining it in lwipopts.h: - * #define LWIP_CHKSUM_COPY(dst, src, len) your_chksum_copy(dst, src, len) - */ - -#if (LWIP_CHKSUM_COPY_ALGORITHM == 1) /* Version #1 */ -/** Safe but slow: first call MEMCPY, then call LWIP_CHKSUM. - * For architectures with big caches, data might still be in cache when - * generating the checksum after copying. - */ -u16_t -lwip_chksum_copy(void *dst, const void *src, u16_t len) -{ - MEMCPY(dst, src, len); - return LWIP_CHKSUM(dst, len); -} -#endif /* (LWIP_CHKSUM_COPY_ALGORITHM == 1) */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/init.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/init.c deleted file mode 100644 index 4d4571a97c0383ac8682001fee951e72c05e8cf9..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/init.c +++ /dev/null @@ -1,382 +0,0 @@ -/** - * @file - * Modules initialization - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - */ - -#include "lwip/opt.h" - -#include "lwip/init.h" -#include "lwip/stats.h" -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/sockets.h" -#include "lwip/ip.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" -#include "lwip/timeouts.h" -#include "lwip/etharp.h" -#include "lwip/ip6.h" -#include "lwip/nd6.h" -#include "lwip/mld6.h" -#include "lwip/api.h" - -#ifndef LWIP_SKIP_PACKING_CHECK - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct packed_struct_test -{ - PACK_STRUCT_FLD_8(u8_t dummy1); - PACK_STRUCT_FIELD(u32_t dummy2); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define PACKED_STRUCT_TEST_EXPECTED_SIZE 5 - -#endif - -/* Compile-time sanity checks for configuration errors. - * These can be done independently of LWIP_DEBUG, without penalty. - */ -#ifndef BYTE_ORDER - #error "BYTE_ORDER is not defined, you have to define it in your cc.h" -#endif -#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV) - #error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_UDPLITE) - #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_DHCP) - #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_MULTICAST_TX_OPTIONS) - #error "If you want to use IGMP/LWIP_MULTICAST_TX_OPTIONS, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_DNS) - #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if !MEMP_MEM_MALLOC /* MEMP_NUM_* checks are disabled when not using the pool allocator */ -#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0)) - #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h" -#endif -#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0)) - #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0)) - #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0)) - #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1)) - #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h" -#endif -#if (LWIP_IGMP && !LWIP_MULTICAST_TX_OPTIONS) - #error "If you want to use IGMP, you have to define LWIP_MULTICAST_TX_OPTIONS==1 in your lwipopts.h" -#endif -#if (LWIP_IGMP && !LWIP_IPV4) - #error "IGMP needs LWIP_IPV4 enabled in your lwipopts.h" -#endif -#if (LWIP_MULTICAST_TX_OPTIONS && !LWIP_IPV4) - #error "LWIP_MULTICAST_TX_OPTIONS needs LWIP_IPV4 enabled in your lwipopts.h" -#endif -#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0)) - #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h" -#endif -/* There must be sufficient timeouts, taking into account requirements of the subsystems. */ -#if LWIP_TIMERS && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0))) - #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts" -#endif -#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS)) - #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!" -#endif -#endif /* !MEMP_MEM_MALLOC */ -#if LWIP_WND_SCALE -#if (LWIP_TCP && (TCP_WND > 0xffffffff)) - #error "If you want to use TCP, TCP_WND must fit in an u32_t, so, you have to reduce it in your lwipopts.h" -#endif -#if (LWIP_TCP && (TCP_RCV_SCALE > 14)) - #error "The maximum valid window scale value is 14!" -#endif -#if (LWIP_TCP && (TCP_WND > (0xFFFFU << TCP_RCV_SCALE))) - #error "TCP_WND is bigger than the configured LWIP_WND_SCALE allows!" -#endif -#if (LWIP_TCP && ((TCP_WND >> TCP_RCV_SCALE) == 0)) - #error "TCP_WND is too small for the configured LWIP_WND_SCALE (results in zero window)!" -#endif -#else /* LWIP_WND_SCALE */ -#if (LWIP_TCP && (TCP_WND > 0xffff)) - #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h (or enable window scaling)" -#endif -#endif /* LWIP_WND_SCALE */ -#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff)) - #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h" -#endif -#if (LWIP_TCP && (TCP_SND_QUEUELEN < 2)) - #error "TCP_SND_QUEUELEN must be at least 2 for no-copy TCP writes to work" -#endif -#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12))) - #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h" -#endif -#if (LWIP_TCP && TCP_LISTEN_BACKLOG && ((TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff))) - #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t" -#endif -#if (LWIP_NETIF_API && (NO_SYS==1)) - #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1)) - #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if (LWIP_PPP_API && (NO_SYS==1)) - #error "If you want to use PPP API, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if (LWIP_PPP_API && (PPP_SUPPORT==0)) - #error "If you want to use PPP API, you have to enable PPP_SUPPORT in your lwipopts.h" -#endif -#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP) - #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h" -#endif -#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK) - #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h" -#endif -#if (!LWIP_ARP && LWIP_AUTOIP) - #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h" -#endif -#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API))) - #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h" -#endif -#if (MEM_LIBC_MALLOC && MEM_USE_POOLS) - #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h" -#endif -#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS) - #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h" -#endif -#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT) - #error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf" -#endif -#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT))) - #error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST" -#endif -#if PPP_SUPPORT && !PPPOS_SUPPORT && !PPPOE_SUPPORT && !PPPOL2TP_SUPPORT - #error "PPP_SUPPORT needs at least one of PPPOS_SUPPORT, PPPOE_SUPPORT or PPPOL2TP_SUPPORT turned on" -#endif -#if PPP_SUPPORT && !PPP_IPV4_SUPPORT && !PPP_IPV6_SUPPORT - #error "PPP_SUPPORT needs PPP_IPV4_SUPPORT and/or PPP_IPV6_SUPPORT turned on" -#endif -#if PPP_SUPPORT && PPP_IPV4_SUPPORT && !LWIP_IPV4 - #error "PPP_IPV4_SUPPORT needs LWIP_IPV4 turned on" -#endif -#if PPP_SUPPORT && PPP_IPV6_SUPPORT && !LWIP_IPV6 - #error "PPP_IPV6_SUPPORT needs LWIP_IPV6 turned on" -#endif -#if !LWIP_ETHERNET && (LWIP_ARP || PPPOE_SUPPORT) - #error "LWIP_ETHERNET needs to be turned on for LWIP_ARP or PPPOE_SUPPORT" -#endif -#if LWIP_TCPIP_CORE_LOCKING_INPUT && !LWIP_TCPIP_CORE_LOCKING - #error "When using LWIP_TCPIP_CORE_LOCKING_INPUT, LWIP_TCPIP_CORE_LOCKING must be enabled, too" -#endif -#if LWIP_TCP && LWIP_NETIF_TX_SINGLE_PBUF && !TCP_OVERSIZE - #error "LWIP_NETIF_TX_SINGLE_PBUF needs TCP_OVERSIZE enabled to create single-pbuf TCP packets" -#endif -#if LWIP_NETCONN && LWIP_TCP -#if NETCONN_COPY != TCP_WRITE_FLAG_COPY - #error "NETCONN_COPY != TCP_WRITE_FLAG_COPY" -#endif -#if NETCONN_MORE != TCP_WRITE_FLAG_MORE - #error "NETCONN_MORE != TCP_WRITE_FLAG_MORE" -#endif -#endif /* LWIP_NETCONN && LWIP_TCP */ -#if LWIP_SOCKET -/* Check that the SO_* socket options and SOF_* lwIP-internal flags match */ -#if SO_REUSEADDR != SOF_REUSEADDR - #error "WARNING: SO_REUSEADDR != SOF_REUSEADDR" -#endif -#if SO_KEEPALIVE != SOF_KEEPALIVE - #error "WARNING: SO_KEEPALIVE != SOF_KEEPALIVE" -#endif -#if SO_BROADCAST != SOF_BROADCAST - #error "WARNING: SO_BROADCAST != SOF_BROADCAST" -#endif -#endif /* LWIP_SOCKET */ - - -/* Compile-time checks for deprecated options. - */ -#ifdef MEMP_NUM_TCPIP_MSG - #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef TCP_REXMIT_DEBUG - #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef RAW_STATS - #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef ETHARP_QUEUE_FIRST - #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef ETHARP_ALWAYS_INSERT - #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h." -#endif -#if !NO_SYS && LWIP_TCPIP_CORE_LOCKING && LWIP_COMPAT_MUTEX && !defined(LWIP_COMPAT_MUTEX_ALLOWED) - #error "LWIP_COMPAT_MUTEX cannot prevent priority inversion. It is recommended to implement priority-aware mutexes. (Define LWIP_COMPAT_MUTEX_ALLOWED to disable this error.)" -#endif - -#ifndef LWIP_DISABLE_TCP_SANITY_CHECKS -#define LWIP_DISABLE_TCP_SANITY_CHECKS 0 -#endif -#ifndef LWIP_DISABLE_MEMP_SANITY_CHECKS -#define LWIP_DISABLE_MEMP_SANITY_CHECKS 0 -#endif - -/* MEMP sanity checks */ -#if MEMP_MEM_MALLOC -#if !LWIP_DISABLE_MEMP_SANITY_CHECKS -#if LWIP_NETCONN || LWIP_SOCKET -#if !MEMP_NUM_NETCONN && LWIP_SOCKET -#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN cannot be 0 when using sockets!" -#endif -#else /* MEMP_MEM_MALLOC */ -#if MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB) -#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN. If you know what you are doing, define LWIP_DISABLE_MEMP_SANITY_CHECKS to 1 to disable this error." -#endif -#endif /* LWIP_NETCONN || LWIP_SOCKET */ -#endif /* !LWIP_DISABLE_MEMP_SANITY_CHECKS */ -#if MEM_USE_POOLS -#error "MEMP_MEM_MALLOC and MEM_USE_POOLS cannot be enabled at the same time" -#endif -#ifdef LWIP_HOOK_MEMP_AVAILABLE -#error "LWIP_HOOK_MEMP_AVAILABLE doesn't make sense with MEMP_MEM_MALLOC" -#endif -#endif /* MEMP_MEM_MALLOC */ - -/* TCP sanity checks */ -#if !LWIP_DISABLE_TCP_SANITY_CHECKS -#if LWIP_TCP -#if !MEMP_MEM_MALLOC && (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN) - #error "lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if TCP_SND_BUF < (2 * TCP_MSS) - #error "lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF / TCP_MSS)) - #error "lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if TCP_SNDLOWAT >= TCP_SND_BUF - #error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than TCP_SND_BUF. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if TCP_SNDLOWAT >= (0xFFFF - (4 * TCP_MSS)) - #error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must at least be 4*MSS below u16_t overflow!" -#endif -#if TCP_SNDQUEUELOWAT >= TCP_SND_QUEUELEN - #error "lwip_sanity_check: WARNING: TCP_SNDQUEUELOWAT must be less than TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (PBUF_POOL_BUFSIZE <= (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) - #error "lwip_sanity_check: WARNING: PBUF_POOL_BUFSIZE does not provide enough space for protocol headers. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (TCP_WND > (PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)))) - #error "lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - protocol headers). If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#if TCP_WND < TCP_MSS - #error "lwip_sanity_check: WARNING: TCP_WND is smaller than MSS. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." -#endif -#endif /* LWIP_TCP */ -#endif /* !LWIP_DISABLE_TCP_SANITY_CHECKS */ - -/** - * @ingroup lwip_nosys - * Initialize all modules. - * Use this in NO_SYS mode. Use tcpip_init() otherwise. - */ -void -lwip_init(void) -{ -#ifndef LWIP_SKIP_CONST_CHECK - int a; - LWIP_UNUSED_ARG(a); - LWIP_ASSERT("LWIP_CONST_CAST not implemented correctly. Check your lwIP port.", LWIP_CONST_CAST(void*, &a) == &a); -#endif -#ifndef LWIP_SKIP_PACKING_CHECK - LWIP_ASSERT("Struct packing not implemented correctly. Check your lwIP port.", sizeof(struct packed_struct_test) == PACKED_STRUCT_TEST_EXPECTED_SIZE); -#endif - - /* Modules initialization */ - stats_init(); -#if !NO_SYS - sys_init(); -#endif /* !NO_SYS */ - mem_init(); - memp_init(); - pbuf_init(); - netif_init(); -#if LWIP_IPV4 - ip_init(); -#if LWIP_ARP - etharp_init(); -#endif /* LWIP_ARP */ -#endif /* LWIP_IPV4 */ -#if LWIP_RAW - raw_init(); -#endif /* LWIP_RAW */ -#if LWIP_UDP - udp_init(); -#endif /* LWIP_UDP */ -#if LWIP_TCP - tcp_init(); -#endif /* LWIP_TCP */ -#if LWIP_IGMP - igmp_init(); -#endif /* LWIP_IGMP */ -#if LWIP_DNS - dns_init(); -#endif /* LWIP_DNS */ -#if PPP_SUPPORT - ppp_init(); -#endif - -#if LWIP_TIMERS - sys_timeouts_init(); -#endif /* LWIP_TIMERS */ -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ip.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ip.c deleted file mode 100644 index 2e0240851f4f92505e2bb254dd74bfad83f404f6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ip.c +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * Common IPv4 and IPv6 code - * - * @defgroup ip IP - * @ingroup callbackstyle_api - * - * @defgroup ip4 IPv4 - * @ingroup ip - * - * @defgroup ip6 IPv6 - * @ingroup ip - * - * @defgroup ipaddr IP address handling - * @ingroup infrastructure - * - * @defgroup ip4addr IPv4 only - * @ingroup ipaddr - * - * @defgroup ip6addr IPv6 only - * @ingroup ipaddr - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 || LWIP_IPV6 - -#include "lwip/ip_addr.h" -#include "lwip/ip.h" - -/** Global data for both IPv4 and IPv6 */ -struct ip_globals ip_data; - -#if LWIP_IPV4 && LWIP_IPV6 - -const ip_addr_t ip_addr_any_type = IPADDR_ANY_TYPE_INIT; - -/** - * @ingroup ipaddr - * Convert IP address string (both versions) to numeric. - * The version is auto-detected from the string. - * - * @param cp IP address string to convert - * @param addr conversion result is stored here - * @return 1 on success, 0 on error - */ -int -ipaddr_aton(const char *cp, ip_addr_t *addr) -{ - if (cp != NULL) { - const char* c; - for (c = cp; *c != 0; c++) { - if (*c == ':') { - /* contains a colon: IPv6 address */ - if (addr) { - IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V6); - } - return ip6addr_aton(cp, ip_2_ip6(addr)); - } else if (*c == '.') { - /* contains a dot: IPv4 address */ - break; - } - } - /* call ip4addr_aton as fallback or if IPv4 was found */ - if (addr) { - IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V4); - } - return ip4addr_aton(cp, ip_2_ip4(addr)); - } - return 0; -} - -/** - * @ingroup lwip_nosys - * If both IP versions are enabled, this function can dispatch packets to the correct one. - * Don't call directly, pass to netif_add() and call netif->input(). - */ -err_t -ip_input(struct pbuf *p, struct netif *inp) -{ - if (p != NULL) { - if (IP_HDR_GET_VERSION(p->payload) == 6) { - return ip6_input(p, inp); - } - return ip4_input(p, inp); - } - return ERR_VAL; -} - -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#endif /* LWIP_IPV4 || LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/dhcp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/dhcp.c deleted file mode 100644 index 292c63819c914db5ea6d9b0a62a0f8882ea681b8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/dhcp.c +++ /dev/null @@ -1,2043 +0,0 @@ -/** - * @file - * Dynamic Host Configuration Protocol client - * - * @defgroup dhcp4 DHCPv4 - * @ingroup ip4 - * DHCP (IPv4) related functions - * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform - * with RFC 2131 and RFC 2132. - * - * @todo: - * - Support for interfaces other than Ethernet (SLIP, PPP, ...) - * - * Options: - * @ref DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) - * @ref DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) - * - * dhcp_start() starts a DHCP client instance which - * configures the interface by obtaining an IP address lease and maintaining it. - * - * Use dhcp_release() to end the lease and use dhcp_stop() - * to remove the DHCP client. - * - * @see netifapi_dhcp4 - */ - -/* - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. - * - * Author: Leon Woestenberg - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 && LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/def.h" -#include "lwip/dhcp.h" -#include "lwip/dns.h" -#include "lwip/etharp.h" -#include "lwip/prot/dhcp.h" - -#include - -#include "error.h" -#include "fake_clock_pub.h" -#include "rtos_pub.h" -#include "role_launch.h" -#include "wlan_ui_pub.h" - -/** DHCP_CREATE_RAND_XID: if this is set to 1, the xid is created using - * LWIP_RAND() (this overrides DHCP_GLOBAL_XID) - */ -#ifndef DHCP_CREATE_RAND_XID -#define DHCP_CREATE_RAND_XID 1 -#endif - -/** Default for DHCP_GLOBAL_XID is 0xABCD0000 - * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g. - * \#define DHCP_GLOBAL_XID_HEADER "stdlib.h" - * \#define DHCP_GLOBAL_XID rand() - */ -#ifdef DHCP_GLOBAL_XID_HEADER -#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */ -#endif - -/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU - * MTU is checked to be big enough in dhcp_start */ -#define DHCP_MAX_MSG_LEN(netif) (netif->mtu) -#define DHCP_MAX_MSG_LEN_MIN_REQUIRED 576 -/** Minimum length for reply before packet is parsed */ -#define DHCP_MIN_REPLY_LEN 44 - -#define REBOOT_TRIES 2 - -#if LWIP_DNS && LWIP_DHCP_MAX_DNS_SERVERS -#if DNS_MAX_SERVERS > LWIP_DHCP_MAX_DNS_SERVERS -#define LWIP_DHCP_PROVIDE_DNS_SERVERS LWIP_DHCP_MAX_DNS_SERVERS -#else -#define LWIP_DHCP_PROVIDE_DNS_SERVERS DNS_MAX_SERVERS -#endif -#else -#define LWIP_DHCP_PROVIDE_DNS_SERVERS 0 -#endif - -/** Option handling: options are parsed in dhcp_parse_reply - * and saved in an array where other functions can load them from. - * This might be moved into the struct dhcp (not necessarily since - * lwIP is single-threaded and the array is only used while in recv - * callback). */ -enum dhcp_option_idx { - DHCP_OPTION_IDX_OVERLOAD = 0, - DHCP_OPTION_IDX_MSG_TYPE, - DHCP_OPTION_IDX_SERVER_ID, - DHCP_OPTION_IDX_LEASE_TIME, - DHCP_OPTION_IDX_T1, - DHCP_OPTION_IDX_T2, - DHCP_OPTION_IDX_SUBNET_MASK, - DHCP_OPTION_IDX_ROUTER, - -#if LWIP_DHCP_PROVIDE_DNS_SERVERS - DHCP_OPTION_IDX_DNS_SERVER, - DHCP_OPTION_IDX_DNS_SERVER_LAST = DHCP_OPTION_IDX_DNS_SERVER + LWIP_DHCP_PROVIDE_DNS_SERVERS - 1, -#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ - -#if LWIP_DHCP_GET_NTP_SRV - DHCP_OPTION_IDX_NTP_SERVER, - DHCP_OPTION_IDX_NTP_SERVER_LAST = DHCP_OPTION_IDX_NTP_SERVER + LWIP_DHCP_MAX_NTP_SERVERS - 1, -#endif /* LWIP_DHCP_GET_NTP_SRV */ - - DHCP_OPTION_IDX_MAX -}; - -/** Holds the decoded option values, only valid while in dhcp_recv. - @todo: move this into struct dhcp? */ -u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX]; -/** Holds a flag which option was received and is contained in dhcp_rx_options_val, - only valid while in dhcp_recv. - @todo: move this into struct dhcp? */ -u8_t dhcp_rx_options_given[DHCP_OPTION_IDX_MAX]; - -static u8_t dhcp_discover_request_options[] = { - DHCP_OPTION_SUBNET_MASK, - DHCP_OPTION_ROUTER, - DHCP_OPTION_BROADCAST -#if LWIP_DHCP_PROVIDE_DNS_SERVERS - , DHCP_OPTION_DNS_SERVER -#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ -#if LWIP_DHCP_GET_NTP_SRV - , DHCP_OPTION_NTP -#endif /* LWIP_DHCP_GET_NTP_SRV */ - }; - -#ifdef DHCP_GLOBAL_XID -static u32_t xid; -static u8_t xid_initialised; -#endif /* DHCP_GLOBAL_XID */ -static beken2_timer_t dhcp_tmr = {0}; - -#define dhcp_option_given(dhcp, idx) (dhcp_rx_options_given[idx] != 0) -#define dhcp_got_option(dhcp, idx) (dhcp_rx_options_given[idx] = 1) -#define dhcp_clear_option(dhcp, idx) (dhcp_rx_options_given[idx] = 0) -#define dhcp_clear_all_options(dhcp) (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given))) -#define dhcp_get_option_value(dhcp, idx) (dhcp_rx_options_val[idx]) -#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val)) - -static struct udp_pcb *dhcp_pcb; -static u8_t dhcp_pcb_refcount; - -/* DHCP client state machine functions */ -static err_t dhcp_discover(struct netif *netif); -static err_t dhcp_select(struct netif *netif); -static void dhcp_bind(struct netif *netif); -#if DHCP_DOES_ARP_CHECK -static err_t dhcp_decline(struct netif *netif); -#endif /* DHCP_DOES_ARP_CHECK */ -static err_t dhcp_rebind(struct netif *netif); -static err_t dhcp_reboot(struct netif *netif); -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); - -/* receive, unfold, parse and free incoming messages */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); - -/* set the DHCP timers */ -static void dhcp_timeout(struct netif *netif); -static void dhcp_t1_timeout(struct netif *netif); -static void dhcp_t2_timeout(struct netif *netif); - -/* build outgoing messages */ -/* create a DHCP message, fill in common headers */ -static err_t dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type); -/* free a DHCP request */ -static void dhcp_delete_msg(struct dhcp *dhcp); -/* add a DHCP option (type, then length in bytes) */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); -/* add option values */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); -static void dhcp_option_short(struct dhcp *dhcp, u16_t value); -static void dhcp_option_long(struct dhcp *dhcp, u32_t value); -#if LWIP_NETIF_HOSTNAME -static void dhcp_option_hostname(struct dhcp *dhcp, struct netif *netif); -#endif /* LWIP_NETIF_HOSTNAME */ -/* always add the DHCP options trailer to end and pad */ -static void dhcp_option_trailer(struct dhcp *dhcp); - -/** Ensure DHCP PCB is allocated and bound */ -static err_t -dhcp_inc_pcb_refcount(void) -{ - if (dhcp_pcb_refcount == 0) { - LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL); - - /* allocate UDP PCB */ - dhcp_pcb = udp_new(); - - if (dhcp_pcb == NULL) { - return ERR_MEM; - } - - ip_set_option(dhcp_pcb, SOF_BROADCAST); - - /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */ - udp_bind(dhcp_pcb, IP4_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp_pcb, IP4_ADDR_ANY, DHCP_SERVER_PORT); - udp_recv(dhcp_pcb, dhcp_recv, NULL); - } - - dhcp_pcb_refcount++; - - return ERR_OK; -} - -/** Free DHCP PCB if the last netif stops using it */ -static void -dhcp_dec_pcb_refcount(void) -{ - LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0)); - dhcp_pcb_refcount--; - - if (dhcp_pcb_refcount == 0) { - udp_remove(dhcp_pcb); - dhcp_pcb = NULL; - } -} - -/** - * Back-off the DHCP client (because of a received NAK response). - * - * Back-off the DHCP client because of a received NAK. Receiving a - * NAK means the client asked for something non-sensible, for - * example when it tries to renew a lease obtained on another network. - * - * We clear any existing set IP address and restart DHCP negotiation - * afresh (as per RFC2131 3.2.3). - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_nak(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - /* Change to a defined state - set this before assigning the address - to ensure the callback can use dhcp_supplied_address() */ - dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); - /* remove IP address from interface (must no longer be used, as per RFC2131) */ - netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); - /* We can immediately restart discovery */ - dhcp_discover(netif); -} - -#if DHCP_DOES_ARP_CHECK -/** - * Checks if the offered IP address is already in use. - * - * It does so by sending an ARP request for the offered address and - * entering CHECKING state. If no ARP reply is received within a small - * interval, the address is assumed to be free for use by us. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_check(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], - (s16_t)netif->name[1])); - dhcp_set_state(dhcp, DHCP_STATE_CHECKING); - /* create an ARP query for the offered IP address, expecting that no host - responds, as the IP address should not be in use. */ - result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); - if (result != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - msecs = 500; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); -} -#endif /* DHCP_DOES_ARP_CHECK */ - -/** - * Remember the configuration offered by a DHCP server. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_offer(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - /* obtain the server address */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) { - ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID))); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", - ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); - /* remember offered address */ - ip4_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", - ip4_addr_get_u32(&dhcp->offered_ip_addr))); - - dhcp_select(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void*)netif)); - } -} - -/** - * Select a DHCP server offer out of all offers. - * - * Simply select the first offer received. - * - * @param netif the netif under DHCP control - * @return lwIP specific error (see error.h) - */ -static err_t -dhcp_select(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - u16_t msecs; - u8_t i; - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - dhcp_set_state(dhcp, DHCP_STATE_REQUESTING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - /* MUST request the offered IP address */ - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); - for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { - dhcp_option_byte(dhcp, dhcp_discover_request_options[i]); - } - -#if LWIP_NETIF_HOSTNAME - dhcp_option_hostname(dhcp, netif); -#endif /* LWIP_NETIF_HOSTNAME */ - - dhcp_option_trailer(dhcp); - /* shrink the pbuf to the actual content length */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* send broadcast to any DHCP server */ - udp_sendto_if_src(dhcp_pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP4_ADDR_ANY); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * The DHCP timer that checks for lease renewal/rebind timeouts. - * Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS). - */ -void -dhcp_coarse_tmr(void) -{ - struct netif *netif = netif_list; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n")); - /* iterate through all network interfaces */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - struct dhcp *dhcp = netif_dhcp_data(netif); - if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) { - /* compare lease time to expire timeout */ - if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n")); - /* this clients' lease time has expired */ - dhcp_release(netif); - dhcp_discover(netif); - /* timer is active (non zero), and triggers (zeroes) now? */ - } else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); - /* this clients' rebind timeout triggered */ - dhcp_t2_timeout(netif); - /* timer is active (non zero), and triggers (zeroes) now */ - } else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); - /* this clients' renewal timeout triggered */ - dhcp_t1_timeout(netif); - } - } - /* proceed to next netif */ - netif = netif->next; - } -} - -/** - * DHCP transaction timeout handling (this function must be called every 500ms, - * see @ref DHCP_FINE_TIMER_MSECS). - * - * A DHCP server is expected to respond within a short period of time. - * This timer checks whether an outstanding DHCP request is timed out. - */ -void -dhcp_fine_tmr(void) -{ - struct netif *netif = netif_list; - /* loop through netif's */ - while (netif != NULL) { - struct dhcp *dhcp = netif_dhcp_data(netif); - /* only act on DHCP configured interfaces */ - if (dhcp != NULL) { - /* timer is active (non zero), and is about to trigger now */ - if (dhcp->request_timeout > 1) { - dhcp->request_timeout--; - } - else if (dhcp->request_timeout == 1) { - dhcp->request_timeout--; - /* { netif->dhcp->request_timeout == 0 } */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); - /* this client's request timeout triggered */ - dhcp_timeout(netif); - } - } - /* proceed to next network interface */ - netif = netif->next; - } -} - -/** - * A DHCP negotiation transaction, or ARP request, has timed out. - * - * The timer that was started with the DHCP or ARP request has - * timed out, indicating no response was received in time. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n")); - /* back-off period has passed, or server selection timed out */ - if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); - dhcp_discover(netif); - /* receiving the requested lease timed out */ - } else if (dhcp->state == DHCP_STATE_REQUESTING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); - if (dhcp->tries <= 5) { - dhcp_select(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); - dhcp_release(netif); - dhcp_discover(netif); - } -#if DHCP_DOES_ARP_CHECK - /* received no ARP reply for the offered address (which is good) */ - } else if (dhcp->state == DHCP_STATE_CHECKING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); - if (dhcp->tries <= 1) { - dhcp_check(netif); - /* no ARP replies on the offered address, - looks like the IP address is indeed free */ - } else { - /* bind the interface to the offered address */ - dhcp_bind(netif); - } -#endif /* DHCP_DOES_ARP_CHECK */ - } else if (dhcp->state == DHCP_STATE_REBOOTING) { - if (dhcp->tries < REBOOT_TRIES) { - dhcp_reboot(netif); - } else { - dhcp_discover(netif); - } - } -} - -/** - * The renewal period has timed out. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_t1_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n")); - if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || - (dhcp->state == DHCP_STATE_RENEWING)) { - /* just retry to renew - note that the rebind timer (t2) will - * eventually time-out if renew tries fail. */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("dhcp_t1_timeout(): must renew\n")); - /* This slightly different to RFC2131: DHCPREQUEST will be sent from state - DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */ - dhcp_renew(netif); - /* Calculate next timeout */ - if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) - { - dhcp->t1_renew_time = ((dhcp->t2_timeout - dhcp->lease_used) / 2); - } - } -} - -/** - * The rebind period has timed out. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_t2_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n")); - if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || - (dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) { - /* just retry to rebind */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("dhcp_t2_timeout(): must rebind\n")); - /* This slightly different to RFC2131: DHCPREQUEST will be sent from state - DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */ - dhcp_rebind(netif); - /* Calculate next timeout */ - if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) - { - dhcp->t2_rebind_time = ((dhcp->t0_timeout - dhcp->lease_used) / 2); - } - } -} - -/** - * Handle a DHCP ACK packet - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_ack(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - -#if LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV - u8_t n; -#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV */ -#if LWIP_DHCP_GET_NTP_SRV - ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS]; -#endif - - /* clear options we might not get from the ACK */ - ip4_addr_set_zero(&dhcp->offered_sn_mask); - ip4_addr_set_zero(&dhcp->offered_gw_addr); -#if LWIP_DHCP_BOOTP_FILE - ip4_addr_set_zero(&dhcp->offered_si_addr); -#endif /* LWIP_DHCP_BOOTP_FILE */ - - /* lease time given? */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) { - /* remember offered lease time */ - dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME); - } - /* renewal period given? */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) { - /* remember given renewal period */ - dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1); - } else { - /* calculate safe periods for renewal */ - dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; - } - - /* renewal period given? */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) { - /* remember given rebind period */ - dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2); - } else { - /* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/ - dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U; - } - - /* (y)our internet address */ - ip4_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr); - -#if LWIP_DHCP_BOOTP_FILE - /* copy boot server address, - boot file name copied in dhcp_parse_reply if not overloaded */ - ip4_addr_copy(dhcp->offered_si_addr, dhcp->msg_in->siaddr); -#endif /* LWIP_DHCP_BOOTP_FILE */ - - /* subnet mask given? */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) { - /* remember given subnet mask */ - ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK))); - dhcp->subnet_mask_given = 1; - } else { - dhcp->subnet_mask_given = 0; - } - - /* gateway router */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) { - ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER))); - } - -#if LWIP_DHCP_GET_NTP_SRV - /* NTP servers */ - for (n = 0; (n < LWIP_DHCP_MAX_NTP_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n); n++) { - ip4_addr_set_u32(&ntp_server_addrs[n], lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n))); - } - dhcp_set_ntp_servers(n, ntp_server_addrs); -#endif /* LWIP_DHCP_GET_NTP_SRV */ - -#if LWIP_DHCP_PROVIDE_DNS_SERVERS - /* DNS servers */ - for (n = 0; (n < LWIP_DHCP_PROVIDE_DNS_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) - { - ip_addr_t dns_addr; - ip_addr_set_ip4_u32(&dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n))); - dns_setserver(n, &dns_addr); - } -#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ -} - -/** - * @ingroup dhcp4 - * Set a statically allocated struct dhcp to work with. - * Using this prevents dhcp_start to allocate it using mem_malloc. - * - * @param netif the netif for which to set the struct dhcp - * @param dhcp (uninitialised) dhcp struct allocated by the application - */ -void -dhcp_set_struct(struct netif *netif, struct dhcp *dhcp) -{ - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_ASSERT("dhcp != NULL", dhcp != NULL); - LWIP_ASSERT("netif already has a struct dhcp set", netif_dhcp_data(netif) == NULL); - - /* clear data structure */ - memset(dhcp, 0, sizeof(struct dhcp)); - /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */ - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp); -} - -/** - * @ingroup dhcp4 - * Removes a struct dhcp from a netif. - * - * ATTENTION: Only use this when not using dhcp_set_struct() to allocate the - * struct dhcp since the memory is passed back to the heap. - * - * @param netif the netif from which to remove the struct dhcp - */ -void dhcp_cleanup(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", netif != NULL); - - if (netif_dhcp_data(netif) != NULL) { - mem_free(netif_dhcp_data(netif)); - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL); - } -} - -void dhcp_check_status(void) -{ - struct netif *netif = netif_list; - - while (netif != NULL) { - struct dhcp *dhcp = netif_dhcp_data(netif); - if(dhcp != NULL){ - if(dhcp->state != DHCP_STATE_BOUND){ - bk_wlan_connection_loss(); - } - } - netif = netif->next; - } -} - -void dhcp_stop_timeout_check(void) -{ - OSStatus ret = kNoErr; - - if(rtos_is_oneshot_timer_init(&dhcp_tmr)) - { - if (rtos_is_oneshot_timer_running(&dhcp_tmr)) - { - ret = rtos_stop_oneshot_timer(&dhcp_tmr); - ASSERT(kNoErr == ret); - } - - ret = rtos_deinit_oneshot_timer(&dhcp_tmr); - ASSERT(kNoErr == ret); - } -} - -void dhcp_start_timeout_check(u32_t secs, u32_t usecs) -{ - OSStatus err = kNoErr; - u32_t clk_time; - - clk_time = (secs * 1000 + usecs / 1000 ); - - if(rtos_is_oneshot_timer_init(&dhcp_tmr)) - { - os_printf("dhcp_check_status_reload_timer\r\n\r\n"); - rtos_oneshot_reload_timer(&dhcp_tmr); - } - else - { - err = rtos_init_oneshot_timer(&dhcp_tmr, - clk_time, - (timer_2handler_t)dhcp_check_status, - NULL, - NULL); - ASSERT(kNoErr == err); - - err = rtos_start_oneshot_timer(&dhcp_tmr); - ASSERT(kNoErr == err); - os_printf("\r\ndhcp_check_status_init_timer:%d\r\n", clk_time); - } - - return; -} - -/** - * @ingroup dhcp4 - * Start DHCP negotiation for a network interface. - * - * If no DHCP client instance was attached to this interface, - * a new client is created first. If a DHCP client instance - * was already present, it restarts negotiation. - * - * @param netif The lwIP network interface - * @return lwIP error code - * - ERR_OK - No error - * - ERR_MEM - Out of memory - */ -err_t -dhcp_start(struct netif *netif) -{ - struct dhcp *dhcp; - err_t result; - - /*if dhcp can't get IP, will rescan after 10 seconds.*/ - dhcp_start_timeout_check(20, 0); - - LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;); - LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;); - dhcp = netif_dhcp_data(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* check MTU of the netif */ - if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n")); - return ERR_MEM; - } - - /* no DHCP client attached yet? */ - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); - dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); - return ERR_MEM; - } - - /* store this dhcp client in the netif */ - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp")); - /* already has DHCP client attached */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n")); - LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL); - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL ); - - if (dhcp->pcb_allocated != 0) { - dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ - } - /* dhcp is cleared below, no need to reset flag*/ - } - - /* clear data structure */ - memset(dhcp, 0, sizeof(struct dhcp)); - /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */ - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); - - if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */ - return ERR_MEM; - } - dhcp->pcb_allocated = 1; - -#if LWIP_DHCP_CHECK_LINK_UP - if (!netif_is_link_up(netif)) { - /* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */ - dhcp_set_state(dhcp, DHCP_STATE_INIT); - return ERR_OK; - } -#endif /* LWIP_DHCP_CHECK_LINK_UP */ - -#if CFG_ROLE_LAUNCH - if(rl_pre_sta_set_status(RL_STATUS_STA_DHCPING)) - { - return -1; - } -#endif - - /* (re)start the DHCP negotiation */ - result = dhcp_discover(netif); - if (result != ERR_OK) { - /* free resources allocated above */ - dhcp_stop(netif); - return ERR_MEM; - } - - return result; -} - -/** - * @ingroup dhcp4 - * Inform a DHCP server of our manual configuration. - * - * This informs DHCP servers of our fixed IP address configuration - * by sending an INFORM message. It does not involve DHCP address - * configuration, it is just here to be nice to the network. - * - * @param netif The lwIP network interface - */ -void -dhcp_inform(struct netif *netif) -{ - struct dhcp dhcp; - err_t result = ERR_OK; - - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - - if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */ - return; - } - - memset(&dhcp, 0, sizeof(struct dhcp)); - dhcp_set_state(&dhcp, DHCP_STATE_INFORMING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, &dhcp, DHCP_INFORM); - if (result == ERR_OK) { - dhcp_option(&dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(&dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option_trailer(&dhcp); - - pbuf_realloc(dhcp.p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp.options_out_len); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n")); - - udp_sendto_if(dhcp_pcb, dhcp.p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - - dhcp_delete_msg(&dhcp); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n")); - } - - dhcp_dec_pcb_refcount(); /* delete DHCP PCB if not needed any more */ -} - -/** Handle a possible change in the network configuration. - * - * This enters the REBOOTING state to verify that the currently bound - * address is still valid. - */ -void -dhcp_network_changed(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - - if (!dhcp) - return; - switch (dhcp->state) { - case DHCP_STATE_REBINDING: - case DHCP_STATE_RENEWING: - case DHCP_STATE_BOUND: - case DHCP_STATE_REBOOTING: - dhcp->tries = 0; - dhcp_reboot(netif); - break; - case DHCP_STATE_OFF: - /* stay off */ - break; - default: - /* INIT/REQUESTING/CHECKING/BACKING_OFF restart with new 'rid' because the - state changes, SELECTING: continue with current 'rid' as we stay in the - same state */ -#if LWIP_DHCP_AUTOIP_COOP - if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { - autoip_stop(netif); - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - /* ensure we start with short timeouts, even if already discovering */ - dhcp->tries = 0; - dhcp_discover(netif); - break; - } -} - -#if DHCP_DOES_ARP_CHECK -/** - * Match an ARP reply with the offered IP address: - * check whether the offered IP address is not in use using ARP - * - * @param netif the network interface on which the reply was received - * @param addr The IP address we received a reply from - */ -void -dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr) -{ - struct dhcp *dhcp; - - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - dhcp = netif_dhcp_data(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n")); - /* is a DHCP client doing an ARP check? */ - if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", - ip4_addr_get_u32(addr))); - /* did a host respond with the address we - were offered by the DHCP server? */ - if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) { - /* we will not accept the offered address */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, - ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); - dhcp_decline(netif); - } - } -} - -/** - * Decline an offered lease. - * - * Tell the DHCP server we do not accept the offered address. - * One reason to decline the lease is when we find out the address - * is already in use by another host (through ARP). - * - * @param netif the netif under DHCP control - */ -static err_t -dhcp_decline(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n")); - dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_DECLINE); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); - - dhcp_option_trailer(dhcp); - /* resize pbuf to reflect true size of options */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* per section 4.4.4, broadcast DECLINE messages */ - udp_sendto_if_src(dhcp_pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP4_ADDR_ANY); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_decline: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - msecs = 10*1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} -#endif /* DHCP_DOES_ARP_CHECK */ - - -/** - * Start the DHCP process, discover a DHCP server. - * - * @param netif the netif under DHCP control - */ -static err_t -dhcp_discover(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result = ERR_OK; - u16_t msecs; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n")); - ip4_addr_set_any(&dhcp->offered_ip_addr); - dhcp_set_state(dhcp, DHCP_STATE_SELECTING); - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER); - if (result == ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n")); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); - for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { - dhcp_option_byte(dhcp, dhcp_discover_request_options[i]); - } - -#if LWIP_NETIF_HOSTNAME - dhcp_option_hostname(dhcp, netif); -#endif /* LWIP_NETIF_HOSTNAME */ - - dhcp_option_trailer(dhcp); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n")); - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); - udp_sendto_if_src(dhcp_pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP4_ADDR_ANY); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n")); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } -#if LWIP_DHCP_AUTOIP_COOP - if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) { - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON; - autoip_start(netif); - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); - - return result; -} - - -/** - * Bind the interface to the offered IP address. - * - * @param netif network interface to bind to the offered address - */ -static void -dhcp_bind(struct netif *netif) -{ - u32_t timeout; - struct dhcp *dhcp; - ip4_addr_t sn_mask, gw_addr; - LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;); - dhcp = netif_dhcp_data(netif); - LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* reset time used of lease */ - dhcp->lease_used = 0; - - if (dhcp->offered_t0_lease != 0xffffffffUL) { - /* set renewal period timer */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease)); - timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (timeout > 0xffff) { - timeout = 0xffff; - } - dhcp->t0_timeout = (u16_t)timeout; - if (dhcp->t0_timeout == 0) { - dhcp->t0_timeout = 1; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease*1000)); - } - - /* temporary DHCP lease? */ - if (dhcp->offered_t1_renew != 0xffffffffUL) { - /* set renewal period timer */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); - timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (timeout > 0xffff) { - timeout = 0xffff; - } - dhcp->t1_timeout = (u16_t)timeout; - if (dhcp->t1_timeout == 0) { - dhcp->t1_timeout = 1; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); - dhcp->t1_renew_time = dhcp->t1_timeout; - } - /* set renewal period timer */ - if (dhcp->offered_t2_rebind != 0xffffffffUL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); - timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (timeout > 0xffff) { - timeout = 0xffff; - } - dhcp->t2_timeout = (u16_t)timeout; - if (dhcp->t2_timeout == 0) { - dhcp->t2_timeout = 1; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); - dhcp->t2_rebind_time = dhcp->t2_timeout; - } - - /* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */ - if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) { - dhcp->t1_timeout = 0; - } - - if (dhcp->subnet_mask_given) { - /* copy offered network mask */ - ip4_addr_copy(sn_mask, dhcp->offered_sn_mask); - } else { - /* subnet mask not given, choose a safe subnet mask given the network class */ - u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr); - if (first_octet <= 127) { - ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL)); - } else if (first_octet >= 192) { - ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL)); - } else { - ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL)); - } - } - - ip4_addr_copy(gw_addr, dhcp->offered_gw_addr); - /* gateway address not given? */ - if (ip4_addr_isany_val(gw_addr)) { - /* copy network address */ - ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask); - /* use first host address on network as gateway */ - ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL)); - } - -#if LWIP_DHCP_AUTOIP_COOP - if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { - autoip_stop(netif); - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n", - ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr))); - /* netif is now bound to DHCP leased address - set this before assigning the address - to ensure the callback can use dhcp_supplied_address() */ - dhcp_set_state(dhcp, DHCP_STATE_BOUND); - - dhcp_stop_timeout_check(); - - netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr); - /* interface is used by routing now that an address is set */ -} - -/** - * @ingroup dhcp4 - * Renew an existing DHCP lease at the involved DHCP server. - * - * @param netif network interface which must renew its lease - */ -err_t -dhcp_renew(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - u16_t msecs; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n")); - dhcp_set_state(dhcp, DHCP_STATE_RENEWING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); - for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { - dhcp_option_byte(dhcp, dhcp_discover_request_options[i]); - } - -#if LWIP_NETIF_HOSTNAME - dhcp_option_hostname(dhcp, netif); -#endif /* LWIP_NETIF_HOSTNAME */ - - /* append DHCP message trailer */ - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_sendto_if(dhcp_pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif); - dhcp_delete_msg(dhcp); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - /* back-off on retries, but to a maximum of 20 seconds */ - msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Rebind with a DHCP server for an existing DHCP lease. - * - * @param netif network interface which must rebind with a DHCP server - */ -static err_t -dhcp_rebind(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - u16_t msecs; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n")); - dhcp_set_state(dhcp, DHCP_STATE_REBINDING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); - for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { - dhcp_option_byte(dhcp, dhcp_discover_request_options[i]); - } - -#if LWIP_NETIF_HOSTNAME - dhcp_option_hostname(dhcp, netif); -#endif /* LWIP_NETIF_HOSTNAME */ - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* broadcast to server */ - udp_sendto_if(dhcp_pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Enter REBOOTING state to verify an existing lease - * - * @param netif network interface which must reboot - */ -static err_t -dhcp_reboot(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - u16_t msecs; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n")); - dhcp_set_state(dhcp, DHCP_STATE_REBOOTING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN_MIN_REQUIRED); - - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); - for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { - dhcp_option_byte(dhcp, dhcp_discover_request_options[i]); - } - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* broadcast to server */ - udp_sendto_if(dhcp_pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n")); - } - if (dhcp->tries < 255) { - dhcp->tries++; - } - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - - -/** - * @ingroup dhcp4 - * Release a DHCP lease (usually called before @ref dhcp_stop). - * - * @param netif network interface which must release its lease - */ -err_t -dhcp_release(struct netif *netif) -{ - struct dhcp *dhcp = netif_dhcp_data(netif); - err_t result; - ip_addr_t server_ip_addr; - u8_t is_dhcp_supplied_address; - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n")); - if (dhcp == NULL) { - return ERR_ARG; - } - ip_addr_copy(server_ip_addr, dhcp->server_ip_addr); - - is_dhcp_supplied_address = dhcp_supplied_address(netif); - - /* idle DHCP client */ - dhcp_set_state(dhcp, DHCP_STATE_OFF); - /* clean old DHCP offer */ - ip_addr_set_zero_ip4(&dhcp->server_ip_addr); - ip4_addr_set_zero(&dhcp->offered_ip_addr); - ip4_addr_set_zero(&dhcp->offered_sn_mask); - ip4_addr_set_zero(&dhcp->offered_gw_addr); -#if LWIP_DHCP_BOOTP_FILE - ip4_addr_set_zero(&dhcp->offered_si_addr); -#endif /* LWIP_DHCP_BOOTP_FILE */ - dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; - dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0; - - if (!is_dhcp_supplied_address) { - /* don't issue release message when address is not dhcp-assigned */ - return ERR_OK; - } - - /* create and initialize the DHCP message header */ - result = dhcp_create_msg(netif, dhcp, DHCP_RELEASE); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr)))); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_sendto_if(dhcp_pcb, dhcp->p_out, &server_ip_addr, DHCP_SERVER_PORT, netif); - dhcp_delete_msg(dhcp); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_STATE_OFF\n")); - } else { - /* sending release failed, but that's not a problem since the correct behaviour of dhcp does not rely on release */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n")); - } - /* remove IP address from interface (prevents routing from selecting this interface) */ - netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); - - return result; -} - -/** - * @ingroup dhcp4 - * Remove the DHCP client from the interface. - * - * @param netif The network interface to stop DHCP on - */ -void -dhcp_stop(struct netif *netif) -{ - struct dhcp *dhcp; - LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;); - dhcp = netif_dhcp_data(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n")); - /* netif is DHCP configured? */ - if (dhcp != NULL) { -#if LWIP_DHCP_AUTOIP_COOP - if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { - autoip_stop(netif); - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL); - dhcp_set_state(dhcp, DHCP_STATE_OFF); - - if (dhcp->pcb_allocated != 0) { - dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ - dhcp->pcb_allocated = 0; - } - } - - dhcp_cleanup(netif); - - dhcp_stop_timeout_check(); -} - -/* - * Set the DHCP state of a DHCP client. - * - * If the state changed, reset the number of tries. - */ -static void -dhcp_set_state(struct dhcp *dhcp, u8_t new_state) -{ - if (new_state != dhcp->state) { - dhcp->state = new_state; - dhcp->tries = 0; - dhcp->request_timeout = 0; - } -} - -/* - * Concatenate an option type and length field to the outgoing - * DHCP message. - * - */ -static void -dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) -{ - LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = option_type; - dhcp->msg_out->options[dhcp->options_out_len++] = option_len; -} -/* - * Concatenate a single byte to the outgoing DHCP message. - * - */ -static void -dhcp_option_byte(struct dhcp *dhcp, u8_t value) -{ - LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = value; -} - -static void -dhcp_option_short(struct dhcp *dhcp, u16_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU); -} - -static void -dhcp_option_long(struct dhcp *dhcp, u32_t value) -{ - LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL)); -} - -#if LWIP_NETIF_HOSTNAME -static void -dhcp_option_hostname(struct dhcp *dhcp, struct netif *netif) -{ - if (netif->hostname != NULL) { - size_t namelen = strlen(netif->hostname); - if (namelen > 0) { - size_t len; - const char *p = netif->hostname; - /* Shrink len to available bytes (need 2 bytes for OPTION_HOSTNAME - and 1 byte for trailer) */ - size_t available = DHCP_OPTIONS_LEN - dhcp->options_out_len - 3; - LWIP_ASSERT("DHCP: hostname is too long!", namelen <= available); - len = LWIP_MIN(namelen, available); - LWIP_ASSERT("DHCP: hostname is too long!", len <= 0xFF); - dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, (u8_t)len); - while (len--) { - dhcp_option_byte(dhcp, *p++); - } - } - } -} -#endif /* LWIP_NETIF_HOSTNAME */ - -/** - * Extract the DHCP message and the DHCP options. - * - * Extract the DHCP message and the DHCP options, each into a contiguous - * piece of memory. As a DHCP message is variable sized by its options, - * and also allows overriding some fields for options, the easy approach - * is to first unfold the options into a contiguous piece of memory, and - * use that further on. - * - */ -static err_t -dhcp_parse_reply(struct dhcp *dhcp, struct pbuf *p) -{ - u8_t *options; - u16_t offset; - u16_t offset_max; - u16_t options_idx; - u16_t options_idx_max; - struct pbuf *q; - int parse_file_as_options = 0; - int parse_sname_as_options = 0; - - /* clear received options */ - dhcp_clear_all_options(dhcp); - /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */ - if (p->len < DHCP_SNAME_OFS) { - return ERR_BUF; - } - dhcp->msg_in = (struct dhcp_msg *)p->payload; -#if LWIP_DHCP_BOOTP_FILE - /* clear boot file name */ - dhcp->boot_file_name[0] = 0; -#endif /* LWIP_DHCP_BOOTP_FILE */ - - /* parse options */ - - /* start with options field */ - options_idx = DHCP_OPTIONS_OFS; - /* parse options to the end of the received packet */ - options_idx_max = p->tot_len; -again: - q = p; - while ((q != NULL) && (options_idx >= q->len)) { - options_idx -= q->len; - options_idx_max -= q->len; - q = q->next; - } - if (q == NULL) { - return ERR_BUF; - } - offset = options_idx; - offset_max = options_idx_max; - options = (u8_t*)q->payload; - /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ - while ((q != NULL) && (options[offset] != DHCP_OPTION_END) && (offset < offset_max)) { - u8_t op = options[offset]; - u8_t len; - u8_t decode_len = 0; - int decode_idx = -1; - u16_t val_offset = offset + 2; - /* len byte might be in the next pbuf */ - if ((offset + 1) < q->len) { - len = options[offset + 1]; - } else { - len = (q->next != NULL ? ((u8_t*)q->next->payload)[0] : 0); - } - /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ - decode_len = len; - switch(op) { - /* case(DHCP_OPTION_END): handled above */ - case(DHCP_OPTION_PAD): - /* special option: no len encoded */ - decode_len = len = 0; - /* will be increased below */ - offset--; - break; - case(DHCP_OPTION_SUBNET_MASK): - LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_SUBNET_MASK; - break; - case(DHCP_OPTION_ROUTER): - decode_len = 4; /* only copy the first given router */ - LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_ROUTER; - break; -#if LWIP_DHCP_PROVIDE_DNS_SERVERS - case(DHCP_OPTION_DNS_SERVER): - /* special case: there might be more than one server */ - LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;); - /* limit number of DNS servers */ - decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS); - LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_DNS_SERVER; - break; -#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ - case(DHCP_OPTION_LEASE_TIME): - LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_LEASE_TIME; - break; -#if LWIP_DHCP_GET_NTP_SRV - case(DHCP_OPTION_NTP): - /* special case: there might be more than one server */ - LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;); - /* limit number of NTP servers */ - decode_len = LWIP_MIN(len, 4 * LWIP_DHCP_MAX_NTP_SERVERS); - LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_NTP_SERVER; - break; -#endif /* LWIP_DHCP_GET_NTP_SRV*/ - case(DHCP_OPTION_OVERLOAD): - LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); - /* decode overload only in options, not in file/sname: invalid packet */ - LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_OVERLOAD; - break; - case(DHCP_OPTION_MESSAGE_TYPE): - LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_MSG_TYPE; - break; - case(DHCP_OPTION_SERVER_ID): - LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_SERVER_ID; - break; - case(DHCP_OPTION_T1): - LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_T1; - break; - case(DHCP_OPTION_T2): - LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); - decode_idx = DHCP_OPTION_IDX_T2; - break; - default: - decode_len = 0; - LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op)); - break; - } - offset += len + 2; - if (decode_len > 0) { - u32_t value = 0; - u16_t copy_len; -decode_next: - LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX); - if (!dhcp_option_given(dhcp, decode_idx)) { - copy_len = LWIP_MIN(decode_len, 4); - if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) { - return ERR_BUF; - } - if (decode_len > 4) { - /* decode more than one u32_t */ - LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;); - dhcp_got_option(dhcp, decode_idx); - dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value)); - decode_len -= 4; - val_offset += 4; - decode_idx++; - goto decode_next; - } else if (decode_len == 4) { - value = lwip_ntohl(value); - } else { - LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;); - value = ((u8_t*)&value)[0]; - } - dhcp_got_option(dhcp, decode_idx); - dhcp_set_option_value(dhcp, decode_idx, value); - } - } - if (offset >= q->len) { - offset -= q->len; - offset_max -= q->len; - if ((offset < offset_max) && offset_max) { - q = q->next; - LWIP_ASSERT("next pbuf was null", q); - options = (u8_t*)q->payload; - } else { - /* We've run out of bytes, probably no end marker. Don't proceed. */ - break; - } - } - } - /* is this an overloaded message? */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) { - u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD); - dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD); - if (overload == DHCP_OVERLOAD_FILE) { - parse_file_as_options = 1; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n")); - } else if (overload == DHCP_OVERLOAD_SNAME) { - parse_sname_as_options = 1; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n")); - } else if (overload == DHCP_OVERLOAD_SNAME_FILE) { - parse_sname_as_options = 1; - parse_file_as_options = 1; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload)); - } -#if LWIP_DHCP_BOOTP_FILE - if (!parse_file_as_options) { - /* only do this for ACK messages */ - if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) && - (dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK)) - /* copy bootp file name, don't care for sname (server hostname) */ - if (pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS) != (DHCP_FILE_LEN-1)) { - return ERR_BUF; - } - /* make sure the string is really NULL-terminated */ - dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0; - } -#endif /* LWIP_DHCP_BOOTP_FILE */ - } - if (parse_file_as_options) { - /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */ - parse_file_as_options = 0; - options_idx = DHCP_FILE_OFS; - options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN; - goto again; - } else if (parse_sname_as_options) { - parse_sname_as_options = 0; - options_idx = DHCP_SNAME_OFS; - options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN; - goto again; - } - return ERR_OK; -} - -/** - * If an incoming DHCP message is in response to us, then trigger the state machine - */ -static void -dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) -{ - struct netif *netif = ip_current_input_netif(); - struct dhcp *dhcp = netif_dhcp_data(netif); - struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; - u8_t msg_type; - u8_t i; - - LWIP_UNUSED_ARG(arg); - - /* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */ - if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) { - goto free_pbuf_and_return; - } - - LWIP_ASSERT("invalid server address type", IP_IS_V4(addr)); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, - ip4_addr1_16(ip_2_ip4(addr)), ip4_addr2_16(ip_2_ip4(addr)), ip4_addr3_16(ip_2_ip4(addr)), ip4_addr4_16(ip_2_ip4(addr)), port)); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); - /* prevent warnings about unused arguments */ - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(addr); - LWIP_UNUSED_ARG(port); - - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL); - - if (p->len < DHCP_MIN_REPLY_LEN) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n")); - goto free_pbuf_and_return; - } - - if (reply_msg->op != DHCP_BOOTREPLY) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); - goto free_pbuf_and_return; - } - /* iterate through hardware address and match against DHCP message */ - for (i = 0; i < netif->hwaddr_len && i < NETIF_MAX_HWADDR_LEN && i < DHCP_CHADDR_LEN; i++) { - if (netif->hwaddr[i] != reply_msg->chaddr[i]) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", - (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); - goto free_pbuf_and_return; - } - } - /* match transaction ID against what we expected */ - if (lwip_ntohl(reply_msg->xid) != dhcp->xid) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",lwip_ntohl(reply_msg->xid),dhcp->xid)); - goto free_pbuf_and_return; - } - /* option fields could be unfold? */ - if (dhcp_parse_reply(dhcp, p) != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("problem unfolding DHCP message - too short on memory?\n")); - goto free_pbuf_and_return; - } - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); - /* obtain pointer to DHCP message type */ - if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); - goto free_pbuf_and_return; - } - - /* read DHCP message type */ - msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE); - /* message type is DHCP ACK? */ - if (msg_type == DHCP_ACK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n")); - /* in requesting state? */ - if (dhcp->state == DHCP_STATE_REQUESTING) { - dhcp_handle_ack(netif); -#if DHCP_DOES_ARP_CHECK - if ((netif->flags & NETIF_FLAG_ETHARP) != 0) { - /* check if the acknowledged lease address is already in use */ - dhcp_check(netif); - } else { - /* bind interface to the acknowledged lease address */ - dhcp_bind(netif); - } -#else - /* bind interface to the acknowledged lease address */ - dhcp_bind(netif); -#endif - } - /* already bound to the given lease address? */ - else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) || - (dhcp->state == DHCP_STATE_RENEWING)) { - dhcp_handle_ack(netif); - dhcp_bind(netif); - } - } - /* received a DHCP_NAK in appropriate state? */ - else if ((msg_type == DHCP_NAK) && - ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) || - (dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n")); - dhcp_handle_nak(netif); - } - /* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */ - else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n")); - dhcp->request_timeout = 0; - /* remember offered lease */ - dhcp_handle_offer(netif); - } - -free_pbuf_and_return: - if (dhcp != NULL) { - dhcp->msg_in = NULL; - } - pbuf_free(p); -} - -/** - * Create a DHCP request, fill in common headers - * - * @param netif the netif under DHCP control - * @param dhcp dhcp control struct - * @param message_type message type of the request - */ -static err_t -dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type) -{ - u16_t i; -#ifndef DHCP_GLOBAL_XID - /** default global transaction identifier starting value (easy to match - * with a packet analyser). We simply increment for each new request. - * Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one - * at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */ -#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND) - static u32_t xid; -#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ - static u32_t xid = 0xABCD0000; -#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ -#else - if (!xid_initialised) { - xid = DHCP_GLOBAL_XID; - xid_initialised = !xid_initialised; - } -#endif - LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return ERR_ARG;); - LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return ERR_VAL;); - LWIP_ASSERT("dhcp_create_msg: dhcp->p_out == NULL", dhcp->p_out == NULL); - LWIP_ASSERT("dhcp_create_msg: dhcp->msg_out == NULL", dhcp->msg_out == NULL); - dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); - if (dhcp->p_out == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_create_msg(): could not allocate pbuf\n")); - return ERR_MEM; - } - LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg", - (dhcp->p_out->len >= sizeof(struct dhcp_msg))); - - /* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */ - if (message_type != DHCP_REQUEST) { - /* reuse transaction identifier in retransmissions */ - if (dhcp->tries == 0) { -#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND) - xid = LWIP_RAND(); -#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ - xid++; -#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ - } - dhcp->xid = xid; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, - ("transaction id xid(%"X32_F")\n", xid)); - - dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; - - dhcp->msg_out->op = DHCP_BOOTREQUEST; - /* @todo: make link layer independent */ - dhcp->msg_out->htype = DHCP_HTYPE_ETH; - dhcp->msg_out->hlen = netif->hwaddr_len; - dhcp->msg_out->hops = 0; - dhcp->msg_out->xid = lwip_htonl(dhcp->xid); - dhcp->msg_out->secs = 0; - /* we don't need the broadcast flag since we can receive unicast traffic - before being fully configured! */ - dhcp->msg_out->flags = 0; - ip4_addr_set_zero(&dhcp->msg_out->ciaddr); - /* set ciaddr to netif->ip_addr based on message_type and state */ - if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) || - ((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */ - ((dhcp->state== DHCP_STATE_RENEWING) || dhcp->state== DHCP_STATE_REBINDING))) { - ip4_addr_copy(dhcp->msg_out->ciaddr, *netif_ip4_addr(netif)); - } - ip4_addr_set_zero(&dhcp->msg_out->yiaddr); - ip4_addr_set_zero(&dhcp->msg_out->siaddr); - ip4_addr_set_zero(&dhcp->msg_out->giaddr); - for (i = 0; i < DHCP_CHADDR_LEN; i++) { - /* copy netif hardware address, pad with zeroes */ - dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len && i < NETIF_MAX_HWADDR_LEN) ? netif->hwaddr[i] : 0/* pad byte*/; - } - for (i = 0; i < DHCP_SNAME_LEN; i++) { - dhcp->msg_out->sname[i] = 0; - } - for (i = 0; i < DHCP_FILE_LEN; i++) { - dhcp->msg_out->file[i] = 0; - } - dhcp->msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE); - dhcp->options_out_len = 0; - /* fill options field with an incrementing array (for debugging purposes) */ - for (i = 0; i < DHCP_OPTIONS_LEN; i++) { - dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */ - } - /* Add option MESSAGE_TYPE */ - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, message_type); - return ERR_OK; -} - -/** - * Free previously allocated memory used to send a DHCP request. - * - * @param dhcp the dhcp struct to free the request from - */ -static void -dhcp_delete_msg(struct dhcp *dhcp) -{ - LWIP_ERROR("dhcp_delete_msg: dhcp != NULL", (dhcp != NULL), return;); - LWIP_ASSERT("dhcp_delete_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); - LWIP_ASSERT("dhcp_delete_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); - if (dhcp->p_out != NULL) { - pbuf_free(dhcp->p_out); - } - dhcp->p_out = NULL; - dhcp->msg_out = NULL; -} - -/** - * Add a DHCP message trailer - * - * Adds the END option to the DHCP message, and if - * necessary, up to three padding bytes. - * - * @param dhcp DHCP state structure - */ -static void -dhcp_option_trailer(struct dhcp *dhcp) -{ - LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;); - LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; - /* packet is too small, or not 4 byte aligned? */ - while (((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) && - (dhcp->options_out_len < DHCP_OPTIONS_LEN)) { - /* add a fill/padding byte */ - dhcp->msg_out->options[dhcp->options_out_len++] = 0; - } -} - -/** check if DHCP supplied netif->ip_addr - * - * @param netif the netif to check - * @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING), - * 0 otherwise - */ -u8_t -dhcp_supplied_address(const struct netif *netif) -{ - if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) { - struct dhcp* dhcp = netif_dhcp_data(netif); - return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING); - } - return 0; -} - -#endif /* LWIP_IPV4 && LWIP_DHCP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/etharp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/etharp.c deleted file mode 100644 index 203156c7ed72836fd738692b2ffe47ca78a0c144..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/etharp.c +++ /dev/null @@ -1,1205 +0,0 @@ -/** - * @file - * Address Resolution Protocol module for IP over Ethernet - * - * Functionally, ARP is divided into two parts. The first maps an IP address - * to a physical address when sending a packet, and the second part answers - * requests from other machines for our physical address. - * - * This implementation complies with RFC 826 (Ethernet ARP). It supports - * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 - * if an interface calls etharp_gratuitous(our_netif) upon address change. - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" - -#if LWIP_ARP || LWIP_ETHERNET - -#include "lwip/etharp.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/dhcp.h" -#include "netif/ethernet.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */ - -/** Re-request a used ARP entry 1 minute before it would expire to prevent - * breaking a steadily used connection because the ARP entry timed out. */ -#define ARP_AGE_REREQUEST_USED_UNICAST (ARP_MAXAGE - 30) -#define ARP_AGE_REREQUEST_USED_BROADCAST (ARP_MAXAGE - 15) - -/** the time an ARP entry stays pending after first request, - * for ARP_TMR_INTERVAL = 1000, this is - * 10 seconds. - * - * @internal Keep this number at least 2, otherwise it might - * run out instantly if the timeout occurs directly after a request. - */ -#define ARP_MAXPENDING 5 - -/** ARP states */ -enum etharp_state { - ETHARP_STATE_EMPTY = 0, - ETHARP_STATE_PENDING, - ETHARP_STATE_STABLE, - ETHARP_STATE_STABLE_REREQUESTING_1, - ETHARP_STATE_STABLE_REREQUESTING_2 -#if ETHARP_SUPPORT_STATIC_ENTRIES - ,ETHARP_STATE_STATIC -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ -}; - -struct etharp_entry { -#if ARP_QUEUEING - /** Pointer to queue of pending outgoing packets on this ARP entry. */ - struct etharp_q_entry *q; -#else /* ARP_QUEUEING */ - /** Pointer to a single pending outgoing packet on this ARP entry. */ - struct pbuf *q; -#endif /* ARP_QUEUEING */ - ip4_addr_t ipaddr; - struct netif *netif; - struct eth_addr ethaddr; - u16_t ctime; - u8_t state; -}; - -static struct etharp_entry arp_table[ARP_TABLE_SIZE]; - -#if !LWIP_NETIF_HWADDRHINT -static u8_t etharp_cached_entry; -#endif /* !LWIP_NETIF_HWADDRHINT */ - -/** Try hard to create a new entry - we want the IP address to appear in - the cache (even if this means removing an active entry or so). */ -#define ETHARP_FLAG_TRY_HARD 1 -#define ETHARP_FLAG_FIND_ONLY 2 -#if ETHARP_SUPPORT_STATIC_ENTRIES -#define ETHARP_FLAG_STATIC_ENTRY 4 -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - -#if LWIP_NETIF_HWADDRHINT -#define ETHARP_SET_HINT(netif, hint) if (((netif) != NULL) && ((netif)->addr_hint != NULL)) \ - *((netif)->addr_hint) = (hint); -#else /* LWIP_NETIF_HWADDRHINT */ -#define ETHARP_SET_HINT(netif, hint) (etharp_cached_entry = (hint)) -#endif /* LWIP_NETIF_HWADDRHINT */ - - -/* Some checks, instead of etharp_init(): */ -#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) - #error "ARP_TABLE_SIZE must fit in an s8_t, you have to reduce it in your lwipopts.h" -#endif - - -static err_t etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr* hw_dst_addr); -static err_t etharp_raw(struct netif *netif, - const struct eth_addr *ethsrc_addr, const struct eth_addr *ethdst_addr, - const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, - const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, - const u16_t opcode); - -#if ARP_QUEUEING -/** - * Free a complete queue of etharp entries - * - * @param q a qeueue of etharp_q_entry's to free - */ -static void -free_etharp_q(struct etharp_q_entry *q) -{ - struct etharp_q_entry *r; - LWIP_ASSERT("q != NULL", q != NULL); - LWIP_ASSERT("q->p != NULL", q->p != NULL); - while (q) { - r = q; - q = q->next; - LWIP_ASSERT("r->p != NULL", (r->p != NULL)); - pbuf_free(r->p); - memp_free(MEMP_ARP_QUEUE, r); - } -} -#else /* ARP_QUEUEING */ - -/** Compatibility define: free the queued pbuf */ -#define free_etharp_q(q) pbuf_free(q) - -#endif /* ARP_QUEUEING */ - -/** Clean up ARP table entries */ -static void -etharp_free_entry(int i) -{ - /* remove from SNMP ARP index tree */ - mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr); - /* and empty packet queue */ - if (arp_table[i].q != NULL) { - /* remove all queued packets */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); - free_etharp_q(arp_table[i].q); - arp_table[i].q = NULL; - } - /* recycle entry for re-use */ - arp_table[i].state = ETHARP_STATE_EMPTY; -#ifdef LWIP_DEBUG - /* for debugging, clean out the complete entry */ - arp_table[i].ctime = 0; - arp_table[i].netif = NULL; - ip4_addr_set_zero(&arp_table[i].ipaddr); - arp_table[i].ethaddr = ethzero; -#endif /* LWIP_DEBUG */ -} - -/** - * Clears expired entries in the ARP table. - * - * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second), - * in order to expire entries in the ARP table. - */ -void -etharp_tmr(void) -{ - u8_t i; - - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); - /* remove expired entries from the ARP table */ - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - u8_t state = arp_table[i].state; - if (state != ETHARP_STATE_EMPTY -#if ETHARP_SUPPORT_STATIC_ENTRIES - && (state != ETHARP_STATE_STATIC) -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - ) { - arp_table[i].ctime++; - if ((arp_table[i].ctime >= ARP_MAXAGE) || - ((arp_table[i].state == ETHARP_STATE_PENDING) && - (arp_table[i].ctime >= ARP_MAXPENDING))) { - /* pending or stable entry has become old! */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n", - arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i)); - /* clean up entries that have just been expired */ - etharp_free_entry(i); - } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) { - /* Don't send more than one request every 2 seconds. */ - arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2; - } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) { - /* Reset state to stable, so that the next transmitted packet will - re-send an ARP request. */ - arp_table[i].state = ETHARP_STATE_STABLE; - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* still pending, resend an ARP query */ - etharp_request(arp_table[i].netif, &arp_table[i].ipaddr); - } - } - } -} - -/** - * Search the ARP table for a matching or new entry. - * - * If an IP address is given, return a pending or stable ARP entry that matches - * the address. If no match is found, create a new entry with this address set, - * but in state ETHARP_EMPTY. The caller must check and possibly change the - * state of the returned entry. - * - * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. - * - * In all cases, attempt to create new entries from an empty entry. If no - * empty entries are available and ETHARP_FLAG_TRY_HARD flag is set, recycle - * old entries. Heuristic choose the least important entry for recycling. - * - * @param ipaddr IP address to find in ARP cache, or to add if not found. - * @param flags See @ref etharp_state - * @param netif netif related to this address (used for NETIF_HWADDRHINT) - * - * @return The ARP entry index that matched or is created, ERR_MEM if no - * entry is found or could be recycled. - */ -static s8_t -etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif* netif) -{ - s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; - s8_t empty = ARP_TABLE_SIZE; - u8_t i = 0; - /* oldest entry with packets on queue */ - s8_t old_queue = ARP_TABLE_SIZE; - /* its age */ - u16_t age_queue = 0, age_pending = 0, age_stable = 0; - - LWIP_UNUSED_ARG(netif); - - /** - * a) do a search through the cache, remember candidates - * b) select candidate entry - * c) create new entry - */ - - /* a) in a single search sweep, do all of this - * 1) remember the first empty entry (if any) - * 2) remember the oldest stable entry (if any) - * 3) remember the oldest pending entry without queued packets (if any) - * 4) remember the oldest pending entry with queued packets (if any) - * 5) search for a matching IP entry, either pending or stable - * until 5 matches, or all entries are searched for. - */ - - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - u8_t state = arp_table[i].state; - /* no empty entry found yet and now we do find one? */ - if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %"U16_F"\n", (u16_t)i)); - /* remember first empty entry */ - empty = i; - } else if (state != ETHARP_STATE_EMPTY) { - LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE", - state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE); - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr) -#if ETHARP_TABLE_MATCH_NETIF - && ((netif == NULL) || (netif == arp_table[i].netif)) -#endif /* ETHARP_TABLE_MATCH_NETIF */ - ) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ - return i; - } - /* pending entry? */ - if (state == ETHARP_STATE_PENDING) { - /* pending with queued packets? */ - if (arp_table[i].q != NULL) { - if (arp_table[i].ctime >= age_queue) { - old_queue = i; - age_queue = arp_table[i].ctime; - } - } else - /* pending without queued packets? */ - { - if (arp_table[i].ctime >= age_pending) { - old_pending = i; - age_pending = arp_table[i].ctime; - } - } - /* stable entry? */ - } else if (state >= ETHARP_STATE_STABLE) { -#if ETHARP_SUPPORT_STATIC_ENTRIES - /* don't record old_stable for static entries since they never expire */ - if (state < ETHARP_STATE_STATIC) -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - { - /* remember entry with oldest stable entry in oldest, its age in maxtime */ - if (arp_table[i].ctime >= age_stable) { - old_stable = i; - age_stable = arp_table[i].ctime; - } - } - } - } - } - /* { we have no match } => try to create a new entry */ - - /* don't create new entry, only search? */ - if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || - /* or no empty entry found and not allowed to recycle? */ - ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n")); - return (s8_t)ERR_MEM; - } - - /* b) choose the least destructive entry to recycle: - * 1) empty entry - * 2) oldest stable entry - * 3) oldest pending entry without queued packets - * 4) oldest pending entry with queued packets - * - * { ETHARP_FLAG_TRY_HARD is set at this point } - */ - - /* 1) empty entry available? */ - if (empty < ARP_TABLE_SIZE) { - i = empty; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); - } else { - /* 2) found recyclable stable entry? */ - if (old_stable < ARP_TABLE_SIZE) { - /* recycle oldest stable*/ - i = old_stable; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); - /* no queued packets should exist on stable entries */ - LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); - /* 3) found recyclable pending entry without queued packets? */ - } else if (old_pending < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_pending; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); - /* 4) found recyclable pending entry with queued packets? */ - } else if (old_queue < ARP_TABLE_SIZE) { - /* recycle oldest pending (queued packets are free in etharp_free_entry) */ - i = old_queue; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q))); - /* no empty or recyclable entries found */ - } else { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n")); - return (s8_t)ERR_MEM; - } - - /* { empty or recyclable entry found } */ - LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); - etharp_free_entry(i); - } - - LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); - LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", - arp_table[i].state == ETHARP_STATE_EMPTY); - - /* IP address given? */ - if (ipaddr != NULL) { - /* set IP address */ - ip4_addr_copy(arp_table[i].ipaddr, *ipaddr); - } - arp_table[i].ctime = 0; -#if ETHARP_TABLE_MATCH_NETIF - arp_table[i].netif = netif; -#endif /* ETHARP_TABLE_MATCH_NETIF*/ - return (err_t)i; -} - -/** - * Update (or insert) a IP/MAC address pair in the ARP cache. - * - * If a pending entry is resolved, any queued packets will be sent - * at this point. - * - * @param netif netif related to this entry (used for NETIF_ADDRHINT) - * @param ipaddr IP address of the inserted ARP entry. - * @param ethaddr Ethernet address of the inserted ARP entry. - * @param flags See @ref etharp_state - * - * @return - * - ERR_OK Successfully updated ARP cache. - * - ERR_MEM If we could not add a new ARP entry when ETHARP_FLAG_TRY_HARD was set. - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - * @see pbuf_free() - */ -static err_t -etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) -{ - s8_t i; - LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", - ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), - (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], - (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); - /* non-unicast address? */ - if (ip4_addr_isany(ipaddr) || - ip4_addr_isbroadcast(ipaddr, netif) || - ip4_addr_ismulticast(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - /* find or create ARP entry */ - i = etharp_find_entry(ipaddr, flags, netif); - /* bail out if no entry could be found */ - if (i < 0) { - return (err_t)i; - } - -#if ETHARP_SUPPORT_STATIC_ENTRIES - if (flags & ETHARP_FLAG_STATIC_ENTRY) { - /* record static type */ - arp_table[i].state = ETHARP_STATE_STATIC; - } else if (arp_table[i].state == ETHARP_STATE_STATIC) { - /* found entry is a static type, don't overwrite it */ - return ERR_VAL; - } else -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - { - /* mark it stable */ - arp_table[i].state = ETHARP_STATE_STABLE; - } - - /* record network interface */ - arp_table[i].netif = netif; - /* insert in SNMP ARP index tree */ - mib2_add_arp_entry(netif, &arp_table[i].ipaddr); - - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); - /* update address */ - ETHADDR32_COPY(&arp_table[i].ethaddr, ethaddr); - /* reset time stamp */ - arp_table[i].ctime = 0; - /* this is where we will send out queued packets! */ -#if ARP_QUEUEING - while (arp_table[i].q != NULL) { - struct pbuf *p; - /* remember remainder of queue */ - struct etharp_q_entry *q = arp_table[i].q; - /* pop first item off the queue */ - arp_table[i].q = q->next; - /* get the packet pointer */ - p = q->p; - /* now queue entry can be freed */ - memp_free(MEMP_ARP_QUEUE, q); -#else /* ARP_QUEUEING */ - if (arp_table[i].q != NULL) { - struct pbuf *p = arp_table[i].q; - arp_table[i].q = NULL; -#endif /* ARP_QUEUEING */ - /* send the queued IP packet */ - ethernet_output(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr, ETHTYPE_IP); - /* free the queued IP packet */ - pbuf_free(p); - } - return ERR_OK; -} - -#if ETHARP_SUPPORT_STATIC_ENTRIES -/** Add a new static entry to the ARP table. If an entry exists for the - * specified IP address, this entry is overwritten. - * If packets are queued for the specified IP address, they are sent out. - * - * @param ipaddr IP address for the new static entry - * @param ethaddr ethernet address for the new static entry - * @return See return values of etharp_add_static_entry - */ -err_t -etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr) -{ - struct netif *netif; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_add_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", - ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), - (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], - (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); - - netif = ip4_route(ipaddr); - if (netif == NULL) { - return ERR_RTE; - } - - return etharp_update_arp_entry(netif, ipaddr, ethaddr, ETHARP_FLAG_TRY_HARD | ETHARP_FLAG_STATIC_ENTRY); -} - -/** Remove a static entry from the ARP table previously added with a call to - * etharp_add_static_entry. - * - * @param ipaddr IP address of the static entry to remove - * @return ERR_OK: entry removed - * ERR_MEM: entry wasn't found - * ERR_ARG: entry wasn't a static entry but a dynamic one - */ -err_t -etharp_remove_static_entry(const ip4_addr_t *ipaddr) -{ - s8_t i; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_remove_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); - - /* find or create ARP entry */ - i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, NULL); - /* bail out if no entry could be found */ - if (i < 0) { - return (err_t)i; - } - - if (arp_table[i].state != ETHARP_STATE_STATIC) { - /* entry wasn't a static entry, cannot remove it */ - return ERR_ARG; - } - /* entry found, free it */ - etharp_free_entry(i); - return ERR_OK; -} -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - -/** - * Remove all ARP table entries of the specified netif. - * - * @param netif points to a network interface - */ -void -etharp_cleanup_netif(struct netif *netif) -{ - u8_t i; - - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - u8_t state = arp_table[i].state; - if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) { - etharp_free_entry(i); - } - } -} - -/** - * Finds (stable) ethernet/IP address pair from ARP table - * using interface and IP address index. - * @note the addresses in the ARP table are in network order! - * - * @param netif points to interface index - * @param ipaddr points to the (network order) IP address index - * @param eth_ret points to return pointer - * @param ip_ret points to return pointer - * @return table index if found, -1 otherwise - */ -s8_t -etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr, - struct eth_addr **eth_ret, const ip4_addr_t **ip_ret) -{ - s8_t i; - - LWIP_ASSERT("eth_ret != NULL && ip_ret != NULL", - eth_ret != NULL && ip_ret != NULL); - - LWIP_UNUSED_ARG(netif); - - i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, netif); - if ((i >= 0) && (arp_table[i].state >= ETHARP_STATE_STABLE)) { - *eth_ret = &arp_table[i].ethaddr; - *ip_ret = &arp_table[i].ipaddr; - return i; - } - return -1; -} - -/** - * Possibility to iterate over stable ARP table entries - * - * @param i entry number, 0 to ARP_TABLE_SIZE - * @param ipaddr return value: IP address - * @param netif return value: points to interface - * @param eth_ret return value: ETH address - * @return 1 on valid index, 0 otherwise - */ -u8_t -etharp_get_entry(u8_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret) -{ - LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_ASSERT("eth_ret != NULL", eth_ret != NULL); - - if((i < ARP_TABLE_SIZE) && (arp_table[i].state >= ETHARP_STATE_STABLE)) { - *ipaddr = &arp_table[i].ipaddr; - *netif = arp_table[i].netif; - *eth_ret = &arp_table[i].ethaddr; - return 1; - } else { - return 0; - } -} - -/** - * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache - * send out queued IP packets. Updates cache with snooped address pairs. - * - * Should be called for incoming ARP packets. The pbuf in the argument - * is freed by this function. - * - * @param p The ARP packet that arrived on netif. Is freed by this function. - * @param netif The lwIP network interface on which the ARP packet pbuf arrived. - * - * @see pbuf_free() - */ -void -etharp_input(struct pbuf *p, struct netif *netif) -{ - struct etharp_hdr *hdr; - /* these are aligned properly, whereas the ARP header fields might not be */ - ip4_addr_t sipaddr, dipaddr; - u8_t for_us; - - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - - hdr = (struct etharp_hdr *)p->payload; - - /* RFC 826 "Packet Reception": */ - if ((hdr->hwtype != PP_HTONS(HWTYPE_ETHERNET)) || - (hdr->hwlen != ETH_HWADDR_LEN) || - (hdr->protolen != sizeof(ip4_addr_t)) || - (hdr->proto != PP_HTONS(ETHTYPE_IP))) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", - hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen)); - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - pbuf_free(p); - return; - } - ETHARP_STATS_INC(etharp.recv); - -#if LWIP_AUTOIP - /* We have to check if a host already has configured our random - * created link local address and continuously check if there is - * a host with this IP-address so we can detect collisions */ - autoip_arp_reply(netif, hdr); -#endif /* LWIP_AUTOIP */ - - /* Copy struct ip4_addr2 to aligned ip4_addr, to support compilers without - * structure packing (not using structure copy which breaks strict-aliasing rules). */ - IPADDR2_COPY(&sipaddr, &hdr->sipaddr); - IPADDR2_COPY(&dipaddr, &hdr->dipaddr); - - /* this interface is not configured? */ - if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { - for_us = 0; - } else { - /* ARP packet directed to us? */ - for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif)); - } - - /* ARP message directed to us? - -> add IP address in ARP cache; assume requester wants to talk to us, - can result in directly sending the queued packets for this host. - ARP message not directed to us? - -> update the source IP address in the cache, if present */ - etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), - for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); - - /* now act on the message itself */ - switch (hdr->opcode) { - /* ARP request? */ - case PP_HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - * reply. In any case, we time-stamp any existing ARP entry, - * and possibly send out an IP packet that was queued on it. */ - - LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP request\n")); - /* ARP request for our address? */ - if (for_us) { - /* send ARP response */ - etharp_raw(netif, - (struct eth_addr *)netif->hwaddr, &hdr->shwaddr, - (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), - &hdr->shwaddr, &sipaddr, - ARP_REPLY); - /* we are not configured? */ - } else if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { - /* { for_us == 0 and netif->ip_addr.addr == 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: we are unconfigured, ARP request ignored.\n")); - /* request was not directed to us */ - } else { - /* { for_us == 0 and netif->ip_addr.addr != 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP request was not for us.\n")); - } - break; - case PP_HTONS(ARP_REPLY): - /* ARP reply. We already updated the ARP cache earlier. */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP reply\n")); -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) - /* DHCP wants to know about ARP replies from any host with an - * IP address also offered to us by the DHCP server. We do not - * want to take a duplicate IP address on a single network. - * @todo How should we handle redundant (fail-over) interfaces? */ - dhcp_arp_reply(netif, &sipaddr); -#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ - break; - default: - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode))); - ETHARP_STATS_INC(etharp.err); - break; - } - /* free ARP packet */ - pbuf_free(p); -} - -/** Just a small helper function that sends a pbuf to an ethernet address - * in the arp_table specified by the index 'arp_idx'. - */ -static err_t -etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, u8_t arp_idx) -{ - LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE", - arp_table[arp_idx].state >= ETHARP_STATE_STABLE); - /* if arp table entry is about to expire: re-request it, - but only if its state is ETHARP_STATE_STABLE to prevent flooding the - network with ARP requests if this address is used frequently. */ - if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) { - if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) { - /* issue a standard request using broadcast */ - if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) { - arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; - } - } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) { - /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */ - if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) { - arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; - } - } - } - - return ethernet_output(netif, q, (struct eth_addr*)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP); -} - -/** - * Resolve and fill-in Ethernet address header for outgoing IP packet. - * - * For IP multicast and broadcast, corresponding Ethernet addresses - * are selected and the packet is transmitted on the link. - * - * For unicast addresses, the packet is submitted to etharp_query(). In - * case the IP address is outside the local network, the IP address of - * the gateway is used. - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param q The pbuf(s) containing the IP packet to be sent. - * @param ipaddr The IP address of the packet destination. - * - * @return - * - ERR_RTE No route to destination (no gateway to external networks), - * or the return type of either etharp_query() or ethernet_output(). - */ -err_t -etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) -{ - const struct eth_addr *dest; - struct eth_addr mcastaddr; - const ip4_addr_t *dst_addr = ipaddr; - - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_ASSERT("q != NULL", q != NULL); - LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); - - /* Determine on destination hardware address. Broadcasts and multicasts - * are special, other IP addresses are looked up in the ARP table. */ - - /* broadcast destination IP address? */ - if (ip4_addr_isbroadcast(ipaddr, netif)) { - /* broadcast on Ethernet also */ - dest = (const struct eth_addr *)ðbroadcast; - /* multicast destination IP address? */ - } else if (ip4_addr_ismulticast(ipaddr)) { - /* Hash IP multicast address to MAC address.*/ - mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0; - mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1; - mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2; - mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; - mcastaddr.addr[4] = ip4_addr3(ipaddr); - mcastaddr.addr[5] = ip4_addr4(ipaddr); - /* destination Ethernet address is multicast */ - dest = &mcastaddr; - /* unicast destination IP address? */ - } else { - s8_t i; - /* outside local network? if so, this can neither be a global broadcast nor - a subnet broadcast. */ - if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && - !ip4_addr_islinklocal(ipaddr)) { -#if LWIP_AUTOIP - struct ip_hdr *iphdr = LWIP_ALIGNMENT_CAST(struct ip_hdr*, q->payload); - /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with - a link-local source address must always be "directly to its destination - on the same physical link. The host MUST NOT send the packet to any - router for forwarding". */ - if (!ip4_addr_islinklocal(&iphdr->src)) -#endif /* LWIP_AUTOIP */ - { -#ifdef LWIP_HOOK_ETHARP_GET_GW - /* For advanced routing, a single default gateway might not be enough, so get - the IP address of the gateway to handle the current destination address. */ - dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr); - if (dst_addr == NULL) -#endif /* LWIP_HOOK_ETHARP_GET_GW */ - { - /* interface has default gateway? */ - if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) { - /* send to hardware address of default gateway IP address */ - dst_addr = netif_ip4_gw(netif); - /* no default gateway available */ - } else { - /* no route to destination error (default gateway missing) */ - return ERR_RTE; - } - } - } - } -#if LWIP_NETIF_HWADDRHINT - if (netif->addr_hint != NULL) { - /* per-pcb cached entry was given */ - u8_t etharp_cached_entry = *(netif->addr_hint); - if (etharp_cached_entry < ARP_TABLE_SIZE) { -#endif /* LWIP_NETIF_HWADDRHINT */ - if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && -#if ETHARP_TABLE_MATCH_NETIF - (arp_table[etharp_cached_entry].netif == netif) && -#endif - (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) { - /* the per-pcb-cached entry is stable and the right one! */ - ETHARP_STATS_INC(etharp.cachehit); - return etharp_output_to_arp_index(netif, q, etharp_cached_entry); - } -#if LWIP_NETIF_HWADDRHINT - } - } -#endif /* LWIP_NETIF_HWADDRHINT */ - - /* find stable entry: do this here since this is a critical path for - throughput and etharp_find_entry() is kind of slow */ - for (i = 0; i < ARP_TABLE_SIZE; i++) { - if ((arp_table[i].state >= ETHARP_STATE_STABLE) && -#if ETHARP_TABLE_MATCH_NETIF - (arp_table[i].netif == netif) && -#endif - (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) { - /* found an existing, stable entry */ - ETHARP_SET_HINT(netif, i); - return etharp_output_to_arp_index(netif, q, i); - } - } - /* no stable entry found, use the (slower) query function: - queue on destination Ethernet address belonging to ipaddr */ - return etharp_query(netif, dst_addr, q); - } - - /* continuation for multicast/broadcast destinations */ - /* obtain source Ethernet address of the given interface */ - /* send packet directly on the link */ - return ethernet_output(netif, q, (struct eth_addr*)(netif->hwaddr), dest, ETHTYPE_IP); -} - -/** - * Send an ARP request for the given IP address and/or queue a packet. - * - * If the IP address was not yet in the cache, a pending ARP cache entry - * is added and an ARP request is sent for the given address. The packet - * is queued on this entry. - * - * If the IP address was already pending in the cache, a new ARP request - * is sent for the given address. The packet is queued on this entry. - * - * If the IP address was already stable in the cache, and a packet is - * given, it is directly sent and no ARP request is sent out. - * - * If the IP address was already stable in the cache, and no packet is - * given, an ARP request is sent out. - * - * @param netif The lwIP network interface on which ipaddr - * must be queried for. - * @param ipaddr The IP address to be resolved. - * @param q If non-NULL, a pbuf that must be delivered to the IP address. - * q is not freed by this function. - * - * @note q must only be ONE packet, not a packet queue! - * - * @return - * - ERR_BUF Could not make room for Ethernet header. - * - ERR_MEM Hardware address unknown, and no more ARP entries available - * to query for address or queue the packet. - * - ERR_MEM Could not queue packet due to memory shortage. - * - ERR_RTE No route to destination (no gateway to external networks). - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - */ -err_t -etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q) -{ - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_MEM; - int is_new_entry = 0; - s8_t i; /* ARP entry index */ - - /* non-unicast address? */ - if (ip4_addr_isbroadcast(ipaddr, netif) || - ip4_addr_ismulticast(ipaddr) || - ip4_addr_isany(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - - /* find entry in ARP cache, ask to create entry if queueing packet */ - i = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif); - - /* could not find or create entry? */ - if (i < 0) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); - if (q) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); - ETHARP_STATS_INC(etharp.memerr); - } - return (err_t)i; - } - - /* mark a fresh entry as pending (we just sent a request) */ - if (arp_table[i].state == ETHARP_STATE_EMPTY) { - is_new_entry = 1; - arp_table[i].state = ETHARP_STATE_PENDING; - /* record network interface for re-sending arp request in etharp_tmr */ - arp_table[i].netif = netif; - } - - /* { i is either a STABLE or (new or existing) PENDING entry } */ - LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", - ((arp_table[i].state == ETHARP_STATE_PENDING) || - (arp_table[i].state >= ETHARP_STATE_STABLE))); - - /* do we have a new entry? or an implicit query request? */ - if (is_new_entry || (q == NULL)) { - /* try to resolve it; send out ARP request */ - result = etharp_request(netif, ipaddr); - if (result != ERR_OK) { - /* ARP request couldn't be sent */ - /* We don't re-send arp request in etharp_tmr, but we still queue packets, - since this failure could be temporary, and the next packet calling - etharp_query again could lead to sending the queued packets. */ - } - if (q == NULL) { - return result; - } - } - - /* packet given? */ - LWIP_ASSERT("q != NULL", q != NULL); - /* stable entry? */ - if (arp_table[i].state >= ETHARP_STATE_STABLE) { - /* we have a valid IP->Ethernet address mapping */ - ETHARP_SET_HINT(netif, i); - /* send the packet */ - result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP); - /* pending entry? (either just created or already pending */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* entry is still pending, queue the given packet 'q' */ - struct pbuf *p; - int copy_needed = 0; - /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but - * to copy the whole queue into a new PBUF_RAM (see bug #11400) - * PBUF_ROMs can be left as they are, since ROM must not get changed. */ - p = q; - while (p) { - LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); - if (p->type != PBUF_ROM) { - copy_needed = 1; - break; - } - p = p->next; - } - if (copy_needed) { - /* copy the whole packet into new pbufs */ - p = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); - if (p != NULL) { - if (pbuf_copy(p, q) != ERR_OK) { - pbuf_free(p); - p = NULL; - } - } - } else { - /* referencing the old pbuf is enough */ - p = q; - pbuf_ref(p); - } - /* packet could be taken over? */ - if (p != NULL) { - /* queue packet ... */ -#if ARP_QUEUEING - struct etharp_q_entry *new_entry; - /* allocate a new arp queue entry */ - new_entry = (struct etharp_q_entry *)memp_malloc(MEMP_ARP_QUEUE); - if (new_entry != NULL) { - unsigned int qlen = 0; - new_entry->next = 0; - new_entry->p = p; - if (arp_table[i].q != NULL) { - /* queue was already existent, append the new entry to the end */ - struct etharp_q_entry *r; - r = arp_table[i].q; - qlen++; - while (r->next != NULL) { - r = r->next; - qlen++; - } - r->next = new_entry; - } else { - /* queue did not exist, first item in queue */ - arp_table[i].q = new_entry; - } -#if ARP_QUEUE_LEN - if (qlen >= ARP_QUEUE_LEN) { - struct etharp_q_entry *old; - old = arp_table[i].q; - arp_table[i].q = arp_table[i].q->next; - pbuf_free(old->p); - memp_free(MEMP_ARP_QUEUE, old); - } -#endif - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); - result = ERR_OK; - } else { - /* the pool MEMP_ARP_QUEUE is empty */ - pbuf_free(p); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - result = ERR_MEM; - } -#else /* ARP_QUEUEING */ - /* always queue one packet per ARP request only, freeing a previously queued packet */ - if (arp_table[i].q != NULL) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); - pbuf_free(arp_table[i].q); - } - arp_table[i].q = p; - result = ERR_OK; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); -#endif /* ARP_QUEUEING */ - } else { - ETHARP_STATS_INC(etharp.memerr); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - result = ERR_MEM; - } - } - return result; -} - -/** - * Send a raw ARP packet (opcode and all addresses can be modified) - * - * @param netif the lwip network interface on which to send the ARP packet - * @param ethsrc_addr the source MAC address for the ethernet header - * @param ethdst_addr the destination MAC address for the ethernet header - * @param hwsrc_addr the source MAC address for the ARP protocol header - * @param ipsrc_addr the source IP address for the ARP protocol header - * @param hwdst_addr the destination MAC address for the ARP protocol header - * @param ipdst_addr the destination IP address for the ARP protocol header - * @param opcode the type of the ARP packet - * @return ERR_OK if the ARP packet has been sent - * ERR_MEM if the ARP packet couldn't be allocated - * any other err_t on failure - */ -static err_t -etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, - const struct eth_addr *ethdst_addr, - const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, - const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, - const u16_t opcode) -{ - struct pbuf *p; - err_t result = ERR_OK; - struct etharp_hdr *hdr; - - LWIP_ASSERT("netif != NULL", netif != NULL); - - /* allocate a pbuf for the outgoing ARP request packet */ - p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM); - /* could allocate a pbuf for an ARP request? */ - if (p == NULL) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("etharp_raw: could not allocate pbuf for ARP request.\n")); - ETHARP_STATS_INC(etharp.memerr); - return ERR_MEM; - } - LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", - (p->len >= SIZEOF_ETHARP_HDR)); - - hdr = (struct etharp_hdr *)p->payload; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); - hdr->opcode = lwip_htons(opcode); - - LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!", - (netif->hwaddr_len == ETH_HWADDR_LEN)); - - /* Write the ARP MAC-Addresses */ - ETHADDR16_COPY(&hdr->shwaddr, hwsrc_addr); - ETHADDR16_COPY(&hdr->dhwaddr, hwdst_addr); - /* Copy struct ip4_addr2 to aligned ip4_addr, to support compilers without - * structure packing. */ - IPADDR2_COPY(&hdr->sipaddr, ipsrc_addr); - IPADDR2_COPY(&hdr->dipaddr, ipdst_addr); - - hdr->hwtype = PP_HTONS(HWTYPE_ETHERNET); - hdr->proto = PP_HTONS(ETHTYPE_IP); - /* set hwlen and protolen */ - hdr->hwlen = ETH_HWADDR_LEN; - hdr->protolen = sizeof(ip4_addr_t); - - /* send ARP query */ -#if LWIP_AUTOIP - /* If we are using Link-Local, all ARP packets that contain a Link-Local - * 'sender IP address' MUST be sent using link-layer broadcast instead of - * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */ - if(ip4_addr_islinklocal(ipsrc_addr)) { - ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP); - } else -#endif /* LWIP_AUTOIP */ - { - ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP); - } - - ETHARP_STATS_INC(etharp.xmit); - /* free ARP query packet */ - pbuf_free(p); - p = NULL; - /* could not allocate pbuf for ARP request */ - - return result; -} - -/** - * Send an ARP request packet asking for ipaddr to a specific eth address. - * Used to send unicast request to refresh the ARP table just before an entry - * times out - * - * @param netif the lwip network interface on which to send the request - * @param ipaddr the IP address for which to ask - * @param hw_dst_addr the ethernet address to send this packet to - * @return ERR_OK if the request has been sent - * ERR_MEM if the ARP packet couldn't be allocated - * any other err_t on failure - */ -static err_t -etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr* hw_dst_addr) -{ - return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, - (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero, - ipaddr, ARP_REQUEST); -} - -/** - * Send an ARP request packet asking for ipaddr. - * - * @param netif the lwip network interface on which to send the request - * @param ipaddr the IP address for which to ask - * @return ERR_OK if the request has been sent - * ERR_MEM if the ARP packet couldn't be allocated - * any other err_t on failure - */ -err_t -etharp_request(struct netif *netif, const ip4_addr_t *ipaddr) -{ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); - return etharp_request_dst(netif, ipaddr, ðbroadcast); -} -#endif /* LWIP_IPV4 && LWIP_ARP */ - -#endif /* LWIP_ARP || LWIP_ETHERNET */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/icmp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/icmp.c deleted file mode 100644 index 5ee24eedfa1e814decb412efd9ee395bdd300045..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/icmp.c +++ /dev/null @@ -1,397 +0,0 @@ -/** - * @file - * ICMP - Internet Control Message Protocol - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/icmp.h" -#include "lwip/inet_chksum.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/stats.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be - * used to modify and send a response packet (and to 1 if this is not the case, - * e.g. when link header is stripped of when receiving) */ -#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN -#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1 -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ - -/* The amount of data from the original packet to return in a dest-unreachable */ -#define ICMP_DEST_UNREACH_DATASIZE 8 - -static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code); - -/** - * Processes ICMP input packets, called from ip_input(). - * - * Currently only processes icmp echo requests and sends - * out the echo response. - * - * @param p the icmp echo request packet, p->payload pointing to the icmp header - * @param inp the netif on which this packet was received - */ -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; -#ifdef LWIP_DEBUG - u8_t code; -#endif /* LWIP_DEBUG */ - struct icmp_echo_hdr *iecho; - const struct ip_hdr *iphdr_in; - u16_t hlen; - const ip4_addr_t* src; - - ICMP_STATS_INC(icmp.recv); - MIB2_STATS_INC(mib2.icmpinmsgs); - - iphdr_in = ip4_current_header(); - hlen = IPH_HL(iphdr_in) * 4; - if (hlen < IP_HLEN) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen)); - goto lenerr; - } - if (p->len < sizeof(u16_t)*2) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); - goto lenerr; - } - - type = *((u8_t *)p->payload); -#ifdef LWIP_DEBUG - code = *(((u8_t *)p->payload)+1); -#endif /* LWIP_DEBUG */ - switch (type) { - case ICMP_ER: - /* This is OK, echo reply might have been parsed by a raw PCB - (as obviously, an echo request has been sent, too). */ - MIB2_STATS_INC(mib2.icmpinechoreps); - break; - case ICMP_ECHO: - MIB2_STATS_INC(mib2.icmpinechos); - src = ip4_current_dest_addr(); - /* multicast destination address? */ - if (ip4_addr_ismulticast(ip4_current_dest_addr())) { -#if LWIP_MULTICAST_PING - /* For multicast, use address of receiving interface as source address */ - src = netif_ip4_addr(inp); -#else /* LWIP_MULTICAST_PING */ - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n")); - goto icmperr; -#endif /* LWIP_MULTICAST_PING */ - } - /* broadcast destination address? */ - if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) { -#if LWIP_BROADCAST_PING - /* For broadcast, use address of receiving interface as source address */ - src = netif_ip4_addr(inp); -#else /* LWIP_BROADCAST_PING */ - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n")); - goto icmperr; -#endif /* LWIP_BROADCAST_PING */ - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - goto lenerr; - } -#if CHECKSUM_CHECK_ICMP - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) { - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.chkerr); - MIB2_STATS_INC(mib2.icmpinerrors); - return; - } - } -#endif -#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN - if (pbuf_header(p, (s16_t)(hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN))) { - /* p is not big enough to contain link headers - * allocate a new one and copy p into it - */ - struct pbuf *r; - /* allocate new packet buffer with space for link headers */ - r = pbuf_alloc(PBUF_LINK, p->tot_len + hlen, PBUF_RAM); - if (r == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); - goto icmperr; - } - if (r->len < hlen + sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header")); - pbuf_free(r); - goto icmperr; - } - /* copy the ip header */ - MEMCPY(r->payload, iphdr_in, hlen); - /* switch r->payload back to icmp header (cannot fail) */ - if (pbuf_header(r, (s16_t)-hlen)) { - LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0); - pbuf_free(r); - goto icmperr; - } - /* copy the rest of the packet without ip header */ - if (pbuf_copy(r, p) != ERR_OK) { - LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed")); - pbuf_free(r); - goto icmperr; - } - /* free the original p */ - pbuf_free(p); - /* we now have an identical copy of p that has room for link headers */ - p = r; - } else { - /* restore p->payload to point to icmp header (cannot fail) */ - if (pbuf_header(p, -(s16_t)(hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN))) { - LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); - goto icmperr; - } - } -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ - /* At this point, all checks are OK. */ - /* We generate an answer by switching the dest and src ip addresses, - * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ - iecho = (struct icmp_echo_hdr *)p->payload; - if (pbuf_header(p, (s16_t)hlen)) { - LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet")); - } else { - err_t ret; - struct ip_hdr *iphdr = (struct ip_hdr*)p->payload; - ip4_addr_copy(iphdr->src, *src); - ip4_addr_copy(iphdr->dest, *ip4_current_src_addr()); - ICMPH_TYPE_SET(iecho, ICMP_ER); -#if CHECKSUM_GEN_ICMP - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) { - /* adjust the checksum */ - if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) { - iecho->chksum += PP_HTONS(ICMP_ECHO << 8) + 1; - } else { - iecho->chksum += PP_HTONS(ICMP_ECHO << 8); - } - } -#if LWIP_CHECKSUM_CTRL_PER_NETIF - else { - iecho->chksum = 0; - } -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ -#else /* CHECKSUM_GEN_ICMP */ - iecho->chksum = 0; -#endif /* CHECKSUM_GEN_ICMP */ - - /* Set the correct TTL and recalculate the header checksum. */ - IPH_TTL_SET(iphdr, ICMP_TTL); - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_IP) { - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, hlen)); - } -#endif /* CHECKSUM_GEN_IP */ - - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - MIB2_STATS_INC(mib2.icmpoutmsgs); - /* increase number of echo replies attempted to send */ - MIB2_STATS_INC(mib2.icmpoutechoreps); - - /* send an ICMP packet */ - ret = ip4_output_if(p, src, LWIP_IP_HDRINCL, - ICMP_TTL, 0, IP_PROTO_ICMP, inp); - if (ret != ERR_OK) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); - } - } - break; - default: - if (type == ICMP_DUR) { - MIB2_STATS_INC(mib2.icmpindestunreachs); - } else if (type == ICMP_TE) { - MIB2_STATS_INC(mib2.icmpintimeexcds); - } else if (type == ICMP_PP) { - MIB2_STATS_INC(mib2.icmpinparmprobs); - } else if (type == ICMP_SQ) { - MIB2_STATS_INC(mib2.icmpinsrcquenchs); - } else if (type == ICMP_RD) { - MIB2_STATS_INC(mib2.icmpinredirects); - } else if (type == ICMP_TS) { - MIB2_STATS_INC(mib2.icmpintimestamps); - } else if (type == ICMP_TSR) { - MIB2_STATS_INC(mib2.icmpintimestampreps); - } else if (type == ICMP_AM) { - MIB2_STATS_INC(mib2.icmpinaddrmasks); - } else if (type == ICMP_AMR) { - MIB2_STATS_INC(mib2.icmpinaddrmaskreps); - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", - (s16_t)type, (s16_t)code)); - ICMP_STATS_INC(icmp.proterr); - ICMP_STATS_INC(icmp.drop); - } - pbuf_free(p); - return; -lenerr: - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - MIB2_STATS_INC(mib2.icmpinerrors); - return; -#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING -icmperr: - pbuf_free(p); - ICMP_STATS_INC(icmp.err); - MIB2_STATS_INC(mib2.icmpinerrors); - return; -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ -} - -/** - * Send an icmp 'destination unreachable' packet, called from ip_input() if - * the transport layer protocol is unknown and from udp_input() if the local - * port is not bound. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IP header - * @param t type of the 'unreachable' packet - */ -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - MIB2_STATS_INC(mib2.icmpoutdestunreachs); - icmp_send_response(p, ICMP_DUR, t); -} - -#if IP_FORWARD || IP_REASSEMBLY -/** - * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0. - * - * @param p the input packet for which the 'time exceeded' should be sent, - * p->payload pointing to the IP header - * @param t type of the 'time exceeded' packet - */ -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - MIB2_STATS_INC(mib2.icmpouttimeexcds); - icmp_send_response(p, ICMP_TE, t); -} - -#endif /* IP_FORWARD || IP_REASSEMBLY */ - -/** - * Send an icmp packet in response to an incoming packet. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IP header - * @param type Type of the ICMP header - * @param code Code of the ICMP header - */ -static void -icmp_send_response(struct pbuf *p, u8_t type, u8_t code) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - /* we can use the echo header here */ - struct icmp_echo_hdr *icmphdr; - ip4_addr_t iphdr_src; - struct netif *netif; - - /* increase number of messages attempted to send */ - MIB2_STATS_INC(mib2.icmpoutmsgs); - - /* ICMP header + IP header + 8 bytes of data */ - q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, - PBUF_RAM); - if (q == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); - MIB2_STATS_INC(mib2.icmpouterrors); - return; - } - LWIP_ASSERT("check that first pbuf can hold icmp message", - (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); - - iphdr = (struct ip_hdr *)p->payload; - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); - ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src); - LWIP_DEBUGF(ICMP_DEBUG, (" to ")); - ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest); - LWIP_DEBUGF(ICMP_DEBUG, ("\n")); - - icmphdr = (struct icmp_echo_hdr *)q->payload; - icmphdr->type = type; - icmphdr->code = code; - icmphdr->id = 0; - icmphdr->seqno = 0; - - /* copy fields from original packet */ - SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, - IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); - - ip4_addr_copy(iphdr_src, iphdr->src); -#ifdef LWIP_HOOK_IP4_ROUTE_SRC - { - ip4_addr_t iphdr_dst; - ip4_addr_copy(iphdr_dst, iphdr->dest); - netif = ip4_route_src(&iphdr_src, &iphdr_dst); - } -#else - netif = ip4_route(&iphdr_src); -#endif - if (netif != NULL) { - /* calculate checksum */ - icmphdr->chksum = 0; -#if CHECKSUM_GEN_ICMP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) { - icmphdr->chksum = inet_chksum(icmphdr, q->len); - } -#endif - ICMP_STATS_INC(icmp.xmit); - ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif); - } - pbuf_free(q); -} - -#endif /* LWIP_IPV4 && LWIP_ICMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/igmp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/igmp.c deleted file mode 100644 index 74a6c377314905eb16f3df587ad47633c3b46e8e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/igmp.c +++ /dev/null @@ -1,800 +0,0 @@ -/** - * @file - * IGMP - Internet Group Management Protocol - * - * @defgroup igmp IGMP - * @ingroup ip4 - * To be called from TCPIP thread - */ - -/* - * Copyright (c) 2002 CITEL Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. -*/ - -/*------------------------------------------------------------- -Note 1) -Although the rfc requires V1 AND V2 capability -we will only support v2 since now V1 is very old (August 1989) -V1 can be added if required - -a debug print and statistic have been implemented to -show this up. -------------------------------------------------------------- -------------------------------------------------------------- -Note 2) -A query for a specific group address (as opposed to ALLHOSTS) -has now been implemented as I am unsure if it is required - -a debug print and statistic have been implemented to -show this up. -------------------------------------------------------------- -------------------------------------------------------------- -Note 3) -The router alert rfc 2113 is implemented in outgoing packets -but not checked rigorously incoming -------------------------------------------------------------- -Steve Reynolds -------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * RFC 988 - Host extensions for IP multicasting - V0 - * RFC 1054 - Host extensions for IP multicasting - - * RFC 1112 - Host extensions for IP multicasting - V1 - * RFC 2236 - Internet Group Management Protocol, Version 2 - V2 <- this code is based on this RFC (it's the "de facto" standard) - * RFC 3376 - Internet Group Management Protocol, Version 3 - V3 - * RFC 4604 - Using Internet Group Management Protocol Version 3... - V3+ - * RFC 2113 - IP Router Alert Option - - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Includes - *----------------------------------------------------------------------------*/ - -#include "lwip/opt.h" - -#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/igmp.h" -#include "lwip/debug.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/stats.h" -#include "lwip/prot/igmp.h" - -#include "string.h" - -static struct igmp_group *igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr); -static err_t igmp_remove_group(struct netif* netif, struct igmp_group *group); -static void igmp_timeout(struct netif *netif, struct igmp_group *group); -static void igmp_start_timer(struct igmp_group *group, u8_t max_time); -static void igmp_delaying_member(struct igmp_group *group, u8_t maxresp); -static err_t igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif); -static void igmp_send(struct netif *netif, struct igmp_group *group, u8_t type); - -static ip4_addr_t allsystems; -static ip4_addr_t allrouters; - -/** - * Initialize the IGMP module - */ -void -igmp_init(void) -{ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n")); - - IP4_ADDR(&allsystems, 224, 0, 0, 1); - IP4_ADDR(&allrouters, 224, 0, 0, 2); -} - -/** - * Start IGMP processing on interface - * - * @param netif network interface on which start IGMP processing - */ -err_t -igmp_start(struct netif *netif) -{ - struct igmp_group* group; - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", (void*)netif)); - - group = igmp_lookup_group(netif, &allsystems); - - if (group != NULL) { - group->group_state = IGMP_GROUP_IDLE_MEMBER; - group->use++; - - /* Allow the igmp messages at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD ")); - ip4_addr_debug_print_val(IGMP_DEBUG, allsystems); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void*)netif)); - netif->igmp_mac_filter(netif, &allsystems, NETIF_ADD_MAC_FILTER); - } - - return ERR_OK; - } - - return ERR_MEM; -} - -/** - * Stop IGMP processing on interface - * - * @param netif network interface on which stop IGMP processing - */ -err_t -igmp_stop(struct netif *netif) -{ - struct igmp_group *group = netif_igmp_data(netif); - - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, NULL); - - while (group != NULL) { - struct igmp_group *next = group->next; /* avoid use-after-free below */ - - /* disable the group at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL ")); - ip4_addr_debug_print(IGMP_DEBUG, &group->group_address); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void*)netif)); - netif->igmp_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER); - } - - /* free group */ - memp_free(MEMP_IGMP_GROUP, group); - - /* move to "next" */ - group = next; - } - return ERR_OK; -} - -/** - * Report IGMP memberships for this interface - * - * @param netif network interface on which report IGMP memberships - */ -void -igmp_report_groups(struct netif *netif) -{ - struct igmp_group *group = netif_igmp_data(netif); - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", (void*)netif)); - - /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ - if(group != NULL) { - group = group->next; - } - - while (group != NULL) { - igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR); - group = group->next; - } -} - -/** - * Search for a group in the global igmp_group_list - * - * @param ifp the network interface for which to look - * @param addr the group ip address to search for - * @return a struct igmp_group* if the group has been found, - * NULL if the group wasn't found. - */ -struct igmp_group * -igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr) -{ - struct igmp_group *group = netif_igmp_data(ifp); - - while (group != NULL) { - if (ip4_addr_cmp(&(group->group_address), addr)) { - return group; - } - group = group->next; - } - - /* to be clearer, we return NULL here instead of - * 'group' (which is also NULL at this point). - */ - return NULL; -} - -/** - * Search for a specific igmp group and create a new one if not found- - * - * @param ifp the network interface for which to look - * @param addr the group ip address to search - * @return a struct igmp_group*, - * NULL on memory error. - */ -static struct igmp_group * -igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr) -{ - struct igmp_group *group; - struct igmp_group *list_head = netif_igmp_data(ifp); - - /* Search if the group already exists */ - group = igmp_lookfor_group(ifp, addr); - if (group != NULL) { - /* Group already exists. */ - return group; - } - - /* Group doesn't exist yet, create a new one */ - group = (struct igmp_group *)memp_malloc(MEMP_IGMP_GROUP); - if (group != NULL) { - ip4_addr_set(&(group->group_address), addr); - group->timer = 0; /* Not running */ - group->group_state = IGMP_GROUP_NON_MEMBER; - group->last_reporter_flag = 0; - group->use = 0; - - /* Ensure allsystems group is always first in list */ - if (list_head == NULL) { - /* this is the first entry in linked list */ - LWIP_ASSERT("igmp_lookup_group: first group must be allsystems", - (ip4_addr_cmp(addr, &allsystems) != 0)); - group->next = NULL; - netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, group); - } else { - /* append _after_ first entry */ - LWIP_ASSERT("igmp_lookup_group: all except first group must not be allsystems", - (ip4_addr_cmp(addr, &allsystems) == 0)); - group->next = list_head->next; - list_head->next = group; - } - } - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to "))); - ip4_addr_debug_print(IGMP_DEBUG, addr); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void*)ifp)); - - return group; -} - -/** - * Remove a group in the global igmp_group_list, but don't free it yet - * - * @param group the group to remove from the global igmp_group_list - * @return ERR_OK if group was removed from the list, an err_t otherwise - */ -static err_t -igmp_remove_group(struct netif* netif, struct igmp_group *group) -{ - err_t err = ERR_OK; - struct igmp_group *tmp_group; - - /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ - for (tmp_group = netif_igmp_data(netif); tmp_group != NULL; tmp_group = tmp_group->next) { - if (tmp_group->next == group) { - tmp_group->next = group->next; - break; - } - } - /* Group not found in the global igmp_group_list */ - if (tmp_group == NULL) { - err = ERR_ARG; - } - - return err; -} - -/** - * Called from ip_input() if a new IGMP packet is received. - * - * @param p received igmp packet, p->payload pointing to the igmp header - * @param inp network interface on which the packet was received - * @param dest destination ip address of the igmp packet - */ -void -igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest) -{ - struct igmp_msg* igmp; - struct igmp_group* group; - struct igmp_group* groupref; - - IGMP_STATS_INC(igmp.recv); - - /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */ - if (p->len < IGMP_MINLEN) { - pbuf_free(p); - IGMP_STATS_INC(igmp.lenerr); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n")); - return; - } - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from ")); - ip4_addr_debug_print(IGMP_DEBUG, &(ip4_current_header()->src)); - LWIP_DEBUGF(IGMP_DEBUG, (" to address ")); - ip4_addr_debug_print(IGMP_DEBUG, &(ip4_current_header()->dest)); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void*)inp)); - - /* Now calculate and check the checksum */ - igmp = (struct igmp_msg *)p->payload; - if (inet_chksum(igmp, p->len)) { - pbuf_free(p); - IGMP_STATS_INC(igmp.chkerr); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n")); - return; - } - - /* Packet is ok so find an existing group */ - group = igmp_lookfor_group(inp, dest); /* use the destination IP address of incoming packet */ - - /* If group can be found or create... */ - if (!group) { - pbuf_free(p); - IGMP_STATS_INC(igmp.drop); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n")); - return; - } - - /* NOW ACT ON THE INCOMING MESSAGE TYPE... */ - switch (igmp->igmp_msgtype) { - case IGMP_MEMB_QUERY: - /* IGMP_MEMB_QUERY to the "all systems" address ? */ - if ((ip4_addr_cmp(dest, &allsystems)) && ip4_addr_isany(&igmp->igmp_group_address)) { - /* THIS IS THE GENERAL QUERY */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - - if (igmp->igmp_maxresp == 0) { - IGMP_STATS_INC(igmp.rx_v1); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n")); - igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR; - } else { - IGMP_STATS_INC(igmp.rx_general); - } - - groupref = netif_igmp_data(inp); - - /* Do not send messages on the all systems group address! */ - /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ - if(groupref != NULL) { - groupref = groupref->next; - } - - while (groupref) { - igmp_delaying_member(groupref, igmp->igmp_maxresp); - groupref = groupref->next; - } - } else { - /* IGMP_MEMB_QUERY to a specific group ? */ - if (!ip4_addr_isany(&igmp->igmp_group_address)) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group ")); - ip4_addr_debug_print(IGMP_DEBUG, &igmp->igmp_group_address); - if (ip4_addr_cmp(dest, &allsystems)) { - ip4_addr_t groupaddr; - LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - /* we first need to re-look for the group since we used dest last time */ - ip4_addr_copy(groupaddr, igmp->igmp_group_address); - group = igmp_lookfor_group(inp, &groupaddr); - } else { - LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - } - - if (group != NULL) { - IGMP_STATS_INC(igmp.rx_group); - igmp_delaying_member(group, igmp->igmp_maxresp); - } else { - IGMP_STATS_INC(igmp.drop); - } - } else { - IGMP_STATS_INC(igmp.proterr); - } - } - break; - case IGMP_V2_MEMB_REPORT: - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n")); - IGMP_STATS_INC(igmp.rx_report); - if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { - /* This is on a specific group we have already looked up */ - group->timer = 0; /* stopped */ - group->group_state = IGMP_GROUP_IDLE_MEMBER; - group->last_reporter_flag = 0; - } - break; - default: - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n", - igmp->igmp_msgtype, group->group_state, (void*)&group, (void*)inp)); - IGMP_STATS_INC(igmp.proterr); - break; - } - - pbuf_free(p); - return; -} - -/** - * @ingroup igmp - * Join a group on one network interface. - * - * @param ifaddr ip address of the network interface which should join a new group - * @param groupaddr the ip address of the group which to join - * @return ERR_OK if group was joined on the netif(s), an err_t otherwise - */ -err_t -igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct netif *netif; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we join this interface ? */ - if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) { - err = igmp_joingroup_netif(netif, groupaddr); - if (err != ERR_OK) { - /* Return an error even if some network interfaces are joined */ - /** @todo undo any other netif already joined */ - return err; - } - } - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * @ingroup igmp - * Join a group on one network interface. - * - * @param netif the network interface which should join a new group - * @param groupaddr the ip address of the group which to join - * @return ERR_OK if group was joined on the netif, an err_t otherwise - */ -err_t -igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr) -{ - struct igmp_group *group; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_joingroup_netif: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_joingroup_netif: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* make sure it is an igmp-enabled netif */ - LWIP_ERROR("igmp_joingroup_netif: attempt to join on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;); - - /* find group or create a new one if not found */ - group = igmp_lookup_group(netif, groupaddr); - - if (group != NULL) { - /* This should create a new group, check the state to make sure */ - if (group->group_state != IGMP_GROUP_NON_MEMBER) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to group not in state IGMP_GROUP_NON_MEMBER\n")); - } else { - /* OK - it was new group */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to new group: ")); - ip4_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); - - /* If first use of the group, allow the group at the MAC level */ - if ((group->use==0) && (netif->igmp_mac_filter != NULL)) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: igmp_mac_filter(ADD ")); - ip4_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void*)netif)); - netif->igmp_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER); - } - - IGMP_STATS_INC(igmp.tx_join); - igmp_send(netif, group, IGMP_V2_MEMB_REPORT); - - igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR); - - /* Need to work out where this timer comes from */ - group->group_state = IGMP_GROUP_DELAYING_MEMBER; - } - /* Increment group use */ - group->use++; - /* Join on this interface */ - return ERR_OK; - } else { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: Not enough memory to join to group\n")); - return ERR_MEM; - } -} - -/** - * @ingroup igmp - * Leave a group on one network interface. - * - * @param ifaddr ip address of the network interface which should leave a group - * @param groupaddr the ip address of the group which to leave - * @return ERR_OK if group was left on the netif(s), an err_t otherwise - */ -err_t -igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct netif *netif; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we leave this interface ? */ - if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) { - err_t res = igmp_leavegroup_netif(netif, groupaddr); - if (err != ERR_OK) { - /* Store this result if we have not yet gotten a success */ - err = res; - } - } - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * @ingroup igmp - * Leave a group on one network interface. - * - * @param netif the network interface which should leave a group - * @param groupaddr the ip address of the group which to leave - * @return ERR_OK if group was left on the netif, an err_t otherwise - */ -err_t -igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr) -{ - struct igmp_group *group; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_leavegroup_netif: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_leavegroup_netif: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* make sure it is an igmp-enabled netif */ - LWIP_ERROR("igmp_leavegroup_netif: attempt to leave on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;); - - /* find group */ - group = igmp_lookfor_group(netif, groupaddr); - - if (group != NULL) { - /* Only send a leave if the flag is set according to the state diagram */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: Leaving group: ")); - ip4_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); - - /* If there is no other use of the group */ - if (group->use <= 1) { - /* Remove the group from the list */ - igmp_remove_group(netif, group); - - /* If we are the last reporter for this group */ - if (group->last_reporter_flag) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: sending leaving group\n")); - IGMP_STATS_INC(igmp.tx_leave); - igmp_send(netif, group, IGMP_LEAVE_GROUP); - } - - /* Disable the group at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: igmp_mac_filter(DEL ")); - ip4_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void*)netif)); - netif->igmp_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER); - } - - /* Free group struct */ - memp_free(MEMP_IGMP_GROUP, group); - } else { - /* Decrement group use */ - group->use--; - } - return ERR_OK; - } else { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: not member of group\n")); - return ERR_VAL; - } -} - -/** - * The igmp timer function (both for NO_SYS=1 and =0) - * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default). - */ -void -igmp_tmr(void) -{ - struct netif *netif = netif_list; - - while (netif != NULL) { - struct igmp_group *group = netif_igmp_data(netif); - - while (group != NULL) { - if (group->timer > 0) { - group->timer--; - if (group->timer == 0) { - igmp_timeout(netif, group); - } - } - group = group->next; - } - netif = netif->next; - } -} - -/** - * Called if a timeout for one group is reached. - * Sends a report for this group. - * - * @param group an igmp_group for which a timeout is reached - */ -static void -igmp_timeout(struct netif *netif, struct igmp_group *group) -{ - /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group - (unless it is the allsystems group) */ - if ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && - (!(ip4_addr_cmp(&(group->group_address), &allsystems)))) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address ")); - ip4_addr_debug_print(IGMP_DEBUG, &(group->group_address)); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void*)netif)); - - group->group_state = IGMP_GROUP_IDLE_MEMBER; - - IGMP_STATS_INC(igmp.tx_report); - igmp_send(netif, group, IGMP_V2_MEMB_REPORT); - } -} - -/** - * Start a timer for an igmp group - * - * @param group the igmp_group for which to start a timer - * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with - * every call to igmp_tmr()) - */ -static void -igmp_start_timer(struct igmp_group *group, u8_t max_time) -{ -#ifdef LWIP_RAND - group->timer = max_time > 2 ? (LWIP_RAND() % max_time) : 1; -#else /* LWIP_RAND */ - /* ATTENTION: use this only if absolutely necessary! */ - group->timer = max_time / 2; -#endif /* LWIP_RAND */ - - if (group->timer == 0) { - group->timer = 1; - } -} - -/** - * Delaying membership report for a group if necessary - * - * @param group the igmp_group for which "delaying" membership report - * @param maxresp query delay - */ -static void -igmp_delaying_member(struct igmp_group *group, u8_t maxresp) -{ - if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) || - ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && - ((group->timer == 0) || (maxresp < group->timer)))) { - igmp_start_timer(group, maxresp); - group->group_state = IGMP_GROUP_DELAYING_MEMBER; - } -} - - -/** - * Sends an IP packet on a network interface. This function constructs the IP header - * and calculates the IP header checksum. If the source IP address is NULL, - * the IP address of the outgoing network interface is filled in as source address. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IP header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param netif the netif on which to send this packet - * @return ERR_OK if the packet was sent OK - * ERR_BUF if p doesn't have enough space for IP/LINK headers - * returns errors returned by netif->output - */ -static err_t -igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif) -{ - /* This is the "router alert" option */ - u16_t ra[2]; - ra[0] = PP_HTONS(ROUTER_ALERT); - ra[1] = 0x0000; /* Router shall examine packet */ - IGMP_STATS_INC(igmp.xmit); - return ip4_output_if_opt(p, src, dest, IGMP_TTL, 0, IP_PROTO_IGMP, netif, ra, ROUTER_ALERTLEN); -} - -/** - * Send an igmp packet to a specific group. - * - * @param group the group to which to send the packet - * @param type the type of igmp packet to send - */ -static void -igmp_send(struct netif *netif, struct igmp_group *group, u8_t type) -{ - struct pbuf* p = NULL; - struct igmp_msg* igmp = NULL; - ip4_addr_t src = *IP4_ADDR_ANY4; - ip4_addr_t* dest = NULL; - - /* IP header + "router alert" option + IGMP header */ - p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM); - - if (p) { - igmp = (struct igmp_msg *)p->payload; - LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg", - (p->len >= sizeof(struct igmp_msg))); - ip4_addr_copy(src, *netif_ip4_addr(netif)); - - if (type == IGMP_V2_MEMB_REPORT) { - dest = &(group->group_address); - ip4_addr_copy(igmp->igmp_group_address, group->group_address); - group->last_reporter_flag = 1; /* Remember we were the last to report */ - } else { - if (type == IGMP_LEAVE_GROUP) { - dest = &allrouters; - ip4_addr_copy(igmp->igmp_group_address, group->group_address); - } - } - - if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) { - igmp->igmp_msgtype = type; - igmp->igmp_maxresp = 0; - igmp->igmp_checksum = 0; - igmp->igmp_checksum = inet_chksum(igmp, IGMP_MINLEN); - - igmp_ip_output_if(p, &src, dest, netif); - } - - pbuf_free(p); - } else { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n")); - IGMP_STATS_INC(igmp.memerr); - } -} - -#endif /* LWIP_IPV4 && LWIP_IGMP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4.c deleted file mode 100644 index 1b81c31d2c61e6bfb1ef1645a870060329d90d6c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4.c +++ /dev/null @@ -1,1142 +0,0 @@ -/** - * @file - * This is the IPv4 layer implementation for incoming and outgoing IP traffic. - * - * @see ip_frag.c - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 - -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip4_frag.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/igmp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/stats.h" -#include "lwip/prot/dhcp.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -/** Set this to 0 in the rare case of wanting to call an extra function to - * generate the IP checksum (in contrast to calculating it on-the-fly). */ -#ifndef LWIP_INLINE_IP_CHKSUM -#if LWIP_CHECKSUM_CTRL_PER_NETIF -#define LWIP_INLINE_IP_CHKSUM 0 -#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */ -#define LWIP_INLINE_IP_CHKSUM 1 -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ -#endif - -#if LWIP_INLINE_IP_CHKSUM && CHECKSUM_GEN_IP -#define CHECKSUM_GEN_IP_INLINE 1 -#else -#define CHECKSUM_GEN_IP_INLINE 0 -#endif - -#if LWIP_DHCP || defined(LWIP_IP_ACCEPT_UDP_PORT) -#define IP_ACCEPT_LINK_LAYER_ADDRESSING 1 - -/** Some defines for DHCP to let link-layer-addressed packets through while the - * netif is down. - * To use this in your own application/protocol, define LWIP_IP_ACCEPT_UDP_PORT(port) - * to return 1 if the port is accepted and 0 if the port is not accepted. - */ -#if LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) -/* accept DHCP client port and custom port */ -#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (((port) == PP_NTOHS(DHCP_CLIENT_PORT)) \ - || (LWIP_IP_ACCEPT_UDP_PORT(port))) -#elif defined(LWIP_IP_ACCEPT_UDP_PORT) /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ -/* accept custom port only */ -#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (LWIP_IP_ACCEPT_UDP_PORT(port)) -#else /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ -/* accept DHCP client port only */ -#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) ((port) == PP_NTOHS(DHCP_CLIENT_PORT)) -#endif /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ - -#else /* LWIP_DHCP */ -#define IP_ACCEPT_LINK_LAYER_ADDRESSING 0 -#endif /* LWIP_DHCP */ - -/** The IP header ID of the next outgoing IP packet */ -static u16_t ip_id; - -#if LWIP_MULTICAST_TX_OPTIONS -/** The default netif used for multicast */ -static struct netif* ip4_default_multicast_netif; - -/** - * @ingroup ip4 - * Set a default netif for IPv4 multicast. */ -void -ip4_set_default_multicast_netif(struct netif* default_multicast_netif) -{ - ip4_default_multicast_netif = default_multicast_netif; -} -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - -#ifdef LWIP_HOOK_IP4_ROUTE_SRC -/** - * Source based IPv4 routing must be fully implemented in - * LWIP_HOOK_IP4_ROUTE_SRC(). This function only provides he parameters. - */ -struct netif * -ip4_route_src(const ip4_addr_t *dest, const ip4_addr_t *src) -{ - if (src != NULL) { - /* when src==NULL, the hook is called from ip4_route(dest) */ - struct netif *netif = LWIP_HOOK_IP4_ROUTE_SRC(dest, src); - if (netif != NULL) { - return netif; - } - } - return ip4_route(dest); -} -#endif /* LWIP_HOOK_IP4_ROUTE_SRC */ - -/** - * Finds the appropriate network interface for a given IP address. It - * searches the list of network interfaces linearly. A match is found - * if the masked IP address of the network interface equals the masked - * IP address given to the function. - * - * @param dest the destination IP address for which to find the route - * @return the netif on which to send to reach dest - */ -struct netif * -ip4_route(const ip4_addr_t *dest) -{ - struct netif *netif; - -#if LWIP_MULTICAST_TX_OPTIONS - /* Use administratively selected interface for multicast by default */ - if (ip4_addr_ismulticast(dest) && ip4_default_multicast_netif) { - return ip4_default_multicast_netif; - } -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - - /* iterate through netifs */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - /* is the netif up, does it have a link and a valid address? */ - if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) { - /* network mask matches? */ - if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) { - /* return netif on which to forward IP packet */ - return netif; - } - /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */ - if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) { - /* return netif on which to forward IP packet */ - return netif; - } - } - } - -#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF - /* loopif is disabled, looopback traffic is passed through any netif */ - if (ip4_addr_isloopback(dest)) { - /* don't check for link on loopback traffic */ - if (netif_default != NULL && netif_is_up(netif_default)) { - return netif_default; - } - /* default netif is not up, just use any netif for loopback traffic */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (netif_is_up(netif)) { - return netif; - } - } - return NULL; - } -#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ - -#ifdef LWIP_HOOK_IP4_ROUTE_SRC - netif = LWIP_HOOK_IP4_ROUTE_SRC(dest, NULL); - if (netif != NULL) { - return netif; - } -#elif defined(LWIP_HOOK_IP4_ROUTE) - netif = LWIP_HOOK_IP4_ROUTE(dest); - if (netif != NULL) { - return netif; - } -#endif - - if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || - ip4_addr_isany_val(*netif_ip4_addr(netif_default))) { - /* No matching netif found and default netif is not usable. - If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); - IP_STATS_INC(ip.rterr); - MIB2_STATS_INC(mib2.ipoutnoroutes); - return NULL; - } - - return netif_default; -} - -#if IP_FORWARD -/** - * Determine whether an IP address is in a reserved set of addresses - * that may not be forwarded, or whether datagrams to that destination - * may be forwarded. - * @param p the packet to forward - * @return 1: can forward 0: discard - */ -static int -ip4_canforward(struct pbuf *p) -{ - u32_t addr = lwip_htonl(ip4_addr_get_u32(ip4_current_dest_addr())); - - if (p->flags & PBUF_FLAG_LLBCAST) { - /* don't route link-layer broadcasts */ - return 0; - } - if ((p->flags & PBUF_FLAG_LLMCAST) && !IP_MULTICAST(addr)) { - /* don't route link-layer multicasts unless the destination address is an IP - multicast address */ - return 0; - } - if (IP_EXPERIMENTAL(addr)) { - return 0; - } - if (IP_CLASSA(addr)) { - u32_t net = addr & IP_CLASSA_NET; - if ((net == 0) || (net == ((u32_t)IP_LOOPBACKNET << IP_CLASSA_NSHIFT))) { - /* don't route loopback packets */ - return 0; - } - } - return 1; -} - -/** - * Forwards an IP packet. It finds an appropriate route for the - * packet, decrements the TTL value of the packet, adjusts the - * checksum and outputs the packet on the appropriate interface. - * - * @param p the packet to forward (p->payload points to IP header) - * @param iphdr the IP header of the input packet - * @param inp the netif on which this packet was received - */ -static void -ip4_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) -{ - struct netif *netif; - - PERF_START; - LWIP_UNUSED_ARG(inp); - - if (!ip4_canforward(p)) { - goto return_noroute; - } - - /* RFC3927 2.7: do not forward link-local addresses */ - if (ip4_addr_islinklocal(ip4_current_dest_addr())) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not forwarding LLA %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), - ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); - goto return_noroute; - } - - /* Find network interface where to forward this IP packet to. */ - netif = ip4_route_src(ip4_current_dest_addr(), ip4_current_src_addr()); - if (netif == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: no forwarding route for %"U16_F".%"U16_F".%"U16_F".%"U16_F" found\n", - ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), - ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); - /* @todo: send ICMP_DUR_NET? */ - goto return_noroute; - } -#if !IP_FORWARD_ALLOW_TX_ON_RX_NETIF - /* Do not forward packets onto the same network interface on which - * they arrived. */ - if (netif == inp) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not bouncing packets back on incoming interface.\n")); - goto return_noroute; - } -#endif /* IP_FORWARD_ALLOW_TX_ON_RX_NETIF */ - - /* decrement TTL */ - IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); - /* send ICMP if TTL == 0 */ - if (IPH_TTL(iphdr) == 0) { - MIB2_STATS_INC(mib2.ipinhdrerrors); -#if LWIP_ICMP - /* Don't send ICMP messages in response to ICMP messages */ - if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - } -#endif /* LWIP_ICMP */ - return; - } - - /* Incrementally update the IP checksum. */ - if (IPH_CHKSUM(iphdr) >= PP_HTONS(0xffffU - 0x100)) { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100) + 1); - } else { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100)); - } - - LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: forwarding packet to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), - ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); - - IP_STATS_INC(ip.fw); - MIB2_STATS_INC(mib2.ipforwdatagrams); - IP_STATS_INC(ip.xmit); - - PERF_STOP("ip4_forward"); - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > netif->mtu)) { - if ((IPH_OFFSET(iphdr) & PP_NTOHS(IP_DF)) == 0) { -#if IP_FRAG - ip4_frag(p, netif, ip4_current_dest_addr()); -#else /* IP_FRAG */ - /* @todo: send ICMP Destination Unreachable code 13 "Communication administratively prohibited"? */ -#endif /* IP_FRAG */ - } else { -#if LWIP_ICMP - /* send ICMP Destination Unreachable code 4: "Fragmentation Needed and DF Set" */ - icmp_dest_unreach(p, ICMP_DUR_FRAG); -#endif /* LWIP_ICMP */ - } - return; - } - /* transmit pbuf on chosen interface */ - netif->output(netif, p, ip4_current_dest_addr()); - return; -return_noroute: - MIB2_STATS_INC(mib2.ipoutnoroutes); -} -#endif /* IP_FORWARD */ - -#if LWIP_RIPPLE20 -/** - * parse ipv4 IP options - * return: < 0 if IP options contain invalid option, = 0 Ok. - */ -int ip4_parse_opt(u8 *opt, int len) -{ - int ret = 0; - u8 type, item_len; - - while (len > 1) { - type = *opt; - opt++; - item_len = *opt; - len -= item_len; - opt++; - - /* avoid infinite recusive */ - if (type != 0 && item_len == 0) - return -1; - - switch (type) { - case 0: - /* End of Option List */ - return ret; - case 7: { - /* RR Option */ - u8 *pointer = opt; - - if (*pointer < 4 || (*pointer % 4)) - return -1; - - break; - } - - } - - /* Forward to next option */ - opt += item_len - 2; - } - - return ret; -} -#endif /* LWIP_RIPPLE20 */ - -/** - * This function is called by the network interface device driver when - * an IP packet is received. The function does the basic checks of the - * IP header such as packet size being at least larger than the header - * size etc. If the packet was not destined for us, the packet is - * forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - * - * @param p the received IP packet (p->payload points to IP header) - * @param inp the netif on which this packet was received - * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't - * processed, but currently always returns ERR_OK) - */ -err_t -ip4_input(struct pbuf *p, struct netif *inp) -{ - struct ip_hdr *iphdr; - struct netif *netif; - u16_t iphdr_hlen; - u16_t iphdr_len; -#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP - int check_ip_src = 1; -#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP */ - - IP_STATS_INC(ip.recv); - MIB2_STATS_INC(mib2.ipinreceives); - - /* identify the IP header */ - iphdr = (struct ip_hdr *)p->payload; - if (IPH_V(iphdr) != 4) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr))); - ip4_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.err); - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipinhdrerrors); - return ERR_OK; - } - -#ifdef LWIP_HOOK_IP4_INPUT - if (LWIP_HOOK_IP4_INPUT(p, inp)) { - /* the packet has been eaten */ - return ERR_OK; - } -#endif - - /* obtain IP header length in number of 32-bit words */ - iphdr_hlen = IPH_HL(iphdr); - /* calculate IP header length in bytes */ - iphdr_hlen *= 4; - /* obtain ip length in bytes */ - iphdr_len = lwip_ntohs(IPH_LEN(iphdr)); - - /* Trim pbuf. This is especially required for packets < 60 bytes. */ - if (iphdr_len < p->tot_len) { - pbuf_realloc(p, iphdr_len); - } - -#if LWIP_RIPPLE20 - /* Parse IP options */ - if (iphdr_hlen > 20) { - u8 *opt = (u8*)p->payload; - if (ip4_parse_opt(opt + 20, iphdr_hlen - 20)) { - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to invalid IP options\n")); - return ERR_OK; - } - } -#endif - - /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ - if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) { - if (iphdr_hlen < IP_HLEN) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("ip4_input: short IP header (%"U16_F" bytes) received, IP packet dropped\n", iphdr_hlen)); - } - if (iphdr_hlen > p->len) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", - iphdr_hlen, p->len)); - } - if (iphdr_len > p->tot_len) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", - iphdr_len, p->tot_len)); - } - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.lenerr); - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipindiscards); - return ERR_OK; - } - - /* verify checksum */ -#if CHECKSUM_CHECK_IP - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_IP) { - if (inet_chksum(iphdr, iphdr_hlen) != 0) { - - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen))); - ip4_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.chkerr); - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipinhdrerrors); - return ERR_OK; - } - } -#endif - - /* copy IP addresses to aligned ip_addr_t */ - ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest); - ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src); - - /* match packet against an interface, i.e. is this packet for us? */ - if (ip4_addr_ismulticast(ip4_current_dest_addr())) { -#if LWIP_IGMP - if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, ip4_current_dest_addr()))) { - /* IGMP snooping switches need 0.0.0.0 to be allowed as source address (RFC 4541) */ - ip4_addr_t allsystems; - IP4_ADDR(&allsystems, 224, 0, 0, 1); - if (ip4_addr_cmp(ip4_current_dest_addr(), &allsystems) && - ip4_addr_isany(ip4_current_src_addr())) { - check_ip_src = 0; - } - netif = inp; - } else { - netif = NULL; - } -#else /* LWIP_IGMP */ - if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) { - netif = inp; - } else { - netif = NULL; - } -#endif /* LWIP_IGMP */ - } else { - /* start trying with inp. if that's not acceptable, start walking the - list of configured netifs. - 'first' is used as a boolean to mark whether we started walking the list */ - int first = 1; - netif = inp; - do { - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", - ip4_addr_get_u32(&iphdr->dest), ip4_addr_get_u32(netif_ip4_addr(netif)), - ip4_addr_get_u32(&iphdr->dest) & ip4_addr_get_u32(netif_ip4_netmask(netif)), - ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)), - ip4_addr_get_u32(&iphdr->dest) & ~ip4_addr_get_u32(netif_ip4_netmask(netif)))); - - /* interface is up and configured? */ - if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) { - /* unicast to this interface address? */ - if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || - /* or broadcast on this interface network address? */ - ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) -#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF - || (ip4_addr_get_u32(ip4_current_dest_addr()) == PP_HTONL(IPADDR_LOOPBACK)) -#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ - ) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - /* break out of for loop */ - break; - } -#if LWIP_AUTOIP - /* connections to link-local addresses must persist after changing - the netif's address (RFC3927 ch. 1.9) */ - if (autoip_accept_packet(netif, ip4_current_dest_addr())) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_input: LLA packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - /* break out of for loop */ - break; - } -#endif /* LWIP_AUTOIP */ - } - if (first) { -#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF - /* Packets sent to the loopback address must not be accepted on an - * interface that does not have the loopback address assigned to it, - * unless a non-loopback interface is used for loopback traffic. */ - if (ip4_addr_isloopback(ip4_current_dest_addr())) { - netif = NULL; - break; - } -#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ - first = 0; - netif = netif_list; - } else { - netif = netif->next; - } - if (netif == inp) { - netif = netif->next; - } - } while (netif != NULL); - } - -#if IP_ACCEPT_LINK_LAYER_ADDRESSING - /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed - * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. - * According to RFC 1542 section 3.1.1, referred by RFC 2131). - * - * If you want to accept private broadcast communication while a netif is down, - * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.: - * - * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345)) - */ - if (netif == NULL) { - /* remote port is DHCP server? */ - if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { - struct udp_hdr *udphdr = (struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen); - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n", - lwip_ntohs(udphdr->dest))); - if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n")); - netif = inp; - check_ip_src = 0; - } - } - } -#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ - - /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ -#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING - if (check_ip_src -#if IP_ACCEPT_LINK_LAYER_ADDRESSING - /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ - && !ip4_addr_isany_val(*ip4_current_src_addr()) -#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ - ) -#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */ - { - if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || - (ip4_addr_ismulticast(ip4_current_src_addr()))) { - /* packet source is not valid */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n")); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipinaddrerrors); - MIB2_STATS_INC(mib2.ipindiscards); - return ERR_OK; - } - } - - /* packet not for us? */ - if (netif == NULL) { - /* packet not for us, route or discard */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: packet not for us.\n")); -#if IP_FORWARD - /* non-broadcast packet? */ - if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), inp)) { - /* try to forward IP packet on (other) interfaces */ - ip4_forward(p, iphdr, inp); - } else -#endif /* IP_FORWARD */ - { - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipinaddrerrors); - MIB2_STATS_INC(mib2.ipindiscards); - } - pbuf_free(p); - return ERR_OK; - } - /* packet consists of multiple fragments? */ - if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { -#if IP_REASSEMBLY /* packet fragment reassembly code present? */ - LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n", - lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8))); - /* reassemble the packet*/ - p = ip4_reass(p); - /* packet not fully reassembled yet? */ - if (p == NULL) { - return ERR_OK; - } - iphdr = (struct ip_hdr *)p->payload; -#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", - lwip_ntohs(IPH_OFFSET(iphdr)))); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - /* unsupported protocol feature */ - MIB2_STATS_INC(mib2.ipinunknownprotos); - return ERR_OK; -#endif /* IP_REASSEMBLY */ - } - -#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */ - -#if LWIP_IGMP - /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */ - if ((iphdr_hlen > IP_HLEN) && (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) { -#else - if (iphdr_hlen > IP_HLEN) { -#endif /* LWIP_IGMP */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n")); - pbuf_free(p); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - /* unsupported protocol feature */ - MIB2_STATS_INC(mib2.ipinunknownprotos); - return ERR_OK; - } -#endif /* IP_OPTIONS_ALLOWED == 0 */ - - /* send to upper layers */ - LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n")); - ip4_debug_print(p); - LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); - - ip_data.current_netif = netif; - ip_data.current_input_netif = inp; - ip_data.current_ip4_header = iphdr; - ip_data.current_ip_header_tot_len = IPH_HL(iphdr) * 4; - -#if LWIP_RAW - /* raw input did not eat the packet? */ - if (raw_input(p, inp) == 0) -#endif /* LWIP_RAW */ - { - pbuf_header(p, -(s16_t)iphdr_hlen); /* Move to payload, no check necessary. */ - - switch (IPH_PROTO(iphdr)) { -#if LWIP_UDP - case IP_PROTO_UDP: -#if LWIP_UDPLITE - case IP_PROTO_UDPLITE: -#endif /* LWIP_UDPLITE */ - MIB2_STATS_INC(mib2.ipindelivers); - udp_input(p, inp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case IP_PROTO_TCP: - MIB2_STATS_INC(mib2.ipindelivers); - tcp_input(p, inp); - break; -#endif /* LWIP_TCP */ -#if LWIP_ICMP - case IP_PROTO_ICMP: - MIB2_STATS_INC(mib2.ipindelivers); - icmp_input(p, inp); - break; -#endif /* LWIP_ICMP */ -#if LWIP_IGMP - case IP_PROTO_IGMP: - igmp_input(p, inp, ip4_current_dest_addr()); - break; -#endif /* LWIP_IGMP */ - default: -#if LWIP_ICMP - /* send ICMP destination protocol unreachable unless is was a broadcast */ - if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && - !ip4_addr_ismulticast(ip4_current_dest_addr())) { - pbuf_header_force(p, iphdr_hlen); /* Move to ip header, no check necessary. */ - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PROTO); - } -#endif /* LWIP_ICMP */ - pbuf_free(p); - - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", (u16_t)IPH_PROTO(iphdr))); - - IP_STATS_INC(ip.proterr); - IP_STATS_INC(ip.drop); - MIB2_STATS_INC(mib2.ipinunknownprotos); - } - } - - /* @todo: this is not really necessary... */ - ip_data.current_netif = NULL; - ip_data.current_input_netif = NULL; - ip_data.current_ip4_header = NULL; - ip_data.current_ip_header_tot_len = 0; - ip4_addr_set_any(ip4_current_src_addr()); - ip4_addr_set_any(ip4_current_dest_addr()); - - return ERR_OK; -} - -/** - * Sends an IP packet on a network interface. This function constructs - * the IP header and calculates the IP header checksum. If the source - * IP address is NULL, the IP address of the outgoing network - * interface is filled in as source address. - * If the destination IP address is LWIP_IP_HDRINCL, p is assumed to already - * include an IP header and p->payload points to it instead of the data. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IP header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * @param netif the netif on which to send this packet - * @return ERR_OK if the packet was sent OK - * ERR_BUF if p doesn't have enough space for IP/LINK headers - * returns errors returned by netif->output - * - * @note ip_id: RFC791 "some host may be able to simply use - * unique identifiers independent of destination" - */ -err_t -ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, - u8_t proto, struct netif *netif) -{ -#if IP_OPTIONS_SEND - return ip4_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0); -} - -/** - * Same as ip_output_if() but with the possibility to include IP options: - * - * @ param ip_options pointer to the IP options, copied into the IP header - * @ param optlen length of ip_options - */ -err_t -ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen) -{ -#endif /* IP_OPTIONS_SEND */ - const ip4_addr_t *src_used = src; - if (dest != LWIP_IP_HDRINCL) { - if (ip4_addr_isany(src)) { - src_used = netif_ip4_addr(netif); - } - } - -#if IP_OPTIONS_SEND - return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif, - ip_options, optlen); -#else /* IP_OPTIONS_SEND */ - return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif); -#endif /* IP_OPTIONS_SEND */ -} - -/** - * Same as ip_output_if() but 'src' address is not replaced by netif address - * when it is 'any'. - */ -err_t -ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, - u8_t proto, struct netif *netif) -{ -#if IP_OPTIONS_SEND - return ip4_output_if_opt_src(p, src, dest, ttl, tos, proto, netif, NULL, 0); -} - -/** - * Same as ip_output_if_opt() but 'src' address is not replaced by netif address - * when it is 'any'. - */ -err_t -ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen) -{ -#endif /* IP_OPTIONS_SEND */ - struct ip_hdr *iphdr; - ip4_addr_t dest_addr; -#if CHECKSUM_GEN_IP_INLINE - u32_t chk_sum = 0; -#endif /* CHECKSUM_GEN_IP_INLINE */ - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - MIB2_STATS_INC(mib2.ipoutrequests); - - /* Should the IP header be generated or is it already included in p? */ - if (dest != LWIP_IP_HDRINCL) { - u16_t ip_hlen = IP_HLEN; -#if IP_OPTIONS_SEND - u16_t optlen_aligned = 0; - if (optlen != 0) { -#if CHECKSUM_GEN_IP_INLINE - int i; -#endif /* CHECKSUM_GEN_IP_INLINE */ - /* round up to a multiple of 4 */ - optlen_aligned = ((optlen + 3) & ~3); - ip_hlen += optlen_aligned; - /* First write in the IP options */ - if (pbuf_header(p, optlen_aligned)) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output_if_opt: not enough room for IP options in pbuf\n")); - IP_STATS_INC(ip.err); - MIB2_STATS_INC(mib2.ipoutdiscards); - return ERR_BUF; - } - MEMCPY(p->payload, ip_options, optlen); - if (optlen < optlen_aligned) { - /* zero the remaining bytes */ - memset(((char*)p->payload) + optlen, 0, optlen_aligned - optlen); - } -#if CHECKSUM_GEN_IP_INLINE - for (i = 0; i < optlen_aligned/2; i++) { - chk_sum += ((u16_t*)p->payload)[i]; - } -#endif /* CHECKSUM_GEN_IP_INLINE */ - } -#endif /* IP_OPTIONS_SEND */ - /* generate IP header */ - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n")); - - IP_STATS_INC(ip.err); - MIB2_STATS_INC(mib2.ipoutdiscards); - return ERR_BUF; - } - - iphdr = (struct ip_hdr *)p->payload; - LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", - (p->len >= sizeof(struct ip_hdr))); - - IPH_TTL_SET(iphdr, ttl); - IPH_PROTO_SET(iphdr, proto); -#if CHECKSUM_GEN_IP_INLINE - chk_sum += PP_NTOHS(proto | (ttl << 8)); -#endif /* CHECKSUM_GEN_IP_INLINE */ - - /* dest cannot be NULL here */ - ip4_addr_copy(iphdr->dest, *dest); -#if CHECKSUM_GEN_IP_INLINE - chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; - chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; -#endif /* CHECKSUM_GEN_IP_INLINE */ - - IPH_VHL_SET(iphdr, 4, ip_hlen / 4); - IPH_TOS_SET(iphdr, tos); -#if CHECKSUM_GEN_IP_INLINE - chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8)); -#endif /* CHECKSUM_GEN_IP_INLINE */ - IPH_LEN_SET(iphdr, lwip_htons(p->tot_len)); -#if CHECKSUM_GEN_IP_INLINE - chk_sum += iphdr->_len; -#endif /* CHECKSUM_GEN_IP_INLINE */ - IPH_OFFSET_SET(iphdr, 0); - IPH_ID_SET(iphdr, lwip_htons(ip_id)); -#if CHECKSUM_GEN_IP_INLINE - chk_sum += iphdr->_id; -#endif /* CHECKSUM_GEN_IP_INLINE */ - ++ip_id; - - if (src == NULL) { - ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4); - } else { - /* src cannot be NULL here */ - ip4_addr_copy(iphdr->src, *src); - } - -#if CHECKSUM_GEN_IP_INLINE - chk_sum += ip4_addr_get_u32(&iphdr->src) & 0xFFFF; - chk_sum += ip4_addr_get_u32(&iphdr->src) >> 16; - chk_sum = (chk_sum >> 16) + (chk_sum & 0xFFFF); - chk_sum = (chk_sum >> 16) + chk_sum; - chk_sum = ~chk_sum; - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { - iphdr->_chksum = (u16_t)chk_sum; /* network order */ - } -#if LWIP_CHECKSUM_CTRL_PER_NETIF - else { - IPH_CHKSUM_SET(iphdr, 0); - } -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ -#else /* CHECKSUM_GEN_IP_INLINE */ - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen)); - } -#endif /* CHECKSUM_GEN_IP */ -#endif /* CHECKSUM_GEN_IP_INLINE */ - } else { - /* IP header already included in p */ - iphdr = (struct ip_hdr *)p->payload; - ip4_addr_copy(dest_addr, iphdr->dest); - dest = &dest_addr; - } - - IP_STATS_INC(ip.xmit); - - LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num)); - ip4_debug_print(p); - -#if ENABLE_LOOPBACK - if (ip4_addr_cmp(dest, netif_ip4_addr(netif)) -#if !LWIP_HAVE_LOOPIF - || ip4_addr_isloopback(dest) -#endif /* !LWIP_HAVE_LOOPIF */ - ) { - /* Packet to self, enqueue it for loopback */ - LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()")); - return netif_loop_output(netif, p); - } -#if LWIP_MULTICAST_TX_OPTIONS - if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) { - netif_loop_output(netif, p); - } -#endif /* LWIP_MULTICAST_TX_OPTIONS */ -#endif /* ENABLE_LOOPBACK */ -#if IP_FRAG - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > netif->mtu)) { - return ip4_frag(p, netif, dest); - } -#endif /* IP_FRAG */ - - LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n")); - return netif->output(netif, p, dest); -} - -/** - * Simple interface to ip_output_if. It finds the outgoing network - * interface and calls upon ip_output_if to do the actual work. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IP header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto) -{ - struct netif *netif; - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - if ((netif = ip4_route_src(dest, src)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - return ip4_output_if(p, src, dest, ttl, tos, proto, netif); -} - -#if LWIP_NETIF_HWADDRHINT -/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint - * before calling ip_output_if. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IP header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * @param addr_hint address hint pointer set to netif->addr_hint before - * calling ip_output_if() - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint) -{ - struct netif *netif; - err_t err; - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - if ((netif = ip4_route_src(dest, src)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - NETIF_SET_HWADDRHINT(netif, addr_hint); - err = ip4_output_if(p, src, dest, ttl, tos, proto, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - - return err; -} -#endif /* LWIP_NETIF_HWADDRHINT*/ - -#if IP_DEBUG -/* Print an IP header by using LWIP_DEBUGF - * @param p an IP packet, p->payload pointing to the IP header - */ -void -ip4_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", - (u16_t)IPH_V(iphdr), - (u16_t)IPH_HL(iphdr), - (u16_t)IPH_TOS(iphdr), - lwip_ntohs(IPH_LEN(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", - lwip_ntohs(IPH_ID(iphdr)), - (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 15 & 1), - (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 14 & 1), - (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 13 & 1), - (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", - (u16_t)IPH_TTL(iphdr), - (u16_t)IPH_PROTO(iphdr), - lwip_ntohs(IPH_CHKSUM(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", - ip4_addr1_16(&iphdr->src), - ip4_addr2_16(&iphdr->src), - ip4_addr3_16(&iphdr->src), - ip4_addr4_16(&iphdr->src))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", - ip4_addr1_16(&iphdr->dest), - ip4_addr2_16(&iphdr->dest), - ip4_addr3_16(&iphdr->dest), - ip4_addr4_16(&iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ - -#endif /* LWIP_IPV4 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_addr.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_addr.c deleted file mode 100644 index 2d479923bd55c014df614cf24b857637133fbf39..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_addr.c +++ /dev/null @@ -1,331 +0,0 @@ -/** - * @file - * This is the IPv4 address tools implementation. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 - -#include "lwip/ip_addr.h" -#include "lwip/netif.h" - -/* used by IP4_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ -const ip_addr_t ip_addr_any = IPADDR4_INIT(IPADDR_ANY); -const ip_addr_t ip_addr_broadcast = IPADDR4_INIT(IPADDR_BROADCAST); - -/** - * Determine if an address is a broadcast address on a network interface - * - * @param addr address to be checked - * @param netif the network interface against which the address is checked - * @return returns non-zero if the address is a broadcast address - */ -u8_t -ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif) -{ - ip4_addr_t ipaddr; - ip4_addr_set_u32(&ipaddr, addr); - - /* all ones (broadcast) or all zeroes (old skool broadcast) */ - if ((~addr == IPADDR_ANY) || - (addr == IPADDR_ANY)) { - return 1; - /* no broadcast support on this network interface? */ - } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { - /* the given address cannot be a broadcast address - * nor can we check against any broadcast addresses */ - return 0; - /* address matches network interface address exactly? => no broadcast */ - } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) { - return 0; - /* on the same (sub) network... */ - } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) - /* ...and host identifier bits are all ones? =>... */ - && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == - (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) { - /* => network broadcast address */ - return 1; - } else { - return 0; - } -} - -/** Checks if a netmask is valid (starting with ones, then only zeros) - * - * @param netmask the IPv4 netmask to check (in network byte order!) - * @return 1 if the netmask is valid, 0 if it is not - */ -u8_t -ip4_addr_netmask_valid(u32_t netmask) -{ - u32_t mask; - u32_t nm_hostorder = lwip_htonl(netmask); - - /* first, check for the first zero */ - for (mask = 1UL << 31 ; mask != 0; mask >>= 1) { - if ((nm_hostorder & mask) == 0) { - break; - } - } - /* then check that there is no one */ - for (; mask != 0; mask >>= 1) { - if ((nm_hostorder & mask) != 0) { - /* there is a one after the first zero -> invalid */ - return 0; - } - } - /* no one after the first zero -> valid */ - return 1; -} - -/* Here for now until needed in other places in lwIP */ -#ifndef isprint -#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) -#define isprint(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') -#endif - -/** - * Ascii internet address interpretation routine. - * The value returned is in network order. - * - * @param cp IP address in ascii representation (e.g. "127.0.0.1") - * @return ip address in network order - */ -u32_t -ipaddr_addr(const char *cp) -{ - ip4_addr_t val; - - if (ip4addr_aton(cp, &val)) { - return ip4_addr_get_u32(&val); - } - return (IPADDR_NONE); -} - -/** - * Check whether "cp" is a valid ascii representation - * of an Internet address and convert to a binary address. - * Returns 1 if the address is valid, 0 if not. - * This replaces inet_addr, the return value from which - * cannot distinguish between failure and a local broadcast address. - * - * @param cp IP address in ascii representation (e.g. "127.0.0.1") - * @param addr pointer to which to save the ip address in network order - * @return 1 if cp could be converted to addr, 0 on failure - */ -int -ip4addr_aton(const char *cp, ip4_addr_t *addr) -{ - u32_t val; - u8_t base; - char c; - u32_t parts[4]; - u32_t *pp = parts; - - c = *cp; - for (;;) { - /* - * Collect number up to ``.''. - * Values are specified as for C: - * 0x=hex, 0=octal, 1-9=decimal. - */ - if (!isdigit(c)) { - return 0; - } - val = 0; - base = 10; - if (c == '0') { - c = *++cp; - if (c == 'x' || c == 'X') { - base = 16; - c = *++cp; - } else { - base = 8; - } - } - for (;;) { - if (isdigit(c)) { - val = (val * base) + (u32_t)(c - '0'); - c = *++cp; - } else if (base == 16 && isxdigit(c)) { - val = (val << 4) | (u32_t)(c + 10 - (islower(c) ? 'a' : 'A')); - c = *++cp; - } else { - break; - } - } - if (c == '.') { - /* - * Internet format: - * a.b.c.d - * a.b.c (with c treated as 16 bits) - * a.b (with b treated as 24 bits) - */ - if (pp >= parts + 3) { - return 0; - } - *pp++ = val; - c = *++cp; - } else { - break; - } - } - /* - * Check for trailing characters. - */ - if (c != '\0' && !isspace(c)) { - return 0; - } - /* - * Concoct the address according to - * the number of parts specified. - */ - switch (pp - parts + 1) { - - case 0: - return 0; /* initial nondigit */ - - case 1: /* a -- 32 bits */ - break; - - case 2: /* a.b -- 8.24 bits */ - if (val > 0xffffffUL) { - return 0; - } - if (parts[0] > 0xff) { - return 0; - } - val |= parts[0] << 24; - break; - - case 3: /* a.b.c -- 8.8.16 bits */ - if (val > 0xffff) { - return 0; - } - if ((parts[0] > 0xff) || (parts[1] > 0xff)) { - return 0; - } - val |= (parts[0] << 24) | (parts[1] << 16); - break; - - case 4: /* a.b.c.d -- 8.8.8.8 bits */ - if (val > 0xff) { - return 0; - } - if ((parts[0] > 0xff) || (parts[1] > 0xff) || (parts[2] > 0xff)) { - return 0; - } - val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); - break; - default: - LWIP_ASSERT("unhandled", 0); - break; - } - if (addr) { - ip4_addr_set_u32(addr, lwip_htonl(val)); - } - return 1; -} - -/** - * Convert numeric IP address into decimal dotted ASCII representation. - * returns ptr to static buffer; not reentrant! - * - * @param addr ip address in network order to convert - * @return pointer to a global static (!) buffer that holds the ASCII - * representation of addr - */ -char* -ip4addr_ntoa(const ip4_addr_t *addr) -{ - static char str[IP4ADDR_STRLEN_MAX]; - return ip4addr_ntoa_r(addr, str, IP4ADDR_STRLEN_MAX); -} - -/** - * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used. - * - * @param addr ip address in network order to convert - * @param buf target buffer where the string is stored - * @param buflen length of buf - * @return either pointer to buf which now holds the ASCII - * representation of addr or NULL if buf was too small - */ -char* -ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen) -{ - u32_t s_addr; - char inv[3]; - char *rp; - u8_t *ap; - u8_t rem; - u8_t n; - u8_t i; - int len = 0; - - s_addr = ip4_addr_get_u32(addr); - - rp = buf; - ap = (u8_t *)&s_addr; - for (n = 0; n < 4; n++) { - i = 0; - do { - rem = *ap % (u8_t)10; - *ap /= (u8_t)10; - inv[i++] = (char)('0' + rem); - } while (*ap); - while (i--) { - if (len++ >= buflen) { - return NULL; - } - *rp++ = inv[i]; - } - if (len++ >= buflen) { - return NULL; - } - *rp++ = '.'; - ap++; - } - *--rp = 0; - return buf; -} - -#endif /* LWIP_IPV4 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_frag.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_frag.c deleted file mode 100644 index 57fb44cbb366140285cf3114b8ca280a8793b054..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv4/ip4_frag.c +++ /dev/null @@ -1,831 +0,0 @@ -/** - * @file - * This is the IPv4 packet segmentation and reassembly implementation. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * Simon Goldschmidt - * original reassembly code by Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV4 - -#include "lwip/ip4_frag.h" -#include "lwip/def.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/stats.h" -#include "lwip/icmp.h" - -#include - -#if IP_REASSEMBLY -/** - * The IP reassembly code currently has the following limitations: - * - IP header options are not supported - * - fragments must not overlap (e.g. due to different routes), - * currently, overlapping or duplicate fragments are thrown away - * if IP_REASS_CHECK_OVERLAP=1 (the default)! - * - * @todo: work with IP header options - */ - -/** Setting this to 0, you can turn off checking the fragments for overlapping - * regions. The code gets a little smaller. Only use this if you know that - * overlapping won't occur on your network! */ -#ifndef IP_REASS_CHECK_OVERLAP -#define IP_REASS_CHECK_OVERLAP 1 -#endif /* IP_REASS_CHECK_OVERLAP */ - -/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is - * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller. - * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA - * is set to 1, so one datagram can be reassembled at a time, only. */ -#ifndef IP_REASS_FREE_OLDEST -#define IP_REASS_FREE_OLDEST 1 -#endif /* IP_REASS_FREE_OLDEST */ - -#define IP_REASS_FLAG_LASTFRAG 0x01 - -/** This is a helper struct which holds the starting - * offset and the ending offset of this fragment to - * easily chain the fragments. - * It has the same packing requirements as the IP header, since it replaces - * the IP header in memory in incoming fragments (after copying it) to keep - * track of the various fragments. (-> If the IP header doesn't need packing, - * this struct doesn't need packing, too.) - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_reass_helper { - PACK_STRUCT_FIELD(struct pbuf *next_pbuf); - PACK_STRUCT_FIELD(u16_t start); - PACK_STRUCT_FIELD(u16_t end); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB) \ - (ip4_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \ - ip4_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \ - IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0 - -/* global variables */ -static struct ip_reassdata *reassdatagrams; -static u16_t ip_reass_pbufcount; - -/* function prototypes */ -static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); -static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); - -/** - * Reassembly timer base function - * for both NO_SYS == 0 and 1 (!). - * - * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). - */ -void -ip_reass_tmr(void) -{ - struct ip_reassdata *r, *prev = NULL; - - r = reassdatagrams; - while (r != NULL) { - /* Decrement the timer. Once it reaches 0, - * clean up the incomplete fragment assembly */ - if (r->timer > 0) { - r->timer--; - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)r->timer)); - prev = r; - r = r->next; - } else { - /* reassembly timed out */ - struct ip_reassdata *tmp; - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); - tmp = r; - /* get the next pointer before freeing */ - r = r->next; - /* free the helper struct and all enqueued pbufs */ - ip_reass_free_complete_datagram(tmp, prev); - } - } -} - -/** - * Free a datagram (struct ip_reassdata) and all its pbufs. - * Updates the total count of enqueued pbufs (ip_reass_pbufcount), - * SNMP counters and sends an ICMP time exceeded packet. - * - * @param ipr datagram to free - * @param prev the previous datagram in the linked list - * @return the number of pbufs freed - */ -static int -ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) -{ - u16_t pbufs_freed = 0; - u16_t clen; - struct pbuf *p; - struct ip_reass_helper *iprh; - - LWIP_ASSERT("prev != ipr", prev != ipr); - if (prev != NULL) { - LWIP_ASSERT("prev->next == ipr", prev->next == ipr); - } - - MIB2_STATS_INC(mib2.ipreasmfails); -#if LWIP_ICMP - iprh = (struct ip_reass_helper *)ipr->p->payload; - if (iprh->start == 0) { - /* The first fragment was received, send ICMP time exceeded. */ - /* First, de-queue the first pbuf from r->p. */ - p = ipr->p; - ipr->p = iprh->next_pbuf; - /* Then, copy the original header into it. */ - SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); - icmp_time_exceeded(p, ICMP_TE_FRAG); - clen = pbuf_clen(p); - LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); - pbufs_freed += clen; - pbuf_free(p); - } -#endif /* LWIP_ICMP */ - - /* First, free all received pbufs. The individual pbufs need to be released - separately as they have not yet been chained */ - p = ipr->p; - while (p != NULL) { - struct pbuf *pcur; - iprh = (struct ip_reass_helper *)p->payload; - pcur = p; - /* get the next pointer before freeing */ - p = iprh->next_pbuf; - clen = pbuf_clen(pcur); - LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); - pbufs_freed += clen; - pbuf_free(pcur); - } - /* Then, unchain the struct ip_reassdata from the list and free it. */ - ip_reass_dequeue_datagram(ipr, prev); - LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= pbufs_freed); - ip_reass_pbufcount -= pbufs_freed; - - return pbufs_freed; -} - -#if IP_REASS_FREE_OLDEST -/** - * Free the oldest datagram to make room for enqueueing new fragments. - * The datagram 'fraghdr' belongs to is not freed! - * - * @param fraghdr IP header of the current fragment - * @param pbufs_needed number of pbufs needed to enqueue - * (used for freeing other datagrams if not enough space) - * @return the number of pbufs freed - */ -static int -ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) -{ - /* @todo Can't we simply remove the last datagram in the - * linked list behind reassdatagrams? - */ - struct ip_reassdata *r, *oldest, *prev, *oldest_prev; - int pbufs_freed = 0, pbufs_freed_current; - int other_datagrams; - - /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, - * but don't free the datagram that 'fraghdr' belongs to! */ - do { - oldest = NULL; - prev = NULL; - oldest_prev = NULL; - other_datagrams = 0; - r = reassdatagrams; - while (r != NULL) { - if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { - /* Not the same datagram as fraghdr */ - other_datagrams++; - if (oldest == NULL) { - oldest = r; - oldest_prev = prev; - } else if (r->timer <= oldest->timer) { - /* older than the previous oldest */ - oldest = r; - oldest_prev = prev; - } - } - if (r->next != NULL) { - prev = r; - } - r = r->next; - } - if (oldest != NULL) { - pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev); - pbufs_freed += pbufs_freed_current; - } - } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); - return pbufs_freed; -} -#endif /* IP_REASS_FREE_OLDEST */ - -/** - * Enqueues a new fragment into the fragment queue - * @param fraghdr points to the new fragments IP hdr - * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) - * @return A pointer to the queue location into which the fragment was enqueued - */ -static struct ip_reassdata* -ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) -{ - struct ip_reassdata* ipr; -#if ! IP_REASS_FREE_OLDEST - LWIP_UNUSED_ARG(clen); -#endif - - /* No matching previous fragment found, allocate a new reassdata struct */ - ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); - if (ipr == NULL) { -#if IP_REASS_FREE_OLDEST - if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { - ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); - } - if (ipr == NULL) -#endif /* IP_REASS_FREE_OLDEST */ - { - IPFRAG_STATS_INC(ip_frag.memerr); - LWIP_DEBUGF(IP_REASS_DEBUG,("Failed to alloc reassdata struct\n")); - return NULL; - } - } - memset(ipr, 0, sizeof(struct ip_reassdata)); - ipr->timer = IP_REASS_MAXAGE; - - /* enqueue the new structure to the front of the list */ - ipr->next = reassdatagrams; - reassdatagrams = ipr; - /* copy the ip header for later tests and input */ - /* @todo: no ip options supported? */ - SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); - return ipr; -} - -/** - * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. - * @param ipr points to the queue entry to dequeue - */ -static void -ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) -{ - /* dequeue the reass struct */ - if (reassdatagrams == ipr) { - /* it was the first in the list */ - reassdatagrams = ipr->next; - } else { - /* it wasn't the first, so it must have a valid 'prev' */ - LWIP_ASSERT("sanity check linked list", prev != NULL); - prev->next = ipr->next; - } - - /* now we can free the ip_reassdata struct */ - memp_free(MEMP_REASSDATA, ipr); -} - -/** - * Chain a new pbuf into the pbuf list that composes the datagram. The pbuf list - * will grow over time as new pbufs are rx. - * Also checks that the datagram passes basic continuity checks (if the last - * fragment was received at least once). - * @param ipr points to the reassembly state - * @param new_p points to the pbuf for the current fragment - * @return 0 if invalid, >0 otherwise - */ -static int -ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p) -{ - struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL; - struct pbuf *q; - u16_t offset, len; - struct ip_hdr *fraghdr; - int valid = 1; - - /* Extract length and fragment offset from current fragment */ - fraghdr = (struct ip_hdr*)new_p->payload; - len = lwip_ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; - offset = (lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; - - /* overwrite the fragment's ip header from the pbuf with our helper struct, - * and setup the embedded helper structure. */ - /* make sure the struct ip_reass_helper fits into the IP header */ - LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", - sizeof(struct ip_reass_helper) <= IP_HLEN); - iprh = (struct ip_reass_helper*)new_p->payload; - iprh->next_pbuf = NULL; - iprh->start = offset; - iprh->end = offset + len; - - /* Iterate through until we either get to the end of the list (append), - * or we find one with a larger offset (insert). */ - for (q = ipr->p; q != NULL;) { - iprh_tmp = (struct ip_reass_helper*)q->payload; - if (iprh->start < iprh_tmp->start) { - /* the new pbuf should be inserted before this */ - iprh->next_pbuf = q; - if (iprh_prev != NULL) { - /* not the fragment with the lowest offset */ -#if IP_REASS_CHECK_OVERLAP - if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { - /* fragment overlaps with previous or following, throw away */ - goto freepbuf; - } -#endif /* IP_REASS_CHECK_OVERLAP */ - iprh_prev->next_pbuf = new_p; - } else { - /* fragment with the lowest offset */ - ipr->p = new_p; - } - break; - } else if (iprh->start == iprh_tmp->start) { - /* received the same datagram twice: no need to keep the datagram */ - goto freepbuf; -#if IP_REASS_CHECK_OVERLAP - } else if (iprh->start < iprh_tmp->end) { - /* overlap: no need to keep the new datagram */ - goto freepbuf; -#endif /* IP_REASS_CHECK_OVERLAP */ - } else { - /* Check if the fragments received so far have no holes. */ - if (iprh_prev != NULL) { - if (iprh_prev->end != iprh_tmp->start) { - /* There is a fragment missing between the current - * and the previous fragment */ - valid = 0; - } - } - } - q = iprh_tmp->next_pbuf; - iprh_prev = iprh_tmp; - } - - /* If q is NULL, then we made it to the end of the list. Determine what to do now */ - if (q == NULL) { - if (iprh_prev != NULL) { - /* this is (for now), the fragment with the highest offset: - * chain it to the last fragment */ -#if IP_REASS_CHECK_OVERLAP - LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); -#endif /* IP_REASS_CHECK_OVERLAP */ - iprh_prev->next_pbuf = new_p; - if (iprh_prev->end != iprh->start) { - valid = 0; - } - } else { -#if IP_REASS_CHECK_OVERLAP - LWIP_ASSERT("no previous fragment, this must be the first fragment!", - ipr->p == NULL); -#endif /* IP_REASS_CHECK_OVERLAP */ - /* this is the first fragment we ever received for this ip datagram */ - ipr->p = new_p; - } - } - - /* At this point, the validation part begins: */ - /* If we already received the last fragment */ - if ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0) { - /* and had no holes so far */ - if (valid) { - /* then check if the rest of the fragments is here */ - /* Check if the queue starts with the first datagram */ - if ((ipr->p == NULL) || (((struct ip_reass_helper*)ipr->p->payload)->start != 0)) { - valid = 0; - } else { - /* and check that there are no holes after this datagram */ - iprh_prev = iprh; - q = iprh->next_pbuf; - while (q != NULL) { - iprh = (struct ip_reass_helper*)q->payload; - if (iprh_prev->end != iprh->start) { - valid = 0; - break; - } - iprh_prev = iprh; - q = iprh->next_pbuf; - } - /* if still valid, all fragments are received - * (because to the MF==0 already arrived */ - if (valid) { - LWIP_ASSERT("sanity check", ipr->p != NULL); - LWIP_ASSERT("sanity check", - ((struct ip_reass_helper*)ipr->p->payload) != iprh); - LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", - iprh->next_pbuf == NULL); - LWIP_ASSERT("validate_datagram:datagram end!=datagram len", - iprh->end == ipr->datagram_len); - } - } - } - /* If valid is 0 here, there are some fragments missing in the middle - * (since MF == 0 has already arrived). Such datagrams simply time out if - * no more fragments are received... */ - return valid; - } - /* If we come here, not all fragments were received, yet! */ - return 0; /* not yet valid! */ -#if IP_REASS_CHECK_OVERLAP -freepbuf: - ip_reass_pbufcount -= pbuf_clen(new_p); - pbuf_free(new_p); - return 0; -#endif /* IP_REASS_CHECK_OVERLAP */ -} - -/** - * Reassembles incoming IP fragments into an IP datagram. - * - * @param p points to a pbuf chain of the fragment - * @return NULL if reassembly is incomplete, ? otherwise - */ -struct pbuf * -ip4_reass(struct pbuf *p) -{ - struct pbuf *r; - struct ip_hdr *fraghdr; - struct ip_reassdata *ipr; - struct ip_reass_helper *iprh; - u16_t offset, len, clen; - - IPFRAG_STATS_INC(ip_frag.recv); - MIB2_STATS_INC(mib2.ipreasmreqds); - - fraghdr = (struct ip_hdr*)p->payload; - - if ((IPH_HL(fraghdr) * 4) != IP_HLEN) { - LWIP_DEBUGF(IP_REASS_DEBUG,("ip4_reass: IP options currently not supported!\n")); - IPFRAG_STATS_INC(ip_frag.err); - goto nullreturn; - } - - offset = (lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; - len = lwip_ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; - - /* Check if we are allowed to enqueue more datagrams. */ - clen = pbuf_clen(p); - if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { -#if IP_REASS_FREE_OLDEST - if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || - ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) -#endif /* IP_REASS_FREE_OLDEST */ - { - /* No datagram could be freed and still too many pbufs enqueued */ - LWIP_DEBUGF(IP_REASS_DEBUG,("ip4_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n", - ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS)); - IPFRAG_STATS_INC(ip_frag.memerr); - /* @todo: send ICMP time exceeded here? */ - /* drop this pbuf */ - goto nullreturn; - } - } - - /* Look for the datagram the fragment belongs to in the current datagram queue, - * remembering the previous in the queue for later dequeueing. */ - for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { - /* Check if the incoming fragment matches the one currently present - in the reassembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n", - lwip_ntohs(IPH_ID(fraghdr)))); - IPFRAG_STATS_INC(ip_frag.cachehit); - break; - } - } - - if (ipr == NULL) { - /* Enqueue a new datagram into the datagram queue */ - ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); - /* Bail if unable to enqueue */ - if (ipr == NULL) { - goto nullreturn; - } - } else { - if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && - ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { - /* ipr->iphdr is not the header from the first fragment, but fraghdr is - * -> copy fraghdr into ipr->iphdr since we want to have the header - * of the first fragment (for ICMP time exceeded and later, for copying - * all options, if supported)*/ - SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); - } - } - /* Track the current number of pbufs current 'in-flight', in order to limit - the number of fragments that may be enqueued at any one time */ - ip_reass_pbufcount += clen; - - /* At this point, we have either created a new entry or pointing - * to an existing one */ - - /* check for 'no more fragments', and update queue entry*/ - if ((IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0) { - ipr->flags |= IP_REASS_FLAG_LASTFRAG; - ipr->datagram_len = offset + len; - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip4_reass: last fragment seen, total len %"S16_F"\n", - ipr->datagram_len)); - } - /* find the right place to insert this pbuf */ - /* @todo: trim pbufs if fragments are overlapping */ - if (ip_reass_chain_frag_into_datagram_and_validate(ipr, p)) { - struct ip_reassdata *ipr_prev; - /* the totally last fragment (flag more fragments = 0) was received at least - * once AND all fragments are received */ - ipr->datagram_len += IP_HLEN; - - /* save the second pbuf before copying the header over the pointer */ - r = ((struct ip_reass_helper*)ipr->p->payload)->next_pbuf; - - /* copy the original ip header back to the first pbuf */ - fraghdr = (struct ip_hdr*)(ipr->p->payload); - SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); - IPH_LEN_SET(fraghdr, lwip_htons(ipr->datagram_len)); - IPH_OFFSET_SET(fraghdr, 0); - IPH_CHKSUM_SET(fraghdr, 0); - /* @todo: do we need to set/calculate the correct checksum? */ -#if CHECKSUM_GEN_IP - IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) { - IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); - } -#endif /* CHECKSUM_GEN_IP */ - - p = ipr->p; - - /* chain together the pbufs contained within the reass_data list. */ - while (r != NULL) { - iprh = (struct ip_reass_helper*)r->payload; - - /* hide the ip header for every succeeding fragment */ - pbuf_header(r, -IP_HLEN); - pbuf_cat(p, r); - r = iprh->next_pbuf; - } - - /* find the previous entry in the linked list */ - if (ipr == reassdatagrams) { - ipr_prev = NULL; - } else { - for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { - if (ipr_prev->next == ipr) { - break; - } - } - } - - /* release the sources allocate for the fragment queue entry */ - ip_reass_dequeue_datagram(ipr, ipr_prev); - - /* and adjust the number of pbufs currently queued for reassembly. */ - ip_reass_pbufcount -= pbuf_clen(p); - - MIB2_STATS_INC(mib2.ipreasmoks); - - /* Return the pbuf chain */ - return p; - } - /* the datagram is not (yet?) reassembled completely */ - LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); - return NULL; - -nullreturn: - LWIP_DEBUGF(IP_REASS_DEBUG,("ip4_reass: nullreturn\n")); - IPFRAG_STATS_INC(ip_frag.drop); - pbuf_free(p); - return NULL; -} -#endif /* IP_REASSEMBLY */ - -#if IP_FRAG -#if !LWIP_NETIF_TX_SINGLE_PBUF -/** Allocate a new struct pbuf_custom_ref */ -static struct pbuf_custom_ref* -ip_frag_alloc_pbuf_custom_ref(void) -{ - return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF); -} - -/** Free a struct pbuf_custom_ref */ -static void -ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p) -{ - LWIP_ASSERT("p != NULL", p != NULL); - memp_free(MEMP_FRAG_PBUF, p); -} - -/** Free-callback function to free a 'struct pbuf_custom_ref', called by - * pbuf_free. */ -static void -ipfrag_free_pbuf_custom(struct pbuf *p) -{ - struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p; - LWIP_ASSERT("pcr != NULL", pcr != NULL); - LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p); - if (pcr->original != NULL) { - pbuf_free(pcr->original); - } - ip_frag_free_pbuf_custom_ref(pcr); -} -#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ - -/** - * Fragment an IP datagram if too large for the netif. - * - * Chop the datagram in MTU sized chunks and send them in order - * by pointing PBUF_REFs into p. - * - * @param p ip packet to send - * @param netif the netif on which to send - * @param dest destination ip address to which to send - * - * @return ERR_OK if sent successfully, err_t otherwise - */ -err_t -ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest) -{ - struct pbuf *rambuf; -#if !LWIP_NETIF_TX_SINGLE_PBUF - struct pbuf *newpbuf; - u16_t newpbuflen = 0; - u16_t left_to_copy; -#endif - struct ip_hdr *original_iphdr; - struct ip_hdr *iphdr; - const u16_t nfb = (netif->mtu - IP_HLEN) / 8; - u16_t left, fragsize; - u16_t ofo; - int last; - u16_t poff = IP_HLEN; - u16_t tmp; - - original_iphdr = (struct ip_hdr *)p->payload; - iphdr = original_iphdr; - LWIP_ERROR("ip4_frag() does not support IP options", IPH_HL(iphdr) * 4 == IP_HLEN, return ERR_VAL); - - /* Save original offset */ - tmp = lwip_ntohs(IPH_OFFSET(iphdr)); - ofo = tmp & IP_OFFMASK; - LWIP_ERROR("ip_frag(): MF already set", (tmp & IP_MF) == 0, return ERR_VAL); - - left = p->tot_len - IP_HLEN; - - while (left) { - /* Fill this fragment */ - fragsize = LWIP_MIN(left, nfb * 8); - -#if LWIP_NETIF_TX_SINGLE_PBUF - rambuf = pbuf_alloc(PBUF_IP, fragsize, PBUF_RAM); - if (rambuf == NULL) { - goto memerr; - } - LWIP_ASSERT("this needs a pbuf in one piece!", - (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL)); - poff += pbuf_copy_partial(p, rambuf->payload, fragsize, poff); - /* make room for the IP header */ - if (pbuf_header(rambuf, IP_HLEN)) { - pbuf_free(rambuf); - goto memerr; - } - /* fill in the IP header */ - SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); - iphdr = (struct ip_hdr*)rambuf->payload; -#else /* LWIP_NETIF_TX_SINGLE_PBUF */ - /* When not using a static buffer, create a chain of pbufs. - * The first will be a PBUF_RAM holding the link and IP header. - * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, - * but limited to the size of an mtu. - */ - rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); - if (rambuf == NULL) { - goto memerr; - } - LWIP_ASSERT("this needs a pbuf in one piece!", - (p->len >= (IP_HLEN))); - SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); - iphdr = (struct ip_hdr *)rambuf->payload; - - left_to_copy = fragsize; - while (left_to_copy) { - struct pbuf_custom_ref *pcr; - u16_t plen = p->len - poff; - newpbuflen = LWIP_MIN(left_to_copy, plen); - /* Is this pbuf already empty? */ - if (!newpbuflen) { - poff = 0; - p = p->next; - continue; - } - pcr = ip_frag_alloc_pbuf_custom_ref(); - if (pcr == NULL) { - pbuf_free(rambuf); - goto memerr; - } - /* Mirror this pbuf, although we might not need all of it. */ - newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, - (u8_t*)p->payload + poff, newpbuflen); - if (newpbuf == NULL) { - ip_frag_free_pbuf_custom_ref(pcr); - pbuf_free(rambuf); - goto memerr; - } - pbuf_ref(p); - pcr->original = p; - pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; - - /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain - * so that it is removed when pbuf_dechain is later called on rambuf. - */ - pbuf_cat(rambuf, newpbuf); - left_to_copy -= newpbuflen; - if (left_to_copy) { - poff = 0; - p = p->next; - } - } - poff += newpbuflen; -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - - /* Correct header */ - last = (left <= netif->mtu - IP_HLEN); - - /* Set new offset and MF flag */ - tmp = (IP_OFFMASK & (ofo)); - if (!last) { - tmp = tmp | IP_MF; - } - IPH_OFFSET_SET(iphdr, lwip_htons(tmp)); - IPH_LEN_SET(iphdr, lwip_htons(fragsize + IP_HLEN)); - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - } -#endif /* CHECKSUM_GEN_IP */ - - /* No need for separate header pbuf - we allowed room for it in rambuf - * when allocated. - */ - netif->output(netif, rambuf, dest); - IPFRAG_STATS_INC(ip_frag.xmit); - - /* Unfortunately we can't reuse rambuf - the hardware may still be - * using the buffer. Instead we free it (and the ensuing chain) and - * recreate it next time round the loop. If we're lucky the hardware - * will have already sent the packet, the free will really free, and - * there will be zero memory penalty. - */ - - pbuf_free(rambuf); - left -= fragsize; - ofo += nfb; - } - MIB2_STATS_INC(mib2.ipfragoks); - return ERR_OK; -memerr: - MIB2_STATS_INC(mib2.ipfragfails); - return ERR_MEM; -} -#endif /* IP_FRAG */ - -#endif /* LWIP_IPV4 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/dhcp6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/dhcp6.c deleted file mode 100644 index f27a725e3af936316b7dfacc53039758f34bba5a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/dhcp6.c +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * - * DHCPv6. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 && LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip6_addr.h" -#include "lwip/def.h" - - -#endif /* LWIP_IPV6 && LWIP_IPV6_DHCP6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ethip6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ethip6.c deleted file mode 100644 index 8f9a91b5f7aa4d14cce2637bbd5942323562272c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ethip6.c +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * - * Ethernet output for IPv6. Uses ND tables for link-layer addressing. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 && LWIP_ETHERNET - -#include "lwip/ethip6.h" -#include "lwip/nd6.h" -#include "lwip/pbuf.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/icmp6.h" -#include "lwip/prot/ethernet.h" -#include "netif/ethernet.h" - -#include - -/** - * Resolve and fill-in Ethernet address header for outgoing IPv6 packet. - * - * For IPv6 multicast, corresponding Ethernet addresses - * are selected and the packet is transmitted on the link. - * - * For unicast addresses, ask the ND6 module what to do. It will either let us - * send the the packet right away, or queue the packet for later itself, unless - * an error occurs. - * - * @todo anycast addresses - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param q The pbuf(s) containing the IP packet to be sent. - * @param ip6addr The IP address of the packet destination. - * - * @return - * - ERR_OK or the return value of @ref nd6_get_next_hop_addr_or_queue. - */ -err_t -ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr) -{ - struct eth_addr dest; - const u8_t *hwaddr; - err_t result; - - /* multicast destination IP address? */ - if (ip6_addr_ismulticast(ip6addr)) { - /* Hash IP multicast address to MAC address.*/ - dest.addr[0] = 0x33; - dest.addr[1] = 0x33; - dest.addr[2] = ((const u8_t *)(&(ip6addr->addr[3])))[0]; - dest.addr[3] = ((const u8_t *)(&(ip6addr->addr[3])))[1]; - dest.addr[4] = ((const u8_t *)(&(ip6addr->addr[3])))[2]; - dest.addr[5] = ((const u8_t *)(&(ip6addr->addr[3])))[3]; - - /* Send out. */ - return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6); - } - - /* We have a unicast destination IP address */ - /* @todo anycast? */ - - /* Ask ND6 what to do with the packet. */ - result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr); - if (result != ERR_OK) { - return result; - } - - /* If no hardware address is returned, nd6 has queued the packet for later. */ - if (hwaddr == NULL) { - return ERR_OK; - } - - /* Send out the packet using the returned hardware address. */ - SMEMCPY(dest.addr, hwaddr, 6); - return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6); -} - -#endif /* LWIP_IPV6 && LWIP_ETHERNET */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/icmp6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/icmp6.c deleted file mode 100644 index 323b69a2ab7d27e62edbfae35da1ac4d37afcca0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/icmp6.c +++ /dev/null @@ -1,350 +0,0 @@ -/** - * @file - * - * IPv6 version of ICMP, as per RFC 4443. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/icmp6.h" -#include "lwip/prot/icmp6.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/inet_chksum.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/nd6.h" -#include "lwip/mld6.h" -#include "lwip/ip.h" -#include "lwip/stats.h" - -#include - -#ifndef LWIP_ICMP6_DATASIZE -#define LWIP_ICMP6_DATASIZE 8 -#endif -#if LWIP_ICMP6_DATASIZE == 0 -#define LWIP_ICMP6_DATASIZE 8 -#endif - -/* Forward declarations */ -static void icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type); - - -/** - * Process an input ICMPv6 message. Called by ip6_input. - * - * Will generate a reply for echo requests. Other messages are forwarded - * to nd6_input, or mld6_input. - * - * @param p the mld packet, p->payload pointing to the icmpv6 header - * @param inp the netif on which this packet was received - */ -void -icmp6_input(struct pbuf *p, struct netif *inp) -{ - struct icmp6_hdr *icmp6hdr; - struct pbuf *r; - const ip6_addr_t *reply_src; - - ICMP6_STATS_INC(icmp6.recv); - - /* Check that ICMPv6 header fits in payload */ - if (p->len < sizeof(struct icmp6_hdr)) { - /* drop short packets */ - pbuf_free(p); - ICMP6_STATS_INC(icmp6.lenerr); - ICMP6_STATS_INC(icmp6.drop); - return; - } - - icmp6hdr = (struct icmp6_hdr *)p->payload; - -#if CHECKSUM_CHECK_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP6) { - if (ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->tot_len, ip6_current_src_addr(), - ip6_current_dest_addr()) != 0) { - /* Checksum failed */ - pbuf_free(p); - ICMP6_STATS_INC(icmp6.chkerr); - ICMP6_STATS_INC(icmp6.drop); - return; - } - } -#endif /* CHECKSUM_CHECK_ICMP6 */ - - switch (icmp6hdr->type) { - case ICMP6_TYPE_NA: /* Neighbor advertisement */ - case ICMP6_TYPE_NS: /* Neighbor solicitation */ - case ICMP6_TYPE_RA: /* Router advertisement */ - case ICMP6_TYPE_RD: /* Redirect */ - case ICMP6_TYPE_PTB: /* Packet too big */ - nd6_input(p, inp); - return; - break; - case ICMP6_TYPE_RS: -#if LWIP_IPV6_FORWARD - /* @todo implement router functionality */ -#endif - break; -#if LWIP_IPV6_MLD - case ICMP6_TYPE_MLQ: - case ICMP6_TYPE_MLR: - case ICMP6_TYPE_MLD: - mld6_input(p, inp); - return; - break; -#endif - case ICMP6_TYPE_EREQ: -#if !LWIP_MULTICAST_PING - /* multicast destination address? */ - if (ip6_addr_ismulticast(ip6_current_dest_addr())) { - /* drop */ - pbuf_free(p); - ICMP6_STATS_INC(icmp6.drop); - return; - } -#endif /* LWIP_MULTICAST_PING */ - - /* Allocate reply. */ - r = pbuf_alloc(PBUF_IP, p->tot_len, PBUF_RAM); - if (r == NULL) { - /* drop */ - pbuf_free(p); - ICMP6_STATS_INC(icmp6.memerr); - return; - } - - /* Copy echo request. */ - if (pbuf_copy(r, p) != ERR_OK) { - /* drop */ - pbuf_free(p); - pbuf_free(r); - ICMP6_STATS_INC(icmp6.err); - return; - } - - /* Determine reply source IPv6 address. */ -#if LWIP_MULTICAST_PING - if (ip6_addr_ismulticast(ip6_current_dest_addr())) { - reply_src = ip_2_ip6(ip6_select_source_address(inp, ip6_current_src_addr())); - if (reply_src == NULL) { - /* drop */ - pbuf_free(p); - pbuf_free(r); - ICMP6_STATS_INC(icmp6.rterr); - return; - } - } - else -#endif /* LWIP_MULTICAST_PING */ - { - reply_src = ip6_current_dest_addr(); - } - - /* Set fields in reply. */ - ((struct icmp6_echo_hdr *)(r->payload))->type = ICMP6_TYPE_EREP; - ((struct icmp6_echo_hdr *)(r->payload))->chksum = 0; -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP6) { - ((struct icmp6_echo_hdr *)(r->payload))->chksum = ip6_chksum_pseudo(r, - IP6_NEXTH_ICMP6, r->tot_len, reply_src, ip6_current_src_addr()); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - /* Send reply. */ - ICMP6_STATS_INC(icmp6.xmit); - ip6_output_if(r, reply_src, ip6_current_src_addr(), - LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, inp); - pbuf_free(r); - - break; - default: - ICMP6_STATS_INC(icmp6.proterr); - ICMP6_STATS_INC(icmp6.drop); - break; - } - - pbuf_free(p); -} - - -/** - * Send an icmpv6 'destination unreachable' packet. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IPv6 header - * @param c ICMPv6 code for the unreachable type - */ -void -icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c) -{ - icmp6_send_response(p, c, 0, ICMP6_TYPE_DUR); -} - -/** - * Send an icmpv6 'packet too big' packet. - * - * @param p the input packet for which the 'packet too big' should be sent, - * p->payload pointing to the IPv6 header - * @param mtu the maximum mtu that we can accept - */ -void -icmp6_packet_too_big(struct pbuf *p, u32_t mtu) -{ - icmp6_send_response(p, 0, mtu, ICMP6_TYPE_PTB); -} - -/** - * Send an icmpv6 'time exceeded' packet. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IPv6 header - * @param c ICMPv6 code for the time exceeded type - */ -void -icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c) -{ - icmp6_send_response(p, c, 0, ICMP6_TYPE_TE); -} - -/** - * Send an icmpv6 'parameter problem' packet. - * - * @param p the input packet for which the 'param problem' should be sent, - * p->payload pointing to the IP header - * @param c ICMPv6 code for the param problem type - * @param pointer the pointer to the byte where the parameter is found - */ -void -icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, u32_t pointer) -{ - icmp6_send_response(p, c, pointer, ICMP6_TYPE_PP); -} - -/** - * Send an ICMPv6 packet in response to an incoming packet. - * - * @param p the input packet for which the response should be sent, - * p->payload pointing to the IPv6 header - * @param code Code of the ICMPv6 header - * @param data Additional 32-bit parameter in the ICMPv6 header - * @param type Type of the ICMPv6 header - */ -static void -icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type) -{ - struct pbuf *q; - struct icmp6_hdr *icmp6hdr; - const ip6_addr_t *reply_src; - ip6_addr_t *reply_dest; - ip6_addr_t reply_src_local, reply_dest_local; - struct ip6_hdr *ip6hdr; - struct netif *netif; - - /* ICMPv6 header + IPv6 header + data */ - q = pbuf_alloc(PBUF_IP, sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE, - PBUF_RAM); - if (q == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMPv6 packet.\n")); - ICMP6_STATS_INC(icmp6.memerr); - return; - } - LWIP_ASSERT("check that first pbuf can hold icmp 6message", - (q->len >= (sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE))); - - icmp6hdr = (struct icmp6_hdr *)q->payload; - icmp6hdr->type = type; - icmp6hdr->code = code; - icmp6hdr->data = data; - - /* copy fields from original packet */ - SMEMCPY((u8_t *)q->payload + sizeof(struct icmp6_hdr), (u8_t *)p->payload, - IP6_HLEN + LWIP_ICMP6_DATASIZE); - - /* Get the destination address and netif for this ICMP message. */ - if ((ip_current_netif() == NULL) || - ((code == ICMP6_TE_FRAG) && (type == ICMP6_TYPE_TE))) { - /* Special case, as ip6_current_xxx is either NULL, or points - * to a different packet than the one that expired. - * We must use the addresses that are stored in the expired packet. */ - ip6hdr = (struct ip6_hdr *)p->payload; - /* copy from packed address to aligned address */ - ip6_addr_copy(reply_dest_local, ip6hdr->src); - ip6_addr_copy(reply_src_local, ip6hdr->dest); - reply_dest = &reply_dest_local; - reply_src = &reply_src_local; - netif = ip6_route(reply_src, reply_dest); - if (netif == NULL) { - /* drop */ - pbuf_free(q); - ICMP6_STATS_INC(icmp6.rterr); - return; - } - } - else { - netif = ip_current_netif(); - reply_dest = ip6_current_src_addr(); - - /* Select an address to use as source. */ - reply_src = ip_2_ip6(ip6_select_source_address(netif, reply_dest)); - if (reply_src == NULL) { - /* drop */ - pbuf_free(q); - ICMP6_STATS_INC(icmp6.rterr); - return; - } - } - - /* calculate checksum */ - icmp6hdr->chksum = 0; -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { - icmp6hdr->chksum = ip6_chksum_pseudo(q, IP6_NEXTH_ICMP6, q->tot_len, - reply_src, reply_dest); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - ICMP6_STATS_INC(icmp6.xmit); - ip6_output_if(q, reply_src, reply_dest, LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif); - pbuf_free(q); -} - -#endif /* LWIP_ICMP6 && LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/inet6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/inet6.c deleted file mode 100644 index d9a992c22ae5d7f51af5cf72b0a7286551a45b85..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/inet6.c +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * INET v6 addresses. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 && LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/inet.h" - -/** This variable is initialized by the system to contain the wildcard IPv6 address. - */ -const struct in6_addr in6addr_any = IN6ADDR_ANY_INIT; - -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6.c deleted file mode 100644 index f14e33424f567a3233e25bd562df260feb25235a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6.c +++ /dev/null @@ -1,1122 +0,0 @@ -/** - * @file - * - * IPv6 layer. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/netif.h" -#include "lwip/ip.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/ip6_frag.h" -#include "lwip/icmp6.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/dhcp6.h" -#include "lwip/nd6.h" -#include "lwip/mld6.h" -#include "lwip/debug.h" -#include "lwip/stats.h" - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -/** - * Finds the appropriate network interface for a given IPv6 address. It tries to select - * a netif following a sequence of heuristics: - * 1) if there is only 1 netif, return it - * 2) if the destination is a link-local address, try to match the src address to a netif. - * this is a tricky case because with multiple netifs, link-local addresses only have - * meaning within a particular subnet/link. - * 3) tries to match the destination subnet to a configured address - * 4) tries to find a router - * 5) tries to match the source address to the netif - * 6) returns the default netif, if configured - * - * @param src the source IPv6 address, if known - * @param dest the destination IPv6 address for which to find the route - * @return the netif on which to send to reach dest - */ -struct netif * -ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest) -{ - struct netif *netif; - s8_t i; - - /* If single netif configuration, fast return. */ - if ((netif_list != NULL) && (netif_list->next == NULL)) { - if (!netif_is_up(netif_list) || !netif_is_link_up(netif_list)) { - return NULL; - } - return netif_list; - } - - /* Special processing for link-local addresses. */ - if (ip6_addr_islinklocal(dest)) { - if (ip6_addr_isany(src)) { - /* Use default netif, if Up. */ - if (netif_default == NULL || !netif_is_up(netif_default) || - !netif_is_link_up(netif_default)) { - return NULL; - } - return netif_default; - } - - /* Try to find the netif for the source address, checking that link is up. */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (!netif_is_up(netif) || !netif_is_link_up(netif)) { - continue; - } - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_cmp(src, netif_ip6_addr(netif, i))) { - return netif; - } - } - } - - /* netif not found, use default netif, if up */ - if (netif_default == NULL || !netif_is_up(netif_default) || - !netif_is_link_up(netif_default)) { - return NULL; - } - return netif_default; - } - - /* we come here for non-link-local addresses */ -#ifdef LWIP_HOOK_IP6_ROUTE - netif = LWIP_HOOK_IP6_ROUTE(src, dest); - if (netif != NULL) { - return netif; - } -#endif - - /* See if the destination subnet matches a configured address. */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (!netif_is_up(netif) || !netif_is_link_up(netif)) { - continue; - } - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_netcmp(dest, netif_ip6_addr(netif, i))) { - return netif; - } - } - } - - /* Get the netif for a suitable router. */ - netif = nd6_find_route(dest); - if ((netif != NULL) && netif_is_up(netif) && netif_is_link_up(netif)) { - return netif; - } - - /* try with the netif that matches the source address. */ - if (!ip6_addr_isany(src)) { - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (!netif_is_up(netif) || !netif_is_link_up(netif)) { - continue; - } - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_cmp(src, netif_ip6_addr(netif, i))) { - return netif; - } - } - } - } - -#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF - /* loopif is disabled, loopback traffic is passed through any netif */ - if (ip6_addr_isloopback(dest)) { - /* don't check for link on loopback traffic */ - if (netif_default != NULL && netif_is_up(netif_default)) { - return netif_default; - } - /* default netif is not up, just use any netif for loopback traffic */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (netif_is_up(netif)) { - return netif; - } - } - return NULL; - } -#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ - - /* no matching netif found, use default netif, if up */ - if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default)) { - return NULL; - } - return netif_default; -} - -/** - * @ingroup ip6 - * Select the best IPv6 source address for a given destination - * IPv6 address. Loosely follows RFC 3484. "Strong host" behavior - * is assumed. - * - * @param netif the netif on which to send a packet - * @param dest the destination we are trying to reach - * @return the most suitable source address to use, or NULL if no suitable - * source address is found - */ -const ip_addr_t * -ip6_select_source_address(struct netif *netif, const ip6_addr_t *dest) -{ - const ip_addr_t *src = NULL; - u8_t i; - - /* If dest is link-local, choose a link-local source. */ - if (ip6_addr_islinklocal(dest) || ip6_addr_ismulticast_linklocal(dest) || ip6_addr_ismulticast_iflocal(dest)) { - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_islinklocal(netif_ip6_addr(netif, i))) { - return netif_ip_addr6(netif, i); - } - } - } - - /* Choose a site-local with matching prefix. */ - if (ip6_addr_issitelocal(dest) || ip6_addr_ismulticast_sitelocal(dest)) { - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_issitelocal(netif_ip6_addr(netif, i)) && - ip6_addr_netcmp(dest, netif_ip6_addr(netif, i))) { - return netif_ip_addr6(netif, i); - } - } - } - - /* Choose a unique-local with matching prefix. */ - if (ip6_addr_isuniquelocal(dest) || ip6_addr_ismulticast_orglocal(dest)) { - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_isuniquelocal(netif_ip6_addr(netif, i)) && - ip6_addr_netcmp(dest, netif_ip6_addr(netif, i))) { - return netif_ip_addr6(netif, i); - } - } - } - - /* Choose a global with best matching prefix. */ - if (ip6_addr_isglobal(dest) || ip6_addr_ismulticast_global(dest)) { - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_isglobal(netif_ip6_addr(netif, i))) { - if (src == NULL) { - src = netif_ip_addr6(netif, i); - } - else { - /* Replace src only if we find a prefix match. */ - /* @todo find longest matching prefix. */ - if ((!(ip6_addr_netcmp(ip_2_ip6(src), dest))) && - ip6_addr_netcmp(netif_ip6_addr(netif, i), dest)) { - src = netif_ip_addr6(netif, i); - } - } - } - } - if (src != NULL) { - return src; - } - } - - /* Last resort: see if arbitrary prefix matches. */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_netcmp(dest, netif_ip6_addr(netif, i))) { - return netif_ip_addr6(netif, i); - } - } - - return NULL; -} - -#if LWIP_IPV6_FORWARD -/** - * Forwards an IPv6 packet. It finds an appropriate route for the - * packet, decrements the HL value of the packet, and outputs - * the packet on the appropriate interface. - * - * @param p the packet to forward (p->payload points to IP header) - * @param iphdr the IPv6 header of the input packet - * @param inp the netif on which this packet was received - */ -static void -ip6_forward(struct pbuf *p, struct ip6_hdr *iphdr, struct netif *inp) -{ - struct netif *netif; - - /* do not forward link-local or loopback addresses */ - if (ip6_addr_islinklocal(ip6_current_dest_addr()) || - ip6_addr_isloopback(ip6_current_dest_addr())) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not forwarding link-local address.\n")); - IP6_STATS_INC(ip6.rterr); - IP6_STATS_INC(ip6.drop); - return; - } - - /* Find network interface where to forward this IP packet to. */ - netif = ip6_route(IP6_ADDR_ANY6, ip6_current_dest_addr()); - if (netif == NULL) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", - IP6_ADDR_BLOCK1(ip6_current_dest_addr()), - IP6_ADDR_BLOCK2(ip6_current_dest_addr()), - IP6_ADDR_BLOCK3(ip6_current_dest_addr()), - IP6_ADDR_BLOCK4(ip6_current_dest_addr()), - IP6_ADDR_BLOCK5(ip6_current_dest_addr()), - IP6_ADDR_BLOCK6(ip6_current_dest_addr()), - IP6_ADDR_BLOCK7(ip6_current_dest_addr()), - IP6_ADDR_BLOCK8(ip6_current_dest_addr()))); -#if LWIP_ICMP6 - /* Don't send ICMP messages in response to ICMP messages */ - if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { - icmp6_dest_unreach(p, ICMP6_DUR_NO_ROUTE); - } -#endif /* LWIP_ICMP6 */ - IP6_STATS_INC(ip6.rterr); - IP6_STATS_INC(ip6.drop); - return; - } - /* Do not forward packets onto the same network interface on which - * they arrived. */ - if (netif == inp) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not bouncing packets back on incoming interface.\n")); - IP6_STATS_INC(ip6.rterr); - IP6_STATS_INC(ip6.drop); - return; - } - - /* decrement HL */ - IP6H_HOPLIM_SET(iphdr, IP6H_HOPLIM(iphdr) - 1); - /* send ICMP6 if HL == 0 */ - if (IP6H_HOPLIM(iphdr) == 0) { -#if LWIP_ICMP6 - /* Don't send ICMP messages in response to ICMP messages */ - if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { - icmp6_time_exceeded(p, ICMP6_TE_HL); - } -#endif /* LWIP_ICMP6 */ - IP6_STATS_INC(ip6.drop); - return; - } - - if (netif->mtu && (p->tot_len > netif->mtu)) { -#if LWIP_ICMP6 - /* Don't send ICMP messages in response to ICMP messages */ - if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { - icmp6_packet_too_big(p, netif->mtu); - } -#endif /* LWIP_ICMP6 */ - IP6_STATS_INC(ip6.drop); - return; - } - - LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: forwarding packet to %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", - IP6_ADDR_BLOCK1(ip6_current_dest_addr()), - IP6_ADDR_BLOCK2(ip6_current_dest_addr()), - IP6_ADDR_BLOCK3(ip6_current_dest_addr()), - IP6_ADDR_BLOCK4(ip6_current_dest_addr()), - IP6_ADDR_BLOCK5(ip6_current_dest_addr()), - IP6_ADDR_BLOCK6(ip6_current_dest_addr()), - IP6_ADDR_BLOCK7(ip6_current_dest_addr()), - IP6_ADDR_BLOCK8(ip6_current_dest_addr()))); - - /* transmit pbuf on chosen interface */ - netif->output_ip6(netif, p, ip6_current_dest_addr()); - IP6_STATS_INC(ip6.fw); - IP6_STATS_INC(ip6.xmit); - return; -} -#endif /* LWIP_IPV6_FORWARD */ - -/** - * This function is called by the network interface device driver when - * an IPv6 packet is received. The function does the basic checks of the - * IP header such as packet size being at least larger than the header - * size etc. If the packet was not destined for us, the packet is - * forwarded (using ip6_forward). - * - * Finally, the packet is sent to the upper layer protocol input function. - * - * @param p the received IPv6 packet (p->payload points to IPv6 header) - * @param inp the netif on which this packet was received - * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't - * processed, but currently always returns ERR_OK) - */ -err_t -ip6_input(struct pbuf *p, struct netif *inp) -{ - struct ip6_hdr *ip6hdr; - struct netif *netif; - u8_t nexth; - u16_t hlen; /* the current header length */ - u8_t i; -#if 0 /*IP_ACCEPT_LINK_LAYER_ADDRESSING*/ - @todo - int check_ip_src=1; -#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ - - IP6_STATS_INC(ip6.recv); - - /* identify the IP header */ - ip6hdr = (struct ip6_hdr *)p->payload; - if (IP6H_V(ip6hdr) != 6) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IPv6 packet dropped due to bad version number %"U32_F"\n", - IP6H_V(ip6hdr))); - pbuf_free(p); - IP6_STATS_INC(ip6.err); - IP6_STATS_INC(ip6.drop); - return ERR_OK; - } - -#ifdef LWIP_HOOK_IP6_INPUT - if (LWIP_HOOK_IP6_INPUT(p, inp)) { - /* the packet has been eaten */ - return ERR_OK; - } -#endif - - /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ - if ((IP6_HLEN > p->len) || ((IP6H_PLEN(ip6hdr) + IP6_HLEN) > p->tot_len)) { - if (IP6_HLEN > p->len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", - (u16_t)IP6_HLEN, p->len)); - } - if ((IP6H_PLEN(ip6hdr) + IP6_HLEN) > p->tot_len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 (plen %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", - (u16_t)(IP6H_PLEN(ip6hdr) + IP6_HLEN), p->tot_len)); - } - /* free (drop) packet pbufs */ - pbuf_free(p); - IP6_STATS_INC(ip6.lenerr); - IP6_STATS_INC(ip6.drop); - return ERR_OK; - } - - /* Trim pbuf. This should have been done at the netif layer, - * but we'll do it anyway just to be sure that its done. */ - pbuf_realloc(p, IP6_HLEN + IP6H_PLEN(ip6hdr)); - - /* copy IP addresses to aligned ip6_addr_t */ - ip_addr_copy_from_ip6(ip_data.current_iphdr_dest, ip6hdr->dest); - ip_addr_copy_from_ip6(ip_data.current_iphdr_src, ip6hdr->src); - - /* Don't accept virtual IPv4 mapped IPv6 addresses. - * Don't accept multicast source addresses. */ - if (ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_dest)) || - ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_src)) || - ip6_addr_ismulticast(ip_2_ip6(&ip_data.current_iphdr_src))) { - IP6_STATS_INC(ip6.err); - IP6_STATS_INC(ip6.drop); - return ERR_OK; - } - - /* current header pointer. */ - ip_data.current_ip6_header = ip6hdr; - - /* In netif, used in case we need to send ICMPv6 packets back. */ - ip_data.current_netif = inp; - ip_data.current_input_netif = inp; - - /* match packet against an interface, i.e. is this packet for us? */ - if (ip6_addr_ismulticast(ip6_current_dest_addr())) { - /* Always joined to multicast if-local and link-local all-nodes group. */ - if (ip6_addr_isallnodes_iflocal(ip6_current_dest_addr()) || - ip6_addr_isallnodes_linklocal(ip6_current_dest_addr())) { - netif = inp; - } -#if LWIP_IPV6_MLD - else if (mld6_lookfor_group(inp, ip6_current_dest_addr())) { - netif = inp; - } -#else /* LWIP_IPV6_MLD */ - else if (ip6_addr_issolicitednode(ip6_current_dest_addr())) { - /* Filter solicited node packets when MLD is not enabled - * (for Neighbor discovery). */ - netif = NULL; - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) && - ip6_addr_cmp_solicitednode(ip6_current_dest_addr(), netif_ip6_addr(inp, i))) { - netif = inp; - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: solicited node packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - break; - } - } - } -#endif /* LWIP_IPV6_MLD */ - else { - netif = NULL; - } - } else { - /* start trying with inp. if that's not acceptable, start walking the - list of configured netifs. - 'first' is used as a boolean to mark whether we started walking the list */ - int first = 1; - netif = inp; - do { - /* interface is up? */ - if (netif_is_up(netif)) { - /* unicast to this interface address? address configured? */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_cmp(ip6_current_dest_addr(), netif_ip6_addr(netif, i))) { - /* exit outer loop */ - goto netif_found; - } - } - } - if (first) { - if (ip6_addr_islinklocal(ip6_current_dest_addr()) -#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF - || ip6_addr_isloopback(ip6_current_dest_addr()) -#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ - ) { - /* Do not match link-local addresses to other netifs. The loopback - * address is to be considered link-local and packets to it should be - * dropped on other interfaces, as per RFC 4291 Sec. 2.5.3. This - * requirement cannot be implemented in the case that loopback - * traffic is sent across a non-loopback interface, however. - */ - netif = NULL; - break; - } - first = 0; - netif = netif_list; - } else { - netif = netif->next; - } - if (netif == inp) { - netif = netif->next; - } - } while (netif != NULL); -netif_found: - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet accepted on interface %c%c\n", - netif ? netif->name[0] : 'X', netif? netif->name[1] : 'X')); - } - - /* "::" packet source address? (used in duplicate address detection) */ - if (ip6_addr_isany(ip6_current_src_addr()) && - (!ip6_addr_issolicitednode(ip6_current_dest_addr()))) { - /* packet source is not valid */ - /* free (drop) packet pbufs */ - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with src ANY_ADDRESS dropped\n")); - pbuf_free(p); - IP6_STATS_INC(ip6.drop); - goto ip6_input_cleanup; - } - - /* packet not for us? */ - if (netif == NULL) { - /* packet not for us, route or discard */ - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_TRACE, ("ip6_input: packet not for us.\n")); -#if LWIP_IPV6_FORWARD - /* non-multicast packet? */ - if (!ip6_addr_ismulticast(ip6_current_dest_addr())) { - /* try to forward IP packet on (other) interfaces */ - ip6_forward(p, ip6hdr, inp); - } -#endif /* LWIP_IPV6_FORWARD */ - pbuf_free(p); - goto ip6_input_cleanup; - } - - /* current netif pointer. */ - ip_data.current_netif = netif; - - /* Save next header type. */ - nexth = IP6H_NEXTH(ip6hdr); - - /* Init header length. */ - hlen = ip_data.current_ip_header_tot_len = IP6_HLEN; - - /* Move to payload. */ - pbuf_header(p, -IP6_HLEN); - - /* Process known option extension headers, if present. */ - while (nexth != IP6_NEXTH_NONE) - { - switch (nexth) { - case IP6_NEXTH_HOPBYHOP: - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Hop-by-Hop options header\n")); - /* Get next header type. */ - nexth = *((u8_t *)p->payload); - - /* Get the header length. */ - hlen = 8 * (1 + *((u8_t *)p->payload + 1)); - ip_data.current_ip_header_tot_len += hlen; - - /* Skip over this header. */ - if (hlen > p->len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", - hlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP6_STATS_INC(ip6.lenerr); - IP6_STATS_INC(ip6.drop); - goto ip6_input_cleanup; - } - - pbuf_header(p, -(s16_t)hlen); - break; - case IP6_NEXTH_DESTOPTS: - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Destination options header\n")); - /* Get next header type. */ - nexth = *((u8_t *)p->payload); - - /* Get the header length. */ - hlen = 8 * (1 + *((u8_t *)p->payload + 1)); - ip_data.current_ip_header_tot_len += hlen; - - /* Skip over this header. */ - if (hlen > p->len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", - hlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP6_STATS_INC(ip6.lenerr); - IP6_STATS_INC(ip6.drop); - goto ip6_input_cleanup; - } - - pbuf_header(p, -(s16_t)hlen); - break; - case IP6_NEXTH_ROUTING: - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Routing header\n")); - /* Get next header type. */ - nexth = *((u8_t *)p->payload); - - /* Get the header length. */ - hlen = 8 * (1 + *((u8_t *)p->payload + 1)); - ip_data.current_ip_header_tot_len += hlen; - - /* Skip over this header. */ - if (hlen > p->len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", - hlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP6_STATS_INC(ip6.lenerr); - IP6_STATS_INC(ip6.drop); - goto ip6_input_cleanup; - } - - pbuf_header(p, -(s16_t)hlen); - break; - - case IP6_NEXTH_FRAGMENT: - { - struct ip6_frag_hdr *frag_hdr; - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header\n")); - - frag_hdr = (struct ip6_frag_hdr *)p->payload; - - /* Get next header type. */ - nexth = frag_hdr->_nexth; - - /* Fragment Header length. */ - hlen = 8; - ip_data.current_ip_header_tot_len += hlen; - - /* Make sure this header fits in current pbuf. */ - if (hlen > p->len) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", - hlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP6_FRAG_STATS_INC(ip6_frag.lenerr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto ip6_input_cleanup; - } - - /* Offset == 0 and more_fragments == 0? */ - if ((frag_hdr->_fragment_offset & - PP_HTONS(IP6_FRAG_OFFSET_MASK | IP6_FRAG_MORE_FLAG)) == 0) { - /* This is a 1-fragment packet, usually a packet that we have - * already reassembled. Skip this header anc continue. */ - pbuf_header(p, -(s16_t)hlen); - } else { -#if LWIP_IPV6_REASS - - /* reassemble the packet */ - p = ip6_reass(p); - /* packet not fully reassembled yet? */ - if (p == NULL) { - goto ip6_input_cleanup; - } - - /* Returned p point to IPv6 header. - * Update all our variables and pointers and continue. */ - ip6hdr = (struct ip6_hdr *)p->payload; - nexth = IP6H_NEXTH(ip6hdr); - hlen = ip_data.current_ip_header_tot_len = IP6_HLEN; - pbuf_header(p, -IP6_HLEN); - -#else /* LWIP_IPV6_REASS */ - /* free (drop) packet pbufs */ - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header dropped (with LWIP_IPV6_REASS==0)\n")); - pbuf_free(p); - IP6_STATS_INC(ip6.opterr); - IP6_STATS_INC(ip6.drop); - goto ip6_input_cleanup; -#endif /* LWIP_IPV6_REASS */ - } - break; - } - default: - goto options_done; - break; - } - } -options_done: - - /* p points to IPv6 header again. */ - pbuf_header_force(p, (s16_t)ip_data.current_ip_header_tot_len); - - /* send to upper layers */ - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: \n")); - ip6_debug_print(p); - LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); - -#if LWIP_RAW - /* raw input did not eat the packet? */ - if (raw_input(p, inp) == 0) -#endif /* LWIP_RAW */ - { - switch (nexth) { - case IP6_NEXTH_NONE: - pbuf_free(p); - break; -#if LWIP_UDP - case IP6_NEXTH_UDP: -#if LWIP_UDPLITE - case IP6_NEXTH_UDPLITE: -#endif /* LWIP_UDPLITE */ - /* Point to payload. */ - pbuf_header(p, -(s16_t)ip_data.current_ip_header_tot_len); - udp_input(p, inp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case IP6_NEXTH_TCP: - /* Point to payload. */ - pbuf_header(p, -(s16_t)ip_data.current_ip_header_tot_len); - tcp_input(p, inp); - break; -#endif /* LWIP_TCP */ -#if LWIP_ICMP6 - case IP6_NEXTH_ICMP6: - /* Point to payload. */ - pbuf_header(p, -(s16_t)ip_data.current_ip_header_tot_len); - icmp6_input(p, inp); - break; -#endif /* LWIP_ICMP */ - default: -#if LWIP_ICMP6 - /* send ICMP parameter problem unless it was a multicast or ICMPv6 */ - if ((!ip6_addr_ismulticast(ip6_current_dest_addr())) && - (IP6H_NEXTH(ip6hdr) != IP6_NEXTH_ICMP6)) { - icmp6_param_problem(p, ICMP6_PP_HEADER, ip_data.current_ip_header_tot_len - hlen); - } -#endif /* LWIP_ICMP */ - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_input: Unsupported transport protocol %"U16_F"\n", (u16_t)IP6H_NEXTH(ip6hdr))); - pbuf_free(p); - IP6_STATS_INC(ip6.proterr); - IP6_STATS_INC(ip6.drop); - break; - } - } - -ip6_input_cleanup: - ip_data.current_netif = NULL; - ip_data.current_input_netif = NULL; - ip_data.current_ip6_header = NULL; - ip_data.current_ip_header_tot_len = 0; - ip6_addr_set_zero(ip6_current_src_addr()); - ip6_addr_set_zero(ip6_current_dest_addr()); - - return ERR_OK; -} - - -/** - * Sends an IPv6 packet on a network interface. This function constructs - * the IPv6 header. If the source IPv6 address is NULL, the IPv6 "ANY" address is - * used as source (usually during network startup). If the source IPv6 address it - * IP6_ADDR_ANY, the most appropriate IPv6 address of the outgoing network - * interface is filled in as source address. If the destination IPv6 address is - * LWIP_IP_HDRINCL, p is assumed to already include an IPv6 header and - * p->payload points to it instead of the data. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IPv6 header and p->payload points to that IPv6 header) - * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an - * IP address of the netif is selected and used as source address. - * if src == NULL, IP6_ADDR_ANY is used as source) - * @param dest the destination IPv6 address to send the packet to - * @param hl the Hop Limit value to be set in the IPv6 header - * @param tc the Traffic Class value to be set in the IPv6 header - * @param nexth the Next Header to be set in the IPv6 header - * @param netif the netif on which to send this packet - * @return ERR_OK if the packet was sent OK - * ERR_BUF if p doesn't have enough space for IPv6/LINK headers - * returns errors returned by netif->output - */ -err_t -ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, - u8_t nexth, struct netif *netif) -{ - const ip6_addr_t *src_used = src; - if (dest != LWIP_IP_HDRINCL) { - if (src != NULL && ip6_addr_isany(src)) { - src_used = ip_2_ip6(ip6_select_source_address(netif, dest)); - if ((src_used == NULL) || ip6_addr_isany(src_used)) { - /* No appropriate source address was found for this packet. */ - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: No suitable source address for packet.\n")); - IP6_STATS_INC(ip6.rterr); - return ERR_RTE; - } - } - } - return ip6_output_if_src(p, src_used, dest, hl, tc, nexth, netif); -} - -/** - * Same as ip6_output_if() but 'src' address is not replaced by netif address - * when it is 'any'. - */ -err_t -ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, - u8_t nexth, struct netif *netif) -{ - struct ip6_hdr *ip6hdr; - ip6_addr_t dest_addr; - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - /* Should the IPv6 header be generated or is it already included in p? */ - if (dest != LWIP_IP_HDRINCL) { - /* generate IPv6 header */ - if (pbuf_header(p, IP6_HLEN)) { - LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: not enough room for IPv6 header in pbuf\n")); - IP6_STATS_INC(ip6.err); - return ERR_BUF; - } - - ip6hdr = (struct ip6_hdr *)p->payload; - LWIP_ASSERT("check that first pbuf can hold struct ip6_hdr", - (p->len >= sizeof(struct ip6_hdr))); - - IP6H_HOPLIM_SET(ip6hdr, hl); - IP6H_NEXTH_SET(ip6hdr, nexth); - - /* dest cannot be NULL here */ - ip6_addr_copy(ip6hdr->dest, *dest); - - IP6H_VTCFL_SET(ip6hdr, 6, tc, 0); - IP6H_PLEN_SET(ip6hdr, p->tot_len - IP6_HLEN); - - if (src == NULL) { - src = IP6_ADDR_ANY6; - } - /* src cannot be NULL here */ - ip6_addr_copy(ip6hdr->src, *src); - - } else { - /* IP header already included in p */ - ip6hdr = (struct ip6_hdr *)p->payload; - ip6_addr_copy(dest_addr, ip6hdr->dest); - dest = &dest_addr; - } - - IP6_STATS_INC(ip6.xmit); - - LWIP_DEBUGF(IP6_DEBUG, ("ip6_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num)); - ip6_debug_print(p); - -#if ENABLE_LOOPBACK - { - int i; -#if !LWIP_HAVE_LOOPIF - if (ip6_addr_isloopback(dest)) { - return netif_loop_output(netif, p); - } -#endif /* !LWIP_HAVE_LOOPIF */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_cmp(dest, netif_ip6_addr(netif, i))) { - /* Packet to self, enqueue it for loopback */ - LWIP_DEBUGF(IP6_DEBUG, ("netif_loop_output()\n")); - return netif_loop_output(netif, p); - } - } - } -#endif /* ENABLE_LOOPBACK */ -#if LWIP_IPV6_FRAG - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > nd6_get_destination_mtu(dest, netif))) { - return ip6_frag(p, netif, dest); - } -#endif /* LWIP_IPV6_FRAG */ - - LWIP_DEBUGF(IP6_DEBUG, ("netif->output_ip6()\n")); - return netif->output_ip6(netif, p, dest); -} - -/** - * Simple interface to ip6_output_if. It finds the outgoing network - * interface and calls upon ip6_output_if to do the actual work. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IPv6 header and p->payload points to that IPv6 header) - * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an - * IP address of the netif is selected and used as source address. - * if src == NULL, IP6_ADDR_ANY is used as source) - * @param dest the destination IPv6 address to send the packet to - * @param hl the Hop Limit value to be set in the IPv6 header - * @param tc the Traffic Class value to be set in the IPv6 header - * @param nexth the Next Header to be set in the IPv6 header - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth) -{ - struct netif *netif; - struct ip6_hdr *ip6hdr; - ip6_addr_t src_addr, dest_addr; - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - if (dest != LWIP_IP_HDRINCL) { - netif = ip6_route(src, dest); - } else { - /* IP header included in p, read addresses. */ - ip6hdr = (struct ip6_hdr *)p->payload; - ip6_addr_copy(src_addr, ip6hdr->src); - ip6_addr_copy(dest_addr, ip6hdr->dest); - netif = ip6_route(&src_addr, &dest_addr); - } - - if (netif == NULL) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", - IP6_ADDR_BLOCK1(dest), - IP6_ADDR_BLOCK2(dest), - IP6_ADDR_BLOCK3(dest), - IP6_ADDR_BLOCK4(dest), - IP6_ADDR_BLOCK5(dest), - IP6_ADDR_BLOCK6(dest), - IP6_ADDR_BLOCK7(dest), - IP6_ADDR_BLOCK8(dest))); - IP6_STATS_INC(ip6.rterr); - return ERR_RTE; - } - - return ip6_output_if(p, src, dest, hl, tc, nexth, netif); -} - - -#if LWIP_NETIF_HWADDRHINT -/** Like ip6_output, but takes and addr_hint pointer that is passed on to netif->addr_hint - * before calling ip6_output_if. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == LWIP_IP_HDRINCL, p already includes an - IPv6 header and p->payload points to that IPv6 header) - * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an - * IP address of the netif is selected and used as source address. - * if src == NULL, IP6_ADDR_ANY is used as source) - * @param dest the destination IPv6 address to send the packet to - * @param hl the Hop Limit value to be set in the IPv6 header - * @param tc the Traffic Class value to be set in the IPv6 header - * @param nexth the Next Header to be set in the IPv6 header - * @param addr_hint address hint pointer set to netif->addr_hint before - * calling ip_output_if() - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth, u8_t *addr_hint) -{ - struct netif *netif; - struct ip6_hdr *ip6hdr; - ip6_addr_t src_addr, dest_addr; - err_t err; - - LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); - - if (dest != LWIP_IP_HDRINCL) { - netif = ip6_route(src, dest); - } else { - /* IP header included in p, read addresses. */ - ip6hdr = (struct ip6_hdr *)p->payload; - ip6_addr_copy(src_addr, ip6hdr->src); - ip6_addr_copy(dest_addr, ip6hdr->dest); - netif = ip6_route(&src_addr, &dest_addr); - } - - if (netif == NULL) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", - IP6_ADDR_BLOCK1(dest), - IP6_ADDR_BLOCK2(dest), - IP6_ADDR_BLOCK3(dest), - IP6_ADDR_BLOCK4(dest), - IP6_ADDR_BLOCK5(dest), - IP6_ADDR_BLOCK6(dest), - IP6_ADDR_BLOCK7(dest), - IP6_ADDR_BLOCK8(dest))); - IP6_STATS_INC(ip6.rterr); - return ERR_RTE; - } - - NETIF_SET_HWADDRHINT(netif, addr_hint); - err = ip6_output_if(p, src, dest, hl, tc, nexth, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - - return err; -} -#endif /* LWIP_NETIF_HWADDRHINT*/ - -#if LWIP_IPV6_MLD -/** - * Add a hop-by-hop options header with a router alert option and padding. - * - * Used by MLD when sending a Multicast listener report/done message. - * - * @param p the packet to which we will prepend the options header - * @param nexth the next header protocol number (e.g. IP6_NEXTH_ICMP6) - * @param value the value of the router alert option data (e.g. IP6_ROUTER_ALERT_VALUE_MLD) - * @return ERR_OK if hop-by-hop header was added, ERR_* otherwise - */ -err_t -ip6_options_add_hbh_ra(struct pbuf *p, u8_t nexth, u8_t value) -{ - struct ip6_hbh_hdr *hbh_hdr; - - /* Move pointer to make room for hop-by-hop options header. */ - if (pbuf_header(p, sizeof(struct ip6_hbh_hdr))) { - LWIP_DEBUGF(IP6_DEBUG, ("ip6_options: no space for options header\n")); - IP6_STATS_INC(ip6.err); - return ERR_BUF; - } - - hbh_hdr = (struct ip6_hbh_hdr *)p->payload; - - /* Set fields. */ - hbh_hdr->_nexth = nexth; - hbh_hdr->_hlen = 0; - hbh_hdr->_ra_opt_type = IP6_ROUTER_ALERT_OPTION; - hbh_hdr->_ra_opt_dlen = 2; - hbh_hdr->_ra_opt_data = value; - hbh_hdr->_padn_opt_type = IP6_PADN_ALERT_OPTION; - hbh_hdr->_padn_opt_dlen = 0; - - return ERR_OK; -} -#endif /* LWIP_IPV6_MLD */ - -#if IP6_DEBUG -/* Print an IPv6 header by using LWIP_DEBUGF - * @param p an IPv6 packet, p->payload pointing to the IPv6 header - */ -void -ip6_debug_print(struct pbuf *p) -{ - struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload; - - LWIP_DEBUGF(IP6_DEBUG, ("IPv6 header:\n")); - LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP6_DEBUG, ("| %2"U16_F" | %3"U16_F" | %7"U32_F" | (ver, class, flow)\n", - IP6H_V(ip6hdr), - IP6H_TC(ip6hdr), - IP6H_FL(ip6hdr))); - LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP6_DEBUG, ("| %5"U16_F" | %3"U16_F" | %3"U16_F" | (plen, nexth, hopl)\n", - IP6H_PLEN(ip6hdr), - IP6H_NEXTH(ip6hdr), - IP6H_HOPLIM(ip6hdr))); - LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" | (src)\n", - IP6_ADDR_BLOCK1(&(ip6hdr->src)), - IP6_ADDR_BLOCK2(&(ip6hdr->src)), - IP6_ADDR_BLOCK3(&(ip6hdr->src)), - IP6_ADDR_BLOCK4(&(ip6hdr->src)))); - LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" |\n", - IP6_ADDR_BLOCK5(&(ip6hdr->src)), - IP6_ADDR_BLOCK6(&(ip6hdr->src)), - IP6_ADDR_BLOCK7(&(ip6hdr->src)), - IP6_ADDR_BLOCK8(&(ip6hdr->src)))); - LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" | (dest)\n", - IP6_ADDR_BLOCK1(&(ip6hdr->dest)), - IP6_ADDR_BLOCK2(&(ip6hdr->dest)), - IP6_ADDR_BLOCK3(&(ip6hdr->dest)), - IP6_ADDR_BLOCK4(&(ip6hdr->dest)))); - LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" |\n", - IP6_ADDR_BLOCK5(&(ip6hdr->dest)), - IP6_ADDR_BLOCK6(&(ip6hdr->dest)), - IP6_ADDR_BLOCK7(&(ip6hdr->dest)), - IP6_ADDR_BLOCK8(&(ip6hdr->dest)))); - LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP6_DEBUG */ - -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_addr.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_addr.c deleted file mode 100644 index aa06659a0287c3d6ac64d8e7a9c39b685b39c897..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_addr.c +++ /dev/null @@ -1,292 +0,0 @@ -/** - * @file - * - * IPv6 addresses. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * Functions for handling IPv6 addresses. - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip_addr.h" -#include "lwip/def.h" - -/* used by IP6_ADDR_ANY(6) in ip6_addr.h */ -const ip_addr_t ip6_addr_any = IPADDR6_INIT(0ul, 0ul, 0ul, 0ul); - -#ifndef isprint -#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) -#define isprint(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') -#define xchar(i) ((i) < 10 ? '0' + (i) : 'A' + (i) - 10) -#endif - -/** - * Check whether "cp" is a valid ascii representation - * of an IPv6 address and convert to a binary address. - * Returns 1 if the address is valid, 0 if not. - * - * @param cp IPv6 address in ascii representation (e.g. "FF01::1") - * @param addr pointer to which to save the ip address in network order - * @return 1 if cp could be converted to addr, 0 on failure - */ -int -ip6addr_aton(const char *cp, ip6_addr_t *addr) -{ - u32_t addr_index, zero_blocks, current_block_index, current_block_value; - const char *s; - - /* Count the number of colons, to count the number of blocks in a "::" sequence - zero_blocks may be 1 even if there are no :: sequences */ - zero_blocks = 8; - for (s = cp; *s != 0; s++) { - if (*s == ':') { - zero_blocks--; - } else if (!isxdigit(*s)) { - break; - } - } - - /* parse each block */ - addr_index = 0; - current_block_index = 0; - current_block_value = 0; - for (s = cp; *s != 0; s++) { - if (*s == ':') { - if (addr) { - if (current_block_index & 0x1) { - addr->addr[addr_index++] |= current_block_value; - } - else { - addr->addr[addr_index] = current_block_value << 16; - } - } - current_block_index++; - current_block_value = 0; - if (current_block_index > 7) { - /* address too long! */ - return 0; - } - if (s[1] == ':') { - if (s[2] == ':') { - /* invalid format: three successive colons */ - return 0; - } - s++; - /* "::" found, set zeros */ - while (zero_blocks > 0) { - zero_blocks--; - if (current_block_index & 0x1) { - addr_index++; - } else { - if (addr) { - addr->addr[addr_index] = 0; - } - } - current_block_index++; - if (current_block_index > 7) { - /* address too long! */ - return 0; - } - } - } - } else if (isxdigit(*s)) { - /* add current digit */ - current_block_value = (current_block_value << 4) + - (isdigit(*s) ? (u32_t)(*s - '0') : - (u32_t)(10 + (islower(*s) ? *s - 'a' : *s - 'A'))); - } else { - /* unexpected digit, space? CRLF? */ - break; - } - } - - if (addr) { - if (current_block_index & 0x1) { - addr->addr[addr_index++] |= current_block_value; - } - else { - addr->addr[addr_index] = current_block_value << 16; - } - } - - /* convert to network byte order. */ - if (addr) { - for (addr_index = 0; addr_index < 4; addr_index++) { - addr->addr[addr_index] = lwip_htonl(addr->addr[addr_index]); - } - } - - if (current_block_index != 7) { - return 0; - } - - return 1; -} - -/** - * Convert numeric IPv6 address into ASCII representation. - * returns ptr to static buffer; not reentrant! - * - * @param addr ip6 address in network order to convert - * @return pointer to a global static (!) buffer that holds the ASCII - * representation of addr - */ -char * -ip6addr_ntoa(const ip6_addr_t *addr) -{ - static char str[40]; - return ip6addr_ntoa_r(addr, str, 40); -} - -/** - * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used. - * - * @param addr ip6 address in network order to convert - * @param buf target buffer where the string is stored - * @param buflen length of buf - * @return either pointer to buf which now holds the ASCII - * representation of addr or NULL if buf was too small - */ -char * -ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen) -{ - u32_t current_block_index, current_block_value, next_block_value; - s32_t i; - u8_t zero_flag, empty_block_flag; - - i = 0; - empty_block_flag = 0; /* used to indicate a zero chain for "::' */ - - for (current_block_index = 0; current_block_index < 8; current_block_index++) { - /* get the current 16-bit block */ - current_block_value = lwip_htonl(addr->addr[current_block_index >> 1]); - if ((current_block_index & 0x1) == 0) { - current_block_value = current_block_value >> 16; - } - current_block_value &= 0xffff; - - /* Check for empty block. */ - if (current_block_value == 0) { - if (current_block_index == 7 && empty_block_flag == 1) { - /* special case, we must render a ':' for the last block. */ - buf[i++] = ':'; - if (i >= buflen) { - return NULL; - } - break; - } - if (empty_block_flag == 0) { - /* generate empty block "::", but only if more than one contiguous zero block, - * according to current formatting suggestions RFC 5952. */ - next_block_value = lwip_htonl(addr->addr[(current_block_index + 1) >> 1]); - if ((current_block_index & 0x1) == 0x01) { - next_block_value = next_block_value >> 16; - } - next_block_value &= 0xffff; - if (next_block_value == 0) { - empty_block_flag = 1; - buf[i++] = ':'; - if (i >= buflen) { - return NULL; - } - continue; /* move on to next block. */ - } - } else if (empty_block_flag == 1) { - /* move on to next block. */ - continue; - } - } else if (empty_block_flag == 1) { - /* Set this flag value so we don't produce multiple empty blocks. */ - empty_block_flag = 2; - } - - if (current_block_index > 0) { - buf[i++] = ':'; - if (i >= buflen) { - return NULL; - } - } - - if ((current_block_value & 0xf000) == 0) { - zero_flag = 1; - } else { - buf[i++] = xchar(((current_block_value & 0xf000) >> 12)); - zero_flag = 0; - if (i >= buflen) { - return NULL; - } - } - - if (((current_block_value & 0xf00) == 0) && (zero_flag)) { - /* do nothing */ - } else { - buf[i++] = xchar(((current_block_value & 0xf00) >> 8)); - zero_flag = 0; - if (i >= buflen) { - return NULL; - } - } - - if (((current_block_value & 0xf0) == 0) && (zero_flag)) { - /* do nothing */ - } - else { - buf[i++] = xchar(((current_block_value & 0xf0) >> 4)); - zero_flag = 0; - if (i >= buflen) { - return NULL; - } - } - - buf[i++] = xchar((current_block_value & 0xf)); - if (i >= buflen) { - return NULL; - } - } - - buf[i] = 0; - - return buf; -} - -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_frag.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_frag.c deleted file mode 100644 index ff07f71cd24afa28fe7597bf3c17cbb5463d27c8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/ip6_frag.c +++ /dev/null @@ -1,805 +0,0 @@ -/** - * @file - * - * IPv6 fragmentation and reassembly. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" -#include "lwip/ip6_frag.h" -#include "lwip/ip6.h" -#include "lwip/icmp6.h" -#include "lwip/nd6.h" -#include "lwip/ip.h" - -#include "lwip/pbuf.h" -#include "lwip/memp.h" -#include "lwip/stats.h" - -#include - -#if LWIP_IPV6 && LWIP_IPV6_REASS /* don't build if not configured for use in lwipopts.h */ - - -/** Setting this to 0, you can turn off checking the fragments for overlapping - * regions. The code gets a little smaller. Only use this if you know that - * overlapping won't occur on your network! */ -#ifndef IP_REASS_CHECK_OVERLAP -#define IP_REASS_CHECK_OVERLAP 1 -#endif /* IP_REASS_CHECK_OVERLAP */ - -/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is - * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller. - * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA - * is set to 1, so one datagram can be reassembled at a time, only. */ -#ifndef IP_REASS_FREE_OLDEST -#define IP_REASS_FREE_OLDEST 1 -#endif /* IP_REASS_FREE_OLDEST */ - -#if IPV6_FRAG_COPYHEADER -#define IPV6_FRAG_REQROOM ((s16_t)(sizeof(struct ip6_reass_helper) - IP6_FRAG_HLEN)) -#endif - -#define IP_REASS_FLAG_LASTFRAG 0x01 - -/** This is a helper struct which holds the starting - * offset and the ending offset of this fragment to - * easily chain the fragments. - * It has the same packing requirements as the IPv6 header, since it replaces - * the Fragment Header in memory in incoming fragments to keep - * track of the various fragments. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip6_reass_helper { - PACK_STRUCT_FIELD(struct pbuf *next_pbuf); - PACK_STRUCT_FIELD(u16_t start); - PACK_STRUCT_FIELD(u16_t end); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* static variables */ -static struct ip6_reassdata *reassdatagrams; -static u16_t ip6_reass_pbufcount; - -/* Forward declarations. */ -static void ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr); -#if IP_REASS_FREE_OLDEST -static void ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed); -#endif /* IP_REASS_FREE_OLDEST */ - -void -ip6_reass_tmr(void) -{ - struct ip6_reassdata *r, *tmp; - -#if !IPV6_FRAG_COPYHEADER - LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1", - sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN); -#endif /* !IPV6_FRAG_COPYHEADER */ - - r = reassdatagrams; - while (r != NULL) { - /* Decrement the timer. Once it reaches 0, - * clean up the incomplete fragment assembly */ - if (r->timer > 0) { - r->timer--; - r = r->next; - } else { - /* reassembly timed out */ - tmp = r; - /* get the next pointer before freeing */ - r = r->next; - /* free the helper struct and all enqueued pbufs */ - ip6_reass_free_complete_datagram(tmp); - } - } -} - -/** - * Free a datagram (struct ip6_reassdata) and all its pbufs. - * Updates the total count of enqueued pbufs (ip6_reass_pbufcount), - * sends an ICMP time exceeded packet. - * - * @param ipr datagram to free - */ -static void -ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr) -{ - struct ip6_reassdata *prev; - u16_t pbufs_freed = 0; - u16_t clen; - struct pbuf *p; - struct ip6_reass_helper *iprh; - -#if LWIP_ICMP6 - iprh = (struct ip6_reass_helper *)ipr->p->payload; - if (iprh->start == 0) { - /* The first fragment was received, send ICMP time exceeded. */ - /* First, de-queue the first pbuf from r->p. */ - p = ipr->p; - ipr->p = iprh->next_pbuf; - /* Then, move back to the original ipv6 header (we are now pointing to Fragment header). - This cannot fail since we already checked when receiving this fragment. */ - if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)IPV6_FRAG_HDRREF(ipr->iphdr)))) { - LWIP_ASSERT("ip6_reass_free: moving p->payload to ip6 header failed\n", 0); - } - else { - icmp6_time_exceeded(p, ICMP6_TE_FRAG); - } - clen = pbuf_clen(p); - LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); - pbufs_freed += clen; - pbuf_free(p); - } -#endif /* LWIP_ICMP6 */ - - /* First, free all received pbufs. The individual pbufs need to be released - separately as they have not yet been chained */ - p = ipr->p; - while (p != NULL) { - struct pbuf *pcur; - iprh = (struct ip6_reass_helper *)p->payload; - pcur = p; - /* get the next pointer before freeing */ - p = iprh->next_pbuf; - clen = pbuf_clen(pcur); - LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); - pbufs_freed += clen; - pbuf_free(pcur); - } - - /* Then, unchain the struct ip6_reassdata from the list and free it. */ - if (ipr == reassdatagrams) { - reassdatagrams = ipr->next; - } else { - prev = reassdatagrams; - while (prev != NULL) { - if (prev->next == ipr) { - break; - } - prev = prev->next; - } - if (prev != NULL) { - prev->next = ipr->next; - } - } - memp_free(MEMP_IP6_REASSDATA, ipr); - - /* Finally, update number of pbufs in reassembly queue */ - LWIP_ASSERT("ip_reass_pbufcount >= clen", ip6_reass_pbufcount >= pbufs_freed); - ip6_reass_pbufcount -= pbufs_freed; -} - -#if IP_REASS_FREE_OLDEST -/** - * Free the oldest datagram to make room for enqueueing new fragments. - * The datagram ipr is not freed! - * - * @param ipr ip6_reassdata for the current fragment - * @param pbufs_needed number of pbufs needed to enqueue - * (used for freeing other datagrams if not enough space) - */ -static void -ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed) -{ - struct ip6_reassdata *r, *oldest; - - /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, - * but don't free the current datagram! */ - do { - r = oldest = reassdatagrams; - while (r != NULL) { - if (r != ipr) { - if (r->timer <= oldest->timer) { - /* older than the previous oldest */ - oldest = r; - } - } - r = r->next; - } - if (oldest == ipr) { - /* nothing to free, ipr is the only element on the list */ - return; - } - if (oldest != NULL) { - ip6_reass_free_complete_datagram(oldest); - } - } while (((ip6_reass_pbufcount + pbufs_needed) > IP_REASS_MAX_PBUFS) && (reassdatagrams != NULL)); -} -#endif /* IP_REASS_FREE_OLDEST */ - -/** - * Reassembles incoming IPv6 fragments into an IPv6 datagram. - * - * @param p points to the IPv6 Fragment Header - * @return NULL if reassembly is incomplete, pbuf pointing to - * IPv6 Header if reassembly is complete - */ -struct pbuf * -ip6_reass(struct pbuf *p) -{ - struct ip6_reassdata *ipr, *ipr_prev; - struct ip6_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL; - struct ip6_frag_hdr *frag_hdr; - u16_t offset, len; - u16_t clen; - u8_t valid = 1; - struct pbuf *q; - - IP6_FRAG_STATS_INC(ip6_frag.recv); - - if ((const void*)ip6_current_header() != ((u8_t*)p->payload) - IP6_HLEN) { - /* ip6_frag_hdr must be in the first pbuf, not chained */ - IP6_FRAG_STATS_INC(ip6_frag.proterr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; - } - - frag_hdr = (struct ip6_frag_hdr *) p->payload; - - clen = pbuf_clen(p); - - offset = lwip_ntohs(frag_hdr->_fragment_offset); - - /* Calculate fragment length from IPv6 payload length. - * Adjust for headers before Fragment Header. - * And finally adjust by Fragment Header length. */ - len = lwip_ntohs(ip6_current_header()->_plen); - len -= (u16_t)(((u8_t*)p->payload - (const u8_t*)ip6_current_header()) - IP6_HLEN); - len -= IP6_FRAG_HLEN; - - /* Look for the datagram the fragment belongs to in the current datagram queue, - * remembering the previous in the queue for later dequeueing. */ - for (ipr = reassdatagrams, ipr_prev = NULL; ipr != NULL; ipr = ipr->next) { - /* Check if the incoming fragment matches the one currently present - in the reassembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if ((frag_hdr->_identification == ipr->identification) && - ip6_addr_cmp(ip6_current_src_addr(), &(IPV6_FRAG_HDRREF(ipr->iphdr)->src)) && - ip6_addr_cmp(ip6_current_dest_addr(), &(IPV6_FRAG_HDRREF(ipr->iphdr)->dest))) { - IP6_FRAG_STATS_INC(ip6_frag.cachehit); - break; - } - ipr_prev = ipr; - } - - if (ipr == NULL) { - /* Enqueue a new datagram into the datagram queue */ - ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA); - if (ipr == NULL) { -#if IP_REASS_FREE_OLDEST - /* Make room and try again. */ - ip6_reass_remove_oldest_datagram(ipr, clen); - ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA); - if (ipr != NULL) { - /* re-search ipr_prev since it might have been removed */ - for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { - if (ipr_prev->next == ipr) { - break; - } - } - } else -#endif /* IP_REASS_FREE_OLDEST */ - { - IP6_FRAG_STATS_INC(ip6_frag.memerr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; - } - } - - memset(ipr, 0, sizeof(struct ip6_reassdata)); - ipr->timer = IP_REASS_MAXAGE; - - /* enqueue the new structure to the front of the list */ - ipr->next = reassdatagrams; - reassdatagrams = ipr; - - /* Use the current IPv6 header for src/dest address reference. - * Eventually, we will replace it when we get the first fragment - * (it might be this one, in any case, it is done later). */ -#if IPV6_FRAG_COPYHEADER - MEMCPY(&ipr->iphdr, ip6_current_header(), IP6_HLEN); -#else /* IPV6_FRAG_COPYHEADER */ - /* need to use the none-const pointer here: */ - ipr->iphdr = ip_data.current_ip6_header; -#endif /* IPV6_FRAG_COPYHEADER */ - - /* copy the fragmented packet id. */ - ipr->identification = frag_hdr->_identification; - - /* copy the nexth field */ - ipr->nexth = frag_hdr->_nexth; - } - - /* Check if we are allowed to enqueue more datagrams. */ - if ((ip6_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { -#if IP_REASS_FREE_OLDEST - ip6_reass_remove_oldest_datagram(ipr, clen); - if ((ip6_reass_pbufcount + clen) <= IP_REASS_MAX_PBUFS) { - /* re-search ipr_prev since it might have been removed */ - for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { - if (ipr_prev->next == ipr) { - break; - } - } - } else -#endif /* IP_REASS_FREE_OLDEST */ - { - /* @todo: send ICMPv6 time exceeded here? */ - /* drop this pbuf */ - IP6_FRAG_STATS_INC(ip6_frag.memerr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; - } - } - - /* Overwrite Fragment Header with our own helper struct. */ -#if IPV6_FRAG_COPYHEADER - if (IPV6_FRAG_REQROOM > 0) { - /* Make room for struct ip6_reass_helper (only required if sizeof(void*) > 4). - This cannot fail since we already checked when receiving this fragment. */ - u8_t hdrerr = pbuf_header_force(p, IPV6_FRAG_REQROOM); - LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); - } -#else /* IPV6_FRAG_COPYHEADER */ - LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1", - sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN); -#endif /* IPV6_FRAG_COPYHEADER */ - iprh = (struct ip6_reass_helper *)p->payload; - iprh->next_pbuf = NULL; - iprh->start = (offset & IP6_FRAG_OFFSET_MASK); - iprh->end = (offset & IP6_FRAG_OFFSET_MASK) + len; - - /* find the right place to insert this pbuf */ - /* Iterate through until we either get to the end of the list (append), - * or we find on with a larger offset (insert). */ - for (q = ipr->p; q != NULL;) { - iprh_tmp = (struct ip6_reass_helper*)q->payload; - if (iprh->start < iprh_tmp->start) { -#if IP_REASS_CHECK_OVERLAP - if (iprh->end > iprh_tmp->start) { - /* fragment overlaps with following, throw away */ - IP6_FRAG_STATS_INC(ip6_frag.proterr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; - } - if (iprh_prev != NULL) { - if (iprh->start < iprh_prev->end) { - /* fragment overlaps with previous, throw away */ - IP6_FRAG_STATS_INC(ip6_frag.proterr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; - } - } -#endif /* IP_REASS_CHECK_OVERLAP */ - /* the new pbuf should be inserted before this */ - iprh->next_pbuf = q; - if (iprh_prev != NULL) { - /* not the fragment with the lowest offset */ - iprh_prev->next_pbuf = p; - } else { - /* fragment with the lowest offset */ - ipr->p = p; - } - break; - } else if (iprh->start == iprh_tmp->start) { - /* received the same datagram twice: no need to keep the datagram */ - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; -#if IP_REASS_CHECK_OVERLAP - } else if (iprh->start < iprh_tmp->end) { - /* overlap: no need to keep the new datagram */ - IP6_FRAG_STATS_INC(ip6_frag.proterr); - IP6_FRAG_STATS_INC(ip6_frag.drop); - goto nullreturn; -#endif /* IP_REASS_CHECK_OVERLAP */ - } else { - /* Check if the fragments received so far have no gaps. */ - if (iprh_prev != NULL) { - if (iprh_prev->end != iprh_tmp->start) { - /* There is a fragment missing between the current - * and the previous fragment */ - valid = 0; - } - } - } - q = iprh_tmp->next_pbuf; - iprh_prev = iprh_tmp; - } - - /* If q is NULL, then we made it to the end of the list. Determine what to do now */ - if (q == NULL) { - if (iprh_prev != NULL) { - /* this is (for now), the fragment with the highest offset: - * chain it to the last fragment */ -#if IP_REASS_CHECK_OVERLAP - LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); -#endif /* IP_REASS_CHECK_OVERLAP */ - iprh_prev->next_pbuf = p; - if (iprh_prev->end != iprh->start) { - valid = 0; - } - } else { -#if IP_REASS_CHECK_OVERLAP - LWIP_ASSERT("no previous fragment, this must be the first fragment!", - ipr->p == NULL); -#endif /* IP_REASS_CHECK_OVERLAP */ - /* this is the first fragment we ever received for this ip datagram */ - ipr->p = p; - } - } - - /* Track the current number of pbufs current 'in-flight', in order to limit - the number of fragments that may be enqueued at any one time */ - ip6_reass_pbufcount += clen; - - /* Remember IPv6 header if this is the first fragment. */ - if (iprh->start == 0) { -#if IPV6_FRAG_COPYHEADER - if (iprh->next_pbuf != NULL) { - MEMCPY(&ipr->iphdr, ip6_current_header(), IP6_HLEN); - } -#else /* IPV6_FRAG_COPYHEADER */ - /* need to use the none-const pointer here: */ - ipr->iphdr = ip_data.current_ip6_header; -#endif /* IPV6_FRAG_COPYHEADER */ - } - - /* If this is the last fragment, calculate total packet length. */ - if ((offset & IP6_FRAG_MORE_FLAG) == 0) { - ipr->datagram_len = iprh->end; - } - - /* Additional validity tests: we have received first and last fragment. */ - iprh_tmp = (struct ip6_reass_helper*)ipr->p->payload; - if (iprh_tmp->start != 0) { - valid = 0; - } - if (ipr->datagram_len == 0) { - valid = 0; - } - - /* Final validity test: no gaps between current and last fragment. */ - iprh_prev = iprh; - q = iprh->next_pbuf; - while ((q != NULL) && valid) { - iprh = (struct ip6_reass_helper*)q->payload; - if (iprh_prev->end != iprh->start) { - valid = 0; - break; - } - iprh_prev = iprh; - q = iprh->next_pbuf; - } - - if (valid) { - /* All fragments have been received */ - struct ip6_hdr* iphdr_ptr; - - /* chain together the pbufs contained within the ip6_reassdata list. */ - iprh = (struct ip6_reass_helper*) ipr->p->payload; - while (iprh != NULL) { - struct pbuf* next_pbuf = iprh->next_pbuf; - if (next_pbuf != NULL) { - /* Save next helper struct (will be hidden in next step). */ - iprh_tmp = (struct ip6_reass_helper*)next_pbuf->payload; - - /* hide the fragment header for every succeeding fragment */ - pbuf_header(next_pbuf, -IP6_FRAG_HLEN); -#if IPV6_FRAG_COPYHEADER - if (IPV6_FRAG_REQROOM > 0) { - /* hide the extra bytes borrowed from ip6_hdr for struct ip6_reass_helper */ - u8_t hdrerr = pbuf_header(next_pbuf, -(s16_t)(IPV6_FRAG_REQROOM)); - LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); - } -#endif - pbuf_cat(ipr->p, next_pbuf); - } - else { - iprh_tmp = NULL; - } - - iprh = iprh_tmp; - } - -#if IPV6_FRAG_COPYHEADER - if (IPV6_FRAG_REQROOM > 0) { - /* get back room for struct ip6_reass_helper (only required if sizeof(void*) > 4) */ - u8_t hdrerr = pbuf_header(ipr->p, -(s16_t)(IPV6_FRAG_REQROOM)); - LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); - } - iphdr_ptr = (struct ip6_hdr*)((u8_t*)ipr->p->payload - IP6_HLEN); - MEMCPY(iphdr_ptr, &ipr->iphdr, IP6_HLEN); -#else - iphdr_ptr = ipr->iphdr; -#endif - - /* Adjust datagram length by adding header lengths. */ - ipr->datagram_len += (u16_t)(((u8_t*)ipr->p->payload - (u8_t*)iphdr_ptr) - + IP6_FRAG_HLEN - - IP6_HLEN); - - /* Set payload length in ip header. */ - iphdr_ptr->_plen = lwip_htons(ipr->datagram_len); - - /* Get the first pbuf. */ - p = ipr->p; - - /* Restore Fragment Header in first pbuf. Mark as "single fragment" - * packet. Restore nexth. */ - frag_hdr = (struct ip6_frag_hdr *) p->payload; - frag_hdr->_nexth = ipr->nexth; - frag_hdr->reserved = 0; - frag_hdr->_fragment_offset = 0; - frag_hdr->_identification = 0; - - /* release the sources allocate for the fragment queue entry */ - if (reassdatagrams == ipr) { - /* it was the first in the list */ - reassdatagrams = ipr->next; - } else { - /* it wasn't the first, so it must have a valid 'prev' */ - LWIP_ASSERT("sanity check linked list", ipr_prev != NULL); - ipr_prev->next = ipr->next; - } - memp_free(MEMP_IP6_REASSDATA, ipr); - - /* adjust the number of pbufs currently queued for reassembly. */ - ip6_reass_pbufcount -= pbuf_clen(p); - - /* Move pbuf back to IPv6 header. - This cannot fail since we already checked when receiving this fragment. */ - if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)iphdr_ptr))) { - LWIP_ASSERT("ip6_reass: moving p->payload to ip6 header failed\n", 0); - pbuf_free(p); - return NULL; - } - - /* Return the pbuf chain */ - return p; - } - /* the datagram is not (yet?) reassembled completely */ - return NULL; - -nullreturn: - pbuf_free(p); - return NULL; -} - -#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ - -#if LWIP_IPV6 && LWIP_IPV6_FRAG - -#if !LWIP_NETIF_TX_SINGLE_PBUF -/** Allocate a new struct pbuf_custom_ref */ -static struct pbuf_custom_ref* -ip6_frag_alloc_pbuf_custom_ref(void) -{ - return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF); -} - -/** Free a struct pbuf_custom_ref */ -static void -ip6_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p) -{ - LWIP_ASSERT("p != NULL", p != NULL); - memp_free(MEMP_FRAG_PBUF, p); -} - -/** Free-callback function to free a 'struct pbuf_custom_ref', called by - * pbuf_free. */ -static void -ip6_frag_free_pbuf_custom(struct pbuf *p) -{ - struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p; - LWIP_ASSERT("pcr != NULL", pcr != NULL); - LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p); - if (pcr->original != NULL) { - pbuf_free(pcr->original); - } - ip6_frag_free_pbuf_custom_ref(pcr); -} -#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ - -/** - * Fragment an IPv6 datagram if too large for the netif or path MTU. - * - * Chop the datagram in MTU sized chunks and send them in order - * by pointing PBUF_REFs into p - * - * @param p ipv6 packet to send - * @param netif the netif on which to send - * @param dest destination ipv6 address to which to send - * - * @return ERR_OK if sent successfully, err_t otherwise - */ -err_t -ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest) -{ - struct ip6_hdr *original_ip6hdr; - struct ip6_hdr *ip6hdr; - struct ip6_frag_hdr *frag_hdr; - struct pbuf *rambuf; -#if !LWIP_NETIF_TX_SINGLE_PBUF - struct pbuf *newpbuf; - u16_t newpbuflen = 0; - u16_t left_to_copy; -#endif - static u32_t identification; - u16_t nfb; - u16_t left, cop; - u16_t mtu; - u16_t fragment_offset = 0; - u16_t last; - u16_t poff = IP6_HLEN; - - identification++; - - original_ip6hdr = (struct ip6_hdr *)p->payload; - - mtu = nd6_get_destination_mtu(dest, netif); - - /* @todo we assume there are no options in the unfragmentable part (IPv6 header). */ - left = p->tot_len - IP6_HLEN; - - nfb = (mtu - (IP6_HLEN + IP6_FRAG_HLEN)) & IP6_FRAG_OFFSET_MASK; - - while (left) { - last = (left <= nfb); - - /* Fill this fragment */ - cop = last ? left : nfb; - -#if LWIP_NETIF_TX_SINGLE_PBUF - rambuf = pbuf_alloc(PBUF_IP, cop + IP6_FRAG_HLEN, PBUF_RAM); - if (rambuf == NULL) { - IP6_FRAG_STATS_INC(ip6_frag.memerr); - return ERR_MEM; - } - LWIP_ASSERT("this needs a pbuf in one piece!", - (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL)); - poff += pbuf_copy_partial(p, (u8_t*)rambuf->payload + IP6_FRAG_HLEN, cop, poff); - /* make room for the IP header */ - if (pbuf_header(rambuf, IP6_HLEN)) { - pbuf_free(rambuf); - IP6_FRAG_STATS_INC(ip6_frag.memerr); - return ERR_MEM; - } - /* fill in the IP header */ - SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN); - ip6hdr = (struct ip6_hdr *)rambuf->payload; - frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN); -#else - /* When not using a static buffer, create a chain of pbufs. - * The first will be a PBUF_RAM holding the link, IPv6, and Fragment header. - * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, - * but limited to the size of an mtu. - */ - rambuf = pbuf_alloc(PBUF_LINK, IP6_HLEN + IP6_FRAG_HLEN, PBUF_RAM); - if (rambuf == NULL) { - IP6_FRAG_STATS_INC(ip6_frag.memerr); - return ERR_MEM; - } - LWIP_ASSERT("this needs a pbuf in one piece!", - (p->len >= (IP6_HLEN))); - SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN); - ip6hdr = (struct ip6_hdr *)rambuf->payload; - frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN); - - /* Can just adjust p directly for needed offset. */ - p->payload = (u8_t *)p->payload + poff; - p->len -= poff; - p->tot_len -= poff; - - left_to_copy = cop; - while (left_to_copy) { - struct pbuf_custom_ref *pcr; - newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len; - /* Is this pbuf already empty? */ - if (!newpbuflen) { - p = p->next; - continue; - } - pcr = ip6_frag_alloc_pbuf_custom_ref(); - if (pcr == NULL) { - pbuf_free(rambuf); - IP6_FRAG_STATS_INC(ip6_frag.memerr); - return ERR_MEM; - } - /* Mirror this pbuf, although we might not need all of it. */ - newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, p->payload, newpbuflen); - if (newpbuf == NULL) { - ip6_frag_free_pbuf_custom_ref(pcr); - pbuf_free(rambuf); - IP6_FRAG_STATS_INC(ip6_frag.memerr); - return ERR_MEM; - } - pbuf_ref(p); - pcr->original = p; - pcr->pc.custom_free_function = ip6_frag_free_pbuf_custom; - - /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain - * so that it is removed when pbuf_dechain is later called on rambuf. - */ - pbuf_cat(rambuf, newpbuf); - left_to_copy -= newpbuflen; - if (left_to_copy) { - p = p->next; - } - } - poff = newpbuflen; -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - - /* Set headers */ - frag_hdr->_nexth = original_ip6hdr->_nexth; - frag_hdr->reserved = 0; - frag_hdr->_fragment_offset = lwip_htons((fragment_offset & IP6_FRAG_OFFSET_MASK) | (last ? 0 : IP6_FRAG_MORE_FLAG)); - frag_hdr->_identification = lwip_htonl(identification); - - IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_FRAGMENT); - IP6H_PLEN_SET(ip6hdr, cop + IP6_FRAG_HLEN); - - /* No need for separate header pbuf - we allowed room for it in rambuf - * when allocated. - */ - IP6_FRAG_STATS_INC(ip6_frag.xmit); - netif->output_ip6(netif, rambuf, dest); - - /* Unfortunately we can't reuse rambuf - the hardware may still be - * using the buffer. Instead we free it (and the ensuing chain) and - * recreate it next time round the loop. If we're lucky the hardware - * will have already sent the packet, the free will really free, and - * there will be zero memory penalty. - */ - - pbuf_free(rambuf); - left -= cop; - fragment_offset += cop; - } - return ERR_OK; -} - -#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/mld6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/mld6.c deleted file mode 100644 index 9acb82fe248769040b6a1f6ffd3376c78e3aa4df..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/mld6.c +++ /dev/null @@ -1,588 +0,0 @@ -/** - * @file - * Multicast listener discovery - * - * @defgroup mld6 MLD6 - * @ingroup ip6 - * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710. - * No support for MLDv2.\n - * To be called from TCPIP thread - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -/* Based on igmp.c implementation of igmp v2 protocol */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 && LWIP_IPV6_MLD /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/mld6.h" -#include "lwip/prot/mld6.h" -#include "lwip/icmp6.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/ip.h" -#include "lwip/inet_chksum.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/memp.h" -#include "lwip/stats.h" - -#include - - -/* - * MLD constants - */ -#define MLD6_HL 1 -#define MLD6_JOIN_DELAYING_MEMBER_TMR_MS (500) - -#define MLD6_GROUP_NON_MEMBER 0 -#define MLD6_GROUP_DELAYING_MEMBER 1 -#define MLD6_GROUP_IDLE_MEMBER 2 - -/* Forward declarations. */ -static struct mld_group *mld6_new_group(struct netif *ifp, const ip6_addr_t *addr); -static err_t mld6_remove_group(struct netif *netif, struct mld_group *group); -static void mld6_delayed_report(struct mld_group *group, u16_t maxresp); -static void mld6_send(struct netif *netif, struct mld_group *group, u8_t type); - - -/** - * Stop MLD processing on interface - * - * @param netif network interface on which stop MLD processing - */ -err_t -mld6_stop(struct netif *netif) -{ - struct mld_group *group = netif_mld6_data(netif); - - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, NULL); - - while (group != NULL) { - struct mld_group *next = group->next; /* avoid use-after-free below */ - - /* disable the group at the MAC level */ - if (netif->mld_mac_filter != NULL) { - netif->mld_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER); - } - - /* free group */ - memp_free(MEMP_MLD6_GROUP, group); - - /* move to "next" */ - group = next; - } - return ERR_OK; -} - -/** - * Report MLD memberships for this interface - * - * @param netif network interface on which report MLD memberships - */ -void -mld6_report_groups(struct netif *netif) -{ - struct mld_group *group = netif_mld6_data(netif); - - while (group != NULL) { - mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS); - group = group->next; - } -} - -/** - * Search for a group that is joined on a netif - * - * @param ifp the network interface for which to look - * @param addr the group ipv6 address to search for - * @return a struct mld_group* if the group has been found, - * NULL if the group wasn't found. - */ -struct mld_group * -mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr) -{ - struct mld_group *group = netif_mld6_data(ifp); - - while (group != NULL) { - if (ip6_addr_cmp(&(group->group_address), addr)) { - return group; - } - group = group->next; - } - - return NULL; -} - - -/** - * create a new group - * - * @param ifp the network interface for which to create - * @param addr the new group ipv6 - * @return a struct mld_group*, - * NULL on memory error. - */ -static struct mld_group * -mld6_new_group(struct netif *ifp, const ip6_addr_t *addr) -{ - struct mld_group *group; - - group = (struct mld_group *)memp_malloc(MEMP_MLD6_GROUP); - if (group != NULL) { - ip6_addr_set(&(group->group_address), addr); - group->timer = 0; /* Not running */ - group->group_state = MLD6_GROUP_IDLE_MEMBER; - group->last_reporter_flag = 0; - group->use = 0; - group->next = netif_mld6_data(ifp); - - netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group); - } - - return group; -} - -/** - * Remove a group from the mld_group_list, but do not free it yet - * - * @param group the group to remove - * @return ERR_OK if group was removed from the list, an err_t otherwise - */ -static err_t -mld6_remove_group(struct netif *netif, struct mld_group *group) -{ - err_t err = ERR_OK; - - /* Is it the first group? */ - if (netif_mld6_data(netif) == group) { - netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group->next); - } else { - /* look for group further down the list */ - struct mld_group *tmpGroup; - for (tmpGroup = netif_mld6_data(netif); tmpGroup != NULL; tmpGroup = tmpGroup->next) { - if (tmpGroup->next == group) { - tmpGroup->next = group->next; - break; - } - } - /* Group not find group */ - if (tmpGroup == NULL) { - err = ERR_ARG; - } - } - - return err; -} - - -/** - * Process an input MLD message. Called by icmp6_input. - * - * @param p the mld packet, p->payload pointing to the icmpv6 header - * @param inp the netif on which this packet was received - */ -void -mld6_input(struct pbuf *p, struct netif *inp) -{ - struct mld_header *mld_hdr; - struct mld_group *group; - - MLD6_STATS_INC(mld6.recv); - - /* Check that mld header fits in packet. */ - if (p->len < sizeof(struct mld_header)) { - /* @todo debug message */ - pbuf_free(p); - MLD6_STATS_INC(mld6.lenerr); - MLD6_STATS_INC(mld6.drop); - return; - } - - mld_hdr = (struct mld_header *)p->payload; - - switch (mld_hdr->type) { - case ICMP6_TYPE_MLQ: /* Multicast listener query. */ - /* Is it a general query? */ - if (ip6_addr_isallnodes_linklocal(ip6_current_dest_addr()) && - ip6_addr_isany(&(mld_hdr->multicast_address))) { - MLD6_STATS_INC(mld6.rx_general); - /* Report all groups, except all nodes group, and if-local groups. */ - group = netif_mld6_data(inp); - while (group != NULL) { - if ((!(ip6_addr_ismulticast_iflocal(&(group->group_address)))) && - (!(ip6_addr_isallnodes_linklocal(&(group->group_address))))) { - mld6_delayed_report(group, mld_hdr->max_resp_delay); - } - group = group->next; - } - } else { - /* Have we joined this group? - * We use IP6 destination address to have a memory aligned copy. - * mld_hdr->multicast_address should be the same. */ - MLD6_STATS_INC(mld6.rx_group); - group = mld6_lookfor_group(inp, ip6_current_dest_addr()); - if (group != NULL) { - /* Schedule a report. */ - mld6_delayed_report(group, mld_hdr->max_resp_delay); - } - } - break; /* ICMP6_TYPE_MLQ */ - case ICMP6_TYPE_MLR: /* Multicast listener report. */ - /* Have we joined this group? - * We use IP6 destination address to have a memory aligned copy. - * mld_hdr->multicast_address should be the same. */ - MLD6_STATS_INC(mld6.rx_report); - group = mld6_lookfor_group(inp, ip6_current_dest_addr()); - if (group != NULL) { - /* If we are waiting to report, cancel it. */ - if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) { - group->timer = 0; /* stopped */ - group->group_state = MLD6_GROUP_IDLE_MEMBER; - group->last_reporter_flag = 0; - } - } - break; /* ICMP6_TYPE_MLR */ - case ICMP6_TYPE_MLD: /* Multicast listener done. */ - /* Do nothing, router will query us. */ - break; /* ICMP6_TYPE_MLD */ - default: - MLD6_STATS_INC(mld6.proterr); - MLD6_STATS_INC(mld6.drop); - break; - } - - pbuf_free(p); -} - -/** - * @ingroup mld6 - * Join a group on a network interface. - * - * @param srcaddr ipv6 address of the network interface which should - * join a new group. If IP6_ADDR_ANY, join on all netifs - * @param groupaddr the ipv6 address of the group to join - * @return ERR_OK if group was joined on the netif(s), an err_t otherwise - */ -err_t -mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct netif *netif; - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we join this interface ? */ - if (ip6_addr_isany(srcaddr) || - netif_get_ip6_addr_match(netif, srcaddr) >= 0) { - err = mld6_joingroup_netif(netif, groupaddr); - if (err != ERR_OK) { - return err; - } - } - - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * @ingroup mld6 - * Join a group on a network interface. - * - * @param netif the network interface which should join a new group. - * @param groupaddr the ipv6 address of the group to join - * @return ERR_OK if group was joined on the netif, an err_t otherwise - */ -err_t -mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr) -{ - struct mld_group *group; - - /* find group or create a new one if not found */ - group = mld6_lookfor_group(netif, groupaddr); - - if (group == NULL) { - /* Joining a new group. Create a new group entry. */ - group = mld6_new_group(netif, groupaddr); - if (group == NULL) { - return ERR_MEM; - } - - /* Activate this address on the MAC layer. */ - if (netif->mld_mac_filter != NULL) { - netif->mld_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER); - } - - /* Report our membership. */ - MLD6_STATS_INC(mld6.tx_report); - mld6_send(netif, group, ICMP6_TYPE_MLR); - mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS); - } - - /* Increment group use */ - group->use++; - return ERR_OK; -} - -/** - * @ingroup mld6 - * Leave a group on a network interface. - * - * @param srcaddr ipv6 address of the network interface which should - * leave the group. If IP6_ISANY, leave on all netifs - * @param groupaddr the ipv6 address of the group to leave - * @return ERR_OK if group was left on the netif(s), an err_t otherwise - */ -err_t -mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct netif *netif; - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we leave this interface ? */ - if (ip6_addr_isany(srcaddr) || - netif_get_ip6_addr_match(netif, srcaddr) >= 0) { - err_t res = mld6_leavegroup_netif(netif, groupaddr); - if (err != ERR_OK) { - /* Store this result if we have not yet gotten a success */ - err = res; - } - } - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * @ingroup mld6 - * Leave a group on a network interface. - * - * @param netif the network interface which should leave the group. - * @param groupaddr the ipv6 address of the group to leave - * @return ERR_OK if group was left on the netif, an err_t otherwise - */ -err_t -mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr) -{ - struct mld_group *group; - - /* find group */ - group = mld6_lookfor_group(netif, groupaddr); - - if (group != NULL) { - /* Leave if there is no other use of the group */ - if (group->use <= 1) { - /* Remove the group from the list */ - mld6_remove_group(netif, group); - - /* If we are the last reporter for this group */ - if (group->last_reporter_flag) { - MLD6_STATS_INC(mld6.tx_leave); - mld6_send(netif, group, ICMP6_TYPE_MLD); - } - - /* Disable the group at the MAC level */ - if (netif->mld_mac_filter != NULL) { - netif->mld_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER); - } - - /* free group struct */ - memp_free(MEMP_MLD6_GROUP, group); - } else { - /* Decrement group use */ - group->use--; - } - - /* Left group */ - return ERR_OK; - } - - /* Group not found */ - return ERR_VAL; -} - - -/** - * Periodic timer for mld processing. Must be called every - * MLD6_TMR_INTERVAL milliseconds (100). - * - * When a delaying member expires, a membership report is sent. - */ -void -mld6_tmr(void) -{ - struct netif *netif = netif_list; - - while (netif != NULL) { - struct mld_group *group = netif_mld6_data(netif); - - while (group != NULL) { - if (group->timer > 0) { - group->timer--; - if (group->timer == 0) { - /* If the state is MLD6_GROUP_DELAYING_MEMBER then we send a report for this group */ - if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) { - MLD6_STATS_INC(mld6.tx_report); - mld6_send(netif, group, ICMP6_TYPE_MLR); - group->group_state = MLD6_GROUP_IDLE_MEMBER; - } - } - } - group = group->next; - } - netif = netif->next; - } -} - -/** - * Schedule a delayed membership report for a group - * - * @param group the mld_group for which "delaying" membership report - * should be sent - * @param maxresp the max resp delay provided in the query - */ -static void -mld6_delayed_report(struct mld_group *group, u16_t maxresp) -{ - /* Convert maxresp from milliseconds to tmr ticks */ - maxresp = maxresp / MLD6_TMR_INTERVAL; - if (maxresp == 0) { - maxresp = 1; - } - -#ifdef LWIP_RAND - /* Randomize maxresp. (if LWIP_RAND is supported) */ - maxresp = LWIP_RAND() % maxresp; - if (maxresp == 0) { - maxresp = 1; - } -#endif /* LWIP_RAND */ - - /* Apply timer value if no report has been scheduled already. */ - if ((group->group_state == MLD6_GROUP_IDLE_MEMBER) || - ((group->group_state == MLD6_GROUP_DELAYING_MEMBER) && - ((group->timer == 0) || (maxresp < group->timer)))) { - group->timer = maxresp; - group->group_state = MLD6_GROUP_DELAYING_MEMBER; - } -} - -/** - * Send a MLD message (report or done). - * - * An IPv6 hop-by-hop options header with a router alert option - * is prepended. - * - * @param group the group to report or quit - * @param type ICMP6_TYPE_MLR (report) or ICMP6_TYPE_MLD (done) - */ -static void -mld6_send(struct netif *netif, struct mld_group *group, u8_t type) -{ - struct mld_header *mld_hdr; - struct pbuf *p; - const ip6_addr_t *src_addr; - - /* Allocate a packet. Size is MLD header + IPv6 Hop-by-hop options header. */ - p = pbuf_alloc(PBUF_IP, sizeof(struct mld_header) + sizeof(struct ip6_hbh_hdr), PBUF_RAM); - if (p == NULL) { - MLD6_STATS_INC(mld6.memerr); - return; - } - - /* Move to make room for Hop-by-hop options header. */ - if (pbuf_header(p, -IP6_HBH_HLEN)) { - pbuf_free(p); - MLD6_STATS_INC(mld6.lenerr); - return; - } - - /* Select our source address. */ - if (!ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) { - /* This is a special case, when we are performing duplicate address detection. - * We must join the multicast group, but we don't have a valid address yet. */ - src_addr = IP6_ADDR_ANY6; - } else { - /* Use link-local address as source address. */ - src_addr = netif_ip6_addr(netif, 0); - } - - /* MLD message header pointer. */ - mld_hdr = (struct mld_header *)p->payload; - - /* Set fields. */ - mld_hdr->type = type; - mld_hdr->code = 0; - mld_hdr->chksum = 0; - mld_hdr->max_resp_delay = 0; - mld_hdr->reserved = 0; - ip6_addr_set(&(mld_hdr->multicast_address), &(group->group_address)); - -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { - mld_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, - src_addr, &(group->group_address)); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - /* Add hop-by-hop headers options: router alert with MLD value. */ - ip6_options_add_hbh_ra(p, IP6_NEXTH_ICMP6, IP6_ROUTER_ALERT_VALUE_MLD); - - if (type == ICMP6_TYPE_MLR) { - /* Remember we were the last to report */ - group->last_reporter_flag = 1; - } - - /* Send the packet out. */ - MLD6_STATS_INC(mld6.xmit); - ip6_output_if(p, (ip6_addr_isany(src_addr)) ? NULL : src_addr, &(group->group_address), - MLD6_HL, 0, IP6_NEXTH_HOPBYHOP, netif); - pbuf_free(p); -} - -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/nd6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/nd6.c deleted file mode 100644 index 0b367181b2db280751c3d4a5d2a5ab9720427d69..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/ipv6/nd6.c +++ /dev/null @@ -1,2102 +0,0 @@ -/** - * @file - * - * Neighbor discovery and stateless address autoconfiguration for IPv6. - * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 - * (Address autoconfiguration). - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/nd6.h" -#include "lwip/priv/nd6_priv.h" -#include "lwip/prot/nd6.h" -#include "lwip/prot/icmp6.h" -#include "lwip/pbuf.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/icmp6.h" -#include "lwip/mld6.h" -#include "lwip/ip.h" -#include "lwip/stats.h" -#include "lwip/dns.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -#if LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK -#error LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK -#endif - -/* Router tables. */ -struct nd6_neighbor_cache_entry neighbor_cache[LWIP_ND6_NUM_NEIGHBORS]; -struct nd6_destination_cache_entry destination_cache[LWIP_ND6_NUM_DESTINATIONS]; -struct nd6_prefix_list_entry prefix_list[LWIP_ND6_NUM_PREFIXES]; -struct nd6_router_list_entry default_router_list[LWIP_ND6_NUM_ROUTERS]; - -/* Default values, can be updated by a RA message. */ -u32_t reachable_time = LWIP_ND6_REACHABLE_TIME; -u32_t retrans_timer = LWIP_ND6_RETRANS_TIMER; /* @todo implement this value in timer */ - -/* Index for cache entries. */ -static u8_t nd6_cached_neighbor_index; -static u8_t nd6_cached_destination_index; - -/* Multicast address holder. */ -static ip6_addr_t multicast_address; - -/* Static buffer to parse RA packet options (size of a prefix option, biggest option) */ -static u8_t nd6_ra_buffer[sizeof(struct prefix_option)]; - -/* Forward declarations. */ -static s8_t nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr); -static s8_t nd6_new_neighbor_cache_entry(void); -static void nd6_free_neighbor_cache_entry(s8_t i); -static s8_t nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr); -static s8_t nd6_new_destination_cache_entry(void); -static s8_t nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif); -static s8_t nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif); -static s8_t nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif); -static s8_t nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif); -static s8_t nd6_get_onlink_prefix(ip6_addr_t *prefix, struct netif *netif); -static s8_t nd6_new_onlink_prefix(ip6_addr_t *prefix, struct netif *netif); -static s8_t nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif); -static err_t nd6_queue_packet(s8_t neighbor_index, struct pbuf *q); - -#define ND6_SEND_FLAG_MULTICAST_DEST 0x01 -#define ND6_SEND_FLAG_ALLNODES_DEST 0x02 -static void nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags); -static void nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags); -static void nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags); -#if LWIP_IPV6_SEND_ROUTER_SOLICIT -static err_t nd6_send_rs(struct netif *netif); -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ - -#if LWIP_ND6_QUEUEING -static void nd6_free_q(struct nd6_q_entry *q); -#else /* LWIP_ND6_QUEUEING */ -#define nd6_free_q(q) pbuf_free(q) -#endif /* LWIP_ND6_QUEUEING */ -static void nd6_send_q(s8_t i); - - -/** - * Process an incoming neighbor discovery message - * - * @param p the nd packet, p->payload pointing to the icmpv6 header - * @param inp the netif on which this packet was received - */ -void -nd6_input(struct pbuf *p, struct netif *inp) -{ - u8_t msg_type; - s8_t i; - - ND6_STATS_INC(nd6.recv); - - msg_type = *((u8_t *)p->payload); - switch (msg_type) { - case ICMP6_TYPE_NA: /* Neighbor Advertisement. */ - { - struct na_header *na_hdr; - struct lladdr_option *lladdr_opt; - - /* Check that na header fits in packet. */ - if (p->len < (sizeof(struct na_header))) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - na_hdr = (struct na_header *)p->payload; - - /* Unsolicited NA?*/ - if (ip6_addr_ismulticast(ip6_current_dest_addr())) { - ip6_addr_t target_address; - - /* This is an unsolicited NA. - * link-layer changed? - * part of DAD mechanism? */ - - /* Create an aligned copy. */ - ip6_addr_set(&target_address, &(na_hdr->target_address)); - -#if LWIP_IPV6_DUP_DETECT_ATTEMPTS - /* If the target address matches this netif, it is a DAD response. */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) && - ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) { - /* We are using a duplicate address. */ - netif_ip6_addr_set_state(inp, i, IP6_ADDR_INVALID); - -#if LWIP_IPV6_AUTOCONFIG - /* Check to see if this address was autoconfigured. */ - if (!ip6_addr_islinklocal(&target_address)) { - i = nd6_get_onlink_prefix(&target_address, inp); - if (i >= 0) { - /* Mark this prefix as duplicate, so that we don't use it - * to generate this address again. */ - prefix_list[i].flags |= ND6_PREFIX_AUTOCONFIG_ADDRESS_DUPLICATE; - } - } -#endif /* LWIP_IPV6_AUTOCONFIG */ - - pbuf_free(p); - return; - } - } -#endif /* LWIP_IPV6_DUP_DETECT_ATTEMPTS */ - - /* Check that link-layer address option also fits in packet. */ - if (p->len < (sizeof(struct na_header) + 2)) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); - - if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - /* This is an unsolicited NA, most likely there was a LLADDR change. */ - i = nd6_find_neighbor_cache_entry(&target_address); - if (i >= 0) { - if (na_hdr->flags & ND6_FLAG_OVERRIDE) { - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - } - } - } else { - ip6_addr_t target_address; - - /* This is a solicited NA. - * neighbor address resolution response? - * neighbor unreachability detection response? */ - - /* Create an aligned copy. */ - ip6_addr_set(&target_address, &(na_hdr->target_address)); - - /* Find the cache entry corresponding to this na. */ - i = nd6_find_neighbor_cache_entry(&target_address); - if (i < 0) { - /* We no longer care about this target address. drop it. */ - pbuf_free(p); - return; - } - - /* Update cache entry. */ - if ((na_hdr->flags & ND6_FLAG_OVERRIDE) || - (neighbor_cache[i].state == ND6_INCOMPLETE)) { - /* Check that link-layer address option also fits in packet. */ - if (p->len < (sizeof(struct na_header) + 2)) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); - - if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - } - - neighbor_cache[i].netif = inp; - neighbor_cache[i].state = ND6_REACHABLE; - neighbor_cache[i].counter.reachable_time = reachable_time; - - /* Send queued packets, if any. */ - if (neighbor_cache[i].q != NULL) { - nd6_send_q(i); - } - } - - break; /* ICMP6_TYPE_NA */ - } - case ICMP6_TYPE_NS: /* Neighbor solicitation. */ - { - struct ns_header *ns_hdr; - struct lladdr_option *lladdr_opt; - u8_t accepted; - - /* Check that ns header fits in packet. */ - if (p->len < sizeof(struct ns_header)) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - ns_hdr = (struct ns_header *)p->payload; - - /* Check if there is a link-layer address provided. Only point to it if in this buffer. */ - if (p->len >= (sizeof(struct ns_header) + 2)) { - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header)); - if (p->len < (sizeof(struct ns_header) + (lladdr_opt->length << 3))) { - lladdr_opt = NULL; - } - } else { - lladdr_opt = NULL; - } - - /* Check if the target address is configured on the receiving netif. */ - accepted = 0; - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { - if ((ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) || - (ip6_addr_istentative(netif_ip6_addr_state(inp, i)) && - ip6_addr_isany(ip6_current_src_addr()))) && - ip6_addr_cmp(&(ns_hdr->target_address), netif_ip6_addr(inp, i))) { - accepted = 1; - break; - } - } - - /* NS not for us? */ - if (!accepted) { - pbuf_free(p); - return; - } - - /* Check for ANY address in src (DAD algorithm). */ - if (ip6_addr_isany(ip6_current_src_addr())) { - /* Sender is validating this address. */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { - if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) && - ip6_addr_cmp(&(ns_hdr->target_address), netif_ip6_addr(inp, i))) { - /* Send a NA back so that the sender does not use this address. */ - nd6_send_na(inp, netif_ip6_addr(inp, i), ND6_FLAG_OVERRIDE | ND6_SEND_FLAG_ALLNODES_DEST); - if (ip6_addr_istentative(netif_ip6_addr_state(inp, i))) { - /* We shouldn't use this address either. */ - netif_ip6_addr_set_state(inp, i, IP6_ADDR_INVALID); - } - } - } - } else { - ip6_addr_t target_address; - - /* Sender is trying to resolve our address. */ - /* Verify that they included their own link-layer address. */ - if (lladdr_opt == NULL) { - /* Not a valid message. */ - pbuf_free(p); - ND6_STATS_INC(nd6.proterr); - ND6_STATS_INC(nd6.drop); - return; - } - - i = nd6_find_neighbor_cache_entry(ip6_current_src_addr()); - if (i>= 0) { - /* We already have a record for the solicitor. */ - if (neighbor_cache[i].state == ND6_INCOMPLETE) { - neighbor_cache[i].netif = inp; - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - - /* Delay probe in case we get confirmation of reachability from upper layer (TCP). */ - neighbor_cache[i].state = ND6_DELAY; - neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; - } - } else { - /* Add their IPv6 address and link-layer address to neighbor cache. - * We will need it at least to send a unicast NA message, but most - * likely we will also be communicating with this node soon. */ - i = nd6_new_neighbor_cache_entry(); - if (i < 0) { - /* We couldn't assign a cache entry for this neighbor. - * we won't be able to reply. drop it. */ - pbuf_free(p); - ND6_STATS_INC(nd6.memerr); - return; - } - neighbor_cache[i].netif = inp; - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - ip6_addr_set(&(neighbor_cache[i].next_hop_address), ip6_current_src_addr()); - - /* Receiving a message does not prove reachability: only in one direction. - * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ - neighbor_cache[i].state = ND6_DELAY; - neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; - } - - /* Create an aligned copy. */ - ip6_addr_set(&target_address, &(ns_hdr->target_address)); - - /* Send back a NA for us. Allocate the reply pbuf. */ - nd6_send_na(inp, &target_address, ND6_FLAG_SOLICITED | ND6_FLAG_OVERRIDE); - } - - break; /* ICMP6_TYPE_NS */ - } - case ICMP6_TYPE_RA: /* Router Advertisement. */ - { - struct ra_header *ra_hdr; - u8_t *buffer; /* Used to copy options. */ - u16_t offset; -#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS - /* There can by multiple RDNSS options per RA */ - u8_t rdnss_server_idx = 0; -#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */ - - /* Check that RA header fits in packet. */ - if (p->len < sizeof(struct ra_header)) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - ra_hdr = (struct ra_header *)p->payload; - - /* If we are sending RS messages, stop. */ -#if LWIP_IPV6_SEND_ROUTER_SOLICIT - /* ensure at least one solicitation is sent */ - if ((inp->rs_count < LWIP_ND6_MAX_MULTICAST_SOLICIT) || - (nd6_send_rs(inp) == ERR_OK)) { - inp->rs_count = 0; - } -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ - - /* Get the matching default router entry. */ - i = nd6_get_router(ip6_current_src_addr(), inp); - if (i < 0) { - /* Create a new router entry. */ - i = nd6_new_router(ip6_current_src_addr(), inp); - } - - if (i < 0) { - /* Could not create a new router entry. */ - pbuf_free(p); - ND6_STATS_INC(nd6.memerr); - return; - } - - /* Re-set invalidation timer. */ - default_router_list[i].invalidation_timer = lwip_htons(ra_hdr->router_lifetime); - - /* Re-set default timer values. */ -#if LWIP_ND6_ALLOW_RA_UPDATES - if (ra_hdr->retrans_timer > 0) { - retrans_timer = lwip_htonl(ra_hdr->retrans_timer); - } - if (ra_hdr->reachable_time > 0) { - reachable_time = lwip_htonl(ra_hdr->reachable_time); - } -#endif /* LWIP_ND6_ALLOW_RA_UPDATES */ - - /* @todo set default hop limit... */ - /* ra_hdr->current_hop_limit;*/ - - /* Update flags in local entry (incl. preference). */ - default_router_list[i].flags = ra_hdr->flags; - - /* Offset to options. */ - offset = sizeof(struct ra_header); - - /* Process each option. */ - while ((p->tot_len - offset) > 0) { - if (p->len == p->tot_len) { - /* no need to copy from contiguous pbuf */ - buffer = &((u8_t*)p->payload)[offset]; - } else { - buffer = nd6_ra_buffer; - if (pbuf_copy_partial(p, buffer, sizeof(struct prefix_option), offset) != sizeof(struct prefix_option)) { - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - } - if (buffer[1] == 0) { - /* zero-length extension. drop packet */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - switch (buffer[0]) { - case ND6_OPTION_TYPE_SOURCE_LLADDR: - { - struct lladdr_option *lladdr_opt; - lladdr_opt = (struct lladdr_option *)buffer; - if ((default_router_list[i].neighbor_entry != NULL) && - (default_router_list[i].neighbor_entry->state == ND6_INCOMPLETE)) { - SMEMCPY(default_router_list[i].neighbor_entry->lladdr, lladdr_opt->addr, inp->hwaddr_len); - default_router_list[i].neighbor_entry->state = ND6_REACHABLE; - default_router_list[i].neighbor_entry->counter.reachable_time = reachable_time; - } - break; - } - case ND6_OPTION_TYPE_MTU: - { - struct mtu_option *mtu_opt; - mtu_opt = (struct mtu_option *)buffer; - if (lwip_htonl(mtu_opt->mtu) >= 1280) { -#if LWIP_ND6_ALLOW_RA_UPDATES - inp->mtu = (u16_t)lwip_htonl(mtu_opt->mtu); -#endif /* LWIP_ND6_ALLOW_RA_UPDATES */ - } - break; - } - case ND6_OPTION_TYPE_PREFIX_INFO: - { - struct prefix_option *prefix_opt; - prefix_opt = (struct prefix_option *)buffer; - - if ((prefix_opt->flags & ND6_PREFIX_FLAG_ON_LINK) && - (prefix_opt->prefix_length == 64) && - !ip6_addr_islinklocal(&(prefix_opt->prefix))) { - /* Add to on-link prefix list. */ - s8_t prefix; - ip6_addr_t prefix_addr; - - /* Get a memory-aligned copy of the prefix. */ - ip6_addr_set(&prefix_addr, &(prefix_opt->prefix)); - - /* find cache entry for this prefix. */ - prefix = nd6_get_onlink_prefix(&prefix_addr, inp); - if (prefix < 0) { - /* Create a new cache entry. */ - prefix = nd6_new_onlink_prefix(&prefix_addr, inp); - } - if (prefix >= 0) { - prefix_list[prefix].invalidation_timer = lwip_htonl(prefix_opt->valid_lifetime); - -#if LWIP_IPV6_AUTOCONFIG - if (prefix_opt->flags & ND6_PREFIX_FLAG_AUTONOMOUS) { - /* Mark prefix as autonomous, so that address autoconfiguration can take place. - * Only OR flag, so that we don't over-write other flags (such as ADDRESS_DUPLICATE)*/ - prefix_list[prefix].flags |= ND6_PREFIX_AUTOCONFIG_AUTONOMOUS; - } -#endif /* LWIP_IPV6_AUTOCONFIG */ - } - } - - break; - } - case ND6_OPTION_TYPE_ROUTE_INFO: - /* @todo implement preferred routes. - struct route_option * route_opt; - route_opt = (struct route_option *)buffer;*/ - - break; -#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS - case ND6_OPTION_TYPE_RDNSS: - { - u8_t num, n; - struct rdnss_option * rdnss_opt; - - rdnss_opt = (struct rdnss_option *)buffer; - num = (rdnss_opt->length - 1) / 2; - for (n = 0; (rdnss_server_idx < DNS_MAX_SERVERS) && (n < num); n++) { - ip_addr_t rdnss_address; - - /* Get a memory-aligned copy of the prefix. */ - ip_addr_copy_from_ip6(rdnss_address, rdnss_opt->rdnss_address[n]); - - if (htonl(rdnss_opt->lifetime) > 0) { - /* TODO implement Lifetime > 0 */ - dns_setserver(rdnss_server_idx++, &rdnss_address); - } else { - /* TODO implement DNS removal in dns.c */ - u8_t s; - for (s = 0; s < DNS_MAX_SERVERS; s++) { - const ip_addr_t *addr = dns_getserver(s); - if(ip_addr_cmp(addr, &rdnss_address)) { - dns_setserver(s, NULL); - } - } - } - } - break; - } -#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */ - default: - /* Unrecognized option, abort. */ - ND6_STATS_INC(nd6.proterr); - break; - } - /* option length is checked earlier to be non-zero to make sure loop ends */ - offset += 8 * ((u16_t)buffer[1]); - } - - break; /* ICMP6_TYPE_RA */ - } - case ICMP6_TYPE_RD: /* Redirect */ - { - struct redirect_header *redir_hdr; - struct lladdr_option *lladdr_opt; - ip6_addr_t tmp; - - /* Check that Redir header fits in packet. */ - if (p->len < sizeof(struct redirect_header)) { - /* @todo debug message */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - redir_hdr = (struct redirect_header *)p->payload; - - if (p->len >= (sizeof(struct redirect_header) + 2)) { - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct redirect_header)); - if (p->len < (sizeof(struct redirect_header) + (lladdr_opt->length << 3))) { - lladdr_opt = NULL; - } - } else { - lladdr_opt = NULL; - } - - /* Copy original destination address to current source address, to have an aligned copy. */ - ip6_addr_set(&tmp, &(redir_hdr->destination_address)); - - /* Find dest address in cache */ - i = nd6_find_destination_cache_entry(&tmp); - if (i < 0) { - /* Destination not in cache, drop packet. */ - pbuf_free(p); - return; - } - - /* Set the new target address. */ - ip6_addr_set(&(destination_cache[i].next_hop_addr), &(redir_hdr->target_address)); - - /* If Link-layer address of other router is given, try to add to neighbor cache. */ - if (lladdr_opt != NULL) { - if (lladdr_opt->type == ND6_OPTION_TYPE_TARGET_LLADDR) { - /* Copy target address to current source address, to have an aligned copy. */ - ip6_addr_set(&tmp, &(redir_hdr->target_address)); - - i = nd6_find_neighbor_cache_entry(&tmp); - if (i < 0) { - i = nd6_new_neighbor_cache_entry(); - if (i >= 0) { - neighbor_cache[i].netif = inp; - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - ip6_addr_set(&(neighbor_cache[i].next_hop_address), &tmp); - - /* Receiving a message does not prove reachability: only in one direction. - * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ - neighbor_cache[i].state = ND6_DELAY; - neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; - } - } - if (i >= 0) { - if (neighbor_cache[i].state == ND6_INCOMPLETE) { - MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); - /* Receiving a message does not prove reachability: only in one direction. - * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ - neighbor_cache[i].state = ND6_DELAY; - neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; - } - } - } - } - break; /* ICMP6_TYPE_RD */ - } - case ICMP6_TYPE_PTB: /* Packet too big */ - { - struct icmp6_hdr *icmp6hdr; /* Packet too big message */ - struct ip6_hdr *ip6hdr; /* IPv6 header of the packet which caused the error */ - u32_t pmtu; - ip6_addr_t tmp; - - /* Check that ICMPv6 header + IPv6 header fit in payload */ - if (p->len < (sizeof(struct icmp6_hdr) + IP6_HLEN)) { - /* drop short packets */ - pbuf_free(p); - ND6_STATS_INC(nd6.lenerr); - ND6_STATS_INC(nd6.drop); - return; - } - - icmp6hdr = (struct icmp6_hdr *)p->payload; - ip6hdr = (struct ip6_hdr *)((u8_t*)p->payload + sizeof(struct icmp6_hdr)); - - /* Copy original destination address to current source address, to have an aligned copy. */ - ip6_addr_set(&tmp, &(ip6hdr->dest)); - - /* Look for entry in destination cache. */ - i = nd6_find_destination_cache_entry(&tmp); - if (i < 0) { - /* Destination not in cache, drop packet. */ - pbuf_free(p); - return; - } - - /* Change the Path MTU. */ - pmtu = lwip_htonl(icmp6hdr->data); - destination_cache[i].pmtu = (u16_t)LWIP_MIN(pmtu, 0xFFFF); - - break; /* ICMP6_TYPE_PTB */ - } - - default: - ND6_STATS_INC(nd6.proterr); - ND6_STATS_INC(nd6.drop); - break; /* default */ - } - - pbuf_free(p); -} - - -/** - * Periodic timer for Neighbor discovery functions: - * - * - Update neighbor reachability states - * - Update destination cache entries age - * - Update invalidation timers of default routers and on-link prefixes - * - Perform duplicate address detection (DAD) for our addresses - * - Send router solicitations - */ -void -nd6_tmr(void) -{ - s8_t i; - struct netif *netif; - - /* Process neighbor entries. */ - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - switch (neighbor_cache[i].state) { - case ND6_INCOMPLETE: - if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) && - (!neighbor_cache[i].isrouter)) { - /* Retries exceeded. */ - nd6_free_neighbor_cache_entry(i); - } else { - /* Send a NS for this entry. */ - neighbor_cache[i].counter.probes_sent++; - nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST); - } - break; - case ND6_REACHABLE: - /* Send queued packets, if any are left. Should have been sent already. */ - if (neighbor_cache[i].q != NULL) { - nd6_send_q(i); - } - if (neighbor_cache[i].counter.reachable_time <= ND6_TMR_INTERVAL) { - /* Change to stale state. */ - neighbor_cache[i].state = ND6_STALE; - neighbor_cache[i].counter.stale_time = 0; - } else { - neighbor_cache[i].counter.reachable_time -= ND6_TMR_INTERVAL; - } - break; - case ND6_STALE: - neighbor_cache[i].counter.stale_time++; - break; - case ND6_DELAY: - if (neighbor_cache[i].counter.delay_time <= 1) { - /* Change to PROBE state. */ - neighbor_cache[i].state = ND6_PROBE; - neighbor_cache[i].counter.probes_sent = 0; - } else { - neighbor_cache[i].counter.delay_time--; - } - break; - case ND6_PROBE: - if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) && - (!neighbor_cache[i].isrouter)) { - /* Retries exceeded. */ - nd6_free_neighbor_cache_entry(i); - } else { - /* Send a NS for this entry. */ - neighbor_cache[i].counter.probes_sent++; - nd6_send_neighbor_cache_probe(&neighbor_cache[i], 0); - } - break; - case ND6_NO_ENTRY: - default: - /* Do nothing. */ - break; - } - } - - /* Process destination entries. */ - for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { - destination_cache[i].age++; - } - - /* Process router entries. */ - for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { - if (default_router_list[i].neighbor_entry != NULL) { - /* Active entry. */ - if (default_router_list[i].invalidation_timer > 0) { - default_router_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000; - } - if (default_router_list[i].invalidation_timer < ND6_TMR_INTERVAL / 1000) { - /* Less than 1 second remaining. Clear this entry. */ - default_router_list[i].neighbor_entry->isrouter = 0; - default_router_list[i].neighbor_entry = NULL; - default_router_list[i].invalidation_timer = 0; - default_router_list[i].flags = 0; - } - } - } - - /* Process prefix entries. */ - for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { - if (prefix_list[i].netif != NULL) { - if (prefix_list[i].invalidation_timer < ND6_TMR_INTERVAL / 1000) { - /* Entry timed out, remove it */ - prefix_list[i].invalidation_timer = 0; - -#if LWIP_IPV6_AUTOCONFIG - /* If any addresses were configured with this prefix, remove them */ - if (prefix_list[i].flags & ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED) { - s8_t j; - - for (j = 1; j < LWIP_IPV6_NUM_ADDRESSES; j++) { - if ((netif_ip6_addr_state(prefix_list[i].netif, j) != IP6_ADDR_INVALID) && - ip6_addr_netcmp(&prefix_list[i].prefix, netif_ip6_addr(prefix_list[i].netif, j))) { - netif_ip6_addr_set_state(prefix_list[i].netif, j, IP6_ADDR_INVALID); - prefix_list[i].flags = 0; - - /* Exit loop. */ - break; - } - } - } -#endif /* LWIP_IPV6_AUTOCONFIG */ - - prefix_list[i].netif = NULL; - prefix_list[i].flags = 0; - } else { - prefix_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000; - -#if LWIP_IPV6_AUTOCONFIG - /* Initiate address autoconfiguration for this prefix, if conditions are met. */ - if (prefix_list[i].netif->ip6_autoconfig_enabled && - (prefix_list[i].flags & ND6_PREFIX_AUTOCONFIG_AUTONOMOUS) && - !(prefix_list[i].flags & ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED)) { - s8_t j; - /* Try to get an address on this netif that is invalid. - * Skip 0 index (link-local address) */ - for (j = 1; j < LWIP_IPV6_NUM_ADDRESSES; j++) { - if (netif_ip6_addr_state(prefix_list[i].netif, j) == IP6_ADDR_INVALID) { - /* Generate an address using this prefix and interface ID from link-local address. */ - netif_ip6_addr_set_parts(prefix_list[i].netif, j, - prefix_list[i].prefix.addr[0], prefix_list[i].prefix.addr[1], - netif_ip6_addr(prefix_list[i].netif, 0)->addr[2], netif_ip6_addr(prefix_list[i].netif, 0)->addr[3]); - - /* Mark it as tentative (DAD will be performed if configured). */ - netif_ip6_addr_set_state(prefix_list[i].netif, j, IP6_ADDR_TENTATIVE); - - /* Mark this prefix with ADDRESS_GENERATED, so that we don't try again. */ - prefix_list[i].flags |= ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED; - - /* Exit loop. */ - break; - } - } - } -#endif /* LWIP_IPV6_AUTOCONFIG */ - } - } - } - - - /* Process our own addresses, if DAD configured. */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { - u8_t addr_state = netif_ip6_addr_state(netif, i); - if (ip6_addr_istentative(addr_state)) { - if ((addr_state & IP6_ADDR_TENTATIVE_COUNT_MASK) >= LWIP_IPV6_DUP_DETECT_ATTEMPTS) { - /* No NA received in response. Mark address as valid. */ - netif_ip6_addr_set_state(netif, i, IP6_ADDR_PREFERRED); - /* @todo implement preferred and valid lifetimes. */ - } else if (netif->flags & NETIF_FLAG_UP) { - /* Send a NS for this address. */ - nd6_send_ns(netif, netif_ip6_addr(netif, i), ND6_SEND_FLAG_MULTICAST_DEST); - /* tentative: set next state by increasing by one */ - netif_ip6_addr_set_state(netif, i, addr_state + 1); - /* @todo send max 1 NS per tmr call? enable return*/ - /*return;*/ - } - } - } - } - -#if LWIP_IPV6_SEND_ROUTER_SOLICIT - /* Send router solicitation messages, if necessary. */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - if ((netif->rs_count > 0) && (netif->flags & NETIF_FLAG_UP) && - (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, 0)))) { - if (nd6_send_rs(netif) == ERR_OK) { - netif->rs_count--; - } - } - } -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ - -} - -/** Send a neighbor solicitation message for a specific neighbor cache entry - * - * @param entry the neightbor cache entry for wich to send the message - * @param flags one of ND6_SEND_FLAG_* - */ -static void -nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags) -{ - nd6_send_ns(entry->netif, &entry->next_hop_address, flags); -} - -/** - * Send a neighbor solicitation message - * - * @param netif the netif on which to send the message - * @param target_addr the IPv6 target address for the ND message - * @param flags one of ND6_SEND_FLAG_* - */ -static void -nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags) -{ - struct ns_header *ns_hdr; - struct pbuf *p; - const ip6_addr_t *src_addr; - u16_t lladdr_opt_len; - - if (ip6_addr_isvalid(netif_ip6_addr_state(netif,0))) { - /* Use link-local address as source address. */ - src_addr = netif_ip6_addr(netif, 0); - /* calculate option length (in 8-byte-blocks) */ - lladdr_opt_len = ((netif->hwaddr_len + 2) + 7) >> 3; - } else { - src_addr = IP6_ADDR_ANY6; - /* Option "MUST NOT be included when the source IP address is the unspecified address." */ - lladdr_opt_len = 0; - } - - /* Allocate a packet. */ - p = pbuf_alloc(PBUF_IP, sizeof(struct ns_header) + (lladdr_opt_len << 3), PBUF_RAM); - if (p == NULL) { - ND6_STATS_INC(nd6.memerr); - return; - } - - /* Set fields. */ - ns_hdr = (struct ns_header *)p->payload; - - ns_hdr->type = ICMP6_TYPE_NS; - ns_hdr->code = 0; - ns_hdr->chksum = 0; - ns_hdr->reserved = 0; - ip6_addr_set(&(ns_hdr->target_address), target_addr); - - if (lladdr_opt_len != 0) { - struct lladdr_option *lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header)); - lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR; - lladdr_opt->length = (u8_t)lladdr_opt_len; - SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); - } - - /* Generate the solicited node address for the target address. */ - if (flags & ND6_SEND_FLAG_MULTICAST_DEST) { - ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]); - target_addr = &multicast_address; - } - -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { - ns_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, - target_addr); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - /* Send the packet out. */ - ND6_STATS_INC(nd6.xmit); - ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, target_addr, - LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif); - pbuf_free(p); -} - -/** - * Send a neighbor advertisement message - * - * @param netif the netif on which to send the message - * @param target_addr the IPv6 target address for the ND message - * @param flags one of ND6_SEND_FLAG_* - */ -static void -nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags) -{ - struct na_header *na_hdr; - struct lladdr_option *lladdr_opt; - struct pbuf *p; - const ip6_addr_t *src_addr; - const ip6_addr_t *dest_addr; - u16_t lladdr_opt_len; - - /* Use link-local address as source address. */ - /* src_addr = netif_ip6_addr(netif, 0); */ - /* Use target address as source address. */ - src_addr = target_addr; - - /* Allocate a packet. */ - lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0); - p = pbuf_alloc(PBUF_IP, sizeof(struct na_header) + (lladdr_opt_len << 3), PBUF_RAM); - if (p == NULL) { - ND6_STATS_INC(nd6.memerr); - return; - } - - /* Set fields. */ - na_hdr = (struct na_header *)p->payload; - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); - - na_hdr->type = ICMP6_TYPE_NA; - na_hdr->code = 0; - na_hdr->chksum = 0; - na_hdr->flags = flags & 0xf0; - na_hdr->reserved[0] = 0; - na_hdr->reserved[1] = 0; - na_hdr->reserved[2] = 0; - ip6_addr_set(&(na_hdr->target_address), target_addr); - - lladdr_opt->type = ND6_OPTION_TYPE_TARGET_LLADDR; - lladdr_opt->length = (u8_t)lladdr_opt_len; - SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); - - /* Generate the solicited node address for the target address. */ - if (flags & ND6_SEND_FLAG_MULTICAST_DEST) { - ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]); - dest_addr = &multicast_address; - } else if (flags & ND6_SEND_FLAG_ALLNODES_DEST) { - ip6_addr_set_allnodes_linklocal(&multicast_address); - dest_addr = &multicast_address; - } else { - dest_addr = ip6_current_src_addr(); - } - -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { - na_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, - dest_addr); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - /* Send the packet out. */ - ND6_STATS_INC(nd6.xmit); - ip6_output_if(p, src_addr, dest_addr, - LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif); - pbuf_free(p); -} - -#if LWIP_IPV6_SEND_ROUTER_SOLICIT -/** - * Send a router solicitation message - * - * @param netif the netif on which to send the message - */ -static err_t -nd6_send_rs(struct netif *netif) -{ - struct rs_header *rs_hdr; - struct lladdr_option *lladdr_opt; - struct pbuf *p; - const ip6_addr_t *src_addr; - err_t err; - u16_t lladdr_opt_len = 0; - - /* Link-local source address, or unspecified address? */ - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) { - src_addr = netif_ip6_addr(netif, 0); - } else { - src_addr = IP6_ADDR_ANY6; - } - - /* Generate the all routers target address. */ - ip6_addr_set_allrouters_linklocal(&multicast_address); - - /* Allocate a packet. */ - if (src_addr != IP6_ADDR_ANY6) { - lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0); - } - p = pbuf_alloc(PBUF_IP, sizeof(struct rs_header) + (lladdr_opt_len << 3), PBUF_RAM); - if (p == NULL) { - ND6_STATS_INC(nd6.memerr); - return ERR_BUF; - } - - /* Set fields. */ - rs_hdr = (struct rs_header *)p->payload; - - rs_hdr->type = ICMP6_TYPE_RS; - rs_hdr->code = 0; - rs_hdr->chksum = 0; - rs_hdr->reserved = 0; - - if (src_addr != IP6_ADDR_ANY6) { - /* Include our hw address. */ - lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct rs_header)); - lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR; - lladdr_opt->length = (u8_t)lladdr_opt_len; - SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); - } - -#if CHECKSUM_GEN_ICMP6 - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { - rs_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, - &multicast_address); - } -#endif /* CHECKSUM_GEN_ICMP6 */ - - /* Send the packet out. */ - ND6_STATS_INC(nd6.xmit); - - err = ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, &multicast_address, - LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif); - pbuf_free(p); - - return err; -} -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ - -/** - * Search for a neighbor cache entry - * - * @param ip6addr the IPv6 address of the neighbor - * @return The neighbor cache entry index that matched, -1 if no - * entry is found - */ -static s8_t -nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr) -{ - s8_t i; - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if (ip6_addr_cmp(ip6addr, &(neighbor_cache[i].next_hop_address))) { - return i; - } - } - return -1; -} - -/** - * Create a new neighbor cache entry. - * - * If no unused entry is found, will try to recycle an old entry - * according to ad-hoc "age" heuristic. - * - * @return The neighbor cache entry index that was created, -1 if no - * entry could be created - */ -static s8_t -nd6_new_neighbor_cache_entry(void) -{ - s8_t i; - s8_t j; - u32_t time; - - - /* First, try to find an empty entry. */ - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if (neighbor_cache[i].state == ND6_NO_ENTRY) { - return i; - } - } - - /* We need to recycle an entry. in general, do not recycle if it is a router. */ - - /* Next, try to find a Stale entry. */ - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ((neighbor_cache[i].state == ND6_STALE) && - (!neighbor_cache[i].isrouter)) { - nd6_free_neighbor_cache_entry(i); - return i; - } - } - - /* Next, try to find a Probe entry. */ - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ((neighbor_cache[i].state == ND6_PROBE) && - (!neighbor_cache[i].isrouter)) { - nd6_free_neighbor_cache_entry(i); - return i; - } - } - - /* Next, try to find a Delayed entry. */ - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ((neighbor_cache[i].state == ND6_DELAY) && - (!neighbor_cache[i].isrouter)) { - nd6_free_neighbor_cache_entry(i); - return i; - } - } - - /* Next, try to find the oldest reachable entry. */ - time = 0xfffffffful; - j = -1; - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ((neighbor_cache[i].state == ND6_REACHABLE) && - (!neighbor_cache[i].isrouter)) { - if (neighbor_cache[i].counter.reachable_time < time) { - j = i; - time = neighbor_cache[i].counter.reachable_time; - } - } - } - if (j >= 0) { - nd6_free_neighbor_cache_entry(j); - return j; - } - - /* Next, find oldest incomplete entry without queued packets. */ - time = 0; - j = -1; - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ( - (neighbor_cache[i].q == NULL) && - (neighbor_cache[i].state == ND6_INCOMPLETE) && - (!neighbor_cache[i].isrouter)) { - if (neighbor_cache[i].counter.probes_sent >= time) { - j = i; - time = neighbor_cache[i].counter.probes_sent; - } - } - } - if (j >= 0) { - nd6_free_neighbor_cache_entry(j); - return j; - } - - /* Next, find oldest incomplete entry with queued packets. */ - time = 0; - j = -1; - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if ((neighbor_cache[i].state == ND6_INCOMPLETE) && - (!neighbor_cache[i].isrouter)) { - if (neighbor_cache[i].counter.probes_sent >= time) { - j = i; - time = neighbor_cache[i].counter.probes_sent; - } - } - } - if (j >= 0) { - nd6_free_neighbor_cache_entry(j); - return j; - } - - /* No more entries to try. */ - return -1; -} - -/** - * Will free any resources associated with a neighbor cache - * entry, and will mark it as unused. - * - * @param i the neighbor cache entry index to free - */ -static void -nd6_free_neighbor_cache_entry(s8_t i) -{ - if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) { - return; - } - if (neighbor_cache[i].isrouter) { - /* isrouter needs to be cleared before deleting a neighbor cache entry */ - return; - } - - /* Free any queued packets. */ - if (neighbor_cache[i].q != NULL) { - nd6_free_q(neighbor_cache[i].q); - neighbor_cache[i].q = NULL; - } - - neighbor_cache[i].state = ND6_NO_ENTRY; - neighbor_cache[i].isrouter = 0; - neighbor_cache[i].netif = NULL; - neighbor_cache[i].counter.reachable_time = 0; - ip6_addr_set_zero(&(neighbor_cache[i].next_hop_address)); -} - -/** - * Search for a destination cache entry - * - * @param ip6addr the IPv6 address of the destination - * @return The destination cache entry index that matched, -1 if no - * entry is found - */ -static s8_t -nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr) -{ - s8_t i; - for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { - if (ip6_addr_cmp(ip6addr, &(destination_cache[i].destination_addr))) { - return i; - } - } - return -1; -} - -/** - * Create a new destination cache entry. If no unused entry is found, - * will recycle oldest entry. - * - * @return The destination cache entry index that was created, -1 if no - * entry was created - */ -static s8_t -nd6_new_destination_cache_entry(void) -{ - s8_t i, j; - u32_t age; - - /* Find an empty entry. */ - for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { - if (ip6_addr_isany(&(destination_cache[i].destination_addr))) { - return i; - } - } - - /* Find oldest entry. */ - age = 0; - j = LWIP_ND6_NUM_DESTINATIONS - 1; - for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { - if (destination_cache[i].age > age) { - j = i; - } - } - - return j; -} - -/** - * Clear the destination cache. - * - * This operation may be necessary for consistency in the light of changing - * local addresses and/or use of the gateway hook. - */ -void -nd6_clear_destination_cache(void) -{ - int i; - - for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { - ip6_addr_set_any(&destination_cache[i].destination_addr); - } -} - -/** - * Determine whether an address matches an on-link prefix. - * - * @param ip6addr the IPv6 address to match - * @return 1 if the address is on-link, 0 otherwise - */ -static s8_t -nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif) -{ - s8_t i; - for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { - if ((prefix_list[i].netif == netif) && - (prefix_list[i].invalidation_timer > 0) && - ip6_addr_netcmp(ip6addr, &(prefix_list[i].prefix))) { - return 1; - } - } - /* Check to see if address prefix matches a (manually?) configured address. */ - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_netcmp(ip6addr, netif_ip6_addr(netif, i))) { - return 1; - } - } - return 0; -} - -/** - * Select a default router for a destination. - * - * @param ip6addr the destination address - * @param netif the netif for the outgoing packet, if known - * @return the default router entry index, or -1 if no suitable - * router is found - */ -static s8_t -nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif) -{ - s8_t i; - /* last_router is used for round-robin router selection (as recommended - * in RFC). This is more robust in case one router is not reachable, - * we are not stuck trying to resolve it. */ - static s8_t last_router; - (void)ip6addr; /* @todo match preferred routes!! (must implement ND6_OPTION_TYPE_ROUTE_INFO) */ - - /* @todo: implement default router preference */ - - /* Look for reachable routers. */ - for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { - if (++last_router >= LWIP_ND6_NUM_ROUTERS) { - last_router = 0; - } - if ((default_router_list[i].neighbor_entry != NULL) && - (netif != NULL ? netif == default_router_list[i].neighbor_entry->netif : 1) && - (default_router_list[i].invalidation_timer > 0) && - (default_router_list[i].neighbor_entry->state == ND6_REACHABLE)) { - return i; - } - } - - /* Look for router in other reachability states, but still valid according to timer. */ - for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { - if (++last_router >= LWIP_ND6_NUM_ROUTERS) { - last_router = 0; - } - if ((default_router_list[i].neighbor_entry != NULL) && - (netif != NULL ? netif == default_router_list[i].neighbor_entry->netif : 1) && - (default_router_list[i].invalidation_timer > 0)) { - return i; - } - } - - /* Look for any router for which we have any information at all. */ - for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { - if (++last_router >= LWIP_ND6_NUM_ROUTERS) { - last_router = 0; - } - if (default_router_list[i].neighbor_entry != NULL && - (netif != NULL ? netif == default_router_list[i].neighbor_entry->netif : 1)) { - return i; - } - } - - /* no suitable router found. */ - return -1; -} - -/** - * Find a router-announced route to the given destination. - * - * The caller is responsible for checking whether the returned netif, if any, - * is in a suitable state (up, link up) to be used for packet transmission. - * - * @param ip6addr the destination IPv6 address - * @return the netif to use for the destination, or NULL if none found - */ -struct netif * -nd6_find_route(const ip6_addr_t *ip6addr) -{ - s8_t i; - - i = nd6_select_router(ip6addr, NULL); - if (i >= 0) { - if (default_router_list[i].neighbor_entry != NULL) { - return default_router_list[i].neighbor_entry->netif; /* may be NULL */ - } - } - - return NULL; -} - -/** - * Find an entry for a default router. - * - * @param router_addr the IPv6 address of the router - * @param netif the netif on which the router is found, if known - * @return the index of the router entry, or -1 if not found - */ -static s8_t -nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif) -{ - s8_t i; - - /* Look for router. */ - for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { - if ((default_router_list[i].neighbor_entry != NULL) && - ((netif != NULL) ? netif == default_router_list[i].neighbor_entry->netif : 1) && - ip6_addr_cmp(router_addr, &(default_router_list[i].neighbor_entry->next_hop_address))) { - return i; - } - } - - /* router not found. */ - return -1; -} - -/** - * Create a new entry for a default router. - * - * @param router_addr the IPv6 address of the router - * @param netif the netif on which the router is connected, if known - * @return the index on the router table, or -1 if could not be created - */ -static s8_t -nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif) -{ - s8_t router_index; - s8_t free_router_index; - s8_t neighbor_index; - - /* Do we have a neighbor entry for this router? */ - neighbor_index = nd6_find_neighbor_cache_entry(router_addr); - if (neighbor_index < 0) { - /* Create a neighbor entry for this router. */ - neighbor_index = nd6_new_neighbor_cache_entry(); - if (neighbor_index < 0) { - /* Could not create neighbor entry for this router. */ - return -1; - } - ip6_addr_set(&(neighbor_cache[neighbor_index].next_hop_address), router_addr); - neighbor_cache[neighbor_index].netif = netif; - neighbor_cache[neighbor_index].q = NULL; - neighbor_cache[neighbor_index].state = ND6_INCOMPLETE; - neighbor_cache[neighbor_index].counter.probes_sent = 1; - nd6_send_neighbor_cache_probe(&neighbor_cache[neighbor_index], ND6_SEND_FLAG_MULTICAST_DEST); - } - - /* Mark neighbor as router. */ - neighbor_cache[neighbor_index].isrouter = 1; - - /* Look for empty entry. */ - free_router_index = LWIP_ND6_NUM_ROUTERS; - for (router_index = LWIP_ND6_NUM_ROUTERS - 1; router_index >= 0; router_index--) { - /* check if router already exists (this is a special case for 2 netifs on the same subnet - - e.g. wifi and cable) */ - if(default_router_list[router_index].neighbor_entry == &(neighbor_cache[neighbor_index])){ - return router_index; - } - if (default_router_list[router_index].neighbor_entry == NULL) { - /* remember lowest free index to create a new entry */ - free_router_index = router_index; - } - } - if (free_router_index < LWIP_ND6_NUM_ROUTERS) { - default_router_list[free_router_index].neighbor_entry = &(neighbor_cache[neighbor_index]); - return free_router_index; - } - - /* Could not create a router entry. */ - - /* Mark neighbor entry as not-router. Entry might be useful as neighbor still. */ - neighbor_cache[neighbor_index].isrouter = 0; - - /* router not found. */ - return -1; -} - -/** - * Find the cached entry for an on-link prefix. - * - * @param prefix the IPv6 prefix that is on-link - * @param netif the netif on which the prefix is on-link - * @return the index on the prefix table, or -1 if not found - */ -static s8_t -nd6_get_onlink_prefix(ip6_addr_t *prefix, struct netif *netif) -{ - s8_t i; - - /* Look for prefix in list. */ - for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) { - if ((ip6_addr_netcmp(&(prefix_list[i].prefix), prefix)) && - (prefix_list[i].netif == netif)) { - return i; - } - } - - /* Entry not available. */ - return -1; -} - -/** - * Creates a new entry for an on-link prefix. - * - * @param prefix the IPv6 prefix that is on-link - * @param netif the netif on which the prefix is on-link - * @return the index on the prefix table, or -1 if not created - */ -static s8_t -nd6_new_onlink_prefix(ip6_addr_t *prefix, struct netif *netif) -{ - s8_t i; - - /* Create new entry. */ - for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) { - if ((prefix_list[i].netif == NULL) || - (prefix_list[i].invalidation_timer == 0)) { - /* Found empty prefix entry. */ - prefix_list[i].netif = netif; - ip6_addr_set(&(prefix_list[i].prefix), prefix); -#if LWIP_IPV6_AUTOCONFIG - prefix_list[i].flags = 0; -#endif /* LWIP_IPV6_AUTOCONFIG */ - return i; - } - } - - /* Entry not available. */ - return -1; -} - -/** - * Determine the next hop for a destination. Will determine if the - * destination is on-link, else a suitable on-link router is selected. - * - * The last entry index is cached for fast entry search. - * - * @param ip6addr the destination address - * @param netif the netif on which the packet will be sent - * @return the neighbor cache entry for the next hop, ERR_RTE if no - * suitable next hop was found, ERR_MEM if no cache entry - * could be created - */ -static s8_t -nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif) -{ -#ifdef LWIP_HOOK_ND6_GET_GW - const ip6_addr_t *next_hop_addr; -#endif /* LWIP_HOOK_ND6_GET_GW */ - s8_t i; - -#if LWIP_NETIF_HWADDRHINT - if (netif->addr_hint != NULL) { - /* per-pcb cached entry was given */ - u8_t addr_hint = *(netif->addr_hint); - if (addr_hint < LWIP_ND6_NUM_DESTINATIONS) { - nd6_cached_destination_index = addr_hint; - } - } -#endif /* LWIP_NETIF_HWADDRHINT */ - - /* Look for ip6addr in destination cache. */ - if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) { - /* the cached entry index is the right one! */ - /* do nothing. */ - ND6_STATS_INC(nd6.cachehit); - } else { - /* Search destination cache. */ - i = nd6_find_destination_cache_entry(ip6addr); - if (i >= 0) { - /* found destination entry. make it our new cached index. */ - nd6_cached_destination_index = i; - } else { - /* Not found. Create a new destination entry. */ - i = nd6_new_destination_cache_entry(); - if (i >= 0) { - /* got new destination entry. make it our new cached index. */ - nd6_cached_destination_index = i; - } else { - /* Could not create a destination cache entry. */ - return ERR_MEM; - } - - /* Copy dest address to destination cache. */ - ip6_addr_set(&(destination_cache[nd6_cached_destination_index].destination_addr), ip6addr); - - /* Now find the next hop. is it a neighbor? */ - if (ip6_addr_islinklocal(ip6addr) || - nd6_is_prefix_in_netif(ip6addr, netif)) { - /* Destination in local link. */ - destination_cache[nd6_cached_destination_index].pmtu = netif->mtu; - ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, destination_cache[nd6_cached_destination_index].destination_addr); -#ifdef LWIP_HOOK_ND6_GET_GW - } else if ((next_hop_addr = LWIP_HOOK_ND6_GET_GW(netif, ip6addr)) != NULL) { - /* Next hop for destination provided by hook function. */ - destination_cache[nd6_cached_destination_index].pmtu = netif->mtu; - ip6_addr_set(&destination_cache[nd6_cached_destination_index].next_hop_addr, next_hop_addr); -#endif /* LWIP_HOOK_ND6_GET_GW */ - } else { - /* We need to select a router. */ - i = nd6_select_router(ip6addr, netif); - if (i < 0) { - /* No router found. */ - ip6_addr_set_any(&(destination_cache[nd6_cached_destination_index].destination_addr)); - return ERR_RTE; - } - destination_cache[nd6_cached_destination_index].pmtu = netif->mtu; /* Start with netif mtu, correct through ICMPv6 if necessary */ - ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, default_router_list[i].neighbor_entry->next_hop_address); - } - } - } - -#if LWIP_NETIF_HWADDRHINT - if (netif->addr_hint != NULL) { - /* per-pcb cached entry was given */ - *(netif->addr_hint) = nd6_cached_destination_index; - } -#endif /* LWIP_NETIF_HWADDRHINT */ - - /* Look in neighbor cache for the next-hop address. */ - if (ip6_addr_cmp(&(destination_cache[nd6_cached_destination_index].next_hop_addr), - &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) { - /* Cache hit. */ - /* Do nothing. */ - ND6_STATS_INC(nd6.cachehit); - } else { - i = nd6_find_neighbor_cache_entry(&(destination_cache[nd6_cached_destination_index].next_hop_addr)); - if (i >= 0) { - /* Found a matching record, make it new cached entry. */ - nd6_cached_neighbor_index = i; - } else { - /* Neighbor not in cache. Make a new entry. */ - i = nd6_new_neighbor_cache_entry(); - if (i >= 0) { - /* got new neighbor entry. make it our new cached index. */ - nd6_cached_neighbor_index = i; - } else { - /* Could not create a neighbor cache entry. */ - return ERR_MEM; - } - - /* Initialize fields. */ - ip6_addr_copy(neighbor_cache[i].next_hop_address, - destination_cache[nd6_cached_destination_index].next_hop_addr); - neighbor_cache[i].isrouter = 0; - neighbor_cache[i].netif = netif; - neighbor_cache[i].state = ND6_INCOMPLETE; - neighbor_cache[i].counter.probes_sent = 1; - nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST); - } - } - - /* Reset this destination's age. */ - destination_cache[nd6_cached_destination_index].age = 0; - - return nd6_cached_neighbor_index; -} - -/** - * Queue a packet for a neighbor. - * - * @param neighbor_index the index in the neighbor cache table - * @param q packet to be queued - * @return ERR_OK if succeeded, ERR_MEM if out of memory - */ -static err_t -nd6_queue_packet(s8_t neighbor_index, struct pbuf *q) -{ - err_t result = ERR_MEM; - struct pbuf *p; - int copy_needed = 0; -#if LWIP_ND6_QUEUEING - struct nd6_q_entry *new_entry, *r; -#endif /* LWIP_ND6_QUEUEING */ - - if ((neighbor_index < 0) || (neighbor_index >= LWIP_ND6_NUM_NEIGHBORS)) { - return ERR_ARG; - } - - /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but - * to copy the whole queue into a new PBUF_RAM (see bug #11400) - * PBUF_ROMs can be left as they are, since ROM must not get changed. */ - p = q; - while (p) { - if (p->type != PBUF_ROM) { - copy_needed = 1; - break; - } - p = p->next; - } - if (copy_needed) { - /* copy the whole packet into new pbufs */ - p = pbuf_alloc(PBUF_LINK, q->tot_len, PBUF_RAM); - while ((p == NULL) && (neighbor_cache[neighbor_index].q != NULL)) { - /* Free oldest packet (as per RFC recommendation) */ -#if LWIP_ND6_QUEUEING - r = neighbor_cache[neighbor_index].q; - neighbor_cache[neighbor_index].q = r->next; - r->next = NULL; - nd6_free_q(r); -#else /* LWIP_ND6_QUEUEING */ - pbuf_free(neighbor_cache[neighbor_index].q); - neighbor_cache[neighbor_index].q = NULL; -#endif /* LWIP_ND6_QUEUEING */ - p = pbuf_alloc(PBUF_LINK, q->tot_len, PBUF_RAM); - } - if (p != NULL) { - if (pbuf_copy(p, q) != ERR_OK) { - pbuf_free(p); - p = NULL; - } - } - } else { - /* referencing the old pbuf is enough */ - p = q; - pbuf_ref(p); - } - /* packet was copied/ref'd? */ - if (p != NULL) { - /* queue packet ... */ -#if LWIP_ND6_QUEUEING - /* allocate a new nd6 queue entry */ - new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE); - if ((new_entry == NULL) && (neighbor_cache[neighbor_index].q != NULL)) { - /* Free oldest packet (as per RFC recommendation) */ - r = neighbor_cache[neighbor_index].q; - neighbor_cache[neighbor_index].q = r->next; - r->next = NULL; - nd6_free_q(r); - new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE); - } - if (new_entry != NULL) { - new_entry->next = NULL; - new_entry->p = p; - if (neighbor_cache[neighbor_index].q != NULL) { - /* queue was already existent, append the new entry to the end */ - r = neighbor_cache[neighbor_index].q; - while (r->next != NULL) { - r = r->next; - } - r->next = new_entry; - } else { - /* queue did not exist, first item in queue */ - neighbor_cache[neighbor_index].q = new_entry; - } - LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index)); - result = ERR_OK; - } else { - /* the pool MEMP_ND6_QUEUE is empty */ - pbuf_free(p); - LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)p)); - /* { result == ERR_MEM } through initialization */ - } -#else /* LWIP_ND6_QUEUEING */ - /* Queue a single packet. If an older packet is already queued, free it as per RFC. */ - if (neighbor_cache[neighbor_index].q != NULL) { - pbuf_free(neighbor_cache[neighbor_index].q); - } - neighbor_cache[neighbor_index].q = p; - LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index)); - result = ERR_OK; -#endif /* LWIP_ND6_QUEUEING */ - } else { - LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)q)); - /* { result == ERR_MEM } through initialization */ - } - - return result; -} - -#if LWIP_ND6_QUEUEING -/** - * Free a complete queue of nd6 q entries - * - * @param q a queue of nd6_q_entry to free - */ -static void -nd6_free_q(struct nd6_q_entry *q) -{ - struct nd6_q_entry *r; - LWIP_ASSERT("q != NULL", q != NULL); - LWIP_ASSERT("q->p != NULL", q->p != NULL); - while (q) { - r = q; - q = q->next; - LWIP_ASSERT("r->p != NULL", (r->p != NULL)); - pbuf_free(r->p); - memp_free(MEMP_ND6_QUEUE, r); - } -} -#endif /* LWIP_ND6_QUEUEING */ - -/** - * Send queued packets for a neighbor - * - * @param i the neighbor to send packets to - */ -static void -nd6_send_q(s8_t i) -{ - struct ip6_hdr *ip6hdr; - ip6_addr_t dest; -#if LWIP_ND6_QUEUEING - struct nd6_q_entry *q; -#endif /* LWIP_ND6_QUEUEING */ - - if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) { - return; - } - -#if LWIP_ND6_QUEUEING - while (neighbor_cache[i].q != NULL) { - /* remember first in queue */ - q = neighbor_cache[i].q; - /* pop first item off the queue */ - neighbor_cache[i].q = q->next; - /* Get ipv6 header. */ - ip6hdr = (struct ip6_hdr *)(q->p->payload); - /* Create an aligned copy. */ - ip6_addr_set(&dest, &(ip6hdr->dest)); - /* send the queued IPv6 packet */ - (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, q->p, &dest); - /* free the queued IP packet */ - pbuf_free(q->p); - /* now queue entry can be freed */ - memp_free(MEMP_ND6_QUEUE, q); - } -#else /* LWIP_ND6_QUEUEING */ - if (neighbor_cache[i].q != NULL) { - /* Get ipv6 header. */ - ip6hdr = (struct ip6_hdr *)(neighbor_cache[i].q->payload); - /* Create an aligned copy. */ - ip6_addr_set(&dest, &(ip6hdr->dest)); - /* send the queued IPv6 packet */ - (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, neighbor_cache[i].q, &dest); - /* free the queued IP packet */ - pbuf_free(neighbor_cache[i].q); - neighbor_cache[i].q = NULL; - } -#endif /* LWIP_ND6_QUEUEING */ -} - -/** - * A packet is to be transmitted to a specific IPv6 destination on a specific - * interface. Check if we can find the hardware address of the next hop to use - * for the packet. If so, give the hardware address to the caller, which should - * use it to send the packet right away. Otherwise, enqueue the packet for - * later transmission while looking up the hardware address, if possible. - * - * As such, this function returns one of three different possible results: - * - * - ERR_OK with a non-NULL 'hwaddrp': the caller should send the packet now. - * - ERR_OK with a NULL 'hwaddrp': the packet has been enqueued for later. - * - not ERR_OK: something went wrong; forward the error upward in the stack. - * - * @param netif The lwIP network interface on which the IP packet will be sent. - * @param q The pbuf(s) containing the IP packet to be sent. - * @param ip6addr The destination IPv6 address of the packet. - * @param hwaddrp On success, filled with a pointer to a HW address or NULL (meaning - * the packet has been queued). - * @return - * - ERR_OK on success, ERR_RTE if no route was found for the packet, - * or ERR_MEM if low memory conditions prohibit sending the packet at all. - */ -err_t -nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp) -{ - s8_t i; - - /* Get next hop record. */ - i = nd6_get_next_hop_entry(ip6addr, netif); - if (i < 0) { - /* failed to get a next hop neighbor record. */ - return i; - } - - /* Now that we have a destination record, send or queue the packet. */ - if (neighbor_cache[i].state == ND6_STALE) { - /* Switch to delay state. */ - neighbor_cache[i].state = ND6_DELAY; - neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; - } - /* @todo should we send or queue if PROBE? send for now, to let unicast NS pass. */ - if ((neighbor_cache[i].state == ND6_REACHABLE) || - (neighbor_cache[i].state == ND6_DELAY) || - (neighbor_cache[i].state == ND6_PROBE)) { - - /* Tell the caller to send out the packet now. */ - *hwaddrp = neighbor_cache[i].lladdr; - return ERR_OK; - } - - /* We should queue packet on this interface. */ - *hwaddrp = NULL; - return nd6_queue_packet(i, q); -} - - -/** - * Get the Path MTU for a destination. - * - * @param ip6addr the destination address - * @param netif the netif on which the packet will be sent - * @return the Path MTU, if known, or the netif default MTU - */ -u16_t -nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif) -{ - s8_t i; - - i = nd6_find_destination_cache_entry(ip6addr); - if (i >= 0) { - if (destination_cache[i].pmtu > 0) { - return destination_cache[i].pmtu; - } - } - - if (netif != NULL) { - return netif->mtu; - } - - return 1280; /* Minimum MTU */ -} - - -#if LWIP_ND6_TCP_REACHABILITY_HINTS -/** - * Provide the Neighbor discovery process with a hint that a - * destination is reachable. Called by tcp_receive when ACKs are - * received or sent (as per RFC). This is useful to avoid sending - * NS messages every 30 seconds. - * - * @param ip6addr the destination address which is know to be reachable - * by an upper layer protocol (TCP) - */ -void -nd6_reachability_hint(const ip6_addr_t *ip6addr) -{ - s8_t i; - - /* Find destination in cache. */ - if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) { - i = nd6_cached_destination_index; - ND6_STATS_INC(nd6.cachehit); - } else { - i = nd6_find_destination_cache_entry(ip6addr); - } - if (i < 0) { - return; - } - - /* Find next hop neighbor in cache. */ - if (ip6_addr_cmp(&(destination_cache[i].next_hop_addr), &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) { - i = nd6_cached_neighbor_index; - ND6_STATS_INC(nd6.cachehit); - } else { - i = nd6_find_neighbor_cache_entry(&(destination_cache[i].next_hop_addr)); - } - if (i < 0) { - return; - } - - /* For safety: don't set as reachable if we don't have a LL address yet. Misuse protection. */ - if (neighbor_cache[i].state == ND6_INCOMPLETE || neighbor_cache[i].state == ND6_NO_ENTRY) { - return; - } - - /* Set reachability state. */ - neighbor_cache[i].state = ND6_REACHABLE; - neighbor_cache[i].counter.reachable_time = reachable_time; -} -#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ - -/** - * Remove all prefix, neighbor_cache and router entries of the specified netif. - * - * @param netif points to a network interface - */ -void -nd6_cleanup_netif(struct netif *netif) -{ - u8_t i; - s8_t router_index; - for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { - if (prefix_list[i].netif == netif) { - prefix_list[i].netif = NULL; - prefix_list[i].flags = 0; - } - } - for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { - if (neighbor_cache[i].netif == netif) { - for (router_index = 0; router_index < LWIP_ND6_NUM_ROUTERS; router_index++) { - if (default_router_list[router_index].neighbor_entry == &neighbor_cache[i]) { - default_router_list[router_index].neighbor_entry = NULL; - default_router_list[router_index].flags = 0; - } - } - neighbor_cache[i].isrouter = 0; - nd6_free_neighbor_cache_entry(i); - } - } -} - -#if LWIP_IPV6_MLD -/** - * The state of a local IPv6 address entry is about to change. If needed, join - * or leave the solicited-node multicast group for the address. - * - * @param netif The netif that owns the address. - * @param addr_idx The index of the address. - * @param new_state The new (IP6_ADDR_) state for the address. - */ -void -nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state) -{ - u8_t old_state, old_member, new_member; - - old_state = netif_ip6_addr_state(netif, addr_idx); - - /* Determine whether we were, and should be, a member of the solicited-node - * multicast group for this address. For tentative addresses, the group is - * not joined until the address enters the TENTATIVE_1 (or VALID) state. */ - old_member = (old_state != IP6_ADDR_INVALID && old_state != IP6_ADDR_TENTATIVE); - new_member = (new_state != IP6_ADDR_INVALID && new_state != IP6_ADDR_TENTATIVE); - - if (old_member != new_member) { - ip6_addr_set_solicitednode(&multicast_address, netif_ip6_addr(netif, addr_idx)->addr[3]); - - if (new_member) { - mld6_joingroup_netif(netif, &multicast_address); - } else { - mld6_leavegroup_netif(netif, &multicast_address); - } - } -} -#endif /* LWIP_IPV6_MLD */ - -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/mem.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/mem.c deleted file mode 100644 index 7229600915ba427504042dd5ad10da5e3667a2dd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/mem.c +++ /dev/null @@ -1,777 +0,0 @@ -/** - * @file - * Dynamic memory manager - * - * This is a lightweight replacement for the standard C library malloc(). - * - * If you want to use the standard C library malloc() instead, define - * MEM_LIBC_MALLOC to 1 in your lwipopts.h - * - * To let mem_malloc() use pools (prevents fragmentation and is much faster than - * a heap but might waste some memory), define MEM_USE_POOLS to 1, define - * MEMP_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list - * of pools like this (more pools can be added between _START and _END): - * - * Define three pools with sizes 256, 512, and 1512 bytes - * LWIP_MALLOC_MEMPOOL_START - * LWIP_MALLOC_MEMPOOL(20, 256) - * LWIP_MALLOC_MEMPOOL(10, 512) - * LWIP_MALLOC_MEMPOOL(5, 1512) - * LWIP_MALLOC_MEMPOOL_END - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Simon Goldschmidt - * - */ - -#include "lwip/opt.h" -#include "lwip/mem.h" -#include "lwip/def.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/err.h" - -#include - -#if MEM_LIBC_MALLOC -#include /* for malloc()/free() */ -#endif - -#if MEM_LIBC_MALLOC || MEM_USE_POOLS - -/** mem_init is not used when using pools instead of a heap or using - * C library malloc(). - */ -void -mem_init(void) -{ -} - -/** mem_trim is not used when using pools instead of a heap or using - * C library malloc(): we can't free part of a pool element and the stack - * support mem_trim() to return a different pointer - */ -void* -mem_trim(void *mem, mem_size_t size) -{ - LWIP_UNUSED_ARG(size); - return mem; -} -#endif /* MEM_LIBC_MALLOC || MEM_USE_POOLS */ - -#if MEM_LIBC_MALLOC -/* lwIP heap implemented using C library malloc() */ - -/* in case C library malloc() needs extra protection, - * allow these defines to be overridden. - */ -#ifndef mem_clib_free -#define mem_clib_free os_free -#endif -#ifndef mem_clib_malloc -#define mem_clib_malloc os_malloc -#endif -#ifndef mem_clib_calloc -#define mem_clib_calloc os_calloc -#endif - -#if LWIP_STATS && MEM_STATS -#define MEM_LIBC_STATSHELPER_SIZE LWIP_MEM_ALIGN_SIZE(sizeof(mem_size_t)) -#else -#define MEM_LIBC_STATSHELPER_SIZE 0 -#endif - -/** - * Allocate a block of memory with a minimum of 'size' bytes. - * - * @param size is the minimum size of the requested block in bytes. - * @return pointer to allocated memory or NULL if no free memory was found. - * - * Note that the returned value must always be aligned (as defined by MEM_ALIGNMENT). - */ -void * -mem_malloc(mem_size_t size) -{ - void* ret = mem_clib_malloc(size + MEM_LIBC_STATSHELPER_SIZE); - if (ret == NULL) { - MEM_STATS_INC(err); - } else { - LWIP_ASSERT("malloc() must return aligned memory", LWIP_MEM_ALIGN(ret) == ret); -#if LWIP_STATS && MEM_STATS - *(mem_size_t*)ret = size; - ret = (u8_t*)ret + MEM_LIBC_STATSHELPER_SIZE; - MEM_STATS_INC_USED(used, size); -#endif - } - return ret; -} - -/** Put memory back on the heap - * - * @param rmem is the pointer as returned by a previous call to mem_malloc() - */ -void -mem_free(void *rmem) -{ - LWIP_ASSERT("rmem != NULL", (rmem != NULL)); - LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); -#if LWIP_STATS && MEM_STATS - rmem = (u8_t*)rmem - MEM_LIBC_STATSHELPER_SIZE; - MEM_STATS_DEC_USED(used, *(mem_size_t*)rmem); -#endif - mem_clib_free(rmem); -} - -#elif MEM_USE_POOLS - -/* lwIP heap implemented with different sized pools */ - -/** - * Allocate memory: determine the smallest pool that is big enough - * to contain an element of 'size' and get an element from that pool. - * - * @param size the size in bytes of the memory needed - * @return a pointer to the allocated memory or NULL if the pool is empty - */ -void * -mem_malloc(mem_size_t size) -{ - void *ret; - struct memp_malloc_helper *element = NULL; - memp_t poolnr; - mem_size_t required_size = size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper)); - - for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr = (memp_t)(poolnr + 1)) { - /* is this pool big enough to hold an element of the required size - plus a struct memp_malloc_helper that saves the pool this element came from? */ - if (required_size <= memp_pools[poolnr]->size) { - element = (struct memp_malloc_helper*)memp_malloc(poolnr); - if (element == NULL) { - /* No need to DEBUGF or ASSERT: This error is already taken care of in memp.c */ -#if MEM_USE_POOLS_TRY_BIGGER_POOL - /** Try a bigger pool if this one is empty! */ - if (poolnr < MEMP_POOL_LAST) { - continue; - } -#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ - MEM_STATS_INC(err); - return NULL; - } - break; - } - } - if (poolnr > MEMP_POOL_LAST) { - LWIP_ASSERT("mem_malloc(): no pool is that big!", 0); - MEM_STATS_INC(err); - return NULL; - } - - /* save the pool number this element came from */ - element->poolnr = poolnr; - /* and return a pointer to the memory directly after the struct memp_malloc_helper */ - ret = (u8_t*)element + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper)); - -#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) - /* truncating to u16_t is safe because struct memp_desc::size is u16_t */ - element->size = (u16_t)size; - MEM_STATS_INC_USED(used, element->size); -#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */ -#if MEMP_OVERFLOW_CHECK - /* initialize unused memory (diff between requested size and selected pool's size) */ - memset((u8_t*)ret + size, 0xcd, memp_pools[poolnr]->size - size); -#endif /* MEMP_OVERFLOW_CHECK */ - return ret; -} - -/** - * Free memory previously allocated by mem_malloc. Loads the pool number - * and calls memp_free with that pool number to put the element back into - * its pool - * - * @param rmem the memory element to free - */ -void -mem_free(void *rmem) -{ - struct memp_malloc_helper *hmem; - - LWIP_ASSERT("rmem != NULL", (rmem != NULL)); - LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); - - /* get the original struct memp_malloc_helper */ - /* cast through void* to get rid of alignment warnings */ - hmem = (struct memp_malloc_helper*)(void*)((u8_t*)rmem - LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))); - - LWIP_ASSERT("hmem != NULL", (hmem != NULL)); - LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem))); - LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX)); - - MEM_STATS_DEC_USED(used, hmem->size); -#if MEMP_OVERFLOW_CHECK - { - u16_t i; - LWIP_ASSERT("MEM_USE_POOLS: invalid chunk size", - hmem->size <= memp_pools[hmem->poolnr]->size); - /* check that unused memory remained untouched (diff between requested size and selected pool's size) */ - for (i = hmem->size; i < memp_pools[hmem->poolnr]->size; i++) { - u8_t data = *((u8_t*)rmem + i); - LWIP_ASSERT("MEM_USE_POOLS: mem overflow detected", data == 0xcd); - } - } -#endif /* MEMP_OVERFLOW_CHECK */ - - /* and put it in the pool we saved earlier */ - memp_free(hmem->poolnr, hmem); -} - -#else /* MEM_USE_POOLS */ -/* lwIP replacement for your libc malloc() */ - -/** - * The heap is made up as a list of structs of this type. - * This does not have to be aligned since for getting its size, - * we only use the macro SIZEOF_STRUCT_MEM, which automatically aligns. - */ -struct mem { - /** index (-> ram[next]) of the next struct */ - mem_size_t next; - /** index (-> ram[prev]) of the previous struct */ - mem_size_t prev; - /** 1: this area is used; 0: this area is unused */ - u8_t used; -}; - -/** All allocated blocks will be MIN_SIZE bytes big, at least! - * MIN_SIZE can be overridden to suit your needs. Smaller values save space, - * larger values could prevent too small blocks to fragment the RAM too much. */ -#ifndef MIN_SIZE -#define MIN_SIZE 12 -#endif /* MIN_SIZE */ -/* some alignment macros: we define them here for better source code layout */ -#define MIN_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MIN_SIZE) -#define SIZEOF_STRUCT_MEM LWIP_MEM_ALIGN_SIZE(sizeof(struct mem)) -#define MEM_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SIZE) - -/** If you want to relocate the heap to external memory, simply define - * LWIP_RAM_HEAP_POINTER as a void-pointer to that location. - * If so, make sure the memory at that location is big enough (see below on - * how that space is calculated). */ -#ifndef LWIP_RAM_HEAP_POINTER -/** the heap. we need one struct mem at the end and some room for alignment */ -LWIP_DECLARE_MEMORY_ALIGNED(ram_heap, MEM_SIZE_ALIGNED + (2U*SIZEOF_STRUCT_MEM)); -#define LWIP_RAM_HEAP_POINTER ram_heap -#endif /* LWIP_RAM_HEAP_POINTER */ - -/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */ -static u8_t *ram; -/** the last entry, always unused! */ -static struct mem *ram_end; -/** pointer to the lowest free block, this is used for faster search */ -static struct mem *lfree; - -/** concurrent access protection */ -#if !NO_SYS -static sys_mutex_t mem_mutex; -#endif - -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - -static volatile u8_t mem_free_count; - -/* Allow mem_free from other (e.g. interrupt) context */ -#define LWIP_MEM_FREE_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_free) -#define LWIP_MEM_FREE_PROTECT() SYS_ARCH_PROTECT(lev_free) -#define LWIP_MEM_FREE_UNPROTECT() SYS_ARCH_UNPROTECT(lev_free) -#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc) -#define LWIP_MEM_ALLOC_PROTECT() SYS_ARCH_PROTECT(lev_alloc) -#define LWIP_MEM_ALLOC_UNPROTECT() SYS_ARCH_UNPROTECT(lev_alloc) - -#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - -/* Protect the heap only by using a semaphore */ -#define LWIP_MEM_FREE_DECL_PROTECT() -#define LWIP_MEM_FREE_PROTECT() sys_mutex_lock(&mem_mutex) -#define LWIP_MEM_FREE_UNPROTECT() sys_mutex_unlock(&mem_mutex) -/* mem_malloc is protected using semaphore AND LWIP_MEM_ALLOC_PROTECT */ -#define LWIP_MEM_ALLOC_DECL_PROTECT() -#define LWIP_MEM_ALLOC_PROTECT() -#define LWIP_MEM_ALLOC_UNPROTECT() - -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - -/** - * "Plug holes" by combining adjacent empty struct mems. - * After this function is through, there should not exist - * one empty struct mem pointing to another empty struct mem. - * - * @param mem this points to a struct mem which just has been freed - * @internal this function is only called by mem_free() and mem_trim() - * - * This assumes access to the heap is protected by the calling function - * already. - */ -static void -plug_holes(struct mem *mem) -{ - struct mem *nmem; - struct mem *pmem; - - LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); - LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); - LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); - - /* plug hole forward */ - LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); - - nmem = (struct mem *)(void *)&ram[mem->next]; - if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { - /* if mem->next is unused and not end of ram, combine mem and mem->next */ - if (lfree == nmem) { - lfree = mem; - } - mem->next = nmem->next; - ((struct mem *)(void *)&ram[nmem->next])->prev = (mem_size_t)((u8_t *)mem - ram); - } - - /* plug hole backward */ - pmem = (struct mem *)(void *)&ram[mem->prev]; - if (pmem != mem && pmem->used == 0) { - /* if mem->prev is unused, combine mem and mem->prev */ - if (lfree == mem) { - lfree = pmem; - } - pmem->next = mem->next; - ((struct mem *)(void *)&ram[mem->next])->prev = (mem_size_t)((u8_t *)pmem - ram); - } -} - -/** - * Zero the heap and initialize start, end and lowest-free - */ -void -mem_init(void) -{ - struct mem *mem; - - LWIP_ASSERT("Sanity check alignment", - (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0); - - /* align the heap */ - ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); - /* initialize the start of the heap */ - mem = (struct mem *)(void *)ram; - mem->next = MEM_SIZE_ALIGNED; - mem->prev = 0; - mem->used = 0; - /* initialize the end of the heap */ - ram_end = (struct mem *)(void *)&ram[MEM_SIZE_ALIGNED]; - ram_end->used = 1; - ram_end->next = MEM_SIZE_ALIGNED; - ram_end->prev = MEM_SIZE_ALIGNED; - - /* initialize the lowest-free pointer to the start of the heap */ - lfree = (struct mem *)(void *)ram; - - MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); - - if (sys_mutex_new(&mem_mutex) != ERR_OK) { - LWIP_ASSERT("failed to create mem_mutex", 0); - } -} - -/** - * Put a struct mem back on the heap - * - * @param rmem is the data portion of a struct mem as returned by a previous - * call to mem_malloc() - */ -void -mem_free(void *rmem) -{ - struct mem *mem; - LWIP_MEM_FREE_DECL_PROTECT(); - - if (rmem == NULL) { - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); - return; - } - LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0); - - LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - SYS_ARCH_DECL_PROTECT(lev); - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); - /* protect mem stats from concurrent access */ - SYS_ARCH_PROTECT(lev); - MEM_STATS_INC(illegal); - SYS_ARCH_UNPROTECT(lev); - return; - } - /* protect the heap from concurrent access */ - LWIP_MEM_FREE_PROTECT(); - /* Get the corresponding struct mem ... */ - /* cast through void* to get rid of alignment warnings */ - mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - /* ... which has to be in a used state ... */ - LWIP_ASSERT("mem_free: mem->used", mem->used); - /* ... and is now unused. */ - mem->used = 0; - - if (mem < lfree) { - /* the newly freed struct is now the lowest */ - lfree = mem; - } - - MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); - - /* finally, see if prev or next are free also */ - plug_holes(mem); -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 1; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_FREE_UNPROTECT(); -} - -/** - * Shrink memory returned by mem_malloc(). - * - * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked - * @param newsize required size after shrinking (needs to be smaller than or - * equal to the previous size) - * @return for compatibility reasons: is always == rmem, at the moment - * or NULL if newsize is > old size, in which case rmem is NOT touched - * or freed! - */ -void * -mem_trim(void *rmem, mem_size_t newsize) -{ - mem_size_t size; - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ - LWIP_MEM_FREE_DECL_PROTECT(); - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - newsize = LWIP_MEM_ALIGN_SIZE(newsize); - - if (newsize < MIN_SIZE_ALIGNED) { - /* every data block must be at least MIN_SIZE_ALIGNED long */ - newsize = MIN_SIZE_ALIGNED; - } - - if (newsize > MEM_SIZE_ALIGNED) { - return NULL; - } - - LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - SYS_ARCH_DECL_PROTECT(lev); - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); - /* protect mem stats from concurrent access */ - SYS_ARCH_PROTECT(lev); - MEM_STATS_INC(illegal); - SYS_ARCH_UNPROTECT(lev); - return rmem; - } - /* Get the corresponding struct mem ... */ - /* cast through void* to get rid of alignment warnings */ - mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - /* ... and its offset pointer */ - ptr = (mem_size_t)((u8_t *)mem - ram); - - size = mem->next - ptr - SIZEOF_STRUCT_MEM; - LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); - if (newsize > size) { - /* not supported */ - return NULL; - } - if (newsize == size) { - /* No change in size, simply return */ - return rmem; - } - - /* protect the heap from concurrent access */ - LWIP_MEM_FREE_PROTECT(); - - mem2 = (struct mem *)(void *)&ram[mem->next]; - if (mem2->used == 0) { - /* The next struct is unused, we can simply move it at little */ - mem_size_t next; - /* remember the old next pointer */ - next = mem2->next; - /* create new struct mem which is moved directly after the shrinked mem */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - if (lfree == mem2) { - lfree = (struct mem *)(void *)&ram[ptr2]; - } - mem2 = (struct mem *)(void *)&ram[ptr2]; - mem2->used = 0; - /* restore the next pointer */ - mem2->next = next; - /* link it back to mem */ - mem2->prev = ptr; - /* link mem to it */ - mem->next = ptr2; - /* last thing to restore linked list: as we have moved mem2, - * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not - * the end of the heap */ - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; - } - MEM_STATS_DEC_USED(used, (size - newsize)); - /* no need to plug holes, we've already done that */ - } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { - /* Next struct is used but there's room for another struct mem with - * at least MIN_SIZE_ALIGNED of data. - * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem - * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). - * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty - * region that couldn't hold data, but when mem->next gets freed, - * the 2 regions would be combined, resulting in more free memory */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - mem2 = (struct mem *)(void *)&ram[ptr2]; - if (mem2 < lfree) { - lfree = mem2; - } - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - mem->next = ptr2; - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; - } - MEM_STATS_DEC_USED(used, (size - newsize)); - /* the original mem->next is used, so no need to plug holes! */ - } - /* else { - next struct mem is used but size between mem and mem2 is not big enough - to create another struct mem - -> don't do anyhting. - -> the remaining space stays unused since it is too small - } */ -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 1; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_FREE_UNPROTECT(); - return rmem; -} - -/** - * Allocate a block of memory with a minimum of 'size' bytes. - * - * @param size is the minimum size of the requested block in bytes. - * @return pointer to allocated memory or NULL if no free memory was found. - * - * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). - */ -void * -mem_malloc(mem_size_t size) -{ - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - u8_t local_mem_free_count = 0; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_ALLOC_DECL_PROTECT(); - - if (size == 0) { - return NULL; - } - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - size = LWIP_MEM_ALIGN_SIZE(size); - - if (size < MIN_SIZE_ALIGNED) { - /* every data block must be at least MIN_SIZE_ALIGNED long */ - size = MIN_SIZE_ALIGNED; - } - - if (size > MEM_SIZE_ALIGNED) { - return NULL; - } - - /* protect the heap from concurrent access */ - sys_mutex_lock(&mem_mutex); - LWIP_MEM_ALLOC_PROTECT(); -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - /* run as long as a mem_free disturbed mem_malloc or mem_trim */ - do { - local_mem_free_count = 0; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - /* Scan through the heap searching for a free block that is big enough, - * beginning with the lowest free block. - */ - for (ptr = (mem_size_t)((u8_t *)lfree - ram); ptr < MEM_SIZE_ALIGNED - size; - ptr = ((struct mem *)(void *)&ram[ptr])->next) { - mem = (struct mem *)(void *)&ram[ptr]; -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 0; - LWIP_MEM_ALLOC_UNPROTECT(); - /* allow mem_free or mem_trim to run */ - LWIP_MEM_ALLOC_PROTECT(); - if (mem_free_count != 0) { - /* If mem_free or mem_trim have run, we have to restart since they - could have altered our current struct mem. */ - local_mem_free_count = 1; - break; - } -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - if ((!mem->used) && - (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { - /* mem is not used and at least perfect fit is possible: - * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ - - if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { - /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing - * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem') - * -> split large block, create empty remainder, - * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if - * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size, - * struct mem would fit in but no data between mem2 and mem2->next - * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty - * region that couldn't hold data, but when mem->next gets freed, - * the 2 regions would be combined, resulting in more free memory - */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + size; - /* create mem2 struct */ - mem2 = (struct mem *)(void *)&ram[ptr2]; - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - /* and insert it between mem and mem->next */ - mem->next = ptr2; - mem->used = 1; - - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; - } - MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM)); - } else { - /* (a mem2 struct does no fit into the user data space of mem and mem->next will always - * be used at this point: if not we have 2 unused structs in a row, plug_holes should have - * take care of this). - * -> near fit or exact fit: do not split, no mem2 creation - * also can't move mem->next directly behind mem, since mem->next - * will always be used at this point! - */ - mem->used = 1; - MEM_STATS_INC_USED(used, mem->next - (mem_size_t)((u8_t *)mem - ram)); - } -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT -mem_malloc_adjust_lfree: -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - if (mem == lfree) { - struct mem *cur = lfree; - /* Find next free block after mem and update lowest free pointer */ - while (cur->used && cur != ram_end) { -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 0; - LWIP_MEM_ALLOC_UNPROTECT(); - /* prevent high interrupt latency... */ - LWIP_MEM_ALLOC_PROTECT(); - if (mem_free_count != 0) { - /* If mem_free or mem_trim have run, we have to restart since they - could have altered our current struct mem or lfree. */ - goto mem_malloc_adjust_lfree; - } -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - cur = (struct mem *)(void *)&ram[cur->next]; - } - lfree = cur; - LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); - } - LWIP_MEM_ALLOC_UNPROTECT(); - sys_mutex_unlock(&mem_mutex); - LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", - (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); - LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", - ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); - LWIP_ASSERT("mem_malloc: sanity check alignment", - (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0); - - return (u8_t *)mem + SIZEOF_STRUCT_MEM; - } - } -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - /* if we got interrupted by a mem_free, try again */ - } while (local_mem_free_count != 0); -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); - MEM_STATS_INC(err); - LWIP_MEM_ALLOC_UNPROTECT(); - sys_mutex_unlock(&mem_mutex); - return NULL; -} - -#endif /* MEM_USE_POOLS */ - -#if MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) -void * -mem_calloc(mem_size_t count, mem_size_t size) -{ - return mem_clib_calloc(count, size); -} - -#else /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */ -/** - * Contiguously allocates enough space for count objects that are size bytes - * of memory each and returns a pointer to the allocated memory. - * - * The allocated memory is filled with bytes of value zero. - * - * @param count number of objects to allocate - * @param size size of the objects to allocate - * @return pointer to allocated memory / NULL pointer if there is an error - */ -void * -mem_calloc(mem_size_t count, mem_size_t size) -{ - void *p; - - /* allocate 'count' objects of size 'size' */ - p = mem_malloc(count * size); - if (p) { - /* zero the memory */ - memset(p, 0, (size_t)count * (size_t)size); - } - return p; -} -#endif /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/memp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/memp.c deleted file mode 100644 index 2807144a858387bba7258d6cc63fb06af2f36f71..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/memp.c +++ /dev/null @@ -1,533 +0,0 @@ -/** - * @file - * Dynamic pool memory manager - * - * lwIP has dedicated pools for many structures (netconn, protocol control blocks, - * packet buffers, ...). All these pools are managed here. - * - * @defgroup mempool Memory pools - * @ingroup infrastructure - * Custom memory pools - - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/stats.h" - -#include - -/* Make sure we include everything we need for size calculation required by memp_std.h */ -#include "lwip/pbuf.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/ip4_frag.h" -#include "lwip/netbuf.h" -#include "lwip/api.h" -#include "lwip/priv/tcpip_priv.h" -#include "lwip/priv/api_msg.h" -#include "lwip/sockets.h" -#include "lwip/netifapi.h" -#include "lwip/etharp.h" -#include "lwip/igmp.h" -#include "lwip/timeouts.h" -/* needed by default MEMP_NUM_SYS_TIMEOUT */ -#include "lwip/netdb.h" -#include "lwip/dns.h" -#include "lwip/priv/nd6_priv.h" -#include "lwip/ip6_frag.h" -#include "lwip/mld6.h" - -#include "str_pub.h" - -#define LWIP_MEMPOOL(name,num,size,desc) LWIP_MEMPOOL_DECLARE(name,num,size,desc) -#include "lwip/priv/memp_std.h" - -const struct memp_desc* const memp_pools[MEMP_MAX] = { -#define LWIP_MEMPOOL(name,num,size,desc) &memp_ ## name, -#include "lwip/priv/memp_std.h" -}; - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -#if MEMP_MEM_MALLOC && MEMP_OVERFLOW_CHECK >= 2 -#undef MEMP_OVERFLOW_CHECK -/* MEMP_OVERFLOW_CHECK >= 2 does not work with MEMP_MEM_MALLOC, use 1 instead */ -#define MEMP_OVERFLOW_CHECK 1 -#endif - -#if MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC -/** - * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm". - */ -static int -memp_sanity(const struct memp_desc *desc) -{ - struct memp *t, *h; - - t = *desc->tab; - if (t != NULL) { - for (h = t->next; (t != NULL) && (h != NULL); t = t->next, - h = ((h->next != NULL) ? h->next->next : NULL)) { - if (t == h) { - return 0; - } - } - } - - return 1; -} -#endif /* MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC */ - -#if MEMP_OVERFLOW_CHECK -/** - * Check if a memp element was victim of an overflow - * (e.g. the restricted area after it has been altered) - * - * @param p the memp element to check - * @param desc the pool p comes from - */ -static void -memp_overflow_check_element_overflow(struct memp *p, const struct memp_desc *desc) -{ -#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 - u16_t k; - u8_t *m; - m = (u8_t*)p + MEMP_SIZE + desc->size; - for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) { - if (m[k] != 0xcd) { - char errstr[128] = "detected memp overflow in pool "; - strcat(errstr, desc->desc); - LWIP_ASSERT(errstr, 0); - } - } -#else /* MEMP_SANITY_REGION_AFTER_ALIGNED > 0 */ - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(desc); -#endif /* MEMP_SANITY_REGION_AFTER_ALIGNED > 0 */ -} - -/** - * Check if a memp element was victim of an underflow - * (e.g. the restricted area before it has been altered) - * - * @param p the memp element to check - * @param desc the pool p comes from - */ -static void -memp_overflow_check_element_underflow(struct memp *p, const struct memp_desc *desc) -{ -#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 - u16_t k; - u8_t *m; - m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; - for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) { - if (m[k] != 0xcd) { - char errstr[128] = "detected memp underflow in pool "; - strcat(errstr, desc->desc); - LWIP_ASSERT(errstr, 0); - } - } -#else /* MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 */ - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(desc); -#endif /* MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 */ -} - -/** - * Initialize the restricted area of on memp element. - */ -static void -memp_overflow_init_element(struct memp *p, const struct memp_desc *desc) -{ -#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 || MEMP_SANITY_REGION_AFTER_ALIGNED > 0 - u8_t *m; -#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; - memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED); -#endif -#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE + desc->size; - memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED); -#endif -#else /* MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 || MEMP_SANITY_REGION_AFTER_ALIGNED > 0 */ - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(desc); -#endif /* MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 || MEMP_SANITY_REGION_AFTER_ALIGNED > 0 */ -} - -#if MEMP_OVERFLOW_CHECK >= 2 -/** - * Do an overflow check for all elements in every pool. - * - * @see memp_overflow_check_element for a description of the check - */ -static void -memp_overflow_check_all(void) -{ - u16_t i, j; - struct memp *p; - SYS_ARCH_DECL_PROTECT(old_level); - SYS_ARCH_PROTECT(old_level); - - for (i = 0; i < MEMP_MAX; ++i) { - p = (struct memp*)LWIP_MEM_ALIGN(memp_pools[i]->base); - for (j = 0; j < memp_pools[i]->num; ++j) { - memp_overflow_check_element_overflow(p, memp_pools[i]); - memp_overflow_check_element_underflow(p, memp_pools[i]); - p = LWIP_ALIGNMENT_CAST(struct memp*, ((u8_t*)p + MEMP_SIZE + memp_pools[i]->size + MEMP_SANITY_REGION_AFTER_ALIGNED)); - } - } - SYS_ARCH_UNPROTECT(old_level); -} -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ -#endif /* MEMP_OVERFLOW_CHECK */ - -/** - * Initialize custom memory pool. - * Related functions: memp_malloc_pool, memp_free_pool - * - * @param desc pool to initialize - */ -void -memp_init_pool(const struct memp_desc *desc) -{ -#if MEMP_MEM_MALLOC - LWIP_UNUSED_ARG(desc); -#else - int i; - struct memp *memp; - - *desc->tab = NULL; - memp = (struct memp*)LWIP_MEM_ALIGN(desc->base); - /* create a linked list of memp elements */ - for (i = 0; i < desc->num; ++i) { - memp->next = *desc->tab; - *desc->tab = memp; -#if MEMP_OVERFLOW_CHECK - memp_overflow_init_element(memp, desc); -#endif /* MEMP_OVERFLOW_CHECK */ - /* cast through void* to get rid of alignment warnings */ - memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size -#if MEMP_OVERFLOW_CHECK - + MEMP_SANITY_REGION_AFTER_ALIGNED -#endif - ); - } -#if MEMP_STATS - desc->stats->avail = desc->num; -#endif /* MEMP_STATS */ -#endif /* !MEMP_MEM_MALLOC */ - -#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) - desc->stats->name = desc->desc; -#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */ -} - -/** - * Initializes lwIP built-in pools. - * Related functions: memp_malloc, memp_free - * - * Carves out memp_memory into linked lists for each pool-type. - */ -void -memp_init(void) -{ - u16_t i; - - /* for every pool: */ - for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { - memp_init_pool(memp_pools[i]); - -#if LWIP_STATS && MEMP_STATS - lwip_stats.memp[i] = memp_pools[i]->stats; -#endif - } - -#if MEMP_OVERFLOW_CHECK >= 2 - /* check everything a first time to see if it worked */ - memp_overflow_check_all(); -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ -} - -static void* -#if !MEMP_OVERFLOW_CHECK -do_memp_malloc_pool(const struct memp_desc *desc) -#else -do_memp_malloc_pool_fn(const struct memp_desc *desc, const char* file, const int line) -#endif -{ - struct memp *memp; - SYS_ARCH_DECL_PROTECT(old_level); - -#if MEMP_MEM_MALLOC - memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size)); - SYS_ARCH_PROTECT(old_level); -#else /* MEMP_MEM_MALLOC */ - SYS_ARCH_PROTECT(old_level); - - memp = *desc->tab; -#endif /* MEMP_MEM_MALLOC */ - - if (memp != NULL) { -#if !MEMP_MEM_MALLOC -#if MEMP_OVERFLOW_CHECK == 1 - memp_overflow_check_element_overflow(memp, desc); - memp_overflow_check_element_underflow(memp, desc); -#endif /* MEMP_OVERFLOW_CHECK */ - - *desc->tab = memp->next; -#if MEMP_OVERFLOW_CHECK - memp->next = NULL; -#endif /* MEMP_OVERFLOW_CHECK */ -#endif /* !MEMP_MEM_MALLOC */ -#if MEMP_OVERFLOW_CHECK - memp->file = file; - memp->line = line; -#if MEMP_MEM_MALLOC - memp_overflow_init_element(memp, desc); -#endif /* MEMP_MEM_MALLOC */ -#endif /* MEMP_OVERFLOW_CHECK */ - LWIP_ASSERT("memp_malloc: memp properly aligned", - ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); -#if MEMP_STATS - desc->stats->used++; - if (desc->stats->used > desc->stats->max) { - desc->stats->max = desc->stats->used; - } -#endif - SYS_ARCH_UNPROTECT(old_level); - /* cast through u8_t* to get rid of alignment warnings */ - return ((u8_t*)memp + MEMP_SIZE); - } else { - LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc)); -#if MEMP_STATS - desc->stats->err++; -#endif - } - - SYS_ARCH_UNPROTECT(old_level); - return NULL; -} - -/** - * Get an element from a custom pool. - * - * @param desc the pool to get an element from - * - * @return a pointer to the allocated memory or a NULL pointer on error - */ -void * -#if !MEMP_OVERFLOW_CHECK -memp_malloc_pool(const struct memp_desc *desc) -#else -memp_malloc_pool_fn(const struct memp_desc *desc, const char* file, const int line) -#endif -{ - LWIP_ASSERT("invalid pool desc", desc != NULL); - if (desc == NULL) { - return NULL; - } - -#if !MEMP_OVERFLOW_CHECK - return do_memp_malloc_pool(desc); -#else - return do_memp_malloc_pool_fn(desc, file, line); -#endif -} - -/** - * Get an element from a specific pool. - * - * @param type the pool to get an element from - * - * @return a pointer to the allocated memory or a NULL pointer on error - */ -void * -#if !MEMP_OVERFLOW_CHECK -memp_malloc(memp_t type) -#else -memp_malloc_fn(memp_t type, const char* file, const int line) -#endif -{ - void *memp; - LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); - -#if MEMP_OVERFLOW_CHECK >= 2 - memp_overflow_check_all(); -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ - -#if !MEMP_OVERFLOW_CHECK - memp = do_memp_malloc_pool(memp_pools[type]); -#else - memp = do_memp_malloc_pool_fn(memp_pools[type], file, line); -#endif - - return memp; -} - -static void -do_memp_free_pool(const struct memp_desc* desc, void *mem) -{ - struct memp *memp; - SYS_ARCH_DECL_PROTECT(old_level); - - LWIP_ASSERT("memp_free: mem properly aligned", - ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); - - /* cast through void* to get rid of alignment warnings */ - memp = (struct memp *)(void *)((u8_t*)mem - MEMP_SIZE); - - SYS_ARCH_PROTECT(old_level); - -#if MEMP_OVERFLOW_CHECK == 1 - memp_overflow_check_element_overflow(memp, desc); - memp_overflow_check_element_underflow(memp, desc); -#endif /* MEMP_OVERFLOW_CHECK */ - -#if MEMP_STATS - desc->stats->used--; -#endif - -#if MEMP_MEM_MALLOC - LWIP_UNUSED_ARG(desc); - SYS_ARCH_UNPROTECT(old_level); - mem_free(memp); -#else /* MEMP_MEM_MALLOC */ - memp->next = *desc->tab; - *desc->tab = memp; - -#if MEMP_SANITY_CHECK - LWIP_ASSERT("memp sanity", memp_sanity(desc)); -#endif /* MEMP_SANITY_CHECK */ - - SYS_ARCH_UNPROTECT(old_level); -#endif /* !MEMP_MEM_MALLOC */ -} - -/** - * Put a custom pool element back into its pool. - * - * @param desc the pool where to put mem - * @param mem the memp element to free - */ -void -memp_free_pool(const struct memp_desc* desc, void *mem) -{ - LWIP_ASSERT("invalid pool desc", desc != NULL); - if ((desc == NULL) || (mem == NULL)) { - return; - } - - do_memp_free_pool(desc, mem); -} - -/** - * Put an element back into its pool. - * - * @param type the pool where to put mem - * @param mem the memp element to free - */ -void -memp_free(memp_t type, void *mem) -{ -#ifdef LWIP_HOOK_MEMP_AVAILABLE - struct memp *old_first; -#endif - - LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;); - - if (mem == NULL) { - return; - } - -#if MEMP_OVERFLOW_CHECK >= 2 - memp_overflow_check_all(); -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ - -#ifdef LWIP_HOOK_MEMP_AVAILABLE - old_first = *memp_pools[type]->tab; -#endif - - do_memp_free_pool(memp_pools[type], mem); - -#ifdef LWIP_HOOK_MEMP_AVAILABLE - if (old_first == NULL) { - LWIP_HOOK_MEMP_AVAILABLE(type); - } -#endif -} - - -#define cmd_printf(...) do{\ - if (xWriteBufferLen > 0) {\ - snprintf(pcWriteBuffer, xWriteBufferLen, __VA_ARGS__);\ - xWriteBufferLen-= os_strlen(pcWriteBuffer);\ - pcWriteBuffer+= os_strlen(pcWriteBuffer);\ - }\ - }while(0) - -void memp_dump_Command( char *pcWriteBuffer, int xWriteBufferLen, int argc, char **argv ) -{ - int i; - struct memp_desc* tmp; - - SYS_ARCH_DECL_PROTECT(old_level); - SYS_ARCH_PROTECT(old_level); - - cmd_printf("%-16s total used addr size\r\n", "Name"); - cmd_printf("----------------------------------------------------\r\n"); - for(i=0; idesc, tmp->num, tmp->stats->used, - (int)tmp->base, tmp->size); - } - - cmd_printf("===== MEM ======\r\n"); - cmd_printf("avail %d, used %d, max %d\r\n", - lwip_stats.mem.avail, - lwip_stats.mem.used, - lwip_stats.mem.max); - - SYS_ARCH_UNPROTECT(old_level); -} - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/netif.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/netif.c deleted file mode 100644 index e901ec1bed80f64031c6eb9dedd8b4a1f4d7d4a5..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/netif.c +++ /dev/null @@ -1,1262 +0,0 @@ -/** - * @file - * lwIP network interface abstraction - * - * @defgroup netif Network interface (NETIF) - * @ingroup callbackstyle_api - * - * @defgroup netif_ip4 IPv4 address handling - * @ingroup netif - * - * @defgroup netif_ip6 IPv6 address handling - * @ingroup netif - * - * @defgroup netif_cd Client data handling - * Store data (void*) on a netif for application usage. - * @see @ref LWIP_NUM_NETIF_CLIENT_DATA - * @ingroup netif - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - */ - -#include "lwip/opt.h" - -#include - -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/udp.h" -#include "lwip/raw.h" -#include "lwip/snmp.h" -#include "lwip/igmp.h" -#include "lwip/etharp.h" -#include "lwip/stats.h" -#include "lwip/sys.h" -#include "lwip/ip.h" -#if ENABLE_LOOPBACK -#if LWIP_NETIF_LOOPBACK_MULTITHREADING -#include "lwip/tcpip.h" -#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ - -#include "netif/ethernet.h" - -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif /* LWIP_DHCP */ -#if LWIP_IPV6_DHCP6 -#include "lwip/dhcp6.h" -#endif /* LWIP_IPV6_DHCP6 */ -#if LWIP_IPV6_MLD -#include "lwip/mld6.h" -#endif /* LWIP_IPV6_MLD */ -#if LWIP_IPV6 -#include "lwip/nd6.h" -#endif - -#if LWIP_NETIF_STATUS_CALLBACK -#define NETIF_STATUS_CALLBACK(n) do{ if (n->status_callback) { (n->status_callback)(n); }}while(0) -#else -#define NETIF_STATUS_CALLBACK(n) -#endif /* LWIP_NETIF_STATUS_CALLBACK */ - -#if LWIP_NETIF_LINK_CALLBACK -#define NETIF_LINK_CALLBACK(n) do{ if (n->link_callback) { (n->link_callback)(n); }}while(0) -#else -#define NETIF_LINK_CALLBACK(n) -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -struct netif *netif_list; -struct netif *netif_default; - -static u8_t netif_num; - -#if LWIP_NUM_NETIF_CLIENT_DATA > 0 -static u8_t netif_client_id; -#endif - -#define NETIF_REPORT_TYPE_IPV4 0x01 -#define NETIF_REPORT_TYPE_IPV6 0x02 -static void netif_issue_reports(struct netif* netif, u8_t report_type); - -#if LWIP_IPV6 -static err_t netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr); -#endif /* LWIP_IPV6 */ - -#if LWIP_HAVE_LOOPIF -#if LWIP_IPV4 -static err_t netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t* addr); -#endif -#if LWIP_IPV6 -static err_t netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t* addr); -#endif - - -static struct netif loop_netif; - -/** - * Initialize a lwip network interface structure for a loopback interface - * - * @param netif the lwip network interface structure for this loopif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - */ -static err_t -netif_loopif_init(struct netif *netif) -{ - /* initialize the snmp variables and counters inside the struct netif - * ifSpeed: no assumption can be made! - */ - MIB2_INIT_NETIF(netif, snmp_ifType_softwareLoopback, 0); - - netif->name[0] = 'l'; - netif->name[1] = 'o'; -#if LWIP_IPV4 - netif->output = netif_loop_output_ipv4; -#endif -#if LWIP_IPV6 - netif->output_ip6 = netif_loop_output_ipv6; -#endif -#if LWIP_LOOPIF_MULTICAST - netif->flags |= NETIF_FLAG_IGMP; -#endif - return ERR_OK; -} -#endif /* LWIP_HAVE_LOOPIF */ - -void -netif_init(void) -{ -#if LWIP_HAVE_LOOPIF -#if LWIP_IPV4 -#define LOOPIF_ADDRINIT &loop_ipaddr, &loop_netmask, &loop_gw, - ip4_addr_t loop_ipaddr, loop_netmask, loop_gw; - IP4_ADDR(&loop_gw, 127,0,0,1); - IP4_ADDR(&loop_ipaddr, 127,0,0,1); - IP4_ADDR(&loop_netmask, 255,0,0,0); -#else /* LWIP_IPV4 */ -#define LOOPIF_ADDRINIT -#endif /* LWIP_IPV4 */ - -#if NO_SYS - netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, ip_input); -#else /* NO_SYS */ - netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, tcpip_input); -#endif /* NO_SYS */ - -#if LWIP_IPV6 - IP_ADDR6_HOST(loop_netif.ip6_addr, 0, 0, 0, 0x00000001UL); - loop_netif.ip6_addr_state[0] = IP6_ADDR_VALID; -#endif /* LWIP_IPV6 */ - - netif_set_link_up(&loop_netif); - netif_set_up(&loop_netif); - -#endif /* LWIP_HAVE_LOOPIF */ -} - -/** - * @ingroup lwip_nosys - * Forwards a received packet for input processing with - * ethernet_input() or ip_input() depending on netif flags. - * Don't call directly, pass to netif_add() and call - * netif->input(). - * Only works if the netif driver correctly sets - * NETIF_FLAG_ETHARP and/or NETIF_FLAG_ETHERNET flag! - */ -err_t -netif_input(struct pbuf *p, struct netif *inp) -{ -#if LWIP_ETHERNET - if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { - return ethernet_input(p, inp); - } else -#endif /* LWIP_ETHERNET */ - return ip_input(p, inp); -} - -/** - * @ingroup netif - * Add a network interface to the list of lwIP netifs. - * - * @param netif a pre-allocated netif structure - * @param ipaddr IP address for the new netif - * @param netmask network mask for the new netif - * @param gw default gateway IP address for the new netif - * @param state opaque data passed to the new netif - * @param init callback function that initializes the interface - * @param input callback function that is called to pass - * ingress packets up in the protocol layer stack.\n - * It is recommended to use a function that passes the input directly - * to the stack (netif_input(), NO_SYS=1 mode) or via sending a - * message to TCPIP thread (tcpip_input(), NO_SYS=0 mode).\n - * These functions use netif flags NETIF_FLAG_ETHARP and NETIF_FLAG_ETHERNET - * to decide whether to forward to ethernet_input() or ip_input(). - * In other words, the functions only work when the netif - * driver is implemented correctly!\n - * Most members of struct netif should be be initialized by the - * netif init function = netif driver (init parameter of this function).\n - * IPv6: Don't forget to call netif_create_ip6_linklocal_address() after - * setting the MAC address in struct netif.hwaddr - * (IPv6 requires a link-local address). - * - * @return netif, or NULL if failed. - */ -struct netif * -netif_add(struct netif *netif, -#if LWIP_IPV4 - const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, -#endif /* LWIP_IPV4 */ - void *state, netif_init_fn init, netif_input_fn input) -{ -#if LWIP_IPV6 - s8_t i; -#endif - - LWIP_ASSERT("No init function given", init != NULL); - - /* reset new interface configuration state */ -#if LWIP_IPV4 - ip_addr_set_zero_ip4(&netif->ip_addr); - ip_addr_set_zero_ip4(&netif->netmask); - ip_addr_set_zero_ip4(&netif->gw); -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - ip_addr_set_zero_ip6(&netif->ip6_addr[i]); - netif->ip6_addr_state[i] = IP6_ADDR_INVALID; - } - netif->output_ip6 = netif_null_output_ip6; -#endif /* LWIP_IPV6 */ - NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL); - netif->flags = 0; -#ifdef netif_get_client_data - memset(netif->client_data, 0, sizeof(netif->client_data)); -#endif /* LWIP_NUM_NETIF_CLIENT_DATA */ -#if LWIP_IPV6_AUTOCONFIG - /* IPv6 address autoconfiguration not enabled by default */ - netif->ip6_autoconfig_enabled = 0; -#endif /* LWIP_IPV6_AUTOCONFIG */ -#if LWIP_IPV6_SEND_ROUTER_SOLICIT - netif->rs_count = LWIP_ND6_MAX_MULTICAST_SOLICIT; -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ -#if LWIP_NETIF_STATUS_CALLBACK - netif->status_callback = NULL; -#endif /* LWIP_NETIF_STATUS_CALLBACK */ -#if LWIP_NETIF_LINK_CALLBACK - netif->link_callback = NULL; -#endif /* LWIP_NETIF_LINK_CALLBACK */ -#if LWIP_IGMP - netif->igmp_mac_filter = NULL; -#endif /* LWIP_IGMP */ -#if LWIP_IPV6 && LWIP_IPV6_MLD - netif->mld_mac_filter = NULL; -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ -#if ENABLE_LOOPBACK - netif->loop_first = NULL; - netif->loop_last = NULL; -#endif /* ENABLE_LOOPBACK */ - - /* remember netif specific state information data */ - netif->state = state; - netif->num = netif_num++; - netif->input = input; - - NETIF_SET_HWADDRHINT(netif, NULL); -#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS - netif->loop_cnt_current = 0; -#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ - -#if LWIP_IPV4 - netif_set_addr(netif, ipaddr, netmask, gw); -#endif /* LWIP_IPV4 */ - - /* call user specified initialization function for netif */ - if (init(netif) != ERR_OK) { - return NULL; - } - - /* add this netif to the list */ - netif->next = netif_list; - netif_list = netif; - mib2_netif_added(netif); - -#if LWIP_IGMP - /* start IGMP processing */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_start(netif); - } -#endif /* LWIP_IGMP */ - - LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP", - netif->name[0], netif->name[1])); -#if LWIP_IPV4 - LWIP_DEBUGF(NETIF_DEBUG, (" addr ")); - ip4_addr_debug_print(NETIF_DEBUG, ipaddr); - LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); - ip4_addr_debug_print(NETIF_DEBUG, netmask); - LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); - ip4_addr_debug_print(NETIF_DEBUG, gw); -#endif /* LWIP_IPV4 */ - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); - return netif; -} - -#if LWIP_IPV4 -/** - * @ingroup netif_ip4 - * Change IP address configuration for a network interface (including netmask - * and default gateway). - * - * @param netif the network interface to change - * @param ipaddr the new IP address - * @param netmask the new netmask - * @param gw the new default gateway - */ -void -netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, - const ip4_addr_t *gw) -{ - if (ip4_addr_isany(ipaddr)) { - /* when removing an address, we have to remove it *before* changing netmask/gw - to ensure that tcp RST segment can be sent correctly */ - netif_set_ipaddr(netif, ipaddr); - netif_set_netmask(netif, netmask); - netif_set_gw(netif, gw); - } else { - netif_set_netmask(netif, netmask); - netif_set_gw(netif, gw); - /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ - netif_set_ipaddr(netif, ipaddr); - } -} -#endif /* LWIP_IPV4*/ - -/** - * @ingroup netif - * Remove a network interface from the list of lwIP netifs. - * - * @param netif the network interface to remove - */ -void -netif_remove(struct netif *netif) -{ -#if LWIP_IPV6 - int i; -#endif - - if (netif == NULL) { - return; - } - -#if LWIP_IPV4 - if (!ip4_addr_isany_val(*netif_ip4_addr(netif))) { -#if LWIP_TCP - tcp_netif_ip_addr_changed(netif_ip_addr4(netif), NULL); -#endif /* LWIP_TCP */ -#if LWIP_UDP - udp_netif_ip_addr_changed(netif_ip_addr4(netif), NULL); -#endif /* LWIP_UDP */ -#if LWIP_RAW - raw_netif_ip_addr_changed(netif_ip_addr4(netif), NULL); -#endif /* LWIP_RAW */ - } - -#if LWIP_IGMP - /* stop IGMP processing */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_stop(netif); - } -#endif /* LWIP_IGMP */ -#endif /* LWIP_IPV4*/ - -#if LWIP_IPV6 - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) { -#if LWIP_TCP - tcp_netif_ip_addr_changed(netif_ip_addr6(netif, i), NULL); -#endif /* LWIP_TCP */ -#if LWIP_UDP - udp_netif_ip_addr_changed(netif_ip_addr6(netif, i), NULL); -#endif /* LWIP_UDP */ -#if LWIP_RAW - raw_netif_ip_addr_changed(netif_ip_addr6(netif, i), NULL); -#endif /* LWIP_RAW */ - } - } -#if LWIP_IPV6_MLD - /* stop MLD processing */ - mld6_stop(netif); -#endif /* LWIP_IPV6_MLD */ -#endif /* LWIP_IPV6 */ - if (netif_is_up(netif)) { - /* set netif down before removing (call callback function) */ - netif_set_down(netif); - } - - mib2_remove_ip4(netif); - - /* this netif is default? */ - if (netif_default == netif) { - /* reset default netif */ - netif_set_default(NULL); - } - /* is it the first netif? */ - if (netif_list == netif) { - netif_list = netif->next; - } else { - /* look for netif further down the list */ - struct netif * tmp_netif; - for (tmp_netif = netif_list; tmp_netif != NULL; tmp_netif = tmp_netif->next) { - if (tmp_netif->next == netif) { - tmp_netif->next = netif->next; - break; - } - } - if (tmp_netif == NULL) { - return; /* netif is not on the list */ - } - } - mib2_netif_removed(netif); -#if LWIP_NETIF_REMOVE_CALLBACK - if (netif->remove_callback) { - netif->remove_callback(netif); - } -#endif /* LWIP_NETIF_REMOVE_CALLBACK */ - LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); -} - -/** - * @ingroup netif - * Find a network interface by searching for its name - * - * @param name the name of the netif (like netif->name) plus concatenated number - * in ascii representation (e.g. 'en0') - */ -struct netif * -netif_find(const char *name) -{ - struct netif *netif; - u8_t num; - - if (name == NULL) { - return NULL; - } - - num = (u8_t)(name[2] - '0'); - - for (netif = netif_list; netif != NULL; netif = netif->next) { - if (num == netif->num && - name[0] == netif->name[0] && - name[1] == netif->name[1]) { - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); - return netif; - } - } - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); - return NULL; -} - -#if LWIP_IPV4 -/** - * @ingroup netif_ip4 - * Change the IP address of a network interface - * - * @param netif the network interface to change - * @param ipaddr the new IP address - * - * @note call netif_set_addr() if you also want to change netmask and - * default gateway - */ -void -netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr) -{ - ip_addr_t new_addr; - *ip_2_ip4(&new_addr) = (ipaddr ? *ipaddr : *IP4_ADDR_ANY4); - IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4); - - /* address is actually being changed? */ - if (ip4_addr_cmp(ip_2_ip4(&new_addr), netif_ip4_addr(netif)) == 0) { - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); -#if LWIP_TCP - tcp_netif_ip_addr_changed(netif_ip_addr4(netif), &new_addr); -#endif /* LWIP_TCP */ -#if LWIP_UDP - udp_netif_ip_addr_changed(netif_ip_addr4(netif), &new_addr); -#endif /* LWIP_UDP */ -#if LWIP_RAW - raw_netif_ip_addr_changed(netif_ip_addr4(netif), &new_addr); -#endif /* LWIP_RAW */ - - mib2_remove_ip4(netif); - mib2_remove_route_ip4(0, netif); - /* set new IP address to netif */ - ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr); - IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4); - mib2_add_ip4(netif); - mib2_add_route_ip4(0, netif); - - netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4); - - NETIF_STATUS_CALLBACK(netif); - } - - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1_16(netif_ip4_addr(netif)), - ip4_addr2_16(netif_ip4_addr(netif)), - ip4_addr3_16(netif_ip4_addr(netif)), - ip4_addr4_16(netif_ip4_addr(netif)))); -} - -/** - * @ingroup netif_ip4 - * Change the default gateway for a network interface - * - * @param netif the network interface to change - * @param gw the new default gateway - * - * @note call netif_set_addr() if you also want to change ip address and netmask - */ -void -netif_set_gw(struct netif *netif, const ip4_addr_t *gw) -{ - ip4_addr_set(ip_2_ip4(&netif->gw), gw); - IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4); - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1_16(netif_ip4_gw(netif)), - ip4_addr2_16(netif_ip4_gw(netif)), - ip4_addr3_16(netif_ip4_gw(netif)), - ip4_addr4_16(netif_ip4_gw(netif)))); -} - -/** - * @ingroup netif_ip4 - * Change the netmask of a network interface - * - * @param netif the network interface to change - * @param netmask the new netmask - * - * @note call netif_set_addr() if you also want to change ip address and - * default gateway - */ -void -netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask) -{ - mib2_remove_route_ip4(0, netif); - /* set new netmask to netif */ - ip4_addr_set(ip_2_ip4(&netif->netmask), netmask); - IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4); - mib2_add_route_ip4(0, netif); - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1_16(netif_ip4_netmask(netif)), - ip4_addr2_16(netif_ip4_netmask(netif)), - ip4_addr3_16(netif_ip4_netmask(netif)), - ip4_addr4_16(netif_ip4_netmask(netif)))); -} -#endif /* LWIP_IPV4 */ - -/** - * @ingroup netif - * Set a network interface as the default network interface - * (used to output all packets for which no specific route is found) - * - * @param netif the default network interface - */ -void -netif_set_default(struct netif *netif) -{ - if (netif == NULL) { - /* remove default route */ - mib2_remove_route_ip4(1, netif); - } else { - /* install default route */ - mib2_add_route_ip4(1, netif); - } - netif_default = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", - netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); -} - -/** - * @ingroup netif - * Bring an interface up, available for processing - * traffic. - */ -void -netif_set_up(struct netif *netif) -{ - if (!(netif->flags & NETIF_FLAG_UP)) { - netif->flags |= NETIF_FLAG_UP; - - MIB2_COPY_SYSUPTIME_TO(&netif->ts); - - NETIF_STATUS_CALLBACK(netif); - - if (netif->flags & NETIF_FLAG_LINK_UP) { - netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4|NETIF_REPORT_TYPE_IPV6); - } - } -} - -/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change - */ -static void -netif_issue_reports(struct netif* netif, u8_t report_type) -{ -#if LWIP_IPV4 - if ((report_type & NETIF_REPORT_TYPE_IPV4) && - !ip4_addr_isany_val(*netif_ip4_addr(netif))) { -#if LWIP_ARP - /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ - if (netif->flags & (NETIF_FLAG_ETHARP)) { - etharp_gratuitous(netif); - } -#endif /* LWIP_ARP */ - -#if LWIP_IGMP - /* resend IGMP memberships */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_report_groups(netif); - } -#endif /* LWIP_IGMP */ - } -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 - if (report_type & NETIF_REPORT_TYPE_IPV6) { -#if LWIP_IPV6_MLD - /* send mld memberships */ - mld6_report_groups(netif); -#endif /* LWIP_IPV6_MLD */ -#if LWIP_IPV6_SEND_ROUTER_SOLICIT - /* Send Router Solicitation messages. */ - netif->rs_count = LWIP_ND6_MAX_MULTICAST_SOLICIT; -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ - } -#endif /* LWIP_IPV6 */ -} - -/** - * @ingroup netif - * Bring an interface down, disabling any traffic processing. - */ -void -netif_set_down(struct netif *netif) -{ - if (netif->flags & NETIF_FLAG_UP) { - netif->flags &= ~NETIF_FLAG_UP; - MIB2_COPY_SYSUPTIME_TO(&netif->ts); - -#if LWIP_IPV4 && LWIP_ARP - if (netif->flags & NETIF_FLAG_ETHARP) { - etharp_cleanup_netif(netif); - } -#endif /* LWIP_IPV4 && LWIP_ARP */ - -#if LWIP_IPV6 - nd6_cleanup_netif(netif); -#endif /* LWIP_IPV6 */ - - NETIF_STATUS_CALLBACK(netif); - } -} - -#if LWIP_NETIF_STATUS_CALLBACK -/** - * @ingroup netif - * Set callback to be called when interface is brought up/down or address is changed while up - */ -void -netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback) -{ - if (netif) { - netif->status_callback = status_callback; - } -} -#endif /* LWIP_NETIF_STATUS_CALLBACK */ - -#if LWIP_NETIF_REMOVE_CALLBACK -/** - * @ingroup netif - * Set callback to be called when the interface has been removed - */ -void -netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback) -{ - if (netif) { - netif->remove_callback = remove_callback; - } -} -#endif /* LWIP_NETIF_REMOVE_CALLBACK */ - -/** - * @ingroup netif - * Called by a driver when its link goes up - */ -void -netif_set_link_up(struct netif *netif) -{ - if (!(netif->flags & NETIF_FLAG_LINK_UP)) { - netif->flags |= NETIF_FLAG_LINK_UP; - -#if LWIP_DHCP - dhcp_network_changed(netif); -#endif /* LWIP_DHCP */ - -#if LWIP_AUTOIP - autoip_network_changed(netif); -#endif /* LWIP_AUTOIP */ - - if (netif->flags & NETIF_FLAG_UP) { - netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4|NETIF_REPORT_TYPE_IPV6); - } - NETIF_LINK_CALLBACK(netif); - } -} - -/** - * @ingroup netif - * Called by a driver when its link goes down - */ -void -netif_set_link_down(struct netif *netif ) -{ - if (netif->flags & NETIF_FLAG_LINK_UP) { - netif->flags &= ~NETIF_FLAG_LINK_UP; - NETIF_LINK_CALLBACK(netif); - } -} - -#if LWIP_NETIF_LINK_CALLBACK -/** - * @ingroup netif - * Set callback to be called when link is brought up/down - */ -void -netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) -{ - if (netif) { - netif->link_callback = link_callback; - } -} -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -#if ENABLE_LOOPBACK -/** - * @ingroup netif - * Send an IP packet to be received on the same netif (loopif-like). - * The pbuf is simply copied and handed back to netif->input. - * In multithreaded mode, this is done directly since netif->input must put - * the packet on a queue. - * In callback mode, the packet is put on an internal queue and is fed to - * netif->input by netif_poll(). - * - * @param netif the lwip network interface structure - * @param p the (IP) packet to 'send' - * @return ERR_OK if the packet has been sent - * ERR_MEM if the pbuf used to copy the packet couldn't be allocated - */ -err_t -netif_loop_output(struct netif *netif, struct pbuf *p) -{ - struct pbuf *r; - err_t err; - struct pbuf *last; -#if LWIP_LOOPBACK_MAX_PBUFS - u16_t clen = 0; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - /* If we have a loopif, SNMP counters are adjusted for it, - * if not they are adjusted for 'netif'. */ -#if MIB2_STATS -#if LWIP_HAVE_LOOPIF - struct netif *stats_if = &loop_netif; -#else /* LWIP_HAVE_LOOPIF */ - struct netif *stats_if = netif; -#endif /* LWIP_HAVE_LOOPIF */ -#endif /* MIB2_STATS */ - SYS_ARCH_DECL_PROTECT(lev); - - /* Allocate a new pbuf */ - r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); - if (r == NULL) { - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); - return ERR_MEM; - } -#if LWIP_LOOPBACK_MAX_PBUFS - clen = pbuf_clen(r); - /* check for overflow or too many pbuf on queue */ - if (((netif->loop_cnt_current + clen) < netif->loop_cnt_current) || - ((netif->loop_cnt_current + clen) > LWIP_LOOPBACK_MAX_PBUFS)) { - pbuf_free(r); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); - return ERR_MEM; - } - netif->loop_cnt_current += clen; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - - /* Copy the whole pbuf queue p into the single pbuf r */ - if ((err = pbuf_copy(r, p)) != ERR_OK) { - pbuf_free(r); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); - return err; - } - - /* Put the packet on a linked list which gets emptied through calling - netif_poll(). */ - - /* let last point to the last pbuf in chain r */ - for (last = r; last->next != NULL; last = last->next); - - SYS_ARCH_PROTECT(lev); - if (netif->loop_first != NULL) { - LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL); - netif->loop_last->next = r; - netif->loop_last = last; - } else { - netif->loop_first = r; - netif->loop_last = last; - } - SYS_ARCH_UNPROTECT(lev); - - LINK_STATS_INC(link.xmit); - MIB2_STATS_NETIF_ADD(stats_if, ifoutoctets, p->tot_len); - MIB2_STATS_NETIF_INC(stats_if, ifoutucastpkts); - -#if LWIP_NETIF_LOOPBACK_MULTITHREADING - /* For multithreading environment, schedule a call to netif_poll */ - tcpip_callback_with_block((tcpip_callback_fn)netif_poll, netif, 0); -#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ - - return ERR_OK; -} - -#if LWIP_HAVE_LOOPIF -#if LWIP_IPV4 -static err_t -netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t* addr) -{ - LWIP_UNUSED_ARG(addr); - return netif_loop_output(netif, p); -} -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -static err_t -netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t* addr) -{ - LWIP_UNUSED_ARG(addr); - return netif_loop_output(netif, p); -} -#endif /* LWIP_IPV6 */ -#endif /* LWIP_HAVE_LOOPIF */ - - -/** - * Call netif_poll() in the main loop of your application. This is to prevent - * reentering non-reentrant functions like tcp_input(). Packets passed to - * netif_loop_output() are put on a list that is passed to netif->input() by - * netif_poll(). - */ -void -netif_poll(struct netif *netif) -{ - /* If we have a loopif, SNMP counters are adjusted for it, - * if not they are adjusted for 'netif'. */ -#if MIB2_STATS -#if LWIP_HAVE_LOOPIF - struct netif *stats_if = &loop_netif; -#else /* LWIP_HAVE_LOOPIF */ - struct netif *stats_if = netif; -#endif /* LWIP_HAVE_LOOPIF */ -#endif /* MIB2_STATS */ - SYS_ARCH_DECL_PROTECT(lev); - - /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */ - SYS_ARCH_PROTECT(lev); - while (netif->loop_first != NULL) { - struct pbuf *in, *in_end; -#if LWIP_LOOPBACK_MAX_PBUFS - u8_t clen = 1; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - - in = in_end = netif->loop_first; - while (in_end->len != in_end->tot_len) { - LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL); - in_end = in_end->next; -#if LWIP_LOOPBACK_MAX_PBUFS - clen++; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - } -#if LWIP_LOOPBACK_MAX_PBUFS - /* adjust the number of pbufs on queue */ - LWIP_ASSERT("netif->loop_cnt_current underflow", - ((netif->loop_cnt_current - clen) < netif->loop_cnt_current)); - netif->loop_cnt_current -= clen; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - - /* 'in_end' now points to the last pbuf from 'in' */ - if (in_end == netif->loop_last) { - /* this was the last pbuf in the list */ - netif->loop_first = netif->loop_last = NULL; - } else { - /* pop the pbuf off the list */ - netif->loop_first = in_end->next; - LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL); - } - /* De-queue the pbuf from its successors on the 'loop_' list. */ - in_end->next = NULL; - SYS_ARCH_UNPROTECT(lev); - - LINK_STATS_INC(link.recv); - MIB2_STATS_NETIF_ADD(stats_if, ifinoctets, in->tot_len); - MIB2_STATS_NETIF_INC(stats_if, ifinucastpkts); - /* loopback packets are always IP packets! */ - if (ip_input(in, netif) != ERR_OK) { - pbuf_free(in); - } - SYS_ARCH_PROTECT(lev); - } - SYS_ARCH_UNPROTECT(lev); -} - -#if !LWIP_NETIF_LOOPBACK_MULTITHREADING -/** - * Calls netif_poll() for every netif on the netif_list. - */ -void -netif_poll_all(void) -{ - struct netif *netif = netif_list; - /* loop through netifs */ - while (netif != NULL) { - netif_poll(netif); - /* proceed to next network interface */ - netif = netif->next; - } -} -#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ - -#if LWIP_NUM_NETIF_CLIENT_DATA > 0 -/** - * @ingroup netif_cd - * Allocate an index to store data in client_data member of struct netif. - * Returned value is an index in mentioned array. - * @see LWIP_NUM_NETIF_CLIENT_DATA - */ -u8_t -netif_alloc_client_data_id(void) -{ - u8_t result = netif_client_id; - netif_client_id++; - - LWIP_ASSERT("Increase LWIP_NUM_NETIF_CLIENT_DATA in lwipopts.h", result < LWIP_NUM_NETIF_CLIENT_DATA); - return result + LWIP_NETIF_CLIENT_DATA_INDEX_MAX; -} -#endif - -#if LWIP_IPV6 -/** - * @ingroup netif_ip6 - * Change an IPv6 address of a network interface - * - * @param netif the network interface to change - * @param addr_idx index of the IPv6 address - * @param addr6 the new IPv6 address - * - * @note call netif_ip6_addr_set_state() to set the address valid/temptative - */ -void -netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6) -{ - LWIP_ASSERT("addr6 != NULL", addr6 != NULL); - netif_ip6_addr_set_parts(netif, addr_idx, addr6->addr[0], addr6->addr[1], - addr6->addr[2], addr6->addr[3]); -} - -/* - * Change an IPv6 address of a network interface (internal version taking 4 * u32_t) - * - * @param netif the network interface to change - * @param addr_idx index of the IPv6 address - * @param i0 word0 of the new IPv6 address - * @param i1 word1 of the new IPv6 address - * @param i2 word2 of the new IPv6 address - * @param i3 word3 of the new IPv6 address - */ -void -netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3) -{ - const ip6_addr_t *old_addr; - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES); - - old_addr = netif_ip6_addr(netif, addr_idx); - /* address is actually being changed? */ - if ((old_addr->addr[0] != i0) || (old_addr->addr[1] != i1) || - (old_addr->addr[2] != i2) || (old_addr->addr[3] != i3)) { - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set: netif address being changed\n")); - - if (netif_ip6_addr_state(netif, addr_idx) & IP6_ADDR_VALID) { -#if LWIP_TCP || LWIP_UDP - ip_addr_t new_ipaddr; - IP_ADDR6(&new_ipaddr, i0, i1, i2, i3); -#endif /* LWIP_TCP || LWIP_UDP */ -#if LWIP_TCP - tcp_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), &new_ipaddr); -#endif /* LWIP_TCP */ -#if LWIP_UDP - udp_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), &new_ipaddr); -#endif /* LWIP_UDP */ -#if LWIP_RAW - raw_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), &new_ipaddr); -#endif /* LWIP_RAW */ - } - /* @todo: remove/readd mib2 ip6 entries? */ - - IP6_ADDR(ip_2_ip6(&(netif->ip6_addr[addr_idx])), i0, i1, i2, i3); - IP_SET_TYPE_VAL(netif->ip6_addr[addr_idx], IPADDR_TYPE_V6); - - if (netif_ip6_addr_state(netif, addr_idx) & IP6_ADDR_VALID) { - netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6); - NETIF_STATUS_CALLBACK(netif); - } - } - - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n", - addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)), - netif_ip6_addr_state(netif, addr_idx))); -} - -/** - * @ingroup netif_ip6 - * Change the state of an IPv6 address of a network interface - * (INVALID, TEMPTATIVE, PREFERRED, DEPRECATED, where TEMPTATIVE - * includes the number of checks done, see ip6_addr.h) - * - * @param netif the network interface to change - * @param addr_idx index of the IPv6 address - * @param state the new IPv6 address state - */ -void -netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state) -{ - u8_t old_state; - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES); - - old_state = netif_ip6_addr_state(netif, addr_idx); - /* state is actually being changed? */ - if (old_state != state) { - u8_t old_valid = old_state & IP6_ADDR_VALID; - u8_t new_valid = state & IP6_ADDR_VALID; - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set_state: netif address state being changed\n")); - -#if LWIP_IPV6_MLD - /* Reevaluate solicited-node multicast group membership. */ - if (netif->flags & NETIF_FLAG_MLD6) { - nd6_adjust_mld_membership(netif, addr_idx, state); - } -#endif /* LWIP_IPV6_MLD */ - - if (old_valid && !new_valid) { - /* address about to be removed by setting invalid */ -#if LWIP_TCP - tcp_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), NULL); -#endif /* LWIP_TCP */ -#if LWIP_UDP - udp_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), NULL); -#endif /* LWIP_UDP */ -#if LWIP_RAW - raw_netif_ip_addr_changed(netif_ip_addr6(netif, addr_idx), NULL); -#endif /* LWIP_RAW */ - /* @todo: remove mib2 ip6 entries? */ - } - netif->ip6_addr_state[addr_idx] = state; - - if (!old_valid && new_valid) { - /* address added by setting valid */ - /* @todo: add mib2 ip6 entries? */ - netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6); - } - if ((old_state & IP6_ADDR_PREFERRED) != (state & IP6_ADDR_PREFERRED)) { - /* address state has changed (valid flag changed or switched between - preferred and deprecated) -> call the callback function */ - NETIF_STATUS_CALLBACK(netif); - } - } - - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n", - addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)), - netif_ip6_addr_state(netif, addr_idx))); -} - -/** - * Checks if a specific address is assigned to the netif and returns its - * index. - * - * @param netif the netif to check - * @param ip6addr the IPv6 address to find - * @return >= 0: address found, this is its index - * -1: address not found on this netif - */ -s8_t -netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr) -{ - s8_t i; - for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i)) && - ip6_addr_cmp(netif_ip6_addr(netif, i), ip6addr)) { - return i; - } - } - return -1; -} - -/** - * @ingroup netif_ip6 - * Create a link-local IPv6 address on a netif (stored in slot 0) - * - * @param netif the netif to create the address on - * @param from_mac_48bit if != 0, assume hwadr is a 48-bit MAC address (std conversion) - * if == 0, use hwaddr directly as interface ID - */ -void -netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit) -{ - u8_t i, addr_index; - - /* Link-local prefix. */ - ip_2_ip6(&netif->ip6_addr[0])->addr[0] = PP_HTONL(0xfe800000ul); - ip_2_ip6(&netif->ip6_addr[0])->addr[1] = 0; - - /* Generate interface ID. */ - if (from_mac_48bit) { - /* Assume hwaddr is a 48-bit IEEE 802 MAC. Convert to EUI-64 address. Complement Group bit. */ - ip_2_ip6(&netif->ip6_addr[0])->addr[2] = lwip_htonl((((u32_t)(netif->hwaddr[0] ^ 0x02)) << 24) | - ((u32_t)(netif->hwaddr[1]) << 16) | - ((u32_t)(netif->hwaddr[2]) << 8) | - (0xff)); - ip_2_ip6(&netif->ip6_addr[0])->addr[3] = lwip_htonl((0xfeul << 24) | - ((u32_t)(netif->hwaddr[3]) << 16) | - ((u32_t)(netif->hwaddr[4]) << 8) | - (netif->hwaddr[5])); - } else { - /* Use hwaddr directly as interface ID. */ - ip_2_ip6(&netif->ip6_addr[0])->addr[2] = 0; - ip_2_ip6(&netif->ip6_addr[0])->addr[3] = 0; - - addr_index = 3; - for (i = 0; (i < 8) && (i < netif->hwaddr_len); i++) { - if (i == 4) { - addr_index--; - } - ip_2_ip6(&netif->ip6_addr[0])->addr[addr_index] |= ((u32_t)(netif->hwaddr[netif->hwaddr_len - i - 1])) << (8 * (i & 0x03)); - } - } - - /* Set address state. */ -#if LWIP_IPV6_DUP_DETECT_ATTEMPTS - /* Will perform duplicate address detection (DAD). */ - netif_ip6_addr_set_state(netif, 0, IP6_ADDR_TENTATIVE); -#else - /* Consider address valid. */ - netif_ip6_addr_set_state(netif, 0, IP6_ADDR_PREFERRED); -#endif /* LWIP_IPV6_AUTOCONFIG */ -} - -/** - * @ingroup netif_ip6 - * This function allows for the easy addition of a new IPv6 address to an interface. - * It takes care of finding an empty slot and then sets the address tentative - * (to make sure that all the subsequent processing happens). - * - * @param netif netif to add the address on - * @param ip6addr address to add - * @param chosen_idx if != NULL, the chosen IPv6 address index will be stored here - */ -err_t -netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx) -{ - s8_t i; - - i = netif_get_ip6_addr_match(netif, ip6addr); - if (i >= 0) { - /* Address already added */ - if (chosen_idx != NULL) { - *chosen_idx = i; - } - return ERR_OK; - } - - /* Find a free slot -- musn't be the first one (reserved for link local) */ - for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) { - if (ip6_addr_isinvalid(netif_ip6_addr_state(netif, i))) { - ip_addr_copy_from_ip6(netif->ip6_addr[i], *ip6addr); - netif_ip6_addr_set_state(netif, i, IP6_ADDR_TENTATIVE); - if (chosen_idx != NULL) { - *chosen_idx = i; - } - return ERR_OK; - } - } - - if (chosen_idx != NULL) { - *chosen_idx = -1; - } - return ERR_VAL; -} - -/** Dummy IPv6 output function for netifs not supporting IPv6 - */ -static err_t -netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr) -{ - LWIP_UNUSED_ARG(netif); - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(ipaddr); - - return ERR_IF; -} -#endif /* LWIP_IPV6 */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/pbuf.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/pbuf.c deleted file mode 100644 index 059f83a5713b3ccd4ba5b8f4fa074f4c307d2f5e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/pbuf.c +++ /dev/null @@ -1,1442 +0,0 @@ -/** - * @file - * Packet buffer management - */ - -/** - * @defgroup pbuf Packet buffers (PBUF) - * @ingroup infrastructure - * - * Packets are built from the pbuf data structure. It supports dynamic - * memory allocation for packet contents or can reference externally - * managed packet contents both in RAM and ROM. Quick allocation for - * incoming packets is provided through pools with fixed sized pbufs. - * - * A packet may span over multiple pbufs, chained as a singly linked - * list. This is called a "pbuf chain". - * - * Multiple packets may be queued, also using this singly linked list. - * This is called a "packet queue". - * - * So, a packet queue consists of one or more pbuf chains, each of - * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE - * NOT SUPPORTED!!! Use helper structs to queue multiple packets. - * - * The differences between a pbuf chain and a packet queue are very - * precise but subtle. - * - * The last pbuf of a packet has a ->tot_len field that equals the - * ->len field. It can be found by traversing the list. If the last - * pbuf of a packet has a ->next field other than NULL, more packets - * are on the queue. - * - * Therefore, looping through a pbuf of a single packet, has an - * loop end condition (tot_len == p->len), NOT (next == NULL). - * - * Example of custom pbuf usage for zero-copy RX: - @code{.c} -typedef struct my_custom_pbuf -{ - struct pbuf_custom p; - void* dma_descriptor; -} my_custom_pbuf_t; - -LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(my_custom_pbuf_t), "Zero-copy RX PBUF pool"); - -void my_pbuf_free_custom(void* p) -{ - my_custom_pbuf_t* my_puf = (my_custom_pbuf_t*)p; - - LOCK_INTERRUPTS(); - free_rx_dma_descriptor(my_pbuf->dma_descriptor); - LWIP_MEMPOOL_FREE(RX_POOL, my_pbuf); - UNLOCK_INTERRUPTS(); -} - -void eth_rx_irq() -{ - dma_descriptor* dma_desc = get_RX_DMA_descriptor_from_ethernet(); - my_custom_pbuf_t* my_pbuf = (my_custom_pbuf_t*)LWIP_MEMPOOL_ALLOC(RX_POOL); - - my_pbuf->p.custom_free_function = my_pbuf_free_custom; - my_pbuf->dma_descriptor = dma_desc; - - invalidate_cpu_cache(dma_desc->rx_data, dma_desc->rx_length); - - struct pbuf* p = pbuf_alloced_custom(PBUF_RAW, - dma_desc->rx_length, - PBUF_REF, - &my_pbuf->p, - dma_desc->rx_data, - dma_desc->max_buffer_size); - - if(netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } -} - @endcode - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/stats.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#if LWIP_TCP && TCP_QUEUE_OOSEQ -#include "lwip/priv/tcp_priv.h" -#endif -#if LWIP_CHECKSUM_ON_COPY -#include "lwip/inet_chksum.h" -#endif - -#include - -#define SIZEOF_STRUCT_PBUF LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) -/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically - aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */ -#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE) - -#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ -#define PBUF_POOL_IS_EMPTY() -#else /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ - -#if !NO_SYS -#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL -#include "lwip/tcpip.h" -#define PBUF_POOL_FREE_OOSEQ_QUEUE_CALL() do { \ - if (tcpip_callback_with_block(pbuf_free_ooseq_callback, NULL, 0) != ERR_OK) { \ - SYS_ARCH_PROTECT(old_level); \ - pbuf_free_ooseq_pending = 0; \ - SYS_ARCH_UNPROTECT(old_level); \ - } } while(0) -#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ -#endif /* !NO_SYS */ - -volatile u8_t pbuf_free_ooseq_pending; -#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty() - -/** - * Attempt to reclaim some memory from queued out-of-sequence TCP segments - * if we run out of pool pbufs. It's better to give priority to new packets - * if we're running out. - * - * This must be done in the correct thread context therefore this function - * can only be used with NO_SYS=0 and through tcpip_callback. - */ -#if !NO_SYS -static -#endif /* !NO_SYS */ -void -pbuf_free_ooseq(void) -{ - struct tcp_pcb* pcb; - SYS_ARCH_SET(pbuf_free_ooseq_pending, 0); - - for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { - if (NULL != pcb->ooseq) { - /** Free the ooseq pbufs of one PCB only */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - return; - } - } -} - -#if !NO_SYS -/** - * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq(). - */ -static void -pbuf_free_ooseq_callback(void *arg) -{ - LWIP_UNUSED_ARG(arg); - pbuf_free_ooseq(); -} -#endif /* !NO_SYS */ - -/** Queue a call to pbuf_free_ooseq if not already queued. */ -static void -pbuf_pool_is_empty(void) -{ -#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL - SYS_ARCH_SET(pbuf_free_ooseq_pending, 1); -#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ - u8_t queued; - SYS_ARCH_DECL_PROTECT(old_level); - SYS_ARCH_PROTECT(old_level); - queued = pbuf_free_ooseq_pending; - pbuf_free_ooseq_pending = 1; - SYS_ARCH_UNPROTECT(old_level); - - if (!queued) { - /* queue a call to pbuf_free_ooseq if not already queued */ - PBUF_POOL_FREE_OOSEQ_QUEUE_CALL(); - } -#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ -} -#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ - -/** - * @ingroup pbuf - * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). - * - * The actual memory allocated for the pbuf is determined by the - * layer at which the pbuf is allocated and the requested size - * (from the size parameter). - * - * @param layer flag to define header size - * @param length size of the pbuf's payload - * @param type this parameter decides how and where the pbuf - * should be allocated as follows: - * - * - PBUF_RAM: buffer memory for pbuf is allocated as one large - * chunk. This includes protocol headers as well. - * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for - * protocol headers. Additional headers must be prepended - * by allocating another pbuf and chain in to the front of - * the ROM pbuf. It is assumed that the memory used is really - * similar to ROM in that it is immutable and will not be - * changed. Memory which is dynamic should generally not - * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. - * - PBUF_REF: no buffer memory is allocated for the pbuf, even for - * protocol headers. It is assumed that the pbuf is only - * being used in a single thread. If the pbuf gets queued, - * then pbuf_take should be called to copy the buffer. - * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from - * the pbuf pool that is allocated during pbuf_init(). - * - * @return the allocated pbuf. If multiple pbufs where allocated, this - * is the first pbuf of a pbuf chain. - */ -struct pbuf * -pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) -{ - struct pbuf *p, *q, *r; - u16_t offset; - s32_t rem_len; /* remaining length */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); - - /* determine header offset */ - switch (layer) { - case PBUF_TRANSPORT: - /* add room for transport (often TCP) layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN; - break; - case PBUF_IP: - /* add room for IP layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN; - break; - case PBUF_LINK: - /* add room for link layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN; - break; - case PBUF_RAW_TX: - /* add room for encapsulating link layer headers (e.g. 802.11) */ - offset = PBUF_LINK_ENCAPSULATION_HLEN; - break; - case PBUF_RAW: - /* no offset (e.g. RX buffers or chain successors) */ - offset = 0; - break; - default: - LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); - return NULL; - } - - switch (type) { - case PBUF_POOL: - /* allocate head of pbuf chain into p */ - p = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); - if (p == NULL) { - PBUF_POOL_IS_EMPTY(); - return NULL; - } - p->type = type; - p->next = NULL; - - /* make the payload pointer point 'offset' bytes into pbuf data memory */ - p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset))); - LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - /* the total length of the pbuf chain is the requested size */ - p->tot_len = length; - /* set the length of the first pbuf in the chain */ - p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)); - LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", - ((u8_t*)p->payload + p->len <= - (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); - LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", - (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); - /* set reference count (needed here in case we fail) */ - p->ref = 1; - - /* now allocate the tail of the pbuf chain */ - - /* remember first pbuf for linkage in next iteration */ - r = p; - /* remaining length to be allocated */ - rem_len = length - p->len; - /* any remaining pbufs to be allocated? */ - while (rem_len > 0) { - q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); - if (q == NULL) { - PBUF_POOL_IS_EMPTY(); - /* free chain so far allocated */ - pbuf_free(p); - /* bail out unsuccessfully */ - return NULL; - } - q->type = type; - q->flags = 0; - q->next = NULL; - /* make previous pbuf point to this pbuf */ - r->next = q; - /* set total length of this pbuf and next in chain */ - LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff); - q->tot_len = (u16_t)rem_len; - /* this pbuf length is pool size, unless smaller sized tail */ - q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED); - q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF); - LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", - ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); - LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", - ((u8_t*)p->payload + p->len <= - (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); - q->ref = 1; - /* calculate remaining length to be allocated */ - rem_len -= q->len; - /* remember this pbuf for linkage in next iteration */ - r = q; - } - /* end of chain */ - /*r->next = NULL;*/ - - break; - case PBUF_RAM: - { - mem_size_t alloc_len = LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length); - - /* bug #50040: Check for integer overflow when calculating alloc_len */ - if (alloc_len < LWIP_MEM_ALIGN_SIZE(length)) { - return NULL; - } - - /* If pbuf is to be allocated in RAM, allocate memory for it. */ - p = (struct pbuf*)mem_malloc(alloc_len); - } - - if (p == NULL) { - return NULL; - } - /* Set up internal structure of the pbuf. */ - p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)); - p->len = p->tot_len = length; - p->next = NULL; - p->type = type; - - LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - break; - /* pbuf references existing (non-volatile static constant) ROM payload? */ - case PBUF_ROM: - /* pbuf references existing (externally allocated) RAM payload? */ - case PBUF_REF: - /* only allocate memory for the pbuf structure */ - p = (struct pbuf *)memp_malloc(MEMP_PBUF); - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", - (type == PBUF_ROM) ? "ROM" : "REF")); - return NULL; - } - /* caller must set this field properly, afterwards */ - p->payload = NULL; - p->len = p->tot_len = length; - p->next = NULL; - p->type = type; - break; - default: - LWIP_ASSERT("pbuf_alloc: erroneous type", 0); - return NULL; - } - /* set reference count */ - p->ref = 1; - /* set flags */ - p->flags = 0; - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); - return p; -} - -#if LWIP_SUPPORT_CUSTOM_PBUF -/** - * @ingroup pbuf - * Initialize a custom pbuf (already allocated). - * - * @param l flag to define header size - * @param length size of the pbuf's payload - * @param type type of the pbuf (only used to treat the pbuf accordingly, as - * this function allocates no memory) - * @param p pointer to the custom pbuf to initialize (already allocated) - * @param payload_mem pointer to the buffer that is used for payload and headers, - * must be at least big enough to hold 'length' plus the header size, - * may be NULL if set later. - * ATTENTION: The caller is responsible for correct alignment of this buffer!! - * @param payload_mem_len the size of the 'payload_mem' buffer, must be at least - * big enough to hold 'length' plus the header size - */ -struct pbuf* -pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, - void *payload_mem, u16_t payload_mem_len) -{ - u16_t offset; - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); - - /* determine header offset */ - switch (l) { - case PBUF_TRANSPORT: - /* add room for transport (often TCP) layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN; - break; - case PBUF_IP: - /* add room for IP layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN; - break; - case PBUF_LINK: - /* add room for link layer header */ - offset = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN; - break; - case PBUF_RAW_TX: - /* add room for encapsulating link layer headers (e.g. 802.11) */ - offset = PBUF_LINK_ENCAPSULATION_HLEN; - break; - case PBUF_RAW: - offset = 0; - break; - default: - LWIP_ASSERT("pbuf_alloced_custom: bad pbuf layer", 0); - return NULL; - } - - if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) { - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); - return NULL; - } - - p->pbuf.next = NULL; - if (payload_mem != NULL) { - p->pbuf.payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset); - } else { - p->pbuf.payload = NULL; - } - p->pbuf.flags = PBUF_FLAG_IS_CUSTOM; - p->pbuf.len = p->pbuf.tot_len = length; - p->pbuf.type = type; - p->pbuf.ref = 1; - return &p->pbuf; -} -#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ - -/** - * @ingroup pbuf - * Shrink a pbuf chain to a desired length. - * - * @param p pbuf to shrink. - * @param new_len desired new length of pbuf chain - * - * Depending on the desired length, the first few pbufs in a chain might - * be skipped and left unchanged. The new last pbuf in the chain will be - * resized, and any remaining pbufs will be freed. - * - * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. - * @note May not be called on a packet queue. - * - * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). - */ -void -pbuf_realloc(struct pbuf *p, u16_t new_len) -{ - struct pbuf *q; - u16_t rem_len; /* remaining length */ - s32_t grow; - - LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); - LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL || - p->type == PBUF_ROM || - p->type == PBUF_RAM || - p->type == PBUF_REF); - - /* desired length larger than current length? */ - if (new_len >= p->tot_len) { - /* enlarging not yet supported */ - return; - } - - /* the pbuf chain grows by (new_len - p->tot_len) bytes - * (which may be negative in case of shrinking) */ - grow = new_len - p->tot_len; - - /* first, step over any pbufs that should remain in the chain */ - rem_len = new_len; - q = p; - /* should this pbuf be kept? */ - while (rem_len > q->len) { - /* decrease remaining length by pbuf length */ - rem_len -= q->len; - /* decrease total length indicator */ - LWIP_ASSERT("grow < max_u16_t", grow < 0xffff); - q->tot_len += (u16_t)grow; - /* proceed to next pbuf in chain */ - q = q->next; - LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); - } - /* we have now reached the new last pbuf (in q) */ - /* rem_len == desired length for pbuf q */ - - /* shrink allocated memory for PBUF_RAM */ - /* (other types merely adjust their length fields */ - if ((q->type == PBUF_RAM) && (rem_len != q->len) -#if LWIP_SUPPORT_CUSTOM_PBUF - && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0) -#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ - ) { - /* reallocate and adjust the length of the pbuf that will be split */ - q = (struct pbuf *)mem_trim(q, (u16_t)((u8_t *)q->payload - (u8_t *)q) + rem_len); - LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); - } - /* adjust length fields for new last pbuf */ - q->len = rem_len; - q->tot_len = q->len; - - /* any remaining pbufs in chain? */ - if (q->next != NULL) { - /* free remaining pbufs in chain */ - pbuf_free(q->next); - } - /* q is last packet in chain */ - q->next = NULL; - -} - -/** - * Adjusts the payload pointer to hide or reveal headers in the payload. - * @see pbuf_header. - * - * @param p pbuf to change the header size. - * @param header_size_increment Number of bytes to increment header size. - * @param force Allow 'header_size_increment > 0' for PBUF_REF/PBUF_ROM types - * - * @return non-zero on failure, zero on success. - * - */ -static u8_t -pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force) -{ - u16_t type; - void *payload; - u16_t increment_magnitude; - - LWIP_ASSERT("p != NULL", p != NULL); - if ((header_size_increment == 0) || (p == NULL)) { - return 0; - } - - if (header_size_increment < 0) { - increment_magnitude = (u16_t)-header_size_increment; - /* Check that we aren't going to move off the end of the pbuf */ - LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); - } else { - increment_magnitude = (u16_t)header_size_increment; -#if 0 - /* Can't assert these as some callers speculatively call - pbuf_header() to see if it's OK. Will return 1 below instead. */ - /* Check that we've got the correct type of pbuf to work with */ - LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", - p->type == PBUF_RAM || p->type == PBUF_POOL); - /* Check that we aren't going to move off the beginning of the pbuf */ - LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF", - (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF); -#endif - } - - type = p->type; - /* remember current payload pointer */ - payload = p->payload; - - /* pbuf types containing payloads? */ - if (type == PBUF_RAM || type == PBUF_POOL) { - /* set new payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - /* boundary check fails? */ - if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, - ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", - (void *)p->payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF))); - /* restore old payload pointer */ - p->payload = payload; - /* bail out unsuccessfully */ - return 1; - } - /* pbuf types referring to external payloads? */ - } else if (type == PBUF_REF || type == PBUF_ROM) { - /* hide a header in the payload? */ - if ((header_size_increment < 0) && (increment_magnitude <= p->len)) { - /* increase payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - } else if ((header_size_increment > 0) && force) { - p->payload = (u8_t *)p->payload - header_size_increment; - } else { - /* cannot expand payload to front (yet!) - * bail out unsuccessfully */ - return 1; - } - } else { - /* Unknown type */ - LWIP_ASSERT("bad pbuf type", 0); - return 1; - } - /* modify pbuf length fields */ - p->len += header_size_increment; - p->tot_len += header_size_increment; - - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n", - (void *)payload, (void *)p->payload, header_size_increment)); - - return 0; -} - -/** - * Adjusts the payload pointer to hide or reveal headers in the payload. - * - * Adjusts the ->payload pointer so that space for a header - * (dis)appears in the pbuf payload. - * - * The ->payload, ->tot_len and ->len fields are adjusted. - * - * @param p pbuf to change the header size. - * @param header_size_increment Number of bytes to increment header size which - * increases the size of the pbuf. New space is on the front. - * (Using a negative value decreases the header size.) - * If hdr_size_inc is 0, this function does nothing and returns successful. - * - * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so - * the call will fail. A check is made that the increase in header size does - * not move the payload pointer in front of the start of the buffer. - * @return non-zero on failure, zero on success. - * - */ -u8_t -pbuf_header(struct pbuf *p, s16_t header_size_increment) -{ - return pbuf_header_impl(p, header_size_increment, 0); -} - -/** - * Same as pbuf_header but does not check if 'header_size > 0' is allowed. - * This is used internally only, to allow PBUF_REF for RX. - */ -u8_t -pbuf_header_force(struct pbuf *p, s16_t header_size_increment) -{ - return pbuf_header_impl(p, header_size_increment, 1); -} - -/** - * @ingroup pbuf - * Dereference a pbuf chain or queue and deallocate any no-longer-used - * pbufs at the head of this chain or queue. - * - * Decrements the pbuf reference count. If it reaches zero, the pbuf is - * deallocated. - * - * For a pbuf chain, this is repeated for each pbuf in the chain, - * up to the first pbuf which has a non-zero reference count after - * decrementing. So, when all reference counts are one, the whole - * chain is free'd. - * - * @param p The pbuf (chain) to be dereferenced. - * - * @return the number of pbufs that were de-allocated - * from the head of the chain. - * - * @note MUST NOT be called on a packet queue (Not verified to work yet). - * @note the reference counter of a pbuf equals the number of pointers - * that refer to the pbuf (or into the pbuf). - * - * @internal examples: - * - * Assuming existing chains a->b->c with the following reference - * counts, calling pbuf_free(a) results in: - * - * 1->2->3 becomes ...1->3 - * 3->3->3 becomes 2->3->3 - * 1->1->2 becomes ......1 - * 2->1->1 becomes 1->1->1 - * 1->1->1 becomes ....... - * - */ -u8_t -pbuf_free(struct pbuf *p) -{ - u16_t type; - struct pbuf *q; - u8_t count; - - if (p == NULL) { - LWIP_ASSERT("p != NULL", p != NULL); - /* if assertions are disabled, proceed with debug output */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("pbuf_free(p == NULL) was called.\n")); - return 0; - } - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); - - PERF_START; - - LWIP_ASSERT("pbuf_free: sane type", - p->type == PBUF_RAM || p->type == PBUF_ROM || - p->type == PBUF_REF || p->type == PBUF_POOL); - - count = 0; - /* de-allocate all consecutive pbufs from the head of the chain that - * obtain a zero reference count after decrementing*/ - while (p != NULL) { - u16_t ref; - SYS_ARCH_DECL_PROTECT(old_level); - /* Since decrementing ref cannot be guaranteed to be a single machine operation - * we must protect it. We put the new ref into a local variable to prevent - * further protection. */ - SYS_ARCH_PROTECT(old_level); - /* all pbufs in a chain are referenced at least once */ - LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); - /* decrease reference count (number of pointers to pbuf) */ - ref = --(p->ref); - SYS_ARCH_UNPROTECT(old_level); - /* this pbuf is no longer referenced to? */ - if (ref == 0) { - /* remember next pbuf in chain for next iteration */ - q = p->next; - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); - type = p->type; -#if LWIP_SUPPORT_CUSTOM_PBUF - /* is this a custom pbuf? */ - if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { - struct pbuf_custom *pc = (struct pbuf_custom*)p; - LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); - pc->custom_free_function(p); - } else -#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ - { - /* is this a pbuf from the pool? */ - if (type == PBUF_POOL) { - memp_free(MEMP_PBUF_POOL, p); - /* is this a ROM or RAM referencing pbuf? */ - } else if (type == PBUF_ROM || type == PBUF_REF) { - memp_free(MEMP_PBUF, p); - /* type == PBUF_RAM */ - } else { - mem_free(p); - } - } - count++; - /* proceed to next pbuf */ - p = q; - /* p->ref > 0, this pbuf is still referenced to */ - /* (and so the remaining pbufs in chain as well) */ - } else { - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref)); - /* stop walking through the chain */ - p = NULL; - } - } - PERF_STOP("pbuf_free"); - /* return number of de-allocated pbufs */ - return count; -} - -/** - * Count number of pbufs in a chain - * - * @param p first pbuf of chain - * @return the number of pbufs in a chain - */ -u16_t -pbuf_clen(const struct pbuf *p) -{ - u16_t len; - - len = 0; - while (p != NULL) { - ++len; - p = p->next; - } - return len; -} - -/** - * @ingroup pbuf - * Increment the reference count of the pbuf. - * - * @param p pbuf to increase reference counter of - * - */ -void -pbuf_ref(struct pbuf *p) -{ - /* pbuf given? */ - if (p != NULL) { - SYS_ARCH_INC(p->ref, 1); - LWIP_ASSERT("pbuf ref overflow", p->ref > 0); - } -} - -/** - * @ingroup pbuf - * Concatenate two pbufs (each may be a pbuf chain) and take over - * the caller's reference of the tail pbuf. - * - * @note The caller MAY NOT reference the tail pbuf afterwards. - * Use pbuf_chain() for that purpose. - * - * @see pbuf_chain() - */ -void -pbuf_cat(struct pbuf *h, struct pbuf *t) -{ - struct pbuf *p; - - LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", - ((h != NULL) && (t != NULL)), return;); - - /* proceed to last pbuf of chain */ - for (p = h; p->next != NULL; p = p->next) { - /* add total length of second chain to all totals of first chain */ - p->tot_len += t->tot_len; - } - /* { p is last pbuf of first h chain, p->next == NULL } */ - LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); - LWIP_ASSERT("p->next == NULL", p->next == NULL); - /* add total length of second chain to last pbuf total of first chain */ - p->tot_len += t->tot_len; - /* chain last pbuf of head (p) with first of tail (t) */ - p->next = t; - /* p->next now references t, but the caller will drop its reference to t, - * so netto there is no change to the reference count of t. - */ -} - -/** - * @ingroup pbuf - * Chain two pbufs (or pbuf chains) together. - * - * The caller MUST call pbuf_free(t) once it has stopped - * using it. Use pbuf_cat() instead if you no longer use t. - * - * @param h head pbuf (chain) - * @param t tail pbuf (chain) - * @note The pbufs MUST belong to the same packet. - * @note MAY NOT be called on a packet queue. - * - * The ->tot_len fields of all pbufs of the head chain are adjusted. - * The ->next field of the last pbuf of the head chain is adjusted. - * The ->ref field of the first pbuf of the tail chain is adjusted. - * - */ -void -pbuf_chain(struct pbuf *h, struct pbuf *t) -{ - pbuf_cat(h, t); - /* t is now referenced by h */ - pbuf_ref(t); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); -} - -/** - * Dechains the first pbuf from its succeeding pbufs in the chain. - * - * Makes p->tot_len field equal to p->len. - * @param p pbuf to dechain - * @return remainder of the pbuf chain, or NULL if it was de-allocated. - * @note May not be called on a packet queue. - */ -struct pbuf * -pbuf_dechain(struct pbuf *p) -{ - struct pbuf *q; - u8_t tail_gone = 1; - /* tail */ - q = p->next; - /* pbuf has successor in chain? */ - if (q != NULL) { - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); - /* enforce invariant if assertion is disabled */ - q->tot_len = p->tot_len - p->len; - /* decouple pbuf from remainder */ - p->next = NULL; - /* total length of pbuf p is its own length only */ - p->tot_len = p->len; - /* q is no longer referenced by p, free it */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); - tail_gone = pbuf_free(q); - if (tail_gone > 0) { - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, - ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); - } - /* return remaining tail or NULL if deallocated */ - } - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); - return ((tail_gone > 0) ? NULL : q); -} - -/** - * @ingroup pbuf - * Create PBUF_RAM copies of pbufs. - * - * Used to queue packets on behalf of the lwIP stack, such as - * ARP based queueing. - * - * @note You MUST explicitly use p = pbuf_take(p); - * - * @note Only one packet is copied, no packet queue! - * - * @param p_to pbuf destination of the copy - * @param p_from pbuf source of the copy - * - * @return ERR_OK if pbuf was copied - * ERR_ARG if one of the pbufs is NULL or p_to is not big - * enough to hold p_from - */ -err_t -pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from) -{ - u16_t offset_to=0, offset_from=0, len; - - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", - (const void*)p_to, (const void*)p_from)); - - /* is the target big enough to hold the source? */ - LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && - (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); - - /* iterate through pbuf chain */ - do - { - /* copy one part of the original chain */ - if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { - /* complete current p_from fits into current p_to */ - len = p_from->len - offset_from; - } else { - /* current p_from does not fit into current p_to */ - len = p_to->len - offset_to; - } - MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len); - offset_to += len; - offset_from += len; - LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); - LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); - if (offset_from >= p_from->len) { - /* on to next p_from (if any) */ - offset_from = 0; - p_from = p_from->next; - } - if (offset_to == p_to->len) { - /* on to next p_to (if any) */ - offset_to = 0; - p_to = p_to->next; - LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL) , return ERR_ARG;); - } - - if ((p_from != NULL) && (p_from->len == p_from->tot_len)) { - /* don't copy more than one packet! */ - LWIP_ERROR("pbuf_copy() does not allow packet queues!", - (p_from->next == NULL), return ERR_VAL;); - } - if ((p_to != NULL) && (p_to->len == p_to->tot_len)) { - /* don't copy more than one packet! */ - LWIP_ERROR("pbuf_copy() does not allow packet queues!", - (p_to->next == NULL), return ERR_VAL;); - } - } while (p_from); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); - return ERR_OK; -} - -/** - * @ingroup pbuf - * Copy (part of) the contents of a packet buffer - * to an application supplied buffer. - * - * @param buf the pbuf from which to copy data - * @param dataptr the application supplied buffer - * @param len length of data to copy (dataptr must be big enough). No more - * than buf->tot_len will be copied, irrespective of len - * @param offset offset into the packet buffer from where to begin copying len bytes - * @return the number of bytes copied, or 0 on failure - */ -u16_t -pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) -{ - const struct pbuf *p; - u16_t left; - u16_t buf_copy_len; - u16_t copied_total = 0; - - LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); - LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); - - left = 0; - - if ((buf == NULL) || (dataptr == NULL)) { - return 0; - } - - /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ - for (p = buf; len != 0 && p != NULL; p = p->next) { - if ((offset != 0) && (offset >= p->len)) { - /* don't copy from this buffer -> on to the next */ - offset -= p->len; - } else { - /* copy from this buffer. maybe only partially. */ - buf_copy_len = p->len - offset; - if (buf_copy_len > len) { - buf_copy_len = len; - } - /* copy the necessary parts of the buffer */ - MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len); - copied_total += buf_copy_len; - left += buf_copy_len; - len -= buf_copy_len; - offset = 0; - } - } - return copied_total; -} - -#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE -/** - * This method modifies a 'pbuf chain', so that its total length is - * smaller than 64K. The remainder of the original pbuf chain is stored - * in *rest. - * This function never creates new pbufs, but splits an existing chain - * in two parts. The tot_len of the modified packet queue will likely be - * smaller than 64K. - * 'packet queues' are not supported by this function. - * - * @param p the pbuf queue to be split - * @param rest pointer to store the remainder (after the first 64K) - */ -void pbuf_split_64k(struct pbuf *p, struct pbuf **rest) -{ - *rest = NULL; - if ((p != NULL) && (p->next != NULL)) { - u16_t tot_len_front = p->len; - struct pbuf *i = p; - struct pbuf *r = p->next; - - /* continue until the total length (summed up as u16_t) overflows */ - while ((r != NULL) && ((u16_t)(tot_len_front + r->len) > tot_len_front)) { - tot_len_front += r->len; - i = r; - r = r->next; - } - /* i now points to last packet of the first segment. Set next - pointer to NULL */ - i->next = NULL; - - if (r != NULL) { - /* Update the tot_len field in the first part */ - for (i = p; i != NULL; i = i->next) { - i->tot_len -= r->tot_len; - LWIP_ASSERT("tot_len/len mismatch in last pbuf", - (i->next != NULL) || (i->tot_len == i->len)); - } - if (p->flags & PBUF_FLAG_TCP_FIN) { - r->flags |= PBUF_FLAG_TCP_FIN; - } - - /* tot_len field in rest does not need modifications */ - /* reference counters do not need modifications */ - *rest = r; - } - } -} -#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - -/* Actual implementation of pbuf_skip() but returning const pointer... */ -static const struct pbuf* -pbuf_skip_const(const struct pbuf* in, u16_t in_offset, u16_t* out_offset) -{ - u16_t offset_left = in_offset; - const struct pbuf* q = in; - - /* get the correct pbuf */ - while ((q != NULL) && (q->len <= offset_left)) { - offset_left -= q->len; - q = q->next; - } - if (out_offset != NULL) { - *out_offset = offset_left; - } - return q; -} - -/** - * @ingroup pbuf - * Skip a number of bytes at the start of a pbuf - * - * @param in input pbuf - * @param in_offset offset to skip - * @param out_offset resulting offset in the returned pbuf - * @return the pbuf in the queue where the offset is - */ -struct pbuf* -pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset) -{ - const struct pbuf* out = pbuf_skip_const(in, in_offset, out_offset); - return LWIP_CONST_CAST(struct pbuf*, out); -} - -/** - * @ingroup pbuf - * Copy application supplied data into a pbuf. - * This function can only be used to copy the equivalent of buf->tot_len data. - * - * @param buf pbuf to fill with data - * @param dataptr application supplied data buffer - * @param len length of the application supplied data buffer - * - * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough - */ -err_t -pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) -{ - struct pbuf *p; - u16_t buf_copy_len; - u16_t total_copy_len = len; - u16_t copied_total = 0; - - LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return ERR_ARG;); - LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return ERR_ARG;); - LWIP_ERROR("pbuf_take: buf not large enough", (buf->tot_len >= len), return ERR_MEM;); - - if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { - return ERR_ARG; - } - - /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ - for (p = buf; total_copy_len != 0; p = p->next) { - LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); - buf_copy_len = total_copy_len; - if (buf_copy_len > p->len) { - /* this pbuf cannot hold all remaining data */ - buf_copy_len = p->len; - } - /* copy the necessary parts of the buffer */ - MEMCPY(p->payload, &((const char*)dataptr)[copied_total], buf_copy_len); - total_copy_len -= buf_copy_len; - copied_total += buf_copy_len; - } - LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); - return ERR_OK; -} - -/** - * @ingroup pbuf - * Same as pbuf_take() but puts data at an offset - * - * @param buf pbuf to fill with data - * @param dataptr application supplied data buffer - * @param len length of the application supplied data buffer - * @param offset offset in pbuf where to copy dataptr to - * - * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough - */ -err_t -pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset) -{ - u16_t target_offset; - struct pbuf* q = pbuf_skip(buf, offset, &target_offset); - - /* return requested data if pbuf is OK */ - if ((q != NULL) && (q->tot_len >= target_offset + len)) { - u16_t remaining_len = len; - const u8_t* src_ptr = (const u8_t*)dataptr; - /* copy the part that goes into the first pbuf */ - u16_t first_copy_len = LWIP_MIN(q->len - target_offset, len); - MEMCPY(((u8_t*)q->payload) + target_offset, dataptr, first_copy_len); - remaining_len -= first_copy_len; - src_ptr += first_copy_len; - if (remaining_len > 0) { - return pbuf_take(q->next, src_ptr, remaining_len); - } - return ERR_OK; - } - return ERR_MEM; -} - -/** - * @ingroup pbuf - * Creates a single pbuf out of a queue of pbufs. - * - * @remark: Either the source pbuf 'p' is freed by this function or the original - * pbuf 'p' is returned, therefore the caller has to check the result! - * - * @param p the source pbuf - * @param layer pbuf_layer of the new pbuf - * - * @return a new, single pbuf (p->next is NULL) - * or the old pbuf if allocation fails - */ -struct pbuf* -pbuf_coalesce(struct pbuf *p, pbuf_layer layer) -{ - struct pbuf *q; - err_t err; - if (p->next == NULL) { - return p; - } - q = pbuf_alloc(layer, p->tot_len, PBUF_RAM); - if (q == NULL) { - /* @todo: what do we do now? */ - return p; - } - err = pbuf_copy(q, p); - LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ - LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); - pbuf_free(p); - return q; -} - -#if LWIP_CHECKSUM_ON_COPY -/** - * Copies data into a single pbuf (*not* into a pbuf queue!) and updates - * the checksum while copying - * - * @param p the pbuf to copy data into - * @param start_offset offset of p->payload where to copy the data to - * @param dataptr data to copy into the pbuf - * @param len length of data to copy into the pbuf - * @param chksum pointer to the checksum which is updated - * @return ERR_OK if successful, another error if the data does not fit - * within the (first) pbuf (no pbuf queues!) - */ -err_t -pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, - u16_t len, u16_t *chksum) -{ - u32_t acc; - u16_t copy_chksum; - char *dst_ptr; - LWIP_ASSERT("p != NULL", p != NULL); - LWIP_ASSERT("dataptr != NULL", dataptr != NULL); - LWIP_ASSERT("chksum != NULL", chksum != NULL); - LWIP_ASSERT("len != 0", len != 0); - - if ((start_offset >= p->len) || (start_offset + len > p->len)) { - return ERR_ARG; - } - - dst_ptr = ((char*)p->payload) + start_offset; - copy_chksum = LWIP_CHKSUM_COPY(dst_ptr, dataptr, len); - if ((start_offset & 1) != 0) { - copy_chksum = SWAP_BYTES_IN_WORD(copy_chksum); - } - acc = *chksum; - acc += copy_chksum; - *chksum = FOLD_U32T(acc); - return ERR_OK; -} -#endif /* LWIP_CHECKSUM_ON_COPY */ - -/** - * @ingroup pbuf - * Get one byte from the specified position in a pbuf - * WARNING: returns zero for offset >= p->tot_len - * - * @param p pbuf to parse - * @param offset offset into p of the byte to return - * @return byte at an offset into p OR ZERO IF 'offset' >= p->tot_len - */ -u8_t -pbuf_get_at(const struct pbuf* p, u16_t offset) -{ - int ret = pbuf_try_get_at(p, offset); - if (ret >= 0) { - return (u8_t)ret; - } - return 0; -} - -/** - * @ingroup pbuf - * Get one byte from the specified position in a pbuf - * - * @param p pbuf to parse - * @param offset offset into p of the byte to return - * @return byte at an offset into p [0..0xFF] OR negative if 'offset' >= p->tot_len - */ -int -pbuf_try_get_at(const struct pbuf* p, u16_t offset) -{ - u16_t q_idx; - const struct pbuf* q = pbuf_skip_const(p, offset, &q_idx); - - /* return requested data if pbuf is OK */ - if ((q != NULL) && (q->len > q_idx)) { - return ((u8_t*)q->payload)[q_idx]; - } - return -1; -} - -/** - * @ingroup pbuf - * Put one byte to the specified position in a pbuf - * WARNING: silently ignores offset >= p->tot_len - * - * @param p pbuf to fill - * @param offset offset into p of the byte to write - * @param data byte to write at an offset into p - */ -void -pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data) -{ - u16_t q_idx; - struct pbuf* q = pbuf_skip(p, offset, &q_idx); - - /* write requested data if pbuf is OK */ - if ((q != NULL) && (q->len > q_idx)) { - ((u8_t*)q->payload)[q_idx] = data; - } -} - -/** - * @ingroup pbuf - * Compare pbuf contents at specified offset with memory s2, both of length n - * - * @param p pbuf to compare - * @param offset offset into p at which to start comparing - * @param s2 buffer to compare - * @param n length of buffer to compare - * @return zero if equal, nonzero otherwise - * (0xffff if p is too short, diffoffset+1 otherwise) - */ -u16_t -pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n) -{ - u16_t start = offset; - const struct pbuf* q = p; - u16_t i; - - /* pbuf long enough to perform check? */ - if(p->tot_len < (offset + n)) { - return 0xffff; - } - - /* get the correct pbuf from chain. We know it succeeds because of p->tot_len check above. */ - while ((q != NULL) && (q->len <= start)) { - start -= q->len; - q = q->next; - } - - /* return requested data if pbuf is OK */ - for (i = 0; i < n; i++) { - /* We know pbuf_get_at() succeeds because of p->tot_len check above. */ - u8_t a = pbuf_get_at(q, start + i); - u8_t b = ((const u8_t*)s2)[i]; - if (a != b) { - return i+1; - } - } - return 0; -} - -/** - * @ingroup pbuf - * Find occurrence of mem (with length mem_len) in pbuf p, starting at offset - * start_offset. - * - * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as - * return value 'not found' - * @param mem search for the contents of this buffer - * @param mem_len length of 'mem' - * @param start_offset offset into p at which to start searching - * @return 0xFFFF if substr was not found in p or the index where it was found - */ -u16_t -pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset) -{ - u16_t i; - u16_t max = p->tot_len - mem_len; - if (p->tot_len >= mem_len + start_offset) { - for (i = start_offset; i <= max; i++) { - u16_t plus = pbuf_memcmp(p, i, mem, mem_len); - if (plus == 0) { - return i; - } - } - } - return 0xFFFF; -} - -/** - * Find occurrence of substr with length substr_len in pbuf p, start at offset - * start_offset - * WARNING: in contrast to strstr(), this one does not stop at the first \0 in - * the pbuf/source string! - * - * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as - * return value 'not found' - * @param substr string to search for in p, maximum length is 0xFFFE - * @return 0xFFFF if substr was not found in p or the index where it was found - */ -u16_t -pbuf_strstr(const struct pbuf* p, const char* substr) -{ - size_t substr_len; - if ((substr == NULL) || (substr[0] == 0) || (p->tot_len == 0xFFFF)) { - return 0xFFFF; - } - substr_len = strlen(substr); - if (substr_len >= 0xFFFF) { - return 0xFFFF; - } - return pbuf_memfind(p, substr, (u16_t)substr_len, 0); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/raw.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/raw.c deleted file mode 100644 index 80cf9ec64bc0b537755f1fa873163268764d5304..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/raw.c +++ /dev/null @@ -1,521 +0,0 @@ -/** - * @file - * Implementation of raw protocol PCBs for low-level handling of - * different types of protocols besides (or overriding) those - * already available in lwIP.\n - * See also @ref raw_raw - * - * @defgroup raw_raw RAW - * @ingroup callbackstyle_api - * Implementation of raw protocol PCBs for low-level handling of - * different types of protocols besides (or overriding) those - * already available in lwIP.\n - * @see @ref raw_api - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/raw.h" -#include "lwip/stats.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/inet_chksum.h" - -#include - -/** The list of RAW PCBs */ -static struct raw_pcb *raw_pcbs; - -static u8_t -raw_input_match(struct raw_pcb *pcb, u8_t broadcast) -{ - LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ - -#if LWIP_IPV4 && LWIP_IPV6 - /* Dual-stack: PCBs listening to any IP type also listen to any IP address */ - if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { -#if IP_SOF_BROADCAST_RECV - if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) { - return 0; - } -#endif /* IP_SOF_BROADCAST_RECV */ - return 1; - } -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - - /* Only need to check PCB if incoming IP version matches PCB IP version */ - if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { -#if LWIP_IPV4 - /* Special case: IPv4 broadcast: receive all broadcasts - * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ - if (broadcast != 0) { -#if IP_SOF_BROADCAST_RECV - if (ip_get_option(pcb, SOF_BROADCAST)) -#endif /* IP_SOF_BROADCAST_RECV */ - { - if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip))) { - return 1; - } - } - } else -#endif /* LWIP_IPV4 */ - /* Handle IPv4 and IPv6: catch all or exact match */ - if (ip_addr_isany(&pcb->local_ip) || - ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { - return 1; - } - } - - return 0; -} - -/** - * Determine if in incoming IP packet is covered by a RAW PCB - * and if so, pass it to a user-provided receive callback function. - * - * Given an incoming IP datagram (as a chain of pbufs) this function - * finds a corresponding RAW PCB and calls the corresponding receive - * callback function. - * - * @param p pbuf to be demultiplexed to a RAW PCB. - * @param inp network interface on which the datagram was received. - * @return - 1 if the packet has been eaten by a RAW PCB receive - * callback function. The caller MAY NOT not reference the - * packet any longer, and MAY NOT call pbuf_free(). - * @return - 0 if packet is not eaten (pbuf is still referenced by the - * caller). - * - */ -u8_t -raw_input(struct pbuf *p, struct netif *inp) -{ - struct raw_pcb *pcb, *prev; - s16_t proto; - u8_t eaten = 0; - u8_t broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); - - LWIP_UNUSED_ARG(inp); - -#if LWIP_IPV6 -#if LWIP_IPV4 - if (IP_HDR_GET_VERSION(p->payload) == 6) -#endif /* LWIP_IPV4 */ - { - struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload; - proto = IP6H_NEXTH(ip6hdr); - } -#if LWIP_IPV4 - else -#endif /* LWIP_IPV4 */ -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 - { - proto = IPH_PROTO((struct ip_hdr *)p->payload); - } -#endif /* LWIP_IPV4 */ - - prev = NULL; - pcb = raw_pcbs; - /* loop through all raw pcbs until the packet is eaten by one */ - /* this allows multiple pcbs to match against the packet by design */ - while ((eaten == 0) && (pcb != NULL)) { - if ((pcb->protocol == proto) && raw_input_match(pcb, broadcast)) { - /* receive callback function available? */ - if (pcb->recv != NULL) { -#ifndef LWIP_NOASSERT - void* old_payload = p->payload; -#endif - /* the receive callback function did not eat the packet? */ - eaten = pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr()); - if (eaten != 0) { - /* receive function ate the packet */ - p = NULL; - eaten = 1; - if (prev != NULL) { - /* move the pcb to the front of raw_pcbs so that is - found faster next time */ - prev->next = pcb->next; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - } else { - /* sanity-check that the receive callback did not alter the pbuf */ - LWIP_ASSERT("raw pcb recv callback altered pbuf payload pointer without eating packet", - p->payload == old_payload); - } - } - /* no receive callback function was set for this raw PCB */ - } - /* drop the packet */ - prev = pcb; - pcb = pcb->next; - } - return eaten; -} - -/** - * @ingroup raw_raw - * Bind a RAW PCB. - * - * @param pcb RAW PCB to be bound with a local address ipaddr. - * @param ipaddr local IP address to bind with. Use IP4_ADDR_ANY to - * bind to all local interfaces. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occurred. - * - ERR_USE. The specified IP address is already bound to by - * another RAW PCB. - * - * @see raw_disconnect() - */ -err_t -raw_bind(struct raw_pcb *pcb, const ip_addr_t *ipaddr) -{ - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); - return ERR_OK; -} - -/** - * @ingroup raw_raw - * Connect an RAW PCB. This function is required by upper layers - * of lwip. Using the raw api you could use raw_sendto() instead - * - * This will associate the RAW PCB with the remote address. - * - * @param pcb RAW PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * - * @return lwIP error code - * - * @see raw_disconnect() and raw_sendto() - */ -err_t -raw_connect(struct raw_pcb *pcb, const ip_addr_t *ipaddr) -{ - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); - return ERR_OK; -} - -/** - * @ingroup raw_raw - * Set the callback function for received packets that match the - * raw PCB's protocol and binding. - * - * The callback function MUST either - * - eat the packet by calling pbuf_free() and returning non-zero. The - * packet will not be passed to other raw PCBs or other protocol layers. - * - not free the packet, and return zero. The packet will be matched - * against further PCBs and/or forwarded to another protocol layers. - */ -void -raw_recv(struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * @ingroup raw_raw - * Send the raw IP packet to the given address. Note that actually you cannot - * modify the IP headers (this is inconsistent with the receive callback where - * you actually get the IP headers), you can only specify the IP payload here. - * It requires some more changes in lwIP. (there will be a raw_send() function - * then.) - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_sendto(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr) -{ - err_t err; - struct netif *netif; - const ip_addr_t *src_ip; - struct pbuf *q; /* q will be sent down the stack */ - s16_t header_size; - - if ((pcb == NULL) || (ipaddr == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr)) { - return ERR_VAL; - } - - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n")); - - header_size = ( -#if LWIP_IPV4 && LWIP_IPV6 - IP_IS_V6(ipaddr) ? IP6_HLEN : IP_HLEN); -#elif LWIP_IPV4 - IP_HLEN); -#else - IP6_HLEN); -#endif - - /* not enough space to add an IP header to first pbuf in given p chain? */ - if (pbuf_header(p, header_size)) { - /* allocate header in new pbuf */ - q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n")); - return ERR_MEM; - } - if (p->tot_len != 0) { - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - } - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* first pbuf q equals given pbuf */ - q = p; - if (pbuf_header(q, -header_size)) { - LWIP_ASSERT("Can't restore header we just removed!", 0); - return ERR_MEM; - } - } - - if(IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { - /* Don't call ip_route() with IP_ANY_TYPE */ - netif = ip_route(IP46_ADDR_ANY(IP_GET_TYPE(ipaddr)), ipaddr); - } else { - netif = ip_route(&pcb->local_ip, ipaddr); - } - - if (netif == NULL) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to ")); - ip_addr_debug_print(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ipaddr); - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_RTE; - } - -#if IP_SOF_BROADCAST - if (IP_IS_V4(ipaddr)) - { - /* broadcast filter? */ - if (!ip_get_option(pcb, SOF_BROADCAST) && ip_addr_isbroadcast(ipaddr, netif)) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_VAL; - } - } -#endif /* IP_SOF_BROADCAST */ - - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = ip_netif_get_local_ip(netif, ipaddr); -#if LWIP_IPV6 - if (src_ip == NULL) { - if (q != p) { - pbuf_free(q); - } - return ERR_RTE; - } -#endif /* LWIP_IPV6 */ - } else { - /* use RAW PCB local IP address as source address */ - src_ip = &pcb->local_ip; - } - -#if LWIP_IPV6 - /* If requested, based on the IPV6_CHECKSUM socket option per RFC3542, - compute the checksum and update the checksum in the payload. */ - if (IP_IS_V6(ipaddr) && pcb->chksum_reqd) { - u16_t chksum = ip6_chksum_pseudo(p, pcb->protocol, p->tot_len, ip_2_ip6(src_ip), ip_2_ip6(ipaddr)); - LWIP_ASSERT("Checksum must fit into first pbuf", p->len >= (pcb->chksum_offset + 2)); - SMEMCPY(((u8_t *)p->payload) + pcb->chksum_offset, &chksum, sizeof(u16_t)); - } -#endif - - NETIF_SET_HWADDRHINT(netif, &pcb->addr_hint); - err = ip_output_if(q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - - /* did we chain a header earlier? */ - if (q != p) { - /* free the header */ - pbuf_free(q); - } - return err; -} - -/** - * @ingroup raw_raw - * Send the raw IP packet to the address given by raw_connect() - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * - */ -err_t -raw_send(struct raw_pcb *pcb, struct pbuf *p) -{ - return raw_sendto(pcb, p, &pcb->remote_ip); -} - -/** - * @ingroup raw_raw - * Remove an RAW PCB. - * - * @param pcb RAW PCB to be removed. The PCB is removed from the list of - * RAW PCB's and the data structure is freed from memory. - * - * @see raw_new() - */ -void -raw_remove(struct raw_pcb *pcb) -{ - struct raw_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (raw_pcbs == pcb) { - /* make list start at 2nd pcb */ - raw_pcbs = raw_pcbs->next; - /* pcb not 1st in list */ - } else { - for (pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in raw_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - break; - } - } - } - memp_free(MEMP_RAW_PCB, pcb); -} - -/** - * @ingroup raw_raw - * Create a RAW PCB. - * - * @return The RAW PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) - * - * @see raw_remove() - */ -struct raw_pcb * -raw_new(u8_t proto) -{ - struct raw_pcb *pcb; - - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n")); - - pcb = (struct raw_pcb *)memp_malloc(MEMP_RAW_PCB); - /* could allocate RAW PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct raw_pcb)); - pcb->protocol = proto; - pcb->ttl = RAW_TTL; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - return pcb; -} - -/** - * @ingroup raw_raw - * Create a RAW PCB for specific IP type. - * - * @return The RAW PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @param type IP address type, see @ref lwip_ip_addr_type definitions. - * If you want to listen to IPv4 and IPv6 (dual-stack) packets, - * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. - * @param proto the protocol number (next header) of the IPv6 packet payload - * (e.g. IP6_NEXTH_ICMP6) - * - * @see raw_remove() - */ -struct raw_pcb * -raw_new_ip_type(u8_t type, u8_t proto) -{ - struct raw_pcb *pcb; - pcb = raw_new(proto); -#if LWIP_IPV4 && LWIP_IPV6 - if (pcb != NULL) { - IP_SET_TYPE_VAL(pcb->local_ip, type); - IP_SET_TYPE_VAL(pcb->remote_ip, type); - } -#else /* LWIP_IPV4 && LWIP_IPV6 */ - LWIP_UNUSED_ARG(type); -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - return pcb; -} - -/** This function is called from netif.c when address is changed - * - * @param old_addr IP address of the netif before change - * @param new_addr IP address of the netif after change - */ -void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr) -{ - struct raw_pcb* rpcb; - - if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { - for (rpcb = raw_pcbs; rpcb != NULL; rpcb = rpcb->next) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&rpcb->local_ip, old_addr)) { - /* The PCB is bound to the old ipaddr and - * is set to bound to the new one instead */ - ip_addr_copy(rpcb->local_ip, *new_addr); - } - } - } -} - -#endif /* LWIP_RAW */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/stats.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/stats.c deleted file mode 100644 index 893d199c0447ab3da36dd68318e1811c9a4957df..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/stats.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - * @file - * Statistics module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/debug.h" - -#include - -struct stats_ lwip_stats; - -void -stats_init(void) -{ -#ifdef LWIP_DEBUG -#if MEM_STATS - lwip_stats.mem.name = "MEM"; -#endif /* MEM_STATS */ -#endif /* LWIP_DEBUG */ -} - -#if LWIP_STATS_DISPLAY -void -stats_display_proto(struct stats_proto *proto, const char *name) -{ - LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); - LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); - LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); - LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); - LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); - LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); - LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); - LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); - LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); - LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); - LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); - LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); - LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); -} - -#if IGMP_STATS || MLD6_STATS -void -stats_display_igmp(struct stats_igmp *igmp, const char *name) -{ - LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); - LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", igmp->xmit)); - LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", igmp->recv)); - LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", igmp->drop)); - LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); - LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); - LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", igmp->memerr)); - LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", igmp->proterr)); - LWIP_PLATFORM_DIAG(("rx_v1: %"STAT_COUNTER_F"\n\t", igmp->rx_v1)); - LWIP_PLATFORM_DIAG(("rx_group: %"STAT_COUNTER_F"\n\t", igmp->rx_group)); - LWIP_PLATFORM_DIAG(("rx_general: %"STAT_COUNTER_F"\n\t", igmp->rx_general)); - LWIP_PLATFORM_DIAG(("rx_report: %"STAT_COUNTER_F"\n\t", igmp->rx_report)); - LWIP_PLATFORM_DIAG(("tx_join: %"STAT_COUNTER_F"\n\t", igmp->tx_join)); - LWIP_PLATFORM_DIAG(("tx_leave: %"STAT_COUNTER_F"\n\t", igmp->tx_leave)); - LWIP_PLATFORM_DIAG(("tx_report: %"STAT_COUNTER_F"\n", igmp->tx_report)); -} -#endif /* IGMP_STATS || MLD6_STATS */ - -#if MEM_STATS || MEMP_STATS -void -stats_display_mem(struct stats_mem *mem, const char *name) -{ - LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name)); - LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail)); - LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used)); - LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max)); - LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err)); -} - -#if MEMP_STATS -void -stats_display_memp(struct stats_mem *mem, int index) -{ - if (index < MEMP_MAX) { - stats_display_mem(mem, mem->name); - } -} -#endif /* MEMP_STATS */ -#endif /* MEM_STATS || MEMP_STATS */ - -#if SYS_STATS -void -stats_display_sys(struct stats_sys *sys) -{ - LWIP_PLATFORM_DIAG(("\nSYS\n\t")); - LWIP_PLATFORM_DIAG(("sem.used: %"U32_F"\n\t", (u32_t)sys->sem.used)); - LWIP_PLATFORM_DIAG(("sem.max: %"U32_F"\n\t", (u32_t)sys->sem.max)); - LWIP_PLATFORM_DIAG(("sem.err: %"U32_F"\n\t", (u32_t)sys->sem.err)); - LWIP_PLATFORM_DIAG(("mutex.used: %"U32_F"\n\t", (u32_t)sys->mutex.used)); - LWIP_PLATFORM_DIAG(("mutex.max: %"U32_F"\n\t", (u32_t)sys->mutex.max)); - LWIP_PLATFORM_DIAG(("mutex.err: %"U32_F"\n\t", (u32_t)sys->mutex.err)); - LWIP_PLATFORM_DIAG(("mbox.used: %"U32_F"\n\t", (u32_t)sys->mbox.used)); - LWIP_PLATFORM_DIAG(("mbox.max: %"U32_F"\n\t", (u32_t)sys->mbox.max)); - LWIP_PLATFORM_DIAG(("mbox.err: %"U32_F"\n", (u32_t)sys->mbox.err)); -} -#endif /* SYS_STATS */ - -void -stats_display(void) -{ - s16_t i; - - LINK_STATS_DISPLAY(); - ETHARP_STATS_DISPLAY(); - IPFRAG_STATS_DISPLAY(); - IP6_FRAG_STATS_DISPLAY(); - IP_STATS_DISPLAY(); - ND6_STATS_DISPLAY(); - IP6_STATS_DISPLAY(); - IGMP_STATS_DISPLAY(); - MLD6_STATS_DISPLAY(); - ICMP_STATS_DISPLAY(); - ICMP6_STATS_DISPLAY(); - UDP_STATS_DISPLAY(); - TCP_STATS_DISPLAY(); - MEM_STATS_DISPLAY(); - for (i = 0; i < MEMP_MAX; i++) { - MEMP_STATS_DISPLAY(i); - } - SYS_STATS_DISPLAY(); -} -#endif /* LWIP_STATS_DISPLAY */ - -#endif /* LWIP_STATS */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/sys.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/sys.c deleted file mode 100644 index 7059b4de5be9beef4c89e3f090c5f019a2deadcb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/sys.c +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * lwIP Operating System abstraction - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/** - * @defgroup sys_layer Porting (system abstraction layer) - * @ingroup lwip - * @verbinclude "sys_arch.txt" - * - * @defgroup sys_os OS abstraction layer - * @ingroup sys_layer - * No need to implement functions in this section in NO_SYS mode. - * - * @defgroup sys_sem Semaphores - * @ingroup sys_os - * - * @defgroup sys_mutex Mutexes - * @ingroup sys_os - * Mutexes are recommended to correctly handle priority inversion, - * especially if you use LWIP_CORE_LOCKING . - * - * @defgroup sys_mbox Mailboxes - * @ingroup sys_os - * - * @defgroup sys_time Time - * @ingroup sys_layer - * - * @defgroup sys_prot Critical sections - * @ingroup sys_layer - * Used to protect short regions of code against concurrent access. - * - Your system is a bare-metal system (probably with an RTOS) - * and interrupts are under your control: - * Implement this as LockInterrupts() / UnlockInterrupts() - * - Your system uses an RTOS with deferred interrupt handling from a - * worker thread: Implement as a global mutex or lock/unlock scheduler - * - Your system uses a high-level OS with e.g. POSIX signals: - * Implement as a global mutex - * - * @defgroup sys_misc Misc - * @ingroup sys_os - */ - -#include "lwip/opt.h" - -#include "lwip/sys.h" - -/* Most of the functions defined in sys.h must be implemented in the - * architecture-dependent file sys_arch.c */ - -#if !NO_SYS - -#ifndef sys_msleep -/** - * Sleep for some ms. Timeouts are NOT processed while sleeping. - * - * @param ms number of milliseconds to sleep - */ -void -sys_msleep(u32_t ms) -{ - if (ms > 0) { - sys_sem_t delaysem; - err_t err = sys_sem_new(&delaysem, 0); - if (err == ERR_OK) { - sys_arch_sem_wait(&delaysem, ms); - sys_sem_free(&delaysem); - } - } -} -#endif /* sys_msleep */ - -#endif /* !NO_SYS */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp.c deleted file mode 100644 index 0476a4acf340b320625628fcecdf130b1bd4cb7d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp.c +++ /dev/null @@ -1,2170 +0,0 @@ -/** - * @file - * Transmission Control Protocol for IP - * See also @ref tcp_raw - * - * @defgroup tcp_raw TCP - * @ingroup callbackstyle_api - * Transmission Control Protocol for IP\n - * @see @ref raw_api and @ref netconn - * - * Common functions for the TCP implementation, such as functinos - * for manipulating the data structures and the TCP timer functions. TCP functions - * related to input and output is found in tcp_in.c and tcp_out.c respectively.\n - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/tcp.h" -#include "lwip/priv/tcp_priv.h" -#include "lwip/debug.h" -#include "lwip/stats.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/nd6.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -#ifndef TCP_LOCAL_PORT_RANGE_START -/* From http://www.iana.org/assignments/port-numbers: - "The Dynamic and/or Private Ports are those from 49152 through 65535" */ -#define TCP_LOCAL_PORT_RANGE_START 0xc000 -#define TCP_LOCAL_PORT_RANGE_END 0xffff -#define TCP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & ~TCP_LOCAL_PORT_RANGE_START) + TCP_LOCAL_PORT_RANGE_START)) -#endif - -#if LWIP_TCP_KEEPALIVE -#define TCP_KEEP_DUR(pcb) ((pcb)->keep_cnt * (pcb)->keep_intvl) -#define TCP_KEEP_INTVL(pcb) ((pcb)->keep_intvl) -#else /* LWIP_TCP_KEEPALIVE */ -#define TCP_KEEP_DUR(pcb) TCP_MAXIDLE -#define TCP_KEEP_INTVL(pcb) TCP_KEEPINTVL_DEFAULT -#endif /* LWIP_TCP_KEEPALIVE */ - -/* As initial send MSS, we use TCP_MSS but limit it to 536. */ -#if TCP_MSS > 536 -#define INITIAL_MSS 536 -#else -#define INITIAL_MSS TCP_MSS -#endif - -static const char * const tcp_state_str[] = { - "CLOSED", - "LISTEN", - "SYN_SENT", - "SYN_RCVD", - "ESTABLISHED", - "FIN_WAIT_1", - "FIN_WAIT_2", - "CLOSE_WAIT", - "CLOSING", - "LAST_ACK", - "TIME_WAIT" -}; - -/* last local TCP port */ -static u16_t tcp_port = TCP_LOCAL_PORT_RANGE_START; - -/* Incremented every coarse grained timer shot (typically every 500 ms). */ -u32_t tcp_ticks; -static const u8_t tcp_backoff[13] = - { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; - /* Times per slowtmr hits */ -static const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 }; - -/* The TCP PCB lists. */ - -/** List of all TCP PCBs bound but not yet (connected || listening) */ -struct tcp_pcb *tcp_bound_pcbs; -/** List of all TCP PCBs in LISTEN state */ -union tcp_listen_pcbs_t tcp_listen_pcbs; -/** List of all TCP PCBs that are in a state in which - * they accept or send data. */ -struct tcp_pcb *tcp_active_pcbs; -/** List of all TCP PCBs in TIME-WAIT state */ -struct tcp_pcb *tcp_tw_pcbs; - -/** An array with all (non-temporary) PCB lists, mainly used for smaller code size */ -struct tcp_pcb ** const tcp_pcb_lists[] = {&tcp_listen_pcbs.pcbs, &tcp_bound_pcbs, - &tcp_active_pcbs, &tcp_tw_pcbs}; - -u8_t tcp_active_pcbs_changed; - -/** Timer counter to handle calling slow-timer from tcp_tmr() */ -static u8_t tcp_timer; -static u8_t tcp_timer_ctr; -static u16_t tcp_new_port(void); - -static err_t tcp_close_shutdown_fin(struct tcp_pcb *pcb); - -/** - * Initialize this module. - */ -void -tcp_init(void) -{ -#if LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS && defined(LWIP_RAND) - tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); - os_printf("tcp_port:%d\r\n", tcp_port); -#endif /* LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS && defined(LWIP_RAND) */ -} - -/** - * Called periodically to dispatch TCP timers. - */ -void -tcp_tmr(void) -{ - /* Call tcp_fasttmr() every 250 ms */ - tcp_fasttmr(); - - if (++tcp_timer & 1) { - /* Call tcp_slowtmr() every 500 ms, i.e., every other timer - tcp_tmr() is called. */ - tcp_slowtmr(); - } -} - -#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG -/** Called when a listen pcb is closed. Iterates one pcb list and removes the - * closed listener pcb from pcb->listener if matching. - */ -static void -tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb) -{ - struct tcp_pcb *pcb; - for (pcb = list; pcb != NULL; pcb = pcb->next) { - if (pcb->listener == lpcb) { - pcb->listener = NULL; - } - } -} -#endif - -/** Called when a listen pcb is closed. Iterates all pcb lists and removes the - * closed listener pcb from pcb->listener if matching. - */ -static void -tcp_listen_closed(struct tcp_pcb *pcb) -{ -#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG - size_t i; - LWIP_ASSERT("pcb != NULL", pcb != NULL); - LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN); - for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { - tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen*)pcb); - } -#endif - LWIP_UNUSED_ARG(pcb); -} - -#if TCP_LISTEN_BACKLOG -/** @ingroup tcp_raw - * Delay accepting a connection in respect to the listen backlog: - * the number of outstanding connections is increased until - * tcp_backlog_accepted() is called. - * - * ATTENTION: the caller is responsible for calling tcp_backlog_accepted() - * or else the backlog feature will get out of sync! - * - * @param pcb the connection pcb which is not fully accepted yet - */ -void -tcp_backlog_delayed(struct tcp_pcb* pcb) -{ - LWIP_ASSERT("pcb != NULL", pcb != NULL); - if ((pcb->flags & TF_BACKLOGPEND) == 0) { - if (pcb->listener != NULL) { - pcb->listener->accepts_pending++; - LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0); - pcb->flags |= TF_BACKLOGPEND; - } - } -} - -/** @ingroup tcp_raw - * A delayed-accept a connection is accepted (or closed/aborted): decreases - * the number of outstanding connections after calling tcp_backlog_delayed(). - * - * ATTENTION: the caller is responsible for calling tcp_backlog_accepted() - * or else the backlog feature will get out of sync! - * - * @param pcb the connection pcb which is now fully accepted (or closed/aborted) - */ -void -tcp_backlog_accepted(struct tcp_pcb* pcb) -{ - LWIP_ASSERT("pcb != NULL", pcb != NULL); - if ((pcb->flags & TF_BACKLOGPEND) != 0) { - if (pcb->listener != NULL) { - LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0); - pcb->listener->accepts_pending--; - pcb->flags &= ~TF_BACKLOGPEND; - } - } -} -#endif /* TCP_LISTEN_BACKLOG */ - -/** - * Closes the TX side of a connection held by the PCB. - * For tcp_close(), a RST is sent if the application didn't receive all data - * (tcp_recved() not called for all data passed to recv callback). - * - * Listening pcbs are freed and may not be referenced any more. - * Connection pcbs are freed if not yet connected and may not be referenced - * any more. If a connection is established (at least SYN received or in - * a closing state), the connection is closed, and put in a closing state. - * The pcb is then automatically freed in tcp_slowtmr(). It is therefore - * unsafe to reference it. - * - * @param pcb the tcp_pcb to close - * @return ERR_OK if connection has been closed - * another err_t if closing failed and pcb is not freed - */ -static err_t -tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) -{ - if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { - if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) { - /* Not all data received by application, send RST to tell the remote - side about this. */ - LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); - - /* don't call tcp_abort here: we must not deallocate the pcb since - that might not be expected when calling tcp_close */ - tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, - pcb->local_port, pcb->remote_port); - - tcp_pcb_purge(pcb); - TCP_RMV_ACTIVE(pcb); - if (pcb->state == ESTABLISHED) { - /* move to TIME_WAIT since we close actively */ - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } else { - /* CLOSE_WAIT: deallocate the pcb since we already sent a RST for it */ - if (tcp_input_pcb == pcb) { - /* prevent using a deallocated pcb: free it from tcp_input later */ - tcp_trigger_input_pcb_close(); - } else { - memp_free(MEMP_TCP_PCB, pcb); - } - } - return ERR_OK; - } - } - - /* - states which free the pcb are handled here, - - states which send FIN and change state are handled in tcp_close_shutdown_fin() */ - switch (pcb->state) { - case CLOSED: - /* Closing a pcb in the CLOSED state might seem erroneous, - * however, it is in this state once allocated and as yet unused - * and the user needs some way to free it should the need arise. - * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) - * or for a pcb that has been used and then entered the CLOSED state - * is erroneous, but this should never happen as the pcb has in those cases - * been freed, and so any remaining handles are bogus. */ - if (pcb->local_port != 0) { - TCP_RMV(&tcp_bound_pcbs, pcb); - } - memp_free(MEMP_TCP_PCB, pcb); - break; - case LISTEN: - tcp_listen_closed(pcb); - tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); - memp_free(MEMP_TCP_PCB_LISTEN, pcb); - break; - case SYN_SENT: - TCP_PCB_REMOVE_ACTIVE(pcb); - memp_free(MEMP_TCP_PCB, pcb); - MIB2_STATS_INC(mib2.tcpattemptfails); - break; - default: - return tcp_close_shutdown_fin(pcb); - } - return ERR_OK; -} - -static err_t -tcp_close_shutdown_fin(struct tcp_pcb *pcb) -{ - err_t err; - LWIP_ASSERT("pcb != NULL", pcb != NULL); - - switch (pcb->state) { - case SYN_RCVD: - err = tcp_send_fin(pcb); - if (err == ERR_OK) { - tcp_backlog_accepted(pcb); - MIB2_STATS_INC(mib2.tcpattemptfails); - pcb->state = FIN_WAIT_1; - } - break; - case ESTABLISHED: - err = tcp_send_fin(pcb); - if (err == ERR_OK) { - MIB2_STATS_INC(mib2.tcpestabresets); - pcb->state = FIN_WAIT_1; - } - break; - case CLOSE_WAIT: - err = tcp_send_fin(pcb); - if (err == ERR_OK) { - MIB2_STATS_INC(mib2.tcpestabresets); - pcb->state = LAST_ACK; - } - break; - default: - /* Has already been closed, do nothing. */ - return ERR_OK; - break; - } - - if (err == ERR_OK) { - /* To ensure all data has been sent when tcp_close returns, we have - to make sure tcp_output doesn't fail. - Since we don't really have to ensure all data has been sent when tcp_close - returns (unsent data is sent from tcp timer functions, also), we don't care - for the return value of tcp_output for now. */ - tcp_output(pcb); - } else if (err == ERR_MEM) { - /* Mark this pcb for closing. Closing is retried from tcp_tmr. */ - pcb->flags |= TF_CLOSEPEND; - } - return err; -} - -/** - * @ingroup tcp_raw - * Closes the connection held by the PCB. - * - * Listening pcbs are freed and may not be referenced any more. - * Connection pcbs are freed if not yet connected and may not be referenced - * any more. If a connection is established (at least SYN received or in - * a closing state), the connection is closed, and put in a closing state. - * The pcb is then automatically freed in tcp_slowtmr(). It is therefore - * unsafe to reference it (unless an error is returned). - * - * @param pcb the tcp_pcb to close - * @return ERR_OK if connection has been closed - * another err_t if closing failed and pcb is not freed - */ -err_t -tcp_close(struct tcp_pcb *pcb) -{ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); - tcp_debug_print_state(pcb->state); - - if (pcb->state != LISTEN) { - /* Set a flag not to receive any more data... */ - pcb->flags |= TF_RXCLOSED; - } - /* ... and close */ - return tcp_close_shutdown(pcb, 1); -} - -/** - * @ingroup tcp_raw - * Causes all or part of a full-duplex connection of this PCB to be shut down. - * This doesn't deallocate the PCB unless shutting down both sides! - * Shutting down both sides is the same as calling tcp_close, so if it succeds, - * the PCB should not be referenced any more. - * - * @param pcb PCB to shutdown - * @param shut_rx shut down receive side if this is != 0 - * @param shut_tx shut down send side if this is != 0 - * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down) - * another err_t on error. - */ -err_t -tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx) -{ - if (pcb->state == LISTEN) { - return ERR_CONN; - } - if (shut_rx) { - /* shut down the receive side: set a flag not to receive any more data... */ - pcb->flags |= TF_RXCLOSED; - if (shut_tx) { - /* shutting down the tx AND rx side is the same as closing for the raw API */ - return tcp_close_shutdown(pcb, 1); - } - /* ... and free buffered data */ - if (pcb->refused_data != NULL) { - pbuf_free(pcb->refused_data); - pcb->refused_data = NULL; - } - } - if (shut_tx) { - /* This can't happen twice since if it succeeds, the pcb's state is changed. - Only close in these states as the others directly deallocate the PCB */ - switch (pcb->state) { - case SYN_RCVD: - case ESTABLISHED: - case CLOSE_WAIT: - return tcp_close_shutdown(pcb, (u8_t)shut_rx); - default: - /* Not (yet?) connected, cannot shutdown the TX side as that would bring us - into CLOSED state, where the PCB is deallocated. */ - return ERR_CONN; - } - } - return ERR_OK; -} - -/** - * Abandons a connection and optionally sends a RST to the remote - * host. Deletes the local protocol control block. This is done when - * a connection is killed because of shortage of memory. - * - * @param pcb the tcp_pcb to abort - * @param reset boolean to indicate whether a reset should be sent - */ -void -tcp_abandon(struct tcp_pcb *pcb, int reset) -{ - u32_t seqno, ackno; -#if LWIP_CALLBACK_API - tcp_err_fn errf; -#endif /* LWIP_CALLBACK_API */ - void *errf_arg; - - /* pcb->state LISTEN not allowed here */ - LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", - pcb->state != LISTEN); - /* Figure out on which TCP PCB list we are, and remove us. If we - are in an active state, call the receive function associated with - the PCB with a NULL argument, and send an RST to the remote end. */ - if (pcb->state == TIME_WAIT) { - tcp_pcb_remove(&tcp_tw_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - int send_rst = 0; - u16_t local_port = 0; - enum tcp_state last_state; - seqno = pcb->snd_nxt; - ackno = pcb->rcv_nxt; -#if LWIP_CALLBACK_API - errf = pcb->errf; -#endif /* LWIP_CALLBACK_API */ - errf_arg = pcb->callback_arg; - if (pcb->state == CLOSED) { - if (pcb->local_port != 0) { - /* bound, not yet opened */ - TCP_RMV(&tcp_bound_pcbs, pcb); - } - } else { - send_rst = reset; - local_port = pcb->local_port; - TCP_PCB_REMOVE_ACTIVE(pcb); - } - if (pcb->unacked != NULL) { - tcp_segs_free(pcb->unacked); - } - if (pcb->unsent != NULL) { - tcp_segs_free(pcb->unsent); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - tcp_segs_free(pcb->ooseq); - } -#endif /* TCP_QUEUE_OOSEQ */ - tcp_backlog_accepted(pcb); - if (send_rst) { - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); - tcp_rst(seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port); - } - last_state = pcb->state; - memp_free(MEMP_TCP_PCB, pcb); - TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT); - } -} - -/** - * @ingroup tcp_raw - * Aborts the connection by sending a RST (reset) segment to the remote - * host. The pcb is deallocated. This function never fails. - * - * ATTENTION: When calling this from one of the TCP callbacks, make - * sure you always return ERR_ABRT (and never return ERR_ABRT otherwise - * or you will risk accessing deallocated memory or memory leaks! - * - * @param pcb the tcp pcb to abort - */ -void -tcp_abort(struct tcp_pcb *pcb) -{ - tcp_abandon(pcb, 1); -} - -/** - * @ingroup tcp_raw - * Binds the connection to a local port number and IP address. If the - * IP address is not given (i.e., ipaddr == NULL), the IP address of - * the outgoing network interface is used instead. - * - * @param pcb the tcp_pcb to bind (no check is done whether this pcb is - * already bound!) - * @param ipaddr the local ip address to bind to (use IP4_ADDR_ANY to bind - * to any local address - * @param port the local port to bind to - * @return ERR_USE if the port is already in use - * ERR_VAL if bind failed because the PCB is not in a valid state - * ERR_OK if bound - */ -err_t -tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) -{ - int i; - int max_pcb_list = NUM_TCP_PCB_LISTS; - struct tcp_pcb *cpcb; - -#if LWIP_IPV4 - /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ - if (ipaddr == NULL) { - ipaddr = IP4_ADDR_ANY; - } -#endif /* LWIP_IPV4 */ - - /* still need to check for ipaddr == NULL in IPv6 only case */ - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - - LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL); - -#if SO_REUSE - /* Unless the REUSEADDR flag is set, - we have to check the pcbs in TIME-WAIT state, also. - We do not dump TIME_WAIT pcb's; they can still be matched by incoming - packets using both local and remote IP addresses and ports to distinguish. - */ - if (ip_get_option(pcb, SOF_REUSEADDR)) { - max_pcb_list = NUM_TCP_PCB_LISTS_NO_TIME_WAIT; - } -#endif /* SO_REUSE */ - - if (port == 0) { - port = tcp_new_port(); - if (port == 0) { - return ERR_BUF; - } - } else { - /* Check if the address already is in use (on all lists) */ - for (i = 0; i < max_pcb_list; i++) { - for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { -#if SO_REUSE - /* Omit checking for the same port if both pcbs have REUSEADDR set. - For SO_REUSEADDR, the duplicate-check for a 5-tuple is done in - tcp_connect. */ - if (!ip_get_option(pcb, SOF_REUSEADDR) || - !ip_get_option(cpcb, SOF_REUSEADDR)) -#endif /* SO_REUSE */ - { - /* @todo: check accept_any_ip_version */ - if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) && - (ip_addr_isany(&cpcb->local_ip) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&cpcb->local_ip, ipaddr))) { - return ERR_USE; - } - } - } - } - } - } - - if (!ip_addr_isany(ipaddr)) { - ip_addr_set(&pcb->local_ip, ipaddr); - } - pcb->local_port = port; - TCP_REG(&tcp_bound_pcbs, pcb); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); - return ERR_OK; -} -#if LWIP_CALLBACK_API -/** - * Default accept callback if no accept callback is specified by the user. - */ -static err_t -tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) -{ - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(err); - - tcp_abort(pcb); - - return ERR_ABRT; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * @ingroup tcp_raw - * Set the state of the connection to be LISTEN, which means that it - * is able to accept incoming connections. The protocol control block - * is reallocated in order to consume less memory. Setting the - * connection to LISTEN is an irreversible process. - * - * @param pcb the original tcp_pcb - * @param backlog the incoming connections queue limit - * @return tcp_pcb used for listening, consumes less memory. - * - * @note The original tcp_pcb is freed. This function therefore has to be - * called like this: - * tpcb = tcp_listen_with_backlog(tpcb, backlog); - */ -struct tcp_pcb * -tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) -{ - return tcp_listen_with_backlog_and_err(pcb, backlog, NULL); -} - -/** - * @ingroup tcp_raw - * Set the state of the connection to be LISTEN, which means that it - * is able to accept incoming connections. The protocol control block - * is reallocated in order to consume less memory. Setting the - * connection to LISTEN is an irreversible process. - * - * @param pcb the original tcp_pcb - * @param backlog the incoming connections queue limit - * @param err when NULL is returned, this contains the error reason - * @return tcp_pcb used for listening, consumes less memory. - * - * @note The original tcp_pcb is freed. This function therefore has to be - * called like this: - * tpcb = tcp_listen_with_backlog_and_err(tpcb, backlog, &err); - */ -struct tcp_pcb * -tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err) -{ - struct tcp_pcb_listen *lpcb = NULL; - err_t res; - - LWIP_UNUSED_ARG(backlog); - LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, res = ERR_CLSD; goto done); - - /* already listening? */ - if (pcb->state == LISTEN) { - lpcb = (struct tcp_pcb_listen*)pcb; - res = ERR_ALREADY; - goto done; - } -#if SO_REUSE - if (ip_get_option(pcb, SOF_REUSEADDR)) { - /* Since SOF_REUSEADDR allows reusing a local address before the pcb's usage - is declared (listen-/connection-pcb), we have to make sure now that - this port is only used once for every local IP. */ - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if ((lpcb->local_port == pcb->local_port) && - ip_addr_cmp(&lpcb->local_ip, &pcb->local_ip)) { - /* this address/port is already used */ - lpcb = NULL; - res = ERR_USE; - goto done; - } - } - } -#endif /* SO_REUSE */ - lpcb = (struct tcp_pcb_listen *)memp_malloc(MEMP_TCP_PCB_LISTEN); - if (lpcb == NULL) { - res = ERR_MEM; - goto done; - } - lpcb->callback_arg = pcb->callback_arg; - lpcb->local_port = pcb->local_port; - lpcb->state = LISTEN; - lpcb->prio = pcb->prio; - lpcb->so_options = pcb->so_options; - lpcb->ttl = pcb->ttl; - lpcb->tos = pcb->tos; -#if LWIP_IPV4 && LWIP_IPV6 - IP_SET_TYPE_VAL(lpcb->remote_ip, pcb->local_ip.type); -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - ip_addr_copy(lpcb->local_ip, pcb->local_ip); - if (pcb->local_port != 0) { - TCP_RMV(&tcp_bound_pcbs, pcb); - } - memp_free(MEMP_TCP_PCB, pcb); -#if LWIP_CALLBACK_API - lpcb->accept = tcp_accept_null; -#endif /* LWIP_CALLBACK_API */ -#if TCP_LISTEN_BACKLOG - lpcb->accepts_pending = 0; - tcp_backlog_set(lpcb, backlog); -#endif /* TCP_LISTEN_BACKLOG */ - TCP_REG(&tcp_listen_pcbs.pcbs, (struct tcp_pcb *)lpcb); - res = ERR_OK; -done: - if (err != NULL) { - *err = res; - } - return (struct tcp_pcb *)lpcb; -} - -/** - * Update the state that tracks the available window space to advertise. - * - * Returns how much extra window would be advertised if we sent an - * update now. - */ -u32_t -tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) -{ - u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; - - if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { - /* we can advertise more window */ - pcb->rcv_ann_wnd = pcb->rcv_wnd; - return new_right_edge - pcb->rcv_ann_right_edge; - } else { - if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { - /* Can happen due to other end sending out of advertised window, - * but within actual available (but not yet advertised) window */ - pcb->rcv_ann_wnd = 0; - } else { - /* keep the right edge of window constant */ - u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; -#if !LWIP_WND_SCALE - LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); -#endif - pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd; - } - return 0; - } -} - -/** - * @ingroup tcp_raw - * This function should be called by the application when it has - * processed the data. The purpose is to advertise a larger window - * when the data has been processed. - * - * @param pcb the tcp_pcb for which data is read - * @param len the amount of bytes that have been read by the application - */ -void -tcp_recved(struct tcp_pcb *pcb, u16_t len) -{ - int wnd_inflation; - - /* pcb->state LISTEN not allowed here */ - LWIP_ASSERT("don't call tcp_recved for listen-pcbs", - pcb->state != LISTEN); - - pcb->rcv_wnd += len; - if (pcb->rcv_wnd > TCP_WND_MAX(pcb)) { - pcb->rcv_wnd = TCP_WND_MAX(pcb); - } else if (pcb->rcv_wnd == 0) { - /* rcv_wnd overflowed */ - if ((pcb->state == CLOSE_WAIT) || (pcb->state == LAST_ACK)) { - /* In passive close, we allow this, since the FIN bit is added to rcv_wnd - by the stack itself, since it is not mandatory for an application - to call tcp_recved() for the FIN bit, but e.g. the netconn API does so. */ - pcb->rcv_wnd = TCP_WND_MAX(pcb); - } else { - LWIP_ASSERT("tcp_recved: len wrapped rcv_wnd\n", 0); - } - } - - wnd_inflation = tcp_update_rcv_ann_wnd(pcb); - - /* If the change in the right edge of window is significant (default - * watermark is TCP_WND/4), then send an explicit update now. - * Otherwise wait for a packet to be sent in the normal course of - * events (or more window to be available later) */ - if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { - tcp_ack_now(pcb); - tcp_output(pcb); - } - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n", - len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd))); -} - -/** - * Allocate a new local TCP port. - * - * @return a new (free) local TCP port number - */ -static u16_t -tcp_new_port(void) -{ - u8_t i; - u16_t n = 0; - struct tcp_pcb *pcb; - -again: - if (tcp_port++ == TCP_LOCAL_PORT_RANGE_END) { - tcp_port = TCP_LOCAL_PORT_RANGE_START; - } - /* Check all PCB lists. */ - for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { - for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == tcp_port) { - if (++n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) { - return 0; - } - goto again; - } - } - } - return tcp_port; -} - -/** - * @ingroup tcp_raw - * Connects to another host. The function given as the "connected" - * argument will be called when the connection has been established. - * - * @param pcb the tcp_pcb used to establish the connection - * @param ipaddr the remote ip address to connect to - * @param port the remote tcp port to connect to - * @param connected callback function to call when connected (on error, - the err calback will be called) - * @return ERR_VAL if invalid arguments are given - * ERR_OK if connect request has been sent - * other err_t values if connect request couldn't be sent - */ -err_t -tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port, - tcp_connected_fn connected) -{ - err_t ret; - u32_t iss; - u16_t old_local_port; - - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - - LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); - ip_addr_set(&pcb->remote_ip, ipaddr); - pcb->remote_port = port; - - /* check if we have a route to the remote host */ - if (ip_addr_isany(&pcb->local_ip)) { - /* no local IP address set, yet. */ - struct netif *netif; - const ip_addr_t *local_ip; - ip_route_get_local_ip(&pcb->local_ip, &pcb->remote_ip, netif, local_ip); - if ((netif == NULL) || (local_ip == NULL)) { - /* Don't even try to send a SYN packet if we have no route - since that will fail. */ - return ERR_RTE; - } - /* Use the address as local address of the pcb. */ - ip_addr_copy(pcb->local_ip, *local_ip); - } - - old_local_port = pcb->local_port; - if (pcb->local_port == 0) { - pcb->local_port = tcp_new_port(); - if (pcb->local_port == 0) { - return ERR_BUF; - } - } else { -#if SO_REUSE - if (ip_get_option(pcb, SOF_REUSEADDR)) { - /* Since SOF_REUSEADDR allows reusing a local address, we have to make sure - now that the 5-tuple is unique. */ - struct tcp_pcb *cpcb; - int i; - /* Don't check listen- and bound-PCBs, check active- and TIME-WAIT PCBs. */ - for (i = 2; i < NUM_TCP_PCB_LISTS; i++) { - for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { - if ((cpcb->local_port == pcb->local_port) && - (cpcb->remote_port == port) && - ip_addr_cmp(&cpcb->local_ip, &pcb->local_ip) && - ip_addr_cmp(&cpcb->remote_ip, ipaddr)) { - /* linux returns EISCONN here, but ERR_USE should be OK for us */ - return ERR_USE; - } - } - } - } -#endif /* SO_REUSE */ - } - - iss = tcp_next_iss(pcb); - pcb->rcv_nxt = 0; - pcb->snd_nxt = iss; - pcb->lastack = iss - 1; - pcb->snd_wl2 = iss - 1; - pcb->snd_lbb = iss - 1; - /* Start with a window that does not need scaling. When window scaling is - enabled and used, the window is enlarged when both sides agree on scaling. */ - pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); - pcb->rcv_ann_right_edge = pcb->rcv_nxt; - pcb->snd_wnd = TCP_WND; - /* As initial send MSS, we use TCP_MSS but limit it to 536. - The send MSS is updated when an MSS option is received. */ - pcb->mss = INITIAL_MSS; -#if TCP_CALCULATE_EFF_SEND_MSS - pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - pcb->cwnd = 1; -#if LWIP_CALLBACK_API - pcb->connected = connected; -#else /* LWIP_CALLBACK_API */ - LWIP_UNUSED_ARG(connected); -#endif /* LWIP_CALLBACK_API */ - - /* Send a SYN together with the MSS option. */ - ret = tcp_enqueue_flags(pcb, TCP_SYN); - if (ret == ERR_OK) { - /* SYN segment was enqueued, changed the pcbs state now */ - pcb->state = SYN_SENT; - if (old_local_port != 0) { - TCP_RMV(&tcp_bound_pcbs, pcb); - } - TCP_REG_ACTIVE(pcb); - MIB2_STATS_INC(mib2.tcpactiveopens); - - tcp_output(pcb); - } - return ret; -} - -/** - * Called every 500 ms and implements the retransmission timer and the timer that - * removes PCBs that have been in TIME-WAIT for enough time. It also increments - * various timers such as the inactivity timer in each PCB. - * - * Automatically called from tcp_tmr(). - */ -void -tcp_slowtmr(void) -{ - struct tcp_pcb *pcb, *prev; - tcpwnd_size_t eff_wnd; - u8_t pcb_remove; /* flag if a PCB should be removed */ - u8_t pcb_reset; /* flag if a RST should be sent when removing */ - err_t err; - - err = ERR_OK; - - ++tcp_ticks; - ++tcp_timer_ctr; - -tcp_slowtmr_start: - /* Steps through all of the active PCBs. */ - prev = NULL; - pcb = tcp_active_pcbs; - if (pcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); - } - while (pcb != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); - if (pcb->last_timer == tcp_timer_ctr) { - /* skip this pcb, we have already processed it */ - pcb = pcb->next; - continue; - } - pcb->last_timer = tcp_timer_ctr; - - pcb_remove = 0; - pcb_reset = 0; - - if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); - } - else if (pcb->nrtx >= TCP_MAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); - } else { - if (pcb->persist_backoff > 0) { - /* If snd_wnd is zero, use persist timer to send 1 byte probes - * instead of using the standard retransmission mechanism. */ - u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff-1]; - if (pcb->persist_cnt < backoff_cnt) { - pcb->persist_cnt++; - } - if (pcb->persist_cnt >= backoff_cnt) { - if (tcp_zero_window_probe(pcb) == ERR_OK) { - pcb->persist_cnt = 0; - if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { - pcb->persist_backoff++; - } - } - } - } else { - /* Increase the retransmission timer if it is running */ - if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) { - ++pcb->rtime; - } - - if (pcb->rtime >= pcb->rto) { - /* Time for a retransmission. */ - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F - " pcb->rto %"S16_F"\n", - pcb->rtime, pcb->rto)); - /* If prepare phase fails but we have unsent data but no unacked data, - still execute the backoff calculations below, as this means we somehow - failed to send segment. */ - if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) { - /* Double retransmission time-out unless we are trying to - * connect to somebody (i.e., we are in SYN_SENT). */ - if (pcb->state != SYN_SENT) { - u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1); - int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx]; - pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF); - } - - /* Reset the retransmission timer. */ - pcb->rtime = 0; - - /* Reduce congestion window and ssthresh. */ - eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); - pcb->ssthresh = eff_wnd >> 1; - if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) { - pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1); - } - pcb->cwnd = pcb->mss; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F - " ssthresh %"TCPWNDSIZE_F"\n", - pcb->cwnd, pcb->ssthresh)); - - /* The following needs to be called AFTER cwnd is set to one - mss - STJ */ - tcp_rexmit_rto_commit(pcb); - } - } - } - } - /* Check if this PCB has stayed too long in FIN-WAIT-2 */ - if (pcb->state == FIN_WAIT_2) { - /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */ - if (pcb->flags & TF_RXCLOSED) { - /* PCB was fully closed (either through close() or SHUT_RDWR): - normal FIN-WAIT timeout handling. */ - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); - } - } - } - - /* Check if KEEPALIVE should be sent */ - if (ip_get_option(pcb, SOF_KEEPALIVE) && - ((pcb->state == ESTABLISHED) || - (pcb->state == CLOSE_WAIT))) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) - { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to ")); - ip_addr_debug_print(TCP_DEBUG, &pcb->remote_ip); - LWIP_DEBUGF(TCP_DEBUG, ("\n")); - - ++pcb_remove; - ++pcb_reset; - } else if ((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb)) - / TCP_SLOW_INTERVAL) - { - err = tcp_keepalive(pcb); - if (err == ERR_OK) { - pcb->keep_cnt_sent++; - } - } - } - - /* If this PCB has queued out of sequence data, but has been - inactive for too long, will drop the data (it will eventually - be retransmitted). */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) { - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); - } -#endif /* TCP_QUEUE_OOSEQ */ - - /* Check if this PCB has stayed too long in SYN-RCVD */ - if (pcb->state == SYN_RCVD) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); - } - } - - /* Check if this PCB has stayed too long in LAST-ACK */ - if (pcb->state == LAST_ACK) { - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); - } - } - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - struct tcp_pcb *pcb2; -#if LWIP_CALLBACK_API - tcp_err_fn err_fn = pcb->errf; -#endif /* LWIP_CALLBACK_API */ - void *err_arg; - enum tcp_state last_state; - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_active_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); - tcp_active_pcbs = pcb->next; - } - - if (pcb_reset) { - tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, - pcb->local_port, pcb->remote_port); - } - - err_arg = pcb->callback_arg; - last_state = pcb->state; - pcb2 = pcb; - pcb = pcb->next; - memp_free(MEMP_TCP_PCB, pcb2); - - tcp_active_pcbs_changed = 0; - TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT); - if (tcp_active_pcbs_changed) { - goto tcp_slowtmr_start; - } - } else { - /* get the 'next' element now and work with 'prev' below (in case of abort) */ - prev = pcb; - pcb = pcb->next; - - /* We check if we should poll the connection. */ - ++prev->polltmr; - if (prev->polltmr >= prev->pollinterval) { - prev->polltmr = 0; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); - tcp_active_pcbs_changed = 0; - TCP_EVENT_POLL(prev, err); - if (tcp_active_pcbs_changed) { - goto tcp_slowtmr_start; - } - /* if err == ERR_ABRT, 'prev' is already deallocated */ - if (err == ERR_OK) { - tcp_output(prev); - } - } - } - } - - - /* Steps through all of the TIME-WAIT PCBs. */ - prev = NULL; - pcb = tcp_tw_pcbs; - while (pcb != NULL) { - LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - pcb_remove = 0; - - /* Check if this PCB has stayed long enough in TIME-WAIT */ - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - } - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - struct tcp_pcb *pcb2; - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_tw_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); - tcp_tw_pcbs = pcb->next; - } - pcb2 = pcb; - pcb = pcb->next; - memp_free(MEMP_TCP_PCB, pcb2); - } else { - prev = pcb; - pcb = pcb->next; - } - } -} - -/** - * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously - * "refused" by upper layer (application) and sends delayed ACKs. - * - * Automatically called from tcp_tmr(). - */ -void -tcp_fasttmr(void) -{ - struct tcp_pcb *pcb; - - ++tcp_timer_ctr; - -tcp_fasttmr_start: - pcb = tcp_active_pcbs; - - while (pcb != NULL) { - if (pcb->last_timer != tcp_timer_ctr) { - struct tcp_pcb *next; - pcb->last_timer = tcp_timer_ctr; - /* send delayed ACKs */ - if (pcb->flags & TF_ACK_DELAY) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); - tcp_ack_now(pcb); - tcp_output(pcb); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - /* send pending FIN */ - if (pcb->flags & TF_CLOSEPEND) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n")); - pcb->flags &= ~(TF_CLOSEPEND); - tcp_close_shutdown_fin(pcb); - } - - next = pcb->next; - - /* If there is data which was previously "refused" by upper layer */ - if (pcb->refused_data != NULL) { - tcp_active_pcbs_changed = 0; - tcp_process_refused_data(pcb); - if (tcp_active_pcbs_changed) { - /* application callback has changed the pcb list: restart the loop */ - goto tcp_fasttmr_start; - } - } - pcb = next; - } else { - pcb = pcb->next; - } - } -} - -/** Call tcp_output for all active pcbs that have TF_NAGLEMEMERR set */ -void -tcp_txnow(void) -{ - struct tcp_pcb *pcb; - - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->flags & TF_NAGLEMEMERR) { - tcp_output(pcb); - } - } -} - -/** Pass pcb->refused_data to the recv callback */ -err_t -tcp_process_refused_data(struct tcp_pcb *pcb) -{ -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - struct pbuf *rest; - while (pcb->refused_data != NULL) -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - { - err_t err; - u8_t refused_flags = pcb->refused_data->flags; - /* set pcb->refused_data to NULL in case the callback frees it and then - closes the pcb */ - struct pbuf *refused_data = pcb->refused_data; -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - pbuf_split_64k(refused_data, &rest); - pcb->refused_data = rest; -#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - pcb->refused_data = NULL; -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - /* Notify again application with data previously received. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); - TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err); - if (err == ERR_OK) { - /* did refused_data include a FIN? */ - if (refused_flags & PBUF_FLAG_TCP_FIN -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - && (rest == NULL) -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - ) { - /* correct rcv_wnd as the application won't call tcp_recved() - for the FIN's seqno */ - if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { - pcb->rcv_wnd++; - } - TCP_EVENT_CLOSED(pcb, err); - if (err == ERR_ABRT) { - return ERR_ABRT; - } - } - } else if (err == ERR_ABRT) { - /* if err == ERR_ABRT, 'pcb' is already deallocated */ - /* Drop incoming packets because pcb is "full" (only if the incoming - segment contains data). */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); - return ERR_ABRT; - } else { - /* data is still refused, pbuf is still valid (go on for ACK-only packets) */ -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - if (rest != NULL) { - pbuf_cat(refused_data, rest); - } -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - pcb->refused_data = refused_data; - return ERR_INPROGRESS; - } - } - return ERR_OK; -} - -/** - * Deallocates a list of TCP segments (tcp_seg structures). - * - * @param seg tcp_seg list of TCP segments to free - */ -void -tcp_segs_free(struct tcp_seg *seg) -{ - while (seg != NULL) { - struct tcp_seg *next = seg->next; - tcp_seg_free(seg); - seg = next; - } -} - -/** - * Frees a TCP segment (tcp_seg structure). - * - * @param seg single tcp_seg to free - */ -void -tcp_seg_free(struct tcp_seg *seg) -{ - if (seg != NULL) { - if (seg->p != NULL) { - pbuf_free(seg->p); -#if TCP_DEBUG - seg->p = NULL; -#endif /* TCP_DEBUG */ - } - memp_free(MEMP_TCP_SEG, seg); - } -} - -/** - * Sets the priority of a connection. - * - * @param pcb the tcp_pcb to manipulate - * @param prio new priority - */ -void -tcp_setprio(struct tcp_pcb *pcb, u8_t prio) -{ - pcb->prio = prio; -} - -#if TCP_QUEUE_OOSEQ -/** - * Returns a copy of the given TCP segment. - * The pbuf and data are not copied, only the pointers - * - * @param seg the old tcp_seg - * @return a copy of seg - */ -struct tcp_seg * -tcp_seg_copy(struct tcp_seg *seg) -{ - struct tcp_seg *cseg; - - cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); - if (cseg == NULL) { - return NULL; - } - SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); - pbuf_ref(cseg->p); - return cseg; -} -#endif /* TCP_QUEUE_OOSEQ */ - -#if LWIP_CALLBACK_API -/** - * Default receive callback that is called if the user didn't register - * a recv callback for the pcb. - */ -err_t -tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - LWIP_UNUSED_ARG(arg); - if (p != NULL) { - tcp_recved(pcb, p->tot_len); - pbuf_free(p); - } else if (err == ERR_OK) { - return tcp_close(pcb); - } - return ERR_OK; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * Kills the oldest active connection that has the same or lower priority than - * 'prio'. - * - * @param prio minimum priority - */ -static void -tcp_kill_prio(u8_t prio) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - u8_t mprio; - - mprio = LWIP_MIN(TCP_PRIO_MAX, prio); - - /* We kill the oldest active connection that has lower priority than prio. */ - inactivity = 0; - inactive = NULL; - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->prio <= mprio && - (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - mprio = pcb->prio; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - -/** - * Kills the oldest connection that is in specific state. - * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available. - */ -static void -tcp_kill_state(enum tcp_state state) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - - LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK)); - - inactivity = 0; - inactive = NULL; - /* Go through the list of active pcbs and get the oldest pcb that is in state - CLOSING/LAST_ACK. */ - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->state == state) { - if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - } - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n", - tcp_state_str[state], (void *)inactive, inactivity)); - /* Don't send a RST, since no data is lost. */ - tcp_abandon(inactive, 0); - } -} - -/** - * Kills the oldest connection that is in TIME_WAIT state. - * Called from tcp_alloc() if no more connections are available. - */ -static void -tcp_kill_timewait(void) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - - inactivity = 0; - inactive = NULL; - /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ - for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - -/** - * Allocate a new tcp_pcb structure. - * - * @param prio priority for the new pcb - * @return a new tcp_pcb that initially is in state CLOSED - */ -struct tcp_pcb * -tcp_alloc(u8_t prio) -{ - struct tcp_pcb *pcb; - - pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in TIME-WAIT. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); - tcp_kill_timewait(); - /* Try to allocate a tcp_pcb again. */ - pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n")); - tcp_kill_state(LAST_ACK); - /* Try to allocate a tcp_pcb again. */ - pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in CLOSING. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n")); - tcp_kill_state(CLOSING); - /* Try to allocate a tcp_pcb again. */ - pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing active connections with lower priority than the new one. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio)); - tcp_kill_prio(prio); - /* Try to allocate a tcp_pcb again. */ - pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); - if (pcb != NULL) { - /* adjust err stats: memp_malloc failed multiple times before */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - /* adjust err stats: memp_malloc failed multiple times before */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - /* adjust err stats: memp_malloc failed multiple times before */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - /* adjust err stats: memp_malloc failed above */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - /* zero out the whole pcb, so there is no need to initialize members to zero */ - memset(pcb, 0, sizeof(struct tcp_pcb)); - pcb->prio = prio; - pcb->snd_buf = TCP_SND_BUF; - /* Start with a window that does not need scaling. When window scaling is - enabled and used, the window is enlarged when both sides agree on scaling. */ - pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); - pcb->ttl = TCP_TTL; - /* As initial send MSS, we use TCP_MSS but limit it to 536. - The send MSS is updated when an MSS option is received. */ - pcb->mss = INITIAL_MSS; - pcb->rto = 3000 / TCP_SLOW_INTERVAL; - pcb->sv = 3000 / TCP_SLOW_INTERVAL; - pcb->rtime = -1; - pcb->cwnd = 1; - pcb->tmr = tcp_ticks; - pcb->last_timer = tcp_timer_ctr; - - /* RFC 5681 recommends setting ssthresh abritrarily high and gives an example - of using the largest advertised receive window. We've seen complications with - receiving TCPs that use window scaling and/or window auto-tuning where the - initial advertised window is very small and then grows rapidly once the - connection is established. To avoid these complications, we set ssthresh to the - largest effective cwnd (amount of in-flight data) that the sender can have. */ - pcb->ssthresh = TCP_SND_BUF; - -#if LWIP_CALLBACK_API - pcb->recv = tcp_recv_null; -#endif /* LWIP_CALLBACK_API */ - - /* Init KEEPALIVE timer */ - pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; - -#if LWIP_TCP_KEEPALIVE - pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; - pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; -#endif /* LWIP_TCP_KEEPALIVE */ - } - return pcb; -} - -/** - * @ingroup tcp_raw - * Creates a new TCP protocol control block but doesn't place it on - * any of the TCP PCB lists. - * The pcb is not put on any list until binding using tcp_bind(). - * - * @internal: Maybe there should be a idle TCP PCB list where these - * PCBs are put on. Port reservation using tcp_bind() is implemented but - * allocated pcbs that are not bound can't be killed automatically if wanting - * to allocate a pcb with higher prio (@see tcp_kill_prio()) - * - * @return a new tcp_pcb that initially is in state CLOSED - */ -struct tcp_pcb * -tcp_new(void) -{ - return tcp_alloc(TCP_PRIO_NORMAL); -} - -/** - * @ingroup tcp_raw - * Creates a new TCP protocol control block but doesn't - * place it on any of the TCP PCB lists. - * The pcb is not put on any list until binding using tcp_bind(). - * - * @param type IP address type, see @ref lwip_ip_addr_type definitions. - * If you want to listen to IPv4 and IPv6 (dual-stack) connections, - * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. - * @return a new tcp_pcb that initially is in state CLOSED - */ -struct tcp_pcb * -tcp_new_ip_type(u8_t type) -{ - struct tcp_pcb * pcb; - pcb = tcp_alloc(TCP_PRIO_NORMAL); -#if LWIP_IPV4 && LWIP_IPV6 - if (pcb != NULL) { - IP_SET_TYPE_VAL(pcb->local_ip, type); - IP_SET_TYPE_VAL(pcb->remote_ip, type); - } -#else - LWIP_UNUSED_ARG(type); -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - return pcb; -} - -/** - * @ingroup tcp_raw - * Used to specify the argument that should be passed callback - * functions. - * - * @param pcb tcp_pcb to set the callback argument - * @param arg void pointer argument to pass to callback functions - */ -void -tcp_arg(struct tcp_pcb *pcb, void *arg) -{ - /* This function is allowed to be called for both listen pcbs and - connection pcbs. */ - if (pcb != NULL) { - pcb->callback_arg = arg; - } -} -#if LWIP_CALLBACK_API - -/** - * @ingroup tcp_raw - * Used to specify the function that should be called when a TCP - * connection receives data. - * - * @param pcb tcp_pcb to set the recv callback - * @param recv callback function to call for this pcb when data is received - */ -void -tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv) -{ - if (pcb != NULL) { - LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN); - pcb->recv = recv; - } -} - -/** - * @ingroup tcp_raw - * Used to specify the function that should be called when TCP data - * has been successfully delivered to the remote host. - * - * @param pcb tcp_pcb to set the sent callback - * @param sent callback function to call for this pcb when data is successfully sent - */ -void -tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent) -{ - if (pcb != NULL) { - LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN); - pcb->sent = sent; - } -} - -/** - * @ingroup tcp_raw - * Used to specify the function that should be called when a fatal error - * has occurred on the connection. - * - * @note The corresponding pcb is already freed when this callback is called! - * - * @param pcb tcp_pcb to set the err callback - * @param err callback function to call for this pcb when a fatal error - * has occurred on the connection - */ -void -tcp_err(struct tcp_pcb *pcb, tcp_err_fn err) -{ - if (pcb != NULL) { - LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN); - pcb->errf = err; - } -} - -/** - * @ingroup tcp_raw - * Used for specifying the function that should be called when a - * LISTENing connection has been connected to another host. - * - * @param pcb tcp_pcb to set the accept callback - * @param accept callback function to call for this pcb when LISTENing - * connection has been connected to another host - */ -void -tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept) -{ - if ((pcb != NULL) && (pcb->state == LISTEN)) { - struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen*)pcb; - lpcb->accept = accept; - } -} -#endif /* LWIP_CALLBACK_API */ - - -/** - * @ingroup tcp_raw - * Used to specify the function that should be called periodically - * from TCP. The interval is specified in terms of the TCP coarse - * timer interval, which is called twice a second. - * - */ -void -tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval) -{ - LWIP_ASSERT("invalid socket state for poll", pcb->state != LISTEN); -#if LWIP_CALLBACK_API - pcb->poll = poll; -#else /* LWIP_CALLBACK_API */ - LWIP_UNUSED_ARG(poll); -#endif /* LWIP_CALLBACK_API */ - pcb->pollinterval = interval; -} - -/** - * Purges a TCP PCB. Removes any buffered data and frees the buffer memory - * (pcb->ooseq, pcb->unsent and pcb->unacked are freed). - * - * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! - */ -void -tcp_pcb_purge(struct tcp_pcb *pcb) -{ - if (pcb->state != CLOSED && - pcb->state != TIME_WAIT && - pcb->state != LISTEN) { - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); - - tcp_backlog_accepted(pcb); - - if (pcb->refused_data != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); - pbuf_free(pcb->refused_data); - pcb->refused_data = NULL; - } - if (pcb->unsent != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); - } - if (pcb->unacked != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); - } - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; -#endif /* TCP_QUEUE_OOSEQ */ - - /* Stop the retransmission timer as it will expect data on unacked - queue if it fires */ - pcb->rtime = -1; - - tcp_segs_free(pcb->unsent); - tcp_segs_free(pcb->unacked); - pcb->unacked = pcb->unsent = NULL; -#if TCP_OVERSIZE - pcb->unsent_oversize = 0; -#endif /* TCP_OVERSIZE */ - } -} - -/** - * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. - * - * @param pcblist PCB list to purge. - * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! - */ -void -tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) -{ - TCP_RMV(pcblist, pcb); - - tcp_pcb_purge(pcb); - - /* if there is an outstanding delayed ACKs, send it */ - if (pcb->state != TIME_WAIT && - pcb->state != LISTEN && - pcb->flags & TF_ACK_DELAY) { - pcb->flags |= TF_ACK_NOW; - tcp_output(pcb); - } - - if (pcb->state != LISTEN) { - LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); - LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); -#if TCP_QUEUE_OOSEQ - LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); -#endif /* TCP_QUEUE_OOSEQ */ - } - - pcb->state = CLOSED; - /* reset the local port to prevent the pcb from being 'bound' */ - pcb->local_port = 0; - - LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); -} - -/** - * Calculates a new initial sequence number for new connections. - * - * @return u32_t pseudo random sequence number - */ -u32_t -tcp_next_iss(struct tcp_pcb *pcb) -{ -#ifdef LWIP_HOOK_TCP_ISN - return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port); -#else /* LWIP_HOOK_TCP_ISN */ - static u32_t iss = 6510; - - LWIP_UNUSED_ARG(pcb); - - iss += tcp_ticks; /* XXX */ - return iss; -#endif /* LWIP_HOOK_TCP_ISN */ -} - -#if TCP_CALCULATE_EFF_SEND_MSS -/** - * Calculates the effective send mss that can be used for a specific IP address - * by using ip_route to determine the netif used to send to the address and - * calculating the minimum of TCP_MSS and that netif's mtu (if set). - */ -u16_t -tcp_eff_send_mss_impl(u16_t sendmss, const ip_addr_t *dest -#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING - , const ip_addr_t *src -#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */ - ) -{ - u16_t mss_s; - struct netif *outif; - s16_t mtu; - - outif = ip_route(src, dest); -#if LWIP_IPV6 -#if LWIP_IPV4 - if (IP_IS_V6(dest)) -#endif /* LWIP_IPV4 */ - { - /* First look in destination cache, to see if there is a Path MTU. */ - mtu = nd6_get_destination_mtu(ip_2_ip6(dest), outif); - } -#if LWIP_IPV4 - else -#endif /* LWIP_IPV4 */ -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 - { - if (outif == NULL) { - return sendmss; - } - mtu = outif->mtu; - } -#endif /* LWIP_IPV4 */ - - if (mtu != 0) { -#if LWIP_IPV6 -#if LWIP_IPV4 - if (IP_IS_V6(dest)) -#endif /* LWIP_IPV4 */ - { - mss_s = mtu - IP6_HLEN - TCP_HLEN; - } -#if LWIP_IPV4 - else -#endif /* LWIP_IPV4 */ -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 - { - mss_s = mtu - IP_HLEN - TCP_HLEN; - } -#endif /* LWIP_IPV4 */ - /* RFC 1122, chap 4.2.2.6: - * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize - * We correct for TCP options in tcp_write(), and don't support IP options. - */ - sendmss = LWIP_MIN(sendmss, mss_s); - } - return sendmss; -} -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - -/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */ -static void -tcp_netif_ip_addr_changed_pcblist(const ip_addr_t* old_addr, struct tcp_pcb* pcb_list) -{ - struct tcp_pcb *pcb; - pcb = pcb_list; - while (pcb != NULL) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&pcb->local_ip, old_addr) -#if LWIP_AUTOIP - /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ - && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip))) -#endif /* LWIP_AUTOIP */ - ) { - /* this connection must be aborted */ - struct tcp_pcb *next = pcb->next; - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); - tcp_abort(pcb); - pcb = next; - } else { - pcb = pcb->next; - } - } -} - -/** This function is called from netif.c when address is changed or netif is removed - * - * @param old_addr IP address of the netif before change - * @param new_addr IP address of the netif after change or NULL if netif has been removed - */ -void -tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr) -{ - struct tcp_pcb_listen *lpcb, *next; - - if (!ip_addr_isany(old_addr)) { - tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs); - tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs); - - if (!ip_addr_isany(new_addr)) { - /* PCB bound to current local interface address? */ - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = next) { - next = lpcb->next; - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&lpcb->local_ip, old_addr)) { - /* The PCB is listening to the old ipaddr and - * is set to listen to the new one instead */ - ip_addr_copy(lpcb->local_ip, *new_addr); - } - } - } - } -} - -const char* -tcp_debug_state_str(enum tcp_state s) -{ - return tcp_state_str[s]; -} - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -/** - * Print a tcp header for debugging purposes. - * - * @param tcphdr pointer to a struct tcp_hdr - */ -void -tcp_debug_print(struct tcp_hdr *tcphdr) -{ - LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - lwip_ntohs(tcphdr->src), lwip_ntohs(tcphdr->dest))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", - lwip_ntohl(tcphdr->seqno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", - lwip_ntohl(tcphdr->ackno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", - TCPH_HDRLEN(tcphdr), - (u16_t)(TCPH_FLAGS(tcphdr) >> 5 & 1), - (u16_t)(TCPH_FLAGS(tcphdr) >> 4 & 1), - (u16_t)(TCPH_FLAGS(tcphdr) >> 3 & 1), - (u16_t)(TCPH_FLAGS(tcphdr) >> 2 & 1), - (u16_t)(TCPH_FLAGS(tcphdr) >> 1 & 1), - (u16_t)(TCPH_FLAGS(tcphdr) & 1), - lwip_ntohs(tcphdr->wnd))); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", - lwip_ntohs(tcphdr->chksum), lwip_ntohs(tcphdr->urgp))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); -} - -/** - * Print a tcp state for debugging purposes. - * - * @param s enum tcp_state to print - */ -void -tcp_debug_print_state(enum tcp_state s) -{ - LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s])); -} - -/** - * Print tcp flags for debugging purposes. - * - * @param flags tcp flags, all active flags are printed - */ -void -tcp_debug_print_flags(u8_t flags) -{ - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); - } - if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); - } - if (flags & TCP_RST) { - LWIP_DEBUGF(TCP_DEBUG, ("RST ")); - } - if (flags & TCP_PSH) { - LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); - } - if (flags & TCP_ACK) { - LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); - } - if (flags & TCP_URG) { - LWIP_DEBUGF(TCP_DEBUG, ("URG ")); - } - if (flags & TCP_ECE) { - LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); - } - if (flags & TCP_CWR) { - LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); - } - LWIP_DEBUGF(TCP_DEBUG, ("\n")); -} - -/** - * Print all tcp_pcbs in every list for debugging purposes. - */ -void -tcp_debug_print_pcbs(void) -{ - struct tcp_pcb *pcb; - struct tcp_pcb_listen *pcbl; - - LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - - LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); - for (pcbl = tcp_listen_pcbs.listen_pcbs; pcbl != NULL; pcbl = pcbl->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F" ", pcbl->local_port)); - tcp_debug_print_state(pcbl->state); - } - - LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); - for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } -} - -/** - * Check state consistency of the tcp_pcb lists. - */ -s16_t -tcp_pcbs_sane(void) -{ - struct tcp_pcb *pcb; - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - } - for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - } - return 1; -} -#endif /* TCP_DEBUG */ - -#endif /* LWIP_TCP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_in.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_in.c deleted file mode 100644 index ba879284f270f96e1c51872732bcc227f2b94734..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_in.c +++ /dev/null @@ -1,1818 +0,0 @@ -/** - * @file - * Transmission Control Protocol, incoming traffic - * - * The input processing functions of the TCP layer. - * - * These functions are generally called in the order (ip_input() ->) - * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/priv/tcp_priv.h" -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/inet_chksum.h" -#include "lwip/stats.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#if LWIP_ND6_TCP_REACHABILITY_HINTS -#include "lwip/nd6.h" -#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ - -/** Initial CWND calculation as defined RFC 2581 */ -#define LWIP_TCP_CALC_INITIAL_CWND(mss) LWIP_MIN((4U * (mss)), LWIP_MAX((2U * (mss)), 4380U)); - -/* These variables are global to all functions involved in the input - processing of TCP segments. They are set by the tcp_input() - function. */ -static struct tcp_seg inseg; -static struct tcp_hdr *tcphdr; -static u16_t tcphdr_optlen; -static u16_t tcphdr_opt1len; -static u8_t* tcphdr_opt2; -static u16_t tcp_optidx; -static u32_t seqno, ackno; -static tcpwnd_size_t recv_acked; -static u16_t tcplen; -static u8_t flags; - -static u8_t recv_flags; -static struct pbuf *recv_data; - -struct tcp_pcb *tcp_input_pcb; - -/* Forward declarations. */ -static err_t tcp_process(struct tcp_pcb *pcb); -static void tcp_receive(struct tcp_pcb *pcb); -static void tcp_parseopt(struct tcp_pcb *pcb); - -static void tcp_listen_input(struct tcp_pcb_listen *pcb); -static void tcp_timewait_input(struct tcp_pcb *pcb); - -/** - * The initial input processing of TCP. It verifies the TCP header, demultiplexes - * the segment between the PCBs and passes it on to tcp_process(), which implements - * the TCP finite state machine. This function is called by the IP layer (in - * ip_input()). - * - * @param p received TCP segment to process (p->payload pointing to the TCP header) - * @param inp network interface on which this segment was received - */ -void -tcp_input(struct pbuf *p, struct netif *inp) -{ - struct tcp_pcb *pcb, *prev; - struct tcp_pcb_listen *lpcb; -#if SO_REUSE - struct tcp_pcb *lpcb_prev = NULL; - struct tcp_pcb_listen *lpcb_any = NULL; -#endif /* SO_REUSE */ - u8_t hdrlen_bytes; - err_t err; - - LWIP_UNUSED_ARG(inp); - - PERF_START; - - TCP_STATS_INC(tcp.recv); - MIB2_STATS_INC(mib2.tcpinsegs); - - tcphdr = (struct tcp_hdr *)p->payload; - -#if TCP_INPUT_DEBUG - tcp_debug_print(tcphdr); -#endif - - /* Check that TCP header fits in payload */ - if (p->len < TCP_HLEN) { - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); - TCP_STATS_INC(tcp.lenerr); - goto dropped; - } - - /* Don't even process incoming broadcasts/multicasts. */ - if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || - ip_addr_ismulticast(ip_current_dest_addr())) { - TCP_STATS_INC(tcp.proterr); - goto dropped; - } - -#if CHECKSUM_CHECK_TCP - IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_TCP) { - /* Verify TCP checksum. */ - u16_t chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - ip_current_src_addr(), ip_current_dest_addr()); - if (chksum != 0) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", - chksum)); - tcp_debug_print(tcphdr); - TCP_STATS_INC(tcp.chkerr); - goto dropped; - } - } -#endif /* CHECKSUM_CHECK_TCP */ - - /* sanity-check header length */ - hdrlen_bytes = TCPH_HDRLEN(tcphdr) * 4; - if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: invalid header length (%"U16_F")\n", (u16_t)hdrlen_bytes)); - TCP_STATS_INC(tcp.lenerr); - goto dropped; - } - - /* Move the payload pointer in the pbuf so that it points to the - TCP data instead of the TCP header. */ - tcphdr_optlen = hdrlen_bytes - TCP_HLEN; - tcphdr_opt2 = NULL; - if (p->len >= hdrlen_bytes) { - /* all options are in the first pbuf */ - tcphdr_opt1len = tcphdr_optlen; - pbuf_header(p, -(s16_t)hdrlen_bytes); /* cannot fail */ - } else { - u16_t opt2len; - /* TCP header fits into first pbuf, options don't - data is in the next pbuf */ - /* there must be a next pbuf, due to hdrlen_bytes sanity check above */ - LWIP_ASSERT("p->next != NULL", p->next != NULL); - - /* advance over the TCP header (cannot fail) */ - pbuf_header(p, -TCP_HLEN); - - /* determine how long the first and second parts of the options are */ - tcphdr_opt1len = p->len; - opt2len = tcphdr_optlen - tcphdr_opt1len; - - /* options continue in the next pbuf: set p to zero length and hide the - options in the next pbuf (adjusting p->tot_len) */ - pbuf_header(p, -(s16_t)tcphdr_opt1len); - - /* check that the options fit in the second pbuf */ - if (opt2len > p->next->len) { - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: options overflow second pbuf (%"U16_F" bytes)\n", p->next->len)); - TCP_STATS_INC(tcp.lenerr); - goto dropped; - } - - /* remember the pointer to the second part of the options */ - tcphdr_opt2 = (u8_t*)p->next->payload; - - /* advance p->next to point after the options, and manually - adjust p->tot_len to keep it consistent with the changed p->next */ - pbuf_header(p->next, -(s16_t)opt2len); - p->tot_len -= opt2len; - - LWIP_ASSERT("p->len == 0", p->len == 0); - LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len); - } - - /* Convert fields in TCP header to host byte order. */ - tcphdr->src = lwip_ntohs(tcphdr->src); - tcphdr->dest = lwip_ntohs(tcphdr->dest); - seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno); - ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno); - tcphdr->wnd = lwip_ntohs(tcphdr->wnd); - - flags = TCPH_FLAGS(tcphdr); - tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0); - - /* Demultiplex an incoming segment. First, we check if it is destined - for an active connection. */ - prev = NULL; - - for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && - ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); - if (prev != NULL) { - prev->next = pcb->next; - pcb->next = tcp_active_pcbs; - tcp_active_pcbs = pcb; - } else { - TCP_STATS_INC(tcp.cachehit); - } - LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); - break; - } - prev = pcb; - } - - if (pcb == NULL) { - /* If it did not go to an active connection, we check the connections - in the TIME-WAIT state. */ - for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && - ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { - /* We don't really care enough to move this PCB to the front - of the list since we are not very likely to receive that - many segments for connections in TIME-WAIT. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); - tcp_timewait_input(pcb); - pbuf_free(p); - return; - } - } - - /* Finally, if we still did not get a match, we check all PCBs that - are LISTENing for incoming connections. */ - prev = NULL; - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if (lpcb->local_port == tcphdr->dest) { - if (IP_IS_ANY_TYPE_VAL(lpcb->local_ip)) { - /* found an ANY TYPE (IPv4/IPv6) match */ -#if SO_REUSE - lpcb_any = lpcb; - lpcb_prev = prev; -#else /* SO_REUSE */ - break; -#endif /* SO_REUSE */ - } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) { - if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) { - /* found an exact match */ - break; - } else if (ip_addr_isany(&lpcb->local_ip)) { - /* found an ANY-match */ -#if SO_REUSE - lpcb_any = lpcb; - lpcb_prev = prev; -#else /* SO_REUSE */ - break; - #endif /* SO_REUSE */ - } - } - } - prev = (struct tcp_pcb *)lpcb; - } -#if SO_REUSE - /* first try specific local IP */ - if (lpcb == NULL) { - /* only pass to ANY if no specific local IP has been found */ - lpcb = lpcb_any; - prev = lpcb_prev; - } -#endif /* SO_REUSE */ - if (lpcb != NULL) { - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - if (prev != NULL) { - ((struct tcp_pcb_listen *)prev)->next = lpcb->next; - /* our successor is the remainder of the listening list */ - lpcb->next = tcp_listen_pcbs.listen_pcbs; - /* put this listening pcb at the head of the listening list */ - tcp_listen_pcbs.listen_pcbs = lpcb; - } else { - TCP_STATS_INC(tcp.cachehit); - } - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); - tcp_listen_input(lpcb); - pbuf_free(p); - return; - } - } - -#if TCP_INPUT_DEBUG - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); -#endif /* TCP_INPUT_DEBUG */ - - - if (pcb != NULL) { - /* The incoming segment belongs to a connection. */ -#if TCP_INPUT_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_INPUT_DEBUG */ - - /* Set up a tcp_seg structure. */ - inseg.next = NULL; - inseg.len = p->tot_len; - inseg.p = p; - inseg.tcphdr = tcphdr; - - recv_data = NULL; - recv_flags = 0; - recv_acked = 0; - - if (flags & TCP_PSH) { - p->flags |= PBUF_FLAG_PUSH; - } - - /* If there is data which was previously "refused" by upper layer */ - if (pcb->refused_data != NULL) { - if ((tcp_process_refused_data(pcb) == ERR_ABRT) || - ((pcb->refused_data != NULL) && (tcplen > 0))) { - /* pcb has been aborted or refused data is still refused and the new - segment contains data */ - if (pcb->rcv_ann_wnd == 0) { - /* this is a zero-window probe, we respond to it with current RCV.NXT - and drop the data segment */ - tcp_send_empty_ack(pcb); - } - TCP_STATS_INC(tcp.drop); - MIB2_STATS_INC(mib2.tcpinerrs); - goto aborted; - } - } - tcp_input_pcb = pcb; - err = tcp_process(pcb); - /* A return value of ERR_ABRT means that tcp_abort() was called - and that the pcb has been freed. If so, we don't do anything. */ - if (err != ERR_ABRT) { - if (recv_flags & TF_RESET) { - /* TF_RESET means that the connection was reset by the other - end. We then call the error callback to inform the - application that the connection is dead before we - deallocate the PCB. */ - TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST); - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - err = ERR_OK; - /* If the application has registered a "sent" function to be - called when new send buffer space is available, we call it - now. */ - if (recv_acked > 0) { - u16_t acked16; -#if LWIP_WND_SCALE - /* recv_acked is u32_t but the sent callback only takes a u16_t, - so we might have to call it multiple times. */ - u32_t acked = recv_acked; - while (acked > 0) { - acked16 = (u16_t)LWIP_MIN(acked, 0xffffu); - acked -= acked16; -#else - { - acked16 = recv_acked; -#endif - TCP_EVENT_SENT(pcb, (u16_t)acked16, err); - if (err == ERR_ABRT) { - goto aborted; - } - } - recv_acked = 0; - } - if (recv_flags & TF_CLOSED) { - /* The connection has been closed and we will deallocate the - PCB. */ - if (!(pcb->flags & TF_RXCLOSED)) { - /* Connection closed although the application has only shut down the - tx side: call the PCB's err callback and indicate the closure to - ensure the application doesn't continue using the PCB. */ - TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD); - } - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - goto aborted; - } -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - while (recv_data != NULL) { - struct pbuf *rest = NULL; - pbuf_split_64k(recv_data, &rest); -#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - if (recv_data != NULL) { -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - - LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); - if (pcb->flags & TF_RXCLOSED) { - /* received data although already closed -> abort (send RST) to - notify the remote host that not all data has been processed */ - pbuf_free(recv_data); -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - if (rest != NULL) { - pbuf_free(rest); - } -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - tcp_abort(pcb); - goto aborted; - } - - /* Notify application that data has been received. */ - TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); - if (err == ERR_ABRT) { -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - if (rest != NULL) { - pbuf_free(rest); - } -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - goto aborted; - } - - /* If the upper layer can't receive this data, store it */ - if (err != ERR_OK) { -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - if (rest != NULL) { - pbuf_cat(recv_data, rest); - } -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - pcb->refused_data = recv_data; - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n")); -#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE - break; - } else { - /* Upper layer received the data, go on with the rest if > 64K */ - recv_data = rest; -#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - } - } - - /* If a FIN segment was received, we call the callback - function with a NULL buffer to indicate EOF. */ - if (recv_flags & TF_GOT_FIN) { - if (pcb->refused_data != NULL) { - /* Delay this if we have refused data. */ - pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN; - } else { - /* correct rcv_wnd as the application won't call tcp_recved() - for the FIN's seqno */ - if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { - pcb->rcv_wnd++; - } - TCP_EVENT_CLOSED(pcb, err); - if (err == ERR_ABRT) { - goto aborted; - } - } - } - - tcp_input_pcb = NULL; - /* Try to send something out. */ - tcp_output(pcb); -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - } - } - /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). - Below this line, 'pcb' may not be dereferenced! */ -aborted: - tcp_input_pcb = NULL; - recv_data = NULL; - - /* give up our reference to inseg.p */ - if (inseg.p != NULL) - { - pbuf_free(inseg.p); - inseg.p = NULL; - } - } else { - - /* If no matching PCB was found, send a TCP RST (reset) to the - sender. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); - if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { - TCP_STATS_INC(tcp.proterr); - TCP_STATS_INC(tcp.drop); - tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), - ip_current_src_addr(), tcphdr->dest, tcphdr->src); - } - pbuf_free(p); - } - - LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); - PERF_STOP("tcp_input"); - return; -dropped: - TCP_STATS_INC(tcp.drop); - MIB2_STATS_INC(mib2.tcpinerrs); - pbuf_free(p); -} - -/** - * Called by tcp_input() when a segment arrives for a listening - * connection (from tcp_input()). - * - * @param pcb the tcp_pcb_listen for which a segment arrived - * - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static void -tcp_listen_input(struct tcp_pcb_listen *pcb) -{ - struct tcp_pcb *npcb; - u32_t iss; - err_t rc; - - if (flags & TCP_RST) { - /* An incoming RST should be ignored. Return. */ - return; - } - - /* In the LISTEN state, we check for incoming SYN segments, - creates a new PCB, and responds with a SYN|ACK. */ - if (flags & TCP_ACK) { - /* For incoming segments with the ACK flag set, respond with a - RST. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); - tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), - ip_current_src_addr(), tcphdr->dest, tcphdr->src); - } else if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); -#if TCP_LISTEN_BACKLOG - if (pcb->accepts_pending >= pcb->backlog) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest)); - return; - } -#endif /* TCP_LISTEN_BACKLOG */ - npcb = tcp_alloc(pcb->prio); - /* If a new PCB could not be created (probably due to lack of memory), - we don't do anything, but rely on the sender will retransmit the - SYN at a time when we have more memory available. */ - if (npcb == NULL) { - err_t err; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); - TCP_STATS_INC(tcp.memerr); - TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); - LWIP_UNUSED_ARG(err); /* err not useful here */ - return; - } -#if TCP_LISTEN_BACKLOG - pcb->accepts_pending++; - npcb->flags |= TF_BACKLOGPEND; -#endif /* TCP_LISTEN_BACKLOG */ - /* Set up the new PCB. */ - ip_addr_copy(npcb->local_ip, *ip_current_dest_addr()); - ip_addr_copy(npcb->remote_ip, *ip_current_src_addr()); - npcb->local_port = pcb->local_port; - npcb->remote_port = tcphdr->src; - npcb->state = SYN_RCVD; - npcb->rcv_nxt = seqno + 1; - npcb->rcv_ann_right_edge = npcb->rcv_nxt; - iss = tcp_next_iss(npcb); - npcb->snd_wl2 = iss; - npcb->snd_nxt = iss; - npcb->lastack = iss; - npcb->snd_lbb = iss; - npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ - npcb->callback_arg = pcb->callback_arg; -#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG - npcb->listener = pcb; -#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ - /* inherit socket options */ - npcb->so_options = pcb->so_options & SOF_INHERITED; - /* Register the new PCB so that we can begin receiving segments - for it. */ - TCP_REG_ACTIVE(npcb); - - /* Parse any options in the SYN. */ - tcp_parseopt(npcb); - npcb->snd_wnd = tcphdr->wnd; - npcb->snd_wnd_max = npcb->snd_wnd; - -#if TCP_CALCULATE_EFF_SEND_MSS - npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - - MIB2_STATS_INC(mib2.tcppassiveopens); - - /* Send a SYN|ACK together with the MSS option. */ - rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); - if (rc != ERR_OK) { - tcp_abandon(npcb, 0); - return; - } - tcp_output(npcb); - } - return; -} - -/** - * Called by tcp_input() when a segment arrives for a connection in - * TIME_WAIT. - * - * @param pcb the tcp_pcb for which a segment arrived - * - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static void -tcp_timewait_input(struct tcp_pcb *pcb) -{ - /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ - /* RFC 793 3.9 Event Processing - Segment Arrives: - * - first check sequence number - we skip that one in TIME_WAIT (always - * acceptable since we only send ACKs) - * - second check the RST bit (... return) */ - if (flags & TCP_RST) { - return; - } - /* - fourth, check the SYN bit, */ - if (flags & TCP_SYN) { - /* If an incoming segment is not acceptable, an acknowledgment - should be sent in reply */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) { - /* If the SYN is in the window it is an error, send a reset */ - tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), - ip_current_src_addr(), tcphdr->dest, tcphdr->src); - return; - } - } else if (flags & TCP_FIN) { - /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. - Restart the 2 MSL time-wait timeout.*/ - pcb->tmr = tcp_ticks; - } - - if ((tcplen > 0)) { - /* Acknowledge data, FIN or out-of-window SYN */ - pcb->flags |= TF_ACK_NOW; - tcp_output(pcb); - } - return; -} - -/** - * Implements the TCP state machine. Called by tcp_input. In some - * states tcp_receive() is called to receive data. The tcp_seg - * argument will be freed by the caller (tcp_input()) unless the - * recv_data pointer in the pcb is set. - * - * @param pcb the tcp_pcb for which a segment arrived - * - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static err_t -tcp_process(struct tcp_pcb *pcb) -{ - struct tcp_seg *rseg; - u8_t acceptable = 0; - err_t err; - - err = ERR_OK; - - /* Process incoming RST segments. */ - if (flags & TCP_RST) { - /* First, determine if the reset is acceptable. */ - if (pcb->state == SYN_SENT) { - /* "In the SYN-SENT state (a RST received in response to an initial SYN), - the RST is acceptable if the ACK field acknowledges the SYN." */ - if (ackno == pcb->snd_nxt) { - acceptable = 1; - } - } else { - /* "In all states except SYN-SENT, all reset (RST) segments are validated - by checking their SEQ-fields." */ - if (seqno == pcb->rcv_nxt) { - acceptable = 1; - } else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, - pcb->rcv_nxt + pcb->rcv_wnd)) { - /* If the sequence number is inside the window, we only send an ACK - and wait for a re-send with matching sequence number. - This violates RFC 793, but is required to protection against - CVE-2004-0230 (RST spoofing attack). */ - tcp_ack_now(pcb); - } - } - - if (acceptable) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); - LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); - recv_flags |= TF_RESET; - pcb->flags &= ~TF_ACK_DELAY; - return ERR_RST; - } else { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - return ERR_OK; - } - } - - if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { - /* Cope with new connection attempt after remote end crashed */ - tcp_ack_now(pcb); - return ERR_OK; - } - - if ((pcb->flags & TF_RXCLOSED) == 0) { - /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ - pcb->tmr = tcp_ticks; - } - pcb->keep_cnt_sent = 0; - - tcp_parseopt(pcb); - - /* Do different things depending on the TCP state. */ - switch (pcb->state) { - case SYN_SENT: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, - pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno))); - /* received SYN ACK with expected sequence number? */ - if ((flags & TCP_ACK) && (flags & TCP_SYN) - && (ackno == pcb->lastack + 1)) { - pcb->rcv_nxt = seqno + 1; - pcb->rcv_ann_right_edge = pcb->rcv_nxt; - pcb->lastack = ackno; - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wnd_max = pcb->snd_wnd; - pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ - pcb->state = ESTABLISHED; - -#if TCP_CALCULATE_EFF_SEND_MSS - pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - - pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F - " ssthresh %"TCPWNDSIZE_F"\n", - pcb->cwnd, pcb->ssthresh)); - LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); - --pcb->snd_queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); - rseg = pcb->unacked; - if (rseg == NULL) { - /* might happen if tcp_output fails in tcp_rexmit_rto() - in which case the segment is on the unsent list */ - rseg = pcb->unsent; - LWIP_ASSERT("no segment to free", rseg != NULL); - pcb->unsent = rseg->next; - } else { - pcb->unacked = rseg->next; - } - tcp_seg_free(rseg); - - /* If there's nothing left to acknowledge, stop the retransmit - timer, otherwise reset it to start again */ - if (pcb->unacked == NULL) { - pcb->rtime = -1; - } else { - pcb->rtime = 0; - pcb->nrtx = 0; - } - - /* Call the user specified function to call when successfully - * connected. */ - TCP_EVENT_CONNECTED(pcb, ERR_OK, err); - if (err == ERR_ABRT) { - return ERR_ABRT; - } - tcp_ack_now(pcb); - } - /* received ACK? possibly a half-open connection */ - else if (flags & TCP_ACK) { - /* send a RST to bring the other side in a non-synchronized state. */ - tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), - ip_current_src_addr(), tcphdr->dest, tcphdr->src); - /* Resend SYN immediately (don't wait for rto timeout) to establish - connection faster, but do not send more SYNs than we otherwise would - have, or we might get caught in a loop on loopback interfaces. */ - if (pcb->nrtx < TCP_SYNMAXRTX) { - pcb->rtime = 0; - tcp_rexmit_rto(pcb); - } - } - break; - case SYN_RCVD: - if (flags & TCP_ACK) { - /* expected ACK number? */ - if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { - pcb->state = ESTABLISHED; - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); -#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG -#if LWIP_CALLBACK_API - LWIP_ASSERT("pcb->listener->accept != NULL", - (pcb->listener == NULL) || (pcb->listener->accept != NULL)); -#endif - if (pcb->listener == NULL) { - /* listen pcb might be closed by now */ - err = ERR_VAL; - } else -#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ - { - tcp_backlog_accepted(pcb); - /* Call the accept function. */ - TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err); - } - if (err != ERR_OK) { - /* If the accept function returns with an error, we abort - * the connection. */ - /* Already aborted? */ - if (err != ERR_ABRT) { - tcp_abort(pcb); - } - return ERR_ABRT; - } - /* If there was any data contained within this ACK, - * we'd better pass it on to the application as well. */ - tcp_receive(pcb); - - /* Prevent ACK for SYN to generate a sent event */ - if (recv_acked != 0) { - recv_acked--; - } - - pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F - " ssthresh %"TCPWNDSIZE_F"\n", - pcb->cwnd, pcb->ssthresh)); - - if (recv_flags & TF_GOT_FIN) { - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - } else { - /* incorrect ACK number, send RST */ - tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), - ip_current_src_addr(), tcphdr->dest, tcphdr->src); - } - } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { - /* Looks like another copy of the SYN - retransmit our SYN-ACK */ - tcp_rexmit(pcb); - } - break; - case CLOSE_WAIT: - /* FALLTHROUGH */ - case ESTABLISHED: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { /* passive close */ - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - break; - case FIN_WAIT_1: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { - if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && - pcb->unsent == NULL) { - LWIP_DEBUGF(TCP_DEBUG, - ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV_ACTIVE(pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } else { - tcp_ack_now(pcb); - pcb->state = CLOSING; - } - } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && - pcb->unsent == NULL) { - pcb->state = FIN_WAIT_2; - } - break; - case FIN_WAIT_2: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV_ACTIVE(pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case CLOSING: - tcp_receive(pcb); - if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_pcb_purge(pcb); - TCP_RMV_ACTIVE(pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case LAST_ACK: - tcp_receive(pcb); - if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ - recv_flags |= TF_CLOSED; - } - break; - default: - break; - } - return ERR_OK; -} - -#if TCP_QUEUE_OOSEQ -/** - * Insert segment into the list (segments covered with new one will be deleted) - * - * Called from tcp_receive() - */ -static void -tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) -{ - struct tcp_seg *old_seg; - - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - /* received segment overlaps all following segments */ - tcp_segs_free(next); - next = NULL; - } else { - /* delete some following segments - oos queue may have segments with FIN flag */ - while (next && - TCP_SEQ_GEQ((seqno + cseg->len), - (next->tcphdr->seqno + next->len))) { - /* cseg with FIN already processed */ - if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { - TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); - } - old_seg = next; - next = next->next; - tcp_seg_free(old_seg); - } - if (next && - TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - cseg->len = (u16_t)(next->tcphdr->seqno - seqno); - pbuf_realloc(cseg->p, cseg->len); - } - } - cseg->next = next; -} -#endif /* TCP_QUEUE_OOSEQ */ - -/** - * Called by tcp_process. Checks if the given segment is an ACK for outstanding - * data, and if so frees the memory of the buffered data. Next, it places the - * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment - * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until - * it has been removed from the buffer. - * - * If the incoming segment constitutes an ACK for a segment that was used for RTT - * estimation, the RTT is estimated here as well. - * - * Called from tcp_process(). - */ -static void -tcp_receive(struct tcp_pcb *pcb) -{ - struct tcp_seg *next; -#if TCP_QUEUE_OOSEQ - struct tcp_seg *prev, *cseg; -#endif /* TCP_QUEUE_OOSEQ */ - s32_t off; - s16_t m; - u32_t right_wnd_edge; - u16_t new_tot_len; - int found_dupack = 0; -#if TCP_OOSEQ_MAX_BYTES || TCP_OOSEQ_MAX_PBUFS - u32_t ooseq_blen; - u16_t ooseq_qlen; -#endif /* TCP_OOSEQ_MAX_BYTES || TCP_OOSEQ_MAX_PBUFS */ - - LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED); - - if (flags & TCP_ACK) { - right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; - - /* Update window. */ - if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || - (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || - (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { - pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd); - /* keep track of the biggest window announced by the remote host to calculate - the maximum segment size */ - if (pcb->snd_wnd_max < pcb->snd_wnd) { - pcb->snd_wnd_max = pcb->snd_wnd; - } - pcb->snd_wl1 = seqno; - pcb->snd_wl2 = ackno; - if (pcb->snd_wnd == 0) { - if (pcb->persist_backoff == 0) { - /* start persist timer */ - pcb->persist_cnt = 0; - pcb->persist_backoff = 1; - } - } else if (pcb->persist_backoff > 0) { - /* stop persist timer */ - pcb->persist_backoff = 0; - } - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"TCPWNDSIZE_F"\n", pcb->snd_wnd)); -#if TCP_WND_DEBUG - } else { - if (pcb->snd_wnd != (tcpwnd_size_t)SND_WND_SCALE(pcb, tcphdr->wnd)) { - LWIP_DEBUGF(TCP_WND_DEBUG, - ("tcp_receive: no window update lastack %"U32_F" ackno %" - U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", - pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); - } -#endif /* TCP_WND_DEBUG */ - } - - /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a - * duplicate ack if: - * 1) It doesn't ACK new data - * 2) length of received packet is zero (i.e. no payload) - * 3) the advertised window hasn't changed - * 4) There is outstanding unacknowledged data (retransmission timer running) - * 5) The ACK is == biggest ACK sequence number so far seen (snd_una) - * - * If it passes all five, should process as a dupack: - * a) dupacks < 3: do nothing - * b) dupacks == 3: fast retransmit - * c) dupacks > 3: increase cwnd - * - * If it only passes 1-3, should reset dupack counter (and add to - * stats, which we don't do in lwIP) - * - * If it only passes 1, should reset dupack counter - * - */ - - /* Clause 1 */ - if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { - /* Clause 2 */ - if (tcplen == 0) { - /* Clause 3 */ - if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) { - /* Clause 4 */ - if (pcb->rtime >= 0) { - /* Clause 5 */ - if (pcb->lastack == ackno) { - found_dupack = 1; - if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) { - ++pcb->dupacks; - } - if (pcb->dupacks > 3) { - /* Inflate the congestion window, but not if it means that - the value overflows. */ - if ((tcpwnd_size_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - } else if (pcb->dupacks == 3) { - /* Do fast retransmit */ - tcp_rexmit_fast(pcb); - } - } - } - } - } - /* If Clause (1) or more is true, but not a duplicate ack, reset - * count of consecutive duplicate acks */ - if (!found_dupack) { - pcb->dupacks = 0; - } - } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { - /* We come here when the ACK acknowledges new data. */ - - /* Reset the "IN Fast Retransmit" flag, since we are no longer - in fast retransmit. Also reset the congestion window to the - slow start threshold. */ - if (pcb->flags & TF_INFR) { - pcb->flags &= ~TF_INFR; - pcb->cwnd = pcb->ssthresh; - } - - /* Reset the number of retransmissions. */ - pcb->nrtx = 0; - - /* Reset the retransmission time-out. */ - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - /* Reset the fast retransmit variables. */ - pcb->dupacks = 0; - pcb->lastack = ackno; - - /* Update the congestion control variables (cwnd and - ssthresh). */ - if (pcb->state >= ESTABLISHED) { - if (pcb->cwnd < pcb->ssthresh) { - if ((tcpwnd_size_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); - } else { - tcpwnd_size_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); - if (new_cwnd > pcb->cwnd) { - pcb->cwnd = new_cwnd; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); - } - } - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", - ackno, - pcb->unacked != NULL? - lwip_ntohl(pcb->unacked->tcphdr->seqno): 0, - pcb->unacked != NULL? - lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); - - /* Remove segment from the unacknowledged list if the incoming - ACK acknowledges them. */ - while (pcb->unacked != NULL && - TCP_SEQ_LEQ(lwip_ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked), ackno)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", - lwip_ntohl(pcb->unacked->tcphdr->seqno), - lwip_ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked))); - - next = pcb->unacked; - pcb->unacked = pcb->unacked->next; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", (tcpwnd_size_t)pcb->snd_queuelen)); - LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); - - pcb->snd_queuelen -= pbuf_clen(next->p); - recv_acked += next->len; - tcp_seg_free(next); - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing unacked)\n", (tcpwnd_size_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - } - - /* If there's nothing left to acknowledge, stop the retransmit - timer, otherwise reset it to start again */ - if (pcb->unacked == NULL) { - pcb->rtime = -1; - } else { - pcb->rtime = 0; - } - - pcb->polltmr = 0; - -#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS - if (ip_current_is_v6()) { - /* Inform neighbor reachability of forward progress. */ - nd6_reachability_hint(ip6_current_src_addr()); - } -#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ - } else { - /* Out of sequence ACK, didn't really ack anything */ - tcp_send_empty_ack(pcb); - } - - /* We go through the ->unsent list to see if any of the segments - on the list are acknowledged by the ACK. This may seem - strange since an "unsent" segment shouldn't be acked. The - rationale is that lwIP puts all outstanding segments on the - ->unsent list after a retransmission, so these segments may - in fact have been sent once. */ - while (pcb->unsent != NULL && - TCP_SEQ_BETWEEN(ackno, lwip_ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", - lwip_ntohl(pcb->unsent->tcphdr->seqno), lwip_ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent))); - - next = pcb->unsent; - pcb->unsent = pcb->unsent->next; -#if TCP_OVERSIZE - if (pcb->unsent == NULL) { - pcb->unsent_oversize = 0; - } -#endif /* TCP_OVERSIZE */ - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", (tcpwnd_size_t)pcb->snd_queuelen)); - LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); - /* Prevent ACK for FIN to generate a sent event */ - pcb->snd_queuelen -= pbuf_clen(next->p); - recv_acked += next->len; - tcp_seg_free(next); - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing unsent)\n", (tcpwnd_size_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - } - pcb->snd_buf += recv_acked; - /* End of ACK for new data processing. */ - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", - pcb->rttest, pcb->rtseq, ackno)); - - /* RTT estimation calculations. This is done by checking if the - incoming segment acknowledges the segment we use to take a - round-trip time measurement. */ - if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { - /* diff between this shouldn't exceed 32K since this are tcp timer ticks - and a round-trip shouldn't be that long... */ - m = (s16_t)(tcp_ticks - pcb->rttest); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", - m, (u16_t)(m * TCP_SLOW_INTERVAL))); - - /* This is taken directly from VJs original code in his paper */ - m = m - (pcb->sa >> 3); - pcb->sa += m; - if (m < 0) { - m = -m; - } - m = m - (pcb->sv >> 2); - pcb->sv += m; - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", - pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL))); - - pcb->rttest = 0; - } - } - - /* If the incoming segment contains data, we must process it - further unless the pcb already received a FIN. - (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING, - LAST-ACK and TIME-WAIT: "Ignore the segment text.") */ - if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) { - /* This code basically does three things: - - +) If the incoming segment contains data that is the next - in-sequence data, this data is passed to the application. This - might involve trimming the first edge of the data. The rcv_nxt - variable and the advertised window are adjusted. - - +) If the incoming segment has data that is above the next - sequence number expected (->rcv_nxt), the segment is placed on - the ->ooseq queue. This is done by finding the appropriate - place in the ->ooseq queue (which is ordered by sequence - number) and trim the segment in both ends if needed. An - immediate ACK is sent to indicate that we received an - out-of-sequence segment. - - +) Finally, we check if the first segment on the ->ooseq queue - now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If - rcv_nxt > ooseq->seqno, we must trim the first edge of the - segment on ->ooseq before we adjust rcv_nxt. The data in the - segments that are now on sequence are chained onto the - incoming segment so that we only need to call the application - once. - */ - - /* First, we check if we must trim the first edge. We have to do - this if the sequence number of the incoming segment is less - than rcv_nxt, and the sequence number plus the length of the - segment is larger than rcv_nxt. */ - /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { - if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ - if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { - /* Trimming the first edge is done by pushing the payload - pointer in the pbuf downwards. This is somewhat tricky since - we do not want to discard the full contents of the pbuf up to - the new starting point of the data since we have to keep the - TCP header which is present in the first pbuf in the chain. - - What is done is really quite a nasty hack: the first pbuf in - the pbuf chain is pointed to by inseg.p. Since we need to be - able to deallocate the whole pbuf, we cannot change this - inseg.p pointer to point to any of the later pbufs in the - chain. Instead, we point the ->payload pointer in the first - pbuf to data in one of the later pbufs. We also set the - inseg.data pointer to point to the right place. This way, the - ->p pointer will still point to the first pbuf, but the - ->p->payload pointer will point to data in another pbuf. - - After we are done with adjusting the pbuf pointers we must - adjust the ->data pointer in the seg and the segment - length.*/ - - struct pbuf *p = inseg.p; - off = pcb->rcv_nxt - seqno; - LWIP_ASSERT("inseg.p != NULL", inseg.p); - LWIP_ASSERT("insane offset!", (off < 0x7fff)); - if (inseg.p->len < off) { - LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); - new_tot_len = (u16_t)(inseg.p->tot_len - off); - while (p->len < off) { - off -= p->len; - /* KJM following line changed (with addition of new_tot_len var) - to fix bug #9076 - inseg.p->tot_len -= p->len; */ - p->tot_len = new_tot_len; - p->len = 0; - p = p->next; - } - if (pbuf_header(p, (s16_t)-off)) { - /* Do we need to cope with this failing? Assert for now */ - LWIP_ASSERT("pbuf_header failed", 0); - } - } else { - if (pbuf_header(inseg.p, (s16_t)-off)) { - /* Do we need to cope with this failing? Assert for now */ - LWIP_ASSERT("pbuf_header failed", 0); - } - } - inseg.len -= (u16_t)(pcb->rcv_nxt - seqno); - inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; - } - else { - if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { - /* the whole segment is < rcv_nxt */ - /* must be a duplicate of a packet that has already been correctly handled */ - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); - tcp_ack_now(pcb); - } - } - - /* The sequence number must be within the window (above rcv_nxt - and below rcv_nxt + rcv_wnd) in order to be further - processed. */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, - pcb->rcv_nxt + pcb->rcv_wnd - 1)) { - if (pcb->rcv_nxt == seqno) { - /* The incoming segment is the next in sequence. We check if - we have to trim the end of the segment and update rcv_nxt - and pass the data to the application. */ - tcplen = TCP_TCPLEN(&inseg); - - if (tcplen > pcb->rcv_wnd) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, - ("tcp_receive: other end overran receive window" - "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", - seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - /* Must remove the FIN from the header as we're trimming - * that byte of sequence-space from the packet */ - TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN); - } - /* Adjust length of segment to fit in the window. */ - TCPWND_CHECK16(pcb->rcv_wnd); - inseg.len = (u16_t)pcb->rcv_wnd; - if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { - inseg.len -= 1; - } - pbuf_realloc(inseg.p, inseg.len); - tcplen = TCP_TCPLEN(&inseg); - LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", - (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); - } -#if TCP_QUEUE_OOSEQ - /* Received in-sequence data, adjust ooseq data if: - - FIN has been received or - - inseq overlaps with ooseq */ - if (pcb->ooseq != NULL) { - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, - ("tcp_receive: received in-order FIN, binning ooseq queue\n")); - /* Received in-order FIN means anything that was received - * out of order must now have been received in-order, so - * bin the ooseq queue */ - while (pcb->ooseq != NULL) { - struct tcp_seg *old_ooseq = pcb->ooseq; - pcb->ooseq = pcb->ooseq->next; - tcp_seg_free(old_ooseq); - } - } else { - next = pcb->ooseq; - /* Remove all segments on ooseq that are covered by inseg already. - * FIN is copied from ooseq to inseg if present. */ - while (next && - TCP_SEQ_GEQ(seqno + tcplen, - next->tcphdr->seqno + next->len)) { - /* inseg cannot have FIN here (already processed above) */ - if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && - (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { - TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); - tcplen = TCP_TCPLEN(&inseg); - } - prev = next; - next = next->next; - tcp_seg_free(prev); - } - /* Now trim right side of inseg if it overlaps with the first - * segment on ooseq */ - if (next && - TCP_SEQ_GT(seqno + tcplen, - next->tcphdr->seqno)) { - /* inseg cannot have FIN here (already processed above) */ - inseg.len = (u16_t)(next->tcphdr->seqno - seqno); - if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { - inseg.len -= 1; - } - pbuf_realloc(inseg.p, inseg.len); - tcplen = TCP_TCPLEN(&inseg); - LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", - (seqno + tcplen) == next->tcphdr->seqno); - } - pcb->ooseq = next; - } - } -#endif /* TCP_QUEUE_OOSEQ */ - - pcb->rcv_nxt = seqno + tcplen; - - /* Update the receiver's (our) window. */ - LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); - pcb->rcv_wnd -= tcplen; - - tcp_update_rcv_ann_wnd(pcb); - - /* If there is data in the segment, we make preparations to - pass this up to the application. The ->recv_data variable - is used for holding the pbuf that goes to the - application. The code for reassembling out-of-sequence data - chains its data on this pbuf as well. - - If the segment was a FIN, we set the TF_GOT_FIN flag that will - be used to indicate to the application that the remote side has - closed its end of the connection. */ - if (inseg.p->tot_len > 0) { - recv_data = inseg.p; - /* Since this pbuf now is the responsibility of the - application, we delete our reference to it so that we won't - (mistakingly) deallocate it. */ - inseg.p = NULL; - } - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); - recv_flags |= TF_GOT_FIN; - } - -#if TCP_QUEUE_OOSEQ - /* We now check if we have segments on the ->ooseq queue that - are now in sequence. */ - while (pcb->ooseq != NULL && - pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { - - cseg = pcb->ooseq; - seqno = pcb->ooseq->tcphdr->seqno; - - pcb->rcv_nxt += TCP_TCPLEN(cseg); - LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", - pcb->rcv_wnd >= TCP_TCPLEN(cseg)); - pcb->rcv_wnd -= TCP_TCPLEN(cseg); - - tcp_update_rcv_ann_wnd(pcb); - - if (cseg->p->tot_len > 0) { - /* Chain this pbuf onto the pbuf that we will pass to - the application. */ - /* With window scaling, this can overflow recv_data->tot_len, but - that's not a problem since we explicitly fix that before passing - recv_data to the application. */ - if (recv_data) { - pbuf_cat(recv_data, cseg->p); - } else { - recv_data = cseg->p; - } - cseg->p = NULL; - } - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); - recv_flags |= TF_GOT_FIN; - if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ - pcb->state = CLOSE_WAIT; - } - } - - pcb->ooseq = cseg->next; - tcp_seg_free(cseg); - } -#endif /* TCP_QUEUE_OOSEQ */ - - - /* Acknowledge the segment(s). */ - tcp_ack(pcb); - -#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS - if (ip_current_is_v6()) { - /* Inform neighbor reachability of forward progress. */ - nd6_reachability_hint(ip6_current_src_addr()); - } -#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ - - } else { - /* We get here if the incoming segment is out-of-sequence. */ - tcp_send_empty_ack(pcb); -#if TCP_QUEUE_OOSEQ - /* We queue the segment on the ->ooseq queue. */ - if (pcb->ooseq == NULL) { - pcb->ooseq = tcp_seg_copy(&inseg); - } else { - /* If the queue is not empty, we walk through the queue and - try to find a place where the sequence number of the - incoming segment is between the sequence numbers of the - previous and the next segment on the ->ooseq queue. That is - the place where we put the incoming segment. If needed, we - trim the second edges of the previous and the incoming - segment so that it will fit into the sequence. - - If the incoming segment has the same sequence number as a - segment on the ->ooseq queue, we discard the segment that - contains less data. */ - - prev = NULL; - for (next = pcb->ooseq; next != NULL; next = next->next) { - if (seqno == next->tcphdr->seqno) { - /* The sequence number of the incoming segment is the - same as the sequence number of the segment on - ->ooseq. We check the lengths to see which one to - discard. */ - if (inseg.len > next->len) { - /* The incoming segment is larger than the old - segment. We replace some segments with the new - one. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - if (prev != NULL) { - prev->next = cseg; - } else { - pcb->ooseq = cseg; - } - tcp_oos_insert_segment(cseg, next); - } - break; - } else { - /* Either the lengths are the same or the incoming - segment was smaller than the old one; in either - case, we ditch the incoming segment. */ - break; - } - } else { - if (prev == NULL) { - if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { - /* The sequence number of the incoming segment is lower - than the sequence number of the first segment on the - queue. We put the incoming segment first on the - queue. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - pcb->ooseq = cseg; - tcp_oos_insert_segment(cseg, next); - } - break; - } - } else { - /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && - TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ - if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) { - /* The sequence number of the incoming segment is in - between the sequence numbers of the previous and - the next segment on ->ooseq. We trim trim the previous - segment, delete next segments that included in received segment - and trim received, if needed. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { - /* We need to trim the prev segment. */ - prev->len = (u16_t)(seqno - prev->tcphdr->seqno); - pbuf_realloc(prev->p, prev->len); - } - prev->next = cseg; - tcp_oos_insert_segment(cseg, next); - } - break; - } - } - /* If the "next" segment is the last segment on the - ooseq queue, we add the incoming segment to the end - of the list. */ - if (next->next == NULL && - TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { - if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { - /* segment "next" already contains all data */ - break; - } - next->next = tcp_seg_copy(&inseg); - if (next->next != NULL) { - if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { - /* We need to trim the last segment. */ - next->len = (u16_t)(seqno - next->tcphdr->seqno); - pbuf_realloc(next->p, next->len); - } - /* check if the remote side overruns our receive window */ - if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, - ("tcp_receive: other end overran receive window" - "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", - seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); - if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { - /* Must remove the FIN from the header as we're trimming - * that byte of sequence-space from the packet */ - TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN); - } - /* Adjust length of segment to fit in the window. */ - next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno); - pbuf_realloc(next->next->p, next->next->len); - tcplen = TCP_TCPLEN(next->next); - LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", - (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); - } - } - break; - } - } - prev = next; - } - } -#if TCP_OOSEQ_MAX_BYTES || TCP_OOSEQ_MAX_PBUFS - /* Check that the data on ooseq doesn't exceed one of the limits - and throw away everything above that limit. */ - ooseq_blen = 0; - ooseq_qlen = 0; - prev = NULL; - for (next = pcb->ooseq; next != NULL; prev = next, next = next->next) { - struct pbuf *p = next->p; - ooseq_blen += p->tot_len; - ooseq_qlen += pbuf_clen(p); - if ((ooseq_blen > TCP_OOSEQ_MAX_BYTES) || - (ooseq_qlen > TCP_OOSEQ_MAX_PBUFS)) { - /* too much ooseq data, dump this and everything after it */ - tcp_segs_free(next); - if (prev == NULL) { - /* first ooseq segment is too much, dump the whole queue */ - pcb->ooseq = NULL; - } else { - /* just dump 'next' and everything after it */ - prev->next = NULL; - } - break; - } - } -#endif /* TCP_OOSEQ_MAX_BYTES || TCP_OOSEQ_MAX_PBUFS */ -#endif /* TCP_QUEUE_OOSEQ */ - } - } else { - /* The incoming segment is not within the window. */ - tcp_send_empty_ack(pcb); - } - } else { - /* Segments with length 0 is taken care of here. Segments that - fall out of the window are ACKed. */ - if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) { - tcp_ack_now(pcb); - } - } -} - -static u8_t -tcp_getoptbyte(void) -{ - if ((tcphdr_opt2 == NULL) || (tcp_optidx < tcphdr_opt1len)) { - u8_t* opts = (u8_t *)tcphdr + TCP_HLEN; - return opts[tcp_optidx++]; - } else { - u8_t idx = (u8_t)(tcp_optidx++ - tcphdr_opt1len); - return tcphdr_opt2[idx]; - } -} - -/** - * Parses the options contained in the incoming segment. - * - * Called from tcp_listen_input() and tcp_process(). - * Currently, only the MSS option is supported! - * - * @param pcb the tcp_pcb for which a segment arrived - */ -static void -tcp_parseopt(struct tcp_pcb *pcb) -{ - u8_t data; - u16_t mss; -#if LWIP_TCP_TIMESTAMPS - u32_t tsval; -#endif - - /* Parse the TCP MSS option, if present. */ - if (tcphdr_optlen != 0) { - for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { - u8_t opt = tcp_getoptbyte(); - switch (opt) { - case LWIP_TCP_OPT_EOL: - /* End of options. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); - return; - case LWIP_TCP_OPT_NOP: - /* NOP option. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); - break; - case LWIP_TCP_OPT_MSS: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); - if (tcp_getoptbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) { - /* Bad length */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - return; - } - /* An MSS option with the right option length. */ - mss = (tcp_getoptbyte() << 8); - mss |= tcp_getoptbyte(); - /* Limit the mss to the configured TCP_MSS and prevent division by zero */ - pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; - break; -#if LWIP_WND_SCALE - case LWIP_TCP_OPT_WS: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: WND_SCALE\n")); - if (tcp_getoptbyte() != LWIP_TCP_OPT_LEN_WS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_WS) > tcphdr_optlen) { - /* Bad length */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - return; - } - /* If syn was received with wnd scale option, - activate wnd scale opt, but only if this is not a retransmission */ - if ((flags & TCP_SYN) && !(pcb->flags & TF_WND_SCALE)) { - /* An WND_SCALE option with the right option length. */ - data = tcp_getoptbyte(); - pcb->snd_scale = data; - if (pcb->snd_scale > 14U) { - pcb->snd_scale = 14U; - } - pcb->rcv_scale = TCP_RCV_SCALE; - pcb->flags |= TF_WND_SCALE; - /* window scaling is enabled, we can use the full receive window */ - LWIP_ASSERT("window not at default value", pcb->rcv_wnd == TCPWND_MIN16(TCP_WND)); - LWIP_ASSERT("window not at default value", pcb->rcv_ann_wnd == TCPWND_MIN16(TCP_WND)); - pcb->rcv_wnd = pcb->rcv_ann_wnd = TCP_WND; - } - break; -#endif -#if LWIP_TCP_TIMESTAMPS - case LWIP_TCP_OPT_TS: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n")); - if (tcp_getoptbyte() != LWIP_TCP_OPT_LEN_TS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_TS) > tcphdr_optlen) { - /* Bad length */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - return; - } - /* TCP timestamp option with valid length */ - tsval = tcp_getoptbyte(); - tsval |= (tcp_getoptbyte() << 8); - tsval |= (tcp_getoptbyte() << 16); - tsval |= (tcp_getoptbyte() << 24); - if (flags & TCP_SYN) { - pcb->ts_recent = lwip_ntohl(tsval); - /* Enable sending timestamps in every segment now that we know - the remote host supports it. */ - pcb->flags |= TF_TIMESTAMP; - } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) { - pcb->ts_recent = lwip_ntohl(tsval); - } - /* Advance to next option (6 bytes already read) */ - tcp_optidx += LWIP_TCP_OPT_LEN_TS - 6; - break; -#endif - default: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); - data = tcp_getoptbyte(); - if (data < 2) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - /* If the length field is zero, the options are malformed - and we don't process them further. */ - return; - } - /* All other options have a length field, so that we easily - can skip past them. */ - tcp_optidx += data - 2; - } - } - } -} - -void -tcp_trigger_input_pcb_close(void) -{ - recv_flags |= TF_CLOSED; -} - -#endif /* LWIP_TCP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_out.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_out.c deleted file mode 100644 index 8603555c1e000d7d1d4c9ab19ac8925129024e0a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/tcp_out.c +++ /dev/null @@ -1,1742 +0,0 @@ -/** - * @file - * Transmission Control Protocol, outgoing traffic - * - * The output functions of TCP. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/priv/tcp_priv.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet_chksum.h" -#include "lwip/stats.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#if LWIP_TCP_TIMESTAMPS -#include "lwip/sys.h" -#endif - -#include - -/* Define some copy-macros for checksum-on-copy so that the code looks - nicer by preventing too many ifdef's. */ -#if TCP_CHECKSUM_ON_COPY -#define TCP_DATA_COPY(dst, src, len, seg) do { \ - tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), \ - len, &seg->chksum, &seg->chksum_swapped); \ - seg->flags |= TF_SEG_DATA_CHECKSUMMED; } while(0) -#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) \ - tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), len, chksum, chksum_swapped); -#else /* TCP_CHECKSUM_ON_COPY*/ -#define TCP_DATA_COPY(dst, src, len, seg) MEMCPY(dst, src, len) -#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) MEMCPY(dst, src, len) -#endif /* TCP_CHECKSUM_ON_COPY*/ - -/** Define this to 1 for an extra check that the output checksum is valid - * (usefule when the checksum is generated by the application, not the stack) */ -#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK -#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK 0 -#endif -/* Allow to override the failure of sanity check from warning to e.g. hard failure */ -#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK -#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL -#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL(msg) LWIP_DEBUGF(TCP_DEBUG | LWIP_DBG_LEVEL_WARNING, msg) -#endif -#endif - -#if TCP_OVERSIZE -/** The size of segment pbufs created when TCP_OVERSIZE is enabled */ -#ifndef TCP_OVERSIZE_CALC_LENGTH -#define TCP_OVERSIZE_CALC_LENGTH(length) ((length) + TCP_OVERSIZE) -#endif -#endif - -/* Forward declarations.*/ -static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif); - -/** Allocate a pbuf and create a tcphdr at p->payload, used for output - * functions other than the default tcp_output -> tcp_output_segment - * (e.g. tcp_send_empty_ack, etc.) - * - * @param pcb tcp pcb for which to send a packet (used to initialize tcp_hdr) - * @param optlen length of header-options - * @param datalen length of tcp data to reserve in pbuf - * @param seqno_be seqno in network byte order (big-endian) - * @return pbuf with p->payload being the tcp_hdr - */ -static struct pbuf * -tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, - u32_t seqno_be /* already in network byte order */) -{ - struct tcp_hdr *tcphdr; - struct pbuf *p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); - if (p != NULL) { - LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", - (p->len >= TCP_HLEN + optlen)); - tcphdr = (struct tcp_hdr *)p->payload; - tcphdr->src = lwip_htons(pcb->local_port); - tcphdr->dest = lwip_htons(pcb->remote_port); - tcphdr->seqno = seqno_be; - tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); - TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), TCP_ACK); - tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); - tcphdr->chksum = 0; - tcphdr->urgp = 0; - - /* If we're sending a packet, update the announced right window edge */ - pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; - } - return p; -} - -/** - * Called by tcp_close() to send a segment including FIN flag but not data. - * - * @param pcb the tcp_pcb over which to send a segment - * @return ERR_OK if sent, another err_t otherwise - */ -err_t -tcp_send_fin(struct tcp_pcb *pcb) -{ - /* first, try to add the fin to the last unsent segment */ - if (pcb->unsent != NULL) { - struct tcp_seg *last_unsent; - for (last_unsent = pcb->unsent; last_unsent->next != NULL; - last_unsent = last_unsent->next); - - if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { - /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ - TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); - pcb->flags |= TF_FIN; - return ERR_OK; - } - } - /* no data, no length, flags, copy=1, no optdata */ - return tcp_enqueue_flags(pcb, TCP_FIN); -} - -/** - * Create a TCP segment with prefilled header. - * - * Called by tcp_write and tcp_enqueue_flags. - * - * @param pcb Protocol control block for the TCP connection. - * @param p pbuf that is used to hold the TCP header. - * @param flags TCP flags for header. - * @param seqno TCP sequence number of this packet - * @param optflags options to include in TCP header - * @return a new tcp_seg pointing to p, or NULL. - * The TCP header is filled in except ackno and wnd. - * p is freed on failure. - */ -static struct tcp_seg * -tcp_create_segment(struct tcp_pcb *pcb, struct pbuf *p, u8_t flags, u32_t seqno, u8_t optflags) -{ - struct tcp_seg *seg; - u8_t optlen = LWIP_TCP_OPT_LENGTH(optflags); - - if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n")); - pbuf_free(p); - return NULL; - } - seg->flags = optflags; - seg->next = NULL; - seg->p = p; - LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen); - seg->len = p->tot_len - optlen; -#if TCP_OVERSIZE_DBGCHECK - seg->oversize_left = 0; -#endif /* TCP_OVERSIZE_DBGCHECK */ -#if TCP_CHECKSUM_ON_COPY - seg->chksum = 0; - seg->chksum_swapped = 0; - /* check optflags */ - LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", - (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); -#endif /* TCP_CHECKSUM_ON_COPY */ - - /* build TCP header */ - if (pbuf_header(p, TCP_HLEN)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n")); - TCP_STATS_INC(tcp.err); - tcp_seg_free(seg); - return NULL; - } - seg->tcphdr = (struct tcp_hdr *)seg->p->payload; - seg->tcphdr->src = lwip_htons(pcb->local_port); - seg->tcphdr->dest = lwip_htons(pcb->remote_port); - seg->tcphdr->seqno = lwip_htonl(seqno); - /* ackno is set in tcp_output */ - TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), flags); - /* wnd and chksum are set in tcp_output */ - seg->tcphdr->urgp = 0; - return seg; -} - -/** - * Allocate a PBUF_RAM pbuf, perhaps with extra space at the end. - * - * This function is like pbuf_alloc(layer, length, PBUF_RAM) except - * there may be extra bytes available at the end. - * - * @param layer flag to define header size. - * @param length size of the pbuf's payload. - * @param max_length maximum usable size of payload+oversize. - * @param oversize pointer to a u16_t that will receive the number of usable tail bytes. - * @param pcb The TCP connection that will enqueue the pbuf. - * @param apiflags API flags given to tcp_write. - * @param first_seg true when this pbuf will be used in the first enqueued segment. - */ -#if TCP_OVERSIZE -static struct pbuf * -tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length, - u16_t *oversize, struct tcp_pcb *pcb, u8_t apiflags, - u8_t first_seg) -{ - struct pbuf *p; - u16_t alloc = length; - -#if LWIP_NETIF_TX_SINGLE_PBUF - LWIP_UNUSED_ARG(max_length); - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(apiflags); - LWIP_UNUSED_ARG(first_seg); - alloc = max_length; -#else /* LWIP_NETIF_TX_SINGLE_PBUF */ - if (length < max_length) { - /* Should we allocate an oversized pbuf, or just the minimum - * length required? If tcp_write is going to be called again - * before this segment is transmitted, we want the oversized - * buffer. If the segment will be transmitted immediately, we can - * save memory by allocating only length. We use a simple - * heuristic based on the following information: - * - * Did the user set TCP_WRITE_FLAG_MORE? - * - * Will the Nagle algorithm defer transmission of this segment? - */ - if ((apiflags & TCP_WRITE_FLAG_MORE) || - (!(pcb->flags & TF_NODELAY) && - (!first_seg || - pcb->unsent != NULL || - pcb->unacked != NULL))) { - alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length))); - } - } -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - p = pbuf_alloc(layer, alloc, PBUF_RAM); - if (p == NULL) { - return NULL; - } - LWIP_ASSERT("need unchained pbuf", p->next == NULL); - *oversize = p->len - length; - /* trim p->len to the currently used size */ - p->len = p->tot_len = length; - return p; -} -#else /* TCP_OVERSIZE */ -#define tcp_pbuf_prealloc(layer, length, mx, os, pcb, api, fst) pbuf_alloc((layer), (length), PBUF_RAM) -#endif /* TCP_OVERSIZE */ - -#if TCP_CHECKSUM_ON_COPY -/** Add a checksum of newly added data to the segment */ -static void -tcp_seg_add_chksum(u16_t chksum, u16_t len, u16_t *seg_chksum, - u8_t *seg_chksum_swapped) -{ - u32_t helper; - /* add chksum to old chksum and fold to u16_t */ - helper = chksum + *seg_chksum; - chksum = FOLD_U32T(helper); - if ((len & 1) != 0) { - *seg_chksum_swapped = 1 - *seg_chksum_swapped; - chksum = SWAP_BYTES_IN_WORD(chksum); - } - *seg_chksum = chksum; -} -#endif /* TCP_CHECKSUM_ON_COPY */ - -/** Checks if tcp_write is allowed or not (checks state, snd_buf and snd_queuelen). - * - * @param pcb the tcp pcb to check for - * @param len length of data to send (checked agains snd_buf) - * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise - */ -static err_t -tcp_write_checks(struct tcp_pcb *pcb, u16_t len) -{ - /* connection is in invalid state for data transmission? */ - if ((pcb->state != ESTABLISHED) && - (pcb->state != CLOSE_WAIT) && - (pcb->state != SYN_SENT) && - (pcb->state != SYN_RCVD)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); - return ERR_CONN; - } else if (len == 0) { - return ERR_OK; - } - - /* fail on too much data */ - if (len > pcb->snd_buf) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n", - len, pcb->snd_buf)); - pcb->flags |= TF_NAGLEMEMERR; - return ERR_MEM; - } - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); - - /* If total number of pbufs on the unsent/unacked queues exceeds the - * configured maximum, return an error */ - /* check for configured max queuelen and possible overflow */ - if ((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n", - pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN)); - TCP_STATS_INC(tcp.memerr); - pcb->flags |= TF_NAGLEMEMERR; - return ERR_MEM; - } - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty", - pcb->unacked != NULL || pcb->unsent != NULL); - } else { - LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty", - pcb->unacked == NULL && pcb->unsent == NULL); - } - return ERR_OK; -} - -/** - * @ingroup tcp_raw - * Write data for sending (but does not send it immediately). - * - * It waits in the expectation of more data being sent soon (as - * it can send them more efficiently by combining them together). - * To prompt the system to send data now, call tcp_output() after - * calling tcp_write(). - * - * @param pcb Protocol control block for the TCP connection to enqueue data for. - * @param arg Pointer to the data to be enqueued for sending. - * @param len Data length in bytes - * @param apiflags combination of following flags : - * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack - * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent, - * @return ERR_OK if enqueued, another err_t on error - */ -err_t -tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags) -{ - struct pbuf *concat_p = NULL; - struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL; - u16_t pos = 0; /* position in 'arg' data */ - u16_t queuelen; - u8_t optlen = 0; - u8_t optflags = 0; -#if TCP_OVERSIZE - u16_t oversize = 0; - u16_t oversize_used = 0; -#if TCP_OVERSIZE_DBGCHECK - u16_t oversize_add = 0; -#endif /* TCP_OVERSIZE_DBGCHECK*/ -#endif /* TCP_OVERSIZE */ - u16_t extendlen = 0; -#if TCP_CHECKSUM_ON_COPY - u16_t concat_chksum = 0; - u8_t concat_chksum_swapped = 0; - u16_t concat_chksummed = 0; -#endif /* TCP_CHECKSUM_ON_COPY */ - err_t err; - /* don't allocate segments bigger than half the maximum window we ever received */ - u16_t mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max/2)); - mss_local = mss_local ? mss_local : pcb->mss; - -#if LWIP_NETIF_TX_SINGLE_PBUF - /* Always copy to try to create single pbufs for TX */ - apiflags |= TCP_WRITE_FLAG_COPY; -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", - (void *)pcb, arg, len, (u16_t)apiflags)); - LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", - arg != NULL, return ERR_ARG;); - - err = tcp_write_checks(pcb, len); - if (err != ERR_OK) { - return err; - } - queuelen = pcb->snd_queuelen; - -#if LWIP_TCP_TIMESTAMPS - if ((pcb->flags & TF_TIMESTAMP)) { - /* Make sure the timestamp option is only included in data segments if we - agreed about it with the remote host. */ - optflags = TF_SEG_OPTS_TS; - optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); - /* ensure that segments can hold at least one data byte... */ - mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1); - } -#endif /* LWIP_TCP_TIMESTAMPS */ - - - /* - * TCP segmentation is done in three phases with increasing complexity: - * - * 1. Copy data directly into an oversized pbuf. - * 2. Chain a new pbuf to the end of pcb->unsent. - * 3. Create new segments. - * - * We may run out of memory at any point. In that case we must - * return ERR_MEM and not change anything in pcb. Therefore, all - * changes are recorded in local variables and committed at the end - * of the function. Some pcb fields are maintained in local copies: - * - * queuelen = pcb->snd_queuelen - * oversize = pcb->unsent_oversize - * - * These variables are set consistently by the phases: - * - * seg points to the last segment tampered with. - * - * pos records progress as data is segmented. - */ - - /* Find the tail of the unsent queue. */ - if (pcb->unsent != NULL) { - u16_t space; - u16_t unsent_optlen; - - /* @todo: this could be sped up by keeping last_unsent in the pcb */ - for (last_unsent = pcb->unsent; last_unsent->next != NULL; - last_unsent = last_unsent->next); - - /* Usable space at the end of the last unsent segment */ - unsent_optlen = LWIP_TCP_OPT_LENGTH(last_unsent->flags); - LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen); - space = mss_local - (last_unsent->len + unsent_optlen); - - /* - * Phase 1: Copy data directly into an oversized pbuf. - * - * The number of bytes copied is recorded in the oversize_used - * variable. The actual copying is done at the bottom of the - * function. - */ -#if TCP_OVERSIZE -#if TCP_OVERSIZE_DBGCHECK - /* check that pcb->unsent_oversize matches last_unsent->oversize_left */ - LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)", - pcb->unsent_oversize == last_unsent->oversize_left); -#endif /* TCP_OVERSIZE_DBGCHECK */ - oversize = pcb->unsent_oversize; - if (oversize > 0) { - LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space); - seg = last_unsent; - oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len)); - pos += oversize_used; - oversize -= oversize_used; - space -= oversize_used; - } - /* now we are either finished or oversize is zero */ - LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len)); -#endif /* TCP_OVERSIZE */ - - /* - * Phase 2: Chain a new pbuf to the end of pcb->unsent. - * - * As an exception when NOT copying the data, if the given data buffer - * directly follows the last unsent data buffer in memory, extend the last - * ROM pbuf reference to the buffer, thus saving a ROM pbuf allocation. - * - * We don't extend segments containing SYN/FIN flags or options - * (len==0). The new pbuf is kept in concat_p and pbuf_cat'ed at - * the end. - */ - if ((pos < len) && (space > 0) && (last_unsent->len > 0)) { - u16_t seglen = LWIP_MIN(space, len - pos); - seg = last_unsent; - - /* Create a pbuf with a copy or reference to seglen bytes. We - * can use PBUF_RAW here since the data appears in the middle of - * a segment. A header will never be prepended. */ - if (apiflags & TCP_WRITE_FLAG_COPY) { - /* Data is copied */ - if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", - seglen)); - goto memerr; - } -#if TCP_OVERSIZE_DBGCHECK - oversize_add = oversize; -#endif /* TCP_OVERSIZE_DBGCHECK */ - TCP_DATA_COPY2(concat_p->payload, (const u8_t*)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped); -#if TCP_CHECKSUM_ON_COPY - concat_chksummed += seglen; -#endif /* TCP_CHECKSUM_ON_COPY */ - queuelen += pbuf_clen(concat_p); - } else { - /* Data is not copied */ - /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */ - struct pbuf *p; - for (p = last_unsent->p; p->next != NULL; p = p->next); - if (p->type == PBUF_ROM && (const u8_t *)p->payload + p->len == (const u8_t *)arg) { - LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0); - extendlen = seglen; - } else { - if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_write: could not allocate memory for zero-copy pbuf\n")); - goto memerr; - } - /* reference the non-volatile payload data */ - ((struct pbuf_rom*)concat_p)->payload = (const u8_t*)arg + pos; - queuelen += pbuf_clen(concat_p); - } -#if TCP_CHECKSUM_ON_COPY - /* calculate the checksum of nocopy-data */ - tcp_seg_add_chksum(~inet_chksum((const u8_t*)arg + pos, seglen), seglen, - &concat_chksum, &concat_chksum_swapped); - concat_chksummed += seglen; -#endif /* TCP_CHECKSUM_ON_COPY */ - } - - pos += seglen; - } - } else { -#if TCP_OVERSIZE - LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)", - pcb->unsent_oversize == 0); -#endif /* TCP_OVERSIZE */ - } - - /* - * Phase 3: Create new segments. - * - * The new segments are chained together in the local 'queue' - * variable, ready to be appended to pcb->unsent. - */ - while (pos < len) { - struct pbuf *p; - u16_t left = len - pos; - u16_t max_len = mss_local - optlen; - u16_t seglen = LWIP_MIN(left, max_len); -#if TCP_CHECKSUM_ON_COPY - u16_t chksum = 0; - u8_t chksum_swapped = 0; -#endif /* TCP_CHECKSUM_ON_COPY */ - - if (apiflags & TCP_WRITE_FLAG_COPY) { - /* If copy is set, memory should be allocated and data copied - * into pbuf */ - if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); - goto memerr; - } - LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen", - (p->len >= seglen)); - TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t*)arg + pos, seglen, &chksum, &chksum_swapped); - } else { - /* Copy is not set: First allocate a pbuf for holding the data. - * Since the referenced data is available at least until it is - * sent out on the link (as it has to be ACKed by the remote - * party) we can safely use PBUF_ROM instead of PBUF_REF here. - */ - struct pbuf *p2; -#if TCP_OVERSIZE - LWIP_ASSERT("oversize == 0", oversize == 0); -#endif /* TCP_OVERSIZE */ - if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for zero-copy pbuf\n")); - goto memerr; - } -#if TCP_CHECKSUM_ON_COPY - /* calculate the checksum of nocopy-data */ - chksum = ~inet_chksum((const u8_t*)arg + pos, seglen); - if (seglen & 1) { - chksum_swapped = 1; - chksum = SWAP_BYTES_IN_WORD(chksum); - } -#endif /* TCP_CHECKSUM_ON_COPY */ - /* reference the non-volatile payload data */ - ((struct pbuf_rom*)p2)->payload = (const u8_t*)arg + pos; - - /* Second, allocate a pbuf for the headers. */ - if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { - /* If allocation fails, we have to deallocate the data pbuf as - * well. */ - pbuf_free(p2); - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n")); - goto memerr; - } - /* Concatenate the headers and data pbufs together. */ - pbuf_cat(p/*header*/, p2/*data*/); - } - - queuelen += pbuf_clen(p); - - /* Now that there are more segments queued, we check again if the - * length of the queue exceeds the configured maximum or - * overflows. */ - if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n", - queuelen, (int)TCP_SND_QUEUELEN)); - pbuf_free(p); - goto memerr; - } - - if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) { - goto memerr; - } -#if TCP_OVERSIZE_DBGCHECK - seg->oversize_left = oversize; -#endif /* TCP_OVERSIZE_DBGCHECK */ -#if TCP_CHECKSUM_ON_COPY - seg->chksum = chksum; - seg->chksum_swapped = chksum_swapped; - seg->flags |= TF_SEG_DATA_CHECKSUMMED; -#endif /* TCP_CHECKSUM_ON_COPY */ - - /* first segment of to-be-queued data? */ - if (queue == NULL) { - queue = seg; - } else { - /* Attach the segment to the end of the queued segments */ - LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL); - prev_seg->next = seg; - } - /* remember last segment of to-be-queued data for next iteration */ - prev_seg = seg; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n", - lwip_ntohl(seg->tcphdr->seqno), - lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg))); - - pos += seglen; - } - - /* - * All three segmentation phases were successful. We can commit the - * transaction. - */ -#if TCP_OVERSIZE_DBGCHECK - if ((last_unsent != NULL) && (oversize_add != 0)) { - last_unsent->oversize_left += oversize_add; - } -#endif /* TCP_OVERSIZE_DBGCHECK */ - - /* - * Phase 1: If data has been added to the preallocated tail of - * last_unsent, we update the length fields of the pbuf chain. - */ -#if TCP_OVERSIZE - if (oversize_used > 0) { - struct pbuf *p; - /* Bump tot_len of whole chain, len of tail */ - for (p = last_unsent->p; p; p = p->next) { - p->tot_len += oversize_used; - if (p->next == NULL) { - TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent); - p->len += oversize_used; - } - } - last_unsent->len += oversize_used; -#if TCP_OVERSIZE_DBGCHECK - LWIP_ASSERT("last_unsent->oversize_left >= oversize_used", - last_unsent->oversize_left >= oversize_used); - last_unsent->oversize_left -= oversize_used; -#endif /* TCP_OVERSIZE_DBGCHECK */ - } - pcb->unsent_oversize = oversize; -#endif /* TCP_OVERSIZE */ - - /* - * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we - * determined that the last ROM pbuf can be extended to include the new data. - */ - if (concat_p != NULL) { - LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty", - (last_unsent != NULL)); - pbuf_cat(last_unsent->p, concat_p); - last_unsent->len += concat_p->tot_len; - } else if (extendlen > 0) { - struct pbuf *p; - LWIP_ASSERT("tcp_write: extension of reference requires reference", - last_unsent != NULL && last_unsent->p != NULL); - for (p = last_unsent->p; p->next != NULL; p = p->next) { - p->tot_len += extendlen; - } - p->tot_len += extendlen; - p->len += extendlen; - last_unsent->len += extendlen; - } - -#if TCP_CHECKSUM_ON_COPY - if (concat_chksummed) { - LWIP_ASSERT("tcp_write: concat checksum needs concatenated data", - concat_p != NULL || extendlen > 0); - /*if concat checksumm swapped - swap it back */ - if (concat_chksum_swapped) { - concat_chksum = SWAP_BYTES_IN_WORD(concat_chksum); - } - tcp_seg_add_chksum(concat_chksum, concat_chksummed, &last_unsent->chksum, - &last_unsent->chksum_swapped); - last_unsent->flags |= TF_SEG_DATA_CHECKSUMMED; - } -#endif /* TCP_CHECKSUM_ON_COPY */ - - /* - * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that - * is harmless - */ - if (last_unsent == NULL) { - pcb->unsent = queue; - } else { - last_unsent->next = queue; - } - - /* - * Finally update the pcb state. - */ - pcb->snd_lbb += len; - pcb->snd_buf -= len; - pcb->snd_queuelen = queuelen; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n", - pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_write: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - /* Set the PSH flag in the last segment that we enqueued. */ - if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) { - TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); - } - - return ERR_OK; -memerr: - pcb->flags |= TF_NAGLEMEMERR; - TCP_STATS_INC(tcp.memerr); - - if (concat_p != NULL) { - pbuf_free(concat_p); - } - if (queue != NULL) { - tcp_segs_free(queue); - } - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); - return ERR_MEM; -} - -/** - * Enqueue TCP options for transmission. - * - * Called by tcp_connect(), tcp_listen_input(), and tcp_send_ctrl(). - * - * @param pcb Protocol control block for the TCP connection. - * @param flags TCP header flags to set in the outgoing segment. - */ -err_t -tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) -{ - struct pbuf *p; - struct tcp_seg *seg; - u8_t optflags = 0; - u8_t optlen = 0; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - - LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", - (flags & (TCP_SYN | TCP_FIN)) != 0); - - /* check for configured max queuelen and possible overflow (FIN flag should always come through!) */ - if (((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) && - ((flags & TCP_FIN) == 0)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_enqueue_flags: too long queue %"U16_F" (max %"U16_F")\n", - pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN)); - TCP_STATS_INC(tcp.memerr); - pcb->flags |= TF_NAGLEMEMERR; - return ERR_MEM; - } - - if (flags & TCP_SYN) { - optflags = TF_SEG_OPTS_MSS; -#if LWIP_WND_SCALE - if ((pcb->state != SYN_RCVD) || (pcb->flags & TF_WND_SCALE)) { - /* In a (sent in state SYN_RCVD), the window scale option may only - be sent if we received a window scale option from the remote host. */ - optflags |= TF_SEG_OPTS_WND_SCALE; - } -#endif /* LWIP_WND_SCALE */ - } -#if LWIP_TCP_TIMESTAMPS - if ((pcb->flags & TF_TIMESTAMP)) { - /* Make sure the timestamp option is only included in data segments if we - agreed about it with the remote host. */ - optflags |= TF_SEG_OPTS_TS; - } -#endif /* LWIP_TCP_TIMESTAMPS */ - optlen = LWIP_TCP_OPT_LENGTH(optflags); - - /* Allocate pbuf with room for TCP header + options */ - if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { - pcb->flags |= TF_NAGLEMEMERR; - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", - (p->len >= optlen)); - - /* Allocate memory for tcp_seg, and fill in fields. */ - if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { - pcb->flags |= TF_NAGLEMEMERR; - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0); - LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, - ("tcp_enqueue_flags: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", - lwip_ntohl(seg->tcphdr->seqno), - lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), - (u16_t)flags)); - - /* Now append seg to pcb->unsent queue */ - if (pcb->unsent == NULL) { - pcb->unsent = seg; - } else { - struct tcp_seg *useg; - for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); - useg->next = seg; - } -#if TCP_OVERSIZE - /* The new unsent tail has no space */ - pcb->unsent_oversize = 0; -#endif /* TCP_OVERSIZE */ - - /* SYN and FIN bump the sequence number */ - if ((flags & TCP_SYN) || (flags & TCP_FIN)) { - pcb->snd_lbb++; - /* optlen does not influence snd_buf */ - } - if (flags & TCP_FIN) { - pcb->flags |= TF_FIN; - } - - /* update number of segments on the queues */ - pcb->snd_queuelen += pbuf_clen(seg->p); - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - return ERR_OK; -} - -#if LWIP_TCP_TIMESTAMPS -/* Build a timestamp option (12 bytes long) at the specified options pointer) - * - * @param pcb tcp_pcb - * @param opts option pointer where to store the timestamp option - */ -static void -tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts) -{ - /* Pad with two NOP options to make everything nicely aligned */ - opts[0] = PP_HTONL(0x0101080A); - opts[1] = lwip_htonl(sys_now()); - opts[2] = lwip_htonl(pcb->ts_recent); -} -#endif - -#if LWIP_WND_SCALE -/** Build a window scale option (3 bytes long) at the specified options pointer) - * - * @param opts option pointer where to store the window scale option - */ -static void -tcp_build_wnd_scale_option(u32_t *opts) -{ - /* Pad with one NOP option to make everything nicely aligned */ - opts[0] = PP_HTONL(0x01030300 | TCP_RCV_SCALE); -} -#endif - -/** - * Send an ACK without data. - * - * @param pcb Protocol control block for the TCP connection to send the ACK - */ -err_t -tcp_send_empty_ack(struct tcp_pcb *pcb) -{ - err_t err; - struct pbuf *p; - u8_t optlen = 0; - struct netif *netif; -#if LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP - struct tcp_hdr *tcphdr; -#endif /* LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP */ - -#if LWIP_TCP_TIMESTAMPS - if (pcb->flags & TF_TIMESTAMP) { - optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); - } -#endif - - p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt)); - if (p == NULL) { - /* let tcp_fasttmr retry sending this ACK */ - pcb->flags |= (TF_ACK_DELAY | TF_ACK_NOW); - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); - return ERR_BUF; - } -#if LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP - tcphdr = (struct tcp_hdr *)p->payload; -#endif /* LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP */ - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, - ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); - - /* NB. MSS and window scale options are only sent on SYNs, so ignore them here */ -#if LWIP_TCP_TIMESTAMPS - pcb->ts_lastacksent = pcb->rcv_nxt; - - if (pcb->flags & TF_TIMESTAMP) { - tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1)); - } -#endif - - netif = ip_route(&pcb->local_ip, &pcb->remote_ip); - if (netif == NULL) { - err = ERR_RTE; - } else { -#if CHECKSUM_GEN_TCP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { - tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - &pcb->local_ip, &pcb->remote_ip); - } -#endif - NETIF_SET_HWADDRHINT(netif, &(pcb->addr_hint)); - err = ip_output_if(p, &pcb->local_ip, &pcb->remote_ip, - pcb->ttl, pcb->tos, IP_PROTO_TCP, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - } - pbuf_free(p); - - if (err != ERR_OK) { - /* let tcp_fasttmr retry sending this ACK */ - pcb->flags |= (TF_ACK_DELAY | TF_ACK_NOW); - } else { - /* remove ACK flags from the PCB, as we sent an empty ACK now */ - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - - return err; -} - -/** - * @ingroup tcp_raw - * Find out what we can send and send it - * - * @param pcb Protocol control block for the TCP connection to send data - * @return ERR_OK if data has been sent or nothing to send - * another err_t on error - */ -err_t -tcp_output(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg, *useg; - u32_t wnd, snd_nxt; - err_t err; - struct netif *netif; -#if TCP_CWND_DEBUG - s16_t i = 0; -#endif /* TCP_CWND_DEBUG */ - - /* pcb->state LISTEN not allowed here */ - LWIP_ASSERT("don't call tcp_output for listen-pcbs", - pcb->state != LISTEN); - - /* First, check if we are invoked by the TCP input processing - code. If so, we do not output anything. Instead, we rely on the - input processing code to call us when input processing is done - with. */ - if (tcp_input_pcb == pcb) { - return ERR_OK; - } - - wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); - - seg = pcb->unsent; - - /* If the TF_ACK_NOW flag is set and no data will be sent (either - * because the ->unsent queue is empty or because the window does - * not allow it), construct an empty ACK segment and send it. - * - * If data is to be sent, we will just piggyback the ACK (see below). - */ - if (pcb->flags & TF_ACK_NOW && - (seg == NULL || - lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { - return tcp_send_empty_ack(pcb); - } - - /* useg should point to last segment on unacked queue */ - useg = pcb->unacked; - if (useg != NULL) { - for (; useg->next != NULL; useg = useg->next); - } - - netif = ip_route(&pcb->local_ip, &pcb->remote_ip); - if (netif == NULL) { - return ERR_RTE; - } - - /* If we don't have a local IP address, we get one from netif */ - if (ip_addr_isany(&pcb->local_ip)) { - const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip); - if (local_ip == NULL) { - return ERR_RTE; - } - ip_addr_copy(pcb->local_ip, *local_ip); - } - -#if TCP_OUTPUT_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", - (void*)pcb->unsent)); - } -#endif /* TCP_OUTPUT_DEBUG */ -#if TCP_CWND_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F - ", cwnd %"TCPWNDSIZE_F", wnd %"U32_F - ", seg == NULL, ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); - } else { - LWIP_DEBUGF(TCP_CWND_DEBUG, - ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F - ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, - lwip_ntohl(seg->tcphdr->seqno), pcb->lastack)); - } -#endif /* TCP_CWND_DEBUG */ - /* Check if we need to start the persistent timer when the next unsent segment - * does not fit within the remaining send window and RTO timer is not running (we - * have no in-flight data). A traditional approach would fill the remaining window - * with part of the unsent segment (which will engage zero-window probing upon - * reception of the zero window update from the receiver). This ensures the - * subsequent window update is reliably received. With the goal of being lightweight, - * we avoid splitting the unsent segment and treat the window as already zero. - */ - if (seg != NULL && - lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd && - wnd > 0 && wnd == pcb->snd_wnd && pcb->unacked == NULL) { - /* Start the persist timer */ - if (pcb->persist_backoff == 0) { - pcb->persist_cnt = 0; - pcb->persist_backoff = 1; - } - goto output_done; - } - /* data available and window allows it to be sent? */ - while (seg != NULL && - lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { - LWIP_ASSERT("RST not expected here!", - (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0); - /* Stop sending if the nagle algorithm would prevent it - * Don't stop: - * - if tcp_write had a memory error before (prevent delayed ACK timeout) or - * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - - * either seg->next != NULL or pcb->unacked == NULL; - * RST is no sent using tcp_write/tcp_output. - */ - if ((tcp_do_output_nagle(pcb) == 0) && - ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) { - break; - } -#if TCP_CWND_DEBUG - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - lwip_ntohl(seg->tcphdr->seqno) + seg->len - - pcb->lastack, - lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i)); - ++i; -#endif /* TCP_CWND_DEBUG */ - - if (pcb->state != SYN_SENT) { - TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); - } - -#if TCP_OVERSIZE_DBGCHECK - seg->oversize_left = 0; -#endif /* TCP_OVERSIZE_DBGCHECK */ - err = tcp_output_segment(seg, pcb, netif); - if (err != ERR_OK) { - /* segment could not be sent, for whatever reason */ - pcb->flags |= TF_NAGLEMEMERR; - return err; - } - pcb->unsent = seg->next; - if (pcb->state != SYN_SENT) { - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); - if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { - pcb->snd_nxt = snd_nxt; - } - /* put segment on unacknowledged list if length > 0 */ - if (TCP_TCPLEN(seg) > 0) { - seg->next = NULL; - /* unacked list is empty? */ - if (pcb->unacked == NULL) { - pcb->unacked = seg; - useg = seg; - /* unacked list is not empty? */ - } else { - /* In the case of fast retransmit, the packet should not go to the tail - * of the unacked queue, but rather somewhere before it. We need to check for - * this case. -STJ Jul 27, 2004 */ - if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) { - /* add segment to before tail of unacked list, keeping the list sorted */ - struct tcp_seg **cur_seg = &(pcb->unacked); - while (*cur_seg && - TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { - cur_seg = &((*cur_seg)->next ); - } - seg->next = (*cur_seg); - (*cur_seg) = seg; - } else { - /* add segment to tail of unacked list */ - useg->next = seg; - useg = useg->next; - } - } - /* do not queue empty segments on the unacked list */ - } else { - tcp_seg_free(seg); - } - seg = pcb->unsent; - } -output_done: -#if TCP_OVERSIZE - if (pcb->unsent == NULL) { - /* last unsent has been removed, reset unsent_oversize */ - pcb->unsent_oversize = 0; - } -#endif /* TCP_OVERSIZE */ - - pcb->flags &= ~TF_NAGLEMEMERR; - return ERR_OK; -} - -/** Check if a segment's pbufs are used by someone else than TCP. - * This can happen on retransmission if the pbuf of this segment is still - * referenced by the netif driver due to deferred transmission. - * This is the case (only!) if someone down the TX call path called - * pbuf_ref() on one of the pbufs! - * - * @arg seg the tcp segment to check - * @return 1 if ref != 1, 0 if ref == 1 - */ -static int -tcp_output_segment_busy(const struct tcp_seg *seg) -{ - LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL); - - /* We only need to check the first pbuf here: - If a pbuf is queued for transmission, a driver calls pbuf_ref(), - which only changes the ref count of the first pbuf */ - if (seg->p->ref != 1) { - /* other reference found */ - return 1; - } - /* no other references found */ - return 0; -} - -/** - * Called by tcp_output() to actually send a TCP segment over IP. - * - * @param seg the tcp_seg to send - * @param pcb the tcp_pcb for the TCP connection used to send the segment - * @param netif the netif used to send the segment - */ -static err_t -tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif) -{ - err_t err; - u16_t len; - u32_t *opts; - - if (seg->p->ref != 1) { - /* This can happen if the pbuf of this segment is still referenced by the - netif driver due to deferred transmission. Since this function modifies - p->len, we must not continue in this case. */ - return ERR_OK; - } - - /* The TCP header has already been constructed, but the ackno and - wnd fields remain. */ - seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); - - /* advertise our receive window size in this TCP segment */ -#if LWIP_WND_SCALE - if (seg->flags & TF_SEG_OPTS_WND_SCALE) { - /* The Window field in a SYN segment itself (the only type where we send - the window scale option) is never scaled. */ - seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd)); - } else -#endif /* LWIP_WND_SCALE */ - { - seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); - } - - pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; - - /* Add any requested options. NB MSS option is only set on SYN - packets, so ignore it here */ - /* cast through void* to get rid of alignment warnings */ - opts = (u32_t *)(void *)(seg->tcphdr + 1); - if (seg->flags & TF_SEG_OPTS_MSS) { - u16_t mss; -#if TCP_CALCULATE_EFF_SEND_MSS - mss = tcp_eff_send_mss(TCP_MSS, &pcb->local_ip, &pcb->remote_ip); -#else /* TCP_CALCULATE_EFF_SEND_MSS */ - mss = TCP_MSS; -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - *opts = TCP_BUILD_MSS_OPTION(mss); - opts += 1; - } -#if LWIP_TCP_TIMESTAMPS - pcb->ts_lastacksent = pcb->rcv_nxt; - - if (seg->flags & TF_SEG_OPTS_TS) { - tcp_build_timestamp_option(pcb, opts); - opts += 3; - } -#endif -#if LWIP_WND_SCALE - if (seg->flags & TF_SEG_OPTS_WND_SCALE) { - tcp_build_wnd_scale_option(opts); - opts += 1; - } -#endif - - /* Set retransmission timer running if it is not currently enabled - This must be set before checking the route. */ - if (pcb->rtime < 0) { - pcb->rtime = 0; - } - - if (pcb->rttest == 0) { - pcb->rttest = tcp_ticks; - pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", - lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) + - seg->len)); - - len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); - if (len == 0) { - /** Exclude retransmitted segments from this count. */ - MIB2_STATS_INC(mib2.tcpoutsegs); - } - - seg->p->len -= len; - seg->p->tot_len -= len; - - seg->p->payload = seg->tcphdr; - - seg->tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { -#if TCP_CHECKSUM_ON_COPY - u32_t acc; -#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK - u16_t chksum_slow = ip_chksum_pseudo(seg->p, IP_PROTO_TCP, - seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip); -#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ - if ((seg->flags & TF_SEG_DATA_CHECKSUMMED) == 0) { - LWIP_ASSERT("data included but not checksummed", - seg->p->tot_len == (TCPH_HDRLEN(seg->tcphdr) * 4)); - } - - /* rebuild TCP header checksum (TCP header changes for retransmissions!) */ - acc = ip_chksum_pseudo_partial(seg->p, IP_PROTO_TCP, - seg->p->tot_len, TCPH_HDRLEN(seg->tcphdr) * 4, &pcb->local_ip, &pcb->remote_ip); - /* add payload checksum */ - if (seg->chksum_swapped) { - seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); - seg->chksum_swapped = 0; - } - acc += (u16_t)~(seg->chksum); - seg->tcphdr->chksum = FOLD_U32T(acc); -#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK - if (chksum_slow != seg->tcphdr->chksum) { - TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL( - ("tcp_output_segment: calculated checksum is %"X16_F" instead of %"X16_F"\n", - seg->tcphdr->chksum, chksum_slow)); - seg->tcphdr->chksum = chksum_slow; - } -#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ -#else /* TCP_CHECKSUM_ON_COPY */ - seg->tcphdr->chksum = ip_chksum_pseudo(seg->p, IP_PROTO_TCP, - seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip); -#endif /* TCP_CHECKSUM_ON_COPY */ - } -#endif /* CHECKSUM_GEN_TCP */ - TCP_STATS_INC(tcp.xmit); - - NETIF_SET_HWADDRHINT(netif, &(pcb->addr_hint)); - err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, - pcb->tos, IP_PROTO_TCP, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - return err; -} - -/** - * Send a TCP RESET packet (empty segment with RST flag set) either to - * abort a connection or to show that there is no matching local connection - * for a received segment. - * - * Called by tcp_abort() (to abort a local connection), tcp_input() (if no - * matching local pcb was found), tcp_listen_input() (if incoming segment - * has ACK flag set) and tcp_process() (received segment in the wrong state) - * - * Since a RST segment is in most cases not sent for an active connection, - * tcp_rst() has a number of arguments that are taken from a tcp_pcb for - * most other segment output functions. - * - * @param seqno the sequence number to use for the outgoing segment - * @param ackno the acknowledge number to use for the outgoing segment - * @param local_ip the local IP address to send the segment from - * @param remote_ip the remote IP address to send the segment to - * @param local_port the local TCP port to send the segment from - * @param remote_port the remote TCP port to send the segment to - */ -void -tcp_rst(u32_t seqno, u32_t ackno, - const ip_addr_t *local_ip, const ip_addr_t *remote_ip, - u16_t local_port, u16_t remote_port) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - struct netif *netif; - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); - return; - } - LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", - (p->len >= sizeof(struct tcp_hdr))); - - tcphdr = (struct tcp_hdr *)p->payload; - tcphdr->src = lwip_htons(local_port); - tcphdr->dest = lwip_htons(remote_port); - tcphdr->seqno = lwip_htonl(seqno); - tcphdr->ackno = lwip_htonl(ackno); - TCPH_HDRLEN_FLAGS_SET(tcphdr, TCP_HLEN/4, TCP_RST | TCP_ACK); -#if LWIP_WND_SCALE - tcphdr->wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF)); -#else - tcphdr->wnd = PP_HTONS(TCP_WND); -#endif - tcphdr->chksum = 0; - tcphdr->urgp = 0; - - TCP_STATS_INC(tcp.xmit); - MIB2_STATS_INC(mib2.tcpoutrsts); - - netif = ip_route(local_ip, remote_ip); - if (netif != NULL) { -#if CHECKSUM_GEN_TCP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { - tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - local_ip, remote_ip); - } -#endif - /* Send output with hardcoded TTL/HL since we have no access to the pcb */ - ip_output_if(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP, netif); - } - pbuf_free(p); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); -} - -/** - * Requeue all unacked segments for retransmission - * - * Called by tcp_slowtmr() for slow retransmission. - * - * @param pcb the tcp_pcb for which to re-enqueue all unacked segments - */ -err_t -tcp_rexmit_rto_prepare(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL); - - if (pcb->unacked == NULL) { - return ERR_VAL; - } - - /* Move all unacked segments to the head of the unsent queue. - However, give up if any of the unsent pbufs are still referenced by the - netif driver due to deferred transmission. No point loading the link further - if it is struggling to flush its buffered writes. */ - for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { - if (tcp_output_segment_busy(seg)) { - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); - return ERR_VAL; - } - } - if (tcp_output_segment_busy(seg)) { - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); - return ERR_VAL; - } - /* concatenate unsent queue after unacked queue */ - seg->next = pcb->unsent; -#if TCP_OVERSIZE_DBGCHECK - /* if last unsent changed, we need to update unsent_oversize */ - if (pcb->unsent == NULL) { - pcb->unsent_oversize = seg->oversize_left; - } -#endif /* TCP_OVERSIZE_DBGCHECK */ - /* unsent queue is the concatenated queue (of unacked, unsent) */ - pcb->unsent = pcb->unacked; - /* unacked queue is now empty */ - pcb->unacked = NULL; - - /* Don't take any RTT measurements after retransmitting. */ - pcb->rttest = 0; - - return ERR_OK; -} - -/** - * Requeue all unacked segments for retransmission - * - * Called by tcp_slowtmr() for slow retransmission. - * - * @param pcb the tcp_pcb for which to re-enqueue all unacked segments - */ -void -tcp_rexmit_rto_commit(struct tcp_pcb *pcb) -{ - LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL); - - /* increment number of retransmissions */ - if (pcb->nrtx < 0xFF) { - ++pcb->nrtx; - } - /* Do the actual retransmission */ - tcp_output(pcb); -} - -/** - * Requeue all unacked segments for retransmission - * - * Called by tcp_process() only, tcp_slowtmr() needs to do some things between - * "prepare" and "commit". - * - * @param pcb the tcp_pcb for which to re-enqueue all unacked segments - */ -void -tcp_rexmit_rto(struct tcp_pcb *pcb) -{ - LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL); - - if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) { - tcp_rexmit_rto_commit(pcb); - } -} - -/** - * Requeue the first unacked segment for retransmission - * - * Called by tcp_receive() for fast retransmit. - * - * @param pcb the tcp_pcb for which to retransmit the first unacked segment - */ -void -tcp_rexmit(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - struct tcp_seg **cur_seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move the first unacked segment to the unsent queue */ - /* Keep the unsent queue sorted. */ - seg = pcb->unacked; - pcb->unacked = seg->next; - - cur_seg = &(pcb->unsent); - while (*cur_seg && - TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { - cur_seg = &((*cur_seg)->next ); - } - seg->next = *cur_seg; - *cur_seg = seg; -#if TCP_OVERSIZE - if (seg->next == NULL) { - /* the retransmitted segment is last in unsent, so reset unsent_oversize */ - pcb->unsent_oversize = 0; - } -#endif /* TCP_OVERSIZE */ - - if (pcb->nrtx < 0xFF) { - ++pcb->nrtx; - } - - /* Don't take any rtt measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission. */ - MIB2_STATS_INC(mib2.tcpretranssegs); - /* No need to call tcp_output: we are always called from tcp_input() - and thus tcp_output directly returns. */ -} - - -/** - * Handle retransmission after three dupacks received - * - * @param pcb the tcp_pcb for which to retransmit the first unacked segment - */ -void -tcp_rexmit_fast(struct tcp_pcb *pcb) -{ - if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { - /* This is fast retransmit. Retransmit the first unacked segment. */ - LWIP_DEBUGF(TCP_FR_DEBUG, - ("tcp_receive: dupacks %"U16_F" (%"U32_F - "), fast retransmit %"U32_F"\n", - (u16_t)pcb->dupacks, pcb->lastack, - lwip_ntohl(pcb->unacked->tcphdr->seqno))); - tcp_rexmit(pcb); - - /* Set ssthresh to half of the minimum of the current - * cwnd and the advertised window */ - pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2; - - /* The minimum value for ssthresh should be 2 MSS */ - if (pcb->ssthresh < (2U * pcb->mss)) { - LWIP_DEBUGF(TCP_FR_DEBUG, - ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F - " should be min 2 mss %"U16_F"...\n", - pcb->ssthresh, (u16_t)(2*pcb->mss))); - pcb->ssthresh = 2*pcb->mss; - } - - pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; - pcb->flags |= TF_INFR; - - /* Reset the retransmission timer to prevent immediate rto retransmissions */ - pcb->rtime = 0; - } -} - - -/** - * Send keepalive packets to keep a connection active although - * no data is sent over it. - * - * Called by tcp_slowtmr() - * - * @param pcb the tcp_pcb for which to send a keepalive packet - */ -err_t -tcp_keepalive(struct tcp_pcb *pcb) -{ - err_t err; - struct pbuf *p; - struct netif *netif; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to ")); - ip_addr_debug_print(TCP_DEBUG, &pcb->remote_ip); - LWIP_DEBUGF(TCP_DEBUG, ("\n")); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", - tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); - - p = tcp_output_alloc_header(pcb, 0, 0, lwip_htonl(pcb->snd_nxt - 1)); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, - ("tcp_keepalive: could not allocate memory for pbuf\n")); - return ERR_MEM; - } - netif = ip_route(&pcb->local_ip, &pcb->remote_ip); - if (netif == NULL) { - err = ERR_RTE; - } else { -#if CHECKSUM_GEN_TCP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { - struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload; - tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - &pcb->local_ip, &pcb->remote_ip); - } -#endif /* CHECKSUM_GEN_TCP */ - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ - NETIF_SET_HWADDRHINT(netif, &(pcb->addr_hint)); - err = ip_output_if(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - } - pbuf_free(p); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n", - pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); - return err; -} - - -/** - * Send persist timer zero-window probes to keep a connection active - * when a window update is lost. - * - * Called by tcp_slowtmr() - * - * @param pcb the tcp_pcb for which to send a zero-window probe packet - */ -err_t -tcp_zero_window_probe(struct tcp_pcb *pcb) -{ - err_t err; - struct pbuf *p; - struct tcp_hdr *tcphdr; - struct tcp_seg *seg; - u16_t len; - u8_t is_fin; - u32_t snd_nxt; - struct netif *netif; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: sending ZERO WINDOW probe to ")); - ip_addr_debug_print(TCP_DEBUG, &pcb->remote_ip); - LWIP_DEBUGF(TCP_DEBUG, ("\n")); - - LWIP_DEBUGF(TCP_DEBUG, - ("tcp_zero_window_probe: tcp_ticks %"U32_F - " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", - tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); - - seg = pcb->unacked; - - if (seg == NULL) { - seg = pcb->unsent; - } - if (seg == NULL) { - /* nothing to send, zero window probe not needed */ - return ERR_OK; - } - - is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); - /* we want to send one seqno: either FIN or data (no options) */ - len = is_fin ? 0 : 1; - - p = tcp_output_alloc_header(pcb, 0, len, seg->tcphdr->seqno); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); - return ERR_MEM; - } - tcphdr = (struct tcp_hdr *)p->payload; - - if (is_fin) { - /* FIN segment, no data */ - TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); - } else { - /* Data segment, copy in one byte from the head of the unacked queue */ - char *d = ((char *)p->payload + TCP_HLEN); - /* Depending on whether the segment has already been sent (unacked) or not - (unsent), seg->p->payload points to the IP header or TCP header. - Ensure we copy the first TCP data byte: */ - pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len); - } - - /* The byte may be acknowledged without the window being opened. */ - snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1; - if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { - pcb->snd_nxt = snd_nxt; - } - - netif = ip_route(&pcb->local_ip, &pcb->remote_ip); - if (netif == NULL) { - err = ERR_RTE; - } else { -#if CHECKSUM_GEN_TCP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { - tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - &pcb->local_ip, &pcb->remote_ip); - } -#endif - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ - NETIF_SET_HWADDRHINT(netif, &(pcb->addr_hint)); - err = ip_output_if(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, - 0, IP_PROTO_TCP, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - } - - pbuf_free(p); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F - " ackno %"U32_F" err %d.\n", - pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); - return err; -} -#endif /* LWIP_TCP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/timeouts.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/timeouts.c deleted file mode 100644 index ed98979cb104abf299ad06f79b36fa5f63cd98d2..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/timeouts.c +++ /dev/null @@ -1,432 +0,0 @@ -/** - * @file - * Stack-internal timers implementation. - * This file includes timer callbacks for stack-internal timers as well as - * functions to set up or stop timers and check for expired timers. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Simon Goldschmidt - * - */ - -#include "lwip/opt.h" - -#include "lwip/timeouts.h" -#include "lwip/priv/tcp_priv.h" - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/priv/tcpip_priv.h" - -#include "lwip/ip4_frag.h" -#include "lwip/etharp.h" -#include "lwip/dhcp.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" -#include "lwip/nd6.h" -#include "lwip/ip6_frag.h" -#include "lwip/mld6.h" -#include "lwip/sys.h" -#include "lwip/pbuf.h" - -#if LWIP_DEBUG_TIMERNAMES -#define HANDLER(x) x, #x -#else /* LWIP_DEBUG_TIMERNAMES */ -#define HANDLER(x) x -#endif /* LWIP_DEBUG_TIMERNAMES */ - -/** This array contains all stack-internal cyclic timers. To get the number of - * timers, use LWIP_ARRAYSIZE() */ -const struct lwip_cyclic_timer lwip_cyclic_timers[] = { -#if LWIP_TCP - /* The TCP timer is a special case: it does not have to run always and - is triggered to start from TCP using tcp_timer_needed() */ - {TCP_TMR_INTERVAL, HANDLER(tcp_tmr)}, -#endif /* LWIP_TCP */ -#if LWIP_IPV4 -#if IP_REASSEMBLY - {IP_TMR_INTERVAL, HANDLER(ip_reass_tmr)}, -#endif /* IP_REASSEMBLY */ -#if LWIP_ARP - {ARP_TMR_INTERVAL, HANDLER(etharp_tmr)}, -#endif /* LWIP_ARP */ -#if LWIP_DHCP - {DHCP_COARSE_TIMER_MSECS, HANDLER(dhcp_coarse_tmr)}, - {DHCP_FINE_TIMER_MSECS, HANDLER(dhcp_fine_tmr)}, -#endif /* LWIP_DHCP */ -#if LWIP_AUTOIP - {AUTOIP_TMR_INTERVAL, HANDLER(autoip_tmr)}, -#endif /* LWIP_AUTOIP */ -#if LWIP_IGMP - {IGMP_TMR_INTERVAL, HANDLER(igmp_tmr)}, -#endif /* LWIP_IGMP */ -#endif /* LWIP_IPV4 */ -#if LWIP_DNS - {DNS_TMR_INTERVAL, HANDLER(dns_tmr)}, -#endif /* LWIP_DNS */ -#if LWIP_IPV6 - {ND6_TMR_INTERVAL, HANDLER(nd6_tmr)}, -#if LWIP_IPV6_REASS - {IP6_REASS_TMR_INTERVAL, HANDLER(ip6_reass_tmr)}, -#endif /* LWIP_IPV6_REASS */ -#if LWIP_IPV6_MLD - {MLD6_TMR_INTERVAL, HANDLER(mld6_tmr)}, -#endif /* LWIP_IPV6_MLD */ -#endif /* LWIP_IPV6 */ -}; - -#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM - -/** The one and only timeout list */ -static struct sys_timeo *next_timeout; -static u32_t timeouts_last_time; - -#if LWIP_TCP -/** global variable that shows if the tcp timer is currently scheduled or not */ -static int tcpip_tcp_timer_active; - -/** - * Timer callback function that calls tcp_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -tcpip_tcp_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - - /* call TCP timer handler */ - tcp_tmr(); - /* timer still needed? */ - if (tcp_active_pcbs || tcp_tw_pcbs) { - /* restart timer */ - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } else { - /* disable timer */ - tcpip_tcp_timer_active = 0; - } -} - -/** - * Called from TCP_REG when registering a new PCB: - * the reason is to have the TCP timer only running when - * there are active (or time-wait) PCBs. - */ -void -tcp_timer_needed(void) -{ - /* timer is off but needed again? */ - if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { - /* enable and start timer */ - tcpip_tcp_timer_active = 1; - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } -} -#endif /* LWIP_TCP */ - -/** - * Timer callback function that calls mld6_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -cyclic_timer(void *arg) -{ - const struct lwip_cyclic_timer* cyclic = (const struct lwip_cyclic_timer*)arg; -#if LWIP_DEBUG_TIMERNAMES - LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); -#endif - cyclic->handler(); - sys_timeout(cyclic->interval_ms, cyclic_timer, arg); -} - -/** Initialize this module */ -void sys_timeouts_init(void) -{ - size_t i; - /* tcp_tmr() at index 0 is started on demand */ - for (i = 1; i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { - /* we have to cast via size_t to get rid of const warning - (this is OK as cyclic_timer() casts back to const* */ - sys_timeout(lwip_cyclic_timers[i].interval_ms, cyclic_timer, LWIP_CONST_CAST(void*, &lwip_cyclic_timers[i])); - } - - /* Initialise timestamp for sys_check_timeouts */ - timeouts_last_time = sys_now(); -} - -/** - * Create a one-shot timer (aka timeout). Timeouts are processed in the - * following cases: - * - while waiting for a message using sys_timeouts_mbox_fetch() - * - by calling sys_check_timeouts() (NO_SYS==1 only) - * - * @param msecs time in milliseconds after that the timer should expire - * @param handler callback function to call when msecs have elapsed - * @param arg argument to pass to the callback function - */ -#if LWIP_DEBUG_TIMERNAMES -void -sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name) -#else /* LWIP_DEBUG_TIMERNAMES */ -void -sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) -#endif /* LWIP_DEBUG_TIMERNAMES */ -{ - struct sys_timeo *timeout, *t; - u32_t now, diff; - - timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); - if (timeout == NULL) { - LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); - return; - } - - now = sys_now(); - if (next_timeout == NULL) { - diff = 0; - timeouts_last_time = now; - } else { - diff = now - timeouts_last_time; - } - - timeout->next = NULL; - timeout->h = handler; - timeout->arg = arg; - timeout->time = msecs + diff; -#if LWIP_DEBUG_TIMERNAMES - timeout->handler_name = handler_name; - LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" handler=%s arg=%p\n", - (void *)timeout, msecs, handler_name, (void *)arg)); -#endif /* LWIP_DEBUG_TIMERNAMES */ - - if (next_timeout == NULL) { - next_timeout = timeout; - return; - } - - if (next_timeout->time > msecs) { - next_timeout->time -= msecs; - timeout->next = next_timeout; - next_timeout = timeout; - } else { - for (t = next_timeout; t != NULL; t = t->next) { - timeout->time -= t->time; - if (t->next == NULL || t->next->time > timeout->time) { - if (t->next != NULL) { - t->next->time -= timeout->time; - } else if (timeout->time > msecs) { - /* If this is the case, 'timeouts_last_time' and 'now' differs too much. - This can be due to sys_check_timeouts() not being called at the right - times, but also when stopping in a breakpoint. Anyway, let's assume - this is not wanted, so add the first timer's time instead of 'diff' */ - timeout->time = msecs + next_timeout->time; - } - timeout->next = t->next; - t->next = timeout; - break; - } - } - } -} - -/** - * Go through timeout list (for this task only) and remove the first matching - * entry (subsequent entries remain untouched), even though the timeout has not - * triggered yet. - * - * @param handler callback function that would be called by the timeout - * @param arg callback argument that would be passed to handler -*/ -void -sys_untimeout(sys_timeout_handler handler, void *arg) -{ - struct sys_timeo *prev_t, *t; - - if (next_timeout == NULL) { - return; - } - - for (t = next_timeout, prev_t = NULL; t != NULL; prev_t = t, t = t->next) { - if ((t->h == handler) && (t->arg == arg)) { - /* We have a match */ - /* Unlink from previous in list */ - if (prev_t == NULL) { - next_timeout = t->next; - } else { - prev_t->next = t->next; - } - /* If not the last one, add time of this one back to next */ - if (t->next != NULL) { - t->next->time += t->time; - } - memp_free(MEMP_SYS_TIMEOUT, t); - return; - } - } - return; -} - -/** - * @ingroup lwip_nosys - * Handle timeouts for NO_SYS==1 (i.e. without using - * tcpip_thread/sys_timeouts_mbox_fetch(). Uses sys_now() to call timeout - * handler functions when timeouts expire. - * - * Must be called periodically from your main loop. - */ -#if !NO_SYS && !defined __DOXYGEN__ -static -#endif /* !NO_SYS */ -void -sys_check_timeouts(void) -{ - if (next_timeout) { - struct sys_timeo *tmptimeout; - u32_t diff; - sys_timeout_handler handler; - void *arg; - u8_t had_one; - u32_t now; - - now = sys_now(); - /* this cares for wraparounds */ - diff = now - timeouts_last_time; - do { - PBUF_CHECK_FREE_OOSEQ(); - had_one = 0; - tmptimeout = next_timeout; - if (tmptimeout && (tmptimeout->time <= diff)) { - /* timeout has expired */ - had_one = 1; - timeouts_last_time += tmptimeout->time; - diff -= tmptimeout->time; - next_timeout = tmptimeout->next; - handler = tmptimeout->h; - arg = tmptimeout->arg; -#if LWIP_DEBUG_TIMERNAMES - if (handler != NULL) { - LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s arg=%p\n", - tmptimeout->handler_name, arg)); - } -#endif /* LWIP_DEBUG_TIMERNAMES */ - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (handler != NULL) { -#if !NO_SYS - /* For LWIP_TCPIP_CORE_LOCKING, lock the core before calling the - timeout handler function. */ - LOCK_TCPIP_CORE(); -#endif /* !NO_SYS */ - handler(arg); -#if !NO_SYS - UNLOCK_TCPIP_CORE(); -#endif /* !NO_SYS */ - } - LWIP_TCPIP_THREAD_ALIVE(); - } - /* repeat until all expired timers have been called */ - } while (had_one); - } -} - -/** Set back the timestamp of the last call to sys_check_timeouts() - * This is necessary if sys_check_timeouts() hasn't been called for a long - * time (e.g. while saving energy) to prevent all timer functions of that - * period being called. - */ -void -sys_restart_timeouts(void) -{ - timeouts_last_time = sys_now(); -} - -/** Return the time left before the next timeout is due. If no timeouts are - * enqueued, returns 0xffffffff - */ -#if !NO_SYS -static -#endif /* !NO_SYS */ -u32_t -sys_timeouts_sleeptime(void) -{ - u32_t diff; - if (next_timeout == NULL) { - return 0xffffffff; - } - diff = sys_now() - timeouts_last_time; - if (diff > next_timeout->time) { - return 0; - } else { - return next_timeout->time - diff; - } -} - -#if !NO_SYS - -/** - * Wait (forever) for a message to arrive in an mbox. - * While waiting, timeouts are processed. - * - * @param mbox the mbox to fetch the message from - * @param msg the place to store the message - */ -void -sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg) -{ - u32_t sleeptime; - -again: - if (!next_timeout) { - sys_arch_mbox_fetch(mbox, msg, 0); - return; - } - - sleeptime = sys_timeouts_sleeptime(); - if (sleeptime == 0 || sys_arch_mbox_fetch(mbox, msg, sleeptime) == SYS_ARCH_TIMEOUT) { - /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred - before a message could be fetched. */ - sys_check_timeouts(); - /* We try again to fetch a message from the mbox. */ - goto again; - } -} - -#endif /* NO_SYS */ - -#else /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ -/* Satisfy the TCP code which calls this function */ -void -tcp_timer_needed(void) -{ -} -#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/udp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/udp.c deleted file mode 100644 index ce2e3d295ff8cba5be418366f2fbd4f35f26477d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/core/udp.c +++ /dev/null @@ -1,1191 +0,0 @@ -/** - * @file - * User Datagram Protocol module\n - * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).\n - * See also @ref udp_raw - * - * @defgroup udp_raw UDP - * @ingroup callbackstyle_api - * User Datagram Protocol module\n - * @see @ref raw_api and @ref netconn - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'! - */ - -#include "lwip/opt.h" - -#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/udp.h" -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet_chksum.h" -#include "lwip/ip_addr.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/icmp6.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/dhcp.h" - -#include - -#ifndef UDP_LOCAL_PORT_RANGE_START -/* From http://www.iana.org/assignments/port-numbers: - "The Dynamic and/or Private Ports are those from 49152 through 65535" */ -#define UDP_LOCAL_PORT_RANGE_START 0xc000 -#define UDP_LOCAL_PORT_RANGE_END 0xffff -#define UDP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & ~UDP_LOCAL_PORT_RANGE_START) + UDP_LOCAL_PORT_RANGE_START)) -#endif - -/* last local UDP port */ -static u16_t udp_port = UDP_LOCAL_PORT_RANGE_START; - -/* The list of UDP PCBs */ -/* exported in udp.h (was static) */ -struct udp_pcb *udp_pcbs; - -/** - * Initialize this module. - */ -void -udp_init(void) -{ -#if LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS && defined(LWIP_RAND) - udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); -#endif /* LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS && defined(LWIP_RAND) */ -} - -/** - * Allocate a new local UDP port. - * - * @return a new (free) local UDP port number - */ -static u16_t -udp_new_port(void) -{ - u16_t n = 0; - struct udp_pcb *pcb; - -again: - if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) { - udp_port = UDP_LOCAL_PORT_RANGE_START; - } - /* Check all PCBs. */ - for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == udp_port) { - if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) { - return 0; - } - goto again; - } - } - return udp_port; -} - -/** Common code to see if the current input packet matches the pcb - * (current input packet is accessed via ip(4/6)_current_* macros) - * - * @param pcb pcb to check - * @param inp network interface on which the datagram was received (only used for IPv4) - * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4) - * @return 1 on match, 0 otherwise - */ -static u8_t -udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast) -{ - LWIP_UNUSED_ARG(inp); /* in IPv6 only case */ - LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ - - /* Dual-stack: PCBs listening to any IP type also listen to any IP address */ - if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { -#if LWIP_IPV4 && IP_SOF_BROADCAST_RECV - if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) { - return 0; - } -#endif /* LWIP_IPV4 && IP_SOF_BROADCAST_RECV */ - return 1; - } - - /* Only need to check PCB if incoming IP version matches PCB IP version */ - if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { -#if LWIP_IPV4 - /* Special case: IPv4 broadcast: all or broadcasts in my subnet - * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ - if (broadcast != 0) { -#if IP_SOF_BROADCAST_RECV - if (ip_get_option(pcb, SOF_BROADCAST)) -#endif /* IP_SOF_BROADCAST_RECV */ - { - if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || - ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || - ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) { - return 1; - } - } - } else -#endif /* LWIP_IPV4 */ - /* Handle IPv4 and IPv6: all or exact match */ - if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { - return 1; - } - } - - return 0; -} - -/** - * Process an incoming UDP datagram. - * - * Given an incoming UDP datagram (as a chain of pbufs) this function - * finds a corresponding UDP PCB and hands over the pbuf to the pcbs - * recv function. If no pcb is found or the datagram is incorrect, the - * pbuf is freed. - * - * @param p pbuf to be demultiplexed to a UDP PCB (p->payload pointing to the UDP header) - * @param inp network interface on which the datagram was received. - * - */ -void -udp_input(struct pbuf *p, struct netif *inp) -{ - struct udp_hdr *udphdr; - struct udp_pcb *pcb, *prev; - struct udp_pcb *uncon_pcb; - u16_t src, dest; - u8_t broadcast; - u8_t for_us = 0; - - LWIP_UNUSED_ARG(inp); - - PERF_START; - - UDP_STATS_INC(udp.recv); - - /* Check minimum length (UDP header) */ - if (p->len < UDP_HLEN) { - /* drop short packets */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); - UDP_STATS_INC(udp.lenerr); - UDP_STATS_INC(udp.drop); - MIB2_STATS_INC(mib2.udpinerrors); - pbuf_free(p); - goto end; - } - - udphdr = (struct udp_hdr *)p->payload; - - /* is broadcast packet ? */ - broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); - - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); - - /* convert src and dest ports to host byte order */ - src = lwip_ntohs(udphdr->src); - dest = lwip_ntohs(udphdr->dest); - - udp_debug_print(udphdr); - - /* print the UDP source and destination */ - LWIP_DEBUGF(UDP_DEBUG, ("udp (")); - ip_addr_debug_print(UDP_DEBUG, ip_current_dest_addr()); - LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest))); - ip_addr_debug_print(UDP_DEBUG, ip_current_src_addr()); - LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src))); - - pcb = NULL; - prev = NULL; - uncon_pcb = NULL; - /* Iterate through the UDP pcb list for a matching pcb. - * 'Perfect match' pcbs (connected to the remote port & ip address) are - * preferred. If no perfect match is found, the first unconnected pcb that - * matches the local port and ip address gets the datagram. */ - for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { - /* print the PCB local and remote address */ - LWIP_DEBUGF(UDP_DEBUG, ("pcb (")); - ip_addr_debug_print(UDP_DEBUG, &pcb->local_ip); - LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port)); - ip_addr_debug_print(UDP_DEBUG, &pcb->remote_ip); - LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port)); - - /* compare PCB local addr+port to UDP destination addr+port */ - if ((pcb->local_port == dest) && - (udp_input_local_match(pcb, inp, broadcast) != 0)) { - if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) && - ((uncon_pcb == NULL) -#if SO_REUSE - /* prefer specific IPs over cath-all */ - || !ip_addr_isany(&pcb->local_ip) -#endif /* SO_REUSE */ - )) { - /* the first unconnected matching PCB */ - uncon_pcb = pcb; - } - - /* compare PCB remote addr+port to UDP source addr+port */ - if ((pcb->remote_port == src) && - (ip_addr_isany_val(pcb->remote_ip) || - ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { - /* the first fully matching PCB */ - if (prev != NULL) { - /* move the pcb to the front of udp_pcbs so that is - found faster next time */ - prev->next = pcb->next; - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } else { - UDP_STATS_INC(udp.cachehit); - } - break; - } - } - - prev = pcb; - } - /* no fully matching pcb found? then look for an unconnected pcb */ - if (pcb == NULL) { - pcb = uncon_pcb; - } - - /* Check checksum if this is a match or if it was directed at us. */ - if (pcb != NULL) { - for_us = 1; - } else { -#if LWIP_IPV6 - if (ip_current_is_v6()) { - for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0; - } -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 - if (!ip_current_is_v6()) { - for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr()); - } -#endif /* LWIP_IPV4 */ - } - - if (for_us) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n")); -#if CHECKSUM_CHECK_UDP - IF__NETIF_CHECKSUM_ENABLED(inp, CHECKSUM_CHECK_UDP) { -#if LWIP_UDPLITE - if (ip_current_header_proto() == IP_PROTO_UDPLITE) { - /* Do the UDP Lite checksum */ - u16_t chklen = lwip_ntohs(udphdr->len); - if (chklen < sizeof(struct udp_hdr)) { - if (chklen == 0) { - /* For UDP-Lite, checksum length of 0 means checksum - over the complete packet (See RFC 3828 chap. 3.1) */ - chklen = p->tot_len; - } else { - /* At least the UDP-Lite header must be covered by the - checksum! (Again, see RFC 3828 chap. 3.1) */ - goto chkerr; - } - } - if (ip_chksum_pseudo_partial(p, IP_PROTO_UDPLITE, - p->tot_len, chklen, - ip_current_src_addr(), ip_current_dest_addr()) != 0) { - goto chkerr; - } - } else -#endif /* LWIP_UDPLITE */ - { - if (udphdr->chksum != 0) { - if (ip_chksum_pseudo(p, IP_PROTO_UDP, p->tot_len, - ip_current_src_addr(), - ip_current_dest_addr()) != 0) { - goto chkerr; - } - } - } - } -#endif /* CHECKSUM_CHECK_UDP */ - if (pbuf_header(p, -UDP_HLEN)) { - /* Can we cope with this failing? Just assert for now */ - LWIP_ASSERT("pbuf_header failed\n", 0); - UDP_STATS_INC(udp.drop); - MIB2_STATS_INC(mib2.udpinerrors); - pbuf_free(p); - goto end; - } - - if (pcb != NULL) { - MIB2_STATS_INC(mib2.udpindatagrams); -#if SO_REUSE && SO_REUSE_RXTOALL - if (ip_get_option(pcb, SOF_REUSEADDR) && - (broadcast || ip_addr_ismulticast(ip_current_dest_addr()))) { - /* pass broadcast- or multicast packets to all multicast pcbs - if SOF_REUSEADDR is set on the first match */ - struct udp_pcb *mpcb; - u8_t p_header_changed = 0; - s16_t hdrs_len = (s16_t)(ip_current_header_tot_len() + UDP_HLEN); - for (mpcb = udp_pcbs; mpcb != NULL; mpcb = mpcb->next) { - if (mpcb != pcb) { - /* compare PCB local addr+port to UDP destination addr+port */ - if ((mpcb->local_port == dest) && - (udp_input_local_match(mpcb, inp, broadcast) != 0)) { - /* pass a copy of the packet to all local matches */ - if (mpcb->recv != NULL) { - struct pbuf *q; - /* for that, move payload to IP header again */ - if (p_header_changed == 0) { - pbuf_header_force(p, hdrs_len); - p_header_changed = 1; - } - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if (q != NULL) { - err_t err = pbuf_copy(q, p); - if (err == ERR_OK) { - /* move payload to UDP data */ - pbuf_header(q, -hdrs_len); - mpcb->recv(mpcb->recv_arg, mpcb, q, ip_current_src_addr(), src); - } - } - } - } - } - } - if (p_header_changed) { - /* and move payload to UDP data again */ - pbuf_header(p, -hdrs_len); - } - } -#endif /* SO_REUSE && SO_REUSE_RXTOALL */ - /* callback */ - if (pcb->recv != NULL) { - /* now the recv function is responsible for freeing p */ - pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); - } else { - /* no recv function registered? then we have to free the pbuf! */ - pbuf_free(p); - goto end; - } - } else { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n")); - -#if LWIP_ICMP || LWIP_ICMP6 - /* No match was found, send ICMP destination port unreachable unless - destination address was broadcast/multicast. */ - if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) { - /* move payload pointer back to ip header */ - pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN)); - icmp_port_unreach(ip_current_is_v6(), p); - } -#endif /* LWIP_ICMP || LWIP_ICMP6 */ - UDP_STATS_INC(udp.proterr); - UDP_STATS_INC(udp.drop); - MIB2_STATS_INC(mib2.udpnoports); - pbuf_free(p); - } - } else { - pbuf_free(p); - } -end: - PERF_STOP("udp_input"); - return; -#if CHECKSUM_CHECK_UDP -chkerr: - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("udp_input: UDP (or UDP Lite) datagram discarded due to failing checksum\n")); - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - MIB2_STATS_INC(mib2.udpinerrors); - pbuf_free(p); - PERF_STOP("udp_input"); -#endif /* CHECKSUM_CHECK_UDP */ -} - -/** - * @ingroup udp_raw - * Send data using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * - * The datagram will be sent to the current remote_ip & remote_port - * stored in pcb. If the pcb is not bound to a port, it will - * automatically be bound to a random port. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occurred. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - ERR_VAL. No PCB or PCB is dual-stack - * - More errors could be returned by lower protocol layers. - * - * @see udp_disconnect() udp_sendto() - */ -err_t -udp_send(struct udp_pcb *pcb, struct pbuf *p) -{ - if ((pcb == NULL) || IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) { - return ERR_VAL; - } - - /* send to the packet using remote ip and port stored in the pcb */ - return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); -} - -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP -/** @ingroup udp_raw - * Same as udp_send() but with checksum - */ -err_t -udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, - u8_t have_chksum, u16_t chksum) -{ - if ((pcb == NULL) || IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) { - return ERR_VAL; - } - - /* send to the packet using remote ip and port stored in the pcb */ - return udp_sendto_chksum(pcb, p, &pcb->remote_ip, pcb->remote_port, - have_chksum, chksum); -} -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - -/** - * @ingroup udp_raw - * Send data to a specified address using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * - * dst_ip & dst_port are expected to be in the same byte order as in the pcb. - * - * If the PCB already has a remote address association, it will - * be restored after the data is sent. - * - * @return lwIP error code (@see udp_send for possible error codes) - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port) -{ -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP - return udp_sendto_chksum(pcb, p, dst_ip, dst_port, 0, 0); -} - -/** @ingroup udp_raw - * Same as udp_sendto(), but with checksum */ -err_t -udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, - u16_t dst_port, u8_t have_chksum, u16_t chksum) -{ -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - struct netif *netif; - const ip_addr_t *dst_ip_route = dst_ip; - - if ((pcb == NULL) || (dst_ip == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { - return ERR_VAL; - } - - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); - -#if LWIP_IPV6 || (LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS) - if (ip_addr_ismulticast(dst_ip_route)) { -#if LWIP_IPV6 - if (IP_IS_V6(dst_ip)) { - /* For multicast, find a netif based on source address. */ - dst_ip_route = &pcb->local_ip; - } else -#endif /* LWIP_IPV6 */ - { -#if LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS - /* IPv4 does not use source-based routing by default, so we use an - administratively selected interface for multicast by default. - However, this can be overridden by setting an interface address - in pcb->multicast_ip that is used for routing. */ - if (!ip_addr_isany_val(pcb->multicast_ip) && - !ip4_addr_cmp(ip_2_ip4(&pcb->multicast_ip), IP4_ADDR_BROADCAST)) { - dst_ip_route = &pcb->multicast_ip; - } -#endif /* LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS */ - } - } -#endif /* LWIP_IPV6 || (LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS) */ - - /* find the outgoing network interface for this packet */ - if(IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { - /* Don't call ip_route() with IP_ANY_TYPE */ - netif = ip_route(IP46_ADDR_ANY(IP_GET_TYPE(dst_ip_route)), dst_ip_route); - } else { - netif = ip_route(&pcb->local_ip, dst_ip_route); - } - - /* no outgoing network interface could be found? */ - if (netif == NULL) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to ")); - ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, dst_ip); - LWIP_DEBUGF(UDP_DEBUG, ("\n")); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP - return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum); -#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ -} - -/** - * @ingroup udp_raw - * Send data to a specified address using UDP. - * The netif used for sending can be specified. - * - * This function exists mainly for DHCP, to be able to send UDP packets - * on a netif that is still down. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * @param netif the netif used for sending. - * - * dst_ip & dst_port are expected to be in the same byte order as in the pcb. - * - * @return lwIP error code (@see udp_send for possible error codes) - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif) -{ -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP - return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0); -} - -/** Same as udp_sendto_if(), but with checksum */ -err_t -udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, - u16_t dst_port, struct netif *netif, u8_t have_chksum, - u16_t chksum) -{ -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - const ip_addr_t *src_ip; - - if ((pcb == NULL) || (dst_ip == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { - return ERR_VAL; - } - - /* PCB local address is IP_ANY_ADDR? */ -#if LWIP_IPV6 - if (IP_IS_V6(dst_ip)) { - if (ip6_addr_isany(ip_2_ip6(&pcb->local_ip))) { - src_ip = ip6_select_source_address(netif, ip_2_ip6(dst_ip)); - if (src_ip == NULL) { - /* No suitable source address was found. */ - return ERR_RTE; - } - } else { - /* use UDP PCB local IPv6 address as source address, if still valid. */ - if (netif_get_ip6_addr_match(netif, ip_2_ip6(&pcb->local_ip)) < 0) { - /* Address isn't valid anymore. */ - return ERR_RTE; - } - src_ip = &pcb->local_ip; - } - } -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 && LWIP_IPV6 - else -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -#if LWIP_IPV4 - if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || - ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) { - /* if the local_ip is any or multicast - * use the outgoing network interface IP address as source address */ - src_ip = netif_ip_addr4(netif); - } else { - /* check if UDP PCB local IP address is correct - * this could be an old address if netif->ip_addr has changed */ - if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) { - /* local_ip doesn't match, drop the packet */ - return ERR_RTE; - } - /* use UDP PCB local IP address as source address */ - src_ip = &pcb->local_ip; - } -#endif /* LWIP_IPV4 */ -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP - return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip); -#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip); -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ -} - -/** @ingroup udp_raw - * Same as @ref udp_sendto_if, but with source address */ -err_t -udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip) -{ -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP - return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0, src_ip); -} - -/** Same as udp_sendto_if_src(), but with checksum */ -err_t -udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, - u16_t dst_port, struct netif *netif, u8_t have_chksum, - u16_t chksum, const ip_addr_t *src_ip) -{ -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - struct udp_hdr *udphdr; - err_t err; - struct pbuf *q; /* q will be sent down the stack */ - u8_t ip_proto; - u8_t ttl; - - if ((pcb == NULL) || (dst_ip == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, src_ip) || - !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { - return ERR_VAL; - } - -#if LWIP_IPV4 && IP_SOF_BROADCAST - /* broadcast filter? */ - if (!ip_get_option(pcb, SOF_BROADCAST) && -#if LWIP_IPV6 - IP_IS_V4(dst_ip) && -#endif /* LWIP_IPV6 */ - ip_addr_isbroadcast(dst_ip, netif)) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); - return ERR_VAL; - } -#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */ - - /* if the PCB is not yet bound to a port, bind it here */ - if (pcb->local_port == 0) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); - err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); - return err; - } - } - - /* not enough space to add an UDP header to first pbuf in given p chain? */ - if (pbuf_header(p, UDP_HLEN)) { - /* allocate header in a separate new pbuf */ - q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); - return ERR_MEM; - } - if (p->tot_len != 0) { - /* chain header q in front of given pbuf p (only if p contains data) */ - pbuf_chain(q, p); - } - /* first pbuf q points to header pbuf */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* adding space for header within p succeeded */ - /* first pbuf q equals given pbuf */ - q = p; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); - } - LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", - (q->len >= sizeof(struct udp_hdr))); - /* q now represents the packet to be sent */ - udphdr = (struct udp_hdr *)q->payload; - udphdr->src = lwip_htons(pcb->local_port); - udphdr->dest = lwip_htons(dst_port); - /* in UDP, 0 checksum means 'no checksum' */ - udphdr->chksum = 0x0000; - - /* Multicast Loop? */ -#if (LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS) || (LWIP_IPV6 && LWIP_IPV6_MLD) - if (((pcb->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) && ip_addr_ismulticast(dst_ip)) { - q->flags |= PBUF_FLAG_MCASTLOOP; - } -#endif /* (LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS) || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); - -#if LWIP_UDPLITE - /* UDP Lite protocol? */ - if (pcb->flags & UDP_FLAGS_UDPLITE) { - u16_t chklen, chklen_hdr; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); - /* set UDP message length in UDP header */ - chklen_hdr = chklen = pcb->chksum_len_tx; - if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) { - if (chklen != 0) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen)); - } - /* For UDP-Lite, checksum length of 0 means checksum - over the complete packet. (See RFC 3828 chap. 3.1) - At least the UDP-Lite header must be covered by the - checksum, therefore, if chksum_len has an illegal - value, we generate the checksum over the complete - packet to be safe. */ - chklen_hdr = 0; - chklen = q->tot_len; - } - udphdr->len = lwip_htons(chklen_hdr); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) { -#if LWIP_CHECKSUM_ON_COPY - if (have_chksum) { - chklen = UDP_HLEN; - } -#endif /* LWIP_CHECKSUM_ON_COPY */ - udphdr->chksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDPLITE, - q->tot_len, chklen, src_ip, dst_ip); -#if LWIP_CHECKSUM_ON_COPY - if (have_chksum) { - u32_t acc; - acc = udphdr->chksum + (u16_t)~(chksum); - udphdr->chksum = FOLD_U32T(acc); - } -#endif /* LWIP_CHECKSUM_ON_COPY */ - - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) { - udphdr->chksum = 0xffff; - } - } -#endif /* CHECKSUM_GEN_UDP */ - - ip_proto = IP_PROTO_UDPLITE; - } else -#endif /* LWIP_UDPLITE */ - { /* UDP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); - udphdr->len = lwip_htons(q->tot_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) { - /* Checksum is mandatory over IPv6. */ - if (IP_IS_V6(dst_ip) || (pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { - u16_t udpchksum; -#if LWIP_CHECKSUM_ON_COPY - if (have_chksum) { - u32_t acc; - udpchksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDP, - q->tot_len, UDP_HLEN, src_ip, dst_ip); - acc = udpchksum + (u16_t)~(chksum); - udpchksum = FOLD_U32T(acc); - } else -#endif /* LWIP_CHECKSUM_ON_COPY */ - { - udpchksum = ip_chksum_pseudo(q, IP_PROTO_UDP, q->tot_len, - src_ip, dst_ip); - } - - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udpchksum == 0x0000) { - udpchksum = 0xffff; - } - udphdr->chksum = udpchksum; - } - } -#endif /* CHECKSUM_GEN_UDP */ - ip_proto = IP_PROTO_UDP; - } - - /* Determine TTL to use */ -#if LWIP_MULTICAST_TX_OPTIONS - ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl); -#else /* LWIP_MULTICAST_TX_OPTIONS */ - ttl = pcb->ttl; -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto)); - /* output to IP */ - NETIF_SET_HWADDRHINT(netif, &(pcb->addr_hint)); - err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif); - NETIF_SET_HWADDRHINT(netif, NULL); - - /* @todo: must this be increased even if error occurred? */ - MIB2_STATS_INC(mib2.udpoutdatagrams); - - /* did we chain a separate header pbuf earlier? */ - if (q != p) { - /* free the header pbuf */ - pbuf_free(q); - q = NULL; - /* p is still referenced by the caller, and will live on */ - } - - UDP_STATS_INC(udp.xmit); - return err; -} - -/** - * @ingroup udp_raw - * Bind an UDP PCB. - * - * @param pcb UDP PCB to be bound with a local address ipaddr and port. - * @param ipaddr local IP address to bind with. Use IP4_ADDR_ANY to - * bind to all local interfaces. - * @param port local UDP port to bind with. Use 0 to automatically bind - * to a random port between UDP_LOCAL_PORT_RANGE_START and - * UDP_LOCAL_PORT_RANGE_END. - * - * ipaddr & port are expected to be in the same byte order as in the pcb. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occurred. - * - ERR_USE. The specified ipaddr and port are already bound to by - * another UDP PCB. - * - * @see udp_disconnect() - */ -err_t -udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - u8_t rebind; - -#if LWIP_IPV4 - /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ - if (ipaddr == NULL) { - ipaddr = IP4_ADDR_ANY; - } -#endif /* LWIP_IPV4 */ - - /* still need to check for ipaddr == NULL in IPv6 only case */ - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); - ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr); - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); - - rebind = 0; - /* Check for double bind and rebind of the same pcb */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - /* is this UDP PCB already on active list? */ - if (pcb == ipcb) { - rebind = 1; - break; - } - } - - /* no port specified? */ - if (port == 0) { - port = udp_new_port(); - if (port == 0) { - /* no more ports available in local range */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); - return ERR_USE; - } - } else { - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - if (pcb != ipcb) { - /* By default, we don't allow to bind to a port that any other udp - PCB is already bound to, unless *all* PCBs with that port have tha - REUSEADDR flag set. */ -#if SO_REUSE - if (!ip_get_option(pcb, SOF_REUSEADDR) || - !ip_get_option(ipcb, SOF_REUSEADDR)) -#endif /* SO_REUSE */ - { - /* port matches that of PCB in list and REUSEADDR not set -> reject */ - if ((ipcb->local_port == port) && - /* IP address matches? */ - ip_addr_cmp(&ipcb->local_ip, ipaddr)) { - /* other PCB already binds to this local IP and port */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); - return ERR_USE; - } - } - } - } - } - - ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); - - pcb->local_port = port; - mib2_udp_bind(pcb); - /* pcb not active yet? */ - if (rebind == 0) { - /* place the PCB on the active list if not already there */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to ")); - ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, &pcb->local_ip); - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port)); - return ERR_OK; -} - -/** - * @ingroup udp_raw - * Connect an UDP PCB. - * - * This will associate the UDP PCB with the remote address. - * - * @param pcb UDP PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * @param port remote UDP port to connect with. - * - * @return lwIP error code - * - * ipaddr & port are expected to be in the same byte order as in the pcb. - * - * The udp pcb is bound to a random local port if not already bound. - * - * @see udp_disconnect() - */ -err_t -udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - - if ((pcb == NULL) || (ipaddr == NULL)) { - return ERR_VAL; - } - - if (pcb->local_port == 0) { - err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) { - return err; - } - } - - ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); - pcb->remote_port = port; - pcb->flags |= UDP_FLAGS_CONNECTED; - - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_connect: connected to ")); - ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - &pcb->remote_ip); - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port)); - - /* Insert UDP PCB into the list of active UDP PCBs. */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - if (pcb == ipcb) { - /* already on the list, just return */ - return ERR_OK; - } - } - /* PCB not yet on the list, add PCB now */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - return ERR_OK; -} - -/** - * @ingroup udp_raw - * Disconnect a UDP PCB - * - * @param pcb the udp pcb to disconnect. - */ -void -udp_disconnect(struct udp_pcb *pcb) -{ - /* reset remote address association */ -#if LWIP_IPV4 && LWIP_IPV6 - if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { - ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE); - } else { -#endif - ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip); -#if LWIP_IPV4 && LWIP_IPV6 - } -#endif - pcb->remote_port = 0; - /* mark PCB as unconnected */ - pcb->flags &= ~UDP_FLAGS_CONNECTED; -} - -/** - * @ingroup udp_raw - * Set a receive callback for a UDP PCB - * - * This callback will be called when receiving a datagram for the pcb. - * - * @param pcb the pcb for which to set the recv callback - * @param recv function pointer of the callback function - * @param recv_arg additional argument to pass to the callback function - */ -void -udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * @ingroup udp_raw - * Remove an UDP PCB. - * - * @param pcb UDP PCB to be removed. The PCB is removed from the list of - * UDP PCB's and the data structure is freed from memory. - * - * @see udp_new() - */ -void -udp_remove(struct udp_pcb *pcb) -{ - struct udp_pcb *pcb2; - - mib2_udp_unbind(pcb); - /* pcb to be removed is first in list? */ - if (udp_pcbs == pcb) { - /* make list start at 2nd pcb */ - udp_pcbs = udp_pcbs->next; - /* pcb not 1st in list */ - } else { - for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in udp_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - break; - } - } - } - memp_free(MEMP_UDP_PCB, pcb); -} - -/** - * @ingroup udp_raw - * Create a UDP PCB. - * - * @return The UDP PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @see udp_remove() - */ -struct udp_pcb * -udp_new(void) -{ - struct udp_pcb *pcb; - pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB); - /* could allocate UDP PCB? */ - if (pcb != NULL) { - /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 - * which means checksum is generated over the whole datagram per default - * (recommended as default by RFC 3828). */ - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct udp_pcb)); - pcb->ttl = UDP_TTL; -#if LWIP_MULTICAST_TX_OPTIONS - udp_set_multicast_ttl(pcb, UDP_TTL); -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - } - return pcb; -} - -/** - * @ingroup udp_raw - * Create a UDP PCB for specific IP type. - * - * @param type IP address type, see @ref lwip_ip_addr_type definitions. - * If you want to listen to IPv4 and IPv6 (dual-stack) packets, - * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. - * @return The UDP PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @see udp_remove() - */ -struct udp_pcb * -udp_new_ip_type(u8_t type) -{ - struct udp_pcb *pcb; - pcb = udp_new(); -#if LWIP_IPV4 && LWIP_IPV6 - if (pcb != NULL) { - IP_SET_TYPE_VAL(pcb->local_ip, type); - IP_SET_TYPE_VAL(pcb->remote_ip, type); - } -#else - LWIP_UNUSED_ARG(type); -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - return pcb; -} - -/** This function is called from netif.c when address is changed - * - * @param old_addr IP address of the netif before change - * @param new_addr IP address of the netif after change - */ -void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr) -{ - struct udp_pcb* upcb; - - if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { - for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&upcb->local_ip, old_addr)) { - /* The PCB is bound to the old ipaddr and - * is set to bound to the new one instead */ - ip_addr_copy(upcb->local_ip, *new_addr); - } - } - } -} - -#if UDP_DEBUG -/** - * Print UDP header information for debug purposes. - * - * @param udphdr pointer to the udp header in memory. - */ -void -udp_debug_print(struct udp_hdr *udphdr) -{ - LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - lwip_ntohs(udphdr->src), lwip_ntohs(udphdr->dest))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", - lwip_ntohs(udphdr->len), lwip_ntohs(udphdr->chksum))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* UDP_DEBUG */ - -#endif /* LWIP_UDP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/api.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/api.h deleted file mode 100644 index 16a35cc22fe45a90c44aa3ab8cbea3bcd56de359..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/api.h +++ /dev/null @@ -1,401 +0,0 @@ -/** - * @file - * netconn API (to be used from non-TCPIP threads) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_API_H -#define LWIP_HDR_API_H - -#include "lwip/opt.h" - -#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ -/* Note: Netconn API is always available when sockets are enabled - - * sockets are implemented on top of them */ - -#include "lwip/arch.h" -#include "lwip/netbuf.h" -#include "lwip/sys.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Throughout this file, IP addresses and port numbers are expected to be in - * the same byte order as in the corresponding pcb. - */ - -/* Flags for netconn_write (u8_t) */ -#define NETCONN_NOFLAG 0x00 -#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ -#define NETCONN_COPY 0x01 -#define NETCONN_MORE 0x02 -#define NETCONN_DONTBLOCK 0x04 - -/* Flags for struct netconn.flags (u8_t) */ -/** Should this netconn avoid blocking? */ -#define NETCONN_FLAG_NON_BLOCKING 0x02 -/** Was the last connect action a non-blocking one? */ -#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT 0x04 -/** If a nonblocking write has been rejected before, poll_tcp needs to - check if the netconn is writable again */ -#define NETCONN_FLAG_CHECK_WRITESPACE 0x10 -#if LWIP_IPV6 -/** If this flag is set then only IPv6 communication is allowed on the - netconn. As per RFC#3493 this features defaults to OFF allowing - dual-stack usage by default. */ -#define NETCONN_FLAG_IPV6_V6ONLY 0x20 -#endif /* LWIP_IPV6 */ - - -/* Helpers to process several netconn_types by the same code */ -#define NETCONNTYPE_GROUP(t) ((t)&0xF0) -#define NETCONNTYPE_DATAGRAM(t) ((t)&0xE0) -#if LWIP_IPV6 -#define NETCONN_TYPE_IPV6 0x08 -#define NETCONNTYPE_ISIPV6(t) (((t)&NETCONN_TYPE_IPV6) != 0) -#define NETCONNTYPE_ISUDPLITE(t) (((t)&0xF3) == NETCONN_UDPLITE) -#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM) -#else /* LWIP_IPV6 */ -#define NETCONNTYPE_ISIPV6(t) (0) -#define NETCONNTYPE_ISUDPLITE(t) ((t) == NETCONN_UDPLITE) -#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM) -#endif /* LWIP_IPV6 */ - -/** @ingroup netconn_common - * Protocol family and type of the netconn - */ -enum netconn_type { - NETCONN_INVALID = 0, - /** TCP IPv4 */ - NETCONN_TCP = 0x10, -#if LWIP_IPV6 - /** TCP IPv6 */ - NETCONN_TCP_IPV6 = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */, -#endif /* LWIP_IPV6 */ - /** UDP IPv4 */ - NETCONN_UDP = 0x20, - /** UDP IPv4 lite */ - NETCONN_UDPLITE = 0x21, - /** UDP IPv4 no checksum */ - NETCONN_UDPNOCHKSUM = 0x22, - -#if LWIP_IPV6 - /** UDP IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ - NETCONN_UDP_IPV6 = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */, - /** UDP IPv6 lite (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ - NETCONN_UDPLITE_IPV6 = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */, - /** UDP IPv6 no checksum (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ - NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */, -#endif /* LWIP_IPV6 */ - - /** Raw connection IPv4 */ - NETCONN_RAW = 0x40 -#if LWIP_IPV6 - /** Raw connection IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ - , NETCONN_RAW_IPV6 = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */ -#endif /* LWIP_IPV6 */ -}; - -/** Current state of the netconn. Non-TCP netconns are always - * in state NETCONN_NONE! */ -enum netconn_state { - NETCONN_NONE, - NETCONN_WRITE, - NETCONN_LISTEN, - NETCONN_CONNECT, - NETCONN_CLOSE -}; - -/** Used to inform the callback function about changes - * - * Event explanation: - * - * In the netconn implementation, there are three ways to block a client: - * - * - accept mbox (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); in netconn_accept()) - * - receive mbox (sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); in netconn_recv_data()) - * - send queue is full (sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); in lwip_netconn_do_write()) - * - * The events have to be seen as events signaling the state of these mboxes/semaphores. For non-blocking - * connections, you need to know in advance whether a call to a netconn function call would block or not, - * and these events tell you about that. - * - * RCVPLUS events say: Safe to perform a potentially blocking call call once more. - * They are counted in sockets - three RCVPLUS events for accept mbox means you are safe - * to call netconn_accept 3 times without being blocked. - * Same thing for receive mbox. - * - * RCVMINUS events say: Your call to to a possibly blocking function is "acknowledged". - * Socket implementation decrements the counter. - * - * For TX, there is no need to count, its merely a flag. SENDPLUS means you may send something. - * SENDPLUS occurs when enough data was delivered to peer so netconn_send() can be called again. - * A SENDMINUS event occurs when the next call to a netconn_send() would be blocking. - */ -enum netconn_evt { - NETCONN_EVT_RCVPLUS, - NETCONN_EVT_RCVMINUS, - NETCONN_EVT_SENDPLUS, - NETCONN_EVT_SENDMINUS, - NETCONN_EVT_ERROR -}; - -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) -/** Used for netconn_join_leave_group() */ -enum netconn_igmp { - NETCONN_JOIN, - NETCONN_LEAVE -}; -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - -#if LWIP_DNS -/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */ -#define NETCONN_DNS_DEFAULT NETCONN_DNS_IPV4_IPV6 -#define NETCONN_DNS_IPV4 0 -#define NETCONN_DNS_IPV6 1 -#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */ -#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */ -#endif /* LWIP_DNS */ - -/* forward-declare some structs to avoid to include their headers */ -struct ip_pcb; -struct tcp_pcb; -struct udp_pcb; -struct raw_pcb; -struct netconn; -struct api_msg; - -/** A callback prototype to inform about events for a netconn */ -typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); - -/** A netconn descriptor */ -struct netconn { - /** type of the netconn (TCP, UDP or RAW) */ - enum netconn_type type; - /** current state of the netconn */ - enum netconn_state state; - /** the lwIP internal protocol control block */ - union { - struct ip_pcb *ip; - struct tcp_pcb *tcp; - struct udp_pcb *udp; - struct raw_pcb *raw; - } pcb; - /** the last error this netconn had */ - err_t last_err; -#if !LWIP_NETCONN_SEM_PER_THREAD - /** sem that is used to synchronously execute functions in the core context */ - sys_sem_t op_completed; -#endif - /** mbox where received packets are stored until they are fetched - by the netconn application thread (can grow quite big) */ - sys_mbox_t recvmbox; -#if LWIP_TCP - /** mbox where new connections are stored until processed - by the application thread */ - sys_mbox_t acceptmbox; -#endif /* LWIP_TCP */ - /** only used for socket layer */ -#if LWIP_SOCKET - int socket; -#endif /* LWIP_SOCKET */ -#if LWIP_SO_SNDTIMEO - /** timeout to wait for sending data (which means enqueueing data for sending - in internal buffers) in milliseconds */ - s32_t send_timeout; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVTIMEO - /** timeout in milliseconds to wait for new data to be received - (or connections to arrive for listening netconns) */ - int recv_timeout; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - /** maximum amount of bytes queued in recvmbox - not used for TCP: adjust TCP_WND instead! */ - int recv_bufsize; - /** number of bytes currently in recvmbox to be received, - tested against recv_bufsize to limit bytes on recvmbox - for UDP and RAW, used for FIONREAD */ - int recv_avail; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_SO_LINGER - /** values <0 mean linger is disabled, values > 0 are seconds to linger */ - s16_t linger; -#endif /* LWIP_SO_LINGER */ - /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */ - u8_t flags; -#if LWIP_TCP - /** TCP: when data passed to netconn_write doesn't fit into the send buffer, - this temporarily stores how much is already sent. */ - size_t write_offset; - /** TCP: when data passed to netconn_write doesn't fit into the send buffer, - this temporarily stores the message. - Also used during connect and close. */ - struct api_msg *current_msg; -#endif /* LWIP_TCP */ - /** A callback function that is informed about events for this netconn */ - netconn_callback callback; -}; - -/** Register an Network connection event */ -#define API_EVENT(c,e,l) if (c->callback) { \ - (*c->callback)(c, e, l); \ - } - -/** Set conn->last_err to err but don't overwrite fatal errors */ -#define NETCONN_SET_SAFE_ERR(conn, err) do { if ((conn) != NULL) { \ - SYS_ARCH_DECL_PROTECT(netconn_set_safe_err_lev); \ - SYS_ARCH_PROTECT(netconn_set_safe_err_lev); \ - if (!ERR_IS_FATAL((conn)->last_err)) { \ - (conn)->last_err = err; \ - } \ - SYS_ARCH_UNPROTECT(netconn_set_safe_err_lev); \ -}} while(0); - -/* Network connection functions: */ - -/** @ingroup netconn_common - * Create new netconn connection - * @param t @ref netconn_type */ -#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) -#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) -struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, - netconn_callback callback); -err_t netconn_delete(struct netconn *conn); -/** Get the type of a netconn (as enum netconn_type). */ -#define netconn_type(conn) (conn->type) - -err_t netconn_getaddr(struct netconn *conn, ip_addr_t *addr, - u16_t *port, u8_t local); -/** @ingroup netconn_common */ -#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) -/** @ingroup netconn_common */ -#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) - -err_t netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port); -err_t netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port); -err_t netconn_disconnect (struct netconn *conn); -err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); -/** @ingroup netconn_tcp */ -#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) -err_t netconn_accept(struct netconn *conn, struct netconn **new_conn); -err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf); -err_t netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf); -err_t netconn_sendto(struct netconn *conn, struct netbuf *buf, - const ip_addr_t *addr, u16_t port); -err_t netconn_send(struct netconn *conn, struct netbuf *buf); -err_t netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, - u8_t apiflags, size_t *bytes_written); -/** @ingroup netconn_tcp */ -#define netconn_write(conn, dataptr, size, apiflags) \ - netconn_write_partly(conn, dataptr, size, apiflags, NULL) -err_t netconn_close(struct netconn *conn); -err_t netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx); - -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) -err_t netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr, - const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave); -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - -#if LWIP_DNS -#if LWIP_IPV4 && LWIP_IPV6 -err_t netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype); -#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT) -#else /* LWIP_IPV4 && LWIP_IPV6 */ -err_t netconn_gethostbyname(const char *name, ip_addr_t *addr); -#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ -#endif /* LWIP_DNS */ - -#define netconn_err(conn) ((conn)->last_err) -#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) - -/** Set the blocking status of netconn calls (@todo: write/send is missing) */ -#define netconn_set_nonblocking(conn, val) do { if(val) { \ - (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \ -} else { \ - (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0) -/** Get the blocking status of netconn calls (@todo: write/send is missing) */ -#define netconn_is_nonblocking(conn) (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0) - -#if LWIP_IPV6 -/** @ingroup netconn_common - * TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) - */ -#define netconn_set_ipv6only(conn, val) do { if(val) { \ - (conn)->flags |= NETCONN_FLAG_IPV6_V6ONLY; \ -} else { \ - (conn)->flags &= ~ NETCONN_FLAG_IPV6_V6ONLY; }} while(0) -/** @ingroup netconn_common - * TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) - */ -#define netconn_get_ipv6only(conn) (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0) -#endif /* LWIP_IPV6 */ - -#if LWIP_SO_SNDTIMEO -/** Set the send timeout in milliseconds */ -#define netconn_set_sendtimeout(conn, timeout) ((conn)->send_timeout = (timeout)) -/** Get the send timeout in milliseconds */ -#define netconn_get_sendtimeout(conn) ((conn)->send_timeout) -#endif /* LWIP_SO_SNDTIMEO */ -#if LWIP_SO_RCVTIMEO -/** Set the receive timeout in milliseconds */ -#define netconn_set_recvtimeout(conn, timeout) ((conn)->recv_timeout = (timeout)) -/** Get the receive timeout in milliseconds */ -#define netconn_get_recvtimeout(conn) ((conn)->recv_timeout) -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF -/** Set the receive buffer in bytes */ -#define netconn_set_recvbufsize(conn, recvbufsize) ((conn)->recv_bufsize = (recvbufsize)) -/** Get the receive buffer in bytes */ -#define netconn_get_recvbufsize(conn) ((conn)->recv_bufsize) -#endif /* LWIP_SO_RCVBUF*/ - -#if LWIP_NETCONN_SEM_PER_THREAD -void netconn_thread_init(void); -void netconn_thread_cleanup(void); -#else /* LWIP_NETCONN_SEM_PER_THREAD */ -#define netconn_thread_init() -#define netconn_thread_cleanup() -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETCONN || LWIP_SOCKET */ - -#endif /* LWIP_HDR_API_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/FILES b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/FILES deleted file mode 100644 index adfc0f33450c6b7c8fddb9b4b4a53075c5e350af..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/FILES +++ /dev/null @@ -1,2 +0,0 @@ -This directory contains application headers. -Every application shall provide one api file APP.h and optionally one options file APP_opts.h diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/fs.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/fs.h deleted file mode 100644 index bb176fa010716f1dedc944fc1870943e5f02d739..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/fs.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_APPS_FS_H -#define LWIP_HDR_APPS_FS_H - -#include "httpd_opts.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define FS_READ_EOF -1 -#define FS_READ_DELAYED -2 - -#if HTTPD_PRECALCULATED_CHECKSUM -struct fsdata_chksum { - u32_t offset; - u16_t chksum; - u16_t len; -}; -#endif /* HTTPD_PRECALCULATED_CHECKSUM */ - -#define FS_FILE_FLAGS_HEADER_INCLUDED 0x01 -#define FS_FILE_FLAGS_HEADER_PERSISTENT 0x02 - -struct fs_file { - const char *data; - int len; - int index; - void *pextension; -#if HTTPD_PRECALCULATED_CHECKSUM - const struct fsdata_chksum *chksum; - u16_t chksum_count; -#endif /* HTTPD_PRECALCULATED_CHECKSUM */ - u8_t flags; -#if LWIP_HTTPD_CUSTOM_FILES - u8_t is_custom_file; -#endif /* LWIP_HTTPD_CUSTOM_FILES */ -#if LWIP_HTTPD_FILE_STATE - void *state; -#endif /* LWIP_HTTPD_FILE_STATE */ -}; - -#if LWIP_HTTPD_FS_ASYNC_READ -typedef void (*fs_wait_cb)(void *arg); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ - -err_t fs_open(struct fs_file *file, const char *name); -void fs_close(struct fs_file *file); -#if LWIP_HTTPD_DYNAMIC_FILE_READ -#if LWIP_HTTPD_FS_ASYNC_READ -int fs_read_async(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg); -#else /* LWIP_HTTPD_FS_ASYNC_READ */ -int fs_read(struct fs_file *file, char *buffer, int count); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ -#if LWIP_HTTPD_FS_ASYNC_READ -int fs_is_file_ready(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg); -#endif /* LWIP_HTTPD_FS_ASYNC_READ */ -int fs_bytes_left(struct fs_file *file); - -#if LWIP_HTTPD_FILE_STATE -/** This user-defined function is called when a file is opened. */ -void *fs_state_init(struct fs_file *file, const char *name); -/** This user-defined function is called when a file is closed. */ -void fs_state_free(struct fs_file *file, void *state); -#endif /* #if LWIP_HTTPD_FILE_STATE */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_FS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd.h deleted file mode 100644 index 40f1811e574bc5662aa147166e8d40ca1eb81960..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd.h +++ /dev/null @@ -1,236 +0,0 @@ -/** - * @file - * HTTP server - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * This version of the file has been modified by Texas Instruments to offer - * simple server-side-include (SSI) and Common Gateway Interface (CGI) - * capability. - */ - -#ifndef LWIP_HDR_APPS_HTTPD_H -#define LWIP_HDR_APPS_HTTPD_H - -#include "httpd_opts.h" -#include "lwip/err.h" -#include "lwip/pbuf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_HTTPD_CGI - -/* - * Function pointer for a CGI script handler. - * - * This function is called each time the HTTPD server is asked for a file - * whose name was previously registered as a CGI function using a call to - * http_set_cgi_handler. The iIndex parameter provides the index of the - * CGI within the ppcURLs array passed to http_set_cgi_handler. Parameters - * pcParam and pcValue provide access to the parameters provided along with - * the URI. iNumParams provides a count of the entries in the pcParam and - * pcValue arrays. Each entry in the pcParam array contains the name of a - * parameter with the corresponding entry in the pcValue array containing the - * value for that parameter. Note that pcParam may contain multiple elements - * with the same name if, for example, a multi-selection list control is used - * in the form generating the data. - * - * The function should return a pointer to a character string which is the - * path and filename of the response that is to be sent to the connected - * browser, for example "/thanks.htm" or "/response/error.ssi". - * - * The maximum number of parameters that will be passed to this function via - * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in the incoming - * HTTP request above this number will be discarded. - * - * Requests intended for use by this CGI mechanism must be sent using the GET - * method (which encodes all parameters within the URI rather than in a block - * later in the request). Attempts to use the POST method will result in the - * request being ignored. - * - */ -typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[], - char *pcValue[]); - -/* - * Structure defining the base filename (URL) of a CGI and the associated - * function which is to be called when that URL is requested. - */ -typedef struct -{ - const char *pcCGIName; - tCGIHandler pfnCGIHandler; -} tCGI; - -void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers); - -#endif /* LWIP_HTTPD_CGI */ - -#if LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI - -#if LWIP_HTTPD_CGI_SSI -/** Define this generic CGI handler in your application. - * It is called once for every URI with parameters. - * The parameters can be stored to - */ -extern void httpd_cgi_handler(const char* uri, int iNumParams, char **pcParam, char **pcValue -#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE - , void *connection_state -#endif /* LWIP_HTTPD_FILE_STATE */ - ); -#endif /* LWIP_HTTPD_CGI_SSI */ - -#endif /* LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI */ - -#if LWIP_HTTPD_SSI - -/* - * Function pointer for the SSI tag handler callback. - * - * This function will be called each time the HTTPD server detects a tag of the - * form in a .shtml, .ssi or .shtm file where "name" appears as - * one of the tags supplied to http_set_ssi_handler in the ppcTags array. The - * returned insert string, which will be appended after the the string - * "" in file sent back to the client,should be written to pointer - * pcInsert. iInsertLen contains the size of the buffer pointed to by - * pcInsert. The iIndex parameter provides the zero-based index of the tag as - * found in the ppcTags array and identifies the tag that is to be processed. - * - * The handler returns the number of characters written to pcInsert excluding - * any terminating NULL or a negative number to indicate a failure (tag not - * recognized, for example). - * - * Note that the behavior of this SSI mechanism is somewhat different from the - * "normal" SSI processing as found in, for example, the Apache web server. In - * this case, the inserted text is appended following the SSI tag rather than - * replacing the tag entirely. This allows for an implementation that does not - * require significant additional buffering of output data yet which will still - * offer usable SSI functionality. One downside to this approach is when - * attempting to use SSI within JavaScript. The SSI tag is structured to - * resemble an HTML comment but this syntax does not constitute a comment - * within JavaScript and, hence, leaving the tag in place will result in - * problems in these cases. To work around this, any SSI tag which needs to - * output JavaScript code must do so in an encapsulated way, sending the whole - * HTML section as a single include. - */ -typedef u16_t (*tSSIHandler)( -#if LWIP_HTTPD_SSI_RAW - const char* ssi_tag_name, -#else /* LWIP_HTTPD_SSI_RAW */ - int iIndex, -#endif /* LWIP_HTTPD_SSI_RAW */ - char *pcInsert, int iInsertLen -#if LWIP_HTTPD_SSI_MULTIPART - , u16_t current_tag_part, u16_t *next_tag_part -#endif /* LWIP_HTTPD_SSI_MULTIPART */ -#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE - , void *connection_state -#endif /* LWIP_HTTPD_FILE_STATE */ - ); - -/** Set the SSI handler function - * (if LWIP_HTTPD_SSI_RAW==1, only the first argument is used) - */ -void http_set_ssi_handler(tSSIHandler pfnSSIHandler, - const char **ppcTags, int iNumTags); - -/** For LWIP_HTTPD_SSI_RAW==1, return this to indicate the tag is unknown. - * In this case, the webserver writes a warning into the page. - * You can also just return 0 to write nothing for unknown tags. - */ -#define HTTPD_SSI_TAG_UNKNOWN 0xFFFF - -#endif /* LWIP_HTTPD_SSI */ - -#if LWIP_HTTPD_SUPPORT_POST - -/* These functions must be implemented by the application */ - -/** Called when a POST request has been received. The application can decide - * whether to accept it or not. - * - * @param connection Unique connection identifier, valid until httpd_post_end - * is called. - * @param uri The HTTP header URI receiving the POST request. - * @param http_request The raw HTTP request (the first packet, normally). - * @param http_request_len Size of 'http_request'. - * @param content_len Content-Length from HTTP header. - * @param response_uri Filename of response file, to be filled when denying the - * request - * @param response_uri_len Size of the 'response_uri' buffer. - * @param post_auto_wnd Set this to 0 to let the callback code handle window - * updates by calling 'httpd_post_data_recved' (to throttle rx speed) - * default is 1 (httpd handles window updates automatically) - * @return ERR_OK: Accept the POST request, data may be passed in - * another err_t: Deny the POST request, send back 'bad request'. - */ -err_t httpd_post_begin(void *connection, const char *uri, const char *http_request, - u16_t http_request_len, int content_len, char *response_uri, - u16_t response_uri_len, u8_t *post_auto_wnd); - -/** Called for each pbuf of data that has been received for a POST. - * ATTENTION: The application is responsible for freeing the pbufs passed in! - * - * @param connection Unique connection identifier. - * @param p Received data. - * @return ERR_OK: Data accepted. - * another err_t: Data denied, http_post_get_response_uri will be called. - */ -err_t httpd_post_receive_data(void *connection, struct pbuf *p); - -/** Called when all data is received or when the connection is closed. - * The application must return the filename/URI of a file to send in response - * to this POST request. If the response_uri buffer is untouched, a 404 - * response is returned. - * - * @param connection Unique connection identifier. - * @param response_uri Filename of response file, to be filled when denying the request - * @param response_uri_len Size of the 'response_uri' buffer. - */ -void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len); - -#if LWIP_HTTPD_POST_MANUAL_WND -void httpd_post_data_recved(void *connection, u16_t recved_len); -#endif /* LWIP_HTTPD_POST_MANUAL_WND */ - -#endif /* LWIP_HTTPD_SUPPORT_POST */ - -void httpd_init(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HTTPD_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd_opts.h deleted file mode 100644 index 340db15f6630f2f909900e429ba56353269bb041..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/httpd_opts.h +++ /dev/null @@ -1,323 +0,0 @@ -/** - * @file - * HTTP server options list - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * This version of the file has been modified by Texas Instruments to offer - * simple server-side-include (SSI) and Common Gateway Interface (CGI) - * capability. - */ - -#ifndef LWIP_HDR_APPS_HTTPD_OPTS_H -#define LWIP_HDR_APPS_HTTPD_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup httpd_opts Options - * @ingroup httpd - * @{ - */ - -/** Set this to 1 to support CGI (old style) */ -#if !defined LWIP_HTTPD_CGI || defined __DOXYGEN__ -#define LWIP_HTTPD_CGI 0 -#endif - -/** Set this to 1 to support CGI (new style) */ -#if !defined LWIP_HTTPD_CGI_SSI || defined __DOXYGEN__ -#define LWIP_HTTPD_CGI_SSI 0 -#endif - -/** Set this to 1 to support SSI (Server-Side-Includes) */ -#if !defined LWIP_HTTPD_SSI || defined __DOXYGEN__ -#define LWIP_HTTPD_SSI 0 -#endif - -/** Set this to 1 to implement an SSI tag handler callback that gets a const char* - * to the tag (instead of an index into a pre-registered array of known tags) */ -#if !defined LWIP_HTTPD_SSI_RAW || defined __DOXYGEN__ -#define LWIP_HTTPD_SSI_RAW 0 -#endif - -/** Set this to 1 to support HTTP POST */ -#if !defined LWIP_HTTPD_SUPPORT_POST || defined __DOXYGEN__ -#define LWIP_HTTPD_SUPPORT_POST 0 -#endif - -/* The maximum number of parameters that the CGI handler can be sent. */ -#if !defined LWIP_HTTPD_MAX_CGI_PARAMETERS || defined __DOXYGEN__ -#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16 -#endif - -/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more - * arguments indicating a counter for insert string that are too long to be - * inserted at once: the SSI handler function must then set 'next_tag_part' - * which will be passed back to it in the next call. */ -#if !defined LWIP_HTTPD_SSI_MULTIPART || defined __DOXYGEN__ -#define LWIP_HTTPD_SSI_MULTIPART 0 -#endif - -/* The maximum length of the string comprising the tag name */ -#if !defined LWIP_HTTPD_MAX_TAG_NAME_LEN || defined __DOXYGEN__ -#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8 -#endif - -/* The maximum length of string that can be returned to replace any given tag */ -#if !defined LWIP_HTTPD_MAX_TAG_INSERT_LEN || defined __DOXYGEN__ -#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192 -#endif - -#if !defined LWIP_HTTPD_POST_MANUAL_WND || defined __DOXYGEN__ -#define LWIP_HTTPD_POST_MANUAL_WND 0 -#endif - -/** This string is passed in the HTTP header as "Server: " */ -#if !defined HTTPD_SERVER_AGENT || defined __DOXYGEN__ -#define HTTPD_SERVER_AGENT "lwIP/" LWIP_VERSION_STRING " (http://savannah.nongnu.org/projects/lwip)" -#endif - -/** Set this to 1 if you want to include code that creates HTTP headers - * at runtime. Default is off: HTTP headers are then created statically - * by the makefsdata tool. Static headers mean smaller code size, but - * the (readonly) fsdata will grow a bit as every file includes the HTTP - * header. */ -#if !defined LWIP_HTTPD_DYNAMIC_HEADERS || defined __DOXYGEN__ -#define LWIP_HTTPD_DYNAMIC_HEADERS 0 -#endif - -#if !defined HTTPD_DEBUG || defined __DOXYGEN__ -#define HTTPD_DEBUG LWIP_DBG_OFF -#endif - -/** Set this to 1 to use a memp pool for allocating - * struct http_state instead of the heap. - */ -#if !defined HTTPD_USE_MEM_POOL || defined __DOXYGEN__ -#define HTTPD_USE_MEM_POOL 0 -#endif - -/** The server port for HTTPD to use */ -#if !defined HTTPD_SERVER_PORT || defined __DOXYGEN__ -#define HTTPD_SERVER_PORT 80 -#endif - -/** Maximum retries before the connection is aborted/closed. - * - number of times pcb->poll is called -> default is 4*500ms = 2s; - * - reset when pcb->sent is called - */ -#if !defined HTTPD_MAX_RETRIES || defined __DOXYGEN__ -#define HTTPD_MAX_RETRIES 4 -#endif - -/** The poll delay is X*500ms */ -#if !defined HTTPD_POLL_INTERVAL || defined __DOXYGEN__ -#define HTTPD_POLL_INTERVAL 4 -#endif - -/** Priority for tcp pcbs created by HTTPD (very low by default). - * Lower priorities get killed first when running out of memory. - */ -#if !defined HTTPD_TCP_PRIO || defined __DOXYGEN__ -#define HTTPD_TCP_PRIO TCP_PRIO_MIN -#endif - -/** Set this to 1 to enable timing each file sent */ -#if !defined LWIP_HTTPD_TIMING || defined __DOXYGEN__ -#define LWIP_HTTPD_TIMING 0 -#endif -/** Set this to 1 to enable timing each file sent */ -#if !defined HTTPD_DEBUG_TIMING || defined __DOXYGEN__ -#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF -#endif - -/** Set this to one to show error pages when parsing a request fails instead - of simply closing the connection. */ -#if !defined LWIP_HTTPD_SUPPORT_EXTSTATUS || defined __DOXYGEN__ -#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0 -#endif - -/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */ -#if !defined LWIP_HTTPD_SUPPORT_V09 || defined __DOXYGEN__ -#define LWIP_HTTPD_SUPPORT_V09 1 -#endif - -/** Set this to 1 to enable HTTP/1.1 persistent connections. - * ATTENTION: If the generated file system includes HTTP headers, these must - * include the "Connection: keep-alive" header (pass argument "-11" to makefsdata). - */ -#if !defined LWIP_HTTPD_SUPPORT_11_KEEPALIVE || defined __DOXYGEN__ -#define LWIP_HTTPD_SUPPORT_11_KEEPALIVE 0 -#endif - -/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */ -#if !defined LWIP_HTTPD_SUPPORT_REQUESTLIST || defined __DOXYGEN__ -#define LWIP_HTTPD_SUPPORT_REQUESTLIST 1 -#endif - -#if LWIP_HTTPD_SUPPORT_REQUESTLIST -/** Number of rx pbufs to enqueue to parse an incoming request (up to the first - newline) */ -#if !defined LWIP_HTTPD_REQ_QUEUELEN || defined __DOXYGEN__ -#define LWIP_HTTPD_REQ_QUEUELEN 5 -#endif - -/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming - request (up to the first double-newline) */ -#if !defined LWIP_HTTPD_REQ_BUFSIZE || defined __DOXYGEN__ -#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH -#endif - -/** Defines the maximum length of a HTTP request line (up to the first CRLF, - copied from pbuf into this a global buffer when pbuf- or packet-queues - are received - otherwise the input pbuf is used directly) */ -#if !defined LWIP_HTTPD_MAX_REQ_LENGTH || defined __DOXYGEN__ -#define LWIP_HTTPD_MAX_REQ_LENGTH LWIP_MIN(1023, (LWIP_HTTPD_REQ_QUEUELEN * PBUF_POOL_BUFSIZE)) -#endif -#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ - -/** This is the size of a static buffer used when URIs end with '/'. - * In this buffer, the directory requested is concatenated with all the - * configured default file names. - * Set to 0 to disable checking default filenames on non-root directories. - */ -#if !defined LWIP_HTTPD_MAX_REQUEST_URI_LEN || defined __DOXYGEN__ -#define LWIP_HTTPD_MAX_REQUEST_URI_LEN 63 -#endif - -/** Maximum length of the filename to send as response to a POST request, - * filled in by the application when a POST is finished. - */ -#if !defined LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN || defined __DOXYGEN__ -#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63 -#endif - -/** Set this to 0 to not send the SSI tag (default is on, so the tag will - * be sent in the HTML page */ -#if !defined LWIP_HTTPD_SSI_INCLUDE_TAG || defined __DOXYGEN__ -#define LWIP_HTTPD_SSI_INCLUDE_TAG 1 -#endif - -/** Set this to 1 to call tcp_abort when tcp_close fails with memory error. - * This can be used to prevent consuming all memory in situations where the - * HTTP server has low priority compared to other communication. */ -#if !defined LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR || defined __DOXYGEN__ -#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0 -#endif - -/** Set this to 1 to kill the oldest connection when running out of - * memory for 'struct http_state' or 'struct http_ssi_state'. - * ATTENTION: This puts all connections on a linked list, so may be kind of slow. - */ -#if !defined LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED || defined __DOXYGEN__ -#define LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED 0 -#endif - -/** Set this to 1 to send URIs without extension without headers - * (who uses this at all??) */ -#if !defined LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI || defined __DOXYGEN__ -#define LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI 0 -#endif - -/** Default: Tags are sent from struct http_state and are therefore volatile */ -#if !defined HTTP_IS_TAG_VOLATILE || defined __DOXYGEN__ -#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY -#endif - -/* By default, the httpd is limited to send 2*pcb->mss to keep resource usage low - when http is not an important protocol in the device. */ -#if !defined HTTPD_LIMIT_SENDING_TO_2MSS || defined __DOXYGEN__ -#define HTTPD_LIMIT_SENDING_TO_2MSS 1 -#endif - -/* Define this to a function that returns the maximum amount of data to enqueue. - The function have this signature: u16_t fn(struct tcp_pcb* pcb); */ -#if !defined HTTPD_MAX_WRITE_LEN || defined __DOXYGEN__ -#if HTTPD_LIMIT_SENDING_TO_2MSS -#define HTTPD_MAX_WRITE_LEN(pcb) (2 * tcp_mss(pcb)) -#endif -#endif - -/*------------------- FS OPTIONS -------------------*/ - -/** Set this to 1 and provide the functions: - * - "int fs_open_custom(struct fs_file *file, const char *name)" - * Called first for every opened file to allow opening files - * that are not included in fsdata(_custom).c - * - "void fs_close_custom(struct fs_file *file)" - * Called to free resources allocated by fs_open_custom(). - */ -#if !defined LWIP_HTTPD_CUSTOM_FILES || defined __DOXYGEN__ -#define LWIP_HTTPD_CUSTOM_FILES 0 -#endif - -/** Set this to 1 to support fs_read() to dynamically read file data. - * Without this (default=off), only one-block files are supported, - * and the contents must be ready after fs_open(). - */ -#if !defined LWIP_HTTPD_DYNAMIC_FILE_READ || defined __DOXYGEN__ -#define LWIP_HTTPD_DYNAMIC_FILE_READ 0 -#endif - -/** Set this to 1 to include an application state argument per file - * that is opened. This allows to keep a state per connection/file. - */ -#if !defined LWIP_HTTPD_FILE_STATE || defined __DOXYGEN__ -#define LWIP_HTTPD_FILE_STATE 0 -#endif - -/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for - * predefined (MSS-sized) chunks of the files to prevent having to calculate - * the checksums at runtime. */ -#if !defined HTTPD_PRECALCULATED_CHECKSUM || defined __DOXYGEN__ -#define HTTPD_PRECALCULATED_CHECKSUM 0 -#endif - -/** LWIP_HTTPD_FS_ASYNC_READ==1: support asynchronous read operations - * (fs_read_async returns FS_READ_DELAYED and calls a callback when finished). - */ -#if !defined LWIP_HTTPD_FS_ASYNC_READ || defined __DOXYGEN__ -#define LWIP_HTTPD_FS_ASYNC_READ 0 -#endif - -/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the - * file system (to prevent changing the file included in CVS) */ -#if !defined HTTPD_USE_CUSTOM_FSDATA || defined __DOXYGEN__ -#define HTTPD_USE_CUSTOM_FSDATA 0 -#endif - -/** - * @} - */ - -#endif /* LWIP_HDR_APPS_HTTPD_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/lwiperf.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/lwiperf.h deleted file mode 100644 index 7dbebb08264d891ae270e8583417e89b65246c5b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/lwiperf.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * lwIP iPerf server implementation - */ - -/* - * Copyright (c) 2014 Simon Goldschmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_APPS_LWIPERF_H -#define LWIP_HDR_APPS_LWIPERF_H - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define LWIPERF_TCP_PORT_DEFAULT 5001 - -/** lwIPerf test results */ -enum lwiperf_report_type -{ - /** The server side test is done */ - LWIPERF_TCP_DONE_SERVER, - /** The client side test is done */ - LWIPERF_TCP_DONE_CLIENT, - /** Local error lead to test abort */ - LWIPERF_TCP_ABORTED_LOCAL, - /** Data check error lead to test abort */ - LWIPERF_TCP_ABORTED_LOCAL_DATAERROR, - /** Transmit error lead to test abort */ - LWIPERF_TCP_ABORTED_LOCAL_TXERROR, - /** Remote side aborted the test */ - LWIPERF_TCP_ABORTED_REMOTE -}; - -/** Prototype of a report function that is called when a session is finished. - This report function can show the test results. - @param report_type contains the test result */ -typedef void (*lwiperf_report_fn)(void *arg, enum lwiperf_report_type report_type, - const ip_addr_t* local_addr, u16_t local_port, const ip_addr_t* remote_addr, u16_t remote_port, - u32_t bytes_transferred, u32_t ms_duration, u32_t bandwidth_kbitpsec); - - -void* lwiperf_start_tcp_server(const ip_addr_t* local_addr, u16_t local_port, - lwiperf_report_fn report_fn, void* report_arg); -void* lwiperf_start_tcp_server_default(lwiperf_report_fn report_fn, void* report_arg); -void lwiperf_abort(void* lwiperf_session); - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_LWIPERF_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns.h deleted file mode 100644 index d036816115d5e5d5f166f76f1747f00f0a23688d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * MDNS responder - */ - - /* - * Copyright (c) 2015 Verisure Innovation AB - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ -#ifndef LWIP_HDR_MDNS_H -#define LWIP_HDR_MDNS_H - -#include "lwip/apps/mdns_opts.h" -#include "lwip/netif.h" - -#if LWIP_MDNS_RESPONDER - -enum mdns_sd_proto { - DNSSD_PROTO_UDP = 0, - DNSSD_PROTO_TCP = 1 -}; - -#define MDNS_LABEL_MAXLEN 63 - -struct mdns_host; -struct mdns_service; - -/** Callback function to add text to a reply, called when generating the reply */ -typedef void (*service_get_txt_fn_t)(struct mdns_service *service, void *txt_userdata); - -void mdns_resp_init(void); - -err_t mdns_resp_add_netif(struct netif *netif, const char *hostname, u32_t dns_ttl); -err_t mdns_resp_remove_netif(struct netif *netif); - -err_t mdns_resp_add_service(struct netif *netif, const char *name, const char *service, enum mdns_sd_proto proto, u16_t port, u32_t dns_ttl, service_get_txt_fn_t txt_fn, void *txt_userdata); -err_t mdns_resp_add_service_txtitem(struct mdns_service *service, const char *txt, u8_t txt_len); -void mdns_resp_netif_settings_changed(struct netif *netif); - -#endif /* LWIP_MDNS_RESPONDER */ - -#endif /* LWIP_HDR_MDNS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_opts.h deleted file mode 100644 index bf186bcce17396ede971e7488fcf33da611a0248..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_opts.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * MDNS responder - */ - - /* - * Copyright (c) 2015 Verisure Innovation AB - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ - -#ifndef LWIP_HDR_APPS_MDNS_OPTS_H -#define LWIP_HDR_APPS_MDNS_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup mdns_opts Options - * @ingroup mdns - * @{ - */ - -/** - * LWIP_MDNS_RESPONDER==1: Turn on multicast DNS module. UDP must be available for MDNS - * transport. IGMP is needed for IPv4 multicast. - */ -#ifndef LWIP_MDNS_RESPONDER -#define LWIP_MDNS_RESPONDER 0 -#endif /* LWIP_MDNS_RESPONDER */ - -/** The maximum number of services per netif */ -#ifndef MDNS_MAX_SERVICES -#define MDNS_MAX_SERVICES 1 -#endif - -/** - * MDNS_DEBUG: Enable debugging for multicast DNS. - */ -#ifndef MDNS_DEBUG -#define MDNS_DEBUG LWIP_DBG_OFF -#endif - -/** - * @} - */ - -#endif /* LWIP_HDR_APPS_MDNS_OPTS_H */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_priv.h deleted file mode 100644 index 8ee6db86af4ccb1bb50de0052abdf987fbeb0d40..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mdns_priv.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * @file - * MDNS responder private definitions - */ - - /* - * Copyright (c) 2015 Verisure Innovation AB - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ -#ifndef LWIP_HDR_MDNS_PRIV_H -#define LWIP_HDR_MDNS_PRIV_H - -#include "lwip/apps/mdns_opts.h" -#include "lwip/pbuf.h" - -#if LWIP_MDNS_RESPONDER - -/* Domain struct and methods - visible for unit tests */ - -#define MDNS_DOMAIN_MAXLEN 256 -#define MDNS_READNAME_ERROR 0xFFFF - -struct mdns_domain { - /* Encoded domain name */ - u8_t name[MDNS_DOMAIN_MAXLEN]; - /* Total length of domain name, including zero */ - u16_t length; - /* Set if compression of this domain is not allowed */ - u8_t skip_compression; -}; - -err_t mdns_domain_add_label(struct mdns_domain *domain, const char *label, u8_t len); -u16_t mdns_readname(struct pbuf *p, u16_t offset, struct mdns_domain *domain); -int mdns_domain_eq(struct mdns_domain *a, struct mdns_domain *b); -u16_t mdns_compress_domain(struct pbuf *pbuf, u16_t *offset, struct mdns_domain *domain); - -#endif /* LWIP_MDNS_RESPONDER */ - -#endif /* LWIP_HDR_MDNS_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt.h deleted file mode 100644 index 34b230b888b79a6b59c0a61cac3aece2e3121b88..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt.h +++ /dev/null @@ -1,244 +0,0 @@ -/** - * @file - * MQTT client - */ - -/* - * Copyright (c) 2016 Erik Andersson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Andersson - * - */ -#ifndef LWIP_HDR_APPS_MQTT_CLIENT_H -#define LWIP_HDR_APPS_MQTT_CLIENT_H - -#include "lwip/apps/mqtt_opts.h" -#include "lwip/err.h" -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct mqtt_client_t mqtt_client_t; - -/** @ingroup mqtt - * Default MQTT port */ -#define MQTT_PORT 1883 - -/*---------------------------------------------------------------------------------------------- */ -/* Connection with server */ - -/** - * @ingroup mqtt - * Client information and connection parameters */ -struct mqtt_connect_client_info_t { - /** Client identifier, must be set by caller */ - const char *client_id; - /** User name and password, set to NULL if not used */ - const char* client_user; - const char* client_pass; - /** keep alive time in seconds, 0 to disable keep alive functionality*/ - u16_t keep_alive; - /** will topic, set to NULL if will is not to be used, - will_msg, will_qos and will retain are then ignored */ - const char* will_topic; - const char* will_msg; - u8_t will_qos; - u8_t will_retain; -}; - -/** - * @ingroup mqtt - * Connection status codes */ -typedef enum -{ - MQTT_CONNECT_ACCEPTED = 0, - MQTT_CONNECT_REFUSED_PROTOCOL_VERSION = 1, - MQTT_CONNECT_REFUSED_IDENTIFIER = 2, - MQTT_CONNECT_REFUSED_SERVER = 3, - MQTT_CONNECT_REFUSED_USERNAME_PASS = 4, - MQTT_CONNECT_REFUSED_NOT_AUTHORIZED_ = 5, - MQTT_CONNECT_DISCONNECTED = 256, - MQTT_CONNECT_TIMEOUT = 257 -} mqtt_connection_status_t; - -/** - * @ingroup mqtt - * Function prototype for mqtt connection status callback. Called when - * client has connected to the server after initiating a mqtt connection attempt by - * calling mqtt_connect() or when connection is closed by server or an error - * - * @param client MQTT client itself - * @param arg Additional argument to pass to the callback function - * @param status Connect result code or disconnection notification @see mqtt_connection_status_t - * - */ -typedef void (*mqtt_connection_cb_t)(mqtt_client_t *client, void *arg, mqtt_connection_status_t status); - - -/** - * @ingroup mqtt - * Data callback flags */ -enum { - /** Flag set when last fragment of data arrives in data callback */ - MQTT_DATA_FLAG_LAST = 1 -}; - -/** - * @ingroup mqtt - * Function prototype for MQTT incoming publish data callback function. Called when data - * arrives to a subscribed topic @see mqtt_subscribe - * - * @param arg Additional argument to pass to the callback function - * @param data User data, pointed object, data may not be referenced after callback return, - NULL is passed when all publish data are delivered - * @param len Length of publish data fragment - * @param flags MQTT_DATA_FLAG_LAST set when this call contains the last part of data from publish message - * - */ -typedef void (*mqtt_incoming_data_cb_t)(void *arg, const u8_t *data, u16_t len, u8_t flags); - - -/** - * @ingroup mqtt - * Function prototype for MQTT incoming publish function. Called when an incoming publish - * arrives to a subscribed topic @see mqtt_subscribe - * - * @param arg Additional argument to pass to the callback function - * @param topic Zero terminated Topic text string, topic may not be referenced after callback return - * @param tot_len Total length of publish data, if set to 0 (no publish payload) data callback will not be invoked - */ -typedef void (*mqtt_incoming_publish_cb_t)(void *arg, const char *topic, u32_t tot_len); - - -/** - * @ingroup mqtt - * Function prototype for mqtt request callback. Called when a subscribe, unsubscribe - * or publish request has completed - * @param arg Pointer to user data supplied when invoking request - * @param err ERR_OK on success - * ERR_TIMEOUT if no response was received within timeout, - * ERR_ABRT if (un)subscribe was denied - */ -typedef void (*mqtt_request_cb_t)(void *arg, err_t err); - - -/** - * Pending request item, binds application callback to pending server requests - */ -struct mqtt_request_t -{ - /** Next item in list, NULL means this is the last in chain, - next pointing at itself means request is unallocated */ - struct mqtt_request_t *next; - /** Callback to upper layer */ - mqtt_request_cb_t cb; - void *arg; - /** MQTT packet identifier */ - u16_t pkt_id; - /** Expire time relative to element before this */ - u16_t timeout_diff; -}; - -/** Ring buffer */ -struct mqtt_ringbuf_t { - u16_t put; - u16_t get; - u8_t buf[MQTT_OUTPUT_RINGBUF_SIZE]; -}; - -/** MQTT client */ -struct mqtt_client_t -{ - /** Timers and timeouts */ - u16_t cyclic_tick; - u16_t keep_alive; - u16_t server_watchdog; - /** Packet identifier generator*/ - u16_t pkt_id_seq; - /** Packet identifier of pending incoming publish */ - u16_t inpub_pkt_id; - /** Connection state */ - u8_t conn_state; - struct tcp_pcb *conn; - /** Connection callback */ - void *connect_arg; - mqtt_connection_cb_t connect_cb; - /** Pending requests to server */ - struct mqtt_request_t *pend_req_queue; - struct mqtt_request_t req_list[MQTT_REQ_MAX_IN_FLIGHT]; - void *inpub_arg; - /** Incoming data callback */ - mqtt_incoming_data_cb_t data_cb; - mqtt_incoming_publish_cb_t pub_cb; - /** Input */ - u32_t msg_idx; - u8_t rx_buffer[MQTT_VAR_HEADER_BUFFER_LEN]; - /** Output ring-buffer */ - struct mqtt_ringbuf_t output; -}; - - -/** Connect to server */ -err_t mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ipaddr, u16_t port, mqtt_connection_cb_t cb, void *arg, - const struct mqtt_connect_client_info_t *client_info); - -/** Disconnect from server */ -void mqtt_disconnect(mqtt_client_t *client); - -/** Create new client */ -mqtt_client_t *mqtt_client_new(void); - -/** Check connection status */ -u8_t mqtt_client_is_connected(mqtt_client_t *client); - -/** Set callback to call for incoming publish */ -void mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t, - mqtt_incoming_data_cb_t data_cb, void *arg); - -/** Common function for subscribe and unsubscribe */ -err_t mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub); - -/** @ingroup mqtt - *Subscribe to topic */ -#define mqtt_subscribe(client, topic, qos, cb, arg) mqtt_sub_unsub(client, topic, qos, cb, arg, 1) -/** @ingroup mqtt - * Unsubscribe to topic */ -#define mqtt_unsubscribe(client, topic, cb, arg) mqtt_sub_unsub(client, topic, 0, cb, arg, 0) - - -/** Publish data to topic */ -err_t mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain, - mqtt_request_cb_t cb, void *arg); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_MQTT_CLIENT_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt_opts.h deleted file mode 100644 index ffefacd2595173f1da34e4f1eee393bef36e4fb2..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/mqtt_opts.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file - * MQTT client options - */ - -/* - * Copyright (c) 2016 Erik Andersson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Andersson - * - */ -#ifndef LWIP_HDR_APPS_MQTT_OPTS_H -#define LWIP_HDR_APPS_MQTT_OPTS_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup mqtt_opts Options - * @ingroup mqtt - * @{ - */ - -/** - * Output ring-buffer size, must be able to fit largest outgoing publish message topic+payloads - */ -#ifndef MQTT_OUTPUT_RINGBUF_SIZE -#define MQTT_OUTPUT_RINGBUF_SIZE 256 -#endif - -/** - * Number of bytes in receive buffer, must be at least the size of the longest incoming topic + 8 - * If one wants to avoid fragmented incoming publish, set length to max incoming topic length + max payload length + 8 - */ -#ifndef MQTT_VAR_HEADER_BUFFER_LEN -#define MQTT_VAR_HEADER_BUFFER_LEN 128 -#endif - -/** - * Maximum number of pending subscribe, unsubscribe and publish requests to server . - */ -#ifndef MQTT_REQ_MAX_IN_FLIGHT -#define MQTT_REQ_MAX_IN_FLIGHT 4 -#endif - -/** - * Seconds between each cyclic timer call. - */ -#ifndef MQTT_CYCLIC_TIMER_INTERVAL -#define MQTT_CYCLIC_TIMER_INTERVAL 5 -#endif - -/** - * Publish, subscribe and unsubscribe request timeout in seconds. - */ -#ifndef MQTT_REQ_TIMEOUT -#define MQTT_REQ_TIMEOUT 30 -#endif - -/** - * Seconds for MQTT connect response timeout after sending connect request - */ -#ifndef MQTT_CONNECT_TIMOUT -#define MQTT_CONNECT_TIMOUT 100 -#endif - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_MQTT_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns.h deleted file mode 100644 index c9f68d8d12c64b6d8388d3657bb373ea5df53d3e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * NETBIOS name service responder - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ -#ifndef LWIP_HDR_APPS_NETBIOS_H -#define LWIP_HDR_APPS_NETBIOS_H - -#include "lwip/apps/netbiosns_opts.h" - -void netbiosns_init(void); -#ifndef NETBIOS_LWIP_NAME -void netbiosns_set_name(const char* hostname); -#endif -void netbiosns_stop(void); - -#endif /* LWIP_HDR_APPS_NETBIOS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns_opts.h deleted file mode 100644 index 0909ef7b94ef6af37879fcb9e7c45d9f981c9092..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/netbiosns_opts.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * @file - * NETBIOS name service responder options - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ -#ifndef LWIP_HDR_APPS_NETBIOS_OPTS_H -#define LWIP_HDR_APPS_NETBIOS_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup netbiosns_opts Options - * @ingroup netbiosns - * @{ - */ - -/** NetBIOS name of lwip device - * This must be uppercase until NETBIOS_STRCMP() is defined to a string - * comparision function that is case insensitive. - * If you want to use the netif's hostname, use this (with LWIP_NETIF_HOSTNAME): - * (ip_current_netif() != NULL ? ip_current_netif()->hostname != NULL ? ip_current_netif()->hostname : "" : "") - * - * If this is not defined, netbiosns_set_name() can be called at runtime to change the name. - */ -#ifdef __DOXYGEN__ -#define NETBIOS_LWIP_NAME "NETBIOSLWIPDEV" -#endif - -/** - * @} - */ - -#endif /* LWIP_HDR_APPS_NETBIOS_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp.h deleted file mode 100644 index 10e8ff434bb8f253c6e41980df96dc3876202ea1..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * @file - * SNMP server main API - start and basic configuration - */ - -/* - * Copyright (c) 2001, 2002 Leon Woestenberg - * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * Martin Hentschel - * - */ -#ifndef LWIP_HDR_APPS_SNMP_H -#define LWIP_HDR_APPS_SNMP_H - -#include "lwip/apps/snmp_opts.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/err.h" -#include "lwip/apps/snmp_core.h" - -/** SNMP variable binding descriptor (publically needed for traps) */ -struct snmp_varbind -{ - /** pointer to next varbind, NULL for last in list */ - struct snmp_varbind *next; - /** pointer to previous varbind, NULL for first in list */ - struct snmp_varbind *prev; - - /** object identifier */ - struct snmp_obj_id oid; - - /** value ASN1 type */ - u8_t type; - /** object value length */ - u16_t value_len; - /** object value */ - void *value; -}; - -/** - * @ingroup snmp_core - * Agent setup, start listening to port 161. - */ -void snmp_init(void); -void snmp_set_mibs(const struct snmp_mib **mibs, u8_t num_mibs); - -void snmp_set_device_enterprise_oid(const struct snmp_obj_id* device_enterprise_oid); -const struct snmp_obj_id* snmp_get_device_enterprise_oid(void); - -void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); -void snmp_trap_dst_ip_set(u8_t dst_idx, const ip_addr_t *dst); - -/** Generic trap: cold start */ -#define SNMP_GENTRAP_COLDSTART 0 -/** Generic trap: warm start */ -#define SNMP_GENTRAP_WARMSTART 1 -/** Generic trap: link down */ -#define SNMP_GENTRAP_LINKDOWN 2 -/** Generic trap: link up */ -#define SNMP_GENTRAP_LINKUP 3 -/** Generic trap: authentication failure */ -#define SNMP_GENTRAP_AUTH_FAILURE 4 -/** Generic trap: EGP neighbor lost */ -#define SNMP_GENTRAP_EGP_NEIGHBOR_LOSS 5 -/** Generic trap: enterprise specific */ -#define SNMP_GENTRAP_ENTERPRISE_SPECIFIC 6 - -err_t snmp_send_trap_generic(s32_t generic_trap); -err_t snmp_send_trap_specific(s32_t specific_trap, struct snmp_varbind *varbinds); -err_t snmp_send_trap(const struct snmp_obj_id* oid, s32_t generic_trap, s32_t specific_trap, struct snmp_varbind *varbinds); - -#define SNMP_AUTH_TRAPS_DISABLED 0 -#define SNMP_AUTH_TRAPS_ENABLED 1 -void snmp_set_auth_traps_enabled(u8_t enable); -u8_t snmp_get_auth_traps_enabled(void); - -const char * snmp_get_community(void); -const char * snmp_get_community_write(void); -const char * snmp_get_community_trap(void); -void snmp_set_community(const char * const community); -void snmp_set_community_write(const char * const community); -void snmp_set_community_trap(const char * const community); - -void snmp_coldstart_trap(void); -void snmp_authfail_trap(void); - -typedef void (*snmp_write_callback_fct)(const u32_t* oid, u8_t oid_len, void* callback_arg); -void snmp_set_write_callback(snmp_write_callback_fct write_callback, void* callback_arg); - -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_core.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_core.h deleted file mode 100644 index e781c532b38e7e97beb99d72168ccf36672e4d0b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_core.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * @file - * SNMP core API for implementing MIBs - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - * Martin Hentschel - */ - -#ifndef LWIP_HDR_APPS_SNMP_CORE_H -#define LWIP_HDR_APPS_SNMP_CORE_H - -#include "lwip/apps/snmp_opts.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip_addr.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* basic ASN1 defines */ -#define SNMP_ASN1_CLASS_UNIVERSAL 0x00 -#define SNMP_ASN1_CLASS_APPLICATION 0x40 -#define SNMP_ASN1_CLASS_CONTEXT 0x80 -#define SNMP_ASN1_CLASS_PRIVATE 0xC0 - -#define SNMP_ASN1_CONTENTTYPE_PRIMITIVE 0x00 -#define SNMP_ASN1_CONTENTTYPE_CONSTRUCTED 0x20 - -/* universal tags (from ASN.1 spec.) */ -#define SNMP_ASN1_UNIVERSAL_END_OF_CONTENT 0 -#define SNMP_ASN1_UNIVERSAL_INTEGER 2 -#define SNMP_ASN1_UNIVERSAL_OCTET_STRING 4 -#define SNMP_ASN1_UNIVERSAL_NULL 5 -#define SNMP_ASN1_UNIVERSAL_OBJECT_ID 6 -#define SNMP_ASN1_UNIVERSAL_SEQUENCE_OF 16 - -/* application specific (SNMP) tags (from SNMPv2-SMI) */ -#define SNMP_ASN1_APPLICATION_IPADDR 0 /* [APPLICATION 0] IMPLICIT OCTET STRING (SIZE (4)) */ -#define SNMP_ASN1_APPLICATION_COUNTER 1 /* [APPLICATION 1] IMPLICIT INTEGER (0..4294967295) => u32_t */ -#define SNMP_ASN1_APPLICATION_GAUGE 2 /* [APPLICATION 2] IMPLICIT INTEGER (0..4294967295) => u32_t */ -#define SNMP_ASN1_APPLICATION_TIMETICKS 3 /* [APPLICATION 3] IMPLICIT INTEGER (0..4294967295) => u32_t */ -#define SNMP_ASN1_APPLICATION_OPAQUE 4 /* [APPLICATION 4] IMPLICIT OCTET STRING */ -#define SNMP_ASN1_APPLICATION_COUNTER64 6 /* [APPLICATION 6] IMPLICIT INTEGER (0..18446744073709551615) */ - -/* context specific (SNMP) tags (from RFC 1905) */ -#define SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE 1 - -/* full ASN1 type defines */ -#define SNMP_ASN1_TYPE_END_OF_CONTENT (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_END_OF_CONTENT) -#define SNMP_ASN1_TYPE_INTEGER (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_INTEGER) -#define SNMP_ASN1_TYPE_OCTET_STRING (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OCTET_STRING) -#define SNMP_ASN1_TYPE_NULL (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_NULL) -#define SNMP_ASN1_TYPE_OBJECT_ID (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OBJECT_ID) -#define SNMP_ASN1_TYPE_SEQUENCE (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_UNIVERSAL_SEQUENCE_OF) -#define SNMP_ASN1_TYPE_IPADDR (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_IPADDR) -#define SNMP_ASN1_TYPE_IPADDRESS SNMP_ASN1_TYPE_IPADDR -#define SNMP_ASN1_TYPE_COUNTER (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER) -#define SNMP_ASN1_TYPE_COUNTER32 SNMP_ASN1_TYPE_COUNTER -#define SNMP_ASN1_TYPE_GAUGE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_GAUGE) -#define SNMP_ASN1_TYPE_GAUGE32 SNMP_ASN1_TYPE_GAUGE -#define SNMP_ASN1_TYPE_UNSIGNED32 SNMP_ASN1_TYPE_GAUGE -#define SNMP_ASN1_TYPE_TIMETICKS (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_TIMETICKS) -#define SNMP_ASN1_TYPE_OPAQUE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_OPAQUE) -#define SNMP_ASN1_TYPE_COUNTER64 (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER64) - -#define SNMP_VARBIND_EXCEPTION_OFFSET 0xF0 -#define SNMP_VARBIND_EXCEPTION_MASK 0x0F - -/** error codes predefined by SNMP prot. */ -typedef enum { - SNMP_ERR_NOERROR = 0, -/* -outdated v1 error codes. do not use anmore! -#define SNMP_ERR_NOSUCHNAME 2 use SNMP_ERR_NOSUCHINSTANCE instead -#define SNMP_ERR_BADVALUE 3 use SNMP_ERR_WRONGTYPE,SNMP_ERR_WRONGLENGTH,SNMP_ERR_WRONGENCODING or SNMP_ERR_WRONGVALUE instead -#define SNMP_ERR_READONLY 4 use SNMP_ERR_NOTWRITABLE instead -*/ - SNMP_ERR_GENERROR = 5, - SNMP_ERR_NOACCESS = 6, - SNMP_ERR_WRONGTYPE = 7, - SNMP_ERR_WRONGLENGTH = 8, - SNMP_ERR_WRONGENCODING = 9, - SNMP_ERR_WRONGVALUE = 10, - SNMP_ERR_NOCREATION = 11, - SNMP_ERR_INCONSISTENTVALUE = 12, - SNMP_ERR_RESOURCEUNAVAILABLE = 13, - SNMP_ERR_COMMITFAILED = 14, - SNMP_ERR_UNDOFAILED = 15, - SNMP_ERR_NOTWRITABLE = 17, - SNMP_ERR_INCONSISTENTNAME = 18, - - SNMP_ERR_NOSUCHINSTANCE = SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE -} snmp_err_t; - -/** internal object identifier representation */ -struct snmp_obj_id -{ - u8_t len; - u32_t id[SNMP_MAX_OBJ_ID_LEN]; -}; - -struct snmp_obj_id_const_ref -{ - u8_t len; - const u32_t* id; -}; - -extern const struct snmp_obj_id_const_ref snmp_zero_dot_zero; /* administrative identifier from SNMPv2-SMI */ - -/** SNMP variant value, used as reference in struct snmp_node_instance and table implementation */ -union snmp_variant_value -{ - void* ptr; - const void* const_ptr; - u32_t u32; - s32_t s32; -}; - - -/** -SNMP MIB node types - tree node is the only node the stack can process in order to walk the tree, - all other nodes are assumed to be leaf nodes. - This cannot be an enum because users may want to define their own node types. -*/ -#define SNMP_NODE_TREE 0x00 -/* predefined leaf node types */ -#define SNMP_NODE_SCALAR 0x01 -#define SNMP_NODE_SCALAR_ARRAY 0x02 -#define SNMP_NODE_TABLE 0x03 -#define SNMP_NODE_THREADSYNC 0x04 - -/** node "base class" layout, the mandatory fields for a node */ -struct snmp_node -{ - /** one out of SNMP_NODE_TREE or any leaf node type (like SNMP_NODE_SCALAR) */ - u8_t node_type; - /** the number assigned to this node which used as part of the full OID */ - u32_t oid; -}; - -/** SNMP node instance access types */ -typedef enum { - SNMP_NODE_INSTANCE_ACCESS_READ = 1, - SNMP_NODE_INSTANCE_ACCESS_WRITE = 2, - SNMP_NODE_INSTANCE_READ_ONLY = SNMP_NODE_INSTANCE_ACCESS_READ, - SNMP_NODE_INSTANCE_READ_WRITE = (SNMP_NODE_INSTANCE_ACCESS_READ | SNMP_NODE_INSTANCE_ACCESS_WRITE), - SNMP_NODE_INSTANCE_WRITE_ONLY = SNMP_NODE_INSTANCE_ACCESS_WRITE, - SNMP_NODE_INSTANCE_NOT_ACCESSIBLE = 0 -} snmp_access_t; - -struct snmp_node_instance; - -typedef s16_t (*node_instance_get_value_method)(struct snmp_node_instance*, void*); -typedef snmp_err_t (*node_instance_set_test_method)(struct snmp_node_instance*, u16_t, void*); -typedef snmp_err_t (*node_instance_set_value_method)(struct snmp_node_instance*, u16_t, void*); -typedef void (*node_instance_release_method)(struct snmp_node_instance*); - -#define SNMP_GET_VALUE_RAW_DATA 0x8000 - -/** SNMP node instance */ -struct snmp_node_instance -{ - /** prefilled with the node, get_instance() is called on; may be changed by user to any value to pass an arbitrary node between calls to get_instance() and get_value/test_value/set_value */ - const struct snmp_node* node; - /** prefilled with the instance id requested; for get_instance() this is the exact oid requested; for get_next_instance() this is the relative starting point, stack expects relative oid of next node here */ - struct snmp_obj_id instance_oid; - - /** ASN type for this object (see snmp_asn1.h for definitions) */ - u8_t asn1_type; - /** one out of instance access types defined above (SNMP_NODE_INSTANCE_READ_ONLY,...) */ - snmp_access_t access; - - /** returns object value for the given object identifier. Return values <0 to indicate an error */ - node_instance_get_value_method get_value; - /** tests length and/or range BEFORE setting */ - node_instance_set_test_method set_test; - /** sets object value, only called when set_test() was successful */ - node_instance_set_value_method set_value; - /** called in any case when the instance is not required anymore by stack (useful for freeing memory allocated in get_instance/get_next_instance methods) */ - node_instance_release_method release_instance; - - /** reference to pass arbitrary value between calls to get_instance() and get_value/test_value/set_value */ - union snmp_variant_value reference; - /** see reference (if reference is a pointer, the length of underlying data may be stored here or anything else) */ - u32_t reference_len; -}; - - -/** SNMP tree node */ -struct snmp_tree_node -{ - /** inherited "base class" members */ - struct snmp_node node; - u16_t subnode_count; - const struct snmp_node* const *subnodes; -}; - -#define SNMP_CREATE_TREE_NODE(oid, subnodes) \ - {{ SNMP_NODE_TREE, (oid) }, \ - (u16_t)LWIP_ARRAYSIZE(subnodes), (subnodes) } - -#define SNMP_CREATE_EMPTY_TREE_NODE(oid) \ - {{ SNMP_NODE_TREE, (oid) }, \ - 0, NULL } - -/** SNMP leaf node */ -struct snmp_leaf_node -{ - /** inherited "base class" members */ - struct snmp_node node; - snmp_err_t (*get_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - snmp_err_t (*get_next_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -}; - -/** represents a single mib with its base oid and root node */ -struct snmp_mib -{ - const u32_t *base_oid; - u8_t base_oid_len; - const struct snmp_node *root_node; -}; - -#define SNMP_MIB_CREATE(oid_list, root_node) { (oid_list), (u8_t)LWIP_ARRAYSIZE(oid_list), root_node } - -/** OID range structure */ -struct snmp_oid_range -{ - u32_t min; - u32_t max; -}; - -/** checks if incoming OID length and values are in allowed ranges */ -u8_t snmp_oid_in_range(const u32_t *oid_in, u8_t oid_len, const struct snmp_oid_range *oid_ranges, u8_t oid_ranges_len); - -typedef enum { - SNMP_NEXT_OID_STATUS_SUCCESS, - SNMP_NEXT_OID_STATUS_NO_MATCH, - SNMP_NEXT_OID_STATUS_BUF_TO_SMALL -} snmp_next_oid_status_t; - -/** state for next_oid_init / next_oid_check functions */ -struct snmp_next_oid_state -{ - const u32_t* start_oid; - u8_t start_oid_len; - - u32_t* next_oid; - u8_t next_oid_len; - u8_t next_oid_max_len; - - snmp_next_oid_status_t status; - void* reference; -}; - -void snmp_next_oid_init(struct snmp_next_oid_state *state, - const u32_t *start_oid, u8_t start_oid_len, - u32_t *next_oid_buf, u8_t next_oid_max_len); -u8_t snmp_next_oid_precheck(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len); -u8_t snmp_next_oid_check(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len, void* reference); - -void snmp_oid_assign(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); -void snmp_oid_combine(struct snmp_obj_id* target, const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); -void snmp_oid_prefix(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); -void snmp_oid_append(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); -u8_t snmp_oid_equal(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); -s8_t snmp_oid_compare(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); - -#if LWIP_IPV4 -u8_t snmp_oid_to_ip4(const u32_t *oid, ip4_addr_t *ip); -void snmp_ip4_to_oid(const ip4_addr_t *ip, u32_t *oid); -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 -u8_t snmp_oid_to_ip6(const u32_t *oid, ip6_addr_t *ip); -void snmp_ip6_to_oid(const ip6_addr_t *ip, u32_t *oid); -#endif /* LWIP_IPV6 */ -#if LWIP_IPV4 || LWIP_IPV6 -u8_t snmp_ip_to_oid(const ip_addr_t *ip, u32_t *oid); -u8_t snmp_ip_port_to_oid(const ip_addr_t *ip, u16_t port, u32_t *oid); - -u8_t snmp_oid_to_ip(const u32_t *oid, u8_t oid_len, ip_addr_t *ip); -u8_t snmp_oid_to_ip_port(const u32_t *oid, u8_t oid_len, ip_addr_t *ip, u16_t *port); -#endif /* LWIP_IPV4 || LWIP_IPV6 */ - -struct netif; -u8_t netif_to_num(const struct netif *netif); - -snmp_err_t snmp_set_test_ok(struct snmp_node_instance* instance, u16_t value_len, void* value); /* generic function which can be used if test is always successful */ - -err_t snmp_decode_bits(const u8_t *buf, u32_t buf_len, u32_t *bit_value); -err_t snmp_decode_truthvalue(const s32_t *asn1_value, u8_t *bool_value); -u8_t snmp_encode_bits(u8_t *buf, u32_t buf_len, u32_t bit_value, u8_t bit_count); -u8_t snmp_encode_truthvalue(s32_t *asn1_value, u32_t bool_value); - -struct snmp_statistics -{ - u32_t inpkts; - u32_t outpkts; - u32_t inbadversions; - u32_t inbadcommunitynames; - u32_t inbadcommunityuses; - u32_t inasnparseerrs; - u32_t intoobigs; - u32_t innosuchnames; - u32_t inbadvalues; - u32_t inreadonlys; - u32_t ingenerrs; - u32_t intotalreqvars; - u32_t intotalsetvars; - u32_t ingetrequests; - u32_t ingetnexts; - u32_t insetrequests; - u32_t ingetresponses; - u32_t intraps; - u32_t outtoobigs; - u32_t outnosuchnames; - u32_t outbadvalues; - u32_t outgenerrs; - u32_t outgetrequests; - u32_t outgetnexts; - u32_t outsetrequests; - u32_t outgetresponses; - u32_t outtraps; -}; - -extern struct snmp_statistics snmp_stats; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* LWIP_HDR_APPS_SNMP_CORE_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_mib2.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_mib2.h deleted file mode 100644 index 2f4a68935e2a78d927f1956fad3fad71546784c5..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_mib2.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * @file - * SNMP MIB2 API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Dirk Ziegelmeier - * - */ -#ifndef LWIP_HDR_APPS_SNMP_MIB2_H -#define LWIP_HDR_APPS_SNMP_MIB2_H - -#include "lwip/apps/snmp_opts.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ -#if SNMP_LWIP_MIB2 - -#include "lwip/apps/snmp_core.h" - -extern const struct snmp_mib mib2; - -#if SNMP_USE_NETCONN -#include "lwip/apps/snmp_threadsync.h" -void snmp_mib2_lwip_synchronizer(snmp_threadsync_called_fn fn, void* arg); -extern struct snmp_threadsync_instance snmp_mib2_lwip_locks; -#endif - -#ifndef SNMP_SYSSERVICES -#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) -#endif - -void snmp_mib2_set_sysdescr(const u8_t* str, const u16_t* len); /* read-only be defintion */ -void snmp_mib2_set_syscontact(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); -void snmp_mib2_set_syscontact_readonly(const u8_t *ocstr, const u16_t *ocstrlen); -void snmp_mib2_set_sysname(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); -void snmp_mib2_set_sysname_readonly(const u8_t *ocstr, const u16_t *ocstrlen); -void snmp_mib2_set_syslocation(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); -void snmp_mib2_set_syslocation_readonly(const u8_t *ocstr, const u16_t *ocstrlen); - -#endif /* SNMP_LWIP_MIB2 */ -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNMP_MIB2_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_opts.h deleted file mode 100644 index 6c9ba7beb3321c764dabac07216b349c20b4a64f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_opts.h +++ /dev/null @@ -1,293 +0,0 @@ -/** - * @file - * SNMP server options list - */ - -/* - * Copyright (c) 2015 Dirk Ziegelmeier - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Dirk Ziegelmeier - * - */ -#ifndef LWIP_HDR_SNMP_OPTS_H -#define LWIP_HDR_SNMP_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup snmp_opts Options - * @ingroup snmp - * @{ - */ - -/** - * LWIP_SNMP==1: This enables the lwIP SNMP agent. UDP must be available - * for SNMP transport. - * If you want to use your own SNMP agent, leave this disabled. - * To integrate MIB2 of an external agent, you need to enable - * LWIP_MIB2_CALLBACKS and MIB2_STATS. This will give you the callbacks - * and statistics counters you need to get MIB2 working. - */ -#if !defined LWIP_SNMP || defined __DOXYGEN__ -#define LWIP_SNMP 0 -#endif - -/** - * SNMP_USE_NETCONN: Use netconn API instead of raw API. - * Makes SNMP agent run in a worker thread, so blocking operations - * can be done in MIB calls. - */ -#if !defined SNMP_USE_NETCONN || defined __DOXYGEN__ -#define SNMP_USE_NETCONN 0 -#endif - -/** - * SNMP_USE_RAW: Use raw API. - * SNMP agent does not run in a worker thread, so blocking operations - * should not be done in MIB calls. - */ -#if !defined SNMP_USE_RAW || defined __DOXYGEN__ -#define SNMP_USE_RAW 1 -#endif - -#if SNMP_USE_NETCONN && SNMP_USE_RAW -#error SNMP stack can use only one of the APIs {raw, netconn} -#endif - -#if LWIP_SNMP && !SNMP_USE_NETCONN && !SNMP_USE_RAW -#error SNMP stack needs a receive API and UDP {raw, netconn} -#endif - -#if SNMP_USE_NETCONN -/** - * SNMP_STACK_SIZE: Stack size of SNMP netconn worker thread - */ -#if !defined SNMP_STACK_SIZE || defined __DOXYGEN__ -#define SNMP_STACK_SIZE DEFAULT_THREAD_STACKSIZE -#endif - -/** - * SNMP_THREAD_PRIO: SNMP netconn worker thread priority - */ -#if !defined SNMP_THREAD_PRIO || defined __DOXYGEN__ -#define SNMP_THREAD_PRIO DEFAULT_THREAD_PRIO -#endif -#endif /* SNMP_USE_NETCONN */ - -/** - * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap - * destination is required - */ -#if !defined SNMP_TRAP_DESTINATIONS || defined __DOXYGEN__ -#define SNMP_TRAP_DESTINATIONS 1 -#endif - -/** - * Only allow SNMP write actions that are 'safe' (e.g. disabling netifs is not - * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). - * Unsafe requests are disabled by default! - */ -#if !defined SNMP_SAFE_REQUESTS || defined __DOXYGEN__ -#define SNMP_SAFE_REQUESTS 1 -#endif - -/** - * The maximum length of strings used. - */ -#if !defined SNMP_MAX_OCTET_STRING_LEN || defined __DOXYGEN__ -#define SNMP_MAX_OCTET_STRING_LEN 127 -#endif - -/** - * The maximum number of Sub ID's inside an object identifier. - * Indirectly this also limits the maximum depth of SNMP tree. - */ -#if !defined SNMP_MAX_OBJ_ID_LEN || defined __DOXYGEN__ -#define SNMP_MAX_OBJ_ID_LEN 50 -#endif - -#if !defined SNMP_MAX_VALUE_SIZE || defined __DOXYGEN__ -/** - * The maximum size of a value. - */ -#define SNMP_MIN_VALUE_SIZE (2 * sizeof(u32_t*)) /* size required to store the basic types (8 bytes for counter64) */ -/** - * The minimum size of a value. - */ -#define SNMP_MAX_VALUE_SIZE LWIP_MAX(LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN), sizeof(u32_t)*(SNMP_MAX_OBJ_ID_LEN)), SNMP_MIN_VALUE_SIZE) -#endif - -/** - * The snmp read-access community. Used for write-access and traps, too - * unless SNMP_COMMUNITY_WRITE or SNMP_COMMUNITY_TRAP are enabled, respectively. - */ -#if !defined SNMP_COMMUNITY || defined __DOXYGEN__ -#define SNMP_COMMUNITY "public" -#endif - -/** - * The snmp write-access community. - * Set this community to "" in order to disallow any write access. - */ -#if !defined SNMP_COMMUNITY_WRITE || defined __DOXYGEN__ -#define SNMP_COMMUNITY_WRITE "private" -#endif - -/** - * The snmp community used for sending traps. - */ -#if !defined SNMP_COMMUNITY_TRAP || defined __DOXYGEN__ -#define SNMP_COMMUNITY_TRAP "public" -#endif - -/** - * The maximum length of community string. - * If community names shall be adjusted at runtime via snmp_set_community() calls, - * enter here the possible maximum length (+1 for terminating null character). - */ -#if !defined SNMP_MAX_COMMUNITY_STR_LEN || defined __DOXYGEN__ -#define SNMP_MAX_COMMUNITY_STR_LEN LWIP_MAX(LWIP_MAX(sizeof(SNMP_COMMUNITY), sizeof(SNMP_COMMUNITY_WRITE)), sizeof(SNMP_COMMUNITY_TRAP)) -#endif - -/** - * The OID identifiying the device. This may be the enterprise OID itself or any OID located below it in tree. - */ -#if !defined SNMP_DEVICE_ENTERPRISE_OID || defined __DOXYGEN__ -#define SNMP_LWIP_ENTERPRISE_OID 26381 -/** - * IANA assigned enterprise ID for lwIP is 26381 - * @see http://www.iana.org/assignments/enterprise-numbers - * - * @note this enterprise ID is assigned to the lwIP project, - * all object identifiers living under this ID are assigned - * by the lwIP maintainers! - * @note don't change this define, use snmp_set_device_enterprise_oid() - * - * If you need to create your own private MIB you'll need - * to apply for your own enterprise ID with IANA: - * http://www.iana.org/numbers.html - */ -#define SNMP_DEVICE_ENTERPRISE_OID {1, 3, 6, 1, 4, 1, SNMP_LWIP_ENTERPRISE_OID} -/** - * Length of SNMP_DEVICE_ENTERPRISE_OID - */ -#define SNMP_DEVICE_ENTERPRISE_OID_LEN 7 -#endif - -/** - * SNMP_DEBUG: Enable debugging for SNMP messages. - */ -#if !defined SNMP_DEBUG || defined __DOXYGEN__ -#define SNMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. - */ -#if !defined SNMP_MIB_DEBUG || defined __DOXYGEN__ -#define SNMP_MIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * Indicates if the MIB2 implementation of LWIP SNMP stack is used. - */ -#if !defined SNMP_LWIP_MIB2 || defined __DOXYGEN__ -#define SNMP_LWIP_MIB2 LWIP_SNMP -#endif - -/** - * Value return for sysDesc field of MIB2. - */ -#if !defined SNMP_LWIP_MIB2_SYSDESC || defined __DOXYGEN__ -#define SNMP_LWIP_MIB2_SYSDESC "lwIP" -#endif - -/** - * Value return for sysName field of MIB2. - * To make sysName field settable, call snmp_mib2_set_sysname() to provide the necessary buffers. - */ -#if !defined SNMP_LWIP_MIB2_SYSNAME || defined __DOXYGEN__ -#define SNMP_LWIP_MIB2_SYSNAME "FQDN-unk" -#endif - -/** - * Value return for sysContact field of MIB2. - * To make sysContact field settable, call snmp_mib2_set_syscontact() to provide the necessary buffers. - */ -#if !defined SNMP_LWIP_MIB2_SYSCONTACT || defined __DOXYGEN__ -#define SNMP_LWIP_MIB2_SYSCONTACT "" -#endif - -/** - * Value return for sysLocation field of MIB2. - * To make sysLocation field settable, call snmp_mib2_set_syslocation() to provide the necessary buffers. - */ -#if !defined SNMP_LWIP_MIB2_SYSLOCATION || defined __DOXYGEN__ -#define SNMP_LWIP_MIB2_SYSLOCATION "" -#endif - -/** - * This value is used to limit the repetitions processed in GetBulk requests (value == 0 means no limitation). - * This may be useful to limit the load for a single request. - * According to SNMP RFC 1905 it is allowed to not return all requested variables from a GetBulk request if system load would be too high. - * so the effect is that the client will do more requests to gather all data. - * For the stack this could be useful in case that SNMP processing is done in TCP/IP thread. In this situation a request with many - * repetitions could block the thread for a longer time. Setting limit here will keep the stack more responsive. - */ -#if !defined SNMP_LWIP_GETBULK_MAX_REPETITIONS || defined __DOXYGEN__ -#define SNMP_LWIP_GETBULK_MAX_REPETITIONS 0 -#endif - -/** - * @} - */ - -/* - ------------------------------------ - ---------- SNMPv3 options ---------- - ------------------------------------ -*/ - -/** - * LWIP_SNMP_V3==1: This enables EXPERIMENTAL SNMPv3 support. LWIP_SNMP must - * also be enabled. - * THIS IS UNDER DEVELOPMENT AND SHOULD NOT BE ENABLED IN PRODUCTS. - */ -#ifndef LWIP_SNMP_V3 -#define LWIP_SNMP_V3 0 -#endif - -#ifndef LWIP_SNMP_V3_CRYPTO -#define LWIP_SNMP_V3_CRYPTO LWIP_SNMP_V3 -#endif - -#ifndef LWIP_SNMP_V3_MBEDTLS -#define LWIP_SNMP_V3_MBEDTLS LWIP_SNMP_V3 -#endif - -#endif /* LWIP_HDR_SNMP_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_scalar.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_scalar.h deleted file mode 100644 index 40a060c640483ac0bdf2063f84076a866c333e0b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_scalar.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file - * SNMP server MIB API to implement scalar nodes - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#ifndef LWIP_HDR_APPS_SNMP_SCALAR_H -#define LWIP_HDR_APPS_SNMP_SCALAR_H - -#include "lwip/apps/snmp_opts.h" -#include "lwip/apps/snmp_core.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -/** basic scalar node */ -struct snmp_scalar_node -{ - /** inherited "base class" members */ - struct snmp_leaf_node node; - u8_t asn1_type; - snmp_access_t access; - node_instance_get_value_method get_value; - node_instance_set_test_method set_test; - node_instance_set_value_method set_value; -}; - - -snmp_err_t snmp_scalar_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -snmp_err_t snmp_scalar_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - -#define SNMP_SCALAR_CREATE_NODE(oid, access, asn1_type, get_value_method, set_test_method, set_value_method) \ - {{{ SNMP_NODE_SCALAR, (oid) }, \ - snmp_scalar_get_instance, \ - snmp_scalar_get_next_instance }, \ - (asn1_type), (access), (get_value_method), (set_test_method), (set_value_method) } - -#define SNMP_SCALAR_CREATE_NODE_READONLY(oid, asn1_type, get_value_method) SNMP_SCALAR_CREATE_NODE(oid, SNMP_NODE_INSTANCE_READ_ONLY, asn1_type, get_value_method, NULL, NULL) - -/** scalar array node - a tree node which contains scalars only as children */ -struct snmp_scalar_array_node_def -{ - u32_t oid; - u8_t asn1_type; - snmp_access_t access; -}; - -typedef s16_t (*snmp_scalar_array_get_value_method)(const struct snmp_scalar_array_node_def*, void*); -typedef snmp_err_t (*snmp_scalar_array_set_test_method)(const struct snmp_scalar_array_node_def*, u16_t, void*); -typedef snmp_err_t (*snmp_scalar_array_set_value_method)(const struct snmp_scalar_array_node_def*, u16_t, void*); - -/** basic scalar array node */ -struct snmp_scalar_array_node -{ - /** inherited "base class" members */ - struct snmp_leaf_node node; - u16_t array_node_count; - const struct snmp_scalar_array_node_def* array_nodes; - snmp_scalar_array_get_value_method get_value; - snmp_scalar_array_set_test_method set_test; - snmp_scalar_array_set_value_method set_value; -}; - -snmp_err_t snmp_scalar_array_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -snmp_err_t snmp_scalar_array_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - -#define SNMP_SCALAR_CREATE_ARRAY_NODE(oid, array_nodes, get_value_method, set_test_method, set_value_method) \ - {{{ SNMP_NODE_SCALAR_ARRAY, (oid) }, \ - snmp_scalar_array_get_instance, \ - snmp_scalar_array_get_next_instance }, \ - (u16_t)LWIP_ARRAYSIZE(array_nodes), (array_nodes), (get_value_method), (set_test_method), (set_value_method) } - -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNMP_SCALAR_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_table.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_table.h deleted file mode 100644 index 4988b51c2502ea7cf2212f22c8970b08959776cb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_table.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * @file - * SNMP server MIB API to implement table nodes - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Martin Hentschel - * - */ - -#ifndef LWIP_HDR_APPS_SNMP_TABLE_H -#define LWIP_HDR_APPS_SNMP_TABLE_H - -#include "lwip/apps/snmp_opts.h" -#include "lwip/apps/snmp_core.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -/** default (customizable) read/write table */ -struct snmp_table_col_def -{ - u32_t index; - u8_t asn1_type; - snmp_access_t access; -}; - -/** table node */ -struct snmp_table_node -{ - /** inherited "base class" members */ - struct snmp_leaf_node node; - u16_t column_count; - const struct snmp_table_col_def* columns; - snmp_err_t (*get_cell_instance)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, struct snmp_node_instance* cell_instance); - snmp_err_t (*get_next_cell_instance)(const u32_t* column, struct snmp_obj_id* row_oid, struct snmp_node_instance* cell_instance); - /** returns object value for the given object identifier */ - node_instance_get_value_method get_value; - /** tests length and/or range BEFORE setting */ - node_instance_set_test_method set_test; - /** sets object value, only called when set_test() was successful */ - node_instance_set_value_method set_value; -}; - -snmp_err_t snmp_table_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -snmp_err_t snmp_table_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - -#define SNMP_TABLE_CREATE(oid, columns, get_cell_instance_method, get_next_cell_instance_method, get_value_method, set_test_method, set_value_method) \ - {{{ SNMP_NODE_TABLE, (oid) }, \ - snmp_table_get_instance, \ - snmp_table_get_next_instance }, \ - (u16_t)LWIP_ARRAYSIZE(columns), (columns), \ - (get_cell_instance_method), (get_next_cell_instance_method), \ - (get_value_method), (set_test_method), (set_value_method)} - -#define SNMP_TABLE_GET_COLUMN_FROM_OID(oid) ((oid)[1]) /* first array value is (fixed) row entry (fixed to 1) and 2nd value is column, follow3ed by instance */ - - -/** simple read-only table */ -typedef enum { - SNMP_VARIANT_VALUE_TYPE_U32, - SNMP_VARIANT_VALUE_TYPE_S32, - SNMP_VARIANT_VALUE_TYPE_PTR, - SNMP_VARIANT_VALUE_TYPE_CONST_PTR -} snmp_table_column_data_type_t; - -struct snmp_table_simple_col_def -{ - u32_t index; - u8_t asn1_type; - snmp_table_column_data_type_t data_type; /* depending of what union member is used to store the value*/ -}; - -/** simple read-only table node */ -struct snmp_table_simple_node -{ - /* inherited "base class" members */ - struct snmp_leaf_node node; - u16_t column_count; - const struct snmp_table_simple_col_def* columns; - snmp_err_t (*get_cell_value)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len); - snmp_err_t (*get_next_cell_instance_and_value)(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len); -}; - -snmp_err_t snmp_table_simple_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -snmp_err_t snmp_table_simple_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - -#define SNMP_TABLE_CREATE_SIMPLE(oid, columns, get_cell_value_method, get_next_cell_instance_and_value_method) \ - {{{ SNMP_NODE_TABLE, (oid) }, \ - snmp_table_simple_get_instance, \ - snmp_table_simple_get_next_instance }, \ - (u16_t)LWIP_ARRAYSIZE(columns), (columns), (get_cell_value_method), (get_next_cell_instance_and_value_method) } - -s16_t snmp_table_extract_value_from_s32ref(struct snmp_node_instance* instance, void* value); -s16_t snmp_table_extract_value_from_u32ref(struct snmp_node_instance* instance, void* value); -s16_t snmp_table_extract_value_from_refconstptr(struct snmp_node_instance* instance, void* value); - -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNMP_TABLE_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_threadsync.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_threadsync.h deleted file mode 100644 index a25dbf2d0f05cea9d70b109a3a2c3ff0f690f00f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmp_threadsync.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * @file - * SNMP server MIB API to implement thread synchronization - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Dirk Ziegelmeier - * - */ - -#ifndef LWIP_HDR_APPS_SNMP_THREADSYNC_H -#define LWIP_HDR_APPS_SNMP_THREADSYNC_H - -#include "lwip/apps/snmp_opts.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/apps/snmp_core.h" -#include "lwip/sys.h" - -typedef void (*snmp_threadsync_called_fn)(void* arg); -typedef void (*snmp_threadsync_synchronizer_fn)(snmp_threadsync_called_fn fn, void* arg); - - -/** Thread sync runtime data. For internal usage only. */ -struct threadsync_data -{ - union { - snmp_err_t err; - s16_t s16; - } retval; - union { - const u32_t *root_oid; - void *value; - } arg1; - union { - u8_t root_oid_len; - u16_t len; - } arg2; - const struct snmp_threadsync_node *threadsync_node; - struct snmp_node_instance proxy_instance; -}; - -/** Thread sync instance. Needed EXCATLY once for every thread to be synced into. */ -struct snmp_threadsync_instance -{ - sys_sem_t sem; - sys_mutex_t sem_usage_mutex; - snmp_threadsync_synchronizer_fn sync_fn; - struct threadsync_data data; -}; - -/** SNMP thread sync proxy leaf node */ -struct snmp_threadsync_node -{ - /* inherited "base class" members */ - struct snmp_leaf_node node; - - const struct snmp_leaf_node *target; - struct snmp_threadsync_instance *instance; -}; - -snmp_err_t snmp_threadsync_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); -snmp_err_t snmp_threadsync_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); - -/** Create thread sync proxy node */ -#define SNMP_CREATE_THREAD_SYNC_NODE(oid, target_leaf_node, threadsync_instance) \ - {{{ SNMP_NODE_THREADSYNC, (oid) }, \ - snmp_threadsync_get_instance, \ - snmp_threadsync_get_next_instance }, \ - (target_leaf_node), \ - (threadsync_instance) } - -/** Create thread sync instance data */ -void snmp_threadsync_init(struct snmp_threadsync_instance *instance, snmp_threadsync_synchronizer_fn sync_fn); - -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNMP_THREADSYNC_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmpv3.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmpv3.h deleted file mode 100644 index c99fed4e101aa5a1ec3445410469cca6e8e105a0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/snmpv3.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * @file - * Additional SNMPv3 functionality RFC3414 and RFC3826. - */ - -/* - * Copyright (c) 2016 Elias Oenal. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Elias Oenal - */ - -#ifndef LWIP_HDR_APPS_SNMP_V3_H -#define LWIP_HDR_APPS_SNMP_V3_H - -#include "lwip/apps/snmp_opts.h" -#include "lwip/err.h" - -#if LWIP_SNMP && LWIP_SNMP_V3 - -#define SNMP_V3_AUTH_ALGO_INVAL 0 -#define SNMP_V3_AUTH_ALGO_MD5 1 -#define SNMP_V3_AUTH_ALGO_SHA 2 - -#define SNMP_V3_PRIV_ALGO_INVAL 0 -#define SNMP_V3_PRIV_ALGO_DES 1 -#define SNMP_V3_PRIV_ALGO_AES 2 - -#define SNMP_V3_PRIV_MODE_DECRYPT 0 -#define SNMP_V3_PRIV_MODE_ENCRYPT 1 - -/* - * The following callback functions must be implemented by the application. - * There is a dummy implementation in snmpv3_dummy.c. - */ - -void snmpv3_get_engine_id(const char **id, u8_t *len); -err_t snmpv3_set_engine_id(const char* id, u8_t len); - -u32_t snmpv3_get_engine_boots(void); -void snmpv3_set_engine_boots(u32_t boots); - -u32_t snmpv3_get_engine_time(void); -void snmpv3_reset_engine_time(void); - -err_t snmpv3_get_user(const char* username, u8_t *auth_algo, u8_t *auth_key, u8_t *priv_algo, u8_t *priv_key); - -/* The following functions are provided by the SNMPv3 agent */ - -void snmpv3_engine_id_changed(void); - -void snmpv3_password_to_key_md5( - const u8_t *password, /* IN */ - u8_t passwordlen, /* IN */ - const u8_t *engineID, /* IN - pointer to snmpEngineID */ - u8_t engineLength, /* IN - length of snmpEngineID */ - u8_t *key); /* OUT - pointer to caller 16-octet buffer */ - -void snmpv3_password_to_key_sha( - const u8_t *password, /* IN */ - u8_t passwordlen, /* IN */ - const u8_t *engineID, /* IN - pointer to snmpEngineID */ - u8_t engineLength, /* IN - length of snmpEngineID */ - u8_t *key); /* OUT - pointer to caller 20-octet buffer */ - -#endif - -#endif /* LWIP_HDR_APPS_SNMP_V3_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp.h deleted file mode 100644 index 40df9cc590fc95698f122435d97b0a2fff05260c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * @file - * SNTP client API - */ - -/* - * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Frédéric Bernon, Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_APPS_SNTP_H -#define LWIP_HDR_APPS_SNTP_H - -#include "lwip/apps/sntp_opts.h" -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* SNTP operating modes: default is to poll using unicast. - The mode has to be set before calling sntp_init(). */ -#define SNTP_OPMODE_POLL 0 -#define SNTP_OPMODE_LISTENONLY 1 -void sntp_setoperatingmode(u8_t operating_mode); -u8_t sntp_getoperatingmode(void); - -void sntp_init(void); -void sntp_stop(void); -u8_t sntp_enabled(void); - -void sntp_setserver(u8_t idx, const ip_addr_t *addr); -const ip_addr_t* sntp_getserver(u8_t idx); - -#if SNTP_SERVER_DNS -void sntp_setservername(u8_t idx, char *server); -char *sntp_getservername(u8_t idx); -#endif /* SNTP_SERVER_DNS */ - -#if SNTP_GET_SERVERS_FROM_DHCP -void sntp_servermode_dhcp(int set_servers_from_dhcp); -#else /* SNTP_GET_SERVERS_FROM_DHCP */ -#define sntp_servermode_dhcp(x) -#endif /* SNTP_GET_SERVERS_FROM_DHCP */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_SNTP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp_opts.h deleted file mode 100644 index f3651f90e6d0406ce07ba52e163fabf69658571f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/sntp_opts.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * @file - * SNTP client options list - */ - -/* - * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Frédéric Bernon, Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_APPS_SNTP_OPTS_H -#define LWIP_HDR_APPS_SNTP_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup sntp_opts Options - * @ingroup sntp - * @{ - */ - -/** SNTP macro to change system time in seconds - * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds instead of this one - * if you need the additional precision. - */ -#if !defined SNTP_SET_SYSTEM_TIME || defined __DOXYGEN__ -#define SNTP_SET_SYSTEM_TIME(sec) LWIP_UNUSED_ARG(sec) -#endif - -/** The maximum number of SNTP servers that can be set */ -#if !defined SNTP_MAX_SERVERS || defined __DOXYGEN__ -#define SNTP_MAX_SERVERS LWIP_DHCP_MAX_NTP_SERVERS -#endif - -/** Set this to 1 to implement the callback function called by dhcp when - * NTP servers are received. */ -#if !defined SNTP_GET_SERVERS_FROM_DHCP || defined __DOXYGEN__ -#define SNTP_GET_SERVERS_FROM_DHCP LWIP_DHCP_GET_NTP_SRV -#endif - -/** Set this to 1 to support DNS names (or IP address strings) to set sntp servers - * One server address/name can be defined as default if SNTP_SERVER_DNS == 1: - * \#define SNTP_SERVER_ADDRESS "pool.ntp.org" - */ -#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__ -#define SNTP_SERVER_DNS 0 -#endif - -/** - * SNTP_DEBUG: Enable debugging for SNTP. - */ -#if !defined SNTP_DEBUG || defined __DOXYGEN__ -#define SNTP_DEBUG LWIP_DBG_OFF -#endif - -/** SNTP server port */ -#if !defined SNTP_PORT || defined __DOXYGEN__ -#define SNTP_PORT 123 -#endif - -/** Set this to 1 to allow config of SNTP server(s) by DNS name */ -#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__ -#define SNTP_SERVER_DNS 0 -#endif - -/** Sanity check: - * Define this to - * - 0 to turn off sanity checks (default; smaller code) - * - >= 1 to check address and port of the response packet to ensure the - * response comes from the server we sent the request to. - * - >= 2 to check returned Originate Timestamp against Transmit Timestamp - * sent to the server (to ensure response to older request). - * - >= 3 @todo: discard reply if any of the LI, Stratum, or Transmit Timestamp - * fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast). - * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each - * greater than or equal to 0 and less than infinity, where infinity is - * currently a cozy number like one second. This check avoids using a - * server whose synchronization source has expired for a very long time. - */ -#if !defined SNTP_CHECK_RESPONSE || defined __DOXYGEN__ -#define SNTP_CHECK_RESPONSE 0 -#endif - -/** According to the RFC, this shall be a random delay - * between 1 and 5 minutes (in milliseconds) to prevent load peaks. - * This can be defined to a random generation function, - * which must return the delay in milliseconds as u32_t. - * Turned off by default. - */ -#if !defined SNTP_STARTUP_DELAY || defined __DOXYGEN__ -#define SNTP_STARTUP_DELAY 0 -#endif - -/** If you want the startup delay to be a function, define this - * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1. - */ -#if !defined SNTP_STARTUP_DELAY_FUNC || defined __DOXYGEN__ -#define SNTP_STARTUP_DELAY_FUNC SNTP_STARTUP_DELAY -#endif - -/** SNTP receive timeout - in milliseconds - * Also used as retry timeout - this shouldn't be too low. - * Default is 3 seconds. - */ -#if !defined SNTP_RECV_TIMEOUT || defined __DOXYGEN__ -#define SNTP_RECV_TIMEOUT 3000 -#endif - -/** SNTP update delay - in milliseconds - * Default is 1 hour. Must not be beolw 15 seconds by specification (i.e. 15000) - */ -#if !defined SNTP_UPDATE_DELAY || defined __DOXYGEN__ -#define SNTP_UPDATE_DELAY 3600000 -#endif - -/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2 - * to send in request and compare in response. - */ -#if !defined SNTP_GET_SYSTEM_TIME || defined __DOXYGEN__ -#define SNTP_GET_SYSTEM_TIME(sec, us) do { (sec) = 0; (us) = 0; } while(0) -#endif - -/** Default retry timeout (in milliseconds) if the response - * received is invalid. - * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached. - */ -#if !defined SNTP_RETRY_TIMEOUT || defined __DOXYGEN__ -#define SNTP_RETRY_TIMEOUT SNTP_RECV_TIMEOUT -#endif - -/** Maximum retry timeout (in milliseconds). */ -#if !defined SNTP_RETRY_TIMEOUT_MAX || defined __DOXYGEN__ -#define SNTP_RETRY_TIMEOUT_MAX (SNTP_RETRY_TIMEOUT * 10) -#endif - -/** Increase retry timeout with every retry sent - * Default is on to conform to RFC. - */ -#if !defined SNTP_RETRY_TIMEOUT_EXP || defined __DOXYGEN__ -#define SNTP_RETRY_TIMEOUT_EXP 1 -#endif - -/** - * @} - */ - -#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_opts.h deleted file mode 100644 index 6968a803b439feb20e8df8350790843821022dd4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_opts.h +++ /dev/null @@ -1,105 +0,0 @@ -/****************************************************************//** - * - * @file tftp_opts.h - * - * @author Logan Gunthorpe - * - * @brief Trivial File Transfer Protocol (RFC 1350) implementation options - * - * Copyright (c) Deltatee Enterprises Ltd. 2013 - * All rights reserved. - * - ********************************************************************/ - -/* - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Logan Gunthorpe - * - */ - -#ifndef LWIP_HDR_APPS_TFTP_OPTS_H -#define LWIP_HDR_APPS_TFTP_OPTS_H - -#include "lwip/opt.h" - -/** - * @defgroup tftp_opts Options - * @ingroup tftp - * @{ - */ - -/** - * Enable TFTP debug messages - */ -#if !defined TFTP_DEBUG || defined __DOXYGEN__ -#define TFTP_DEBUG LWIP_DBG_ON -#endif - -/** - * TFTP server port - */ -#if !defined TFTP_PORT || defined __DOXYGEN__ -#define TFTP_PORT 69 -#endif - -/** - * TFTP timeout - */ -#if !defined TFTP_TIMEOUT_MSECS || defined __DOXYGEN__ -#define TFTP_TIMEOUT_MSECS 10000 -#endif - -/** - * Max. number of retries when a file is read from server - */ -#if !defined TFTP_MAX_RETRIES || defined __DOXYGEN__ -#define TFTP_MAX_RETRIES 5 -#endif - -/** - * TFTP timer cyclic interval - */ -#if !defined TFTP_TIMER_MSECS || defined __DOXYGEN__ -#define TFTP_TIMER_MSECS 50 -#endif - -/** - * Max. length of TFTP filename - */ -#if !defined TFTP_MAX_FILENAME_LEN || defined __DOXYGEN__ -#define TFTP_MAX_FILENAME_LEN 20 -#endif - -/** - * Max. length of TFTP mode - */ -#if !defined TFTP_MAX_MODE_LEN || defined __DOXYGEN__ -#define TFTP_MAX_MODE_LEN 7 -#endif - -/** - * @} - */ - -#endif /* LWIP_HDR_APPS_TFTP_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_server.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_server.h deleted file mode 100644 index 3fbe701e0a23dca09f9a57f5ccd1feb54789b071..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/apps/tftp_server.h +++ /dev/null @@ -1,94 +0,0 @@ -/****************************************************************//** - * - * @file tftp_server.h - * - * @author Logan Gunthorpe - * - * @brief Trivial File Transfer Protocol (RFC 1350) - * - * Copyright (c) Deltatee Enterprises Ltd. 2013 - * All rights reserved. - * - ********************************************************************/ - -/* - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Logan Gunthorpe - * - */ - -#ifndef LWIP_HDR_APPS_TFTP_SERVER_H -#define LWIP_HDR_APPS_TFTP_SERVER_H - -#include "lwip/apps/tftp_opts.h" -#include "lwip/err.h" -#include "lwip/pbuf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @ingroup tftp - * TFTP context containing callback functions for TFTP transfers - */ -struct tftp_context { - /** - * Open file for read/write. - * @param fname Filename - * @param mode Mode string from TFTP RFC 1350 (netascii, octet, mail) - * @param write Flag indicating read (0) or write (!= 0) access - * @returns File handle supplied to other functions - */ - void* (*open)(const char* fname, const char* mode, u8_t write); - /** - * Close file handle - * @param handle File handle returned by open() - */ - void (*close)(void* handle); - /** - * Read from file - * @param handle File handle returned by open() - * @param buf Target buffer to copy read data to - * @param bytes Number of bytes to copy to buf - * @returns >= 0: Success; < 0: Error - */ - int (*read)(void* handle, void* buf, int bytes); - /** - * Write to file - * @param handle File handle returned by open() - * @param pbuf PBUF adjusted such that payload pointer points - * to the beginning of write data. In other words, - * TFTP headers are stripped off. - * @returns >= 0: Success; < 0: Error - */ - int (*write)(void* handle, struct pbuf* p); -}; - -err_t tftp_init(const struct tftp_context* ctx); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_APPS_TFTP_SERVER_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/arch.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/arch.h deleted file mode 100644 index 4e5e37d6617fb4e96b7b3e5f174df1e55e56bc7b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/arch.h +++ /dev/null @@ -1,320 +0,0 @@ -/** - * @file - * Support for different processor and compiler architectures - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_ARCH_H -#define LWIP_HDR_ARCH_H - -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 1234 -#endif - -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 4321 -#endif - -#include "arch/cc.h" -#include - -/** - * @defgroup compiler_abstraction Compiler/platform abstraction - * @ingroup sys_layer - * All defines related to this section must not be placed in lwipopts.h, - * but in arch/cc.h! - * These options cannot be \#defined in lwipopts.h since they are not options - * of lwIP itself, but options of the lwIP port to your system. - * @{ - */ - -/** Define the byte order of the system. - * Needed for conversion of network data to host byte order. - * Allowed values: LITTLE_ENDIAN and BIG_ENDIAN - */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif - -/** Define random number generator function of your system */ -#ifdef __DOXYGEN__ -#define LWIP_RAND() ((u32_t)rand()) -#endif - -/** Platform specific diagnostic output.\n - * Note the default implementation pulls in printf, which may - * in turn pull in a lot of standard libary code. In resource-constrained - * systems, this should be defined to something less resource-consuming. - */ -#ifndef LWIP_PLATFORM_DIAG -#define LWIP_PLATFORM_DIAG(x) do {fatal_prf x;} while(0) -#include -#include -#endif - -/** Platform specific assertion handling.\n - * Note the default implementation pulls in printf, fflush and abort, which may - * in turn pull in a lot of standard libary code. In resource-constrained - * systems, this should be defined to something less resource-consuming. - */ -#ifndef LWIP_PLATFORM_ASSERT -#define LWIP_PLATFORM_ASSERT(x) do {os_printf("Assertion \"%s\" failed at line %d in %s\n", \ - x, __LINE__, __FILE__); fflush(NULL); abort();} while(0) -#include -#include -#endif - -/** Define this to 1 in arch/cc.h of your port if you do not want to - * include stddef.h header to get size_t. You need to typedef size_t - * by yourself in this case. - */ -#ifndef LWIP_NO_STDDEF_H -#define LWIP_NO_STDDEF_H 0 -#endif - -#if !LWIP_NO_STDDEF_H -#include /* for size_t */ -#endif - -/** Define this to 1 in arch/cc.h of your port if your compiler does not provide - * the stdint.h header. You need to typedef the generic types listed in - * lwip/arch.h yourself in this case (u8_t, u16_t...). - */ -#ifndef LWIP_NO_STDINT_H -#define LWIP_NO_STDINT_H 0 -#endif - -/* Define generic types used in lwIP */ -#if !LWIP_NO_STDINT_H -#include -typedef uint8_t u8_t; -typedef int8_t s8_t; -typedef uint16_t u16_t; -typedef int16_t s16_t; -typedef uint32_t u32_t; -typedef int32_t s32_t; -typedef uintptr_t mem_ptr_t; -#endif - -/** Define this to 1 in arch/cc.h of your port if your compiler does not provide - * the inttypes.h header. You need to define the format strings listed in - * lwip/arch.h yourself in this case (X8_F, U16_F...). - */ -#ifndef LWIP_NO_INTTYPES_H -#define LWIP_NO_INTTYPES_H 0 -#endif - -/* Define (sn)printf formatters for these lwIP types */ -#if !LWIP_NO_INTTYPES_H -#include -#ifndef X8_F -#define X8_F "02" PRIx8 -#endif -#ifndef U16_F -#define U16_F PRIu16 -#endif -#ifndef S16_F -#define S16_F PRId16 -#endif -#ifndef X16_F -#define X16_F PRIx16 -#endif -#ifndef U32_F -#define U32_F PRIu32 -#endif -#ifndef S32_F -#define S32_F PRId32 -#endif -#ifndef X32_F -#define X32_F PRIx32 -#endif -#ifndef SZT_F -#define SZT_F PRIuPTR -#endif -#endif - -/** Define this to 1 in arch/cc.h of your port if your compiler does not provide - * the limits.h header. You need to define the type limits yourself in this case - * (e.g. INT_MAX). - */ -#ifndef LWIP_NO_LIMITS_H -#define LWIP_NO_LIMITS_H 0 -#endif - -/* Include limits.h? */ -#if !LWIP_NO_LIMITS_H -#include -#endif - -/** C++ const_cast(val) equivalent to remove constness from a value (GCC -Wcast-qual) */ -#ifndef LWIP_CONST_CAST -#define LWIP_CONST_CAST(target_type, val) ((target_type)((ptrdiff_t)val)) -#endif - -/** Get rid of alignment cast warnings (GCC -Wcast-align) */ -#ifndef LWIP_ALIGNMENT_CAST -#define LWIP_ALIGNMENT_CAST(target_type, val) LWIP_CONST_CAST(target_type, val) -#endif - -/** Get rid of warnings related to pointer-to-numeric and vice-versa casts, - * e.g. "conversion from 'u8_t' to 'void *' of greater size" - */ -#ifndef LWIP_PTR_NUMERIC_CAST -#define LWIP_PTR_NUMERIC_CAST(target_type, val) LWIP_CONST_CAST(target_type, val) -#endif - -/** Allocates a memory buffer of specified size that is of sufficient size to align - * its start address using LWIP_MEM_ALIGN. - * You can declare your own version here e.g. to enforce alignment without adding - * trailing padding bytes (see LWIP_MEM_ALIGN_BUFFER) or your own section placement - * requirements.\n - * e.g. if you use gcc and need 32 bit alignment:\n - * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[size] \_\_attribute\_\_((aligned(4)))\n - * or more portable:\n - * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u32_t variable_name[(size + sizeof(u32_t) - 1) / sizeof(u32_t)] - */ -#ifndef LWIP_DECLARE_MEMORY_ALIGNED -#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[LWIP_MEM_ALIGN_BUFFER(size)] -#endif - -/** Calculate memory size for an aligned buffer - returns the next highest - * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and - * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4). - */ -#ifndef LWIP_MEM_ALIGN_SIZE -#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U)) -#endif - -/** Calculate safe memory size for an aligned buffer when using an unaligned - * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the - * start (e.g. if buffer is u8_t[] and actual data will be u32_t*) - */ -#ifndef LWIP_MEM_ALIGN_BUFFER -#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U)) -#endif - -/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT - * so that ADDR % MEM_ALIGNMENT == 0 - */ -#ifndef LWIP_MEM_ALIGN -#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** Packed structs support. - * Placed BEFORE declaration of a packed struct.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_BEGIN -#define PACK_STRUCT_BEGIN -#endif /* PACK_STRUCT_BEGIN */ - -/** Packed structs support. - * Placed AFTER declaration of a packed struct.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_END -#define PACK_STRUCT_END -#endif /* PACK_STRUCT_END */ - -/** Packed structs support. - * Placed between end of declaration of a packed struct and trailing semicolon.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_STRUCT -#if defined(__GNUC__) || defined(__clang__) -#define PACK_STRUCT_STRUCT __attribute__((packed)) -#else -#define PACK_STRUCT_STRUCT -#endif -#endif /* PACK_STRUCT_STRUCT */ - -/** Packed structs support. - * Wraps u32_t and u16_t members.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_FIELD -#define PACK_STRUCT_FIELD(x) x -#endif /* PACK_STRUCT_FIELD */ - -/** Packed structs support. - * Wraps u8_t members, where some compilers warn that packing is not necessary.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_FLD_8 -#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x) -#endif /* PACK_STRUCT_FLD_8 */ - -/** Packed structs support. - * Wraps members that are packed structs themselves, where some compilers warn that packing is not necessary.\n - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifndef PACK_STRUCT_FLD_S -#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x) -#endif /* PACK_STRUCT_FLD_S */ - -/** Packed structs support using \#include files before and after struct to be packed.\n - * The file included BEFORE the struct is "arch/bpstruct.h".\n - * The file included AFTER the struct is "arch/epstruct.h".\n - * This can be used to implement struct packing on MS Visual C compilers, see - * the Win32 port in the lwIP contrib repository for reference. - * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n - * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. - */ -#ifdef __DOXYGEN__ -#define PACK_STRUCT_USE_INCLUDES -#endif - -/** Eliminates compiler warning about unused arguments (GCC -Wextra -Wunused). */ -#ifndef LWIP_UNUSED_ARG -#define LWIP_UNUSED_ARG(x) (void)x -#endif /* LWIP_UNUSED_ARG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_ARCH_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/debug.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/debug.h deleted file mode 100644 index a142f1cff3c9aa06318e092eb265e2a8c69e8daa..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/debug.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - * @file - * Debug messages infrastructure - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_DEBUG_H -#define LWIP_HDR_DEBUG_H - -#include "lwip/arch.h" -#include "lwip/opt.h" - -/** - * @defgroup debugging_levels LWIP_DBG_MIN_LEVEL and LWIP_DBG_TYPES_ON values - * @ingroup lwip_opts_debugmsg - * @{ - */ - -/** @name Debug level (LWIP_DBG_MIN_LEVEL) - * @{ - */ -/** Debug level: ALL messages*/ -#define LWIP_DBG_LEVEL_ALL 0x00 -/** Debug level: Warnings. bad checksums, dropped packets, ... */ -#define LWIP_DBG_LEVEL_WARNING 0x01 -/** Debug level: Serious. memory allocation failures, ... */ -#define LWIP_DBG_LEVEL_SERIOUS 0x02 -/** Debug level: Severe */ -#define LWIP_DBG_LEVEL_SEVERE 0x03 -/** - * @} - */ - -#define LWIP_DBG_MASK_LEVEL 0x03 -/* compatibility define only */ -#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL - -/** @name Enable/disable debug messages completely (LWIP_DBG_TYPES_ON) - * @{ - */ -/** flag for LWIP_DEBUGF to enable that debug message */ -#define LWIP_DBG_ON 0x80U -/** flag for LWIP_DEBUGF to disable that debug message */ -#define LWIP_DBG_OFF 0x00U -/** - * @} - */ - -/** @name Debug message types (LWIP_DBG_TYPES_ON) - * @{ - */ -/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ -#define LWIP_DBG_TRACE 0x40U -/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ -#define LWIP_DBG_STATE 0x20U -/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ -#define LWIP_DBG_FRESH 0x10U -/** flag for LWIP_DEBUGF to halt after printing this debug message */ -#define LWIP_DBG_HALT 0x08U -/** - * @} - */ - -/** - * @} - */ - -/** - * @defgroup lwip_assertions Assertion handling - * @ingroup lwip_opts_debug - * @{ - */ -/** - * LWIP_NOASSERT: Disable LWIP_ASSERT checks: - * To disable assertions define LWIP_NOASSERT in arch/cc.h. - */ -#ifdef __DOXYGEN__ -#define LWIP_NOASSERT -#undef LWIP_NOASSERT -#endif -/** - * @} - */ - -#ifndef LWIP_NOASSERT -#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \ - LWIP_PLATFORM_ASSERT(message); }} while(0) -#ifndef LWIP_PLATFORM_ASSERT -#error "If you want to use LWIP_ASSERT, LWIP_PLATFORM_ASSERT(message) needs to be defined in your arch/cc.h" -#endif -#else /* LWIP_NOASSERT */ -#define LWIP_ASSERT(message, assertion) -#endif /* LWIP_NOASSERT */ - -#ifndef LWIP_ERROR -#ifndef LWIP_NOASSERT -#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message) -#elif defined LWIP_DEBUG -#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message)) -#else -#define LWIP_PLATFORM_ERROR(message) -#endif - -/* if "expression" isn't true, then print "message" and execute "handler" expression */ -#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ - LWIP_PLATFORM_ERROR(message); handler;}} while(0) -#endif /* LWIP_ERROR */ - -/** Enable debug message printing, but only if debug message type is enabled - * AND is of correct type AND is at least LWIP_DBG_LEVEL. - */ -#ifdef __DOXYGEN__ -#define LWIP_DEBUG -#undef LWIP_DEBUG -#endif - -#ifdef LWIP_DEBUG -#ifndef LWIP_PLATFORM_DIAG -#error "If you want to use LWIP_DEBUG, LWIP_PLATFORM_DIAG(message) needs to be defined in your arch/cc.h" -#endif -#define LWIP_DEBUGF(debug, message) do { \ - if ( \ - ((debug) & LWIP_DBG_ON) && \ - ((debug) & LWIP_DBG_TYPES_ON) && \ - ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ - LWIP_PLATFORM_DIAG(message); \ - if ((debug) & LWIP_DBG_HALT) { \ - while(1); \ - } \ - } \ - } while(0) - -#else /* LWIP_DEBUG */ -#define LWIP_DEBUGF(debug, message) -#endif /* LWIP_DEBUG */ - -#endif /* LWIP_HDR_DEBUG_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/def.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/def.h deleted file mode 100644 index 01f462af28b729d5162ed197563304fea0b13d3a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/def.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * @file - * various utility macros - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_DEF_H -#define LWIP_HDR_DEF_H - -/* arch.h might define NULL already */ -#include "lwip/arch.h" -#include "lwip/opt.h" -#include "generic.h" - -#if LWIP_PERF -#include "arch/perf.h" -#else /* LWIP_PERF */ -#define PERF_START /* null definition */ -#define PERF_STOP(x) /* null definition */ -#endif /* LWIP_PERF */ - -#ifdef __cplusplus -extern "C" { -#endif - -#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) -#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) - -/* Get the number of entries in an array ('x' must NOT be a pointer!) */ -#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0])) - -/** Create u32_t value from bytes */ -#define LWIP_MAKEU32(a,b,c,d) (((u32_t)((a) & 0xff) << 24) | \ - ((u32_t)((b) & 0xff) << 16) | \ - ((u32_t)((c) & 0xff) << 8) | \ - (u32_t)((d) & 0xff)) - -#ifndef NULL -#ifdef __cplusplus -#define NULL 0 -#else -#define NULL ((void *)0) -#endif -#endif - -#if BYTE_ORDER == BIG_ENDIAN -#define lwip_htons(x) (x) -#define lwip_ntohs(x) (x) -#define lwip_htonl(x) (x) -#define lwip_ntohl(x) (x) -#define PP_HTONS(x) (x) -#define PP_NTOHS(x) (x) -#define PP_HTONL(x) (x) -#define PP_NTOHL(x) (x) -#else /* BYTE_ORDER != BIG_ENDIAN */ -#ifndef lwip_htons -u16_t lwip_htons(u16_t x); -#endif -#define lwip_ntohs(x) lwip_htons(x) - -#ifndef lwip_htonl -u32_t lwip_htonl(u32_t x); -#endif -#define lwip_ntohl(x) lwip_htonl(x) - -/* Provide usual function names as macros for users, but this can be turned off */ -#ifndef LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS -#define htons(x) lwip_htons(x) -#define ntohs(x) lwip_ntohs(x) -#define htonl(x) lwip_htonl(x) -#define ntohl(x) lwip_ntohl(x) -#endif - -/* These macros should be calculated by the preprocessor and are used - with compile-time constants only (so that there is no little-endian - overhead at runtime). */ -#define PP_HTONS(x) ((((x) & 0x00ffUL) << 8) | (((x) & 0xff00UL) >> 8)) -#define PP_NTOHS(x) PP_HTONS(x) -#define PP_HTONL(x) ((((x) & 0x000000ffUL) << 24) | \ - (((x) & 0x0000ff00UL) << 8) | \ - (((x) & 0x00ff0000UL) >> 8) | \ - (((x) & 0xff000000UL) >> 24)) -#define PP_NTOHL(x) PP_HTONL(x) - -#endif /* BYTE_ORDER == BIG_ENDIAN */ - -/* Functions that are not available as standard implementations. - * In cc.h, you can #define these to implementations available on - * your platform to save some code bytes if you use these functions - * in your application, too. - */ - -#ifndef lwip_itoa -/* This can be #defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform */ -void lwip_itoa(char* result, size_t bufsize, int number); -#endif -#ifndef lwip_strnicmp -/* This can be #defined to strnicmp() or strncasecmp() depending on your platform */ -int lwip_strnicmp(const char* str1, const char* str2, size_t len); -#endif -#ifndef lwip_stricmp -/* This can be #defined to stricmp() or strcasecmp() depending on your platform */ -int lwip_stricmp(const char* str1, const char* str2); -#endif -#ifndef lwip_strnstr -/* This can be #defined to strnstr() depending on your platform */ -char* lwip_strnstr(const char* buffer, const char* token, size_t n); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_DEF_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp.h deleted file mode 100644 index 4a3a1e0dd0c0ed9314d8ae81add3cf04905ceffd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * @file - * DHCP client API - */ - -/* - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * - */ -#ifndef LWIP_HDR_DHCP_H -#define LWIP_HDR_DHCP_H - -#include "lwip/opt.h" - -#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netif.h" -#include "lwip/udp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** period (in seconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_SECS 60 -/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) -/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ -#define DHCP_FINE_TIMER_MSECS 100 - -#define DHCP_BOOT_FILE_LEN 128U - -/* AutoIP cooperation flags (struct dhcp.autoip_coop_state) */ -typedef enum { - DHCP_AUTOIP_COOP_STATE_OFF = 0, - DHCP_AUTOIP_COOP_STATE_ON = 1 -} dhcp_autoip_coop_state_enum_t; - -struct dhcp -{ - /** transaction identifier of last sent request */ - u32_t xid; - /** incoming msg */ - struct dhcp_msg *msg_in; - /** track PCB allocation state */ - u8_t pcb_allocated; - /** current DHCP state machine state */ - u8_t state; - /** retries of current request */ - u8_t tries; -#if LWIP_DHCP_AUTOIP_COOP - u8_t autoip_coop_state; -#endif - u8_t subnet_mask_given; - - struct pbuf *p_out; /* pbuf of outcoming msg */ - struct dhcp_msg *msg_out; /* outgoing msg */ - u16_t options_out_len; /* outgoing msg options length */ - u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ - u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ - u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ - u16_t t1_renew_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */ - u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */ - u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */ - u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */ - ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */ - ip4_addr_t offered_ip_addr; - ip4_addr_t offered_sn_mask; - ip4_addr_t offered_gw_addr; - - u32_t offered_t0_lease; /* lease period (in seconds) */ - u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ - u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period) */ -#if LWIP_DHCP_BOOTP_FILE - ip4_addr_t offered_si_addr; - char boot_file_name[DHCP_BOOT_FILE_LEN]; -#endif /* LWIP_DHCP_BOOTPFILE */ -}; - - -void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp); -/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */ -#define dhcp_remove_struct(netif) do { (netif)->dhcp = NULL; } while(0) -void dhcp_cleanup(struct netif *netif); -err_t dhcp_start(struct netif *netif); -err_t dhcp_renew(struct netif *netif); -err_t dhcp_release(struct netif *netif); -void dhcp_stop(struct netif *netif); -void dhcp_inform(struct netif *netif); -void dhcp_network_changed(struct netif *netif); -#if DHCP_DOES_ARP_CHECK -void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr); -#endif -u8_t dhcp_supplied_address(const struct netif *netif); -/* to be called every minute */ -void dhcp_coarse_tmr(void); -/* to be called every half second */ -void dhcp_fine_tmr(void); - -#if LWIP_DHCP_GET_NTP_SRV -/** This function must exist, in other to add offered NTP servers to - * the NTP (or SNTP) engine. - * See LWIP_DHCP_MAX_NTP_SERVERS */ -extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs); -#endif /* LWIP_DHCP_GET_NTP_SRV */ - -#define netif_dhcp_data(netif) ((struct dhcp*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP)) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_DHCP */ - -#endif /*LWIP_HDR_DHCP_H*/ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp6.h deleted file mode 100644 index 455336d37dc2e6eaaa0d44ced424c28c6dd5e54c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dhcp6.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * - * IPv6 address autoconfiguration as per RFC 4862. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * IPv6 address autoconfiguration as per RFC 4862. - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_IP6_DHCP6_H -#define LWIP_HDR_IP6_DHCP6_H - -#include "lwip/opt.h" - -#if LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */ - - -struct dhcp6 -{ - /*@todo: implement DHCP6*/ -}; - -#endif /* LWIP_IPV6_DHCP6 */ - -#endif /* LWIP_HDR_IP6_DHCP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dns.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dns.h deleted file mode 100644 index 1453d723413dd9d4388043c13f86eafa841f1aa1..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/dns.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * DNS API - */ - -/** - * lwip DNS resolver header file. - - * Author: Jim Pettinato - * April 2007 - - * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LWIP_HDR_DNS_H -#define LWIP_HDR_DNS_H - -#include "lwip/opt.h" - -#if LWIP_DNS - -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** DNS timer period */ -#define DNS_TMR_INTERVAL 1000 - -/* DNS resolve types: */ -#define LWIP_DNS_ADDRTYPE_IPV4 0 -#define LWIP_DNS_ADDRTYPE_IPV6 1 -#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */ -#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */ -#if LWIP_IPV4 && LWIP_IPV6 -#ifndef LWIP_DNS_ADDRTYPE_DEFAULT -#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4_IPV6 -#endif -#elif LWIP_IPV4 -#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4 -#else -#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV6 -#endif - -#if DNS_LOCAL_HOSTLIST -/** struct used for local host-list */ -struct local_hostlist_entry { - /** static hostname */ - const char *name; - /** static host address in network byteorder */ - ip_addr_t addr; - struct local_hostlist_entry *next; -}; -#define DNS_LOCAL_HOSTLIST_ELEM(name, addr_init) {name, addr_init, NULL} -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN -#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN DNS_MAX_NAME_LENGTH -#endif -#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1)) -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ -#endif /* DNS_LOCAL_HOSTLIST */ - -#if LWIP_IPV4 -extern const ip_addr_t dns_mquery_v4group; -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 -extern const ip_addr_t dns_mquery_v6group; -#endif /* LWIP_IPV6 */ - -/** Callback which is invoked when a hostname is found. - * A function of this type must be implemented by the application using the DNS resolver. - * @param name pointer to the name that was looked up. - * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname, - * or NULL if the name could not be found (or on any other error). - * @param callback_arg a user-specified callback argument passed to dns_gethostbyname -*/ -typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg); - -void dns_init(void); -void dns_tmr(void); -void dns_setserver(u8_t numdns, const ip_addr_t *dnsserver); -const ip_addr_t* dns_getserver(u8_t numdns); -err_t dns_gethostbyname(const char *hostname, ip_addr_t *addr, - dns_found_callback found, void *callback_arg); -err_t dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, - dns_found_callback found, void *callback_arg, - u8_t dns_addrtype); - - -#if DNS_LOCAL_HOSTLIST -size_t dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg); -err_t dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype); -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -int dns_local_removehost(const char *hostname, const ip_addr_t *addr); -err_t dns_local_addhost(const char *hostname, const ip_addr_t *addr); -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ -#endif /* DNS_LOCAL_HOSTLIST */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_DNS */ - -#endif /* LWIP_HDR_DNS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/err.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/err.h deleted file mode 100644 index 84e528d1ed8e8793ded3c9206c0fa6622743339b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/err.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * @file - * lwIP Error codes - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_ERR_H -#define LWIP_HDR_ERR_H - -#include "lwip/opt.h" -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup infrastructure_errors Error codes - * @ingroup infrastructure - * @{ - */ - -/** Define LWIP_ERR_T in cc.h if you want to use - * a different type for your platform (must be signed). */ -#ifdef LWIP_ERR_T -typedef LWIP_ERR_T err_t; -#else /* LWIP_ERR_T */ -typedef s8_t err_t; -#endif /* LWIP_ERR_T*/ - -/** Definitions for error constants. */ -typedef enum { -/** No error, everything OK. */ - ERR_OK = 0, -/** Out of memory error. */ - ERR_MEM = -1, -/** Buffer error. */ - ERR_BUF = -2, -/** Timeout. */ - ERR_TIMEOUT = -3, -/** Routing problem. */ - ERR_RTE = -4, -/** Operation in progress */ - ERR_INPROGRESS = -5, -/** Illegal value. */ - ERR_VAL = -6, -/** Operation would block. */ - ERR_WOULDBLOCK = -7, -/** Address in use. */ - ERR_USE = -8, -/** Already connecting. */ - ERR_ALREADY = -9, -/** Conn already established.*/ - ERR_ISCONN = -10, -/** Not connected. */ - ERR_CONN = -11, -/** Low-level netif error */ - ERR_IF = -12, - -/** Connection aborted. */ - ERR_ABRT = -13, -/** Connection reset. */ - ERR_RST = -14, -/** Connection closed. */ - ERR_CLSD = -15, -/** Illegal argument. */ - ERR_ARG = -16 -} err_enum_t; - -#define ERR_IS_FATAL(e) ((e) <= ERR_ABRT) - -/** - * @} - */ - -#ifdef LWIP_DEBUG -extern const char *lwip_strerr(err_t err); -#else -#define lwip_strerr(x) "" -#endif /* LWIP_DEBUG */ - -#if !NO_SYS -int err_to_errno(err_t err); -#endif /* !NO_SYS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_ERR_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/errno.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/errno.h deleted file mode 100644 index 43e5d21e7bd0169b11df6ae026dd89a9cb107e84..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/errno.h +++ /dev/null @@ -1,190 +0,0 @@ -/** - * @file - * Posix Errno defines - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_ERRNO_H -#define LWIP_HDR_ERRNO_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef LWIP_PROVIDE_ERRNO -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -#ifndef errno -extern int errno; -#endif - -#else /* LWIP_PROVIDE_ERRNO */ - -/* Define LWIP_ERRNO_INCLUDE to to include the error defines here */ -#ifdef LWIP_ERRNO_INCLUDE -#include LWIP_ERRNO_INCLUDE -#endif /* LWIP_ERRNO_INCLUDE */ - -#endif /* LWIP_PROVIDE_ERRNO */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_ERRNO_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/etharp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/etharp.h deleted file mode 100644 index 7080a19d0588800e1ce48844fc5260125c363997..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/etharp.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * Ethernet output function - handles OUTGOING ethernet level traffic, implements - * ARP resolving. - * To be used in most low-level netif implementations - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef LWIP_HDR_NETIF_ETHARP_H -#define LWIP_HDR_NETIF_ETHARP_H - -#include "lwip/opt.h" - -#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/ip4_addr.h" -#include "lwip/netif.h" -#include "lwip/ip4.h" -#include "lwip/prot/ethernet.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/prot/etharp.h" - -/** 1 seconds period */ -#define ARP_TMR_INTERVAL 1000 - -#if ARP_QUEUEING -/** struct for queueing outgoing packets for unknown address - * defined here to be accessed by memp.h - */ -struct etharp_q_entry { - struct etharp_q_entry *next; - struct pbuf *p; -}; -#endif /* ARP_QUEUEING */ - -#define etharp_init() /* Compatibility define, no init needed. */ -void etharp_tmr(void); -s8_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr, - struct eth_addr **eth_ret, const ip4_addr_t **ip_ret); -u8_t etharp_get_entry(u8_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret); -err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); -err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q); -err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr); -/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; - * this is an ARP packet sent by a node in order to spontaneously cause other - * nodes to update an entry in their ARP cache. - * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ -#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif)) -void etharp_cleanup_netif(struct netif *netif); - -#if ETHARP_SUPPORT_STATIC_ENTRIES -err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr); -err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr); -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - -#endif /* LWIP_IPV4 && LWIP_ARP */ - -void etharp_input(struct pbuf *p, struct netif *netif); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_ARP || LWIP_ETHERNET */ - -#endif /* LWIP_HDR_NETIF_ETHARP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ethip6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ethip6.h deleted file mode 100644 index 5e88dffd05f1b102402d7244932b0b3589f9cf3e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ethip6.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * Ethernet output for IPv6. Uses ND tables for link-layer addressing. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_ETHIP6_H -#define LWIP_HDR_ETHIP6_H - -#include "lwip/opt.h" - -#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 && LWIP_ETHERNET */ - -#endif /* LWIP_HDR_ETHIP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp.h deleted file mode 100644 index f5a31fd4c070982638b38ee525f26ec35d3ca377..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * @file - * ICMP API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_ICMP_H -#define LWIP_HDR_ICMP_H - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/prot/icmp.h" - -#if LWIP_IPV6 && LWIP_ICMP6 -#include "lwip/icmp6.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** ICMP destination unreachable codes */ -enum icmp_dur_type { - /** net unreachable */ - ICMP_DUR_NET = 0, - /** host unreachable */ - ICMP_DUR_HOST = 1, - /** protocol unreachable */ - ICMP_DUR_PROTO = 2, - /** port unreachable */ - ICMP_DUR_PORT = 3, - /** fragmentation needed and DF set */ - ICMP_DUR_FRAG = 4, - /** source route failed */ - ICMP_DUR_SR = 5 -}; - -/** ICMP time exceeded codes */ -enum icmp_te_type { - /** time to live exceeded in transit */ - ICMP_TE_TTL = 0, - /** fragment reassembly time exceeded */ - ICMP_TE_FRAG = 1 -}; - -#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ - -void icmp_input(struct pbuf *p, struct netif *inp); -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -#endif /* LWIP_IPV4 && LWIP_ICMP */ - -#if LWIP_IPV4 && LWIP_IPV6 -#if LWIP_ICMP && LWIP_ICMP6 -#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \ - icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \ - icmp_dest_unreach(pbuf, ICMP_DUR_PORT)) -#elif LWIP_ICMP -#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0) -#elif LWIP_ICMP6 -#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0) -#else -#define icmp_port_unreach(isipv6, pbuf) -#endif -#elif LWIP_IPV6 && LWIP_ICMP6 -#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) -#elif LWIP_IPV4 && LWIP_ICMP -#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT) -#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */ -#define icmp_port_unreach(isipv6, pbuf) -#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_ICMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp6.h deleted file mode 100644 index a29dc8c1c235c8a7b03871131ba233bf01b56c53..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/icmp6.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * IPv6 version of ICMP, as per RFC 4443. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ -#ifndef LWIP_HDR_ICMP6_H -#define LWIP_HDR_ICMP6_H - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" -#include "lwip/prot/icmp6.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -void icmp6_input(struct pbuf *p, struct netif *inp); -void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c); -void icmp6_packet_too_big(struct pbuf *p, u32_t mtu); -void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c); -void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, u32_t pointer); - -#endif /* LWIP_ICMP6 && LWIP_IPV6 */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* LWIP_HDR_ICMP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/igmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/igmp.h deleted file mode 100644 index ffd80e680c328061cdbab6916556ad2bf610a720..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/igmp.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * @file - * IGMP API - */ - -/* - * Copyright (c) 2002 CITEL Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. -*/ - -#ifndef LWIP_HDR_IGMP_H -#define LWIP_HDR_IGMP_H - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/pbuf.h" - -#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* IGMP timer */ -#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ -#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) -#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) - -/* Compatibility defines (don't use for new code) */ -#define IGMP_DEL_MAC_FILTER NETIF_DEL_MAC_FILTER -#define IGMP_ADD_MAC_FILTER NETIF_ADD_MAC_FILTER - -/** - * igmp group structure - there is - * a list of groups for each interface - * these should really be linked from the interface, but - * if we keep them separate we will not affect the lwip original code - * too much - * - * There will be a group for the all systems group address but this - * will not run the state machine as it is used to kick off reports - * from all the other groups - */ -struct igmp_group { - /** next link */ - struct igmp_group *next; - /** multicast address */ - ip4_addr_t group_address; - /** signifies we were the last person to report */ - u8_t last_reporter_flag; - /** current state of the group */ - u8_t group_state; - /** timer for reporting, negative is OFF */ - u16_t timer; - /** counter of simultaneous uses */ - u8_t use; -}; - -/* Prototypes */ -void igmp_init(void); -err_t igmp_start(struct netif *netif); -err_t igmp_stop(struct netif *netif); -void igmp_report_groups(struct netif *netif); -struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr); -void igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest); -err_t igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr); -err_t igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr); -err_t igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr); -err_t igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr); -void igmp_tmr(void); - -/** @ingroup igmp - * Get list head of IGMP groups for netif. - * Note: The allsystems group IP is contained in the list as first entry. - * @see @ref netif_set_igmp_mac_filter() - */ -#define netif_igmp_data(netif) ((struct igmp_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP)) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV4 && LWIP_IGMP */ - -#endif /* LWIP_HDR_IGMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet.h deleted file mode 100644 index 4a34f026533880bcc4575790a119e46c2b1ddb8e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet.h +++ /dev/null @@ -1,172 +0,0 @@ -/** - * @file - * This file (together with sockets.h) aims to provide structs and functions from - * - arpa/inet.h - * - netinet/in.h - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_INET_H -#define LWIP_HDR_INET_H - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* If your port already typedef's in_addr_t, define IN_ADDR_T_DEFINED - to prevent this code from redefining it. */ -#if !defined(in_addr_t) && !defined(IN_ADDR_T_DEFINED) -typedef u32_t in_addr_t; -#endif - -struct in_addr { - in_addr_t s_addr; -}; - -struct in6_addr { - union { - u32_t u32_addr[4]; - u8_t u8_addr[16]; - } un; -#define s6_addr un.u8_addr -}; - -/** 255.255.255.255 */ -#define INADDR_NONE IPADDR_NONE -/** 127.0.0.1 */ -#define INADDR_LOOPBACK IPADDR_LOOPBACK -/** 0.0.0.0 */ -#define INADDR_ANY IPADDR_ANY -/** 255.255.255.255 */ -#define INADDR_BROADCAST IPADDR_BROADCAST - -/** This macro can be used to initialize a variable of type struct in6_addr - to the IPv6 wildcard address. */ -#define IN6ADDR_ANY_INIT {{{0,0,0,0}}} -/** This macro can be used to initialize a variable of type struct in6_addr - to the IPv6 loopback address. */ -#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}} -/** This variable is initialized by the system to contain the wildcard IPv6 address. */ -extern const struct in6_addr in6addr_any; - -/* Definitions of the bits in an (IPv4) Internet address integer. - - On subnets, host and network parts are found according to - the subnet mask, not these masks. */ -#define IN_CLASSA(a) IP_CLASSA(a) -#define IN_CLASSA_NET IP_CLASSA_NET -#define IN_CLASSA_NSHIFT IP_CLASSA_NSHIFT -#define IN_CLASSA_HOST IP_CLASSA_HOST -#define IN_CLASSA_MAX IP_CLASSA_MAX - -#define IN_CLASSB(b) IP_CLASSB(b) -#define IN_CLASSB_NET IP_CLASSB_NET -#define IN_CLASSB_NSHIFT IP_CLASSB_NSHIFT -#define IN_CLASSB_HOST IP_CLASSB_HOST -#define IN_CLASSB_MAX IP_CLASSB_MAX - -#define IN_CLASSC(c) IP_CLASSC(c) -#define IN_CLASSC_NET IP_CLASSC_NET -#define IN_CLASSC_NSHIFT IP_CLASSC_NSHIFT -#define IN_CLASSC_HOST IP_CLASSC_HOST -#define IN_CLASSC_MAX IP_CLASSC_MAX - -#define IN_CLASSD(d) IP_CLASSD(d) -#define IN_CLASSD_NET IP_CLASSD_NET /* These ones aren't really */ -#define IN_CLASSD_NSHIFT IP_CLASSD_NSHIFT /* net and host fields, but */ -#define IN_CLASSD_HOST IP_CLASSD_HOST /* routing needn't know. */ -#define IN_CLASSD_MAX IP_CLASSD_MAX - -#define IN_MULTICAST(a) IP_MULTICAST(a) - -#define IN_EXPERIMENTAL(a) IP_EXPERIMENTAL(a) -#define IN_BADCLASS(a) IP_BADCLASS(a) - -#define IN_LOOPBACKNET IP_LOOPBACKNET - - -#ifndef INET_ADDRSTRLEN -#define INET_ADDRSTRLEN IP4ADDR_STRLEN_MAX -#endif -#if LWIP_IPV6 -#ifndef INET6_ADDRSTRLEN -#define INET6_ADDRSTRLEN IP6ADDR_STRLEN_MAX -#endif -#endif - -#if LWIP_IPV4 - -#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr)) -#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr) (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr)) -/* ATTENTION: the next define only works because both s_addr and ip4_addr_t are an u32_t effectively! */ -#define inet_addr_to_ip4addr_p(target_ip4addr_p, source_inaddr) ((target_ip4addr_p) = (ip4_addr_t*)&((source_inaddr)->s_addr)) - -/* directly map this to the lwip internal functions */ -#define inet_addr(cp) ipaddr_addr(cp) -#define inet_aton(cp, addr) ip4addr_aton(cp, (ip4_addr_t*)addr) -#define inet_ntoa(addr) ip4addr_ntoa((const ip4_addr_t*)&(addr)) -#define inet_ntoa_r(addr, buf, buflen) ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen) - -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \ - (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \ - (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \ - (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];} -#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr) {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \ - (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \ - (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \ - (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3];} -/* ATTENTION: the next define only works because both in6_addr and ip6_addr_t are an u32_t[4] effectively! */ -#define inet6_addr_to_ip6addr_p(target_ip6addr_p, source_in6addr) ((target_ip6addr_p) = (ip6_addr_t*)(source_in6addr)) - -/* directly map this to the lwip internal functions */ -#define inet6_aton(cp, addr) ip6addr_aton(cp, (ip6_addr_t*)addr) -#define inet6_ntoa(addr) ip6addr_ntoa((const ip6_addr_t*)&(addr)) -#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen) - -#endif /* LWIP_IPV6 */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_INET_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet_chksum.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet_chksum.h deleted file mode 100644 index 4e23d7f1944614f7d7e31d110c2881d87d6cc6c0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/inet_chksum.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * @file - * IP checksum calculation functions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_INET_CHKSUM_H -#define LWIP_HDR_INET_CHKSUM_H - -#include "lwip/opt.h" - -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -/** Swap the bytes in an u16_t: much like lwip_htons() for little-endian */ -#ifndef SWAP_BYTES_IN_WORD -#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8) -#endif /* SWAP_BYTES_IN_WORD */ - -/** Split an u32_t in two u16_ts and add them up */ -#ifndef FOLD_U32T -#define FOLD_U32T(u) (((u) >> 16) + ((u) & 0x0000ffffUL)) -#endif - -#if LWIP_CHECKSUM_ON_COPY -/** Function-like macro: same as MEMCPY but returns the checksum of copied data - as u16_t */ -# ifndef LWIP_CHKSUM_COPY -# define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len) -# ifndef LWIP_CHKSUM_COPY_ALGORITHM -# define LWIP_CHKSUM_COPY_ALGORITHM 1 -# endif /* LWIP_CHKSUM_COPY_ALGORITHM */ -# else /* LWIP_CHKSUM_COPY */ -# define LWIP_CHKSUM_COPY_ALGORITHM 0 -# endif /* LWIP_CHKSUM_COPY */ -#else /* LWIP_CHECKSUM_ON_COPY */ -# define LWIP_CHKSUM_COPY_ALGORITHM 0 -#endif /* LWIP_CHECKSUM_ON_COPY */ - -#ifdef __cplusplus -extern "C" { -#endif - -u16_t inet_chksum(const void *dataptr, u16_t len); -u16_t inet_chksum_pbuf(struct pbuf *p); -#if LWIP_CHKSUM_COPY_ALGORITHM -u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len); -#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ - -#if LWIP_IPV4 -u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip4_addr_t *src, const ip4_addr_t *dest); -u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto, - u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest); -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip6_addr_t *src, const ip6_addr_t *dest); -u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest); -#endif /* LWIP_IPV6 */ - - -u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, - const ip_addr_t *src, const ip_addr_t *dest); -u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, - u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_INET_H */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/init.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/init.h deleted file mode 100644 index 940fa21aff01ec35ce04799792d6f1da636b51ec..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/init.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * lwIP initialization API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_INIT_H -#define LWIP_HDR_INIT_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup lwip_version Version - * @ingroup lwip - * @{ - */ - -/** X.x.x: Major version of the stack */ -#define LWIP_VERSION_MAJOR 2 -/** x.X.x: Minor version of the stack */ -#define LWIP_VERSION_MINOR 0 -/** x.x.X: Revision of the stack */ -#define LWIP_VERSION_REVISION 2 -/** For release candidates, this is set to 1..254 - * For official releases, this is set to 255 (LWIP_RC_RELEASE) - * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */ -#define LWIP_VERSION_RC LWIP_RC_RELEASE - -/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ -#define LWIP_RC_RELEASE 255 -/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */ -#define LWIP_RC_DEVELOPMENT 0 - -#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) -#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) -#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) - -/* Some helper defines to get a version string */ -#define LWIP_VERSTR2(x) #x -#define LWIP_VERSTR(x) LWIP_VERSTR2(x) -#if LWIP_VERSION_IS_RELEASE -#define LWIP_VERSION_STRING_SUFFIX "" -#elif LWIP_VERSION_IS_DEVELOPMENT -#define LWIP_VERSION_STRING_SUFFIX "d" -#else -#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC) -#endif - -/** Provides the version of the stack */ -#define LWIP_VERSION (((u32_t)LWIP_VERSION_MAJOR) << 24 | ((u32_t)LWIP_VERSION_MINOR) << 16 | \ - ((u32_t)LWIP_VERSION_REVISION) << 8 | ((u32_t)LWIP_VERSION_RC)) -/** Provides the version of the stack as string */ -#define LWIP_VERSION_STRING LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX - -/** - * @} - */ - -/* Modules initialization */ -void lwip_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_INIT_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip.h deleted file mode 100644 index 0673be9b4a817e7f6a601ad546f9c25e8d9f8df5..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip.h +++ /dev/null @@ -1,319 +0,0 @@ -/** - * @file - * IP API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_IP_H -#define LWIP_HDR_IP_H - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" -#include "lwip/netif.h" -#include "lwip/ip4.h" -#include "lwip/ip6.h" -#include "lwip/prot/ip.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#define LWIP_IP_HDRINCL NULL - -/** pbufs passed to IP must have a ref-count of 1 as their payload pointer - gets altered as the packet is passed down the stack */ -#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX -#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1) -#endif - -#if LWIP_NETIF_HWADDRHINT -#define IP_PCB_ADDRHINT ;u8_t addr_hint -#else -#define IP_PCB_ADDRHINT -#endif /* LWIP_NETIF_HWADDRHINT */ - -/** This is the common part of all PCB types. It needs to be at the - beginning of a PCB type definition. It is located here so that - changes to this common part are made in one location instead of - having to change all PCB structs. */ -#define IP_PCB \ - /* ip addresses in network byte order */ \ - ip_addr_t local_ip; \ - ip_addr_t remote_ip; \ - /* Socket options */ \ - u8_t so_options; \ - /* Type Of Service */ \ - u8_t tos; \ - /* Time To Live */ \ - u8_t ttl \ - /* link layer address resolution hint */ \ - IP_PCB_ADDRHINT - -struct ip_pcb { -/* Common members of all PCB types */ - IP_PCB; -}; - -/* - * Option flags per-socket. These are the same like SO_XXX in sockets.h - */ -#define SOF_REUSEADDR 0x04U /* allow local address reuse */ -#define SOF_KEEPALIVE 0x08U /* keep connections alive */ -#define SOF_BROADCAST 0x20U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ - -/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */ -#define SOF_INHERITED (SOF_REUSEADDR|SOF_KEEPALIVE) - -/** Global variables of this module, kept in a struct for efficient access using base+index. */ -struct ip_globals -{ - /** The interface that accepted the packet for the current callback invocation. */ - struct netif *current_netif; - /** The interface that received the packet for the current callback invocation. */ - struct netif *current_input_netif; -#if LWIP_IPV4 - /** Header of the input packet currently being processed. */ - struct ip_hdr *current_ip4_header; -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - /** Header of the input IPv6 packet currently being processed. */ - struct ip6_hdr *current_ip6_header; -#endif /* LWIP_IPV6 */ - /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */ - u16_t current_ip_header_tot_len; - /** Source IP address of current_header */ - ip_addr_t current_iphdr_src; - /** Destination IP address of current_header */ - ip_addr_t current_iphdr_dest; -}; -extern struct ip_globals ip_data; - - -/** Get the interface that accepted the current packet. - * This may or may not be the receiving netif, depending on your netif/network setup. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip_current_netif() (ip_data.current_netif) -/** Get the interface that received the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip_current_input_netif() (ip_data.current_input_netif) -/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */ -#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len) -/** Source IP address of current_header */ -#define ip_current_src_addr() (&ip_data.current_iphdr_src) -/** Destination IP address of current_header */ -#define ip_current_dest_addr() (&ip_data.current_iphdr_dest) - -#if LWIP_IPV4 && LWIP_IPV6 -/** Get the IPv4 header of the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip4_current_header() ((const struct ip_hdr*)(ip_data.current_ip4_header)) -/** Get the IPv6 header of the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header)) -/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */ -#define ip_current_is_v6() (ip6_current_header() != NULL) -/** Source IPv6 address of current_header */ -#define ip6_current_src_addr() (ip_2_ip6(&ip_data.current_iphdr_src)) -/** Destination IPv6 address of current_header */ -#define ip6_current_dest_addr() (ip_2_ip6(&ip_data.current_iphdr_dest)) -/** Get the transport layer protocol */ -#define ip_current_header_proto() (ip_current_is_v6() ? \ - IP6H_NEXTH(ip6_current_header()) :\ - IPH_PROTO(ip4_current_header())) -/** Get the transport layer header */ -#define ip_next_header_ptr() ((const void*)((ip_current_is_v6() ? \ - (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header()) + ip_current_header_tot_len())) - -/** Source IP4 address of current_header */ -#define ip4_current_src_addr() (ip_2_ip4(&ip_data.current_iphdr_src)) -/** Destination IP4 address of current_header */ -#define ip4_current_dest_addr() (ip_2_ip4(&ip_data.current_iphdr_dest)) - -#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */ - -/** Get the IPv4 header of the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip4_current_header() ((const struct ip_hdr*)(ip_data.current_ip4_header)) -/** Always returns FALSE when only supporting IPv4 only */ -#define ip_current_is_v6() 0 -/** Get the transport layer protocol */ -#define ip_current_header_proto() IPH_PROTO(ip4_current_header()) -/** Get the transport layer header */ -#define ip_next_header_ptr() ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len())) -/** Source IP4 address of current_header */ -#define ip4_current_src_addr() (&ip_data.current_iphdr_src) -/** Destination IP4 address of current_header */ -#define ip4_current_dest_addr() (&ip_data.current_iphdr_dest) - -#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ - -/** Get the IPv6 header of the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header)) -/** Always returns TRUE when only supporting IPv6 only */ -#define ip_current_is_v6() 1 -/** Get the transport layer protocol */ -#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header()) -/** Get the transport layer header */ -#define ip_next_header_ptr() ((const void*)((const u8_t*)ip6_current_header())) -/** Source IP6 address of current_header */ -#define ip6_current_src_addr() (&ip_data.current_iphdr_src) -/** Destination IP6 address of current_header */ -#define ip6_current_dest_addr() (&ip_data.current_iphdr_dest) - -#endif /* LWIP_IPV6 */ - -/** Union source address of current_header */ -#define ip_current_src_addr() (&ip_data.current_iphdr_src) -/** Union destination address of current_header */ -#define ip_current_dest_addr() (&ip_data.current_iphdr_dest) - -/** Gets an IP pcb option (SOF_* flags) */ -#define ip_get_option(pcb, opt) ((pcb)->so_options & (opt)) -/** Sets an IP pcb option (SOF_* flags) */ -#define ip_set_option(pcb, opt) ((pcb)->so_options |= (opt)) -/** Resets an IP pcb option (SOF_* flags) */ -#define ip_reset_option(pcb, opt) ((pcb)->so_options &= ~(opt)) - -#if LWIP_IPV4 && LWIP_IPV6 -/** - * @ingroup ip - * Output IP packet, netif is selected by source address - */ -#define ip_output(p, src, dest, ttl, tos, proto) \ - (IP_IS_V6(dest) ? \ - ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \ - ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto)) -/** - * @ingroup ip - * Output IP packet to specified interface - */ -#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ - (IP_IS_V6(dest) ? \ - ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \ - ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif)) -/** - * @ingroup ip - * Output IP packet to interface specifying source address - */ -#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ - (IP_IS_V6(dest) ? \ - ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \ - ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif)) -/** Output IP packet with addr_hint */ -#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \ - (IP_IS_V6(dest) ? \ - ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, addr_hint) : \ - ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, addr_hint)) -/** - * @ingroup ip - * Get netif for address combination. See \ref ip6_route and \ref ip4_route - */ -#define ip_route(src, dest) \ - (IP_IS_V6(dest) ? \ - ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \ - ip4_route_src(ip_2_ip4(dest), ip_2_ip4(src))) -/** - * @ingroup ip - * Get netif for IP. - */ -#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \ - ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \ - ip4_netif_get_local_ip(netif)) -#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p)) - -err_t ip_input(struct pbuf *p, struct netif *inp); - -#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */ - -#define ip_output(p, src, dest, ttl, tos, proto) \ - ip4_output(p, src, dest, ttl, tos, proto) -#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ - ip4_output_if(p, src, dest, ttl, tos, proto, netif) -#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ - ip4_output_if_src(p, src, dest, ttl, tos, proto, netif) -#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \ - ip4_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) -#define ip_route(src, dest) \ - ip4_route_src(dest, src) -#define ip_netif_get_local_ip(netif, dest) \ - ip4_netif_get_local_ip(netif) -#define ip_debug_print(is_ipv6, p) ip4_debug_print(p) - -#define ip_input ip4_input - -#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ - -#define ip_output(p, src, dest, ttl, tos, proto) \ - ip6_output(p, src, dest, ttl, tos, proto) -#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ - ip6_output_if(p, src, dest, ttl, tos, proto, netif) -#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ - ip6_output_if_src(p, src, dest, ttl, tos, proto, netif) -#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \ - ip6_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) -#define ip_route(src, dest) \ - ip6_route(src, dest) -#define ip_netif_get_local_ip(netif, dest) \ - ip6_netif_get_local_ip(netif, dest) -#define ip_debug_print(is_ipv6, p) ip6_debug_print(p) - -#define ip_input ip6_input - -#endif /* LWIP_IPV6 */ - -#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \ - (netif) = ip_route(src, dest); \ - (ipaddr) = ip_netif_get_local_ip(netif, dest); \ -}while(0) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_IP_H */ - - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4.h deleted file mode 100644 index 48246ecc257d10442e79637adb882afc9ed6b006..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * @file - * IPv4 API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_IP4_H -#define LWIP_HDR_IP4_H - -#include "lwip/opt.h" - -#if LWIP_IPV4 - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip4_addr.h" -#include "lwip/err.h" -#include "lwip/netif.h" -#include "lwip/prot/ip4.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef LWIP_HOOK_IP4_ROUTE_SRC -#define LWIP_IPV4_SRC_ROUTING 1 -#else -#define LWIP_IPV4_SRC_ROUTING 0 -#endif - -/** Currently, the function ip_output_if_opt() is only used with IGMP */ -#define IP_OPTIONS_SEND (LWIP_IPV4 && LWIP_IGMP) - -#define ip_init() /* Compatibility define, no init needed. */ -struct netif *ip4_route(const ip4_addr_t *dest); -#if LWIP_IPV4_SRC_ROUTING -struct netif *ip4_route_src(const ip4_addr_t *dest, const ip4_addr_t *src); -#else /* LWIP_IPV4_SRC_ROUTING */ -#define ip4_route_src(dest, src) ip4_route(dest) -#endif /* LWIP_IPV4_SRC_ROUTING */ -err_t ip4_input(struct pbuf *p, struct netif *inp); -err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto); -err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif); -err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif); -#if LWIP_NETIF_HWADDRHINT -err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT */ -#if IP_OPTIONS_SEND -err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen); -err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen); -#endif /* IP_OPTIONS_SEND */ - -#if LWIP_MULTICAST_TX_OPTIONS -void ip4_set_default_multicast_netif(struct netif* default_multicast_netif); -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - -#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL) - -#if IP_DEBUG -void ip4_debug_print(struct pbuf *p); -#else -#define ip4_debug_print(p) -#endif /* IP_DEBUG */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV4 */ - -#endif /* LWIP_HDR_IP_H */ - - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_addr.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_addr.h deleted file mode 100644 index 51b46b8d4c654b8f21c30e6775b609be41c4643d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_addr.h +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file - * IPv4 address API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_IP4_ADDR_H -#define LWIP_HDR_IP4_ADDR_H - -#include "lwip/opt.h" -#include "lwip/def.h" - -#if LWIP_IPV4 - -#ifdef __cplusplus -extern "C" { -#endif - -/** This is the aligned version of ip4_addr_t, - used as local variable, on the stack, etc. */ -struct ip4_addr { - u32_t addr; -}; - -/** ip4_addr_t uses a struct for convenience only, so that the same defines can - * operate both on ip4_addr_t as well as on ip4_addr_p_t. */ -typedef struct ip4_addr ip4_addr_t; - -/** - * struct ipaddr2 is used in the definition of the ARP packet format in - * order to support compilers that don't have structure packing. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip4_addr2 { - PACK_STRUCT_FIELD(u16_t addrw[2]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* Forward declaration to not include netif.h */ -struct netif; - -/** 255.255.255.255 */ -#define IPADDR_NONE ((u32_t)0xffffffffUL) -/** 127.0.0.1 */ -#define IPADDR_LOOPBACK ((u32_t)0x7f000001UL) -/** 0.0.0.0 */ -#define IPADDR_ANY ((u32_t)0x00000000UL) -/** 255.255.255.255 */ -#define IPADDR_BROADCAST ((u32_t)0xffffffffUL) - -/* Definitions of the bits in an Internet address integer. - - On subnets, host and network parts are found according to - the subnet mask, not these masks. */ -#define IP_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) -#define IP_CLASSA_NET 0xff000000 -#define IP_CLASSA_NSHIFT 24 -#define IP_CLASSA_HOST (0xffffffff & ~IP_CLASSA_NET) -#define IP_CLASSA_MAX 128 - -#define IP_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) -#define IP_CLASSB_NET 0xffff0000 -#define IP_CLASSB_NSHIFT 16 -#define IP_CLASSB_HOST (0xffffffff & ~IP_CLASSB_NET) -#define IP_CLASSB_MAX 65536 - -#define IP_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) -#define IP_CLASSC_NET 0xffffff00 -#define IP_CLASSC_NSHIFT 8 -#define IP_CLASSC_HOST (0xffffffff & ~IP_CLASSC_NET) - -#define IP_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) -#define IP_CLASSD_NET 0xf0000000 /* These ones aren't really */ -#define IP_CLASSD_NSHIFT 28 /* net and host fields, but */ -#define IP_CLASSD_HOST 0x0fffffff /* routing needn't know. */ -#define IP_MULTICAST(a) IP_CLASSD(a) - -#define IP_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) -#define IP_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) - -#define IP_LOOPBACKNET 127 /* official! */ - -/** Set an IP address given by the four byte-parts */ -#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = PP_HTONL(LWIP_MAKEU32(a,b,c,d)) - -/** MEMCPY-like copying of IP addresses where addresses are known to be - * 16-bit-aligned if the port is correctly configured (so a port could define - * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */ -#ifndef IPADDR2_COPY -#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t)) -#endif - -/** Copy IP address - faster than ip4_addr_set: no NULL check */ -#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr) -/** Safely copy one IP address to another (src may be NULL) */ -#define ip4_addr_set(dest, src) ((dest)->addr = \ - ((src) == NULL ? 0 : \ - (src)->addr)) -/** Set complete address to zero */ -#define ip4_addr_set_zero(ipaddr) ((ipaddr)->addr = 0) -/** Set address to IPADDR_ANY (no need for lwip_htonl()) */ -#define ip4_addr_set_any(ipaddr) ((ipaddr)->addr = IPADDR_ANY) -/** Set address to loopback address */ -#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK)) -/** Check if an address is in the loopback region */ -#define ip4_addr_isloopback(ipaddr) (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24)) -/** Safely copy one IP address to another and change byte order - * from host- to network-order. */ -#define ip4_addr_set_hton(dest, src) ((dest)->addr = \ - ((src) == NULL ? 0:\ - lwip_htonl((src)->addr))) -/** IPv4 only: set the IP address given as an u32_t */ -#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32)) -/** IPv4 only: get the IP address as an u32_t */ -#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr) - -/** Get the network address by combining host address with netmask */ -#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0) - -/** - * Determine if two address are on the same network. - * - * @arg addr1 IP address 1 - * @arg addr2 IP address 2 - * @arg mask network identifier mask - * @return !0 if the network identifiers of both address match - */ -#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ - (mask)->addr) == \ - ((addr2)->addr & \ - (mask)->addr)) -#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) - -#define ip4_addr_isany_val(addr1) ((addr1).addr == IPADDR_ANY) -#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1))) - -#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif) -u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif); - -#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr) -u8_t ip4_addr_netmask_valid(u32_t netmask); - -#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL)) - -#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL)) - -#define ip4_addr_debug_print_parts(debug, a, b, c, d) \ - LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d)) -#define ip4_addr_debug_print(debug, ipaddr) \ - ip4_addr_debug_print_parts(debug, \ - (u16_t)((ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0)) -#define ip4_addr_debug_print_val(debug, ipaddr) \ - ip4_addr_debug_print_parts(debug, \ - ip4_addr1_16(&(ipaddr)), \ - ip4_addr2_16(&(ipaddr)), \ - ip4_addr3_16(&(ipaddr)), \ - ip4_addr4_16(&(ipaddr))) - -/* Get one byte from the 4-byte address */ -#define ip4_addr1(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[0]) -#define ip4_addr2(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[1]) -#define ip4_addr3(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[2]) -#define ip4_addr4(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[3]) -/* These are cast to u16_t, with the intent that they are often arguments - * to printf using the U16_F format from cc.h. */ -#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr)) -#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr)) -#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr)) -#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr)) - -#define IP4ADDR_STRLEN_MAX 16 - -/** For backwards compatibility */ -#define ip_ntoa(ipaddr) ipaddr_ntoa(ipaddr) - -u32_t ipaddr_addr(const char *cp); -int ip4addr_aton(const char *cp, ip4_addr_t *addr); -/** returns ptr to static buffer; not reentrant! */ -char *ip4addr_ntoa(const ip4_addr_t *addr); -char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV4 */ - -#endif /* LWIP_HDR_IP_ADDR_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_frag.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_frag.h deleted file mode 100644 index ed5bf14a31c3381bc3f2398f08d332d5d1af19ae..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip4_frag.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * IP fragmentation/reassembly - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * - */ - -#ifndef LWIP_HDR_IP4_FRAG_H -#define LWIP_HDR_IP4_FRAG_H - -#include "lwip/opt.h" -#include "lwip/err.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/ip_addr.h" -#include "lwip/ip.h" - -#if LWIP_IPV4 - -#ifdef __cplusplus -extern "C" { -#endif - -#if IP_REASSEMBLY -/* The IP reassembly timer interval in milliseconds. */ -#define IP_TMR_INTERVAL 1000 - -/** IP reassembly helper struct. - * This is exported because memp needs to know the size. - */ -struct ip_reassdata { - struct ip_reassdata *next; - struct pbuf *p; - struct ip_hdr iphdr; - u16_t datagram_len; - u8_t flags; - u8_t timer; -}; - -void ip_reass_init(void); -void ip_reass_tmr(void); -struct pbuf * ip4_reass(struct pbuf *p); -#endif /* IP_REASSEMBLY */ - -#if IP_FRAG -#if !LWIP_NETIF_TX_SINGLE_PBUF -#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED -#define LWIP_PBUF_CUSTOM_REF_DEFINED -/** A custom pbuf that holds a reference to another pbuf, which is freed - * when this custom pbuf is freed. This is used to create a custom PBUF_REF - * that points into the original pbuf. */ -struct pbuf_custom_ref { - /** 'base class' */ - struct pbuf_custom pc; - /** pointer to the original pbuf that is referenced */ - struct pbuf *original; -}; -#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */ -#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ - -err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest); -#endif /* IP_FRAG */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV4 */ - -#endif /* LWIP_HDR_IP4_FRAG_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6.h deleted file mode 100644 index 099b94fb74f2f69959420de1efcd7053520c2540..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * @file - * - * IPv6 layer. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ -#ifndef LWIP_HDR_IP6_H -#define LWIP_HDR_IP6_H - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip6_addr.h" -#include "lwip/prot/ip6.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" - -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest); -const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest); -err_t ip6_input(struct pbuf *p, struct netif *inp); -err_t ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth); -err_t ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth, struct netif *netif); -err_t ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth, struct netif *netif); -#if LWIP_NETIF_HWADDRHINT -err_t ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, - u8_t hl, u8_t tc, u8_t nexth, u8_t *addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT */ -#if LWIP_IPV6_MLD -err_t ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value); -#endif /* LWIP_IPV6_MLD */ - -#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \ - ip6_select_source_address(netif, dest) : NULL) - -#if IP6_DEBUG -void ip6_debug_print(struct pbuf *p); -#else -#define ip6_debug_print(p) -#endif /* IP6_DEBUG */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 */ - -#endif /* LWIP_HDR_IP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_addr.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_addr.h deleted file mode 100644 index ee381aeb233722dbab958f96e8ff0d8330b6c1e0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_addr.h +++ /dev/null @@ -1,285 +0,0 @@ -/** - * @file - * - * IPv6 addresses. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * Structs and macros for handling IPv6 addresses. - * - * Please coordinate changes and requests with Ivan Delamer - * - */ -#ifndef LWIP_HDR_IP6_ADDR_H -#define LWIP_HDR_IP6_ADDR_H - -#include "lwip/opt.h" -#include "def.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** This is the aligned version of ip6_addr_t, - used as local variable, on the stack, etc. */ -struct ip6_addr { - u32_t addr[4]; -}; - -/** IPv6 address */ -typedef struct ip6_addr ip6_addr_t; - -/** Set an IPv6 partial address given by byte-parts */ -#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \ - (ip6addr)->addr[index] = PP_HTONL(LWIP_MAKEU32(a,b,c,d)) - -/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order - (use PP_HTONL() for constants) */ -#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \ - (ip6addr)->addr[0] = idx0; \ - (ip6addr)->addr[1] = idx1; \ - (ip6addr)->addr[2] = idx2; \ - (ip6addr)->addr[3] = idx3; } while(0) - -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0])) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1]) >> 16) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1])) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2]) >> 16) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2])) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3]) >> 16) & 0xffff)) -/** Access address in 16-bit block */ -#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3])) & 0xffff)) - -/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */ -#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \ - (dest).addr[1] = (src).addr[1]; \ - (dest).addr[2] = (src).addr[2]; \ - (dest).addr[3] = (src).addr[3];}while(0) -/** Safely copy one IPv6 address to another (src may be NULL) */ -#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \ - (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \ - (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \ - (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3];}while(0) - -/** Set complete address to zero */ -#define ip6_addr_set_zero(ip6addr) do{(ip6addr)->addr[0] = 0; \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[2] = 0; \ - (ip6addr)->addr[3] = 0;}while(0) - -/** Set address to ipv6 'any' (no need for lwip_htonl()) */ -#define ip6_addr_set_any(ip6addr) ip6_addr_set_zero(ip6addr) -/** Set address to ipv6 loopback address */ -#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[2] = 0; \ - (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0) -/** Safely copy one IPv6 address to another and change byte order - * from host- to network-order. */ -#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : lwip_htonl((src)->addr[0]); \ - (dest)->addr[1] = (src) == NULL ? 0 : lwip_htonl((src)->addr[1]); \ - (dest)->addr[2] = (src) == NULL ? 0 : lwip_htonl((src)->addr[2]); \ - (dest)->addr[3] = (src) == NULL ? 0 : lwip_htonl((src)->addr[3]);}while(0) - - -/** - * Determine if two IPv6 address are on the same network. - * - * @arg addr1 IPv6 address 1 - * @arg addr2 IPv6 address 2 - * @return !0 if the network identifiers of both address match - */ -#define ip6_addr_netcmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \ - ((addr1)->addr[1] == (addr2)->addr[1])) - -#define ip6_addr_cmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \ - ((addr1)->addr[1] == (addr2)->addr[1]) && \ - ((addr1)->addr[2] == (addr2)->addr[2]) && \ - ((addr1)->addr[3] == (addr2)->addr[3])) - -#define ip6_get_subnet_id(ip6addr) (lwip_htonl((ip6addr)->addr[2]) & 0x0000ffffUL) - -#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \ - ((ip6addr).addr[1] == 0) && \ - ((ip6addr).addr[2] == 0) && \ - ((ip6addr).addr[3] == 0)) -#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr))) - -#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \ - ((ip6addr)->addr[1] == 0UL) && \ - ((ip6addr)->addr[2] == 0UL) && \ - ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) - -#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL)) - -#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL)) - -#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL)) - -#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL)) - -#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL))) - -#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) -#define ip6_addr_multicast_transient_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL)) -#define ip6_addr_multicast_prefix_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL)) -#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL)) -#define ip6_addr_multicast_scope(ip6addr) ((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xf) -#define IP6_MULTICAST_SCOPE_RESERVED 0x0 -#define IP6_MULTICAST_SCOPE_RESERVED0 0x0 -#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL 0x1 -#define IP6_MULTICAST_SCOPE_LINK_LOCAL 0x2 -#define IP6_MULTICAST_SCOPE_RESERVED3 0x3 -#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL 0x4 -#define IP6_MULTICAST_SCOPE_SITE_LOCAL 0x5 -#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL 0x8 -#define IP6_MULTICAST_SCOPE_GLOBAL 0xe -#define IP6_MULTICAST_SCOPE_RESERVEDF 0xf -#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL)) -#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL)) -#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL)) -#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL)) -#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL)) -#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL)) - -/* @todo define get/set for well-know multicast addresses, e.g. ff02::1 */ -#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \ - ((ip6addr)->addr[1] == 0UL) && \ - ((ip6addr)->addr[2] == 0UL) && \ - ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) - -#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ - ((ip6addr)->addr[1] == 0UL) && \ - ((ip6addr)->addr[2] == 0UL) && \ - ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) -#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[2] = 0; \ - (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0) - -#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ - ((ip6addr)->addr[1] == 0UL) && \ - ((ip6addr)->addr[2] == 0UL) && \ - ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL))) -#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[2] = 0; \ - (ip6addr)->addr[3] = PP_HTONL(0x00000002UL);}while(0) - -#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ - ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \ - (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) ) - -#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \ - (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id));}while(0) - -#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ - ((ip6addr)->addr[1] == 0) && \ - ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \ - ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3]))) - -/* IPv6 address states. */ -#define IP6_ADDR_INVALID 0x00 -#define IP6_ADDR_TENTATIVE 0x08 -#define IP6_ADDR_TENTATIVE_1 0x09 /* 1 probe sent */ -#define IP6_ADDR_TENTATIVE_2 0x0a /* 2 probes sent */ -#define IP6_ADDR_TENTATIVE_3 0x0b /* 3 probes sent */ -#define IP6_ADDR_TENTATIVE_4 0x0c /* 4 probes sent */ -#define IP6_ADDR_TENTATIVE_5 0x0d /* 5 probes sent */ -#define IP6_ADDR_TENTATIVE_6 0x0e /* 6 probes sent */ -#define IP6_ADDR_TENTATIVE_7 0x0f /* 7 probes sent */ -#define IP6_ADDR_VALID 0x10 /* This bit marks an address as valid (preferred or deprecated) */ -#define IP6_ADDR_PREFERRED 0x30 -#define IP6_ADDR_DEPRECATED 0x10 /* Same as VALID (valid but not preferred) */ - -#define IP6_ADDR_TENTATIVE_COUNT_MASK 0x07 /* 1-7 probes sent */ - -#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID) -#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE) -#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */ -#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED) -#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED) - -#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \ - LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \ - a, b, c, d, e, f, g, h)) -#define ip6_addr_debug_print(debug, ipaddr) \ - ip6_addr_debug_print_parts(debug, \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0), \ - (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0)) -#define ip6_addr_debug_print_val(debug, ipaddr) \ - ip6_addr_debug_print_parts(debug, \ - IP6_ADDR_BLOCK1(&(ipaddr)), \ - IP6_ADDR_BLOCK2(&(ipaddr)), \ - IP6_ADDR_BLOCK3(&(ipaddr)), \ - IP6_ADDR_BLOCK4(&(ipaddr)), \ - IP6_ADDR_BLOCK5(&(ipaddr)), \ - IP6_ADDR_BLOCK6(&(ipaddr)), \ - IP6_ADDR_BLOCK7(&(ipaddr)), \ - IP6_ADDR_BLOCK8(&(ipaddr))) - -#define IP6ADDR_STRLEN_MAX 46 - -int ip6addr_aton(const char *cp, ip6_addr_t *addr); -/** returns ptr to static buffer; not reentrant! */ -char *ip6addr_ntoa(const ip6_addr_t *addr); -char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen); - - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 */ - -#endif /* LWIP_HDR_IP6_ADDR_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_frag.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_frag.h deleted file mode 100644 index 6be274734b2198ac8188c266b6a13a082c1e0ffc..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip6_frag.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file - * - * IPv6 fragmentation and reassembly. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ -#ifndef LWIP_HDR_IP6_FRAG_H -#define LWIP_HDR_IP6_FRAG_H - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip6_addr.h" -#include "lwip/ip6.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#if LWIP_IPV6 && LWIP_IPV6_REASS /* don't build if not configured for use in lwipopts.h */ - -/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, this needs to - * be enabled (to not overwrite part of the data). When enabled, the IPv6 header - * is copied instead of referencing it, which gives more room for struct ip6_reass_helper */ -#ifndef IPV6_FRAG_COPYHEADER -#define IPV6_FRAG_COPYHEADER 0 -#endif - -/** The IPv6 reassembly timer interval in milliseconds. */ -#define IP6_REASS_TMR_INTERVAL 1000 - -/* Copy the complete header of the first fragment to struct ip6_reassdata - or just point to its original location in the first pbuf? */ -#if IPV6_FRAG_COPYHEADER -#define IPV6_FRAG_HDRPTR -#define IPV6_FRAG_HDRREF(hdr) (&(hdr)) -#else /* IPV6_FRAG_COPYHEADER */ -#define IPV6_FRAG_HDRPTR * -#define IPV6_FRAG_HDRREF(hdr) (hdr) -#endif /* IPV6_FRAG_COPYHEADER */ - -/** IPv6 reassembly helper struct. - * This is exported because memp needs to know the size. - */ -struct ip6_reassdata { - struct ip6_reassdata *next; - struct pbuf *p; - struct ip6_hdr IPV6_FRAG_HDRPTR iphdr; - u32_t identification; - u16_t datagram_len; - u8_t nexth; - u8_t timer; -}; - -#define ip6_reass_init() /* Compatibility define */ -void ip6_reass_tmr(void); -struct pbuf *ip6_reass(struct pbuf *p); - -#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ - -#if LWIP_IPV6 && LWIP_IPV6_FRAG /* don't build if not configured for use in lwipopts.h */ - -#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED -#define LWIP_PBUF_CUSTOM_REF_DEFINED -/** A custom pbuf that holds a reference to another pbuf, which is freed - * when this custom pbuf is freed. This is used to create a custom PBUF_REF - * that points into the original pbuf. */ -struct pbuf_custom_ref { - /** 'base class' */ - struct pbuf_custom pc; - /** pointer to the original pbuf that is referenced */ - struct pbuf *original; -}; -#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */ - -err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest); - -#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_IP6_FRAG_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip_addr.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip_addr.h deleted file mode 100644 index 11f65d25bde7ae8c551e83cdec54aaed0d5e08dc..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ip_addr.h +++ /dev/null @@ -1,407 +0,0 @@ -/** - * @file - * IP address API (common IPv4 and IPv6) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_IP_ADDR_H -#define LWIP_HDR_IP_ADDR_H - -#include "lwip/opt.h" -#include "lwip/def.h" - -#include "lwip/ip4_addr.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @ingroup ipaddr - * IP address types for use in ip_addr_t.type member. - * @see tcp_new_ip_type(), udp_new_ip_type(), raw_new_ip_type(). - */ -enum lwip_ip_addr_type { - /** IPv4 */ - IPADDR_TYPE_V4 = 0U, - /** IPv6 */ - IPADDR_TYPE_V6 = 6U, - /** IPv4+IPv6 ("dual-stack") */ - IPADDR_TYPE_ANY = 46U -}; - -#if LWIP_IPV4 && LWIP_IPV6 -/** - * @ingroup ipaddr - * A union struct for both IP version's addresses. - * ATTENTION: watch out for its size when adding IPv6 address scope! - */ -typedef struct ip_addr { - union { - ip6_addr_t ip6; - ip4_addr_t ip4; - } u_addr; - /** @ref lwip_ip_addr_type */ - u8_t type; -} ip_addr_t; - -extern const ip_addr_t ip_addr_any_type; - -/** @ingroup ip4addr */ -#define IPADDR4_INIT(u32val) { { { { u32val, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_V4 } -/** @ingroup ip4addr */ -#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d))) -/** @ingroup ip6addr */ -#define IPADDR6_INIT(a, b, c, d) { { { { a, b, c, d } } }, IPADDR_TYPE_V6 } -/** @ingroup ip6addr */ -#define IPADDR6_INIT_HOST(a, b, c, d) { { { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } } }, IPADDR_TYPE_V6 } - -/** @ingroup ipaddr */ -#define IP_IS_ANY_TYPE_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY) -/** @ingroup ipaddr */ -#define IPADDR_ANY_TYPE_INIT { { { { 0ul, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_ANY } - -/** @ingroup ip4addr */ -#define IP_IS_V4_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4) -/** @ingroup ip6addr */ -#define IP_IS_V6_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6) -/** @ingroup ip4addr */ -#define IP_IS_V4(ipaddr) (((ipaddr) == NULL) || IP_IS_V4_VAL(*(ipaddr))) -/** @ingroup ip6addr */ -#define IP_IS_V6(ipaddr) (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr))) - -#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0) -#define IP_SET_TYPE(ipaddr, iptype) do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0) -#define IP_GET_TYPE(ipaddr) ((ipaddr)->type) - -#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr)) -#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr)) - -/** @ingroup ip6addr - * Convert generic ip address to specific protocol version - */ -#define ip_2_ip6(ipaddr) (&((ipaddr)->u_addr.ip6)) -/** @ingroup ip4addr - * Convert generic ip address to specific protocol version - */ -#define ip_2_ip4(ipaddr) (&((ipaddr)->u_addr.ip4)) - -/** @ingroup ip4addr */ -#define IP_ADDR4(ipaddr,a,b,c,d) do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \ - IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0) -/** @ingroup ip6addr */ -#define IP_ADDR6(ipaddr,i0,i1,i2,i3) do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \ - IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0) -/** @ingroup ip6addr */ -#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3)) - -/** @ingroup ipaddr */ -#define ip_addr_copy(dest, src) do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \ - ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \ - ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); }}while(0) -/** @ingroup ip6addr */ -#define ip_addr_copy_from_ip6(dest, src) do{ \ - ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0) -/** @ingroup ip4addr */ -#define ip_addr_copy_from_ip4(dest, src) do{ \ - ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); }while(0) -/** @ingroup ip4addr */ -#define ip_addr_set_ip4_u32(ipaddr, val) do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \ - IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0) -/** @ingroup ip4addr */ -#define ip_addr_get_ip4_u32(ipaddr) (((ipaddr) && IP_IS_V4(ipaddr)) ? \ - ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0) -/** @ingroup ipaddr */ -#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \ - ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \ - ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); }}while(0) -/** @ingroup ipaddr */ -#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src) -/** @ingroup ipaddr */ -#define ip_addr_set_zero(ipaddr) do{ \ - ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0) -/** @ingroup ip5addr */ -#define ip_addr_set_zero_ip4(ipaddr) do{ \ - ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0) -/** @ingroup ip6addr */ -#define ip_addr_set_zero_ip6(ipaddr) do{ \ - ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0) -/** @ingroup ipaddr */ -#define ip_addr_set_any(is_ipv6, ipaddr) do{if(is_ipv6){ \ - ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \ - ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0) -/** @ingroup ipaddr */ -#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \ - ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \ - ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0) -/** @ingroup ipaddr */ -#define ip_addr_set_hton(dest, src) do{if(IP_IS_V6(src)){ \ - ip6_addr_set_hton(ip_2_ip6(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \ - ip4_addr_set_hton(ip_2_ip4(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); }}while(0) -/** @ingroup ipaddr */ -#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \ - ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \ - ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0) -/** @ingroup ipaddr */ -#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \ - 0 : \ - ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask)) -/** @ingroup ipaddr */ -#define ip_addr_cmp(addr1, addr2) ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \ - ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \ - ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2)))) -/** @ingroup ipaddr */ -#define ip_addr_isany(ipaddr) ((IP_IS_V6(ipaddr)) ? \ - ip6_addr_isany(ip_2_ip6(ipaddr)) : \ - ip4_addr_isany(ip_2_ip4(ipaddr))) -/** @ingroup ipaddr */ -#define ip_addr_isany_val(ipaddr) ((IP_IS_V6_VAL(ipaddr)) ? \ - ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \ - ip4_addr_isany_val(*ip_2_ip4(&(ipaddr)))) -/** @ingroup ipaddr */ -#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \ - 0 : \ - ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif)) -/** @ingroup ipaddr */ -#define ip_addr_ismulticast(ipaddr) ((IP_IS_V6(ipaddr)) ? \ - ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \ - ip4_addr_ismulticast(ip_2_ip4(ipaddr))) -/** @ingroup ipaddr */ -#define ip_addr_isloopback(ipaddr) ((IP_IS_V6(ipaddr)) ? \ - ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \ - ip4_addr_isloopback(ip_2_ip4(ipaddr))) -/** @ingroup ipaddr */ -#define ip_addr_islinklocal(ipaddr) ((IP_IS_V6(ipaddr)) ? \ - ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \ - ip4_addr_islinklocal(ip_2_ip4(ipaddr))) -#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \ - ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \ - ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0) -#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \ - ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \ - ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0) -/** @ingroup ipaddr */ -#define ipaddr_ntoa(addr) (((addr) == NULL) ? "NULL" : \ - ((IP_IS_V6(addr)) ? ip6addr_ntoa(ip_2_ip6(addr)) : ip4addr_ntoa(ip_2_ip4(addr)))) -/** @ingroup ipaddr */ -#define ipaddr_ntoa_r(addr, buf, buflen) (((addr) == NULL) ? "NULL" : \ - ((IP_IS_V6(addr)) ? ip6addr_ntoa_r(ip_2_ip6(addr), buf, buflen) : ip4addr_ntoa_r(ip_2_ip4(addr), buf, buflen))) -int ipaddr_aton(const char *cp, ip_addr_t *addr); - -/** @ingroup ipaddr */ -#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX - -/** @ingroup ipaddr */ -#define ip4_2_ipv4_mapped_ipv6(ip6addr, ip4addr) do { \ - (ip6addr)->addr[3] = (ip4addr)->addr; \ - (ip6addr)->addr[2] = PP_HTONL(0x0000FFFFUL); \ - (ip6addr)->addr[1] = 0; \ - (ip6addr)->addr[0] = 0; } while(0); - -/** @ingroup ipaddr */ -#define unmap_ipv4_mapped_ipv6(ip4addr, ip6addr) \ - (ip4addr)->addr = (ip6addr)->addr[3]; - -#define IP46_ADDR_ANY(type) (((type) == IPADDR_TYPE_V6)? IP6_ADDR_ANY : IP4_ADDR_ANY) - -#else /* LWIP_IPV4 && LWIP_IPV6 */ - -#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb) 1 -#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) 1 - -#if LWIP_IPV4 - -typedef ip4_addr_t ip_addr_t; -#define IPADDR4_INIT(u32val) { u32val } -#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d))) -#define IP_IS_V4_VAL(ipaddr) 1 -#define IP_IS_V6_VAL(ipaddr) 0 -#define IP_IS_V4(ipaddr) 1 -#define IP_IS_V6(ipaddr) 0 -#define IP_IS_ANY_TYPE_VAL(ipaddr) 0 -#define IP_SET_TYPE_VAL(ipaddr, iptype) -#define IP_SET_TYPE(ipaddr, iptype) -#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V4 -#define ip_2_ip4(ipaddr) (ipaddr) -#define IP_ADDR4(ipaddr,a,b,c,d) IP4_ADDR(ipaddr,a,b,c,d) - -#define ip_addr_copy(dest, src) ip4_addr_copy(dest, src) -#define ip_addr_copy_from_ip4(dest, src) ip4_addr_copy(dest, src) -#define ip_addr_set_ip4_u32(ipaddr, val) ip4_addr_set_u32(ip_2_ip4(ipaddr), val) -#define ip_addr_get_ip4_u32(ipaddr) ip4_addr_get_u32(ip_2_ip4(ipaddr)) -#define ip_addr_set(dest, src) ip4_addr_set(dest, src) -#define ip_addr_set_ipaddr(dest, src) ip4_addr_set(dest, src) -#define ip_addr_set_zero(ipaddr) ip4_addr_set_zero(ipaddr) -#define ip_addr_set_zero_ip4(ipaddr) ip4_addr_set_zero(ipaddr) -#define ip_addr_set_any(is_ipv6, ipaddr) ip4_addr_set_any(ipaddr) -#define ip_addr_set_loopback(is_ipv6, ipaddr) ip4_addr_set_loopback(ipaddr) -#define ip_addr_set_hton(dest, src) ip4_addr_set_hton(dest, src) -#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask) -#define ip_addr_netcmp(addr1, addr2, mask) ip4_addr_netcmp(addr1, addr2, mask) -#define ip_addr_cmp(addr1, addr2) ip4_addr_cmp(addr1, addr2) -#define ip_addr_isany(ipaddr) ip4_addr_isany(ipaddr) -#define ip_addr_isany_val(ipaddr) ip4_addr_isany_val(ipaddr) -#define ip_addr_isloopback(ipaddr) ip4_addr_isloopback(ipaddr) -#define ip_addr_islinklocal(ipaddr) ip4_addr_islinklocal(ipaddr) -#define ip_addr_isbroadcast(addr, netif) ip4_addr_isbroadcast(addr, netif) -#define ip_addr_ismulticast(ipaddr) ip4_addr_ismulticast(ipaddr) -#define ip_addr_debug_print(debug, ipaddr) ip4_addr_debug_print(debug, ipaddr) -#define ip_addr_debug_print_val(debug, ipaddr) ip4_addr_debug_print_val(debug, ipaddr) -#define ipaddr_ntoa(ipaddr) ip4addr_ntoa(ipaddr) -#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip4addr_ntoa_r(ipaddr, buf, buflen) -#define ipaddr_aton(cp, addr) ip4addr_aton(cp, addr) - -#define IPADDR_STRLEN_MAX IP4ADDR_STRLEN_MAX - -#define IP46_ADDR_ANY(type) (IP4_ADDR_ANY) - -#else /* LWIP_IPV4 */ - -typedef ip6_addr_t ip_addr_t; -#define IPADDR6_INIT(a, b, c, d) { { a, b, c, d } } -#define IPADDR6_INIT_HOST(a, b, c, d) { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } } -#define IP_IS_V4_VAL(ipaddr) 0 -#define IP_IS_V6_VAL(ipaddr) 1 -#define IP_IS_V4(ipaddr) 0 -#define IP_IS_V6(ipaddr) 1 -#define IP_IS_ANY_TYPE_VAL(ipaddr) 0 -#define IP_SET_TYPE_VAL(ipaddr, iptype) -#define IP_SET_TYPE(ipaddr, iptype) -#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V6 -#define ip_2_ip6(ipaddr) (ipaddr) -#define IP_ADDR6(ipaddr,i0,i1,i2,i3) IP6_ADDR(ipaddr,i0,i1,i2,i3) -#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3)) - -#define ip_addr_copy(dest, src) ip6_addr_copy(dest, src) -#define ip_addr_copy_from_ip6(dest, src) ip6_addr_copy(dest, src) -#define ip_addr_set(dest, src) ip6_addr_set(dest, src) -#define ip_addr_set_ipaddr(dest, src) ip6_addr_set(dest, src) -#define ip_addr_set_zero(ipaddr) ip6_addr_set_zero(ipaddr) -#define ip_addr_set_zero_ip6(ipaddr) ip6_addr_set_zero(ipaddr) -#define ip_addr_set_any(is_ipv6, ipaddr) ip6_addr_set_any(ipaddr) -#define ip_addr_set_loopback(is_ipv6, ipaddr) ip6_addr_set_loopback(ipaddr) -#define ip_addr_set_hton(dest, src) ip6_addr_set_hton(dest, src) -#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target) -#define ip_addr_netcmp(addr1, addr2, mask) 0 -#define ip_addr_cmp(addr1, addr2) ip6_addr_cmp(addr1, addr2) -#define ip_addr_isany(ipaddr) ip6_addr_isany(ipaddr) -#define ip_addr_isany_val(ipaddr) ip6_addr_isany_val(ipaddr) -#define ip_addr_isloopback(ipaddr) ip6_addr_isloopback(ipaddr) -#define ip_addr_islinklocal(ipaddr) ip6_addr_islinklocal(ipaddr) -#define ip_addr_isbroadcast(addr, netif) 0 -#define ip_addr_ismulticast(ipaddr) ip6_addr_ismulticast(ipaddr) -#define ip_addr_debug_print(debug, ipaddr) ip6_addr_debug_print(debug, ipaddr) -#define ip_addr_debug_print_val(debug, ipaddr) ip6_addr_debug_print_val(debug, ipaddr) -#define ipaddr_ntoa(ipaddr) ip6addr_ntoa(ipaddr) -#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip6addr_ntoa_r(ipaddr, buf, buflen) -#define ipaddr_aton(cp, addr) ip6addr_aton(cp, addr) - -#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX - -#define IP46_ADDR_ANY(type) (IP6_ADDR_ANY) - -#endif /* LWIP_IPV4 */ -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#if LWIP_IPV4 - -extern const ip_addr_t ip_addr_any; -extern const ip_addr_t ip_addr_broadcast; - -/** - * @ingroup ip4addr - * Can be used as a fixed/const ip_addr_t - * for the IP wildcard. - * Defined to @ref IP4_ADDR_ANY when IPv4 is enabled. - * Defined to @ref IP6_ADDR_ANY in IPv6 only systems. - * Use this if you can handle IPv4 _AND_ IPv6 addresses. - * Use @ref IP4_ADDR_ANY or @ref IP6_ADDR_ANY when the IP - * type matters. - */ -#define IP_ADDR_ANY IP4_ADDR_ANY -/** - * @ingroup ip4addr - * Can be used as a fixed/const ip_addr_t - * for the IPv4 wildcard and the broadcast address - */ -#define IP4_ADDR_ANY (&ip_addr_any) -/** - * @ingroup ip4addr - * Can be used as a fixed/const ip4_addr_t - * for the wildcard and the broadcast address - */ -#define IP4_ADDR_ANY4 (ip_2_ip4(&ip_addr_any)) - -/** @ingroup ip4addr */ -#define IP_ADDR_BROADCAST (&ip_addr_broadcast) -/** @ingroup ip4addr */ -#define IP4_ADDR_BROADCAST (ip_2_ip4(&ip_addr_broadcast)) - -#endif /* LWIP_IPV4*/ - -#if LWIP_IPV6 - -extern const ip_addr_t ip6_addr_any; - -/** - * @ingroup ip6addr - * IP6_ADDR_ANY can be used as a fixed ip_addr_t - * for the IPv6 wildcard address - */ -#define IP6_ADDR_ANY (&ip6_addr_any) -/** - * @ingroup ip6addr - * IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t - * for the IPv6 wildcard address - */ -#define IP6_ADDR_ANY6 (ip_2_ip6(&ip6_addr_any)) - -#if !LWIP_IPV4 -/** IPv6-only configurations */ -#define IP_ADDR_ANY IP6_ADDR_ANY -#endif /* !LWIP_IPV4 */ - -#endif - -#if LWIP_IPV4 && LWIP_IPV6 -/** @ingroup ipaddr */ -#define IP_ANY_TYPE (&ip_addr_any_type) -#else -#define IP_ANY_TYPE IP_ADDR_ANY -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_IP_ADDR_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mem.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mem.h deleted file mode 100644 index ff208d25c327f758f7e4bde952fb667cde3f2e60..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mem.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file - * Heap API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_MEM_H -#define LWIP_HDR_MEM_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if MEM_LIBC_MALLOC - -#include "lwip/arch.h" - -typedef size_t mem_size_t; -#define MEM_SIZE_F SZT_F - -#elif MEM_USE_POOLS - -typedef u16_t mem_size_t; -#define MEM_SIZE_F U16_F - -#else - -/* MEM_SIZE would have to be aligned, but using 64000 here instead of - * 65535 leaves some room for alignment... - */ -#if MEM_SIZE > 64000L -typedef u32_t mem_size_t; -#define MEM_SIZE_F U32_F -#else -typedef u16_t mem_size_t; -#define MEM_SIZE_F U16_F -#endif /* MEM_SIZE > 64000 */ -#endif - -void mem_init(void); -void *mem_trim(void *mem, mem_size_t size); -void *mem_malloc(mem_size_t size); -void *mem_calloc(mem_size_t count, mem_size_t size); -void mem_free(void *mem); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_MEM_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/memp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/memp.h deleted file mode 100644 index 68fcd99145dd93b2b9c4319a18ade2ece2b4579e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/memp.h +++ /dev/null @@ -1,153 +0,0 @@ -/** - * @file - * Memory pool API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef LWIP_HDR_MEMP_H -#define LWIP_HDR_MEMP_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* run once with empty definition to handle all custom includes in lwippools.h */ -#define LWIP_MEMPOOL(name,num,size,desc) -#include "lwip/priv/memp_std.h" - -/** Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ -typedef enum { -#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, -#include "lwip/priv/memp_std.h" - MEMP_MAX -} memp_t; - -#include "lwip/priv/memp_priv.h" -#include "lwip/stats.h" - -extern const struct memp_desc* const memp_pools[MEMP_MAX]; - -/** - * @ingroup mempool - * Declare prototype for private memory pool if it is used in multiple files - */ -#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name - -#if MEMP_MEM_MALLOC - -#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \ - LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \ - const struct memp_desc memp_ ## name = { \ - DECLARE_LWIP_MEMPOOL_DESC(desc) \ - LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \ - LWIP_MEM_ALIGN_SIZE(size) \ - }; - -#else /* MEMP_MEM_MALLOC */ - -/** - * @ingroup mempool - * Declare a private memory pool - * Private mempools example: - * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool); - * .c: - * - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description") - * - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool); - * - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool); - * - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem); - * - * To relocate a pool, declare it as extern in cc.h. Example for GCC: - * extern u8_t __attribute__((section(".onchip_mem"))) memp_memory_my_private_pool[]; - */ -#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \ - LWIP_DECLARE_MEMORY_ALIGNED(memp_memory_ ## name ## _base, ((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))); \ - \ - LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \ - \ - static struct memp *memp_tab_ ## name; \ - \ - const struct memp_desc memp_ ## name = { \ - DECLARE_LWIP_MEMPOOL_DESC(desc) \ - LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \ - LWIP_MEM_ALIGN_SIZE(size), \ - (num), \ - memp_memory_ ## name ## _base, \ - &memp_tab_ ## name \ - }; - -#endif /* MEMP_MEM_MALLOC */ - -/** - * @ingroup mempool - * Initialize a private memory pool - */ -#define LWIP_MEMPOOL_INIT(name) memp_init_pool(&memp_ ## name) -/** - * @ingroup mempool - * Allocate from a private memory pool - */ -#define LWIP_MEMPOOL_ALLOC(name) memp_malloc_pool(&memp_ ## name) -/** - * @ingroup mempool - * Free element from a private memory pool - */ -#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x)) - -#if MEM_USE_POOLS -/** This structure is used to save the pool one element came from. - * This has to be defined here as it is required for pool size calculation. */ -struct memp_malloc_helper -{ - memp_t poolnr; -#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) - u16_t size; -#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */ -}; -#endif /* MEM_USE_POOLS */ - -void memp_init(void); - -#if MEMP_OVERFLOW_CHECK -void *memp_malloc_fn(memp_t type, const char* file, const int line); -#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) -#else -void *memp_malloc(memp_t type); -#endif -void memp_free(memp_t type, void *mem); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_MEMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mld6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mld6.h deleted file mode 100644 index 7fa0797f272c93bbeb0ff051b82c3001aacd9600..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/mld6.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * @file - * - * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710. - * No support for MLDv2. - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_MLD6_H -#define LWIP_HDR_MLD6_H - -#include "lwip/opt.h" - -#if LWIP_IPV6_MLD && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** MLD group */ -struct mld_group { - /** next link */ - struct mld_group *next; - /** multicast address */ - ip6_addr_t group_address; - /** signifies we were the last person to report */ - u8_t last_reporter_flag; - /** current state of the group */ - u8_t group_state; - /** timer for reporting */ - u16_t timer; - /** counter of simultaneous uses */ - u8_t use; -}; - -#define MLD6_TMR_INTERVAL 100 /* Milliseconds */ - -err_t mld6_stop(struct netif *netif); -void mld6_report_groups(struct netif *netif); -void mld6_tmr(void); -struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr); -void mld6_input(struct pbuf *p, struct netif *inp); -err_t mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr); -err_t mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr); -err_t mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr); -err_t mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr); - -/** @ingroup mld6 - * Get list head of MLD6 groups for netif. - * Note: The allnodes group IP is NOT in the list, since it must always - * be received for correct IPv6 operation. - * @see @ref netif_set_mld_mac_filter() - */ -#define netif_mld6_data(netif) ((struct mld_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6)) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */ - -#endif /* LWIP_HDR_MLD6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/nd6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/nd6.h deleted file mode 100644 index 8204fa4cce27adc71fe252b0b566daa6f4b2c9b8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/nd6.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * - * Neighbor discovery and stateless address autoconfiguration for IPv6. - * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 - * (Address autoconfiguration). - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_ND6_H -#define LWIP_HDR_ND6_H - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip6_addr.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** 1 second period */ -#define ND6_TMR_INTERVAL 1000 - -struct pbuf; -struct netif; - -void nd6_tmr(void); -void nd6_input(struct pbuf *p, struct netif *inp); -void nd6_clear_destination_cache(void); -struct netif *nd6_find_route(const ip6_addr_t *ip6addr); -err_t nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp); -u16_t nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif); -#if LWIP_ND6_TCP_REACHABILITY_HINTS -void nd6_reachability_hint(const ip6_addr_t *ip6addr); -#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ -void nd6_cleanup_netif(struct netif *netif); -#if LWIP_IPV6_MLD -void nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state); -#endif /* LWIP_IPV6_MLD */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 */ - -#endif /* LWIP_HDR_ND6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netbuf.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netbuf.h deleted file mode 100644 index e6865f80f94d3f5e557ec64e9775013dda7e5879..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netbuf.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * netbuf API (for netconn API) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_NETBUF_H -#define LWIP_HDR_NETBUF_H - -#include "lwip/opt.h" - -#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ -/* Note: Netconn API is always available when sockets are enabled - - * sockets are implemented on top of them */ - -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** This netbuf has dest-addr/port set */ -#define NETBUF_FLAG_DESTADDR 0x01 -/** This netbuf includes a checksum */ -#define NETBUF_FLAG_CHKSUM 0x02 - -/** "Network buffer" - contains data and addressing info */ -struct netbuf { - struct pbuf *p, *ptr; - ip_addr_t addr; - u16_t port; -#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY -#if LWIP_CHECKSUM_ON_COPY - u8_t flags; -#endif /* LWIP_CHECKSUM_ON_COPY */ - u16_t toport_chksum; -#if LWIP_NETBUF_RECVINFO - ip_addr_t toaddr; -#endif /* LWIP_NETBUF_RECVINFO */ -#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */ -}; - -/* Network buffer functions: */ -struct netbuf * netbuf_new (void); -void netbuf_delete (struct netbuf *buf); -void * netbuf_alloc (struct netbuf *buf, u16_t size); -void netbuf_free (struct netbuf *buf); -err_t netbuf_ref (struct netbuf *buf, - const void *dataptr, u16_t size); -void netbuf_chain (struct netbuf *head, struct netbuf *tail); - -err_t netbuf_data (struct netbuf *buf, - void **dataptr, u16_t *len); -s8_t netbuf_next (struct netbuf *buf); -void netbuf_first (struct netbuf *buf); - - -#define netbuf_copy_partial(buf, dataptr, len, offset) \ - pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) -#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) -#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) -#define netbuf_len(buf) ((buf)->p->tot_len) -#define netbuf_fromaddr(buf) (&((buf)->addr)) -#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr) -#define netbuf_fromport(buf) ((buf)->port) -#if LWIP_NETBUF_RECVINFO -#define netbuf_destaddr(buf) (&((buf)->toaddr)) -#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr) -#if LWIP_CHECKSUM_ON_COPY -#define netbuf_destport(buf) (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0) -#else /* LWIP_CHECKSUM_ON_COPY */ -#define netbuf_destport(buf) ((buf)->toport_chksum) -#endif /* LWIP_CHECKSUM_ON_COPY */ -#endif /* LWIP_NETBUF_RECVINFO */ -#if LWIP_CHECKSUM_ON_COPY -#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \ - (buf)->toport_chksum = chksum; } while(0) -#endif /* LWIP_CHECKSUM_ON_COPY */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETCONN || LWIP_SOCKET */ - -#endif /* LWIP_HDR_NETBUF_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netdb.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netdb.h deleted file mode 100644 index d3d15dfac5ad0b1eb44ba3aa7043cd9fe84831ab..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netdb.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * @file - * NETDB API (sockets) - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_NETDB_H -#define LWIP_HDR_NETDB_H - -#include "lwip/opt.h" - -#if LWIP_DNS && LWIP_SOCKET - -#include "lwip/arch.h" -#include "lwip/inet.h" -#include "lwip/sockets.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* some rarely used options */ -#ifndef LWIP_DNS_API_DECLARE_H_ERRNO -#define LWIP_DNS_API_DECLARE_H_ERRNO 1 -#endif - -#ifndef LWIP_DNS_API_DEFINE_ERRORS -#define LWIP_DNS_API_DEFINE_ERRORS 1 -#endif - -#ifndef LWIP_DNS_API_DEFINE_FLAGS -#define LWIP_DNS_API_DEFINE_FLAGS 1 -#endif - -#ifndef LWIP_DNS_API_DECLARE_STRUCTS -#define LWIP_DNS_API_DECLARE_STRUCTS 1 -#endif - -#if LWIP_DNS_API_DEFINE_ERRORS -/** Errors used by the DNS API functions, h_errno can be one of them */ -#define EAI_NONAME 200 -#define EAI_SERVICE 201 -#define EAI_FAIL 202 -#define EAI_MEMORY 203 -#define EAI_FAMILY 204 - -#define HOST_NOT_FOUND 210 -#define NO_DATA 211 -#define NO_RECOVERY 212 -#define TRY_AGAIN 213 -#endif /* LWIP_DNS_API_DEFINE_ERRORS */ - -#if LWIP_DNS_API_DEFINE_FLAGS -/* input flags for struct addrinfo */ -#define AI_PASSIVE 0x01 -#define AI_CANONNAME 0x02 -#define AI_NUMERICHOST 0x04 -#define AI_NUMERICSERV 0x08 -#define AI_V4MAPPED 0x10 -#define AI_ALL 0x20 -#define AI_ADDRCONFIG 0x40 -#endif /* LWIP_DNS_API_DEFINE_FLAGS */ - -#if LWIP_DNS_API_DECLARE_STRUCTS -struct hostent { - char *h_name; /* Official name of the host. */ - char **h_aliases; /* A pointer to an array of pointers to alternative host names, - terminated by a null pointer. */ - int h_addrtype; /* Address type. */ - int h_length; /* The length, in bytes, of the address. */ - char **h_addr_list; /* A pointer to an array of pointers to network addresses (in - network byte order) for the host, terminated by a null pointer. */ -#define h_addr h_addr_list[0] /* for backward compatibility */ -}; - -struct addrinfo { - int ai_flags; /* Input flags. */ - int ai_family; /* Address family of socket. */ - int ai_socktype; /* Socket type. */ - int ai_protocol; /* Protocol of socket. */ - socklen_t ai_addrlen; /* Length of socket address. */ - struct sockaddr *ai_addr; /* Socket address of socket. */ - char *ai_canonname; /* Canonical name of service location. */ - struct addrinfo *ai_next; /* Pointer to next in list. */ -}; -#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ - -#define NETDB_ELEM_SIZE (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1) - -#if LWIP_DNS_API_DECLARE_H_ERRNO -/* application accessible error code set by the DNS API functions */ -extern int h_errno; -#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ - -struct hostent *lwip_gethostbyname(const char *name); -int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, - size_t buflen, struct hostent **result, int *h_errnop); -void lwip_freeaddrinfo(struct addrinfo *ai); -int lwip_getaddrinfo(const char *nodename, - const char *servname, - const struct addrinfo *hints, - struct addrinfo **res); - -#if LWIP_COMPAT_SOCKETS -/** @ingroup netdbapi */ -#define gethostbyname(name) lwip_gethostbyname(name) -/** @ingroup netdbapi */ -#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ - lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) -/** @ingroup netdbapi */ -#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo) -/** @ingroup netdbapi */ -#define getaddrinfo(nodname, servname, hints, res) \ - lwip_getaddrinfo(nodname, servname, hints, res) -#endif /* LWIP_COMPAT_SOCKETS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_DNS && LWIP_SOCKET */ - -#endif /* LWIP_HDR_NETDB_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netif.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netif.h deleted file mode 100644 index 67a2d24de8bc556cc58b957b21728eb5c6382f8c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netif.h +++ /dev/null @@ -1,474 +0,0 @@ -/** - * @file - * netif API (to be used from TCPIP thread) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_NETIF_H -#define LWIP_HDR_NETIF_H - -#include "lwip/opt.h" - -#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) - -#include "lwip/err.h" - -#include "lwip/ip_addr.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/stats.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Throughout this file, IP addresses are expected to be in - * the same byte order as in IP_PCB. */ - -/** Must be the maximum of all used hardware address lengths - across all types of interfaces in use. - This does not have to be changed, normally. */ -#ifndef NETIF_MAX_HWADDR_LEN -#define NETIF_MAX_HWADDR_LEN 6U -#endif - -/** - * @defgroup netif_flags Flags - * @ingroup netif - * @{ - */ - -/** Whether the network interface is 'up'. This is - * a software flag used to control whether this network - * interface is enabled and processes traffic. - * It must be set by the startup code before this netif can be used - * (also for dhcp/autoip). - */ -#define NETIF_FLAG_UP 0x01U -/** If set, the netif has broadcast capability. - * Set by the netif driver in its init function. */ -#define NETIF_FLAG_BROADCAST 0x02U -/** If set, the interface has an active link - * (set by the network interface driver). - * Either set by the netif driver in its init function (if the link - * is up at that time) or at a later point once the link comes up - * (if link detection is supported by the hardware). */ -#define NETIF_FLAG_LINK_UP 0x04U -/** If set, the netif is an ethernet device using ARP. - * Set by the netif driver in its init function. - * Used to check input packet types and use of DHCP. */ -#define NETIF_FLAG_ETHARP 0x08U -/** If set, the netif is an ethernet device. It might not use - * ARP or TCP/IP if it is used for PPPoE only. - */ -#define NETIF_FLAG_ETHERNET 0x10U -/** If set, the netif has IGMP capability. - * Set by the netif driver in its init function. */ -#define NETIF_FLAG_IGMP 0x20U -/** If set, the netif has MLD6 capability. - * Set by the netif driver in its init function. */ -#define NETIF_FLAG_MLD6 0x40U - -/** - * @} - */ - -enum lwip_internal_netif_client_data_index -{ -#if LWIP_DHCP - LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, -#endif -#if LWIP_AUTOIP - LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, -#endif -#if LWIP_IGMP - LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, -#endif -#if LWIP_IPV6_MLD - LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, -#endif - LWIP_NETIF_CLIENT_DATA_INDEX_MAX -}; - -#if LWIP_CHECKSUM_CTRL_PER_NETIF -#define NETIF_CHECKSUM_GEN_IP 0x0001 -#define NETIF_CHECKSUM_GEN_UDP 0x0002 -#define NETIF_CHECKSUM_GEN_TCP 0x0004 -#define NETIF_CHECKSUM_GEN_ICMP 0x0008 -#define NETIF_CHECKSUM_GEN_ICMP6 0x0010 -#define NETIF_CHECKSUM_CHECK_IP 0x0100 -#define NETIF_CHECKSUM_CHECK_UDP 0x0200 -#define NETIF_CHECKSUM_CHECK_TCP 0x0400 -#define NETIF_CHECKSUM_CHECK_ICMP 0x0800 -#define NETIF_CHECKSUM_CHECK_ICMP6 0x1000 -#define NETIF_CHECKSUM_ENABLE_ALL 0xFFFF -#define NETIF_CHECKSUM_DISABLE_ALL 0x0000 -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ - -struct netif; - -/** MAC Filter Actions, these are passed to a netif's igmp_mac_filter or - * mld_mac_filter callback function. */ -enum netif_mac_filter_action { - /** Delete a filter entry */ - NETIF_DEL_MAC_FILTER = 0, - /** Add a filter entry */ - NETIF_ADD_MAC_FILTER = 1 -}; - -/** Function prototype for netif init functions. Set up flags and output/linkoutput - * callback functions in this function. - * - * @param netif The netif to initialize - */ -typedef err_t (*netif_init_fn)(struct netif *netif); -/** Function prototype for netif->input functions. This function is saved as 'input' - * callback function in the netif struct. Call it when a packet has been received. - * - * @param p The received packet, copied into a pbuf - * @param inp The netif which received the packet - */ -typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp); - -#if LWIP_IPV4 -/** Function prototype for netif->output functions. Called by lwIP when a packet - * shall be sent. For ethernet netif, set this to 'etharp_output' and set - * 'linkoutput'. - * - * @param netif The netif which shall send a packet - * @param p The packet to send (p->payload points to IP header) - * @param ipaddr The IP address to which the packet shall be sent - */ -typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p, - const ip4_addr_t *ipaddr); -#endif /* LWIP_IPV4*/ - -#if LWIP_IPV6 -/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet - * shall be sent. For ethernet netif, set this to 'ethip6_output' and set - * 'linkoutput'. - * - * @param netif The netif which shall send a packet - * @param p The packet to send (p->payload points to IP header) - * @param ipaddr The IPv6 address to which the packet shall be sent - */ -typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p, - const ip6_addr_t *ipaddr); -#endif /* LWIP_IPV6 */ - -/** Function prototype for netif->linkoutput functions. Only used for ethernet - * netifs. This function is called by ARP when a packet shall be sent. - * - * @param netif The netif which shall send a packet - * @param p The packet to send (raw ethernet packet) - */ -typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p); -/** Function prototype for netif status- or link-callback functions. */ -typedef void (*netif_status_callback_fn)(struct netif *netif); -#if LWIP_IPV4 && LWIP_IGMP -/** Function prototype for netif igmp_mac_filter functions */ -typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif, - const ip4_addr_t *group, enum netif_mac_filter_action action); -#endif /* LWIP_IPV4 && LWIP_IGMP */ -#if LWIP_IPV6 && LWIP_IPV6_MLD -/** Function prototype for netif mld_mac_filter functions */ -typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif, - const ip6_addr_t *group, enum netif_mac_filter_action action); -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ - -#if LWIP_DHCP || LWIP_AUTOIP || LWIP_IGMP || LWIP_IPV6_MLD || (LWIP_NUM_NETIF_CLIENT_DATA > 0) -u8_t netif_alloc_client_data_id(void); -/** @ingroup netif_cd - * Set client data. Obtain ID from netif_alloc_client_data_id(). - */ -#define netif_set_client_data(netif, id, data) netif_get_client_data(netif, id) = (data) -/** @ingroup netif_cd - * Get client data. Obtain ID from netif_alloc_client_data_id(). - */ -#define netif_get_client_data(netif, id) (netif)->client_data[(id)] -#endif /* LWIP_DHCP || LWIP_AUTOIP || (LWIP_NUM_NETIF_CLIENT_DATA > 0) */ - -/** Generic data structure used for all lwIP network interfaces. - * The following fields should be filled in by the initialization - * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ -struct netif { - /** pointer to next in linked list */ - struct netif *next; - -#if LWIP_IPV4 - /** IP address configuration in network byte order */ - ip_addr_t ip_addr; - ip_addr_t netmask; - ip_addr_t gw; -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - /** Array of IPv6 addresses for this netif. */ - ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES]; - /** The state of each IPv6 address (Tentative, Preferred, etc). - * @see ip6_addr.h */ - u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES]; -#endif /* LWIP_IPV6 */ - /** This function is called by the network device driver - * to pass a packet up the TCP/IP stack. */ - netif_input_fn input; -#if LWIP_IPV4 - /** This function is called by the IP module when it wants - * to send a packet on the interface. This function typically - * first resolves the hardware address, then sends the packet. - * For ethernet physical layer, this is usually etharp_output() */ - netif_output_fn output; -#endif /* LWIP_IPV4 */ - /** This function is called by ethernet_output() when it wants - * to send a packet on the interface. This function outputs - * the pbuf as-is on the link medium. */ - netif_linkoutput_fn linkoutput; -#if LWIP_IPV6 - /** This function is called by the IPv6 module when it wants - * to send a packet on the interface. This function typically - * first resolves the hardware address, then sends the packet. - * For ethernet physical layer, this is usually ethip6_output() */ - netif_output_ip6_fn output_ip6; -#endif /* LWIP_IPV6 */ -#if LWIP_NETIF_STATUS_CALLBACK - /** This function is called when the netif state is set to up or down - */ - netif_status_callback_fn status_callback; -#endif /* LWIP_NETIF_STATUS_CALLBACK */ -#if LWIP_NETIF_LINK_CALLBACK - /** This function is called when the netif link is set to up or down - */ - netif_status_callback_fn link_callback; -#endif /* LWIP_NETIF_LINK_CALLBACK */ -#if LWIP_NETIF_REMOVE_CALLBACK - /** This function is called when the netif has been removed */ - netif_status_callback_fn remove_callback; -#endif /* LWIP_NETIF_REMOVE_CALLBACK */ - /** This field can be set by the device driver and could point - * to state information for the device. */ - void *state; -#ifdef netif_get_client_data - void* client_data[LWIP_NETIF_CLIENT_DATA_INDEX_MAX + LWIP_NUM_NETIF_CLIENT_DATA]; -#endif -#if LWIP_IPV6_AUTOCONFIG - /** is this netif enabled for IPv6 autoconfiguration */ - u8_t ip6_autoconfig_enabled; -#endif /* LWIP_IPV6_AUTOCONFIG */ -#if LWIP_IPV6_SEND_ROUTER_SOLICIT - /** Number of Router Solicitation messages that remain to be sent. */ - u8_t rs_count; -#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ -#if LWIP_NETIF_HOSTNAME - /* the hostname for this netif, NULL is a valid value */ - const char* hostname; -#endif /* LWIP_NETIF_HOSTNAME */ -#if LWIP_CHECKSUM_CTRL_PER_NETIF - u16_t chksum_flags; -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ - /** maximum transfer unit (in bytes) */ - u16_t mtu; - /** number of bytes used in hwaddr */ - u8_t hwaddr_len; - /** link level hardware address of this interface */ - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - /** flags (@see @ref netif_flags) */ - u8_t flags; - /** descriptive abbreviation */ - char name[2]; - /** number of this interface */ - u8_t num; -#if MIB2_STATS - /** link type (from "snmp_ifType" enum from snmp_mib2.h) */ - u8_t link_type; - /** (estimate) link speed */ - u32_t link_speed; - /** timestamp at last change made (up/down) */ - u32_t ts; - /** counters */ - struct stats_mib2_netif_ctrs mib2_counters; -#endif /* MIB2_STATS */ -#if LWIP_IPV4 && LWIP_IGMP - /** This function could be called to add or delete an entry in the multicast - filter table of the ethernet MAC.*/ - netif_igmp_mac_filter_fn igmp_mac_filter; -#endif /* LWIP_IPV4 && LWIP_IGMP */ -#if LWIP_IPV6 && LWIP_IPV6_MLD - /** This function could be called to add or delete an entry in the IPv6 multicast - filter table of the ethernet MAC. */ - netif_mld_mac_filter_fn mld_mac_filter; -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ -#if LWIP_NETIF_HWADDRHINT - u8_t *addr_hint; -#endif /* LWIP_NETIF_HWADDRHINT */ -#if ENABLE_LOOPBACK - /* List of packets to be queued for ourselves. */ - struct pbuf *loop_first; - struct pbuf *loop_last; -#if LWIP_LOOPBACK_MAX_PBUFS - u16_t loop_cnt_current; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ -#endif /* ENABLE_LOOPBACK */ -}; - -#if LWIP_CHECKSUM_CTRL_PER_NETIF -#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \ - (netif)->chksum_flags = chksumflags; } while(0) -#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0)) -#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */ -#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) -#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) -#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ - -/** The list of network interfaces. */ -extern struct netif *netif_list; -/** The default network interface. */ -extern struct netif *netif_default; - -void netif_init(void); - -struct netif *netif_add(struct netif *netif, -#if LWIP_IPV4 - const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, -#endif /* LWIP_IPV4 */ - void *state, netif_init_fn init, netif_input_fn input); -#if LWIP_IPV4 -void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, - const ip4_addr_t *gw); -#endif /* LWIP_IPV4 */ -void netif_remove(struct netif * netif); - -/* Returns a network interface given its name. The name is of the form - "et0", where the first two letters are the "name" field in the - netif structure, and the digit is in the num field in the same - structure. */ -struct netif *netif_find(const char *name); - -void netif_set_default(struct netif *netif); - -#if LWIP_IPV4 -void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr); -void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask); -void netif_set_gw(struct netif *netif, const ip4_addr_t *gw); -/** @ingroup netif_ip4 */ -#define netif_ip4_addr(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr))) -/** @ingroup netif_ip4 */ -#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask))) -/** @ingroup netif_ip4 */ -#define netif_ip4_gw(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw))) -/** @ingroup netif_ip4 */ -#define netif_ip_addr4(netif) ((const ip_addr_t*)&((netif)->ip_addr)) -/** @ingroup netif_ip4 */ -#define netif_ip_netmask4(netif) ((const ip_addr_t*)&((netif)->netmask)) -/** @ingroup netif_ip4 */ -#define netif_ip_gw4(netif) ((const ip_addr_t*)&((netif)->gw)) -#endif /* LWIP_IPV4 */ - -void netif_set_up(struct netif *netif); -void netif_set_down(struct netif *netif); -/** @ingroup netif - * Ask if an interface is up - */ -#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0) - -#if LWIP_NETIF_STATUS_CALLBACK -void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback); -#endif /* LWIP_NETIF_STATUS_CALLBACK */ -#if LWIP_NETIF_REMOVE_CALLBACK -void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback); -#endif /* LWIP_NETIF_REMOVE_CALLBACK */ - -void netif_set_link_up(struct netif *netif); -void netif_set_link_down(struct netif *netif); -/** Ask if a link is up */ -#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0) - -#if LWIP_NETIF_LINK_CALLBACK -void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback); -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -#if LWIP_NETIF_HOSTNAME -/** @ingroup netif */ -#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0) -/** @ingroup netif */ -#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL) -#endif /* LWIP_NETIF_HOSTNAME */ - -#if LWIP_IGMP -/** @ingroup netif */ -#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0) -#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL) -#endif /* LWIP_IGMP */ - -#if LWIP_IPV6 && LWIP_IPV6_MLD -/** @ingroup netif */ -#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0) -#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL) -#define netif_mld_mac_filter(netif, addr, action) do { if((netif) && (netif)->mld_mac_filter) { (netif)->mld_mac_filter((netif), (addr), (action)); }}while(0) -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ - -#if ENABLE_LOOPBACK -err_t netif_loop_output(struct netif *netif, struct pbuf *p); -void netif_poll(struct netif *netif); -#if !LWIP_NETIF_LOOPBACK_MULTITHREADING -void netif_poll_all(void); -#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ - -err_t netif_input(struct pbuf *p, struct netif *inp); - -#if LWIP_IPV6 -/** @ingroup netif_ip6 */ -#define netif_ip_addr6(netif, i) ((const ip_addr_t*)(&((netif)->ip6_addr[i]))) -/** @ingroup netif_ip6 */ -#define netif_ip6_addr(netif, i) ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i]))) -void netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6); -void netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3); -#define netif_ip6_addr_state(netif, i) ((netif)->ip6_addr_state[i]) -void netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state); -s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr); -void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit); -err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx); -#define netif_set_ip6_autoconfig_enabled(netif, action) do { if(netif) { (netif)->ip6_autoconfig_enabled = (action); }}while(0) -#endif /* LWIP_IPV6 */ - -#if LWIP_NETIF_HWADDRHINT -#define NETIF_SET_HWADDRHINT(netif, hint) ((netif)->addr_hint = (hint)) -#else /* LWIP_NETIF_HWADDRHINT */ -#define NETIF_SET_HWADDRHINT(netif, hint) -#endif /* LWIP_NETIF_HWADDRHINT */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_NETIF_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netifapi.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netifapi.h deleted file mode 100644 index 27a8d118bf7c4377bb7afea961f7e2a18321b28f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/netifapi.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file - * netif API (to be used from non-TCPIP threads) - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ -#ifndef LWIP_HDR_NETIFAPI_H -#define LWIP_HDR_NETIFAPI_H - -#include "lwip/opt.h" - -#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sys.h" -#include "lwip/netif.h" -#include "lwip/dhcp.h" -#include "lwip/priv/tcpip_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_MPU_COMPATIBLE -#define NETIFAPI_IPADDR_DEF(type, m) type m -#else /* LWIP_MPU_COMPATIBLE */ -#define NETIFAPI_IPADDR_DEF(type, m) const type * m -#endif /* LWIP_MPU_COMPATIBLE */ - -typedef void (*netifapi_void_fn)(struct netif *netif); -typedef err_t (*netifapi_errt_fn)(struct netif *netif); - -struct netifapi_msg { - struct tcpip_api_call_data call; - struct netif *netif; - union { - struct { -#if LWIP_IPV4 - NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr); - NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask); - NETIFAPI_IPADDR_DEF(ip4_addr_t, gw); -#endif /* LWIP_IPV4 */ - void *state; - netif_init_fn init; - netif_input_fn input; - } add; - struct { - netifapi_void_fn voidfunc; - netifapi_errt_fn errtfunc; - } common; - } msg; -}; - - -/* API for application */ -err_t netifapi_netif_add(struct netif *netif, -#if LWIP_IPV4 - const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, -#endif /* LWIP_IPV4 */ - void *state, netif_init_fn init, netif_input_fn input); - -#if LWIP_IPV4 -err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, - const ip4_addr_t *netmask, const ip4_addr_t *gw); -#endif /* LWIP_IPV4*/ - -err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc, - netifapi_errt_fn errtfunc); - -/** @ingroup netifapi_netif */ -#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) -/** @ingroup netifapi_netif */ -#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) -/** @ingroup netifapi_netif */ -#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) -/** @ingroup netifapi_netif */ -#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) -/** @ingroup netifapi_netif */ -#define netifapi_netif_set_link_up(n) netifapi_netif_common(n, netif_set_link_up, NULL) -/** @ingroup netifapi_netif */ -#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL) - -/** - * @defgroup netifapi_dhcp4 DHCPv4 - * @ingroup netifapi - * To be called from non-TCPIP threads - */ -/** @ingroup netifapi_dhcp4 */ -#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) -/** @ingroup netifapi_dhcp4 */ -#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) -/** @ingroup netifapi_dhcp4 */ -#define netifapi_dhcp_inform(n) netifapi_netif_common(n, dhcp_inform, NULL) -/** @ingroup netifapi_dhcp4 */ -#define netifapi_dhcp_renew(n) netifapi_netif_common(n, NULL, dhcp_renew) -/** @ingroup netifapi_dhcp4 */ -#define netifapi_dhcp_release(n) netifapi_netif_common(n, NULL, dhcp_release) - -/** - * @defgroup netifapi_autoip AUTOIP - * @ingroup netifapi - * To be called from non-TCPIP threads - */ -/** @ingroup netifapi_autoip */ -#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) -/** @ingroup netifapi_autoip */ -#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETIF_API */ - -#endif /* LWIP_HDR_NETIFAPI_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/opt.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/opt.h deleted file mode 100644 index d27e43b9bf277441c5cfe3862fe0fdf2fd194373..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/opt.h +++ /dev/null @@ -1,2876 +0,0 @@ -/** - * @file - * - * lwIP Options Configuration - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * NOTE: || defined __DOXYGEN__ is a workaround for doxygen bug - - * without this, doxygen does not see the actual #define - */ - -#if !defined LWIP_HDR_OPT_H -#define LWIP_HDR_OPT_H - -/* - * Include user defined options first. Anything not defined in these files - * will be set to standard values. Override anything you don't like! - */ -#include "lwipopts.h" -#include "lwip/debug.h" - -/** - * @defgroup lwip_opts Options (lwipopts.h) - * @ingroup lwip - * - * @defgroup lwip_opts_debug Debugging - * @ingroup lwip_opts - * - * @defgroup lwip_opts_infrastructure Infrastructure - * @ingroup lwip_opts - * - * @defgroup lwip_opts_callback Callback-style APIs - * @ingroup lwip_opts - * - * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs - * @ingroup lwip_opts - */ - - /* - ------------------------------------ - -------------- NO SYS -------------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_nosys NO_SYS - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or - * mboxes). This means threaded APIs cannot be used (socket, netconn, - * i.e. everything in the 'api' folder), only the callback-style raw API is - * available (and you have to watch out for yourself that you don't access - * lwIP functions/structures from more than one context at a time!) - */ -#if !defined NO_SYS || defined __DOXYGEN__ -#define NO_SYS 0 -#endif -/** - * @} - */ - -/** - * @defgroup lwip_opts_timers Timers - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers. - * (the array of lwip-internal cyclic timers is still provided) - * (check NO_SYS_NO_TIMERS for compatibility to old versions) - */ -#if !defined LWIP_TIMERS || defined __DOXYGEN__ -#ifdef NO_SYS_NO_TIMERS -#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) -#else -#define LWIP_TIMERS 1 -#endif -#endif - -/** - * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation. - * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers - * are still included, but the implementation is not. The following functions - * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(), - * sys_timeouts_mbox_fetch() - */ -#if !defined LWIP_TIMERS_CUSTOM || defined __DOXYGEN__ -#define LWIP_TIMERS_CUSTOM 0 -#endif -/** - * @} - */ - -/** - * @defgroup lwip_opts_memcpy memcpy - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * MEMCPY: override this if you have a faster implementation at hand than the - * one included in your C library - */ -#if !defined MEMCPY || defined __DOXYGEN__ -#define MEMCPY(dst,src,len) memcpy(dst,src,len) -#endif - -/** - * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a - * call to memcpy() if the length is known at compile time and is small. - */ -#if !defined SMEMCPY || defined __DOXYGEN__ -#define SMEMCPY(dst,src,len) memcpy(dst,src,len) -#endif -/** - * @} - */ - -/* - ------------------------------------ - ----------- Core locking ----------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_lock Core locking and MPU - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * LWIP_MPU_COMPATIBLE: enables special memory management mechanism - * which makes lwip able to work on MPU (Memory Protection Unit) system - * by not passing stack-pointers to other threads - * (this decreases performance as memory is allocated from pools instead - * of keeping it on the stack) - */ -#if !defined LWIP_MPU_COMPATIBLE || defined __DOXYGEN__ -#define LWIP_MPU_COMPATIBLE 0 -#endif - -/** - * LWIP_TCPIP_CORE_LOCKING - * Creates a global mutex that is held during TCPIP thread operations. - * Can be locked by client code to perform lwIP operations without changing - * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and - * UNLOCK_TCPIP_CORE(). - * Your system should provide mutexes supporting priority inversion to use this. - */ -#if !defined LWIP_TCPIP_CORE_LOCKING || defined __DOXYGEN__ -#define LWIP_TCPIP_CORE_LOCKING 1 -#endif - -/** - * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled, - * this lets tcpip_input() grab the mutex for input packets as well, - * instead of allocating a message and passing it to tcpip_thread. - * - * ATTENTION: this does not work when tcpip_input() is called from - * interrupt context! - */ -#if !defined LWIP_TCPIP_CORE_LOCKING_INPUT || defined __DOXYGEN__ -#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 -#endif - -/** - * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt - * protection) for certain critical regions during buffer allocation, deallocation - * and memory allocation and deallocation. - * ATTENTION: This is required when using lwIP from more than one context! If - * you disable this, you must be sure what you are doing! - */ -#if !defined SYS_LIGHTWEIGHT_PROT || defined __DOXYGEN__ -#define SYS_LIGHTWEIGHT_PROT 1 -#endif -/** - * @} - */ - -/* - ------------------------------------ - ---------- Memory options ---------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_mem Heap and memory pools - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library - * instead of the lwip internal allocator. Can save code size if you - * already use it. - */ -#if !defined MEM_LIBC_MALLOC || defined __DOXYGEN__ -#define MEM_LIBC_MALLOC 0 -#endif - -/** - * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. - * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution - * speed (heap alloc can be much slower than pool alloc) and usage from interrupts - * (especially if your netif driver allocates PBUF_POOL pbufs for received frames - * from interrupt)! - * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools, - * not only for internal pools defined in memp_std.h)! - */ -#if !defined MEMP_MEM_MALLOC || defined __DOXYGEN__ -#define MEMP_MEM_MALLOC 0 -#endif - -/** - * MEM_ALIGNMENT: should be set to the alignment of the CPU - * 4 byte alignment -> \#define MEM_ALIGNMENT 4 - * 2 byte alignment -> \#define MEM_ALIGNMENT 2 - */ -#if !defined MEM_ALIGNMENT || defined __DOXYGEN__ -#define MEM_ALIGNMENT 1 -#endif - -/** - * MEM_SIZE: the size of the heap memory. If the application will send - * a lot of data that needs to be copied, this should be set high. - */ -#if !defined MEM_SIZE || defined __DOXYGEN__ -#define MEM_SIZE 1600 -#endif - -/** - * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable - * amount of bytes before and after each memp element in every pool and fills - * it with a prominent default value. - * MEMP_OVERFLOW_CHECK == 0 no checking - * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed - * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time - * memp_malloc() or memp_free() is called (useful but slow!) - */ -#if !defined MEMP_OVERFLOW_CHECK || defined __DOXYGEN__ -#define MEMP_OVERFLOW_CHECK 0 -#endif - -/** - * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make - * sure that there are no cycles in the linked lists. - */ -#if !defined MEMP_SANITY_CHECK || defined __DOXYGEN__ -#define MEMP_SANITY_CHECK 0 -#endif - -/** - * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set - * of memory pools of various sizes. When mem_malloc is called, an element of - * the smallest pool that can provide the length needed is returned. - * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. - */ -#if !defined MEM_USE_POOLS || defined __DOXYGEN__ -#define MEM_USE_POOLS 0 -#endif - -/** - * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next - * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more - * reliable. */ -#if !defined MEM_USE_POOLS_TRY_BIGGER_POOL || defined __DOXYGEN__ -#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 -#endif - -/** - * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h - * that defines additional pools beyond the "standard" ones required - * by lwIP. If you set this to 1, you must have lwippools.h in your - * include path somewhere. - */ -#if !defined MEMP_USE_CUSTOM_POOLS || defined __DOXYGEN__ -#define MEMP_USE_CUSTOM_POOLS 0 -#endif - -/** - * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from - * interrupt context (or another context that doesn't allow waiting for a - * semaphore). - * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, - * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs - * with each loop so that mem_free can run. - * - * ATTENTION: As you can see from the above description, this leads to dis-/ - * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc - * can need longer. - * - * If you don't want that, at least for NO_SYS=0, you can still use the following - * functions to enqueue a deallocation call which then runs in the tcpip_thread - * context: - * - pbuf_free_callback(p); - * - mem_free_callback(m); - */ -#if !defined LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT || defined __DOXYGEN__ -#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 -#endif -/** - * @} - */ - -/* - ------------------------------------------------ - ---------- Internal Memory Pool Sizes ---------- - ------------------------------------------------ -*/ -/** - * @defgroup lwip_opts_memp Internal memory pools - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). - * If the application sends a lot of data out of ROM (or other static memory), - * this should be set high. - */ -#if !defined MEMP_NUM_PBUF || defined __DOXYGEN__ -#define MEMP_NUM_PBUF 16 -#endif - -/** - * MEMP_NUM_RAW_PCB: Number of raw connection PCBs - * (requires the LWIP_RAW option) - */ -#if !defined MEMP_NUM_RAW_PCB || defined __DOXYGEN__ -#define MEMP_NUM_RAW_PCB 4 -#endif - -/** - * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - * per active UDP "connection". - * (requires the LWIP_UDP option) - */ -#if !defined MEMP_NUM_UDP_PCB || defined __DOXYGEN__ -#define MEMP_NUM_UDP_PCB 4 -#endif - -/** - * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections. - * (requires the LWIP_TCP option) - */ -#if !defined MEMP_NUM_TCP_PCB || defined __DOXYGEN__ -#define MEMP_NUM_TCP_PCB 5 -#endif - -/** - * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. - * (requires the LWIP_TCP option) - */ -#if !defined MEMP_NUM_TCP_PCB_LISTEN || defined __DOXYGEN__ -#define MEMP_NUM_TCP_PCB_LISTEN 8 -#endif - -/** - * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. - * (requires the LWIP_TCP option) - */ -#if !defined MEMP_NUM_TCP_SEG || defined __DOXYGEN__ -#define MEMP_NUM_TCP_SEG 16 -#endif - -/** - * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for - * reassembly (whole packets, not fragments!) - */ -#if !defined MEMP_NUM_REASSDATA || defined __DOXYGEN__ -#define MEMP_NUM_REASSDATA 5 -#endif - -/** - * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent - * (fragments, not whole packets!). - * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 - * with DMA-enabled MACs where the packet is not yet sent when netif->output - * returns. - */ -#if !defined MEMP_NUM_FRAG_PBUF || defined __DOXYGEN__ -#define MEMP_NUM_FRAG_PBUF 15 -#endif - -/** - * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing - * packets (pbufs) that are waiting for an ARP request (to resolve - * their destination address) to finish. - * (requires the ARP_QUEUEING option) - */ -#if !defined MEMP_NUM_ARP_QUEUE || defined __DOXYGEN__ -#define MEMP_NUM_ARP_QUEUE 30 -#endif - -/** - * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces - * can be members at the same time (one per netif - allsystems group -, plus one - * per netif membership). - * (requires the LWIP_IGMP option) - */ -#if !defined MEMP_NUM_IGMP_GROUP || defined __DOXYGEN__ -#define MEMP_NUM_IGMP_GROUP 8 -#endif - -/** - * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts. - * The default number of timeouts is calculated here for all enabled modules. - * The formula expects settings to be either '0' or '1'. - */ -#if !defined MEMP_NUM_SYS_TIMEOUT || defined __DOXYGEN__ -#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) -#endif - -/** - * MEMP_NUM_NETBUF: the number of struct netbufs. - * (only needed if you use the sequential API, like api_lib.c) - */ -#if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__ -#define MEMP_NUM_NETBUF 2 -#endif - -/** - * MEMP_NUM_NETCONN: the number of struct netconns. - * (only needed if you use the sequential API, like api_lib.c) - */ -#if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__ -#define MEMP_NUM_NETCONN 4 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used - * for callback/timeout API communication. - * (only needed if you use tcpip.c) - */ -#if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__ -#define MEMP_NUM_TCPIP_MSG_API 8 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used - * for incoming packets. - * (only needed if you use tcpip.c) - */ -#if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__ -#define MEMP_NUM_TCPIP_MSG_INPKT 8 -#endif - -/** - * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls - * (before freeing the corresponding memory using lwip_freeaddrinfo()). - */ -#if !defined MEMP_NUM_NETDB || defined __DOXYGEN__ -#define MEMP_NUM_NETDB 1 -#endif - -/** - * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list - * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. - */ -#if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__ -#define MEMP_NUM_LOCALHOSTLIST 1 -#endif - -/** - * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. - */ -#if !defined PBUF_POOL_SIZE || defined __DOXYGEN__ -#define PBUF_POOL_SIZE 16 -#endif - -/** MEMP_NUM_API_MSG: the number of concurrently active calls to various - * socket, netconn, and tcpip functions - */ -#if !defined MEMP_NUM_API_MSG || defined __DOXYGEN__ -#define MEMP_NUM_API_MSG MEMP_NUM_TCPIP_MSG_API -#endif - -/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname - */ -#if !defined MEMP_NUM_DNS_API_MSG || defined __DOXYGEN__ -#define MEMP_NUM_DNS_API_MSG MEMP_NUM_TCPIP_MSG_API -#endif - -/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls - * to getsockopt/setsockopt - */ -#if !defined MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA || defined __DOXYGEN__ -#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API -#endif - -/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the - * netifapi functions - */ -#if !defined MEMP_NUM_NETIFAPI_MSG || defined __DOXYGEN__ -#define MEMP_NUM_NETIFAPI_MSG MEMP_NUM_TCPIP_MSG_API -#endif -/** - * @} - */ - -/* - --------------------------------- - ---------- ARP options ---------- - --------------------------------- -*/ -/** - * @defgroup lwip_opts_arp ARP - * @ingroup lwip_opts_ipv4 - * @{ - */ -/** - * LWIP_ARP==1: Enable ARP functionality. - */ -#if !defined LWIP_ARP || defined __DOXYGEN__ -#define LWIP_ARP 1 -#endif - -/** - * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. - */ -#if !defined ARP_TABLE_SIZE || defined __DOXYGEN__ -#define ARP_TABLE_SIZE 10 -#endif - -/** the time an ARP entry stays valid after its last update, - * for ARP_TMR_INTERVAL = 1000, this is - * (60 * 5) seconds = 5 minutes. - */ -#if !defined ARP_MAXAGE || defined __DOXYGEN__ -#define ARP_MAXAGE 300 -#endif - -/** - * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address - * resolution. By default, only the most recent packet is queued per IP address. - * This is sufficient for most protocols and mainly reduces TCP connection - * startup time. Set this to 1 if you know your application sends more than one - * packet in a row to an IP address that is not in the ARP cache. - */ -#if !defined ARP_QUEUEING || defined __DOXYGEN__ -#define ARP_QUEUEING 0 -#endif - -/** The maximum number of packets which may be queued for each - * unresolved address by other network layers. Defaults to 3, 0 means disabled. - * Old packets are dropped, new packets are queued. - */ -#if !defined ARP_QUEUE_LEN || defined __DOXYGEN__ -#define ARP_QUEUE_LEN 3 -#endif - -/** - * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with - * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and - * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers. - * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. - * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. - * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. - * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) - * that returns 1 to accept a packet or 0 to drop a packet. - */ -#if !defined ETHARP_SUPPORT_VLAN || defined __DOXYGEN__ -#define ETHARP_SUPPORT_VLAN 0 -#endif - -/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled - */ -#if !defined LWIP_ETHERNET || defined __DOXYGEN__ -#define LWIP_ETHERNET LWIP_ARP -#endif - -/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure - * alignment of payload after that header. Since the header is 14 bytes long, - * without this padding e.g. addresses in the IP header will not be aligned - * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. - */ -#if !defined ETH_PAD_SIZE || defined __DOXYGEN__ -#define ETH_PAD_SIZE 0 -#endif - -/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table - * entries (using etharp_add_static_entry/etharp_remove_static_entry). - */ -#if !defined ETHARP_SUPPORT_STATIC_ENTRIES || defined __DOXYGEN__ -#define ETHARP_SUPPORT_STATIC_ENTRIES 0 -#endif - -/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries. - * If disabled, duplicate IP address on multiple netifs are not supported - * (but this should only occur for AutoIP). - */ -#if !defined ETHARP_TABLE_MATCH_NETIF || defined __DOXYGEN__ -#define ETHARP_TABLE_MATCH_NETIF 0 -#endif -/** - * @} - */ - -/* - -------------------------------- - ---------- IP options ---------- - -------------------------------- -*/ -/** - * @defgroup lwip_opts_ipv4 IPv4 - * @ingroup lwip_opts - * @{ - */ -/** - * LWIP_IPV4==1: Enable IPv4 - */ -#if !defined LWIP_IPV4 || defined __DOXYGEN__ -#define LWIP_IPV4 1 -#endif - -/** - * IP_FORWARD==1: Enables the ability to forward IP packets across network - * interfaces. If you are going to run lwIP on a device with only one network - * interface, define this to 0. - */ -#if !defined IP_FORWARD || defined __DOXYGEN__ -#define IP_FORWARD 0 -#endif - -/** - * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that - * this option does not affect outgoing packet sizes, which can be controlled - * via IP_FRAG. - */ -#if !defined IP_REASSEMBLY || defined __DOXYGEN__ -#define IP_REASSEMBLY 1 -#endif - -/** - * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note - * that this option does not affect incoming packet sizes, which can be - * controlled via IP_REASSEMBLY. - */ -#if !defined IP_FRAG || defined __DOXYGEN__ -#define IP_FRAG 1 -#endif - -#if !LWIP_IPV4 -/* disable IPv4 extensions when IPv4 is disabled */ -#undef IP_FORWARD -#define IP_FORWARD 0 -#undef IP_REASSEMBLY -#define IP_REASSEMBLY 0 -#undef IP_FRAG -#define IP_FRAG 0 -#endif /* !LWIP_IPV4 */ - -/** - * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. - * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. - * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). - */ -#if !defined IP_OPTIONS_ALLOWED || defined __DOXYGEN__ -#define IP_OPTIONS_ALLOWED 1 -#endif - -/** - * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) - * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived - * in this time, the whole packet is discarded. - */ -#if !defined IP_REASS_MAXAGE || defined __DOXYGEN__ -#define IP_REASS_MAXAGE 3 -#endif - -/** - * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. - * Since the received pbufs are enqueued, be sure to configure - * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive - * packets even if the maximum amount of fragments is enqueued for reassembly! - */ -#if !defined IP_REASS_MAX_PBUFS || defined __DOXYGEN__ -#define IP_REASS_MAX_PBUFS 10 -#endif - -/** - * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. - */ -#if !defined IP_DEFAULT_TTL || defined __DOXYGEN__ -#define IP_DEFAULT_TTL 255 -#endif - -/** - * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast - * filter per pcb on udp and raw send operations. To enable broadcast filter - * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. - */ -#if !defined IP_SOF_BROADCAST || defined __DOXYGEN__ -#define IP_SOF_BROADCAST 0 -#endif - -/** - * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast - * filter on recv operations. - */ -#if !defined IP_SOF_BROADCAST_RECV || defined __DOXYGEN__ -#define IP_SOF_BROADCAST_RECV 0 -#endif - -/** - * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back - * out on the netif where it was received. This should only be used for - * wireless networks. - * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming - * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! - */ -#if !defined IP_FORWARD_ALLOW_TX_ON_RX_NETIF || defined __DOXYGEN__ -#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 -#endif - -/** - * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first - * local TCP/UDP pcb (default==0). This can prevent creating predictable port - * numbers after booting a device. - */ -#if !defined LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS || defined __DOXYGEN__ -#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1 -#endif -/** - * @} - */ - -/* - ---------------------------------- - ---------- ICMP options ---------- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_icmp ICMP - * @ingroup lwip_opts_ipv4 - * @{ - */ -/** - * LWIP_ICMP==1: Enable ICMP module inside the IP stack. - * Be careful, disable that make your product non-compliant to RFC1122 - */ -#if !defined LWIP_ICMP || defined __DOXYGEN__ -#define LWIP_ICMP 1 -#endif - -/** - * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. - */ -#if !defined ICMP_TTL || defined __DOXYGEN__ -#define ICMP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) - */ -#if !defined LWIP_BROADCAST_PING || defined __DOXYGEN__ -#define LWIP_BROADCAST_PING 0 -#endif - -/** - * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) - */ -#if !defined LWIP_MULTICAST_PING || defined __DOXYGEN__ -#define LWIP_MULTICAST_PING 0 -#endif -/** - * @} - */ - -/* - --------------------------------- - ---------- RAW options ---------- - --------------------------------- -*/ -/** - * @defgroup lwip_opts_raw RAW - * @ingroup lwip_opts_callback - * @{ - */ -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#if !defined LWIP_RAW || defined __DOXYGEN__ -#define LWIP_RAW 0 -#endif - -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#if !defined RAW_TTL || defined __DOXYGEN__ -#define RAW_TTL (IP_DEFAULT_TTL) -#endif -/** - * @} - */ - -/* - ---------------------------------- - ---------- DHCP options ---------- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_dhcp DHCP - * @ingroup lwip_opts_ipv4 - * @{ - */ -/** - * LWIP_DHCP==1: Enable DHCP module. - */ -#if !defined LWIP_DHCP || defined __DOXYGEN__ -#define LWIP_DHCP 0 -#endif -#if !LWIP_IPV4 -/* disable DHCP when IPv4 is disabled */ -#undef LWIP_DHCP -#define LWIP_DHCP 0 -#endif /* !LWIP_IPV4 */ - -/** - * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. - */ -#if !defined DHCP_DOES_ARP_CHECK || defined __DOXYGEN__ -#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) -#endif - -/** - * LWIP_DHCP_CHECK_LINK_UP==1: dhcp_start() only really starts if the netif has - * NETIF_FLAG_LINK_UP set in its flags. As this is only an optimization and - * netif drivers might not set this flag, the default is off. If enabled, - * netif_set_link_up() must be called to continue dhcp starting. - */ -#if !defined LWIP_DHCP_CHECK_LINK_UP -#define LWIP_DHCP_CHECK_LINK_UP 0 -#endif - -/** - * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name. - */ -#if !defined LWIP_DHCP_BOOTP_FILE || defined __DOXYGEN__ -#define LWIP_DHCP_BOOTP_FILE 0 -#endif - -/** - * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each - * response packet, an callback is called, which has to be provided by the port: - * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs); -*/ -#if !defined LWIP_DHCP_GET_NTP_SRV || defined __DOXYGEN__ -#define LWIP_DHCP_GET_NTP_SRV 0 -#endif - -/** - * The maximum of NTP servers requested - */ -#if !defined LWIP_DHCP_MAX_NTP_SERVERS || defined __DOXYGEN__ -#define LWIP_DHCP_MAX_NTP_SERVERS 1 -#endif - -/** - * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select. - * DHCP servers received in the response are passed to DNS via @ref dns_setserver() - * (up to the maximum limit defined here). - */ -#if !defined LWIP_DHCP_MAX_DNS_SERVERS || defined __DOXYGEN__ -#define LWIP_DHCP_MAX_DNS_SERVERS DNS_MAX_SERVERS -#endif -/** - * @} - */ - -/* - ------------------------------------ - ---------- AUTOIP options ---------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_autoip AUTOIP - * @ingroup lwip_opts_ipv4 - * @{ - */ -/** - * LWIP_AUTOIP==1: Enable AUTOIP module. - */ -#if !defined LWIP_AUTOIP || defined __DOXYGEN__ -#define LWIP_AUTOIP 0 -#endif -#if !LWIP_IPV4 -/* disable AUTOIP when IPv4 is disabled */ -#undef LWIP_AUTOIP -#define LWIP_AUTOIP 0 -#endif /* !LWIP_IPV4 */ - -/** - * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on - * the same interface at the same time. - */ -#if !defined LWIP_DHCP_AUTOIP_COOP || defined __DOXYGEN__ -#define LWIP_DHCP_AUTOIP_COOP 0 -#endif - -/** - * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes - * that should be sent before falling back on AUTOIP (the DHCP client keeps - * running in this case). This can be set as low as 1 to get an AutoIP address - * very quickly, but you should be prepared to handle a changing IP address - * when DHCP overrides AutoIP. - */ -#if !defined LWIP_DHCP_AUTOIP_COOP_TRIES || defined __DOXYGEN__ -#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 -#endif -/** - * @} - */ - -/* - ---------------------------------- - ----- SNMP MIB2 support ----- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks. - * Turn this on to get callbacks needed to implement MIB2. - * Usually MIB2_STATS should be enabled, too. - */ -#if !defined LWIP_MIB2_CALLBACKS || defined __DOXYGEN__ -#define LWIP_MIB2_CALLBACKS 0 -#endif -/** - * @} - */ - -/* - ---------------------------------- - ----- Multicast/IGMP options ----- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_igmp IGMP - * @ingroup lwip_opts_ipv4 - * @{ - */ -/** - * LWIP_IGMP==1: Turn on IGMP module. - */ -#if !defined LWIP_IGMP || defined __DOXYGEN__ -#define LWIP_IGMP 0 -#endif -#if !LWIP_IPV4 -#undef LWIP_IGMP -#define LWIP_IGMP 0 -#endif - -/** - * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options - * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP - */ -#if !defined LWIP_MULTICAST_TX_OPTIONS || defined __DOXYGEN__ -#define LWIP_MULTICAST_TX_OPTIONS (LWIP_IGMP && LWIP_UDP) -#endif -/** - * @} - */ - -/* - ---------------------------------- - ---------- DNS options ----------- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_dns DNS - * @ingroup lwip_opts_callback - * @{ - */ -/** - * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS - * transport. - */ -#if !defined LWIP_DNS || defined __DOXYGEN__ -#define LWIP_DNS 0 -#endif - -/** DNS maximum number of entries to maintain locally. */ -#if !defined DNS_TABLE_SIZE || defined __DOXYGEN__ -#define DNS_TABLE_SIZE 4 -#endif - -/** DNS maximum host name length supported in the name table. */ -#if !defined DNS_MAX_NAME_LENGTH || defined __DOXYGEN__ -#define DNS_MAX_NAME_LENGTH 256 -#endif - -/** The maximum of DNS servers - * The first server can be initialized automatically by defining - * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*' - */ -#if !defined DNS_MAX_SERVERS || defined __DOXYGEN__ -#define DNS_MAX_SERVERS 2 -#endif - -/** DNS do a name checking between the query and the response. */ -#if !defined DNS_DOES_NAME_CHECK || defined __DOXYGEN__ -#define DNS_DOES_NAME_CHECK 1 -#endif - -/** LWIP_DNS_SECURE: controls the security level of the DNS implementation - * Use all DNS security features by default. - * This is overridable but should only be needed by very small targets - * or when using against non standard DNS servers. */ -#if !defined LWIP_DNS_SECURE || defined __DOXYGEN__ -#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -#endif - -/* A list of DNS security features follows */ -#define LWIP_DNS_SECURE_RAND_XID 1 -#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2 -#define LWIP_DNS_SECURE_RAND_SRC_PORT 4 - -/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer: - * \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \ - * DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)} - * - * Instead, you can also use an external function: - * \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype) - * that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype). - */ -#if !defined DNS_LOCAL_HOSTLIST || defined __DOXYGEN__ -#define DNS_LOCAL_HOSTLIST 0 -#endif /* DNS_LOCAL_HOSTLIST */ - -/** If this is turned on, the local host-list can be dynamically changed - * at runtime. */ -#if !defined DNS_LOCAL_HOSTLIST_IS_DYNAMIC || defined __DOXYGEN__ -#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -/** Set this to 1 to enable querying ".local" names via mDNS - * using a One-Shot Multicast DNS Query */ -#if !defined LWIP_DNS_SUPPORT_MDNS_QUERIES || defined __DOXYGEN__ -#define LWIP_DNS_SUPPORT_MDNS_QUERIES 0 -#endif -/** - * @} - */ - -/* - --------------------------------- - ---------- UDP options ---------- - --------------------------------- -*/ -/** - * @defgroup lwip_opts_udp UDP - * @ingroup lwip_opts_callback - * @{ - */ -/** - * LWIP_UDP==1: Turn on UDP. - */ -#if !defined LWIP_UDP || defined __DOXYGEN__ -#define LWIP_UDP 1 -#endif - -/** - * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) - */ -#if !defined LWIP_UDPLITE || defined __DOXYGEN__ -#define LWIP_UDPLITE 0 -#endif - -/** - * UDP_TTL: Default Time-To-Live value. - */ -#if !defined UDP_TTL || defined __DOXYGEN__ -#define UDP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. - */ -#if !defined LWIP_NETBUF_RECVINFO || defined __DOXYGEN__ -#define LWIP_NETBUF_RECVINFO 0 -#endif -/** - * @} - */ - -/* - --------------------------------- - ---------- TCP options ---------- - --------------------------------- -*/ -/** - * @defgroup lwip_opts_tcp TCP - * @ingroup lwip_opts_callback - * @{ - */ -/** - * LWIP_TCP==1: Turn on TCP. - */ -#if !defined LWIP_TCP || defined __DOXYGEN__ -#define LWIP_TCP 1 -#endif - -/** - * TCP_TTL: Default Time-To-Live value. - */ -#if !defined TCP_TTL || defined __DOXYGEN__ -#define TCP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * TCP_WND: The size of a TCP window. This must be at least - * (2 * TCP_MSS) for things to work well. - * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size - * with scaling applied. Maximum window value in the TCP header - * will be TCP_WND >> TCP_RCV_SCALE - */ -#if !defined TCP_WND || defined __DOXYGEN__ -#define TCP_WND (4 * TCP_MSS) -#endif - -/** - * TCP_MAXRTX: Maximum number of retransmissions of data segments. - */ -#if !defined TCP_MAXRTX || defined __DOXYGEN__ -#define TCP_MAXRTX 12 -#endif - -/** - * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. - */ -#if !defined TCP_SYNMAXRTX || defined __DOXYGEN__ -#define TCP_SYNMAXRTX 6 -#endif - -/** - * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. - * Define to 0 if your device is low on memory. - */ -#if !defined TCP_QUEUE_OOSEQ || defined __DOXYGEN__ -#define TCP_QUEUE_OOSEQ (LWIP_TCP) -#endif - -/** - * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, - * you might want to increase this.) - * For the receive side, this MSS is advertised to the remote side - * when opening a connection. For the transmit size, this MSS sets - * an upper limit on the MSS advertised by the remote host. - */ -#if !defined TCP_MSS || defined __DOXYGEN__ -#define TCP_MSS 536 -#endif - -/** - * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really - * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which - * reflects the available reassembly buffer size at the remote host) and the - * largest size permitted by the IP layer" (RFC 1122) - * Setting this to 1 enables code that checks TCP_MSS against the MTU of the - * netif used for a connection and limits the MSS if it would be too big otherwise. - */ -#if !defined TCP_CALCULATE_EFF_SEND_MSS || defined __DOXYGEN__ -#define TCP_CALCULATE_EFF_SEND_MSS 1 -#endif - - -/** - * TCP_SND_BUF: TCP sender buffer space (bytes). - * To achieve good performance, this should be at least 2 * TCP_MSS. - */ -#if !defined TCP_SND_BUF || defined __DOXYGEN__ -#define TCP_SND_BUF (2 * TCP_MSS) -#endif - -/** - * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least - * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. - */ -#if !defined TCP_SND_QUEUELEN || defined __DOXYGEN__ -#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) -#endif - -/** - * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than - * TCP_SND_BUF. It is the amount of space which must be available in the - * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). - */ -#if !defined TCP_SNDLOWAT || defined __DOXYGEN__ -#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -#endif - -/** - * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less - * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below - * this number, select returns writable (combined with TCP_SNDLOWAT). - */ -#if !defined TCP_SNDQUEUELOWAT || defined __DOXYGEN__ -#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) -#endif - -/** - * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. - * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1. - */ -#if !defined TCP_OOSEQ_MAX_BYTES || defined __DOXYGEN__ -#define TCP_OOSEQ_MAX_BYTES 0 -#endif - -/** - * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. - * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1. - */ -#if !defined TCP_OOSEQ_MAX_PBUFS || defined __DOXYGEN__ -#define TCP_OOSEQ_MAX_PBUFS 0 -#endif - -/** - * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. - */ -#if !defined TCP_LISTEN_BACKLOG || defined __DOXYGEN__ -#define TCP_LISTEN_BACKLOG 0 -#endif - -/** - * The maximum allowed backlog for TCP listen netconns. - * This backlog is used unless another is explicitly specified. - * 0xff is the maximum (u8_t). - */ -#if !defined TCP_DEFAULT_LISTEN_BACKLOG || defined __DOXYGEN__ -#define TCP_DEFAULT_LISTEN_BACKLOG 0xff -#endif - -/** - * TCP_OVERSIZE: The maximum number of bytes that tcp_write may - * allocate ahead of time in an attempt to create shorter pbuf chains - * for transmission. The meaningful range is 0 to TCP_MSS. Some - * suggested values are: - * - * 0: Disable oversized allocation. Each tcp_write() allocates a new - pbuf (old behaviour). - * 1: Allocate size-aligned pbufs with minimal excess. Use this if your - * scatter-gather DMA requires aligned fragments. - * 128: Limit the pbuf/memory overhead to 20%. - * TCP_MSS: Try to create unfragmented TCP packets. - * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. - */ -#if !defined TCP_OVERSIZE || defined __DOXYGEN__ -#define TCP_OVERSIZE TCP_MSS -#endif - -/** - * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. - * The timestamp option is currently only used to help remote hosts, it is not - * really used locally. Therefore, it is only enabled when a TS option is - * received in the initial SYN packet from a remote host. - */ -#if !defined LWIP_TCP_TIMESTAMPS || defined __DOXYGEN__ -#define LWIP_TCP_TIMESTAMPS 0 -#endif - -/** - * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an - * explicit window update - */ -#if !defined TCP_WND_UPDATE_THRESHOLD || defined __DOXYGEN__ -#define TCP_WND_UPDATE_THRESHOLD LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4)) -#endif - -/** - * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. - * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all - * events (accept, sent, etc) that happen in the system. - * LWIP_CALLBACK_API==1: The PCB callback function is called directly - * for the event. This is the default. - */ -#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) || defined __DOXYGEN__ -#define LWIP_EVENT_API 0 -#define LWIP_CALLBACK_API 1 -#else -#ifndef LWIP_EVENT_API -#define LWIP_EVENT_API 0 -#endif -#ifndef LWIP_CALLBACK_API -#define LWIP_CALLBACK_API 0 -#endif -#endif - -/** - * LWIP_WND_SCALE and TCP_RCV_SCALE: - * Set LWIP_WND_SCALE to 1 to enable window scaling. - * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the - * range of [0..14]). - * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large - * send window while having a small receive window only. - */ -#if !defined LWIP_WND_SCALE || defined __DOXYGEN__ -#define LWIP_WND_SCALE 0 -#define TCP_RCV_SCALE 0 -#endif -/** - * @} - */ - -/* - ---------------------------------- - ---------- Pbuf options ---------- - ---------------------------------- -*/ -/** - * @defgroup lwip_opts_pbuf PBUF - * @ingroup lwip_opts - * @{ - */ -/** - * PBUF_LINK_HLEN: the number of bytes that should be allocated for a - * link level header. The default is 14, the standard value for - * Ethernet. - */ -#if !defined PBUF_LINK_HLEN || defined __DOXYGEN__ -#if defined LWIP_HOOK_VLAN_SET && !defined __DOXYGEN__ -#define PBUF_LINK_HLEN (18 + ETH_PAD_SIZE) -#else /* LWIP_HOOK_VLAN_SET */ -#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) -#endif /* LWIP_HOOK_VLAN_SET */ -#endif - -/** - * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated - * for an additional encapsulation header before ethernet headers (e.g. 802.11) - */ -#if !defined PBUF_LINK_ENCAPSULATION_HLEN || defined __DOXYGEN__ -#define PBUF_LINK_ENCAPSULATION_HLEN 0u -#endif - -/** - * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is - * designed to accommodate single full size TCP frame in one pbuf, including - * TCP_MSS, IP header, and link header. - */ -#if !defined PBUF_POOL_BUFSIZE || defined __DOXYGEN__ -#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN) -#endif -/** - * @} - */ - -/* - ------------------------------------------------ - ---------- Network Interfaces options ---------- - ------------------------------------------------ -*/ -/** - * @defgroup lwip_opts_netif NETIF - * @ingroup lwip_opts - * @{ - */ -/** - * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname - * field. - */ -#if !defined LWIP_NETIF_HOSTNAME || defined __DOXYGEN__ -#define LWIP_NETIF_HOSTNAME 0 -#endif - -/** - * LWIP_NETIF_API==1: Support netif api (in netifapi.c) - */ -#if !defined LWIP_NETIF_API || defined __DOXYGEN__ -#define LWIP_NETIF_API 0 -#endif - -/** - * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface - * changes its up/down status (i.e., due to DHCP IP acquisition) - */ -#if !defined LWIP_NETIF_STATUS_CALLBACK || defined __DOXYGEN__ -#define LWIP_NETIF_STATUS_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface - * whenever the link changes (i.e., link down) - */ -#if !defined LWIP_NETIF_LINK_CALLBACK || defined __DOXYGEN__ -#define LWIP_NETIF_LINK_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called - * when a netif has been removed - */ -#if !defined LWIP_NETIF_REMOVE_CALLBACK || defined __DOXYGEN__ -#define LWIP_NETIF_REMOVE_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table - * indices) in struct netif. TCP and UDP can make use of this to prevent - * scanning the ARP table for every sent packet. While this is faster for big - * ARP tables or many concurrent connections, it might be counterproductive - * if you have a tiny ARP table or if there never are concurrent connections. - */ -#if !defined LWIP_NETIF_HWADDRHINT || defined __DOXYGEN__ -#define LWIP_NETIF_HWADDRHINT 0 -#endif - -/** - * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data - * to be sent into one single pbuf. This is for compatibility with DMA-enabled - * MACs that do not support scatter-gather. - * Beware that this might involve CPU-memcpy before transmitting that would not - * be needed without this flag! Use this only if you need to! - * - * @todo: TCP and IP-frag do not work with this, yet: - */ -#if !defined LWIP_NETIF_TX_SINGLE_PBUF || defined __DOXYGEN__ -#define LWIP_NETIF_TX_SINGLE_PBUF 0 -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - -/** - * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store - * data in client_data member array of struct netif. - */ -#if !defined LWIP_NUM_NETIF_CLIENT_DATA || defined __DOXYGEN__ -#define LWIP_NUM_NETIF_CLIENT_DATA 0 -#endif -/** - * @} - */ - -/* - ------------------------------------ - ---------- LOOPIF options ---------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_loop Loopback interface - * @ingroup lwip_opts_netif - * @{ - */ -/** - * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1). - * This is only needed when no real netifs are available. If at least one other - * netif is available, loopback traffic uses this netif. - */ -#if !defined LWIP_HAVE_LOOPIF || defined __DOXYGEN__ -#define LWIP_HAVE_LOOPIF LWIP_NETIF_LOOPBACK -#endif - -/** - * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1). - */ -#if !defined LWIP_LOOPIF_MULTICAST || defined __DOXYGEN__ -#define LWIP_LOOPIF_MULTICAST 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP - * address equal to the netif IP address, looping them back up the stack. - */ -#if !defined LWIP_NETIF_LOOPBACK || defined __DOXYGEN__ -#define LWIP_NETIF_LOOPBACK 0 -#endif - -/** - * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback - * sending for each netif (0 = disabled) - */ -#if !defined LWIP_LOOPBACK_MAX_PBUFS || defined __DOXYGEN__ -#define LWIP_LOOPBACK_MAX_PBUFS 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in - * the system, as netifs must change how they behave depending on this setting - * for the LWIP_NETIF_LOOPBACK option to work. - * Setting this is needed to avoid reentering non-reentrant functions like - * tcp_input(). - * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a - * multithreaded environment like tcpip.c. In this case, netif->input() - * is called directly. - * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. - * The packets are put on a list and netif_poll() must be called in - * the main application loop. - */ -#if !defined LWIP_NETIF_LOOPBACK_MULTITHREADING || defined __DOXYGEN__ -#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) -#endif -/** - * @} - */ - -/* - ------------------------------------ - ---------- Thread options ---------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_thread Threading - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. - */ -#if !defined TCPIP_THREAD_NAME || defined __DOXYGEN__ -#define TCPIP_THREAD_NAME "tcpip_thread" -#endif - -/** - * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined TCPIP_THREAD_STACKSIZE || defined __DOXYGEN__ -#define TCPIP_THREAD_STACKSIZE 0 -#endif - -/** - * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined TCPIP_THREAD_PRIO || defined __DOXYGEN__ -#define TCPIP_THREAD_PRIO 1 -#endif - -/** - * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when tcpip_init is called. - */ -#if !defined TCPIP_MBOX_SIZE || defined __DOXYGEN__ -#define TCPIP_MBOX_SIZE 0 -#endif - -/** - * Define this to something that triggers a watchdog. This is called from - * tcpip_thread after processing a message. - */ -#if !defined LWIP_TCPIP_THREAD_ALIVE || defined __DOXYGEN__ -#define LWIP_TCPIP_THREAD_ALIVE() -#endif - -/** - * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. - */ -#if !defined SLIPIF_THREAD_NAME || defined __DOXYGEN__ -#define SLIPIF_THREAD_NAME "slipif_loop" -#endif - -/** - * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined SLIPIF_THREAD_STACKSIZE || defined __DOXYGEN__ -#define SLIPIF_THREAD_STACKSIZE 0 -#endif - -/** - * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined SLIPIF_THREAD_PRIO || defined __DOXYGEN__ -#define SLIPIF_THREAD_PRIO 1 -#endif - -/** - * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. - */ -#if !defined DEFAULT_THREAD_NAME || defined __DOXYGEN__ -#define DEFAULT_THREAD_NAME "lwIP" -#endif - -/** - * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined DEFAULT_THREAD_STACKSIZE || defined __DOXYGEN__ -#define DEFAULT_THREAD_STACKSIZE 0 -#endif - -/** - * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#if !defined DEFAULT_THREAD_PRIO || defined __DOXYGEN__ -#define DEFAULT_THREAD_PRIO 1 -#endif - -/** - * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#if !defined DEFAULT_RAW_RECVMBOX_SIZE || defined __DOXYGEN__ -#define DEFAULT_RAW_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#if !defined DEFAULT_UDP_RECVMBOX_SIZE || defined __DOXYGEN__ -#define DEFAULT_UDP_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#if !defined DEFAULT_TCP_RECVMBOX_SIZE || defined __DOXYGEN__ -#define DEFAULT_TCP_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when the acceptmbox is created. - */ -#if !defined DEFAULT_ACCEPTMBOX_SIZE || defined __DOXYGEN__ -#define DEFAULT_ACCEPTMBOX_SIZE 0 -#endif -/** - * @} - */ - -/* - ---------------------------------------------- - ---------- Sequential layer options ---------- - ---------------------------------------------- -*/ -/** - * @defgroup lwip_opts_netconn Netconn - * @ingroup lwip_opts_threadsafe_apis - * @{ - */ -/** - * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) - */ -#if !defined LWIP_NETCONN || defined __DOXYGEN__ -#define LWIP_NETCONN 1 -#endif - -/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create - * timers running in tcpip_thread from another thread. - */ -#if !defined LWIP_TCPIP_TIMEOUT || defined __DOXYGEN__ -#define LWIP_TCPIP_TIMEOUT 0 -#endif - -/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per - * thread calling socket/netconn functions instead of allocating one - * semaphore per netconn (and per select etc.) - * ATTENTION: a thread-local semaphore for API calls is needed: - * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t* - * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore - * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore - * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup(). - * Ports may call these for threads created with sys_thread_new(). - */ -#if !defined LWIP_NETCONN_SEM_PER_THREAD || defined __DOXYGEN__ -#define LWIP_NETCONN_SEM_PER_THREAD 0 -#endif - -/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread, - * writing from a 2nd thread and closing from a 3rd thread at the same time. - * ATTENTION: This is currently really alpha! Some requirements: - * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from - * multiple threads at once - * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox - * and prevent a task pending on this during/after deletion - */ -#if !defined LWIP_NETCONN_FULLDUPLEX || defined __DOXYGEN__ -#define LWIP_NETCONN_FULLDUPLEX 0 -#endif -/** - * @} - */ - -/* - ------------------------------------ - ---------- Socket options ---------- - ------------------------------------ -*/ -/** - * @defgroup lwip_opts_socket Sockets - * @ingroup lwip_opts_threadsafe_apis - * @{ - */ -/** - * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) - */ -#if !defined LWIP_SOCKET || defined __DOXYGEN__ -#define LWIP_SOCKET 1 -#endif - -/* LWIP_SOCKET_SET_ERRNO==1: Set errno when socket functions cannot complete - * successfully, as required by POSIX. Default is POSIX-compliant. - */ -#if !defined LWIP_SOCKET_SET_ERRNO || defined __DOXYGEN__ -#define LWIP_SOCKET_SET_ERRNO 1 -#endif - -/** - * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines. - * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created. - * While this helps code completion, it might conflict with existing libraries. - * (only used if you use sockets.c) - */ -#if !defined LWIP_COMPAT_SOCKETS || defined __DOXYGEN__ -#define LWIP_COMPAT_SOCKETS 1 -#endif - -/** - * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. - * Disable this option if you use a POSIX operating system that uses the same - * names (read, write & close). (only used if you use sockets.c) - */ -#if !defined LWIP_POSIX_SOCKETS_IO_NAMES || defined __DOXYGEN__ -#define LWIP_POSIX_SOCKETS_IO_NAMES 1 -#endif - -/** - * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n. - * This can be useful when there are multiple APIs which create file descriptors. - * When they all start with a different offset and you won't make them overlap you can - * re implement read/write/close/ioctl/fnctl to send the requested action to the right - * library (sharing select will need more work though). - */ -#if !defined LWIP_SOCKET_OFFSET || defined __DOXYGEN__ -#define LWIP_SOCKET_OFFSET 0 -#endif - -/** - * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT - * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set - * in seconds. (does not require sockets.c, and will affect tcp.c) - */ -#if !defined LWIP_TCP_KEEPALIVE || defined __DOXYGEN__ -#define LWIP_TCP_KEEPALIVE 0 -#endif - -/** - * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and - * SO_SNDTIMEO processing. - */ -#if !defined LWIP_SO_SNDTIMEO || defined __DOXYGEN__ -#define LWIP_SO_SNDTIMEO 0 -#endif - -/** - * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and - * SO_RCVTIMEO processing. - */ -#if !defined LWIP_SO_RCVTIMEO || defined __DOXYGEN__ -#define LWIP_SO_RCVTIMEO 0 -#endif - -/** - * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int - * (milliseconds, much like winsock does) instead of a struct timeval (default). - */ -#if !defined LWIP_SO_SNDRCVTIMEO_NONSTANDARD || defined __DOXYGEN__ -#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0 -#endif - -/** - * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. - */ -#if !defined LWIP_SO_RCVBUF || defined __DOXYGEN__ -#define LWIP_SO_RCVBUF 0 -#endif - -/** - * LWIP_SO_LINGER==1: Enable SO_LINGER processing. - */ -#if !defined LWIP_SO_LINGER || defined __DOXYGEN__ -#define LWIP_SO_LINGER 0 -#endif - -/** - * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. - */ -#if !defined RECV_BUFSIZE_DEFAULT || defined __DOXYGEN__ -#define RECV_BUFSIZE_DEFAULT INT_MAX -#endif - -/** - * By default, TCP socket/netconn close waits 20 seconds max to send the FIN - */ -#if !defined LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT || defined __DOXYGEN__ -#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000 -#endif - -/** - * SO_REUSE==1: Enable SO_REUSEADDR option. - */ -#if !defined SO_REUSE || defined __DOXYGEN__ -#define SO_REUSE 0 -#endif - -/** - * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets - * to all local matches if SO_REUSEADDR is turned on. - * WARNING: Adds a memcpy for every packet if passing to more than one pcb! - */ -#if !defined SO_REUSE_RXTOALL || defined __DOXYGEN__ -#define SO_REUSE_RXTOALL 0 -#endif - -/** - * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of - * pending data in the network buffer. This is the way windows does it. It's - * the default for lwIP since it is smaller. - * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next - * pending datagram in bytes. This is the way linux does it. This code is only - * here for compatibility. - */ -#if !defined LWIP_FIONREAD_LINUXMODE || defined __DOXYGEN__ -#define LWIP_FIONREAD_LINUXMODE 0 -#endif -/** - * @} - */ - -/* - ---------------------------------------- - ---------- Statistics options ---------- - ---------------------------------------- -*/ -/** - * @defgroup lwip_opts_stats Statistics - * @ingroup lwip_opts_debug - * @{ - */ -/** - * LWIP_STATS==1: Enable statistics collection in lwip_stats. - */ -#if !defined LWIP_STATS || defined __DOXYGEN__ -#define LWIP_STATS 1 -#endif - -#if LWIP_STATS - -/** - * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. - */ -#if !defined LWIP_STATS_DISPLAY || defined __DOXYGEN__ -#define LWIP_STATS_DISPLAY 0 -#endif - -/** - * LINK_STATS==1: Enable link stats. - */ -#if !defined LINK_STATS || defined __DOXYGEN__ -#define LINK_STATS 1 -#endif - -/** - * ETHARP_STATS==1: Enable etharp stats. - */ -#if !defined ETHARP_STATS || defined __DOXYGEN__ -#define ETHARP_STATS (LWIP_ARP) -#endif - -/** - * IP_STATS==1: Enable IP stats. - */ -#if !defined IP_STATS || defined __DOXYGEN__ -#define IP_STATS 1 -#endif - -/** - * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is - * on if using either frag or reass. - */ -#if !defined IPFRAG_STATS || defined __DOXYGEN__ -#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) -#endif - -/** - * ICMP_STATS==1: Enable ICMP stats. - */ -#if !defined ICMP_STATS || defined __DOXYGEN__ -#define ICMP_STATS 1 -#endif - -/** - * IGMP_STATS==1: Enable IGMP stats. - */ -#if !defined IGMP_STATS || defined __DOXYGEN__ -#define IGMP_STATS (LWIP_IGMP) -#endif - -/** - * UDP_STATS==1: Enable UDP stats. Default is on if - * UDP enabled, otherwise off. - */ -#if !defined UDP_STATS || defined __DOXYGEN__ -#define UDP_STATS (LWIP_UDP) -#endif - -/** - * TCP_STATS==1: Enable TCP stats. Default is on if TCP - * enabled, otherwise off. - */ -#if !defined TCP_STATS || defined __DOXYGEN__ -#define TCP_STATS (LWIP_TCP) -#endif - -/** - * MEM_STATS==1: Enable mem.c stats. - */ -#if !defined MEM_STATS || defined __DOXYGEN__ -#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) -#endif - -/** - * MEMP_STATS==1: Enable memp.c pool stats. - */ -#if !defined MEMP_STATS || defined __DOXYGEN__ -#define MEMP_STATS (MEMP_MEM_MALLOC == 0) -#endif - -/** - * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). - */ -#if !defined SYS_STATS || defined __DOXYGEN__ -#define SYS_STATS (NO_SYS == 0) -#endif - -/** - * IP6_STATS==1: Enable IPv6 stats. - */ -#if !defined IP6_STATS || defined __DOXYGEN__ -#define IP6_STATS (LWIP_IPV6) -#endif - -/** - * ICMP6_STATS==1: Enable ICMP for IPv6 stats. - */ -#if !defined ICMP6_STATS || defined __DOXYGEN__ -#define ICMP6_STATS (LWIP_IPV6 && LWIP_ICMP6) -#endif - -/** - * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats. - */ -#if !defined IP6_FRAG_STATS || defined __DOXYGEN__ -#define IP6_FRAG_STATS (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS)) -#endif - -/** - * MLD6_STATS==1: Enable MLD for IPv6 stats. - */ -#if !defined MLD6_STATS || defined __DOXYGEN__ -#define MLD6_STATS (LWIP_IPV6 && LWIP_IPV6_MLD) -#endif - -/** - * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats. - */ -#if !defined ND6_STATS || defined __DOXYGEN__ -#define ND6_STATS (LWIP_IPV6) -#endif - -/** - * MIB2_STATS==1: Stats for SNMP MIB2. - */ -#if !defined MIB2_STATS || defined __DOXYGEN__ -#define MIB2_STATS 0 -#endif - -#else - -#define LINK_STATS 0 -#define ETHARP_STATS 0 -#define IP_STATS 0 -#define IPFRAG_STATS 0 -#define ICMP_STATS 0 -#define IGMP_STATS 0 -#define UDP_STATS 0 -#define TCP_STATS 0 -#define MEM_STATS 0 -#define MEMP_STATS 0 -#define SYS_STATS 0 -#define LWIP_STATS_DISPLAY 0 -#define IP6_STATS 0 -#define ICMP6_STATS 0 -#define IP6_FRAG_STATS 0 -#define MLD6_STATS 0 -#define ND6_STATS 0 -#define MIB2_STATS 0 - -#endif /* LWIP_STATS */ -/** - * @} - */ - -/* - -------------------------------------- - ---------- Checksum options ---------- - -------------------------------------- -*/ -/** - * @defgroup lwip_opts_checksum Checksum - * @ingroup lwip_opts_infrastructure - * @{ - */ -/** - * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled - * per netif. - * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled! - */ -#if !defined LWIP_CHECKSUM_CTRL_PER_NETIF || defined __DOXYGEN__ -#define LWIP_CHECKSUM_CTRL_PER_NETIF 0 -#endif - -/** - * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. - */ -#if !defined CHECKSUM_GEN_IP || defined __DOXYGEN__ -#define CHECKSUM_GEN_IP 1 -#endif - -/** - * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. - */ -#if !defined CHECKSUM_GEN_UDP || defined __DOXYGEN__ -#define CHECKSUM_GEN_UDP 1 -#endif - -/** - * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. - */ -#if !defined CHECKSUM_GEN_TCP || defined __DOXYGEN__ -#define CHECKSUM_GEN_TCP 1 -#endif - -/** - * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. - */ -#if !defined CHECKSUM_GEN_ICMP || defined __DOXYGEN__ -#define CHECKSUM_GEN_ICMP 1 -#endif - -/** - * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets. - */ -#if !defined CHECKSUM_GEN_ICMP6 || defined __DOXYGEN__ -#define CHECKSUM_GEN_ICMP6 1 -#endif - -/** - * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. - */ -#if !defined CHECKSUM_CHECK_IP || defined __DOXYGEN__ -#define CHECKSUM_CHECK_IP 1 -#endif - -/** - * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. - */ -#if !defined CHECKSUM_CHECK_UDP || defined __DOXYGEN__ -#define CHECKSUM_CHECK_UDP 1 -#endif - -/** - * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. - */ -#if !defined CHECKSUM_CHECK_TCP || defined __DOXYGEN__ -#define CHECKSUM_CHECK_TCP 1 -#endif - -/** - * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets. - */ -#if !defined CHECKSUM_CHECK_ICMP || defined __DOXYGEN__ -#define CHECKSUM_CHECK_ICMP 1 -#endif - -/** - * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets - */ -#if !defined CHECKSUM_CHECK_ICMP6 || defined __DOXYGEN__ -#define CHECKSUM_CHECK_ICMP6 1 -#endif - -/** - * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from - * application buffers to pbufs. - */ -#if !defined LWIP_CHECKSUM_ON_COPY || defined __DOXYGEN__ -#define LWIP_CHECKSUM_ON_COPY 0 -#endif -/** - * @} - */ - -/* - --------------------------------------- - ---------- IPv6 options --------------- - --------------------------------------- -*/ -/** - * @defgroup lwip_opts_ipv6 IPv6 - * @ingroup lwip_opts - * @{ - */ -/** - * LWIP_IPV6==1: Enable IPv6 - */ -#if !defined LWIP_IPV6 || defined __DOXYGEN__ -#define LWIP_IPV6 0 -#endif - -/** - * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif. - */ -#if !defined LWIP_IPV6_NUM_ADDRESSES || defined __DOXYGEN__ -#define LWIP_IPV6_NUM_ADDRESSES 3 -#endif - -/** - * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs - */ -#if !defined LWIP_IPV6_FORWARD || defined __DOXYGEN__ -#define LWIP_IPV6_FORWARD 0 -#endif - -/** - * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big. - */ -#if !defined LWIP_IPV6_FRAG || defined __DOXYGEN__ -#define LWIP_IPV6_FRAG 0 -#endif - -/** - * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented - */ -#if !defined LWIP_IPV6_REASS || defined __DOXYGEN__ -#define LWIP_IPV6_REASS (LWIP_IPV6) -#endif - -/** - * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during - * network startup. - */ -#if !defined LWIP_IPV6_SEND_ROUTER_SOLICIT || defined __DOXYGEN__ -#define LWIP_IPV6_SEND_ROUTER_SOLICIT 1 -#endif - -/** - * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862. - */ -#if !defined LWIP_IPV6_AUTOCONFIG || defined __DOXYGEN__ -#define LWIP_IPV6_AUTOCONFIG (LWIP_IPV6) -#endif - -/** - * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts. - */ -#if !defined LWIP_IPV6_DUP_DETECT_ATTEMPTS || defined __DOXYGEN__ -#define LWIP_IPV6_DUP_DETECT_ATTEMPTS 1 -#endif -/** - * @} - */ - -/** - * @defgroup lwip_opts_icmp6 ICMP6 - * @ingroup lwip_opts_ipv6 - * @{ - */ -/** - * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC) - */ -#if !defined LWIP_ICMP6 || defined __DOXYGEN__ -#define LWIP_ICMP6 (LWIP_IPV6) -#endif - -/** - * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in - * ICMPv6 error messages. - */ -#if !defined LWIP_ICMP6_DATASIZE || defined __DOXYGEN__ -#define LWIP_ICMP6_DATASIZE 8 -#endif - -/** - * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages - */ -#if !defined LWIP_ICMP6_HL || defined __DOXYGEN__ -#define LWIP_ICMP6_HL 255 -#endif -/** - * @} - */ - -/** - * @defgroup lwip_opts_mld6 Multicast listener discovery - * @ingroup lwip_opts_ipv6 - * @{ - */ -/** - * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol. - * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must - * indiscriminately pass all inbound IPv6 multicast traffic to lwIP. - */ -#if !defined LWIP_IPV6_MLD || defined __DOXYGEN__ -#define LWIP_IPV6_MLD (LWIP_IPV6) -#endif - -/** - * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined. - * There must be enough groups so that each netif can join the solicited-node - * multicast group for each of its local addresses, plus one for MDNS if - * applicable, plus any number of groups to be joined on UDP sockets. - */ -#if !defined MEMP_NUM_MLD6_GROUP || defined __DOXYGEN__ -#define MEMP_NUM_MLD6_GROUP 4 -#endif -/** - * @} - */ - -/** - * @defgroup lwip_opts_nd6 Neighbor discovery - * @ingroup lwip_opts_ipv6 - * @{ - */ -/** - * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address - * is being resolved. - */ -#if !defined LWIP_ND6_QUEUEING || defined __DOXYGEN__ -#define LWIP_ND6_QUEUEING (LWIP_IPV6) -#endif - -/** - * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. - */ -#if !defined MEMP_NUM_ND6_QUEUE || defined __DOXYGEN__ -#define MEMP_NUM_ND6_QUEUE 20 -#endif - -/** - * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache - */ -#if !defined LWIP_ND6_NUM_NEIGHBORS || defined __DOXYGEN__ -#define LWIP_ND6_NUM_NEIGHBORS 10 -#endif - -/** - * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache - */ -#if !defined LWIP_ND6_NUM_DESTINATIONS || defined __DOXYGEN__ -#define LWIP_ND6_NUM_DESTINATIONS 10 -#endif - -/** - * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache - */ -#if !defined LWIP_ND6_NUM_PREFIXES || defined __DOXYGEN__ -#define LWIP_ND6_NUM_PREFIXES 5 -#endif - -/** - * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache - */ -#if !defined LWIP_ND6_NUM_ROUTERS || defined __DOXYGEN__ -#define LWIP_ND6_NUM_ROUTERS 3 -#endif - -/** - * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send - * (neighbor solicit and router solicit) - */ -#if !defined LWIP_ND6_MAX_MULTICAST_SOLICIT || defined __DOXYGEN__ -#define LWIP_ND6_MAX_MULTICAST_SOLICIT 3 -#endif - -/** - * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages - * to send during neighbor reachability detection. - */ -#if !defined LWIP_ND6_MAX_UNICAST_SOLICIT || defined __DOXYGEN__ -#define LWIP_ND6_MAX_UNICAST_SOLICIT 3 -#endif - -/** - * Unused: See ND RFC (time in milliseconds). - */ -#if !defined LWIP_ND6_MAX_ANYCAST_DELAY_TIME || defined __DOXYGEN__ -#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000 -#endif - -/** - * Unused: See ND RFC - */ -#if !defined LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT || defined __DOXYGEN__ -#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT 3 -#endif - -/** - * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds). - * May be updated by router advertisement messages. - */ -#if !defined LWIP_ND6_REACHABLE_TIME || defined __DOXYGEN__ -#define LWIP_ND6_REACHABLE_TIME 30000 -#endif - -/** - * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages - */ -#if !defined LWIP_ND6_RETRANS_TIMER || defined __DOXYGEN__ -#define LWIP_ND6_RETRANS_TIMER 1000 -#endif - -/** - * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation - * message is sent, during neighbor reachability detection. - */ -#if !defined LWIP_ND6_DELAY_FIRST_PROBE_TIME || defined __DOXYGEN__ -#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000 -#endif - -/** - * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update - * Reachable time and retransmission timers, and netif MTU. - */ -#if !defined LWIP_ND6_ALLOW_RA_UPDATES || defined __DOXYGEN__ -#define LWIP_ND6_ALLOW_RA_UPDATES 1 -#endif - -/** - * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery - * with reachability hints for connected destinations. This helps avoid sending - * unicast neighbor solicitation messages. - */ -#if !defined LWIP_ND6_TCP_REACHABILITY_HINTS || defined __DOXYGEN__ -#define LWIP_ND6_TCP_REACHABILITY_HINTS 1 -#endif - -/** - * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive - * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS - * servers to the DNS module. - */ -#if !defined LWIP_ND6_RDNSS_MAX_DNS_SERVERS || defined __DOXYGEN__ -#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 -#endif -/** - * @} - */ - -/** - * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful address autoconfiguration. - */ -#if !defined LWIP_IPV6_DHCP6 || defined __DOXYGEN__ -#define LWIP_IPV6_DHCP6 0 -#endif - -/* - --------------------------------------- - ---------- Hook options --------------- - --------------------------------------- -*/ - -/** - * @defgroup lwip_opts_hooks Hooks - * @ingroup lwip_opts_infrastructure - * Hooks are undefined by default, define them to a function if you need them. - * @{ - */ - -/** - * LWIP_HOOK_FILENAME: Custom filename to #include in files that provide hooks. - * Declare your hook function prototypes in there, you may also #include all headers - * providing data types that are need in this file. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h" -#endif - -/** - * LWIP_HOOK_TCP_ISN: - * Hook for generation of the Initial Sequence Number (ISN) for a new TCP - * connection. The default lwIP ISN generation algorithm is very basic and may - * allow for TCP spoofing attacks. This hook provides the means to implement - * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn), - * or any other desired algorithm as a replacement. - * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for - * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n - * Signature: u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port); - * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n - * Arguments: - * - local_ip: pointer to the local IP address of the connection - * - local_port: local port number of the connection (host-byte order) - * - remote_ip: pointer to the remote IP address of the connection - * - remote_port: remote port number of the connection (host-byte order)\n - * Return value: - * - the 32-bit Initial Sequence Number to use for the new TCP connection. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port) -#endif - -/** - * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): - * - called from ip_input() (IPv4) - * - pbuf: received struct pbuf passed to ip_input() - * - input_netif: struct netif on which the packet has been received - * Return values: - * - 0: Hook has not consumed the packet, packet is processed as normal - * - != 0: Hook has consumed the packet. - * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook - * (i.e. free it when done). - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif) -#endif - -/** - * LWIP_HOOK_IP4_ROUTE(dest): - * - called from ip_route() (IPv4) - * - dest: destination IPv4 address - * Returns the destination netif or NULL if no destination netif is found. In - * that case, ip_route() continues as normal. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_IP4_ROUTE() -#endif - -/** - * LWIP_HOOK_IP4_ROUTE_SRC(dest, src): - * - source-based routing for IPv4 (see LWIP_HOOK_IP4_ROUTE(), src may be NULL) - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_IP4_ROUTE_SRC(dest, src) -#endif - -/** - * LWIP_HOOK_ETHARP_GET_GW(netif, dest): - * - called from etharp_output() (IPv4) - * - netif: the netif used for sending - * - dest: the destination IPv4 address - * Returns the IPv4 address of the gateway to handle the specified destination - * IPv4 address. If NULL is returned, the netif's default gateway is used. - * The returned address MUST be directly reachable on the specified netif! - * This function is meant to implement advanced IPv4 routing together with - * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is - * not part of lwIP but can e.g. be hidden in the netif's state argument. -*/ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_ETHARP_GET_GW(netif, dest) -#endif - -/** - * LWIP_HOOK_IP6_INPUT(pbuf, input_netif): - * - called from ip6_input() (IPv6) - * - pbuf: received struct pbuf passed to ip6_input() - * - input_netif: struct netif on which the packet has been received - * Return values: - * - 0: Hook has not consumed the packet, packet is processed as normal - * - != 0: Hook has consumed the packet. - * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook - * (i.e. free it when done). - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif) -#endif - -/** - * LWIP_HOOK_IP6_ROUTE(src, dest): - * - called from ip6_route() (IPv6) - * - src: sourc IPv6 address - * - dest: destination IPv6 address - * Returns the destination netif or NULL if no destination netif is found. In - * that case, ip6_route() continues as normal. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_IP6_ROUTE(src, dest) -#endif - -/** - * LWIP_HOOK_ND6_GET_GW(netif, dest): - * - called from nd6_get_next_hop_entry() (IPv6) - * - netif: the netif used for sending - * - dest: the destination IPv6 address - * Returns the IPv6 address of the next hop to handle the specified destination - * IPv6 address. If NULL is returned, a NDP-discovered router is used instead. - * The returned address MUST be directly reachable on the specified netif! - * This function is meant to implement advanced IPv6 routing together with - * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is - * not part of lwIP but can e.g. be hidden in the netif's state argument. -*/ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_ND6_GET_GW(netif, dest) -#endif - -/** - * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr): - * - called from ethernet_input() if VLAN support is enabled - * - netif: struct netif on which the packet has been received - * - eth_hdr: struct eth_hdr of the packet - * - vlan_hdr: struct eth_vlan_hdr of the packet - * Return values: - * - 0: Packet must be dropped. - * - != 0: Packet must be accepted. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr) -#endif - -/** - * LWIP_HOOK_VLAN_SET: - * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data - * on per-netif basis to implement this callback, see @ref netif_cd. - * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n - * Signature: s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n - * Arguments: - * - netif: struct netif that the packet will be sent through - * - p: struct pbuf packet to be sent - * - src: source eth address - * - dst: destination eth address - * - eth_type: ethernet type to packet to be sent\n - * - * - * Return values: - * - <0: Packet shall not contain VLAN header. - * - 0 <= return value <= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order. - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type) -#endif - -/** - * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type): - * - called from memp_free() when a memp pool was empty and an item is now available - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type) -#endif - -/** - * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif): - * Called from ethernet_input() when an unknown eth type is encountered. - * Return ERR_OK if packet is accepted, any error code otherwise. - * Payload points to ethernet header! - */ -#ifdef __DOXYGEN__ -#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif) -#endif -/** - * @} - */ - -/* - --------------------------------------- - ---------- Debugging options ---------- - --------------------------------------- -*/ -/** - * @defgroup lwip_opts_debugmsg Debug messages - * @ingroup lwip_opts_debug - * @{ - */ -/** - * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is - * compared against this value. If it is smaller, then debugging - * messages are written. - * @see debugging_levels - */ -#if !defined LWIP_DBG_MIN_LEVEL || defined __DOXYGEN__ -#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL -#endif - -/** - * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable - * debug messages of certain types. - * @see debugging_levels - */ -#if !defined LWIP_DBG_TYPES_ON || defined __DOXYGEN__ -#define LWIP_DBG_TYPES_ON LWIP_DBG_ON -#endif - -/** - * ETHARP_DEBUG: Enable debugging in etharp.c. - */ -#if !defined ETHARP_DEBUG || defined __DOXYGEN__ -#define ETHARP_DEBUG LWIP_DBG_OFF -#endif - -/** - * NETIF_DEBUG: Enable debugging in netif.c. - */ -#if !defined NETIF_DEBUG || defined __DOXYGEN__ -#define NETIF_DEBUG LWIP_DBG_OFF -#endif - -/** - * PBUF_DEBUG: Enable debugging in pbuf.c. - */ -#if !defined PBUF_DEBUG || defined __DOXYGEN__ -#define PBUF_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_LIB_DEBUG: Enable debugging in api_lib.c. - */ -#if !defined API_LIB_DEBUG || defined __DOXYGEN__ -#define API_LIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_MSG_DEBUG: Enable debugging in api_msg.c. - */ -#if !defined API_MSG_DEBUG || defined __DOXYGEN__ -#define API_MSG_DEBUG LWIP_DBG_OFF -#endif - -/** - * SOCKETS_DEBUG: Enable debugging in sockets.c. - */ -#if !defined SOCKETS_DEBUG || defined __DOXYGEN__ -#define SOCKETS_DEBUG LWIP_DBG_OFF -#endif - -/** - * ICMP_DEBUG: Enable debugging in icmp.c. - */ -#if !defined ICMP_DEBUG || defined __DOXYGEN__ -#define ICMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IGMP_DEBUG: Enable debugging in igmp.c. - */ -#if !defined IGMP_DEBUG || defined __DOXYGEN__ -#define IGMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * INET_DEBUG: Enable debugging in inet.c. - */ -#if !defined INET_DEBUG || defined __DOXYGEN__ -#define INET_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_DEBUG: Enable debugging for IP. - */ -#if !defined IP_DEBUG || defined __DOXYGEN__ -#define IP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. - */ -#if !defined IP_REASS_DEBUG || defined __DOXYGEN__ -#define IP_REASS_DEBUG LWIP_DBG_OFF -#endif - -/** - * RAW_DEBUG: Enable debugging in raw.c. - */ -#if !defined RAW_DEBUG || defined __DOXYGEN__ -#define RAW_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEM_DEBUG: Enable debugging in mem.c. - */ -#if !defined MEM_DEBUG || defined __DOXYGEN__ -#define MEM_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEMP_DEBUG: Enable debugging in memp.c. - */ -#if !defined MEMP_DEBUG || defined __DOXYGEN__ -#define MEMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SYS_DEBUG: Enable debugging in sys.c. - */ -#if !defined SYS_DEBUG || defined __DOXYGEN__ -#define SYS_DEBUG LWIP_DBG_OFF -#endif - -/** - * TIMERS_DEBUG: Enable debugging in timers.c. - */ -#if !defined TIMERS_DEBUG || defined __DOXYGEN__ -#define TIMERS_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_DEBUG: Enable debugging for TCP. - */ -#if !defined TCP_DEBUG || defined __DOXYGEN__ -#define TCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. - */ -#if !defined TCP_INPUT_DEBUG || defined __DOXYGEN__ -#define TCP_INPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. - */ -#if !defined TCP_FR_DEBUG || defined __DOXYGEN__ -#define TCP_FR_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit - * timeout. - */ -#if !defined TCP_RTO_DEBUG || defined __DOXYGEN__ -#define TCP_RTO_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. - */ -#if !defined TCP_CWND_DEBUG || defined __DOXYGEN__ -#define TCP_CWND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. - */ -#if !defined TCP_WND_DEBUG || defined __DOXYGEN__ -#define TCP_WND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. - */ -#if !defined TCP_OUTPUT_DEBUG || defined __DOXYGEN__ -#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. - */ -#if !defined TCP_RST_DEBUG || defined __DOXYGEN__ -#define TCP_RST_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. - */ -#if !defined TCP_QLEN_DEBUG || defined __DOXYGEN__ -#define TCP_QLEN_DEBUG LWIP_DBG_OFF -#endif - -/** - * UDP_DEBUG: Enable debugging in UDP. - */ -#if !defined UDP_DEBUG || defined __DOXYGEN__ -#define UDP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCPIP_DEBUG: Enable debugging in tcpip.c. - */ -#if !defined TCPIP_DEBUG || defined __DOXYGEN__ -#define TCPIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SLIP_DEBUG: Enable debugging in slipif.c. - */ -#if !defined SLIP_DEBUG || defined __DOXYGEN__ -#define SLIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * DHCP_DEBUG: Enable debugging in dhcp.c. - */ -#if !defined DHCP_DEBUG || defined __DOXYGEN__ -#define DHCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * AUTOIP_DEBUG: Enable debugging in autoip.c. - */ -#if !defined AUTOIP_DEBUG || defined __DOXYGEN__ -#define AUTOIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * DNS_DEBUG: Enable debugging for DNS. - */ -#if !defined DNS_DEBUG || defined __DOXYGEN__ -#define DNS_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP6_DEBUG: Enable debugging for IPv6. - */ -#if !defined IP6_DEBUG || defined __DOXYGEN__ -#define IP6_DEBUG LWIP_DBG_OFF -#endif -/** - * @} - */ - -/* - -------------------------------------------------- - ---------- Performance tracking options ---------- - -------------------------------------------------- -*/ -/** - * @defgroup lwip_opts_perf Performance - * @ingroup lwip_opts_debug - * @{ - */ -/** - * LWIP_PERF: Enable performance testing for lwIP - * (if enabled, arch/perf.h is included) - */ -#if !defined LWIP_PERF || defined __DOXYGEN__ -#define LWIP_PERF 0 -#endif -/** - * @} - */ - -#endif /* LWIP_HDR_OPT_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/pbuf.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/pbuf.h deleted file mode 100644 index 90610461ea5c0ca1217b0f74cd6eed6e736cd243..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/pbuf.h +++ /dev/null @@ -1,263 +0,0 @@ -/** - * @file - * pbuf API - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef LWIP_HDR_PBUF_H -#define LWIP_HDR_PBUF_H - -#include "lwip/opt.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type - * but they are allocated by external code (initialised by calling - * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they - * are freed by calling pbuf_custom->custom_free_function(). - * Currently, the pbuf_custom code is only needed for one specific configuration - * of IP_FRAG, unless required by external driver/application code. */ -#ifndef LWIP_SUPPORT_CUSTOM_PBUF -#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)) -#endif - -/* @todo: We need a mechanism to prevent wasting memory in every pbuf - (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */ - -#define PBUF_TRANSPORT_HLEN 20 -#if LWIP_IPV6 -#define PBUF_IP_HLEN 40 -#else -#define PBUF_IP_HLEN 20 -#endif - -/** - * @ingroup pbuf - * Enumeration of pbuf layers - */ -typedef enum { - /** Includes spare room for transport layer header, e.g. UDP header. - * Use this if you intend to pass the pbuf to functions like udp_send(). - */ - PBUF_TRANSPORT, - /** Includes spare room for IP header. - * Use this if you intend to pass the pbuf to functions like raw_send(). - */ - PBUF_IP, - /** Includes spare room for link layer header (ethernet header). - * Use this if you intend to pass the pbuf to functions like ethernet_output(). - * @see PBUF_LINK_HLEN - */ - PBUF_LINK, - /** Includes spare room for additional encapsulation header before ethernet - * headers (e.g. 802.11). - * Use this if you intend to pass the pbuf to functions like netif->linkoutput(). - * @see PBUF_LINK_ENCAPSULATION_HLEN - */ - PBUF_RAW_TX, - /** Use this for input packets in a netif driver when calling netif->input() - * in the most common case - ethernet-layer netif driver. */ - PBUF_RAW -} pbuf_layer; - -/** - * @ingroup pbuf - * Enumeration of pbuf types - */ -typedef enum { - /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload - are allocated in one piece of contiguous memory (so the first payload byte - can be calculated from struct pbuf). - pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might - change in future versions). - This should be used for all OUTGOING packets (TX).*/ - PBUF_RAM, - /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in - totally different memory areas. Since it points to ROM, payload does not - have to be copied when queued for transmission. */ - PBUF_ROM, - /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change - so it has to be duplicated when queued before transmitting, depending on - who has a 'ref' to it. */ - PBUF_REF, - /** pbuf payload refers to RAM. This one comes from a pool and should be used - for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct - pbuf and its payload are allocated in one piece of contiguous memory (so - the first payload byte can be calculated from struct pbuf). - Don't use this for TX, if the pool becomes empty e.g. because of TCP queuing, - you are unable to receive TCP acks! */ - PBUF_POOL -} pbuf_type; - - -/** indicates this packet's data should be immediately passed to the application */ -#define PBUF_FLAG_PUSH 0x01U -/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function() - when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */ -#define PBUF_FLAG_IS_CUSTOM 0x02U -/** indicates this pbuf is UDP multicast to be looped back */ -#define PBUF_FLAG_MCASTLOOP 0x04U -/** indicates this pbuf was received as link-level broadcast */ -#define PBUF_FLAG_LLBCAST 0x08U -/** indicates this pbuf was received as link-level multicast */ -#define PBUF_FLAG_LLMCAST 0x10U -/** indicates this pbuf includes a TCP FIN flag */ -#define PBUF_FLAG_TCP_FIN 0x20U - -/** Main packet buffer struct */ -struct pbuf { - /** next pbuf in singly linked pbuf chain */ - struct pbuf *next; - - /** pointer to the actual data in the buffer */ - void *payload; - - /** - * total length of this buffer and all next buffers in chain - * belonging to the same packet. - * - * For non-queue packet chains this is the invariant: - * p->tot_len == p->len + (p->next? p->next->tot_len: 0) - */ - u16_t tot_len; - - /** length of this buffer */ - u16_t len; - - /** pbuf_type as u8_t instead of enum to save space */ - u8_t /*pbuf_type*/ type; - - /** misc flags */ - u8_t flags; - - /** - * the reference count always equals the number of pointers - * that refer to this pbuf. This can be pointers from an application, - * the stack itself, or pbuf->next pointers from a chain. - */ - u16_t ref; -}; - - -/** Helper struct for const-correctness only. - * The only meaning of this one is to provide a const payload pointer - * for PBUF_ROM type. - */ -struct pbuf_rom { - /** next pbuf in singly linked pbuf chain */ - struct pbuf *next; - - /** pointer to the actual data in the buffer */ - const void *payload; -}; - -#if LWIP_SUPPORT_CUSTOM_PBUF -/** Prototype for a function to free a custom pbuf */ -typedef void (*pbuf_free_custom_fn)(struct pbuf *p); - -/** A custom pbuf: like a pbuf, but following a function pointer to free it. */ -struct pbuf_custom { - /** The actual pbuf */ - struct pbuf pbuf; - /** This function is called when pbuf_free deallocates this pbuf(_custom) */ - pbuf_free_custom_fn custom_free_function; -}; -#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ - -/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ -#ifndef PBUF_POOL_FREE_OOSEQ -#define PBUF_POOL_FREE_OOSEQ 1 -#endif /* PBUF_POOL_FREE_OOSEQ */ -#if LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ -extern volatile u8_t pbuf_free_ooseq_pending; -void pbuf_free_ooseq(void); -/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() - at regular intervals from main level to check if ooseq pbufs need to be - freed! */ -#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \ - /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \ - ooseq queued pbufs now */ \ - pbuf_free_ooseq(); }}while(0) -#else /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ */ - /* Otherwise declare an empty PBUF_CHECK_FREE_OOSEQ */ - #define PBUF_CHECK_FREE_OOSEQ() -#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ*/ - -/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ -#define pbuf_init() - -struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type); -#if LWIP_SUPPORT_CUSTOM_PBUF -struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, - struct pbuf_custom *p, void *payload_mem, - u16_t payload_mem_len); -#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ -void pbuf_realloc(struct pbuf *p, u16_t size); -u8_t pbuf_header(struct pbuf *p, s16_t header_size); -u8_t pbuf_header_force(struct pbuf *p, s16_t header_size); -void pbuf_ref(struct pbuf *p); -u8_t pbuf_free(struct pbuf *p); -u16_t pbuf_clen(const struct pbuf *p); -void pbuf_cat(struct pbuf *head, struct pbuf *tail); -void pbuf_chain(struct pbuf *head, struct pbuf *tail); -struct pbuf *pbuf_dechain(struct pbuf *p); -err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from); -u16_t pbuf_copy_partial(const struct pbuf *p, void *dataptr, u16_t len, u16_t offset); -err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); -err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset); -struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset); -struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); -#if LWIP_CHECKSUM_ON_COPY -err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, - u16_t len, u16_t *chksum); -#endif /* LWIP_CHECKSUM_ON_COPY */ -#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE -void pbuf_split_64k(struct pbuf *p, struct pbuf **rest); -#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ - -u8_t pbuf_get_at(const struct pbuf* p, u16_t offset); -int pbuf_try_get_at(const struct pbuf* p, u16_t offset); -void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data); -u16_t pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n); -u16_t pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset); -u16_t pbuf_strstr(const struct pbuf* p, const char* substr); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PBUF_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ping.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ping.h deleted file mode 100644 index 318414a1b8be4bbae5d841fd99af835da1816820..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/ping.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef LWIP_PING_H -#define LWIP_PING_H - -extern int ping(char* target_name, uint32_t times, size_t size); - -#endif /* LWIP_PING_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/api_msg.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/api_msg.h deleted file mode 100644 index f12b8b7d4f732a77821ca87c5258f5129d0c1445..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/api_msg.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - * @file - * netconn API lwIP internal implementations (do not use in application code) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_API_MSG_H -#define LWIP_HDR_API_MSG_H - -#include "lwip/opt.h" - -#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ -/* Note: Netconn API is always available when sockets are enabled - - * sockets are implemented on top of them */ - -#include "lwip/arch.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" -#include "lwip/sys.h" -#include "lwip/igmp.h" -#include "lwip/api.h" -#include "lwip/priv/tcpip_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_MPU_COMPATIBLE -#if LWIP_NETCONN_SEM_PER_THREAD -#define API_MSG_M_DEF_SEM(m) *m -#else -#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m) -#endif -#else /* LWIP_MPU_COMPATIBLE */ -#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m) -#endif /* LWIP_MPU_COMPATIBLE */ - -/* For the netconn API, these values are use as a bitmask! */ -#define NETCONN_SHUT_RD 1 -#define NETCONN_SHUT_WR 2 -#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR) - -/* IP addresses and port numbers are expected to be in - * the same byte order as in the corresponding pcb. - */ -/** This struct includes everything that is necessary to execute a function - for a netconn in another thread context (mainly used to process netconns - in the tcpip_thread context to be thread safe). */ -struct api_msg { - /** The netconn which to process - always needed: it includes the semaphore - which is used to block the application thread until the function finished. */ - struct netconn *conn; - /** The return value of the function executed in tcpip_thread. */ - err_t err; - /** Depending on the executed function, one of these union members is used */ - union { - /** used for lwip_netconn_do_send */ - struct netbuf *b; - /** used for lwip_netconn_do_newconn */ - struct { - u8_t proto; - } n; - /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */ - struct { - API_MSG_M_DEF_C(ip_addr_t, ipaddr); - u16_t port; - } bc; - /** used for lwip_netconn_do_getaddr */ - struct { - ip_addr_t API_MSG_M_DEF(ipaddr); - u16_t API_MSG_M_DEF(port); - u8_t local; - } ad; - /** used for lwip_netconn_do_write */ - struct { - const void *dataptr; - size_t len; - u8_t apiflags; -#if LWIP_SO_SNDTIMEO - u32_t time_started; -#endif /* LWIP_SO_SNDTIMEO */ - } w; - /** used for lwip_netconn_do_recv */ - struct { - u32_t len; - } r; -#if LWIP_TCP - /** used for lwip_netconn_do_close (/shutdown) */ - struct { - u8_t shut; -#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER - u32_t time_started; -#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - u8_t polls_left; -#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ - } sd; -#endif /* LWIP_TCP */ -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) - /** used for lwip_netconn_do_join_leave_group */ - struct { - API_MSG_M_DEF_C(ip_addr_t, multiaddr); - API_MSG_M_DEF_C(ip_addr_t, netif_addr); - enum netconn_igmp join_or_leave; - } jl; -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ -#if TCP_LISTEN_BACKLOG - struct { - u8_t backlog; - } lb; -#endif /* TCP_LISTEN_BACKLOG */ - } msg; -#if LWIP_NETCONN_SEM_PER_THREAD - sys_sem_t* op_completed_sem; -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ -}; - -#if LWIP_NETCONN_SEM_PER_THREAD -#define LWIP_API_MSG_SEM(msg) ((msg)->op_completed_sem) -#else /* LWIP_NETCONN_SEM_PER_THREAD */ -#define LWIP_API_MSG_SEM(msg) (&(msg)->conn->op_completed) -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ - - -#if LWIP_DNS -/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn, - it has its own struct (to avoid struct api_msg getting bigger than necessary). - lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg - (see netconn_gethostbyname). */ -struct dns_api_msg { - /** Hostname to query or dotted IP address string */ -#if LWIP_MPU_COMPATIBLE - char name[DNS_MAX_NAME_LENGTH]; -#else /* LWIP_MPU_COMPATIBLE */ - const char *name; -#endif /* LWIP_MPU_COMPATIBLE */ - /** The resolved address is stored here */ - ip_addr_t API_MSG_M_DEF(addr); -#if LWIP_IPV4 && LWIP_IPV6 - /** Type of resolve call */ - u8_t dns_addrtype; -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - /** This semaphore is posted when the name is resolved, the application thread - should wait on it. */ - sys_sem_t API_MSG_M_DEF_SEM(sem); - /** Errors are given back here */ - err_t API_MSG_M_DEF(err); -}; -#endif /* LWIP_DNS */ - -#if LWIP_TCP -extern u8_t netconn_aborted; -#endif /* LWIP_TCP */ - -void lwip_netconn_do_newconn (void *m); -void lwip_netconn_do_delconn (void *m); -void lwip_netconn_do_bind (void *m); -void lwip_netconn_do_connect (void *m); -void lwip_netconn_do_disconnect (void *m); -void lwip_netconn_do_listen (void *m); -void lwip_netconn_do_send (void *m); -void lwip_netconn_do_recv (void *m); -#if TCP_LISTEN_BACKLOG -void lwip_netconn_do_accepted (void *m); -#endif /* TCP_LISTEN_BACKLOG */ -void lwip_netconn_do_write (void *m); -void lwip_netconn_do_getaddr (void *m); -void lwip_netconn_do_close (void *m); -void lwip_netconn_do_shutdown (void *m); -#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) -void lwip_netconn_do_join_leave_group(void *m); -#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ - -#if LWIP_DNS -void lwip_netconn_do_gethostbyname(void *arg); -#endif /* LWIP_DNS */ - -struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); -void netconn_free(struct netconn *conn); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETCONN || LWIP_SOCKET */ - -#endif /* LWIP_HDR_API_MSG_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_priv.h deleted file mode 100644 index cc04079cd49d962c6ff524c6b5e7fb70c1f628eb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_priv.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * @file - * memory pools lwIP internal implementations (do not use in application code) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef LWIP_HDR_MEMP_PRIV_H -#define LWIP_HDR_MEMP_PRIV_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include "lwip/mem.h" - -#if MEMP_OVERFLOW_CHECK -/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning - * and at the end of each element, initialize them as 0xcd and check - * them later. */ -/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free, - * every single element in each pool is checked! - * This is VERY SLOW but also very helpful. */ -/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in - * lwipopts.h to change the amount reserved for checking. */ -#ifndef MEMP_SANITY_REGION_BEFORE -#define MEMP_SANITY_REGION_BEFORE 16 -#endif /* MEMP_SANITY_REGION_BEFORE*/ -#if MEMP_SANITY_REGION_BEFORE > 0 -#define MEMP_SANITY_REGION_BEFORE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE) -#else -#define MEMP_SANITY_REGION_BEFORE_ALIGNED 0 -#endif /* MEMP_SANITY_REGION_BEFORE*/ -#ifndef MEMP_SANITY_REGION_AFTER -#define MEMP_SANITY_REGION_AFTER 16 -#endif /* MEMP_SANITY_REGION_AFTER*/ -#if MEMP_SANITY_REGION_AFTER > 0 -#define MEMP_SANITY_REGION_AFTER_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER) -#else -#define MEMP_SANITY_REGION_AFTER_ALIGNED 0 -#endif /* MEMP_SANITY_REGION_AFTER*/ - -/* MEMP_SIZE: save space for struct memp and for sanity check */ -#define MEMP_SIZE (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED) -#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED) - -#else /* MEMP_OVERFLOW_CHECK */ - -/* No sanity checks - * We don't need to preserve the struct memp while not allocated, so we - * can save a little space and set MEMP_SIZE to 0. - */ -#define MEMP_SIZE 0 -#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) - -#endif /* MEMP_OVERFLOW_CHECK */ - -#if !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK -struct memp { - struct memp *next; -#if MEMP_OVERFLOW_CHECK - const char *file; - int line; -#endif /* MEMP_OVERFLOW_CHECK */ -}; -#endif /* !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK */ - -#if MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS -/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ -typedef enum { - /* Get the first (via: - MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ - MEMP_POOL_HELPER_FIRST = ((u8_t) -#define LWIP_MEMPOOL(name,num,size,desc) -#define LWIP_MALLOC_MEMPOOL_START 1 -#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 -#define LWIP_MALLOC_MEMPOOL_END -#include "lwip/priv/memp_std.h" - ) , - /* Get the last (via: - MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ - MEMP_POOL_HELPER_LAST = ((u8_t) -#define LWIP_MEMPOOL(name,num,size,desc) -#define LWIP_MALLOC_MEMPOOL_START -#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * -#define LWIP_MALLOC_MEMPOOL_END 1 -#include "lwip/priv/memp_std.h" - ) -} memp_pool_helper_t; - -/* The actual start and stop values are here (cast them over) - We use this helper type and these defines so we can avoid using const memp_t values */ -#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) -#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) -#endif /* MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS */ - -/** Memory pool descriptor */ -struct memp_desc { -#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY - /** Textual description */ - const char *desc; -#else - const char *desc; -#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY */ -#if MEMP_STATS - /** Statistics */ - struct stats_mem *stats; -#endif - - /** Element size */ - u16_t size; - -#if !MEMP_MEM_MALLOC - /** Number of elements */ - u16_t num; - - /** Base address */ - u8_t *base; - - /** First free element of each pool. Elements form a linked list. */ - struct memp **tab; -#endif /* MEMP_MEM_MALLOC */ -}; - -#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY -#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc), -#else -#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc), -#endif - -#if MEMP_STATS -#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) static struct stats_mem name; -#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) &name, -#else -#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) -#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) -#endif - -void memp_init_pool(const struct memp_desc *desc); - -#if MEMP_OVERFLOW_CHECK -void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line); -#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__) -#else -void *memp_malloc_pool(const struct memp_desc *desc); -#endif -void memp_free_pool(const struct memp_desc* desc, void *mem); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_MEMP_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_std.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_std.h deleted file mode 100644 index ce9fd500312fb3e1c18ef40108892bba2a80109d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/memp_std.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * @file - * lwIP internal memory pools (do not use in application code) - * This file is deliberately included multiple times: once with empty - * definition of LWIP_MEMPOOL() to handle all includes and multiple times - * to build up various lists of mem pools. - */ - -/* - * SETUP: Make sure we define everything we will need. - * - * We have create three types of pools: - * 1) MEMPOOL - standard pools - * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c - * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct - * - * If the include'r doesn't require any special treatment of each of the types - * above, then will declare #2 & #3 to be just standard mempools. - */ -#ifndef LWIP_MALLOC_MEMPOOL -/* This treats "malloc pools" just like any other pool. - The pools are a little bigger to provide 'size' as the amount of user data. */ -#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size) -#define LWIP_MALLOC_MEMPOOL_START -#define LWIP_MALLOC_MEMPOOL_END -#endif /* LWIP_MALLOC_MEMPOOL */ - -#ifndef LWIP_PBUF_MEMPOOL -/* This treats "pbuf pools" just like any other pool. - * Allocates buffers for a pbuf struct AND a payload size */ -#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc) -#endif /* LWIP_PBUF_MEMPOOL */ - - -/* - * A list of internal pools used by LWIP. - * - * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) - * creates a pool name MEMP_pool_name. description is used in stats.c - */ -#if LWIP_RAW -LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") -#endif /* LWIP_RAW */ - -#if LWIP_UDP -LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") -#endif /* LWIP_UDP */ - -#if LWIP_TCP -LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") -LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") -LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") -#endif /* LWIP_TCP */ - -#if LWIP_IPV4 && IP_REASSEMBLY -LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") -#endif /* LWIP_IPV4 && IP_REASSEMBLY */ -#if (IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG) -LWIP_MEMPOOL(FRAG_PBUF, MEMP_NUM_FRAG_PBUF, sizeof(struct pbuf_custom_ref),"FRAG_PBUF") -#endif /* IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF || (LWIP_IPV6 && LWIP_IPV6_FRAG) */ - -#if LWIP_NETCONN || LWIP_SOCKET -LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") -LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") -#endif /* LWIP_NETCONN || LWIP_SOCKET */ - -#if NO_SYS==0 -LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") -#if LWIP_MPU_COMPATIBLE -LWIP_MEMPOOL(API_MSG, MEMP_NUM_API_MSG, sizeof(struct api_msg), "API_MSG") -#if LWIP_DNS -LWIP_MEMPOOL(DNS_API_MSG, MEMP_NUM_DNS_API_MSG, sizeof(struct dns_api_msg), "DNS_API_MSG") -#endif -#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING -LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA") -#endif -#if LWIP_NETIF_API -LWIP_MEMPOOL(NETIFAPI_MSG, MEMP_NUM_NETIFAPI_MSG, sizeof(struct netifapi_msg), "NETIFAPI_MSG") -#endif -#endif /* LWIP_MPU_COMPATIBLE */ -#if !LWIP_TCPIP_CORE_LOCKING_INPUT -LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") -#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ -#endif /* NO_SYS==0 */ - -#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING -LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") -#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */ - -#if LWIP_IGMP -LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") -#endif /* LWIP_IGMP */ - -#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM -LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") -#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ - -#if LWIP_DNS && LWIP_SOCKET -LWIP_MEMPOOL(NETDB, MEMP_NUM_NETDB, NETDB_ELEM_SIZE, "NETDB") -#endif /* LWIP_DNS && LWIP_SOCKET */ -#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC -LWIP_MEMPOOL(LOCALHOSTLIST, MEMP_NUM_LOCALHOSTLIST, LOCALHOSTLIST_ELEM_SIZE, "LOCALHOSTLIST") -#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -#if LWIP_IPV6 && LWIP_ND6_QUEUEING -LWIP_MEMPOOL(ND6_QUEUE, MEMP_NUM_ND6_QUEUE, sizeof(struct nd6_q_entry), "ND6_QUEUE") -#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */ - -#if LWIP_IPV6 && LWIP_IPV6_REASS -LWIP_MEMPOOL(IP6_REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip6_reassdata), "IP6_REASSDATA") -#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ - -#if LWIP_IPV6 && LWIP_IPV6_MLD -LWIP_MEMPOOL(MLD6_GROUP, MEMP_NUM_MLD6_GROUP, sizeof(struct mld_group), "MLD6_GROUP") -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ - - -/* - * A list of pools of pbuf's used by LWIP. - * - * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) - * creates a pool name MEMP_pool_name. description is used in stats.c - * This allocates enough space for the pbuf struct and a payload. - * (Example: pbuf_payload_size=0 allocates only size for the struct) - */ -LWIP_PBUF_MEMPOOL(PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM") -LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") - - -/* - * Allow for user-defined pools; this must be explicitly set in lwipopts.h - * since the default is to NOT look for lwippools.h - */ -#if MEMP_USE_CUSTOM_POOLS -#include "lwippools.h" -#endif /* MEMP_USE_CUSTOM_POOLS */ - -/* - * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later - * (#undef is ignored for something that is not defined) - */ -#undef LWIP_MEMPOOL -#undef LWIP_MALLOC_MEMPOOL -#undef LWIP_MALLOC_MEMPOOL_START -#undef LWIP_MALLOC_MEMPOOL_END -#undef LWIP_PBUF_MEMPOOL diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/nd6_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/nd6_priv.h deleted file mode 100644 index 4bda0b793a36d0e00ffdd27a4e58054146e947c3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/nd6_priv.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * @file - * - * Neighbor discovery and stateless address autoconfiguration for IPv6. - * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 - * (Address autoconfiguration). - */ - -/* - * Copyright (c) 2010 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_ND6_PRIV_H -#define LWIP_HDR_ND6_PRIV_H - -#include "lwip/opt.h" - -#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_ND6_QUEUEING -/** struct for queueing outgoing packets for unknown address - * defined here to be accessed by memp.h - */ -struct nd6_q_entry { - struct nd6_q_entry *next; - struct pbuf *p; -}; -#endif /* LWIP_ND6_QUEUEING */ - -/** Struct for tables. */ -struct nd6_neighbor_cache_entry { - ip6_addr_t next_hop_address; - struct netif *netif; - u8_t lladdr[NETIF_MAX_HWADDR_LEN]; - /*u32_t pmtu;*/ -#if LWIP_ND6_QUEUEING - /** Pointer to queue of pending outgoing packets on this entry. */ - struct nd6_q_entry *q; -#else /* LWIP_ND6_QUEUEING */ - /** Pointer to a single pending outgoing packet on this entry. */ - struct pbuf *q; -#endif /* LWIP_ND6_QUEUEING */ - u8_t state; - u8_t isrouter; - union { - u32_t reachable_time; /* in ms since value may originate from network packet */ - u32_t delay_time; /* ticks (ND6_TMR_INTERVAL) */ - u32_t probes_sent; - u32_t stale_time; /* ticks (ND6_TMR_INTERVAL) */ - } counter; -}; - -struct nd6_destination_cache_entry { - ip6_addr_t destination_addr; - ip6_addr_t next_hop_addr; - u16_t pmtu; - u32_t age; -}; - -struct nd6_prefix_list_entry { - ip6_addr_t prefix; - struct netif *netif; - u32_t invalidation_timer; /* in ms since value may originate from network packet */ -#if LWIP_IPV6_AUTOCONFIG - u8_t flags; -#define ND6_PREFIX_AUTOCONFIG_AUTONOMOUS 0x01 -#define ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED 0x02 -#define ND6_PREFIX_AUTOCONFIG_ADDRESS_DUPLICATE 0x04 -#endif /* LWIP_IPV6_AUTOCONFIG */ -}; - -struct nd6_router_list_entry { - struct nd6_neighbor_cache_entry *neighbor_entry; - u32_t invalidation_timer; /* in ms since value may originate from network packet */ - u8_t flags; -}; - -enum nd6_neighbor_cache_entry_state { - ND6_NO_ENTRY = 0, - ND6_INCOMPLETE, - ND6_REACHABLE, - ND6_STALE, - ND6_DELAY, - ND6_PROBE -}; - -/* Router tables. */ -/* @todo make these static? and entries accessible through API? */ -extern struct nd6_neighbor_cache_entry neighbor_cache[]; -extern struct nd6_destination_cache_entry destination_cache[]; -extern struct nd6_prefix_list_entry prefix_list[]; -extern struct nd6_router_list_entry default_router_list[]; - -/* Default values, can be updated by a RA message. */ -extern u32_t reachable_time; -extern u32_t retrans_timer; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 */ - -#endif /* LWIP_HDR_ND6_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcp_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcp_priv.h deleted file mode 100644 index 73e8967e47d747b7cf866d571266f53b825265f3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcp_priv.h +++ /dev/null @@ -1,507 +0,0 @@ -/** - * @file - * TCP internal implementations (do not use in application code) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_TCP_PRIV_H -#define LWIP_HDR_TCP_PRIV_H - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/tcp.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/ip.h" -#include "lwip/icmp.h" -#include "lwip/err.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/prot/tcp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Functions for interfacing with TCP: */ - -/* Lower layer interface to TCP: */ -void tcp_init (void); /* Initialize this module. */ -void tcp_tmr (void); /* Must be called every - TCP_TMR_INTERVAL - ms. (Typically 250 ms). */ -/* It is also possible to call these two functions at the right - intervals (instead of calling tcp_tmr()). */ -void tcp_slowtmr (void); -void tcp_fasttmr (void); - -/* Call this from a netif driver (watch out for threading issues!) that has - returned a memory error on transmit and now has free buffers to send more. - This iterates all active pcbs that had an error and tries to call - tcp_output, so use this with care as it might slow down the system. */ -void tcp_txnow (void); - -/* Only used by IP to pass a TCP segment to TCP: */ -void tcp_input (struct pbuf *p, struct netif *inp); -/* Used within the TCP code only: */ -struct tcp_pcb * tcp_alloc (u8_t prio); -void tcp_abandon (struct tcp_pcb *pcb, int reset); -err_t tcp_send_empty_ack(struct tcp_pcb *pcb); -void tcp_rexmit (struct tcp_pcb *pcb); -void tcp_rexmit_rto (struct tcp_pcb *pcb); -void tcp_rexmit_fast (struct tcp_pcb *pcb); -u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); -err_t tcp_process_refused_data(struct tcp_pcb *pcb); - -/** - * This is the Nagle algorithm: try to combine user data to send as few TCP - * segments as possible. Only send if - * - no previously transmitted data on the connection remains unacknowledged or - * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or - * - the only unsent segment is at least pcb->mss bytes long (or there is more - * than one unsent segment - with lwIP, this can happen although unsent->len < mss) - * - or if we are in fast-retransmit (TF_INFR) - */ -#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ - ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ - (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ - ((tpcb)->unsent->len >= (tpcb)->mss))) || \ - ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \ - ) ? 1 : 0) -#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) - - -#define TCP_SEQ_LT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0) -#define TCP_SEQ_LEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0) -#define TCP_SEQ_GT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0) -#define TCP_SEQ_GEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0) -/* is b<=a<=c? */ -#if 0 /* see bug #10548 */ -#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) -#endif -#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) - -#ifndef TCP_TMR_INTERVAL -#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ -#endif /* TCP_TMR_INTERVAL */ - -#ifndef TCP_FAST_INTERVAL -#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ -#endif /* TCP_FAST_INTERVAL */ - -#ifndef TCP_SLOW_INTERVAL -#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ -#endif /* TCP_SLOW_INTERVAL */ - -#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ -#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ - -#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ - -#ifndef TCP_MSL -#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ -#endif - -/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ -#ifndef TCP_KEEPIDLE_DEFAULT -#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ -#endif - -#ifndef TCP_KEEPINTVL_DEFAULT -#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ -#endif - -#ifndef TCP_KEEPCNT_DEFAULT -#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ -#endif - -#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ - -#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U)) - -/** Flags used on input processing, not on pcb->flags -*/ -#define TF_RESET (u8_t)0x08U /* Connection was reset. */ -#define TF_CLOSED (u8_t)0x10U /* Connection was successfully closed. */ -#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ - - -#if LWIP_EVENT_API - -#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) ret = lwip_tcp_event(arg, (pcb),\ - LWIP_EVENT_ACCEPT, NULL, 0, err) -#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_SENT, NULL, space, ERR_OK) -#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_RECV, (p), 0, (err)) -#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_RECV, NULL, 0, ERR_OK) -#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_CONNECTED, NULL, 0, (err)) -#define TCP_EVENT_POLL(pcb,ret) do { if ((pcb)->state != SYN_RCVD) { \ - ret = lwip_tcp_event((pcb)->callback_arg, (pcb), LWIP_EVENT_POLL, NULL, 0, ERR_OK); \ - } else { \ - ret = ERR_ARG; } } while(0) -#define TCP_EVENT_ERR(last_state,errf,arg,err) do { if (last_state != SYN_RCVD) { \ - lwip_tcp_event((arg), NULL, LWIP_EVENT_ERR, NULL, 0, (err)); } } while(0) - -#else /* LWIP_EVENT_API */ - -#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) \ - do { \ - if((lpcb)->accept != NULL) \ - (ret) = (lpcb)->accept((arg),(pcb),(err)); \ - else (ret) = ERR_ARG; \ - } while (0) - -#define TCP_EVENT_SENT(pcb,space,ret) \ - do { \ - if((pcb)->sent != NULL) \ - (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_RECV(pcb,p,err,ret) \ - do { \ - if((pcb)->recv != NULL) { \ - (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\ - } else { \ - (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ - } \ - } while (0) - -#define TCP_EVENT_CLOSED(pcb,ret) \ - do { \ - if(((pcb)->recv != NULL)) { \ - (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\ - } else { \ - (ret) = ERR_OK; \ - } \ - } while (0) - -#define TCP_EVENT_CONNECTED(pcb,err,ret) \ - do { \ - if((pcb)->connected != NULL) \ - (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_POLL(pcb,ret) \ - do { \ - if((pcb)->poll != NULL) \ - (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_ERR(last_state,errf,arg,err) \ - do { \ - LWIP_UNUSED_ARG(last_state); \ - if((errf) != NULL) \ - (errf)((arg),(err)); \ - } while (0) - -#endif /* LWIP_EVENT_API */ - -/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */ -#if TCP_OVERSIZE && defined(LWIP_DEBUG) -#define TCP_OVERSIZE_DBGCHECK 1 -#else -#define TCP_OVERSIZE_DBGCHECK 0 -#endif - -/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */ -#define TCP_CHECKSUM_ON_COPY (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP) - -/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */ -struct tcp_seg { - struct tcp_seg *next; /* used when putting segments on a queue */ - struct pbuf *p; /* buffer containing data + TCP header */ - u16_t len; /* the TCP length of this segment */ -#if TCP_OVERSIZE_DBGCHECK - u16_t oversize_left; /* Extra bytes available at the end of the last - pbuf in unsent (used for asserting vs. - tcp_pcb.unsent_oversize only) */ -#endif /* TCP_OVERSIZE_DBGCHECK */ -#if TCP_CHECKSUM_ON_COPY - u16_t chksum; - u8_t chksum_swapped; -#endif /* TCP_CHECKSUM_ON_COPY */ - u8_t flags; -#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ -#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ -#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is - checksummed into 'chksum' */ -#define TF_SEG_OPTS_WND_SCALE (u8_t)0x08U /* Include WND SCALE option */ - struct tcp_hdr *tcphdr; /* the TCP header */ -}; - -#define LWIP_TCP_OPT_EOL 0 -#define LWIP_TCP_OPT_NOP 1 -#define LWIP_TCP_OPT_MSS 2 -#define LWIP_TCP_OPT_WS 3 -#define LWIP_TCP_OPT_TS 8 - -#define LWIP_TCP_OPT_LEN_MSS 4 -#if LWIP_TCP_TIMESTAMPS -#define LWIP_TCP_OPT_LEN_TS 10 -#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */ -#else -#define LWIP_TCP_OPT_LEN_TS_OUT 0 -#endif -#if LWIP_WND_SCALE -#define LWIP_TCP_OPT_LEN_WS 3 -#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */ -#else -#define LWIP_TCP_OPT_LEN_WS_OUT 0 -#endif - -#define LWIP_TCP_OPT_LENGTH(flags) \ - (flags & TF_SEG_OPTS_MSS ? LWIP_TCP_OPT_LEN_MSS : 0) + \ - (flags & TF_SEG_OPTS_TS ? LWIP_TCP_OPT_LEN_TS_OUT : 0) + \ - (flags & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT : 0) - -/** This returns a TCP header option for MSS in an u32_t */ -#define TCP_BUILD_MSS_OPTION(mss) lwip_htonl(0x02040000 | ((mss) & 0xFFFF)) - -#if LWIP_WND_SCALE -#define TCPWNDSIZE_F U32_F -#define TCPWND_MAX 0xFFFFFFFFU -#define TCPWND_CHECK16(x) LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF) -#define TCPWND_MIN16(x) ((u16_t)LWIP_MIN((x), 0xFFFF)) -#else /* LWIP_WND_SCALE */ -#define TCPWNDSIZE_F U16_F -#define TCPWND_MAX 0xFFFFU -#define TCPWND_CHECK16(x) -#define TCPWND_MIN16(x) x -#endif /* LWIP_WND_SCALE */ - -/* Global variables: */ -extern struct tcp_pcb *tcp_input_pcb; -extern u32_t tcp_ticks; -extern u8_t tcp_active_pcbs_changed; - -/* The TCP PCB lists. */ -union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ - struct tcp_pcb_listen *listen_pcbs; - struct tcp_pcb *pcbs; -}; -extern struct tcp_pcb *tcp_bound_pcbs; -extern union tcp_listen_pcbs_t tcp_listen_pcbs; -extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a - state in which they accept or send - data. */ -extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ - -#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT 3 -#define NUM_TCP_PCB_LISTS 4 -extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS]; - -/* Axioms about the above lists: - 1) Every TCP PCB that is not CLOSED is in one of the lists. - 2) A PCB is only in one of the lists. - 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. - 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. -*/ -/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB - with a PCB list or removes a PCB from a list, respectively. */ -#ifndef TCP_DEBUG_PCB_LISTS -#define TCP_DEBUG_PCB_LISTS 0 -#endif -#if TCP_DEBUG_PCB_LISTS -#define TCP_REG(pcbs, npcb) do {\ - struct tcp_pcb *tcp_tmp_pcb; \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \ - for (tcp_tmp_pcb = *(pcbs); \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \ - } \ - LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \ - (npcb)->next = *(pcbs); \ - LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \ - *(pcbs) = (npcb); \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - struct tcp_pcb *tcp_tmp_pcb; \ - LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \ - if(*(pcbs) == (npcb)) { \ - *(pcbs) = (*pcbs)->next; \ - } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next == (npcb)) { \ - tcp_tmp_pcb->next = (npcb)->next; \ - break; \ - } \ - } \ - (npcb)->next = NULL; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \ - } while(0) - -#else /* LWIP_DEBUG */ - -#define TCP_REG(pcbs, npcb) \ - do { \ - (npcb)->next = *pcbs; \ - *(pcbs) = (npcb); \ - tcp_timer_needed(); \ - } while (0) - -#define TCP_RMV(pcbs, npcb) \ - do { \ - if(*(pcbs) == (npcb)) { \ - (*(pcbs)) = (*pcbs)->next; \ - } \ - else { \ - struct tcp_pcb *tcp_tmp_pcb; \ - for (tcp_tmp_pcb = *pcbs; \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next == (npcb)) { \ - tcp_tmp_pcb->next = (npcb)->next; \ - break; \ - } \ - } \ - } \ - (npcb)->next = NULL; \ - } while(0) - -#endif /* LWIP_DEBUG */ - -#define TCP_REG_ACTIVE(npcb) \ - do { \ - TCP_REG(&tcp_active_pcbs, npcb); \ - tcp_active_pcbs_changed = 1; \ - } while (0) - -#define TCP_RMV_ACTIVE(npcb) \ - do { \ - TCP_RMV(&tcp_active_pcbs, npcb); \ - tcp_active_pcbs_changed = 1; \ - } while (0) - -#define TCP_PCB_REMOVE_ACTIVE(pcb) \ - do { \ - tcp_pcb_remove(&tcp_active_pcbs, pcb); \ - tcp_active_pcbs_changed = 1; \ - } while (0) - - -/* Internal functions: */ -struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); -void tcp_pcb_purge(struct tcp_pcb *pcb); -void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); - -void tcp_segs_free(struct tcp_seg *seg); -void tcp_seg_free(struct tcp_seg *seg); -struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); - -#define tcp_ack(pcb) \ - do { \ - if((pcb)->flags & TF_ACK_DELAY) { \ - (pcb)->flags &= ~TF_ACK_DELAY; \ - (pcb)->flags |= TF_ACK_NOW; \ - } \ - else { \ - (pcb)->flags |= TF_ACK_DELAY; \ - } \ - } while (0) - -#define tcp_ack_now(pcb) \ - do { \ - (pcb)->flags |= TF_ACK_NOW; \ - } while (0) - -err_t tcp_send_fin(struct tcp_pcb *pcb); -err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags); - -void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); - -void tcp_rst(u32_t seqno, u32_t ackno, - const ip_addr_t *local_ip, const ip_addr_t *remote_ip, - u16_t local_port, u16_t remote_port); - -u32_t tcp_next_iss(struct tcp_pcb *pcb); - -err_t tcp_keepalive(struct tcp_pcb *pcb); -err_t tcp_zero_window_probe(struct tcp_pcb *pcb); -void tcp_trigger_input_pcb_close(void); - -#if TCP_CALCULATE_EFF_SEND_MSS -u16_t tcp_eff_send_mss_impl(u16_t sendmss, const ip_addr_t *dest -#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING - , const ip_addr_t *src -#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */ - ); -#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING -#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest, src) -#else /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */ -#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest) -#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */ -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - -#if LWIP_CALLBACK_API -err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); -#endif /* LWIP_CALLBACK_API */ - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void tcp_debug_print(struct tcp_hdr *tcphdr); -void tcp_debug_print_flags(u8_t flags); -void tcp_debug_print_state(enum tcp_state s); -void tcp_debug_print_pcbs(void); -s16_t tcp_pcbs_sane(void); -#else -# define tcp_debug_print(tcphdr) -# define tcp_debug_print_flags(flags) -# define tcp_debug_print_state(s) -# define tcp_debug_print_pcbs() -# define tcp_pcbs_sane() 1 -#endif /* TCP_DEBUG */ - -/** External function (implemented in timers.c), called when TCP detects - * that a timer is needed (i.e. active- or time-wait-pcb found). */ -void tcp_timer_needed(void); - -void tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_TCP */ - -#endif /* LWIP_HDR_TCP_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcpip_priv.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcpip_priv.h deleted file mode 100644 index 630efb14022261e08d9b6fe4f362703111b55582..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/priv/tcpip_priv.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * @file - * TCPIP API internal implementations (do not use in application code) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_TCPIP_PRIV_H -#define LWIP_HDR_TCPIP_PRIV_H - -#include "lwip/opt.h" - -#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/tcpip.h" -#include "lwip/sys.h" -#include "lwip/timeouts.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct pbuf; -struct netif; - -#if LWIP_MPU_COMPATIBLE -#define API_VAR_REF(name) (*(name)) -#define API_VAR_DECLARE(type, name) type * name -#define API_VAR_ALLOC(type, pool, name, errorval) do { \ - name = (type *)memp_malloc(pool); \ - if (name == NULL) { \ - return errorval; \ - } \ - } while(0) -#define API_VAR_ALLOC_POOL(type, pool, name, errorval) do { \ - name = (type *)LWIP_MEMPOOL_ALLOC(pool); \ - if (name == NULL) { \ - return errorval; \ - } \ - } while(0) -#define API_VAR_FREE(pool, name) memp_free(pool, name) -#define API_VAR_FREE_POOL(pool, name) LWIP_MEMPOOL_FREE(pool, name) -#define API_EXPR_REF(expr) (&(expr)) -#if LWIP_NETCONN_SEM_PER_THREAD -#define API_EXPR_REF_SEM(expr) (expr) -#else -#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr) -#endif -#define API_EXPR_DEREF(expr) expr -#define API_MSG_M_DEF(m) m -#define API_MSG_M_DEF_C(t, m) t m -#else /* LWIP_MPU_COMPATIBLE */ -#define API_VAR_REF(name) name -#define API_VAR_DECLARE(type, name) type name -#define API_VAR_ALLOC(type, pool, name, errorval) -#define API_VAR_ALLOC_POOL(type, pool, name, errorval) -#define API_VAR_FREE(pool, name) -#define API_VAR_FREE_POOL(pool, name) -#define API_EXPR_REF(expr) expr -#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr) -#define API_EXPR_DEREF(expr) (*(expr)) -#define API_MSG_M_DEF(m) *m -#define API_MSG_M_DEF_C(t, m) const t * m -#endif /* LWIP_MPU_COMPATIBLE */ - -err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem); - -struct tcpip_api_call_data -{ -#if !LWIP_TCPIP_CORE_LOCKING - err_t err; -#if !LWIP_NETCONN_SEM_PER_THREAD - sys_sem_t sem; -#endif /* LWIP_NETCONN_SEM_PER_THREAD */ -#else /* !LWIP_TCPIP_CORE_LOCKING */ - u8_t dummy; /* avoid empty struct :-( */ -#endif /* !LWIP_TCPIP_CORE_LOCKING */ -}; -typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call_data* call); -err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call); - -enum tcpip_msg_type { - TCPIP_MSG_API, - TCPIP_MSG_API_CALL, - TCPIP_MSG_INPKT, -#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS - TCPIP_MSG_TIMEOUT, - TCPIP_MSG_UNTIMEOUT, -#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ - TCPIP_MSG_CALLBACK, - TCPIP_MSG_CALLBACK_STATIC -}; - -struct tcpip_msg { - enum tcpip_msg_type type; - union { - struct { - tcpip_callback_fn function; - void* msg; - } api_msg; - struct { - tcpip_api_call_fn function; - struct tcpip_api_call_data *arg; - sys_sem_t *sem; - } api_call; - struct { - struct pbuf *p; - struct netif *netif; - netif_input_fn input_fn; - } inp; - struct { - tcpip_callback_fn function; - void *ctx; - } cb; -#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS - struct { - u32_t msecs; - sys_timeout_handler h; - void *arg; - } tmo; -#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ - } msg; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* !NO_SYS */ - -#endif /* LWIP_HDR_TCPIP_PRIV_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/autoip.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/autoip.h deleted file mode 100644 index fd3af8a9fc5f0de8ee179a2e49cdb1bc82c3d140..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/autoip.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * @file - * AutoIP protocol definitions - */ - -/* - * - * Copyright (c) 2007 Dominik Spies - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dominik Spies - * - * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform - * with RFC 3927. - * - */ - -#ifndef LWIP_HDR_PROT_AUTOIP_H -#define LWIP_HDR_PROT_AUTOIP_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* 169.254.0.0 */ -#define AUTOIP_NET 0xA9FE0000 -/* 169.254.1.0 */ -#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100) -/* 169.254.254.255 */ -#define AUTOIP_RANGE_END (AUTOIP_NET | 0xFEFF) - -/* RFC 3927 Constants */ -#define PROBE_WAIT 1 /* second (initial random delay) */ -#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ -#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ -#define PROBE_NUM 3 /* (number of probe packets) */ -#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ -#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ -#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ -#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ -#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ -#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ - -/* AutoIP client states */ -typedef enum { - AUTOIP_STATE_OFF = 0, - AUTOIP_STATE_PROBING = 1, - AUTOIP_STATE_ANNOUNCING = 2, - AUTOIP_STATE_BOUND = 3 -} autoip_state_enum_t; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_AUTOIP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dhcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dhcp.h deleted file mode 100644 index 112953cb8bfa2fde36bf34a266995b554521c6fb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dhcp.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - * @file - * DHCP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * - */ -#ifndef LWIP_HDR_PROT_DHCP_H -#define LWIP_HDR_PROT_DHCP_H - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define DHCP_CLIENT_PORT 68 -#define DHCP_SERVER_PORT 67 - - - /* DHCP message item offsets and length */ -#define DHCP_CHADDR_LEN 16U -#define DHCP_SNAME_OFS 44U -#define DHCP_SNAME_LEN 64U -#define DHCP_FILE_OFS 108U -#define DHCP_FILE_LEN 128U -#define DHCP_MSG_LEN 236U -#define DHCP_OPTIONS_OFS (DHCP_MSG_LEN + 4U) /* 4 byte: cookie */ - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** minimum set of fields of any DHCP message */ -struct dhcp_msg -{ - PACK_STRUCT_FLD_8(u8_t op); - PACK_STRUCT_FLD_8(u8_t htype); - PACK_STRUCT_FLD_8(u8_t hlen); - PACK_STRUCT_FLD_8(u8_t hops); - PACK_STRUCT_FIELD(u32_t xid); - PACK_STRUCT_FIELD(u16_t secs); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr); - PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr); - PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr); - PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr); - PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]); - PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]); - PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]); - PACK_STRUCT_FIELD(u32_t cookie); -#define DHCP_MIN_OPTIONS_LEN 68U -/** make sure user does not configure this too small */ -#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) -# undef DHCP_OPTIONS_LEN -#endif -/** allow this to be configured in lwipopts.h, but not too small */ -#if (!defined(DHCP_OPTIONS_LEN)) -/** set this to be sufficient for your options in outgoing DHCP msgs */ -# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN -#endif - PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - - -/* DHCP client states */ -typedef enum { - DHCP_STATE_OFF = 0, - DHCP_STATE_REQUESTING = 1, - DHCP_STATE_INIT = 2, - DHCP_STATE_REBOOTING = 3, - DHCP_STATE_REBINDING = 4, - DHCP_STATE_RENEWING = 5, - DHCP_STATE_SELECTING = 6, - DHCP_STATE_INFORMING = 7, - DHCP_STATE_CHECKING = 8, - DHCP_STATE_PERMANENT = 9, /* not yet implemented */ - DHCP_STATE_BOUND = 10, - DHCP_STATE_RELEASING = 11, /* not yet implemented */ - DHCP_STATE_BACKING_OFF = 12 -} dhcp_state_enum_t; - -/* DHCP op codes */ -#define DHCP_BOOTREQUEST 1 -#define DHCP_BOOTREPLY 2 - -/* DHCP message types */ -#define DHCP_DISCOVER 1 -#define DHCP_OFFER 2 -#define DHCP_REQUEST 3 -#define DHCP_DECLINE 4 -#define DHCP_ACK 5 -#define DHCP_NAK 6 -#define DHCP_RELEASE 7 -#define DHCP_INFORM 8 - -/** DHCP hardware type, currently only ethernet is supported */ -#define DHCP_HTYPE_ETH 1 - -#define DHCP_MAGIC_COOKIE 0x63825363UL - -/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */ - -/* BootP options */ -#define DHCP_OPTION_PAD 0 -#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ -#define DHCP_OPTION_ROUTER 3 -#define DHCP_OPTION_DNS_SERVER 6 -#define DHCP_OPTION_HOSTNAME 12 -#define DHCP_OPTION_IP_TTL 23 -#define DHCP_OPTION_MTU 26 -#define DHCP_OPTION_BROADCAST 28 -#define DHCP_OPTION_TCP_TTL 37 -#define DHCP_OPTION_NTP 42 -#define DHCP_OPTION_END 255 - -/* DHCP options */ -#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ -#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ -#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ - -#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ -#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 - -#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ -#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ - -#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ -#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 - -#define DHCP_OPTION_T1 58 /* T1 renewal time */ -#define DHCP_OPTION_T2 59 /* T2 rebinding time */ -#define DHCP_OPTION_US 60 -#define DHCP_OPTION_CLIENT_ID 61 -#define DHCP_OPTION_TFTP_SERVERNAME 66 -#define DHCP_OPTION_BOOTFILE 67 - -/* possible combinations of overloading the file and sname fields with options */ -#define DHCP_OVERLOAD_NONE 0 -#define DHCP_OVERLOAD_FILE 1 -#define DHCP_OVERLOAD_SNAME 2 -#define DHCP_OVERLOAD_SNAME_FILE 3 - - -#ifdef __cplusplus -} -#endif - -#endif /*LWIP_HDR_PROT_DHCP_H*/ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dns.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dns.h deleted file mode 100644 index 94782d6e9c1e2c330174d14456a360e32c6c3e85..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/dns.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * @file - * DNS - host name to IP address resolver. - */ - -/* - * Port to lwIP from uIP - * by Jim Pettinato April 2007 - * - * security fixes and more by Simon Goldschmidt - * - * uIP version Copyright (c) 2002-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LWIP_HDR_PROT_DNS_H -#define LWIP_HDR_PROT_DNS_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** DNS server port address */ -#ifndef DNS_SERVER_PORT -#define DNS_SERVER_PORT 53 -#endif - -/* DNS field TYPE used for "Resource Records" */ -#define DNS_RRTYPE_A 1 /* a host address */ -#define DNS_RRTYPE_NS 2 /* an authoritative name server */ -#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ -#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ -#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ -#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ -#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ -#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ -#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ -#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ -#define DNS_RRTYPE_WKS 11 /* a well known service description */ -#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ -#define DNS_RRTYPE_HINFO 13 /* host information */ -#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ -#define DNS_RRTYPE_MX 15 /* mail exchange */ -#define DNS_RRTYPE_TXT 16 /* text strings */ -#define DNS_RRTYPE_AAAA 28 /* IPv6 address */ -#define DNS_RRTYPE_SRV 33 /* service location */ -#define DNS_RRTYPE_ANY 255 /* any type */ - -/* DNS field CLASS used for "Resource Records" */ -#define DNS_RRCLASS_IN 1 /* the Internet */ -#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ -#define DNS_RRCLASS_CH 3 /* the CHAOS class */ -#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ -#define DNS_RRCLASS_ANY 255 /* any class */ -#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ - -/* DNS protocol flags */ -#define DNS_FLAG1_RESPONSE 0x80 -#define DNS_FLAG1_OPCODE_STATUS 0x10 -#define DNS_FLAG1_OPCODE_INVERSE 0x08 -#define DNS_FLAG1_OPCODE_STANDARD 0x00 -#define DNS_FLAG1_AUTHORATIVE 0x04 -#define DNS_FLAG1_TRUNC 0x02 -#define DNS_FLAG1_RD 0x01 -#define DNS_FLAG2_RA 0x80 -#define DNS_FLAG2_ERR_MASK 0x0f -#define DNS_FLAG2_ERR_NONE 0x00 -#define DNS_FLAG2_ERR_NAME 0x03 - -#define DNS_HDR_GET_OPCODE(hdr) ((((hdr)->flags1) >> 3) & 0xF) - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** DNS message header */ -struct dns_hdr { - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FLD_8(u8_t flags1); - PACK_STRUCT_FLD_8(u8_t flags2); - PACK_STRUCT_FIELD(u16_t numquestions); - PACK_STRUCT_FIELD(u16_t numanswers); - PACK_STRUCT_FIELD(u16_t numauthrr); - PACK_STRUCT_FIELD(u16_t numextrarr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define SIZEOF_DNS_HDR 12 - - -/* Multicast DNS definitions */ - -/** UDP port for multicast DNS queries */ -#ifndef DNS_MQUERY_PORT -#define DNS_MQUERY_PORT 5353 -#endif - -/* IPv4 group for multicast DNS queries: 224.0.0.251 */ -#ifndef DNS_MQUERY_IPV4_GROUP_INIT -#define DNS_MQUERY_IPV4_GROUP_INIT IPADDR4_INIT_BYTES(224,0,0,251) -#endif - -/* IPv6 group for multicast DNS queries: FF02::FB */ -#ifndef DNS_MQUERY_IPV6_GROUP_INIT -#define DNS_MQUERY_IPV6_GROUP_INIT IPADDR6_INIT_HOST(0xFF020000,0,0,0xFB) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_DNS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/etharp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/etharp.h deleted file mode 100644 index ec78305b822471f0d474fa8dbee7ae5d3b146bd8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/etharp.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * ARP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_ETHARP_H -#define LWIP_HDR_PROT_ETHARP_H - -#include "lwip/arch.h" -#include "lwip/prot/ethernet.h" -#include "lwip/ip4_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ETHARP_HWADDR_LEN -#define ETHARP_HWADDR_LEN ETH_HWADDR_LEN -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** the ARP message, see RFC 826 ("Packet format") */ -struct etharp_hdr { - PACK_STRUCT_FIELD(u16_t hwtype); - PACK_STRUCT_FIELD(u16_t proto); - PACK_STRUCT_FLD_8(u8_t hwlen); - PACK_STRUCT_FLD_8(u8_t protolen); - PACK_STRUCT_FIELD(u16_t opcode); - PACK_STRUCT_FLD_S(struct eth_addr shwaddr); - PACK_STRUCT_FLD_S(struct ip4_addr2 sipaddr); - PACK_STRUCT_FLD_S(struct eth_addr dhwaddr); - PACK_STRUCT_FLD_S(struct ip4_addr2 dipaddr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_ETHARP_HDR 28 - -/* ARP hwtype values */ -enum etharp_hwtype { - HWTYPE_ETHERNET = 1 - /* others not used */ -}; - -/* ARP message types (opcodes) */ -enum etharp_opcode { - ARP_REQUEST = 1, - ARP_REPLY = 2 -}; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_ETHARP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ethernet.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ethernet.h deleted file mode 100644 index 29307c17643b6c05d5685206875cd67afed28cb0..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ethernet.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * @file - * Ethernet protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_ETHERNET_H -#define LWIP_HDR_PROT_ETHERNET_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ETH_HWADDR_LEN -#ifdef ETHARP_HWADDR_LEN -#define ETH_HWADDR_LEN ETHARP_HWADDR_LEN /* compatibility mode */ -#else -#define ETH_HWADDR_LEN 6 -#endif -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_addr { - PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** Ethernet header */ -struct eth_hdr { -#if ETH_PAD_SIZE - PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]); -#endif - PACK_STRUCT_FLD_S(struct eth_addr dest); - PACK_STRUCT_FLD_S(struct eth_addr src); - PACK_STRUCT_FIELD(u16_t type); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** VLAN header inserted between ethernet header and payload - * if 'type' in ethernet header is ETHTYPE_VLAN. - * See IEEE802.Q */ -struct eth_vlan_hdr { - PACK_STRUCT_FIELD(u16_t prio_vid); - PACK_STRUCT_FIELD(u16_t tpid); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_VLAN_HDR 4 -#define VLAN_ID(vlan_hdr) (lwip_htons((vlan_hdr)->prio_vid) & 0xFFF) - -/** - * @ingroup ethernet - * A list of often ethtypes (although lwIP does not use all of them): */ -enum eth_type { - /** Internet protocol v4 */ - ETHTYPE_IP = 0x0800U, - /** Address resolution protocol */ - ETHTYPE_ARP = 0x0806U, - /** Wake on lan */ - ETHTYPE_WOL = 0x0842U, - /** RARP */ - ETHTYPE_RARP = 0x8035U, - /** Virtual local area network */ - ETHTYPE_VLAN = 0x8100U, - /** Internet protocol v6 */ - ETHTYPE_IPV6 = 0x86DDU, - /** PPP Over Ethernet Discovery Stage */ - ETHTYPE_PPPOEDISC = 0x8863U, - /** PPP Over Ethernet Session Stage */ - ETHTYPE_PPPOE = 0x8864U, - /** Jumbo Frames */ - ETHTYPE_JUMBO = 0x8870U, - ETHTYPE_EAPOL = 0x888EU, - /** Process field network */ - ETHTYPE_PROFINET = 0x8892U, - /** Ethernet for control automation technology */ - ETHTYPE_ETHERCAT = 0x88A4U, - /** Link layer discovery protocol */ - ETHTYPE_LLDP = 0x88CCU, - /** Serial real-time communication system */ - ETHTYPE_SERCOS = 0x88CDU, - /** Media redundancy protocol */ - ETHTYPE_MRP = 0x88E3U, - /** Precision time protocol */ - ETHTYPE_PTP = 0x88F7U, - /** Q-in-Q, 802.1ad */ - ETHTYPE_QINQ = 0x9100U -}; - -/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */ -#define LL_IP4_MULTICAST_ADDR_0 0x01 -#define LL_IP4_MULTICAST_ADDR_1 0x00 -#define LL_IP4_MULTICAST_ADDR_2 0x5e - -/** IPv6 multicast uses this prefix */ -#define LL_IP6_MULTICAST_ADDR_0 0x33 -#define LL_IP6_MULTICAST_ADDR_1 0x33 - -/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables - * or known to be 32-bit aligned within the protocol header. */ -#ifndef ETHADDR32_COPY -#define ETHADDR32_COPY(dst, src) SMEMCPY(dst, src, ETH_HWADDR_LEN) -#endif - -/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local - * variables and known to be 16-bit aligned within the protocol header. */ -#ifndef ETHADDR16_COPY -#define ETHADDR16_COPY(dst, src) SMEMCPY(dst, src, ETH_HWADDR_LEN) -#endif - -#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_ETHERNET_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp.h deleted file mode 100644 index 7d19385c7296eb86e3957ff851372ad60b90e8d8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * ICMP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_ICMP_H -#define LWIP_HDR_PROT_ICMP_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ICMP_ER 0 /* echo reply */ -#define ICMP_DUR 3 /* destination unreachable */ -#define ICMP_SQ 4 /* source quench */ -#define ICMP_RD 5 /* redirect */ -#define ICMP_ECHO 8 /* echo */ -#define ICMP_TE 11 /* time exceeded */ -#define ICMP_PP 12 /* parameter problem */ -#define ICMP_TS 13 /* timestamp */ -#define ICMP_TSR 14 /* timestamp reply */ -#define ICMP_IRQ 15 /* information request */ -#define ICMP_IR 16 /* information reply */ -#define ICMP_AM 17 /* address mask request */ -#define ICMP_AMR 18 /* address mask reply */ - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -/** This is the standard ICMP header only that the u32_t data - * is split to two u16_t like ICMP echo needs it. - * This header is also used for other ICMP types that do not - * use the data part. - */ -PACK_STRUCT_BEGIN -struct icmp_echo_hdr { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FIELD(u16_t seqno); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* Compatibility defines, old versions used to combine type and code to an u16_t */ -#define ICMPH_TYPE(hdr) ((hdr)->type) -#define ICMPH_CODE(hdr) ((hdr)->code) -#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) -#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_ICMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp6.h deleted file mode 100644 index 3461120421e44a4c8906c7c28d457d31eb53b44a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/icmp6.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * @file - * ICMP6 protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_ICMP6_H -#define LWIP_HDR_PROT_ICMP6_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** ICMP type */ -enum icmp6_type { - /** Destination unreachable */ - ICMP6_TYPE_DUR = 1, - /** Packet too big */ - ICMP6_TYPE_PTB = 2, - /** Time exceeded */ - ICMP6_TYPE_TE = 3, - /** Parameter problem */ - ICMP6_TYPE_PP = 4, - /** Private experimentation */ - ICMP6_TYPE_PE1 = 100, - /** Private experimentation */ - ICMP6_TYPE_PE2 = 101, - /** Reserved for expansion of error messages */ - ICMP6_TYPE_RSV_ERR = 127, - - /** Echo request */ - ICMP6_TYPE_EREQ = 128, - /** Echo reply */ - ICMP6_TYPE_EREP = 129, - /** Multicast listener query */ - ICMP6_TYPE_MLQ = 130, - /** Multicast listener report */ - ICMP6_TYPE_MLR = 131, - /** Multicast listener done */ - ICMP6_TYPE_MLD = 132, - /** Router solicitation */ - ICMP6_TYPE_RS = 133, - /** Router advertisement */ - ICMP6_TYPE_RA = 134, - /** Neighbor solicitation */ - ICMP6_TYPE_NS = 135, - /** Neighbor advertisement */ - ICMP6_TYPE_NA = 136, - /** Redirect */ - ICMP6_TYPE_RD = 137, - /** Multicast router advertisement */ - ICMP6_TYPE_MRA = 151, - /** Multicast router solicitation */ - ICMP6_TYPE_MRS = 152, - /** Multicast router termination */ - ICMP6_TYPE_MRT = 153, - /** Private experimentation */ - ICMP6_TYPE_PE3 = 200, - /** Private experimentation */ - ICMP6_TYPE_PE4 = 201, - /** Reserved for expansion of informational messages */ - ICMP6_TYPE_RSV_INF = 255 -}; - -/** ICMP destination unreachable codes */ -enum icmp6_dur_code { - /** No route to destination */ - ICMP6_DUR_NO_ROUTE = 0, - /** Communication with destination administratively prohibited */ - ICMP6_DUR_PROHIBITED = 1, - /** Beyond scope of source address */ - ICMP6_DUR_SCOPE = 2, - /** Address unreachable */ - ICMP6_DUR_ADDRESS = 3, - /** Port unreachable */ - ICMP6_DUR_PORT = 4, - /** Source address failed ingress/egress policy */ - ICMP6_DUR_POLICY = 5, - /** Reject route to destination */ - ICMP6_DUR_REJECT_ROUTE = 6 -}; - -/** ICMP time exceeded codes */ -enum icmp6_te_code { - /** Hop limit exceeded in transit */ - ICMP6_TE_HL = 0, - /** Fragment reassembly time exceeded */ - ICMP6_TE_FRAG = 1 -}; - -/** ICMP parameter code */ -enum icmp6_pp_code { - /** Erroneous header field encountered */ - ICMP6_PP_FIELD = 0, - /** Unrecognized next header type encountered */ - ICMP6_PP_HEADER = 1, - /** Unrecognized IPv6 option encountered */ - ICMP6_PP_OPTION = 2 -}; - -/** This is the standard ICMP6 header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct icmp6_hdr { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t data); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** This is the ICMP6 header adapted for echo req/resp. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct icmp6_echo_hdr { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FIELD(u16_t seqno); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_ICMP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/igmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/igmp.h deleted file mode 100644 index d60cb31ee7ccfd0fb59ab7baa0835859e1158735..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/igmp.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * @file - * IGMP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_IGMP_H -#define LWIP_HDR_PROT_IGMP_H - -#include "lwip/arch.h" -#include "lwip/ip4_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * IGMP constants - */ -#define IGMP_TTL 1 -#define IGMP_MINLEN 8 -#define ROUTER_ALERT 0x9404U -#define ROUTER_ALERTLEN 4 - -/* - * IGMP message types, including version number. - */ -#define IGMP_MEMB_QUERY 0x11 /* Membership query */ -#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ -#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ -#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ - -/* Group membership states */ -#define IGMP_GROUP_NON_MEMBER 0 -#define IGMP_GROUP_DELAYING_MEMBER 1 -#define IGMP_GROUP_IDLE_MEMBER 2 - -/** - * IGMP packet format. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct igmp_msg { - PACK_STRUCT_FLD_8(u8_t igmp_msgtype); - PACK_STRUCT_FLD_8(u8_t igmp_maxresp); - PACK_STRUCT_FIELD(u16_t igmp_checksum); - PACK_STRUCT_FLD_S(ip4_addr_p_t igmp_group_address); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_IGMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip.h deleted file mode 100644 index bbfae367527515e890e131936461268f0dbe5fe3..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * IP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_IP_H -#define LWIP_HDR_PROT_IP_H - -#include "lwip/arch.h" - -#define IP_PROTO_ICMP 1 -#define IP_PROTO_IGMP 2 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 136 -#define IP_PROTO_TCP 6 - -/** This operates on a void* by loading the first byte */ -#define IP_HDR_GET_VERSION(ptr) ((*(u8_t*)(ptr)) >> 4) - -#endif /* LWIP_HDR_PROT_IP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip4.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip4.h deleted file mode 100644 index bd442c6892ce5a6db1c4ed563fd5b3d81d2270fa..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip4.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * IPv4 protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_IP4_H -#define LWIP_HDR_PROT_IP4_H - -#include "lwip/arch.h" -#include "lwip/ip4_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** This is the packed version of ip4_addr_t, - used in network headers that are itself packed */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip4_addr_packed { - PACK_STRUCT_FIELD(u32_t addr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -typedef struct ip4_addr_packed ip4_addr_p_t; - -/* Size of the IPv4 header. Same as 'sizeof(struct ip_hdr)'. */ -#define IP_HLEN 20 - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/* The IPv4 header */ -struct ip_hdr { - /* version / header length */ - PACK_STRUCT_FLD_8(u8_t _v_hl); - /* type of service */ - PACK_STRUCT_FLD_8(u8_t _tos); - /* total length */ - PACK_STRUCT_FIELD(u16_t _len); - /* identification */ - PACK_STRUCT_FIELD(u16_t _id); - /* fragment offset field */ - PACK_STRUCT_FIELD(u16_t _offset); -#define IP_RF 0x8000U /* reserved fragment flag */ -#define IP_DF 0x4000U /* don't fragment flag */ -#define IP_MF 0x2000U /* more fragments flag */ -#define IP_OFFMASK 0x1fffU /* mask for fragmenting bits */ - /* time to live */ - PACK_STRUCT_FLD_8(u8_t _ttl); - /* protocol*/ - PACK_STRUCT_FLD_8(u8_t _proto); - /* checksum */ - PACK_STRUCT_FIELD(u16_t _chksum); - /* source and destination IP addresses */ - PACK_STRUCT_FLD_S(ip4_addr_p_t src); - PACK_STRUCT_FLD_S(ip4_addr_p_t dest); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* Macros to get struct ip_hdr fields: */ -#define IPH_V(hdr) ((hdr)->_v_hl >> 4) -#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f) -#define IPH_TOS(hdr) ((hdr)->_tos) -#define IPH_LEN(hdr) ((hdr)->_len) -#define IPH_ID(hdr) ((hdr)->_id) -#define IPH_OFFSET(hdr) ((hdr)->_offset) -#define IPH_TTL(hdr) ((hdr)->_ttl) -#define IPH_PROTO(hdr) ((hdr)->_proto) -#define IPH_CHKSUM(hdr) ((hdr)->_chksum) - -/* Macros to set struct ip_hdr fields: */ -#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl))) -#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos) -#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) -#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) -#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) -#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl) -#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto) -#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_IP4_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip6.h deleted file mode 100644 index 6e1e2632bfc9e42927a8b9cd93add094d3cabe0a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/ip6.h +++ /dev/null @@ -1,169 +0,0 @@ -/** - * @file - * IPv6 protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_IP6_H -#define LWIP_HDR_PROT_IP6_H - -#include "lwip/arch.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** This is the packed version of ip6_addr_t, - used in network headers that are itself packed */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip6_addr_packed { - PACK_STRUCT_FIELD(u32_t addr[4]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -typedef struct ip6_addr_packed ip6_addr_p_t; - -#define IP6_HLEN 40 - -#define IP6_NEXTH_HOPBYHOP 0 -#define IP6_NEXTH_TCP 6 -#define IP6_NEXTH_UDP 17 -#define IP6_NEXTH_ENCAPS 41 -#define IP6_NEXTH_ROUTING 43 -#define IP6_NEXTH_FRAGMENT 44 -#define IP6_NEXTH_ICMP6 58 -#define IP6_NEXTH_NONE 59 -#define IP6_NEXTH_DESTOPTS 60 -#define IP6_NEXTH_UDPLITE 136 - -/** The IPv6 header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip6_hdr { - /** version / traffic class / flow label */ - PACK_STRUCT_FIELD(u32_t _v_tc_fl); - /** payload length */ - PACK_STRUCT_FIELD(u16_t _plen); - /** next header */ - PACK_STRUCT_FLD_8(u8_t _nexth); - /** hop limit */ - PACK_STRUCT_FLD_8(u8_t _hoplim); - /** source and destination IP addresses */ - PACK_STRUCT_FLD_S(ip6_addr_p_t src); - PACK_STRUCT_FLD_S(ip6_addr_p_t dest); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* Hop-by-hop router alert option. */ -#define IP6_HBH_HLEN 8 -#define IP6_PAD1_OPTION 0 -#define IP6_PADN_ALERT_OPTION 1 -#define IP6_ROUTER_ALERT_OPTION 5 -#define IP6_ROUTER_ALERT_VALUE_MLD 0 -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip6_hbh_hdr { - /* next header */ - PACK_STRUCT_FLD_8(u8_t _nexth); - /* header length */ - PACK_STRUCT_FLD_8(u8_t _hlen); - /* router alert option type */ - PACK_STRUCT_FLD_8(u8_t _ra_opt_type); - /* router alert option data len */ - PACK_STRUCT_FLD_8(u8_t _ra_opt_dlen); - /* router alert option data */ - PACK_STRUCT_FIELD(u16_t _ra_opt_data); - /* PadN option type */ - PACK_STRUCT_FLD_8(u8_t _padn_opt_type); - /* PadN option data len */ - PACK_STRUCT_FLD_8(u8_t _padn_opt_dlen); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* Fragment header. */ -#define IP6_FRAG_HLEN 8 -#define IP6_FRAG_OFFSET_MASK 0xfff8 -#define IP6_FRAG_MORE_FLAG 0x0001 -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip6_frag_hdr { - /* next header */ - PACK_STRUCT_FLD_8(u8_t _nexth); - /* reserved */ - PACK_STRUCT_FLD_8(u8_t reserved); - /* fragment offset */ - PACK_STRUCT_FIELD(u16_t _fragment_offset); - /* fragmented packet identification */ - PACK_STRUCT_FIELD(u32_t _identification); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define IP6H_V(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f) -#define IP6H_TC(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 20) & 0xff) -#define IP6H_FL(hdr) (lwip_ntohl((hdr)->_v_tc_fl) & 0x000fffff) -#define IP6H_PLEN(hdr) (lwip_ntohs((hdr)->_plen)) -#define IP6H_NEXTH(hdr) ((hdr)->_nexth) -#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6) -#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim) - -#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (lwip_htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl))) -#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = lwip_htons(plen) -#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth) -#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_IP6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/mld6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/mld6.h deleted file mode 100644 index be3a006af25baaac48ee2b3c998a5f26adf7ff52..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/mld6.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * MLD6 protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_MLD6_H -#define LWIP_HDR_PROT_MLD6_H - -#include "lwip/arch.h" -#include "lwip/prot/ip6.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Multicast listener report/query/done message header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct mld_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t max_resp_delay); - PACK_STRUCT_FIELD(u16_t reserved); - PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_MLD6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/nd6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/nd6.h deleted file mode 100644 index 2d4903d15b671d4cd4ea479d86dc3ec1a8019242..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/nd6.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - * @file - * ND6 protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_ND6_H -#define LWIP_HDR_PROT_ND6_H - -#include "lwip/arch.h" -#include "lwip/ip6_addr.h" -#include "lwip/prot/ip6.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Neighbor solicitation message header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ns_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t reserved); - PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Neighbor advertisement message header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct na_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FLD_8(u8_t flags); - PACK_STRUCT_FLD_8(u8_t reserved[3]); - PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define ND6_FLAG_ROUTER (0x80) -#define ND6_FLAG_SOLICITED (0x40) -#define ND6_FLAG_OVERRIDE (0x20) - -/** Router solicitation message header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct rs_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t reserved); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Router advertisement message header. */ -#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80) -#define ND6_RA_FLAG_OTHER_CONFIG (0x40) -#define ND6_RA_FLAG_HOME_AGENT (0x20) -#define ND6_RA_PREFERENCE_MASK (0x18) -#define ND6_RA_PREFERENCE_HIGH (0x08) -#define ND6_RA_PREFERENCE_MEDIUM (0x00) -#define ND6_RA_PREFERENCE_LOW (0x18) -#define ND6_RA_PREFERENCE_DISABLED (0x10) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ra_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FLD_8(u8_t current_hop_limit); - PACK_STRUCT_FLD_8(u8_t flags); - PACK_STRUCT_FIELD(u16_t router_lifetime); - PACK_STRUCT_FIELD(u32_t reachable_time); - PACK_STRUCT_FIELD(u32_t retrans_timer); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Redirect message header. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct redirect_header { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t reserved); - PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); - PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address); - /* Options follow. */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Link-layer address option. */ -#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01) -#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct lladdr_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Prefix information option. */ -#define ND6_OPTION_TYPE_PREFIX_INFO (0x03) -#define ND6_PREFIX_FLAG_ON_LINK (0x80) -#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40) -#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20) -#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct prefix_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FLD_8(u8_t prefix_length); - PACK_STRUCT_FLD_8(u8_t flags); - PACK_STRUCT_FIELD(u32_t valid_lifetime); - PACK_STRUCT_FIELD(u32_t preferred_lifetime); - PACK_STRUCT_FLD_8(u8_t reserved2[3]); - PACK_STRUCT_FLD_8(u8_t site_prefix_length); - PACK_STRUCT_FLD_S(ip6_addr_p_t prefix); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Redirected header option. */ -#define ND6_OPTION_TYPE_REDIR_HDR (0x04) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct redirected_header_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FLD_8(u8_t reserved[6]); - /* Portion of redirected packet follows. */ - /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */ -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** MTU option. */ -#define ND6_OPTION_TYPE_MTU (0x05) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct mtu_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FIELD(u16_t reserved); - PACK_STRUCT_FIELD(u32_t mtu); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Route information option. */ -#define ND6_OPTION_TYPE_ROUTE_INFO (24) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct route_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FLD_8(u8_t prefix_length); - PACK_STRUCT_FLD_8(u8_t preference); - PACK_STRUCT_FIELD(u32_t route_lifetime); - PACK_STRUCT_FLD_S(ip6_addr_p_t prefix); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** Recursive DNS Server Option. */ -#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS -#define LWIP_RDNSS_OPTION_MAX_SERVERS LWIP_ND6_RDNSS_MAX_DNS_SERVERS -#else -#define LWIP_RDNSS_OPTION_MAX_SERVERS 1 -#endif -#define ND6_OPTION_TYPE_RDNSS (25) -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct rdnss_option { - PACK_STRUCT_FLD_8(u8_t type); - PACK_STRUCT_FLD_8(u8_t length); - PACK_STRUCT_FIELD(u16_t reserved); - PACK_STRUCT_FIELD(u32_t lifetime); - PACK_STRUCT_FLD_S(ip6_addr_p_t rdnss_address[LWIP_RDNSS_OPTION_MAX_SERVERS]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_ND6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/tcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/tcp.h deleted file mode 100644 index 67fe7b9e5fc79a722b641e3a3f27bea3fdfab341..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/tcp.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file - * TCP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_TCP_H -#define LWIP_HDR_PROT_TCP_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Length of the TCP header, excluding options. */ -#define TCP_HLEN 20 - -/* Fields are (of course) in network byte order. - * Some fields are converted to host byte order in tcp_input(). - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct tcp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); - PACK_STRUCT_FIELD(u32_t seqno); - PACK_STRUCT_FIELD(u32_t ackno); - PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); - PACK_STRUCT_FIELD(u16_t wnd); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t urgp); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* TCP header flags bits */ -#define TCP_FIN 0x01U -#define TCP_SYN 0x02U -#define TCP_RST 0x04U -#define TCP_PSH 0x08U -#define TCP_ACK 0x10U -#define TCP_URG 0x20U -#define TCP_ECE 0x40U -#define TCP_CWR 0x80U -/* Valid TCP header flags */ -#define TCP_FLAGS 0x3fU - -#define TCPH_HDRLEN(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)) -#define TCPH_FLAGS(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)) - -#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = lwip_htons(((len) << 12) | TCPH_FLAGS(phdr)) -#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | lwip_htons(flags)) -#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = (u16_t)(lwip_htons((u16_t)((len) << 12) | (flags))) - -#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | lwip_htons(flags)) -#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~lwip_htons(flags)) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_TCP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/udp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/udp.h deleted file mode 100644 index 664f19a3e7bd7bdc7b994dd022b6450066a5a836..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/prot/udp.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * UDP protocol definitions - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_PROT_UDP_H -#define LWIP_HDR_PROT_UDP_H - -#include "lwip/arch.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UDP_HLEN 8 - -/* Fields are (of course) in network byte order. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct udp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ - PACK_STRUCT_FIELD(u16_t len); - PACK_STRUCT_FIELD(u16_t chksum); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_PROT_UDP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/raw.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/raw.h deleted file mode 100644 index 30aa1471096ae58f445532a44578bd3f7438c287..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/raw.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * raw API (to be used from TCPIP thread)\n - * See also @ref raw_raw - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_RAW_H -#define LWIP_HDR_RAW_H - -#include "lwip/opt.h" - -#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/def.h" -#include "lwip/ip.h" -#include "lwip/ip_addr.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct raw_pcb; - -/** Function prototype for raw pcb receive callback functions. - * @param arg user supplied argument (raw_pcb.recv_arg) - * @param pcb the raw_pcb which received data - * @param p the packet buffer that was received - * @param addr the remote IP address from which the packet was received - * @return 1 if the packet was 'eaten' (aka. deleted), - * 0 if the packet lives on - * If returning 1, the callback is responsible for freeing the pbuf - * if it's not used any more. - */ -typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p, - const ip_addr_t *addr); - -/** the RAW protocol control block */ -struct raw_pcb { - /* Common members of all PCB types */ - IP_PCB; - - struct raw_pcb *next; - - u8_t protocol; - - /** receive callback function */ - raw_recv_fn recv; - /* user-supplied argument for the recv callback */ - void *recv_arg; -#if LWIP_IPV6 - /* fields for handling checksum computations as per RFC3542. */ - u16_t chksum_offset; - u8_t chksum_reqd; -#endif -}; - -/* The following functions is the application layer interface to the - RAW code. */ -struct raw_pcb * raw_new (u8_t proto); -struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto); -void raw_remove (struct raw_pcb *pcb); -err_t raw_bind (struct raw_pcb *pcb, const ip_addr_t *ipaddr); -err_t raw_connect (struct raw_pcb *pcb, const ip_addr_t *ipaddr); - -err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr); -err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); - -void raw_recv (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg); - -/* The following functions are the lower layer interface to RAW. */ -u8_t raw_input (struct pbuf *p, struct netif *inp); -#define raw_init() /* Compatibility define, no init needed. */ - -void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); - -/* for compatibility with older implementation */ -#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_RAW */ - -#endif /* LWIP_HDR_RAW_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sio.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sio.h deleted file mode 100644 index 7643e195697e2c212ac8de4df1f24d94677eb331..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sio.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - */ - -/* - * This is the interface to the platform specific serial IO module - * It needs to be implemented by those platforms which need SLIP or PPP - */ - -#ifndef SIO_H -#define SIO_H - -#include "lwip/arch.h" -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* If you want to define sio_fd_t elsewhere or differently, - define this in your cc.h file. */ -#ifndef __sio_fd_t_defined -typedef void * sio_fd_t; -#endif - -/* The following functions can be defined to something else in your cc.h file - or be implemented in your custom sio.c file. */ - -#ifndef sio_open -/** - * Opens a serial device for communication. - * - * @param devnum device number - * @return handle to serial device if successful, NULL otherwise - */ -sio_fd_t sio_open(u8_t devnum); -#endif - -#ifndef sio_send -/** - * Sends a single character to the serial device. - * - * @param c character to send - * @param fd serial device handle - * - * @note This function will block until the character can be sent. - */ -void sio_send(u8_t c, sio_fd_t fd); -#endif - -#ifndef sio_recv -/** - * Receives a single character from the serial device. - * - * @param fd serial device handle - * - * @note This function will block until a character is received. - */ -u8_t sio_recv(sio_fd_t fd); -#endif - -#ifndef sio_read -/** - * Reads from the serial device. - * - * @param fd serial device handle - * @param data pointer to data buffer for receiving - * @param len maximum length (in bytes) of data to receive - * @return number of bytes actually received - may be 0 if aborted by sio_read_abort - * - * @note This function will block until data can be received. The blocking - * can be cancelled by calling sio_read_abort(). - */ -u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len); -#endif - -#ifndef sio_tryread -/** - * Tries to read from the serial device. Same as sio_read but returns - * immediately if no data is available and never blocks. - * - * @param fd serial device handle - * @param data pointer to data buffer for receiving - * @param len maximum length (in bytes) of data to receive - * @return number of bytes actually received - */ -u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len); -#endif - -#ifndef sio_write -/** - * Writes to the serial device. - * - * @param fd serial device handle - * @param data pointer to data to send - * @param len length (in bytes) of data to send - * @return number of bytes actually sent - * - * @note This function will block until all data can be sent. - */ -u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len); -#endif - -#ifndef sio_read_abort -/** - * Aborts a blocking sio_read() call. - * - * @param fd serial device handle - */ -void sio_read_abort(sio_fd_t fd); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* SIO_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/snmp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/snmp.h deleted file mode 100644 index 8704d0b4d2955b9ac0d69c695b4ae9b1cce92a30..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/snmp.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - * @file - * SNMP support API for implementing netifs and statitics for MIB2 - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Dirk Ziegelmeier - * - */ -#ifndef LWIP_HDR_SNMP_H -#define LWIP_HDR_SNMP_H - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct udp_pcb; -struct netif; - -/** - * @defgroup netif_mib2 MIB2 statistics - * @ingroup netif - */ - -/* MIB2 statistics functions */ -#if MIB2_STATS /* don't build if not configured for use in lwipopts.h */ -/** - * @ingroup netif_mib2 - * @see RFC1213, "MIB-II, 6. Definitions" - */ -enum snmp_ifType { - snmp_ifType_other=1, /* none of the following */ - snmp_ifType_regular1822, - snmp_ifType_hdh1822, - snmp_ifType_ddn_x25, - snmp_ifType_rfc877_x25, - snmp_ifType_ethernet_csmacd, - snmp_ifType_iso88023_csmacd, - snmp_ifType_iso88024_tokenBus, - snmp_ifType_iso88025_tokenRing, - snmp_ifType_iso88026_man, - snmp_ifType_starLan, - snmp_ifType_proteon_10Mbit, - snmp_ifType_proteon_80Mbit, - snmp_ifType_hyperchannel, - snmp_ifType_fddi, - snmp_ifType_lapb, - snmp_ifType_sdlc, - snmp_ifType_ds1, /* T-1 */ - snmp_ifType_e1, /* european equiv. of T-1 */ - snmp_ifType_basicISDN, - snmp_ifType_primaryISDN, /* proprietary serial */ - snmp_ifType_propPointToPointSerial, - snmp_ifType_ppp, - snmp_ifType_softwareLoopback, - snmp_ifType_eon, /* CLNP over IP [11] */ - snmp_ifType_ethernet_3Mbit, - snmp_ifType_nsip, /* XNS over IP */ - snmp_ifType_slip, /* generic SLIP */ - snmp_ifType_ultra, /* ULTRA technologies */ - snmp_ifType_ds3, /* T-3 */ - snmp_ifType_sip, /* SMDS */ - snmp_ifType_frame_relay -}; - -/** This macro has a precision of ~49 days because sys_now returns u32_t. \#define your own if you want ~490 days. */ -#ifndef MIB2_COPY_SYSUPTIME_TO -#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (sys_now() / 10)) -#endif - -/** - * @ingroup netif_mib2 - * Increment stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs) - */ -#define MIB2_STATS_NETIF_INC(n, x) do { ++(n)->mib2_counters.x; } while(0) -/** - * @ingroup netif_mib2 - * Add value to stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs) - */ -#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0) - -/** - * @ingroup netif_mib2 - * Init MIB2 statistic counters in netif - * @param netif Netif to init - * @param type one of enum @ref snmp_ifType - * @param speed your link speed here (units: bits per second) - */ -#define MIB2_INIT_NETIF(netif, type, speed) do { \ - (netif)->link_type = (type); \ - (netif)->link_speed = (speed);\ - (netif)->ts = 0; \ - (netif)->mib2_counters.ifinoctets = 0; \ - (netif)->mib2_counters.ifinucastpkts = 0; \ - (netif)->mib2_counters.ifinnucastpkts = 0; \ - (netif)->mib2_counters.ifindiscards = 0; \ - (netif)->mib2_counters.ifinerrors = 0; \ - (netif)->mib2_counters.ifinunknownprotos = 0; \ - (netif)->mib2_counters.ifoutoctets = 0; \ - (netif)->mib2_counters.ifoutucastpkts = 0; \ - (netif)->mib2_counters.ifoutnucastpkts = 0; \ - (netif)->mib2_counters.ifoutdiscards = 0; \ - (netif)->mib2_counters.ifouterrors = 0; } while(0) -#else /* MIB2_STATS */ -#ifndef MIB2_COPY_SYSUPTIME_TO -#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) -#endif -#define MIB2_INIT_NETIF(netif, type, speed) -#define MIB2_STATS_NETIF_INC(n, x) -#define MIB2_STATS_NETIF_ADD(n, x, val) -#endif /* MIB2_STATS */ - -/* LWIP MIB2 callbacks */ -#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */ -/* network interface */ -void mib2_netif_added(struct netif *ni); -void mib2_netif_removed(struct netif *ni); - -#if LWIP_IPV4 && LWIP_ARP -/* ARP (for atTable and ipNetToMediaTable) */ -void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip); -void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip); -#else /* LWIP_IPV4 && LWIP_ARP */ -#define mib2_add_arp_entry(ni,ip) -#define mib2_remove_arp_entry(ni,ip) -#endif /* LWIP_IPV4 && LWIP_ARP */ - -/* IP */ -#if LWIP_IPV4 -void mib2_add_ip4(struct netif *ni); -void mib2_remove_ip4(struct netif *ni); -void mib2_add_route_ip4(u8_t dflt, struct netif *ni); -void mib2_remove_route_ip4(u8_t dflt, struct netif *ni); -#endif /* LWIP_IPV4 */ - -/* UDP */ -#if LWIP_UDP -void mib2_udp_bind(struct udp_pcb *pcb); -void mib2_udp_unbind(struct udp_pcb *pcb); -#endif /* LWIP_UDP */ - -#else /* LWIP_MIB2_CALLBACKS */ -/* LWIP_MIB2_CALLBACKS support not available */ -/* define everything to be empty */ - -/* network interface */ -#define mib2_netif_added(ni) -#define mib2_netif_removed(ni) - -/* ARP */ -#define mib2_add_arp_entry(ni,ip) -#define mib2_remove_arp_entry(ni,ip) - -/* IP */ -#define mib2_add_ip4(ni) -#define mib2_remove_ip4(ni) -#define mib2_add_route_ip4(dflt, ni) -#define mib2_remove_route_ip4(dflt, ni) - -/* UDP */ -#define mib2_udp_bind(pcb) -#define mib2_udp_unbind(pcb) -#endif /* LWIP_MIB2_CALLBACKS */ - -/* for source-code compatibility reasons only, can be removed (not used internally) */ -#define NETIF_INIT_SNMP MIB2_INIT_NETIF -#define snmp_add_ifinoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifinoctets, value) -#define snmp_inc_ifinucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinucastpkts) -#define snmp_inc_ifinnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinnucastpkts) -#define snmp_inc_ifindiscards(ni) MIB2_STATS_NETIF_INC(ni, ifindiscards) -#define snmp_inc_ifinerrors(ni) MIB2_STATS_NETIF_INC(ni, ifinerrors) -#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos) -#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value) -#define snmp_inc_ifoutucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutucastpkts) -#define snmp_inc_ifoutnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts) -#define snmp_inc_ifoutdiscards(ni) MIB2_STATS_NETIF_INC(ni, ifoutdiscards) -#define snmp_inc_ifouterrors(ni) MIB2_STATS_NETIF_INC(ni, ifouterrors) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_SNMP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sockets.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sockets.h deleted file mode 100644 index 14cd441de07a18aa8b90ca5295bc821b93bcaa9f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sockets.h +++ /dev/null @@ -1,595 +0,0 @@ -/** - * @file - * Socket API (to be used from non-TCPIP threads) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_SOCKETS_H -#define LWIP_HDR_SOCKETS_H - -#include "lwip/opt.h" -#include "mem_pub.h" - -#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip_addr.h" -#include "lwip/err.h" -#include "lwip/inet.h" -#include "lwip/errno.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED - to prevent this code from redefining it. */ -#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED) -typedef u8_t sa_family_t; -#endif -/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED - to prevent this code from redefining it. */ -#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED) -typedef u16_t in_port_t; -#endif - -#if LWIP_IPV4 -/* members are in network byte order */ -struct sockaddr_in { - u8_t sin_len; - sa_family_t sin_family; - in_port_t sin_port; - struct in_addr sin_addr; -#define SIN_ZERO_LEN 8 - char sin_zero[SIN_ZERO_LEN]; -}; -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -struct sockaddr_in6 { - u8_t sin6_len; /* length of this structure */ - sa_family_t sin6_family; /* AF_INET6 */ - in_port_t sin6_port; /* Transport layer port # */ - u32_t sin6_flowinfo; /* IPv6 flow information */ - struct in6_addr sin6_addr; /* IPv6 address */ - u32_t sin6_scope_id; /* Set of interfaces for scope */ -}; -#endif /* LWIP_IPV6 */ - -struct sockaddr { - u8_t sa_len; - sa_family_t sa_family; - char sa_data[14]; -}; - -struct sockaddr_storage { - u8_t s2_len; - sa_family_t ss_family; - char s2_data1[2]; - u32_t s2_data2[3]; -#if LWIP_IPV6 - u32_t s2_data3[3]; -#endif /* LWIP_IPV6 */ -}; - -/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED - to prevent this code from redefining it. */ -#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED) -typedef u32_t socklen_t; -#endif - -struct lwip_sock; - -#if !LWIP_TCPIP_CORE_LOCKING -/** Maximum optlen used by setsockopt/getsockopt */ -#define LWIP_SETGETSOCKOPT_MAXOPTLEN 16 - -/** This struct is used to pass data to the set/getsockopt_internal - * functions running in tcpip_thread context (only a void* is allowed) */ -struct lwip_setgetsockopt_data { - /** socket index for which to change options */ - int s; - /** level of the option to process */ - int level; - /** name of the option to process */ - int optname; - /** set: value to set the option to - * get: value of the option is stored here */ -#if LWIP_MPU_COMPATIBLE - u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN]; -#else - union { - void *p; - const void *pc; - } optval; -#endif - /** size of *optval */ - socklen_t optlen; - /** if an error occurs, it is temporarily stored here */ - err_t err; - /** semaphore to wake up the calling task */ - void* completed_sem; -}; -#endif /* !LWIP_TCPIP_CORE_LOCKING */ - -#if !defined(iovec) -struct iovec { - void *iov_base; - size_t iov_len; -}; -#endif - -struct msghdr { - void *msg_name; - socklen_t msg_namelen; - struct iovec *msg_iov; - int msg_iovlen; - void *msg_control; - socklen_t msg_controllen; - int msg_flags; -}; - -/* Socket protocol types (TCP/UDP/RAW) */ -#define SOCK_STREAM 1 -#define SOCK_DGRAM 2 -#define SOCK_RAW 3 - -/* - * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c) - */ -#define SO_REUSEADDR 0x0004 /* Allow local address reuse */ -#define SO_KEEPALIVE 0x0008 /* keep connections alive */ -#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ - - -/* - * Additional options, not kept in so_options. - */ -#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ -#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ -#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ -#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ -#define SO_LINGER 0x0080 /* linger on close if data present */ -#define SO_DONTLINGER ((int)(~SO_LINGER)) -#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ -#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ -#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ -#define SO_RCVBUF 0x1002 /* receive buffer size */ -#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_TYPE 0x1008 /* get socket type */ -#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ -#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ - - -/* - * Structure used for manipulating linger option. - */ -struct linger { - int l_onoff; /* option on/off */ - int l_linger; /* linger time in seconds */ -}; - -/* - * Level number for (get/set)sockopt() to apply to socket itself. - */ -#define SOL_SOCKET 0xfff /* options for socket level */ - - -#define AF_UNSPEC 0 -#define AF_INET 2 -#if LWIP_IPV6 -#define AF_INET6 10 -#else /* LWIP_IPV6 */ -#define AF_INET6 AF_UNSPEC -#endif /* LWIP_IPV6 */ -#define PF_INET AF_INET -#define PF_INET6 AF_INET6 -#define PF_UNSPEC AF_UNSPEC - -#define IPPROTO_IP 0 -#define IPPROTO_ICMP 1 -#define IPPROTO_TCP 6 -#define IPPROTO_UDP 17 - -#if LWIP_IPV6 -#define IPPROTO_IPV6 41 -#define IPPROTO_ICMPV6 58 -#endif /* LWIP_IPV6 */ - -#define IPPROTO_UDPLITE 136 -#define IPPROTO_RAW 255 - -/* Flags we can use with send and recv. */ -#define MSG_PEEK 0x01 /* Peeks at an incoming message */ -#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ -#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ -#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ -#define MSG_MORE 0x10 /* Sender will send more */ - - -/* - * Options for level IPPROTO_IP - */ -#define IP_TOS 1 -#define IP_TTL 2 - -#if LWIP_TCP -/* - * Options for level IPPROTO_TCP - */ -#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ -#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ -#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ -#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ -#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ -#endif /* LWIP_TCP */ - -#if LWIP_IPV6 -/* - * Options for level IPPROTO_IPV6 - */ -#define IPV6_CHECKSUM 7 /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */ -#define IPV6_V6ONLY 27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */ -#endif /* LWIP_IPV6 */ - -#if LWIP_UDP && LWIP_UDPLITE -/* - * Options for level IPPROTO_UDPLITE - */ -#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ -#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ -#endif /* LWIP_UDP && LWIP_UDPLITE*/ - - -#if LWIP_MULTICAST_TX_OPTIONS -/* - * Options and types for UDP multicast traffic handling - */ -#define IP_MULTICAST_TTL 5 -#define IP_MULTICAST_IF 6 -#define IP_MULTICAST_LOOP 7 -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - -#if LWIP_IGMP -/* - * Options and types related to multicast membership - */ -#define IP_ADD_MEMBERSHIP 3 -#define IP_DROP_MEMBERSHIP 4 - -typedef struct ip_mreq { - struct in_addr imr_multiaddr; /* IP multicast address of group */ - struct in_addr imr_interface; /* local IP address of interface */ -} ip_mreq; -#endif /* LWIP_IGMP */ - -/* - * The Type of Service provides an indication of the abstract - * parameters of the quality of service desired. These parameters are - * to be used to guide the selection of the actual service parameters - * when transmitting a datagram through a particular network. Several - * networks offer service precedence, which somehow treats high - * precedence traffic as more important than other traffic (generally - * by accepting only traffic above a certain precedence at time of high - * load). The major choice is a three way tradeoff between low-delay, - * high-reliability, and high-throughput. - * The use of the Delay, Throughput, and Reliability indications may - * increase the cost (in some sense) of the service. In many networks - * better performance for one of these parameters is coupled with worse - * performance on another. Except for very unusual cases at most two - * of these three indications should be set. - */ -#define IPTOS_TOS_MASK 0x1E -#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) -#define IPTOS_LOWDELAY 0x10 -#define IPTOS_THROUGHPUT 0x08 -#define IPTOS_RELIABILITY 0x04 -#define IPTOS_LOWCOST 0x02 -#define IPTOS_MINCOST IPTOS_LOWCOST - -/* - * The Network Control precedence designation is intended to be used - * within a network only. The actual use and control of that - * designation is up to each network. The Internetwork Control - * designation is intended for use by gateway control originators only. - * If the actual use of these precedence designations is of concern to - * a particular network, it is the responsibility of that network to - * control the access to, and use of, those precedence designations. - */ -#define IPTOS_PREC_MASK 0xe0 -#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) -#define IPTOS_PREC_NETCONTROL 0xe0 -#define IPTOS_PREC_INTERNETCONTROL 0xc0 -#define IPTOS_PREC_CRITIC_ECP 0xa0 -#define IPTOS_PREC_FLASHOVERRIDE 0x80 -#define IPTOS_PREC_FLASH 0x60 -#define IPTOS_PREC_IMMEDIATE 0x40 -#define IPTOS_PREC_PRIORITY 0x20 -#define IPTOS_PREC_ROUTINE 0x00 - - -/* - * Commands for ioctlsocket(), taken from the BSD file fcntl.h. - * lwip_ioctl only supports FIONREAD and FIONBIO, for now - * - * Ioctl's have the command encoded in the lower word, - * and the size of any in or out parameters in the upper - * word. The high 2 bits of the upper word are used - * to encode the in/out status of the parameter; for now - * we restrict parameters to at most 128 bytes. - */ -#if !defined(FIONREAD) || !defined(FIONBIO) -#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ -#define IOC_VOID 0x20000000UL /* no parameters */ -#define IOC_OUT 0x40000000UL /* copy out parameters */ -#define IOC_IN 0x80000000UL /* copy in parameters */ -#define IOC_INOUT (IOC_IN|IOC_OUT) - /* 0x20000000 distinguishes new & - old ioctl's */ -#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) - -#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) - -#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) -#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ - -#ifndef FIONREAD -#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ -#endif -#ifndef FIONBIO -#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ -#endif - -/* Socket I/O Controls: unimplemented */ -#ifndef SIOCSHIWAT -#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ -#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ -#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ -#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ -#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ -#endif - -/* commands for fnctl */ -#ifndef F_GETFL -#define F_GETFL 3 -#endif -#ifndef F_SETFL -#define F_SETFL 4 -#endif - -/* File status flags and file access modes for fnctl, - these are bits in an int. */ -#ifndef O_NONBLOCK -#define O_NONBLOCK 1 /* nonblocking I/O */ -#endif -#ifndef O_NDELAY -#define O_NDELAY 1 /* same as O_NONBLOCK, for compatibility */ -#endif - -#ifndef SHUT_RD - #define SHUT_RD 0 - #define SHUT_WR 1 - #define SHUT_RDWR 2 -#endif - -/* FD_SET used for lwip_select */ -#ifndef FD_SET -#undef FD_SETSIZE -/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ -#define FD_SETSIZE MEMP_NUM_NETCONN -#define FDSETSAFESET(n, code) do { \ - if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \ - code; }} while(0) -#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\ - (code) : 0) -#define FD_SET(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] |= (1 << (((n)-LWIP_SOCKET_OFFSET) & 7))) -#define FD_CLR(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &= ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7))) -#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & (1 << (((n)-LWIP_SOCKET_OFFSET) & 7))) -#define FD_ZERO(p) os_memset((void*)(p), 0, sizeof(*(p))) - -typedef struct fd_set -{ - unsigned char fd_bits [(FD_SETSIZE+7)/8]; -} fd_set; - -#elif LWIP_SOCKET_OFFSET -#error LWIP_SOCKET_OFFSET does not work with external FD_SET! -#elif FD_SETSIZE < MEMP_NUM_NETCONN -#error "external FD_SETSIZE too small for number of sockets" -#endif /* FD_SET */ - -/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided - * by your system, set this to 0 and include in cc.h */ -#ifndef LWIP_TIMEVAL_PRIVATE -#define LWIP_TIMEVAL_PRIVATE 0 -#endif - -#if LWIP_TIMEVAL_PRIVATE -struct timeval { - long tv_sec; /* seconds */ - long tv_usec; /* and microseconds */ -}; -#endif /* LWIP_TIMEVAL_PRIVATE */ - -#define lwip_socket_init() /* Compatibility define, no init needed. */ -void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ -void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ - -#if LWIP_COMPAT_SOCKETS == 2 -/* This helps code parsers/code completion by not having the COMPAT functions as defines */ -#define lwip_accept accept -#define lwip_bind bind -#define lwip_shutdown shutdown -#define lwip_getpeername getpeername -#define lwip_getsockname getsockname -#define lwip_setsockopt setsockopt -#define lwip_getsockopt getsockopt -#define lwip_close closesocket -#define lwip_connect connect -#define lwip_listen listen -#define lwip_recv recv -#define lwip_recvfrom recvfrom -#define lwip_send send -#define lwip_sendmsg sendmsg -#define lwip_sendto sendto -#define lwip_socket socket -#define lwip_select select -#define lwip_ioctlsocket ioctl - -#if LWIP_POSIX_SOCKETS_IO_NAMES -#define lwip_read read -#define lwip_write write -#define lwip_writev writev -#undef lwip_close -#define lwip_close close -#define closesocket(s) close(s) -#define lwip_fcntl fcntl -#define lwip_ioctl ioctl -#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ -#endif /* LWIP_COMPAT_SOCKETS == 2 */ - -int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); -int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); -int lwip_shutdown(int s, int how); -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); -int lwip_close(int s); -int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); -int lwip_listen(int s, int backlog); -int lwip_recv(int s, void *mem, size_t len, int flags); -int lwip_read(int s, void *mem, size_t len); -int lwip_recvfrom(int s, void *mem, size_t len, int flags, - struct sockaddr *from, socklen_t *fromlen); -int lwip_send(int s, const void *dataptr, size_t size, int flags); -int lwip_sendmsg(int s, const struct msghdr *message, int flags); -int lwip_sendto(int s, const void *dataptr, size_t size, int flags, - const struct sockaddr *to, socklen_t tolen); -int lwip_socket(int domain, int type, int protocol); -int lwip_write(int s, const void *dataptr, size_t size); -int lwip_writev(int s, const struct iovec *iov, int iovcnt); -int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout); -int lwip_ioctl(int s, long cmd, void *argp); -int lwip_fcntl(int s, int cmd, int val); - -#if LWIP_COMPAT_SOCKETS -#if LWIP_COMPAT_SOCKETS != 2 -/** @ingroup socket */ -#define accept(s,addr,addrlen) lwip_accept(s,addr,addrlen) -/** @ingroup socket */ -#define bind(s,name,namelen) lwip_bind(s,name,namelen) -/** @ingroup socket */ -#define shutdown(s,how) lwip_shutdown(s,how) -/** @ingroup socket */ -#define getpeername(s,name,namelen) lwip_getpeername(s,name,namelen) -/** @ingroup socket */ -#define getsockname(s,name,namelen) lwip_getsockname(s,name,namelen) -/** @ingroup socket */ -#define setsockopt(s,level,optname,opval,optlen) lwip_setsockopt(s,level,optname,opval,optlen) -/** @ingroup socket */ -#define getsockopt(s,level,optname,opval,optlen) lwip_getsockopt(s,level,optname,opval,optlen) -/** @ingroup socket */ -#define closesocket(s) lwip_close(s) -/** @ingroup socket */ -#define connect(s,name,namelen) lwip_connect(s,name,namelen) -/** @ingroup socket */ -#define listen(s,backlog) lwip_listen(s,backlog) -/** @ingroup socket */ -#define recv(s,mem,len,flags) lwip_recv(s,mem,len,flags) -/** @ingroup socket */ -#define recvfrom(s,mem,len,flags,from,fromlen) lwip_recvfrom(s,mem,len,flags,from,fromlen) -/** @ingroup socket */ -#define send(s,dataptr,size,flags) lwip_send(s,dataptr,size,flags) -/** @ingroup socket */ -#define sendmsg(s,message,flags) lwip_sendmsg(s,message,flags) -/** @ingroup socket */ -#define sendto(s,dataptr,size,flags,to,tolen) lwip_sendto(s,dataptr,size,flags,to,tolen) -/** @ingroup socket */ -#define socket(domain,type,protocol) lwip_socket(domain,type,protocol) -/** @ingroup socket */ -#define select(maxfdp1,readset,writeset,exceptset,timeout) lwip_select(maxfdp1,readset,writeset,exceptset,timeout) -/** @ingroup socket */ -#define ioctlsocket(s,cmd,argp) lwip_ioctl(s,cmd,argp) - -#if LWIP_POSIX_SOCKETS_IO_NAMES -/** @ingroup socket */ -#define read(s,mem,len) lwip_read(s,mem,len) -/** @ingroup socket */ -#define write(s,dataptr,len) lwip_write(s,dataptr,len) -/** @ingroup socket */ -#define writev(s,iov,iovcnt) lwip_writev(s,iov,iovcnt) -/** @ingroup socket */ -#define close(s) lwip_close(s) -/** @ingroup socket */ -#define fcntl(s,cmd,val) lwip_fcntl(s,cmd,val) -/** @ingroup socket */ -#define ioctl(s,cmd,argp) lwip_ioctl(s,cmd,argp) -#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ -#endif /* LWIP_COMPAT_SOCKETS != 2 */ - -#if LWIP_IPV4 && LWIP_IPV6 -/** @ingroup socket */ -#define inet_ntop(af,src,dst,size) \ - (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) \ - : (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL)) -/** @ingroup socket */ -#define inet_pton(af,src,dst) \ - (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) \ - : (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0)) -#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */ -#define inet_ntop(af,src,dst,size) \ - (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL) -#define inet_pton(af,src,dst) \ - (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0) -#else /* LWIP_IPV4 && LWIP_IPV6 */ -#define inet_ntop(af,src,dst,size) \ - (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) : NULL) -#define inet_pton(af,src,dst) \ - (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) : 0) -#endif /* LWIP_IPV4 && LWIP_IPV6 */ - -#endif /* LWIP_COMPAT_SOCKETS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SOCKET */ - -#endif /* LWIP_HDR_SOCKETS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/stats.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/stats.h deleted file mode 100644 index bcda2ace6e4310d2cc38b204449fec07aaacf13f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/stats.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - * @file - * Statistics API (to be used from TCPIP thread) - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_STATS_H -#define LWIP_HDR_STATS_H - -#include "lwip/opt.h" - -#include "lwip/mem.h" -#include "lwip/memp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_STATS - -#ifndef LWIP_STATS_LARGE -#define LWIP_STATS_LARGE 0 -#endif - -#if LWIP_STATS_LARGE -#define STAT_COUNTER u32_t -#define STAT_COUNTER_F U32_F -#else -#define STAT_COUNTER u16_t -#define STAT_COUNTER_F U16_F -#endif - -/** Protocol related stats */ -struct stats_proto { - STAT_COUNTER xmit; /* Transmitted packets. */ - STAT_COUNTER recv; /* Received packets. */ - STAT_COUNTER fw; /* Forwarded packets. */ - STAT_COUNTER drop; /* Dropped packets. */ - STAT_COUNTER chkerr; /* Checksum error. */ - STAT_COUNTER lenerr; /* Invalid length error. */ - STAT_COUNTER memerr; /* Out of memory error. */ - STAT_COUNTER rterr; /* Routing error. */ - STAT_COUNTER proterr; /* Protocol error. */ - STAT_COUNTER opterr; /* Error in options. */ - STAT_COUNTER err; /* Misc error. */ - STAT_COUNTER cachehit; -}; - -/** IGMP stats */ -struct stats_igmp { - STAT_COUNTER xmit; /* Transmitted packets. */ - STAT_COUNTER recv; /* Received packets. */ - STAT_COUNTER drop; /* Dropped packets. */ - STAT_COUNTER chkerr; /* Checksum error. */ - STAT_COUNTER lenerr; /* Invalid length error. */ - STAT_COUNTER memerr; /* Out of memory error. */ - STAT_COUNTER proterr; /* Protocol error. */ - STAT_COUNTER rx_v1; /* Received v1 frames. */ - STAT_COUNTER rx_group; /* Received group-specific queries. */ - STAT_COUNTER rx_general; /* Received general queries. */ - STAT_COUNTER rx_report; /* Received reports. */ - STAT_COUNTER tx_join; /* Sent joins. */ - STAT_COUNTER tx_leave; /* Sent leaves. */ - STAT_COUNTER tx_report; /* Sent reports. */ -}; - -/** Memory stats */ -struct stats_mem { -#if defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY - const char *name; -#endif /* defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY */ - STAT_COUNTER err; - mem_size_t avail; - mem_size_t used; - mem_size_t max; - STAT_COUNTER illegal; -}; - -/** System element stats */ -struct stats_syselem { - STAT_COUNTER used; - STAT_COUNTER max; - STAT_COUNTER err; -}; - -/** System stats */ -struct stats_sys { - struct stats_syselem sem; - struct stats_syselem mutex; - struct stats_syselem mbox; -}; - -/** SNMP MIB2 stats */ -struct stats_mib2 { - /* IP */ - u32_t ipinhdrerrors; - u32_t ipinaddrerrors; - u32_t ipinunknownprotos; - u32_t ipindiscards; - u32_t ipindelivers; - u32_t ipoutrequests; - u32_t ipoutdiscards; - u32_t ipoutnoroutes; - u32_t ipreasmoks; - u32_t ipreasmfails; - u32_t ipfragoks; - u32_t ipfragfails; - u32_t ipfragcreates; - u32_t ipreasmreqds; - u32_t ipforwdatagrams; - u32_t ipinreceives; - - /* TCP */ - u32_t tcpactiveopens; - u32_t tcppassiveopens; - u32_t tcpattemptfails; - u32_t tcpestabresets; - u32_t tcpoutsegs; - u32_t tcpretranssegs; - u32_t tcpinsegs; - u32_t tcpinerrs; - u32_t tcpoutrsts; - - /* UDP */ - u32_t udpindatagrams; - u32_t udpnoports; - u32_t udpinerrors; - u32_t udpoutdatagrams; - - /* ICMP */ - u32_t icmpinmsgs; - u32_t icmpinerrors; - u32_t icmpindestunreachs; - u32_t icmpintimeexcds; - u32_t icmpinparmprobs; - u32_t icmpinsrcquenchs; - u32_t icmpinredirects; - u32_t icmpinechos; - u32_t icmpinechoreps; - u32_t icmpintimestamps; - u32_t icmpintimestampreps; - u32_t icmpinaddrmasks; - u32_t icmpinaddrmaskreps; - u32_t icmpoutmsgs; - u32_t icmpouterrors; - u32_t icmpoutdestunreachs; - u32_t icmpouttimeexcds; - u32_t icmpoutechos; /* can be incremented by user application ('ping') */ - u32_t icmpoutechoreps; -}; - -/** - * @ingroup netif_mib2 - * SNMP MIB2 interface stats - */ -struct stats_mib2_netif_ctrs { - /** The total number of octets received on the interface, including framing characters */ - u32_t ifinoctets; - /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were - * not addressed to a multicast or broadcast address at this sub-layer */ - u32_t ifinucastpkts; - /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were - * addressed to a multicast or broadcast address at this sub-layer */ - u32_t ifinnucastpkts; - /** The number of inbound packets which were chosen to be discarded even though no errors had - * been detected to prevent their being deliverable to a higher-layer protocol. One possible - * reason for discarding such a packet could be to free up buffer space */ - u32_t ifindiscards; - /** For packet-oriented interfaces, the number of inbound packets that contained errors - * preventing them from being deliverable to a higher-layer protocol. For character- - * oriented or fixed-length interfaces, the number of inbound transmission units that - * contained errors preventing them from being deliverable to a higher-layer protocol. */ - u32_t ifinerrors; - /** For packet-oriented interfaces, the number of packets received via the interface which - * were discarded because of an unknown or unsupported protocol. For character-oriented - * or fixed-length interfaces that support protocol multiplexing the number of transmission - * units received via the interface which were discarded because of an unknown or unsupported - * protocol. For any interface that does not support protocol multiplexing, this counter will - * always be 0 */ - u32_t ifinunknownprotos; - /** The total number of octets transmitted out of the interface, including framing characters. */ - u32_t ifoutoctets; - /** The total number of packets that higher-level protocols requested be transmitted, and - * which were not addressed to a multicast or broadcast address at this sub-layer, including - * those that were discarded or not sent. */ - u32_t ifoutucastpkts; - /** The total number of packets that higher-level protocols requested be transmitted, and which - * were addressed to a multicast or broadcast address at this sub-layer, including - * those that were discarded or not sent. */ - u32_t ifoutnucastpkts; - /** The number of outbound packets which were chosen to be discarded even though no errors had - * been detected to prevent their being transmitted. One possible reason for discarding - * such a packet could be to free up buffer space. */ - u32_t ifoutdiscards; - /** For packet-oriented interfaces, the number of outbound packets that could not be transmitted - * because of errors. For character-oriented or fixed-length interfaces, the number of outbound - * transmission units that could not be transmitted because of errors. */ - u32_t ifouterrors; -}; - -/** lwIP stats container */ -struct stats_ { -#if LINK_STATS - /** Link level */ - struct stats_proto link; -#endif -#if ETHARP_STATS - /** ARP */ - struct stats_proto etharp; -#endif -#if IPFRAG_STATS - /** Fragmentation */ - struct stats_proto ip_frag; -#endif -#if IP_STATS - /** IP */ - struct stats_proto ip; -#endif -#if ICMP_STATS - /** ICMP */ - struct stats_proto icmp; -#endif -#if IGMP_STATS - /** IGMP */ - struct stats_igmp igmp; -#endif -#if UDP_STATS - /** UDP */ - struct stats_proto udp; -#endif -#if TCP_STATS - /** TCP */ - struct stats_proto tcp; -#endif -#if MEM_STATS - /** Heap */ - struct stats_mem mem; -#endif -#if MEMP_STATS - /** Internal memory pools */ - struct stats_mem *memp[MEMP_MAX]; -#endif -#if SYS_STATS - /** System */ - struct stats_sys sys; -#endif -#if IP6_STATS - /** IPv6 */ - struct stats_proto ip6; -#endif -#if ICMP6_STATS - /** ICMP6 */ - struct stats_proto icmp6; -#endif -#if IP6_FRAG_STATS - /** IPv6 fragmentation */ - struct stats_proto ip6_frag; -#endif -#if MLD6_STATS - /** Multicast listener discovery */ - struct stats_igmp mld6; -#endif -#if ND6_STATS - /** Neighbor discovery */ - struct stats_proto nd6; -#endif -#if MIB2_STATS - /** SNMP MIB2 */ - struct stats_mib2 mib2; -#endif -}; - -/** Global variable containing lwIP internal statistics. Add this to your debugger's watchlist. */ -extern struct stats_ lwip_stats; - -/** Init statistics */ -void stats_init(void); - -#define STATS_INC(x) ++lwip_stats.x -#define STATS_DEC(x) --lwip_stats.x -#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \ - if (lwip_stats.x.max < lwip_stats.x.used) { \ - lwip_stats.x.max = lwip_stats.x.used; \ - } \ - } while(0) -#define STATS_GET(x) lwip_stats.x -#else /* LWIP_STATS */ -#define stats_init() -#define STATS_INC(x) -#define STATS_DEC(x) -#define STATS_INC_USED(x) -#endif /* LWIP_STATS */ - -#if TCP_STATS -#define TCP_STATS_INC(x) STATS_INC(x) -#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") -#else -#define TCP_STATS_INC(x) -#define TCP_STATS_DISPLAY() -#endif - -#if UDP_STATS -#define UDP_STATS_INC(x) STATS_INC(x) -#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") -#else -#define UDP_STATS_INC(x) -#define UDP_STATS_DISPLAY() -#endif - -#if ICMP_STATS -#define ICMP_STATS_INC(x) STATS_INC(x) -#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") -#else -#define ICMP_STATS_INC(x) -#define ICMP_STATS_DISPLAY() -#endif - -#if IGMP_STATS -#define IGMP_STATS_INC(x) STATS_INC(x) -#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP") -#else -#define IGMP_STATS_INC(x) -#define IGMP_STATS_DISPLAY() -#endif - -#if IP_STATS -#define IP_STATS_INC(x) STATS_INC(x) -#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") -#else -#define IP_STATS_INC(x) -#define IP_STATS_DISPLAY() -#endif - -#if IPFRAG_STATS -#define IPFRAG_STATS_INC(x) STATS_INC(x) -#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") -#else -#define IPFRAG_STATS_INC(x) -#define IPFRAG_STATS_DISPLAY() -#endif - -#if ETHARP_STATS -#define ETHARP_STATS_INC(x) STATS_INC(x) -#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") -#else -#define ETHARP_STATS_INC(x) -#define ETHARP_STATS_DISPLAY() -#endif - -#if LINK_STATS -#define LINK_STATS_INC(x) STATS_INC(x) -#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") -#else -#define LINK_STATS_INC(x) -#define LINK_STATS_DISPLAY() -#endif - -#if MEM_STATS -#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y -#define MEM_STATS_INC(x) STATS_INC(mem.x) -#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y) -#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y -#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") -#else -#define MEM_STATS_AVAIL(x, y) -#define MEM_STATS_INC(x) -#define MEM_STATS_INC_USED(x, y) -#define MEM_STATS_DEC_USED(x, y) -#define MEM_STATS_DISPLAY() -#endif - - #if MEMP_STATS -#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i]->x) -#define MEMP_STATS_DISPLAY(i) stats_display_memp(lwip_stats.memp[i], i) -#define MEMP_STATS_GET(x, i) STATS_GET(memp[i]->x) - #else -#define MEMP_STATS_DEC(x, i) -#define MEMP_STATS_DISPLAY(i) -#define MEMP_STATS_GET(x, i) 0 -#endif - -#if SYS_STATS -#define SYS_STATS_INC(x) STATS_INC(sys.x) -#define SYS_STATS_DEC(x) STATS_DEC(sys.x) -#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1) -#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) -#else -#define SYS_STATS_INC(x) -#define SYS_STATS_DEC(x) -#define SYS_STATS_INC_USED(x) -#define SYS_STATS_DISPLAY() -#endif - -#if IP6_STATS -#define IP6_STATS_INC(x) STATS_INC(x) -#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6") -#else -#define IP6_STATS_INC(x) -#define IP6_STATS_DISPLAY() -#endif - -#if ICMP6_STATS -#define ICMP6_STATS_INC(x) STATS_INC(x) -#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6") -#else -#define ICMP6_STATS_INC(x) -#define ICMP6_STATS_DISPLAY() -#endif - -#if IP6_FRAG_STATS -#define IP6_FRAG_STATS_INC(x) STATS_INC(x) -#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG") -#else -#define IP6_FRAG_STATS_INC(x) -#define IP6_FRAG_STATS_DISPLAY() -#endif - -#if MLD6_STATS -#define MLD6_STATS_INC(x) STATS_INC(x) -#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1") -#else -#define MLD6_STATS_INC(x) -#define MLD6_STATS_DISPLAY() -#endif - -#if ND6_STATS -#define ND6_STATS_INC(x) STATS_INC(x) -#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND") -#else -#define ND6_STATS_INC(x) -#define ND6_STATS_DISPLAY() -#endif - -#if MIB2_STATS -#define MIB2_STATS_INC(x) STATS_INC(x) -#else -#define MIB2_STATS_INC(x) -#endif - -/* Display of statistics */ -#if LWIP_STATS_DISPLAY -void stats_display(void); -void stats_display_proto(struct stats_proto *proto, const char *name); -void stats_display_igmp(struct stats_igmp *igmp, const char *name); -void stats_display_mem(struct stats_mem *mem, const char *name); -void stats_display_memp(struct stats_mem *mem, int index); -void stats_display_sys(struct stats_sys *sys); -#else /* LWIP_STATS_DISPLAY */ -#define stats_display() -#define stats_display_proto(proto, name) -#define stats_display_igmp(igmp, name) -#define stats_display_mem(mem, name) -#define stats_display_memp(mem, index) -#define stats_display_sys(sys) -#endif /* LWIP_STATS_DISPLAY */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_STATS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sys.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sys.h deleted file mode 100644 index 9854cff1c38d806705877a1c8e6f9a3c3bf44d80..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/sys.h +++ /dev/null @@ -1,461 +0,0 @@ -/** - * @file - * OS abstraction layer - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - */ - -#ifndef LWIP_HDR_SYS_H -#define LWIP_HDR_SYS_H - -#include "lwip/opt.h" -#include "rtos_pub.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if NO_SYS - -/* For a totally minimal and standalone system, we provide null - definitions of the sys_ functions. */ -typedef u8_t sys_sem_t; -typedef u8_t sys_mutex_t; -typedef u8_t sys_mbox_t; - -#define sys_sem_new(s, c) ERR_OK -#define sys_sem_signal(s) -#define sys_sem_wait(s) -#define sys_arch_sem_wait(s,t) -#define sys_sem_free(s) -#define sys_sem_valid(s) 0 -#define sys_sem_valid_val(s) 0 -#define sys_sem_set_invalid(s) -#define sys_sem_set_invalid_val(s) -#define sys_mutex_new(mu) ERR_OK -#define sys_mutex_lock(mu) -#define sys_mutex_unlock(mu) -#define sys_mutex_free(mu) -#define sys_mutex_valid(mu) 0 -#define sys_mutex_set_invalid(mu) -#define sys_mbox_new(m, s) ERR_OK -#define sys_mbox_fetch(m,d) -#define sys_mbox_tryfetch(m,d) -#define sys_mbox_post(m,d) -#define sys_mbox_trypost(m,d) -#define sys_mbox_free(m) -#define sys_mbox_valid(m) -#define sys_mbox_valid_val(m) -#define sys_mbox_set_invalid(m) -#define sys_mbox_set_invalid_val(m) - -#define sys_thread_new(n,t,a,s,p) - -#define sys_msleep(t) - -#else /* NO_SYS */ - -/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ -#define SYS_ARCH_TIMEOUT 0xffffffffUL - -/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate. - * For now we use the same magic value, but we allow this to change in future. - */ -#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT - -#include "lwip/err.h" -#include "arch/sys_arch.h" - -/** Function prototype for thread functions */ -typedef void (*lwip_thread_fn)(void *arg); - -/* Function prototypes for functions to be implemented by platform ports - (in sys_arch.c) */ - -/* Mutex functions: */ - -/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores - should be used instead */ -#ifndef LWIP_COMPAT_MUTEX -#define LWIP_COMPAT_MUTEX 0 -#endif - -#if LWIP_COMPAT_MUTEX -/* for old ports that don't have mutexes: define them to binary semaphores */ -#define sys_mutex_t sys_sem_t -#define sys_mutex_new(mutex) sys_sem_new(mutex, 1) -#define sys_mutex_lock(mutex) sys_sem_wait(mutex) -#define sys_mutex_unlock(mutex) sys_sem_signal(mutex) -#define sys_mutex_free(mutex) sys_sem_free(mutex) -#define sys_mutex_valid(mutex) sys_sem_valid(mutex) -#define sys_mutex_set_invalid(mutex) sys_sem_set_invalid(mutex) - -#else /* LWIP_COMPAT_MUTEX */ - -typedef beken_mutex_t sys_mutex_t; - -/** - * @ingroup sys_mutex - * Create a new mutex. - * Note that mutexes are expected to not be taken recursively by the lwIP code, - * so both implementation types (recursive or non-recursive) should work. - * @param mutex pointer to the mutex to create - * @return ERR_OK if successful, another err_t otherwise - */ -err_t sys_mutex_new(sys_mutex_t *mutex); -/** - * @ingroup sys_mutex - * Lock a mutex - * @param mutex the mutex to lock - */ -void sys_mutex_lock(sys_mutex_t *mutex); -/** - * @ingroup sys_mutex - * Unlock a mutex - * @param mutex the mutex to unlock - */ -void sys_mutex_unlock(sys_mutex_t *mutex); -/** - * @ingroup sys_mutex - * Delete a semaphore - * @param mutex the mutex to delete - */ -void sys_mutex_free(sys_mutex_t *mutex); - -#ifndef sys_mutex_valid -/** - * @ingroup sys_mutex - * Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid - */ -int sys_mutex_valid(sys_mutex_t *mutex); -#endif - -#ifndef sys_mutex_set_invalid -/** - * @ingroup sys_mutex - * Set a mutex invalid so that sys_mutex_valid returns 0 - */ -void sys_mutex_set_invalid(sys_mutex_t *mutex); -#endif - -#endif /* LWIP_COMPAT_MUTEX */ - -/* Semaphore functions: */ - -/** - * @ingroup sys_sem - * Create a new semaphore - * @param sem pointer to the semaphore to create - * @param count initial count of the semaphore - * @return ERR_OK if successful, another err_t otherwise - */ -err_t sys_sem_new(sys_sem_t *sem, u8_t count); -/** - * @ingroup sys_sem - * Signals a semaphore - * @param sem the semaphore to signal - */ -void sys_sem_signal(sys_sem_t *sem); -/** - * @ingroup sys_sem - * Wait for a semaphore for the specified timeout - * @param sem the semaphore to wait for - * @param timeout timeout in milliseconds to wait (0 = wait forever) - * @return time (in milliseconds) waited for the semaphore - * or SYS_ARCH_TIMEOUT on timeout - */ -u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout); -/** - * @ingroup sys_sem - * Delete a semaphore - * @param sem semaphore to delete - */ -void sys_sem_free(sys_sem_t *sem); -/** Wait for a semaphore - forever/no timeout */ -#define sys_sem_wait(sem) sys_arch_sem_wait(sem, 0) -#ifndef sys_sem_valid -/** - * @ingroup sys_sem - * Check if a semaphore is valid/allocated: return 1 for valid, 0 for invalid - */ -int sys_sem_valid(sys_sem_t *sem); -#endif -#ifndef sys_sem_set_invalid -/** - * @ingroup sys_sem - * Set a semaphore invalid so that sys_sem_valid returns 0 - */ -void sys_sem_set_invalid(sys_sem_t *sem); -#endif -#ifndef sys_sem_valid_val -/** - * Same as sys_sem_valid() but taking a value, not a pointer - */ -#define sys_sem_valid_val(sem) sys_sem_valid(&(sem)) -#endif -#ifndef sys_sem_set_invalid_val -/** - * Same as sys_sem_set_invalid() but taking a value, not a pointer - */ -#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem)) -#endif - -#ifndef sys_msleep -/** - * @ingroup sys_misc - * Sleep for specified number of ms - */ -void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */ -#endif - -/* Mailbox functions. */ - -/** - * @ingroup sys_mbox - * Create a new mbox of specified size - * @param mbox pointer to the mbox to create - * @param size (minimum) number of messages in this mbox - * @return ERR_OK if successful, another err_t otherwise - */ -err_t sys_mbox_new(sys_mbox_t *mbox, int size); -/** - * @ingroup sys_mbox - * Post a message to an mbox - may not fail - * -> blocks if full, only used from tasks not from ISR - * @param mbox mbox to posts the message - * @param msg message to post (ATTENTION: can be NULL) - */ -void sys_mbox_post(sys_mbox_t *mbox, void *msg); -/** - * @ingroup sys_mbox - * Try to post a message to an mbox - may fail if full or ISR - * @param mbox mbox to posts the message - * @param msg message to post (ATTENTION: can be NULL) - */ -err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg); -/** - * @ingroup sys_mbox - * Wait for a new message to arrive in the mbox - * @param mbox mbox to get a message from - * @param msg pointer where the message is stored - * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever) - * @return time (in milliseconds) waited for a message, may be 0 if not waited - or SYS_ARCH_TIMEOUT on timeout - * The returned time has to be accurate to prevent timer jitter! - */ -u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout); -/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */ -#ifndef sys_arch_mbox_tryfetch -/** - * @ingroup sys_mbox - * Wait for a new message to arrive in the mbox - * @param mbox mbox to get a message from - * @param msg pointer where the message is stored - * @return 0 (milliseconds) if a message has been received - * or SYS_MBOX_EMPTY if the mailbox is empty - */ -u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg); -#endif -/** - * For now, we map straight to sys_arch implementation. - */ -#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) -/** - * @ingroup sys_mbox - * Delete an mbox - * @param mbox mbox to delete - */ -void sys_mbox_free(sys_mbox_t *mbox); -#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0) -#ifndef sys_mbox_valid -/** - * @ingroup sys_mbox - * Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid - */ -int sys_mbox_valid(sys_mbox_t *mbox); -#endif -#ifndef sys_mbox_set_invalid -/** - * @ingroup sys_mbox - * Set an mbox invalid so that sys_mbox_valid returns 0 - */ -void sys_mbox_set_invalid(sys_mbox_t *mbox); -#endif -#ifndef sys_mbox_valid_val -/** - * Same as sys_mbox_valid() but taking a value, not a pointer - */ -#define sys_mbox_valid_val(mbox) sys_mbox_valid(&(mbox)) -#endif -#ifndef sys_mbox_set_invalid_val -/** - * Same as sys_mbox_set_invalid() but taking a value, not a pointer - */ -#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox)) -#endif - - -/** - * @ingroup sys_misc - * The only thread function: - * Creates a new thread - * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!) - * @param name human-readable name for the thread (used for debugging purposes) - * @param thread thread-function - * @param arg parameter passed to 'thread' - * @param stacksize stack size in bytes for the new thread (may be ignored by ports) - * @param prio priority of the new thread (may be ignored by ports) */ -sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio); - -#endif /* NO_SYS */ - -/* sys_init() must be called before anything else. */ -void sys_init(void); - -#ifndef sys_jiffies -/** - * Ticks/jiffies since power up. - */ -u32_t sys_jiffies(void); -#endif - -/** - * @ingroup sys_time - * Returns the current time in milliseconds, - * may be the same as sys_jiffies or at least based on it. - */ -u32_t sys_now(void); - -/* Critical Region Protection */ -/* These functions must be implemented in the sys_arch.c file. - In some implementations they can provide a more light-weight protection - mechanism than using semaphores. Otherwise semaphores can be used for - implementation */ -#ifndef SYS_ARCH_PROTECT -/** SYS_LIGHTWEIGHT_PROT - * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#if SYS_LIGHTWEIGHT_PROT - -/** - * @ingroup sys_prot - * SYS_ARCH_DECL_PROTECT - * declare a protection variable. This macro will default to defining a variable of - * type sys_prot_t. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h. - */ -#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev -/** - * @ingroup sys_prot - * SYS_ARCH_PROTECT - * Perform a "fast" protect. This could be implemented by - * disabling interrupts for an embedded system or by using a semaphore or - * mutex. The implementation should allow calling SYS_ARCH_PROTECT when - * already protected. The old protection level is returned in the variable - * "lev". This macro will default to calling the sys_arch_protect() function - * which should be implemented in sys_arch.c. If a particular port needs a - * different implementation, then this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() -/** - * @ingroup sys_prot - * SYS_ARCH_UNPROTECT - * Perform a "fast" set of the protection level to "lev". This could be - * implemented by setting the interrupt level to "lev" within the MACRO or by - * using a semaphore or mutex. This macro will default to calling the - * sys_arch_unprotect() function which should be implemented in - * sys_arch.c. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) -sys_prot_t sys_arch_protect(void); -void sys_arch_unprotect(sys_prot_t pval); - -#else - -#define SYS_ARCH_DECL_PROTECT(lev) -#define SYS_ARCH_PROTECT(lev) -#define SYS_ARCH_UNPROTECT(lev) - -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#endif /* SYS_ARCH_PROTECT */ - -/* - * Macros to set/get and increase/decrease variables in a thread-safe way. - * Use these for accessing variable that are used from more than one thread. - */ - -#ifndef SYS_ARCH_INC -#define SYS_ARCH_INC(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var += val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_INC */ - -#ifndef SYS_ARCH_DEC -#define SYS_ARCH_DEC(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var -= val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_DEC */ - -#ifndef SYS_ARCH_GET -#define SYS_ARCH_GET(var, ret) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - ret = var; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_GET */ - -#ifndef SYS_ARCH_SET -#define SYS_ARCH_SET(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var = val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_SET */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_SYS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcp.h deleted file mode 100644 index 34d1c101583329196e7ca66c952575f4f97da4ca..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcp.h +++ /dev/null @@ -1,433 +0,0 @@ -/** - * @file - * TCP API (to be used from TCPIP thread)\n - * See also @ref tcp_raw - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_TCP_H -#define LWIP_HDR_TCP_H - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/ip.h" -#include "lwip/icmp.h" -#include "lwip/err.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct tcp_pcb; - -/** Function prototype for tcp accept callback functions. Called when a new - * connection can be accepted on a listening pcb. - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param newpcb The new connection pcb - * @param err An error code if there has been an error accepting. - * Only return ERR_ABRT if you have called tcp_abort from within the - * callback function! - */ -typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err); - -/** Function prototype for tcp receive callback functions. Called when data has - * been received. - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param tpcb The connection pcb which received data - * @param p The received data (or NULL when the connection has been closed!) - * @param err An error code if there has been an error receiving - * Only return ERR_ABRT if you have called tcp_abort from within the - * callback function! - */ -typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err); - -/** Function prototype for tcp sent callback functions. Called when sent data has - * been acknowledged by the remote side. Use it to free corresponding resources. - * This also means that the pcb has now space available to send new data. - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param tpcb The connection pcb for which data has been acknowledged - * @param len The amount of bytes acknowledged - * @return ERR_OK: try to send some data by calling tcp_output - * Only return ERR_ABRT if you have called tcp_abort from within the - * callback function! - */ -typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb, - u16_t len); - -/** Function prototype for tcp poll callback functions. Called periodically as - * specified by @see tcp_poll. - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param tpcb tcp pcb - * @return ERR_OK: try to send some data by calling tcp_output - * Only return ERR_ABRT if you have called tcp_abort from within the - * callback function! - */ -typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb); - -/** Function prototype for tcp error callback functions. Called when the pcb - * receives a RST or is unexpectedly closed for any other reason. - * - * @note The corresponding pcb is already freed when this callback is called! - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param err Error code to indicate why the pcb has been closed - * ERR_ABRT: aborted through tcp_abort or by a TCP timer - * ERR_RST: the connection was reset by the remote host - */ -typedef void (*tcp_err_fn)(void *arg, err_t err); - -/** Function prototype for tcp connected callback functions. Called when a pcb - * is connected to the remote side after initiating a connection attempt by - * calling tcp_connect(). - * - * @param arg Additional argument to pass to the callback function (@see tcp_arg()) - * @param tpcb The connection pcb which is connected - * @param err An unused error code, always ERR_OK currently ;-) @todo! - * Only return ERR_ABRT if you have called tcp_abort from within the - * callback function! - * - * @note When a connection attempt fails, the error callback is currently called! - */ -typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err); - -#if LWIP_WND_SCALE -#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale)) -#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale)) -#define TCPWND16(x) ((u16_t)LWIP_MIN((x), 0xFFFF)) -#define TCP_WND_MAX(pcb) ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND))) -typedef u32_t tcpwnd_size_t; -#else -#define RCV_WND_SCALE(pcb, wnd) (wnd) -#define SND_WND_SCALE(pcb, wnd) (wnd) -#define TCPWND16(x) (x) -#define TCP_WND_MAX(pcb) TCP_WND -typedef u16_t tcpwnd_size_t; -#endif - -#if LWIP_WND_SCALE || TCP_LISTEN_BACKLOG || LWIP_TCP_TIMESTAMPS -typedef u16_t tcpflags_t; -#else -typedef u8_t tcpflags_t; -#endif - -enum tcp_state { - CLOSED = 0, - LISTEN = 1, - SYN_SENT = 2, - SYN_RCVD = 3, - ESTABLISHED = 4, - FIN_WAIT_1 = 5, - FIN_WAIT_2 = 6, - CLOSE_WAIT = 7, - CLOSING = 8, - LAST_ACK = 9, - TIME_WAIT = 10 -}; - -/** - * members common to struct tcp_pcb and struct tcp_listen_pcb - */ -#define TCP_PCB_COMMON(type) \ - type *next; /* for the linked list */ \ - void *callback_arg; \ - enum tcp_state state; /* TCP state */ \ - u8_t prio; \ - /* ports are in host byte order */ \ - u16_t local_port - - -/** the TCP protocol control block for listening pcbs */ -struct tcp_pcb_listen { -/** Common members of all PCB types */ - IP_PCB; -/** Protocol specific PCB members */ - TCP_PCB_COMMON(struct tcp_pcb_listen); - -#if LWIP_CALLBACK_API - /* Function to call when a listener has been connected. */ - tcp_accept_fn accept; -#endif /* LWIP_CALLBACK_API */ - -#if TCP_LISTEN_BACKLOG - u8_t backlog; - u8_t accepts_pending; -#endif /* TCP_LISTEN_BACKLOG */ -}; - - -/** the TCP protocol control block */ -struct tcp_pcb { -/** common PCB members */ - IP_PCB; -/** protocol specific PCB members */ - TCP_PCB_COMMON(struct tcp_pcb); - - /* ports are in host byte order */ - u16_t remote_port; - - tcpflags_t flags; -#define TF_ACK_DELAY 0x01U /* Delayed ACK. */ -#define TF_ACK_NOW 0x02U /* Immediate ACK. */ -#define TF_INFR 0x04U /* In fast recovery. */ -#define TF_CLOSEPEND 0x08U /* If this is set, tcp_close failed to enqueue the FIN (retried in tcp_tmr) */ -#define TF_RXCLOSED 0x10U /* rx closed by tcp_shutdown */ -#define TF_FIN 0x20U /* Connection was closed locally (FIN segment enqueued). */ -#define TF_NODELAY 0x40U /* Disable Nagle algorithm */ -#define TF_NAGLEMEMERR 0x80U /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ -#if LWIP_WND_SCALE -#define TF_WND_SCALE 0x0100U /* Window Scale option enabled */ -#endif -#if TCP_LISTEN_BACKLOG -#define TF_BACKLOGPEND 0x0200U /* If this is set, a connection pcb has increased the backlog on its listener */ -#endif -#if LWIP_TCP_TIMESTAMPS -#define TF_TIMESTAMP 0x0400U /* Timestamp option enabled */ -#endif - - /* the rest of the fields are in host byte order - as we have to do some math with them */ - - /* Timers */ - u8_t polltmr, pollinterval; - u8_t last_timer; - u32_t tmr; - - /* receiver variables */ - u32_t rcv_nxt; /* next seqno expected */ - tcpwnd_size_t rcv_wnd; /* receiver window available */ - tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */ - u32_t rcv_ann_right_edge; /* announced right edge of window */ - - /* Retransmission timer. */ - s16_t rtime; - - u16_t mss; /* maximum segment size */ - - /* RTT (round trip time) estimation variables */ - u32_t rttest; /* RTT estimate in 500ms ticks */ - u32_t rtseq; /* sequence number being timed */ - s16_t sa, sv; /* @todo document this */ - - s16_t rto; /* retransmission time-out */ - u8_t nrtx; /* number of retransmissions */ - - /* fast retransmit/recovery */ - u8_t dupacks; - u32_t lastack; /* Highest acknowledged seqno. */ - - /* congestion avoidance/control variables */ - tcpwnd_size_t cwnd; - tcpwnd_size_t ssthresh; - - /* sender variables */ - u32_t snd_nxt; /* next new seqno to be sent */ - u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last - window update. */ - u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ - tcpwnd_size_t snd_wnd; /* sender window */ - tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */ - - tcpwnd_size_t snd_buf; /* Available buffer space for sending (in bytes). */ -#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3) - u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */ - -#if TCP_OVERSIZE - /* Extra bytes available at the end of the last pbuf in unsent. */ - u16_t unsent_oversize; -#endif /* TCP_OVERSIZE */ - - /* These are ordered by sequence number: */ - struct tcp_seg *unsent; /* Unsent (queued) segments. */ - struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ -#if TCP_QUEUE_OOSEQ - struct tcp_seg *ooseq; /* Received out of sequence segments. */ -#endif /* TCP_QUEUE_OOSEQ */ - - struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ - -#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG - struct tcp_pcb_listen* listener; -#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ - -#if LWIP_CALLBACK_API - /* Function to be called when more send buffer space is available. */ - tcp_sent_fn sent; - /* Function to be called when (in-sequence) data has arrived. */ - tcp_recv_fn recv; - /* Function to be called when a connection has been set up. */ - tcp_connected_fn connected; - /* Function which is called periodically. */ - tcp_poll_fn poll; - /* Function to be called whenever a fatal error occurs. */ - tcp_err_fn errf; -#endif /* LWIP_CALLBACK_API */ - -#if LWIP_TCP_TIMESTAMPS - u32_t ts_lastacksent; - u32_t ts_recent; -#endif /* LWIP_TCP_TIMESTAMPS */ - - /* idle time before KEEPALIVE is sent */ - u32_t keep_idle; -#if LWIP_TCP_KEEPALIVE - u32_t keep_intvl; - u32_t keep_cnt; -#endif /* LWIP_TCP_KEEPALIVE */ - - /* Persist timer counter */ - u8_t persist_cnt; - /* Persist timer back-off */ - u8_t persist_backoff; - - /* KEEPALIVE counter */ - u8_t keep_cnt_sent; - -#if LWIP_WND_SCALE - u8_t snd_scale; - u8_t rcv_scale; -#endif -}; - -#if LWIP_EVENT_API - -enum lwip_event { - LWIP_EVENT_ACCEPT, - LWIP_EVENT_SENT, - LWIP_EVENT_RECV, - LWIP_EVENT_CONNECTED, - LWIP_EVENT_POLL, - LWIP_EVENT_ERR -}; - -err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, - enum lwip_event, - struct pbuf *p, - u16_t size, - err_t err); - -#endif /* LWIP_EVENT_API */ - -/* Application program's interface: */ -struct tcp_pcb * tcp_new (void); -struct tcp_pcb * tcp_new_ip_type (u8_t type); - -void tcp_arg (struct tcp_pcb *pcb, void *arg); -#if LWIP_CALLBACK_API -void tcp_recv (struct tcp_pcb *pcb, tcp_recv_fn recv); -void tcp_sent (struct tcp_pcb *pcb, tcp_sent_fn sent); -void tcp_err (struct tcp_pcb *pcb, tcp_err_fn err); -void tcp_accept (struct tcp_pcb *pcb, tcp_accept_fn accept); -#endif /* LWIP_CALLBACK_API */ -void tcp_poll (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval); - -#if LWIP_TCP_TIMESTAMPS -#define tcp_mss(pcb) (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12) : (pcb)->mss) -#else /* LWIP_TCP_TIMESTAMPS */ -#define tcp_mss(pcb) ((pcb)->mss) -#endif /* LWIP_TCP_TIMESTAMPS */ -#define tcp_sndbuf(pcb) (TCPWND16((pcb)->snd_buf)) -#define tcp_sndqueuelen(pcb) ((pcb)->snd_queuelen) -/** @ingroup tcp_raw */ -#define tcp_nagle_disable(pcb) ((pcb)->flags |= TF_NODELAY) -/** @ingroup tcp_raw */ -#define tcp_nagle_enable(pcb) ((pcb)->flags = (tcpflags_t)((pcb)->flags & ~TF_NODELAY)) -/** @ingroup tcp_raw */ -#define tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0) - -#if TCP_LISTEN_BACKLOG -#define tcp_backlog_set(pcb, new_backlog) do { \ - LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \ - ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0) -void tcp_backlog_delayed(struct tcp_pcb* pcb); -void tcp_backlog_accepted(struct tcp_pcb* pcb); -#else /* TCP_LISTEN_BACKLOG */ -#define tcp_backlog_set(pcb, new_backlog) -#define tcp_backlog_delayed(pcb) -#define tcp_backlog_accepted(pcb) -#endif /* TCP_LISTEN_BACKLOG */ -#define tcp_accepted(pcb) /* compatibility define, not needed any more */ - -void tcp_recved (struct tcp_pcb *pcb, u16_t len); -err_t tcp_bind (struct tcp_pcb *pcb, const ip_addr_t *ipaddr, - u16_t port); -err_t tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr, - u16_t port, tcp_connected_fn connected); - -struct tcp_pcb * tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err); -struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); -/** @ingroup tcp_raw */ -#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) - -void tcp_abort (struct tcp_pcb *pcb); -err_t tcp_close (struct tcp_pcb *pcb); -err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx); - -/* Flags for "apiflags" parameter in tcp_write */ -#define TCP_WRITE_FLAG_COPY 0x01 -#define TCP_WRITE_FLAG_MORE 0x02 - -err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, - u8_t apiflags); - -void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); - -#define TCP_PRIO_MIN 1 -#define TCP_PRIO_NORMAL 64 -#define TCP_PRIO_MAX 127 - -err_t tcp_output (struct tcp_pcb *pcb); - - -const char* tcp_debug_state_str(enum tcp_state s); - -/* for compatibility with older implementation */ -#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_TCP */ - -#endif /* LWIP_HDR_TCP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcpip.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcpip.h deleted file mode 100644 index f2f6b469f165cd8f66e1fee1fa286bb76378a0fb..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/tcpip.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * Functions to sync with TCPIP thread - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_TCPIP_H -#define LWIP_HDR_TCPIP_H - -#include "lwip/opt.h" - -#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/err.h" -#include "lwip/timeouts.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_TCPIP_CORE_LOCKING -/** The global semaphore to lock the stack. */ -extern sys_mutex_t lock_tcpip_core; -/** Lock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */ -#define LOCK_TCPIP_CORE() sys_mutex_lock(&lock_tcpip_core) -/** Unlock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */ -#define UNLOCK_TCPIP_CORE() sys_mutex_unlock(&lock_tcpip_core) -#else /* LWIP_TCPIP_CORE_LOCKING */ -#define LOCK_TCPIP_CORE() -#define UNLOCK_TCPIP_CORE() -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -struct pbuf; -struct netif; - -/** Function prototype for the init_done function passed to tcpip_init */ -typedef void (*tcpip_init_done_fn)(void *arg); -/** Function prototype for functions passed to tcpip_callback() */ -typedef void (*tcpip_callback_fn)(void *ctx); - -/* Forward declarations */ -struct tcpip_callback_msg; - -void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg); - -err_t tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn); -err_t tcpip_input(struct pbuf *p, struct netif *inp); - -err_t tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block); -/** - * @ingroup lwip_os - * @see tcpip_callback_with_block - */ -#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) - -struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx); -void tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg); -err_t tcpip_trycallback(struct tcpip_callback_msg* msg); - -/* free pbufs or heap memory from another context without blocking */ -err_t pbuf_free_callback(struct pbuf *p); -err_t mem_free_callback(void *m); - -#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS -err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); -err_t tcpip_untimeout(sys_timeout_handler h, void *arg); -#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ - -#ifdef __cplusplus -} -#endif - -#endif /* !NO_SYS */ - -#endif /* LWIP_HDR_TCPIP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/timeouts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/timeouts.h deleted file mode 100644 index c9b93aa02ace45820f7542f406fc16cf05fd5021..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/timeouts.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * @file - * Timer implementations - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_TIMEOUTS_H -#define LWIP_HDR_TIMEOUTS_H - -#include "lwip/opt.h" -#include "lwip/err.h" -#if !NO_SYS -#include "lwip/sys.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef LWIP_DEBUG_TIMERNAMES -#ifdef LWIP_DEBUG -#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG -#else /* LWIP_DEBUG */ -#define LWIP_DEBUG_TIMERNAMES 0 -#endif /* LWIP_DEBUG*/ -#endif - -/** Function prototype for a stack-internal timer function that has to be - * called at a defined interval */ -typedef void (* lwip_cyclic_timer_handler)(void); - -/** This struct contains information about a stack-internal timer function - that has to be called at a defined interval */ -struct lwip_cyclic_timer { - u32_t interval_ms; - lwip_cyclic_timer_handler handler; -#if LWIP_DEBUG_TIMERNAMES - const char* handler_name; -#endif /* LWIP_DEBUG_TIMERNAMES */ -}; - -/** This array contains all stack-internal cyclic timers. To get the number of - * timers, use LWIP_ARRAYSIZE() */ -extern const struct lwip_cyclic_timer lwip_cyclic_timers[]; - -#if LWIP_TIMERS - -/** Function prototype for a timeout callback function. Register such a function - * using sys_timeout(). - * - * @param arg Additional argument to pass to the function - set up by sys_timeout() - */ -typedef void (* sys_timeout_handler)(void *arg); - -struct sys_timeo { - struct sys_timeo *next; - u32_t time; - sys_timeout_handler h; - void *arg; -#if LWIP_DEBUG_TIMERNAMES - const char* handler_name; -#endif /* LWIP_DEBUG_TIMERNAMES */ -}; - -void sys_timeouts_init(void); - -#if LWIP_DEBUG_TIMERNAMES -void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name); -#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler) -#else /* LWIP_DEBUG_TIMERNAMES */ -void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg); -#endif /* LWIP_DEBUG_TIMERNAMES */ - -void sys_untimeout(sys_timeout_handler handler, void *arg); -void sys_restart_timeouts(void); -#if NO_SYS -void sys_check_timeouts(void); -u32_t sys_timeouts_sleeptime(void); -#else /* NO_SYS */ -void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg); -#endif /* NO_SYS */ - - -#endif /* LWIP_TIMERS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_TIMEOUTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/udp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/udp.h deleted file mode 100644 index b929907394d77694935844a70ab02c343eb94362..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/lwip/udp.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * @file - * UDP API (to be used from TCPIP thread)\n - * See also @ref udp_raw - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_UDP_H -#define LWIP_HDR_UDP_H - -#include "lwip/opt.h" - -#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/ip_addr.h" -#include "lwip/ip.h" -#include "lwip/ip6_addr.h" -#include "lwip/prot/udp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UDP_FLAGS_NOCHKSUM 0x01U -#define UDP_FLAGS_UDPLITE 0x02U -#define UDP_FLAGS_CONNECTED 0x04U -#define UDP_FLAGS_MULTICAST_LOOP 0x08U - -struct udp_pcb; - -/** Function prototype for udp pcb receive callback functions - * addr and port are in same byte order as in the pcb - * The callback is responsible for freeing the pbuf - * if it's not used any more. - * - * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf - * can make 'addr' invalid, too. - * - * @param arg user supplied argument (udp_pcb.recv_arg) - * @param pcb the udp_pcb which received data - * @param p the packet buffer that was received - * @param addr the remote IP address from which the packet was received - * @param port the remote port from which the packet was received - */ -typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *addr, u16_t port); - -/** the UDP protocol control block */ -struct udp_pcb { -/** Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - - struct udp_pcb *next; - - u8_t flags; - /** ports are in host byte order */ - u16_t local_port, remote_port; - -#if LWIP_MULTICAST_TX_OPTIONS - /** outgoing network interface for multicast packets */ - ip_addr_t multicast_ip; - /** TTL for outgoing multicast packets */ - u8_t mcast_ttl; -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - -#if LWIP_UDPLITE - /** used for UDP_LITE only */ - u16_t chksum_len_rx, chksum_len_tx; -#endif /* LWIP_UDPLITE */ - - /** receive callback function */ - udp_recv_fn recv; - /** user-supplied argument for the recv callback */ - void *recv_arg; -}; -/* udp_pcbs export for external reference (e.g. SNMP agent) */ -extern struct udp_pcb *udp_pcbs; - -/* The following functions is the application layer interface to the - UDP code. */ -struct udp_pcb * udp_new (void); -struct udp_pcb * udp_new_ip_type(u8_t type); -void udp_remove (struct udp_pcb *pcb); -err_t udp_bind (struct udp_pcb *pcb, const ip_addr_t *ipaddr, - u16_t port); -err_t udp_connect (struct udp_pcb *pcb, const ip_addr_t *ipaddr, - u16_t port); -void udp_disconnect (struct udp_pcb *pcb); -void udp_recv (struct udp_pcb *pcb, udp_recv_fn recv, - void *recv_arg); -err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, - struct netif *netif); -err_t udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, - struct netif *netif, const ip_addr_t *src_ip); -err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port); -err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); - -#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP -err_t udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, - struct netif *netif, u8_t have_chksum, - u16_t chksum); -err_t udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, - u8_t have_chksum, u16_t chksum); -err_t udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, - u8_t have_chksum, u16_t chksum); -err_t udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p, - const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, - u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip); -#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ - -#define udp_flags(pcb) ((pcb)->flags) -#define udp_setflags(pcb, f) ((pcb)->flags = (f)) - -/* The following functions are the lower layer interface to UDP. */ -void udp_input (struct pbuf *p, struct netif *inp); - -void udp_init (void); - -/* for compatibility with older implementation */ -#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6) - -#if LWIP_MULTICAST_TX_OPTIONS -#define udp_set_multicast_netif_addr(pcb, ip4addr) ip_addr_copy_from_ip4((pcb)->multicast_ip, *(ip4addr)) -#define udp_get_multicast_netif_addr(pcb) ip_2_ip4(&(pcb)->multicast_ip) -#define udp_set_multicast_ttl(pcb, value) do { (pcb)->mcast_ttl = value; } while(0) -#define udp_get_multicast_ttl(pcb) ((pcb)->mcast_ttl) -#endif /* LWIP_MULTICAST_TX_OPTIONS */ - -#if UDP_DEBUG -void udp_debug_print(struct udp_hdr *udphdr); -#else -#define udp_debug_print(udphdr) -#endif - -void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_UDP */ - -#endif /* LWIP_HDR_UDP_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/etharp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/etharp.h deleted file mode 100644 index b536fd280faca7f48627d2df651326bc41646c48..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/etharp.h +++ /dev/null @@ -1,3 +0,0 @@ -/* ARP has been moved to core/ipv4, provide this #include for compatibility only */ -#include "lwip/etharp.h" -#include "netif/ethernet.h" diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/ethernet.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/ethernet.h deleted file mode 100644 index 49649cbf8b2a712b547ab40e736f3c6bb42f74b8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/ethernet.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * @file - * Ethernet input function - handles INCOMING ethernet level traffic - * To be used in most low-level netif implementations - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef LWIP_HDR_NETIF_ETHERNET_H -#define LWIP_HDR_NETIF_ETHERNET_H - -#include "lwip/opt.h" - -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/prot/ethernet.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_ARP || LWIP_ETHERNET - -/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type) - * to a filter function that returns the correct netif when using multiple - * netifs on one hardware interface where the netif's low-level receive - * routine cannot decide for the correct netif (e.g. when mapping multiple - * IP addresses to one hardware interface). - */ -#ifndef LWIP_ARP_FILTER_NETIF -#define LWIP_ARP_FILTER_NETIF 0 -#endif - -err_t ethernet_input(struct pbuf *p, struct netif *netif); -err_t ethernet_output(struct netif* netif, struct pbuf* p, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type); - -extern const struct eth_addr ethbroadcast, ethzero; - -#endif /* LWIP_ARP || LWIP_ETHERNET */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_NETIF_ETHERNET_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6.h deleted file mode 100644 index 4174644bb369a760aa762e5164853b9e99085f73..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @file - * - * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. - */ - -/* - * Copyright (c) 2015 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_LOWPAN6_H -#define LWIP_HDR_LOWPAN6_H - -#include "netif/lowpan6_opts.h" - -#if LWIP_IPV6 && LWIP_6LOWPAN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/ip.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** 1 second period */ -#define LOWPAN6_TMR_INTERVAL 1000 - -void lowpan6_tmr(void); - -err_t lowpan6_set_context(u8_t index, const ip6_addr_t * context); -err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low); - -#if LWIP_IPV4 -err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); -#endif /* LWIP_IPV4 */ -err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr); -err_t lowpan6_input(struct pbuf * p, struct netif *netif); -err_t lowpan6_if_init(struct netif *netif); - -/* pan_id in network byte order. */ -err_t lowpan6_set_pan_id(u16_t pan_id); - -#if !NO_SYS -err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp); -#endif /* !NO_SYS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IPV6 && LWIP_6LOWPAN */ - -#endif /* LWIP_HDR_LOWPAN6_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6_opts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6_opts.h deleted file mode 100644 index fb93ea05de609809ae2e164e0b03c7996f09074e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/lowpan6_opts.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * 6LowPAN options list - */ - -/* - * Copyright (c) 2015 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -#ifndef LWIP_HDR_LOWPAN6_OPTS_H -#define LWIP_HDR_LOWPAN6_OPTS_H - -#include "lwip/opt.h" - -#ifndef LWIP_6LOWPAN -#define LWIP_6LOWPAN 0 -#endif - -#ifndef LWIP_6LOWPAN_NUM_CONTEXTS -#define LWIP_6LOWPAN_NUM_CONTEXTS 10 -#endif - -#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS -#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1 -#endif - -#ifndef LWIP_6LOWPAN_IPHC -#define LWIP_6LOWPAN_IPHC 1 -#endif - -#ifndef LWIP_6LOWPAN_HW_CRC -#define LWIP_6LOWPAN_HW_CRC 1 -#endif - -#ifndef LOWPAN6_DEBUG -#define LOWPAN6_DEBUG LWIP_DBG_OFF -#endif - -#endif /* LWIP_HDR_LOWPAN6_OPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/slipif.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/slipif.h deleted file mode 100644 index 65ba31f835b577c934eb495947a77f3d86edaa84..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/netif/slipif.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * @file - * - * SLIP netif API - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef LWIP_HDR_NETIF_SLIPIF_H -#define LWIP_HDR_NETIF_SLIPIF_H - -#include "lwip/opt.h" -#include "lwip/netif.h" - -/** Set this to 1 to start a thread that blocks reading on the serial line - * (using sio_read()). - */ -#ifndef SLIP_USE_RX_THREAD -#define SLIP_USE_RX_THREAD !NO_SYS -#endif - -/** Set this to 1 to enable functions to pass in RX bytes from ISR context. - * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled - * packets on a queue, which is fed into lwIP from slipif_poll(). - * If disabled, slipif_poll() polls the serial line (using sio_tryread()). - */ -#ifndef SLIP_RX_FROM_ISR -#define SLIP_RX_FROM_ISR 0 -#endif - -/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets - * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available. - * If disabled, packets will be dropped if more than one packet is received. - */ -#ifndef SLIP_RX_QUEUE -#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -err_t slipif_init(struct netif * netif); -void slipif_poll(struct netif *netif); -#if SLIP_RX_FROM_ISR -void slipif_process_rxqueue(struct netif *netif); -void slipif_received_byte(struct netif *netif, u8_t data); -void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len); -#endif /* SLIP_RX_FROM_ISR */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_HDR_NETIF_SLIPIF_H */ - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/errno.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/errno.h deleted file mode 100644 index 5917c75e24a8e01c9666c2714475dec09d27df0c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/errno.h +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file - * This file is a posix wrapper for lwip/errno.h. - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/errno.h" diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/netdb.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/netdb.h deleted file mode 100644 index 12d4c7f566c77fc4ded1aaf30a67072cd3f7d81c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/netdb.h +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file - * This file is a posix wrapper for lwip/netdb.h. - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/netdb.h" diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/sys/socket.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/sys/socket.h deleted file mode 100644 index 0ed9baf3d9f2e514fdfc043a3c7cb85fa0e2f3d6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/include/posix/sys/socket.h +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file - * This file is a posix wrapper for lwip/sockets.h. - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/sockets.h" diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/FILES b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/FILES deleted file mode 100644 index a3ff431d4252eedcb34bbc838f4b1250042b4577..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/FILES +++ /dev/null @@ -1,24 +0,0 @@ -This directory contains generic network interface device drivers that -do not contain any hardware or architecture specific code. The files -are: - -ethernet.c - Shared code for Ethernet based interfaces. - -ethernetif.c - An example of how an Ethernet device driver could look. This - file can be used as a "skeleton" for developing new Ethernet - network device drivers. It uses the etharp.c ARP code. - -lowpan6.c - A 6LoWPAN implementation as a netif. - -slipif.c - A generic implementation of the SLIP (Serial Line IP) - protocol. It requires a sio (serial I/O) module to work. - -ppp/ Point-to-Point Protocol stack - The lwIP PPP support is based from pppd (http://ppp.samba.org) with - huge changes to match code size and memory requirements for embedded - devices. Please read /doc/ppp.txt and ppp/PPPD_FOLLOWUP for a detailed - explanation. diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernet.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernet.c deleted file mode 100644 index d8319a97bcd3cbea28305b073c9ed5a12f8812c8..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernet.c +++ /dev/null @@ -1,309 +0,0 @@ -/** - * @file - * Ethernet common functions - * - * @defgroup ethernet Ethernet - * @ingroup callbackstyle_api - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" - -#if LWIP_ARP || LWIP_ETHERNET - -#include "netif/ethernet.h" -#include "lwip/def.h" -#include "lwip/stats.h" -#include "lwip/etharp.h" -#include "lwip/ip.h" -#include "lwip/snmp.h" - -#include - -#ifdef LWIP_HOOK_FILENAME -#include LWIP_HOOK_FILENAME -#endif - -const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; -const struct eth_addr ethzero = {{0,0,0,0,0,0}}; - -/** - * @ingroup lwip_nosys - * Process received ethernet frames. Using this function instead of directly - * calling ip_input and passing ARP frames through etharp in ethernetif_input, - * the ARP cache is protected from concurrent access.\n - * Don't call directly, pass to netif_add() and call netif->input(). - * - * @param p the received packet, p->payload pointing to the ethernet header - * @param netif the network interface on which the packet was received - * - * @see LWIP_HOOK_UNKNOWN_ETH_PROTOCOL - * @see ETHARP_SUPPORT_VLAN - * @see LWIP_HOOK_VLAN_CHECK - */ -err_t -ethernet_input(struct pbuf *p, struct netif *netif) -{ - struct eth_hdr* ethhdr; - u16_t type; -#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6 - s16_t ip_hdr_offset = SIZEOF_ETH_HDR; -#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */ - - if (p->len <= SIZEOF_ETH_HDR) { - /* a packet with only an ethernet header (or less) is not valid for us */ - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - MIB2_STATS_NETIF_INC(netif, ifinerrors); - goto free_and_return; - } - - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = (struct eth_hdr *)p->payload; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, - ("ethernet_input: dest:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", src:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", type:%"X16_F"\n", - (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2], - (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5], - (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2], - (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5], - lwip_htons(ethhdr->type))); - - type = ethhdr->type; -#if ETHARP_SUPPORT_VLAN - if (type == PP_HTONS(ETHTYPE_VLAN)) { - struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR); - if (p->len <= SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) { - /* a packet with only an ethernet/vlan header (or less) is not valid for us */ - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - MIB2_STATS_NETIF_INC(netif, ifinerrors); - goto free_and_return; - } -#if defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) /* if not, allow all VLANs */ -#ifdef LWIP_HOOK_VLAN_CHECK - if (!LWIP_HOOK_VLAN_CHECK(netif, ethhdr, vlan)) { -#elif defined(ETHARP_VLAN_CHECK_FN) - if (!ETHARP_VLAN_CHECK_FN(ethhdr, vlan)) { -#elif defined(ETHARP_VLAN_CHECK) - if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) { -#endif - /* silently ignore this packet: not for our VLAN */ - pbuf_free(p); - return ERR_OK; - } -#endif /* defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) */ - type = vlan->tpid; - ip_hdr_offset = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR; - } -#endif /* ETHARP_SUPPORT_VLAN */ - -#if LWIP_ARP_FILTER_NETIF - netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type)); -#endif /* LWIP_ARP_FILTER_NETIF*/ - - if (ethhdr->dest.addr[0] & 1) { - /* this might be a multicast or broadcast packet */ - if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) { -#if LWIP_IPV4 - if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && - (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) { - /* mark the pbuf as link-layer multicast */ - p->flags |= PBUF_FLAG_LLMCAST; - } -#endif /* LWIP_IPV4 */ - } -#if LWIP_IPV6 - else if ((ethhdr->dest.addr[0] == LL_IP6_MULTICAST_ADDR_0) && - (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) { - /* mark the pbuf as link-layer multicast */ - p->flags |= PBUF_FLAG_LLMCAST; - } -#endif /* LWIP_IPV6 */ - else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) { - /* mark the pbuf as link-layer broadcast */ - p->flags |= PBUF_FLAG_LLBCAST; - } - } - - switch (type) { -#if LWIP_IPV4 && LWIP_ARP - /* IP packet? */ - case PP_HTONS(ETHTYPE_IP): - if (!(netif->flags & NETIF_FLAG_ETHARP)) { - goto free_and_return; - } - /* skip Ethernet header */ - if ((p->len < ip_hdr_offset) || pbuf_header(p, (s16_t)-ip_hdr_offset)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("ethernet_input: IPv4 packet dropped, too short (%"S16_F"/%"S16_F")\n", - p->tot_len, ip_hdr_offset)); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet")); - goto free_and_return; - } else { - /* pass to IP layer */ - ip4_input(p, netif); - } - break; - - case PP_HTONS(ETHTYPE_ARP): - if (!(netif->flags & NETIF_FLAG_ETHARP)) { - goto free_and_return; - } - /* skip Ethernet header */ - if ((p->len < ip_hdr_offset) || pbuf_header(p, (s16_t)-ip_hdr_offset)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("ethernet_input: ARP response packet dropped, too short (%"S16_F"/%"S16_F")\n", - p->tot_len, ip_hdr_offset)); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet")); - ETHARP_STATS_INC(etharp.lenerr); - ETHARP_STATS_INC(etharp.drop); - goto free_and_return; - } else { - /* pass p to ARP module */ - etharp_input(p, netif); - } - break; -#endif /* LWIP_IPV4 && LWIP_ARP */ -#if PPPOE_SUPPORT - case PP_HTONS(ETHTYPE_PPPOEDISC): /* PPP Over Ethernet Discovery Stage */ - pppoe_disc_input(netif, p); - break; - - case PP_HTONS(ETHTYPE_PPPOE): /* PPP Over Ethernet Session Stage */ - pppoe_data_input(netif, p); - break; -#endif /* PPPOE_SUPPORT */ - -#if LWIP_IPV6 - case PP_HTONS(ETHTYPE_IPV6): /* IPv6 */ - /* skip Ethernet header */ - if ((p->len < ip_hdr_offset) || pbuf_header(p, (s16_t)-ip_hdr_offset)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("ethernet_input: IPv6 packet dropped, too short (%"S16_F"/%"S16_F")\n", - p->tot_len, ip_hdr_offset)); - goto free_and_return; - } else { - /* pass to IPv6 layer */ - ip6_input(p, netif); - } - break; -#endif /* LWIP_IPV6 */ - - default: -#ifdef LWIP_HOOK_UNKNOWN_ETH_PROTOCOL - if(LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(p, netif) == ERR_OK) { - break; - } -#endif - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - MIB2_STATS_NETIF_INC(netif, ifinunknownprotos); - goto free_and_return; - } - - /* This means the pbuf is freed or consumed, - so the caller doesn't have to free it again */ - return ERR_OK; - -free_and_return: - pbuf_free(p); - return ERR_OK; -} - -/** - * @ingroup ethernet - * Send an ethernet packet on the network using netif->linkoutput(). - * The ethernet header is filled in before sending. - * - * @see LWIP_HOOK_VLAN_SET - * - * @param netif the lwIP network interface on which to send the packet - * @param p the packet to send. pbuf layer must be @ref PBUF_LINK. - * @param src the source MAC address to be copied into the ethernet header - * @param dst the destination MAC address to be copied into the ethernet header - * @param eth_type ethernet type (@ref eth_type) - * @return ERR_OK if the packet was sent, any other err_t on failure - */ -err_t -ethernet_output(struct netif* netif, struct pbuf* p, - const struct eth_addr* src, const struct eth_addr* dst, - u16_t eth_type) -{ - struct eth_hdr* ethhdr; - u16_t eth_type_be = lwip_htons(eth_type); - -#if ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) - s32_t vlan_prio_vid = LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type); - if (vlan_prio_vid >= 0) { - struct eth_vlan_hdr* vlanhdr; - - LWIP_ASSERT("prio_vid must be <= 0xFFFF", vlan_prio_vid <= 0xFFFF); - - if (pbuf_header(p, SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) != 0) { - goto pbuf_header_failed; - } - vlanhdr = (struct eth_vlan_hdr*)(((u8_t*)p->payload) + SIZEOF_ETH_HDR); - vlanhdr->tpid = eth_type_be; - vlanhdr->prio_vid = lwip_htons((u16_t)vlan_prio_vid); - - eth_type_be = PP_HTONS(ETHTYPE_VLAN); - } else -#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */ - { - if (pbuf_header(p, SIZEOF_ETH_HDR) != 0) { - goto pbuf_header_failed; - } - } - - ethhdr = (struct eth_hdr*)p->payload; - ethhdr->type = eth_type_be; - ETHADDR32_COPY(ðhdr->dest, dst); - ETHADDR16_COPY(ðhdr->src, src); - - LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!", - (netif->hwaddr_len == ETH_HWADDR_LEN)); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, - ("ethernet_output: sending packet %p\n", (void *)p)); - - /* send the packet */ - return netif->linkoutput(netif, p); - -pbuf_header_failed: - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("ethernet_output: could not allocate room for header.\n")); - LINK_STATS_INC(link.lenerr); - return ERR_BUF; -} - -#endif /* LWIP_ARP || LWIP_ETHERNET */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernetif.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernetif.c deleted file mode 100644 index a439bc3ff22883d5200120e6e7e4d7109839679e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/ethernetif.c +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * Ethernet Interface Skeleton - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. - */ - -#include "lwip/opt.h" - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/lowpan6.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/lowpan6.c deleted file mode 100644 index 9a84cbccc785b53257e283b51155184c5d8d9105..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/lowpan6.c +++ /dev/null @@ -1,1193 +0,0 @@ -/** - * @file - * - * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. - */ - -/* - * Copyright (c) 2015 Inico Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Ivan Delamer - * - * - * Please coordinate changes and requests with Ivan Delamer - * - */ - -/** - * @defgroup sixlowpan 6LowPAN netif - * @ingroup addons - * 6LowPAN netif implementation - */ - -#include "netif/lowpan6.h" - -#if LWIP_IPV6 && LWIP_6LOWPAN - -#include "lwip/ip.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/nd6.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/tcpip.h" -#include "lwip/snmp.h" - -#include - -struct ieee_802154_addr { - u8_t addr_len; - u8_t addr[8]; -}; - -/** This is a helper struct. - */ -struct lowpan6_reass_helper { - struct pbuf *pbuf; - struct lowpan6_reass_helper *next_packet; - u8_t timer; - struct ieee_802154_addr sender_addr; - u16_t datagram_size; - u16_t datagram_tag; -}; - -static struct lowpan6_reass_helper * reass_list; - -#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 -static ip6_addr_t lowpan6_context[LWIP_6LOWPAN_NUM_CONTEXTS]; -#endif - -static u16_t ieee_802154_pan_id; - -static const struct ieee_802154_addr ieee_802154_broadcast = {2, {0xff, 0xff}}; - -#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS -static struct ieee_802154_addr short_mac_addr = {2, {0,0}}; -#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ - -static err_t dequeue_datagram(struct lowpan6_reass_helper *lrh); - -/** - * Periodic timer for 6LowPAN functions: - * - * - Remove incomplete/old packets - */ -void -lowpan6_tmr(void) -{ - struct lowpan6_reass_helper *lrh, *lrh_temp; - - lrh = reass_list; - while (lrh != NULL) { - lrh_temp = lrh->next_packet; - if ((--lrh->timer) == 0) { - dequeue_datagram(lrh); - pbuf_free(lrh->pbuf); - mem_free(lrh); - } - lrh = lrh_temp; - } -} - -/** - * Removes a datagram from the reassembly queue. - **/ -static err_t -dequeue_datagram(struct lowpan6_reass_helper *lrh) -{ - struct lowpan6_reass_helper *lrh_temp; - - if (reass_list == lrh) { - reass_list = reass_list->next_packet; - } else { - lrh_temp = reass_list; - while (lrh_temp != NULL) { - if (lrh_temp->next_packet == lrh) { - lrh_temp->next_packet = lrh->next_packet; - break; - } - lrh_temp = lrh_temp->next_packet; - } - } - - return ERR_OK; -} - -static s8_t -lowpan6_context_lookup(const ip6_addr_t *ip6addr) -{ - s8_t i; - - for (i = 0; i < LWIP_6LOWPAN_NUM_CONTEXTS; i++) { - if (ip6_addr_netcmp(&lowpan6_context[i], ip6addr)) { - return i; - } - } - - return -1; -} - -/* Determine compression mode for unicast address. */ -static s8_t -lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct ieee_802154_addr *mac_addr) -{ - if (mac_addr->addr_len == 2) { - if ((ip6addr->addr[2] == (u32_t)PP_HTONL(0x000000ff)) && - ((ip6addr->addr[3] & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000))) { - if ((ip6addr->addr[3] & PP_HTONL(0x0000ffff)) == lwip_ntohl((mac_addr->addr[0] << 8) | mac_addr->addr[1])) { - return 3; - } - } - } else if (mac_addr->addr_len == 8) { - if ((ip6addr->addr[2] == lwip_ntohl(((mac_addr->addr[0] ^ 2) << 24) | (mac_addr->addr[1] << 16) | mac_addr->addr[2] << 8 | mac_addr->addr[3])) && - (ip6addr->addr[3] == lwip_ntohl((mac_addr->addr[4] << 24) | (mac_addr->addr[5] << 16) | mac_addr->addr[6] << 8 | mac_addr->addr[7]))) { - return 3; - } - } - - if ((ip6addr->addr[2] == PP_HTONL(0x000000ffUL)) && - ((ip6addr->addr[3] & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000UL))) { - return 2; - } - - return 1; -} - -/* Determine compression mode for multicast address. */ -static s8_t -lowpan6_get_address_mode_mc(const ip6_addr_t *ip6addr) -{ - if ((ip6addr->addr[0] == PP_HTONL(0xff020000)) && - (ip6addr->addr[1] == 0) && - (ip6addr->addr[2] == 0) && - ((ip6addr->addr[3] & PP_HTONL(0xffffff00)) == 0)) { - return 3; - } else if (((ip6addr->addr[0] & PP_HTONL(0xff00ffff)) == PP_HTONL(0xff000000)) && - (ip6addr->addr[1] == 0)) { - if ((ip6addr->addr[2] == 0) && - ((ip6addr->addr[3] & PP_HTONL(0xff000000)) == 0)) { - return 2; - } else if ((ip6addr->addr[2] & PP_HTONL(0xffffff00)) == 0) { - return 1; - } - } - - return 0; -} - -/* - * Encapsulates data into IEEE 802.15.4 frames. - * Fragments an IPv6 datagram into 6LowPAN units, which fit into IEEE 802.15.4 frames. - * If configured, will compress IPv6 and or UDP headers. - * */ -static err_t -lowpan6_frag(struct netif *netif, struct pbuf *p, const struct ieee_802154_addr *src, const struct ieee_802154_addr *dst) -{ - struct pbuf * p_frag; - u16_t frag_len, remaining_len; - u8_t * buffer; - u8_t ieee_header_len; - u8_t lowpan6_header_len; - s8_t i; - static u8_t frame_seq_num; - static u16_t datagram_tag; - u16_t datagram_offset; - err_t err = ERR_IF; - - /* We'll use a dedicated pbuf for building 6LowPAN fragments. */ - p_frag = pbuf_alloc(PBUF_RAW, 127, PBUF_RAM); - if (p_frag == NULL) { - MIB2_STATS_NETIF_INC(netif, ifoutdiscards); - return ERR_MEM; - } - - /* Write IEEE 802.15.4 header. */ - buffer = (u8_t*)p_frag->payload; - ieee_header_len = 0; - if (dst == &ieee_802154_broadcast) { - buffer[ieee_header_len++] = 0x01; /* data packet, no ack required. */ - } else { - buffer[ieee_header_len++] = 0x21; /* data packet, ack required. */ - } - buffer[ieee_header_len] = (0x00 << 4); /* 2003 frame version */ - buffer[ieee_header_len] |= (dst->addr_len == 2) ? (0x02 << 2) : (0x03 << 2); /* destination addressing mode */ - buffer[ieee_header_len] |= (src->addr_len == 2) ? (0x02 << 6) : (0x03 << 6); /* source addressing mode */ - ieee_header_len++; - buffer[ieee_header_len++] = frame_seq_num++; - - buffer[ieee_header_len++] = ieee_802154_pan_id & 0xff; /* pan id */ - buffer[ieee_header_len++] = (ieee_802154_pan_id >> 8) & 0xff; /* pan id */ - i = dst->addr_len; - while (i-- > 0) { - buffer[ieee_header_len++] = dst->addr[i]; - } - - buffer[ieee_header_len++] = ieee_802154_pan_id & 0xff; /* pan id */ - buffer[ieee_header_len++] = (ieee_802154_pan_id >> 8) & 0xff; /* pan id */ - i = src->addr_len; - while (i-- > 0) { - buffer[ieee_header_len++] = src->addr[i]; - } - -#if LWIP_6LOWPAN_IPHC - /* Perform 6LowPAN IPv6 header compression according to RFC 6282 */ - { - struct ip6_hdr *ip6hdr; - - /* Point to ip6 header and align copies of src/dest addresses. */ - ip6hdr = (struct ip6_hdr *)p->payload; - ip_addr_copy_from_ip6(ip_data.current_iphdr_dest, ip6hdr->dest); - ip_addr_copy_from_ip6(ip_data.current_iphdr_src, ip6hdr->src); - - /* Basic length of 6LowPAN header, set dispatch and clear fields. */ - lowpan6_header_len = 2; - buffer[ieee_header_len] = 0x60; - buffer[ieee_header_len + 1] = 0; - - /* Determine whether there will be a Context Identifier Extension byte or not. - * If so, set it already. */ -#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 - buffer[ieee_header_len + 2] = 0; - - i = lowpan6_context_lookup(ip_2_ip6(&ip_data.current_iphdr_src)); - if (i >= 0) { - /* Stateful source address compression. */ - buffer[ieee_header_len + 1] |= 0x40; - buffer[ieee_header_len + 2] |= (i & 0x0f) << 4; - } - - i = lowpan6_context_lookup(ip_2_ip6(&ip_data.current_iphdr_dest)); - if (i >= 0) { - /* Stateful destination address compression. */ - buffer[ieee_header_len + 1] |= 0x04; - buffer[ieee_header_len + 2] |= i & 0x0f; - } - - if (buffer[ieee_header_len + 2] != 0x00) { - /* Context identifier extension byte is appended. */ - buffer[ieee_header_len + 1] |= 0x80; - lowpan6_header_len++; - } -#endif /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */ - - /* Determine TF field: Traffic Class, Flow Label */ - if (IP6H_FL(ip6hdr) == 0) { - /* Flow label is elided. */ - buffer[ieee_header_len] |= 0x10; - if (IP6H_TC(ip6hdr) == 0) { - /* Traffic class (ECN+DSCP) elided too. */ - buffer[ieee_header_len] |= 0x08; - } else { - /* Traffic class (ECN+DSCP) appended. */ - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_TC(ip6hdr); - } - } else { - if (((IP6H_TC(ip6hdr) & 0x3f) == 0)) { - /* DSCP portion of Traffic Class is elided, ECN and FL are appended (3 bytes) */ - buffer[ieee_header_len] |= 0x08; - - buffer[ieee_header_len + lowpan6_header_len] = IP6H_TC(ip6hdr) & 0xc0; - buffer[ieee_header_len + lowpan6_header_len++] |= (IP6H_FL(ip6hdr) >> 16) & 0x0f; - buffer[ieee_header_len + lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff; - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff; - } else { - /* Traffic class and flow label are appended (4 bytes) */ - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_TC(ip6hdr); - buffer[ieee_header_len + lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 16) & 0x0f; - buffer[ieee_header_len + lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff; - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff; - } - } - - /* Compress NH? - * Only if UDP for now. @todo support other NH compression. */ - if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) { - buffer[ieee_header_len] |= 0x04; - } else { - /* append nexth. */ - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_NEXTH(ip6hdr); - } - - /* Compress hop limit? */ - if (IP6H_HOPLIM(ip6hdr) == 255) { - buffer[ieee_header_len] |= 0x03; - } else if (IP6H_HOPLIM(ip6hdr) == 64) { - buffer[ieee_header_len] |= 0x02; - } else if (IP6H_HOPLIM(ip6hdr) == 1) { - buffer[ieee_header_len] |= 0x01; - } else { - /* append hop limit */ - buffer[ieee_header_len + lowpan6_header_len++] = IP6H_HOPLIM(ip6hdr); - } - - /* Compress source address */ - if (((buffer[ieee_header_len + 1] & 0x40) != 0) || - (ip6_addr_islinklocal(ip_2_ip6(&ip_data.current_iphdr_src)))) { - /* Context-based or link-local source address compression. */ - i = lowpan6_get_address_mode(ip_2_ip6(&ip_data.current_iphdr_src), src); - buffer[ieee_header_len + 1] |= (i & 0x03) << 4; - if (i == 1) { - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 16, 8); - lowpan6_header_len += 8; - } else if (i == 2) { - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 22, 2); - lowpan6_header_len += 2; - } - } else if (ip6_addr_isany(ip_2_ip6(&ip_data.current_iphdr_src))) { - /* Special case: mark SAC and leave SAM=0 */ - buffer[ieee_header_len + 1] |= 0x40; - } else { - /* Append full address. */ - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 8, 16); - lowpan6_header_len += 16; - } - - /* Compress destination address */ - if (ip6_addr_ismulticast(ip_2_ip6(&ip_data.current_iphdr_dest))) { - /* @todo support stateful multicast address compression */ - - buffer[ieee_header_len + 1] |= 0x08; - - i = lowpan6_get_address_mode_mc(ip_2_ip6(&ip_data.current_iphdr_dest)); - buffer[ieee_header_len + 1] |= i & 0x03; - if (i == 0) { - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 24, 16); - lowpan6_header_len += 16; - } else if (i == 1) { - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[25]; - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 35, 5); - lowpan6_header_len += 5; - } else if (i == 2) { - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[25]; - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 37, 3); - lowpan6_header_len += 3; - } else if (i == 3) { - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[39]; - } - } else if (((buffer[ieee_header_len + 1] & 0x04) != 0) || - (ip6_addr_islinklocal(ip_2_ip6(&ip_data.current_iphdr_dest)))) { - /* Context-based or link-local destination address compression. */ - i = lowpan6_get_address_mode(ip_2_ip6(&ip_data.current_iphdr_dest), dst); - buffer[ieee_header_len + 1] |= i & 0x03; - if (i == 1) { - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 32, 8); - lowpan6_header_len += 8; - } else if (i == 2) { - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 38, 2); - lowpan6_header_len += 2; - } - } else { - /* Append full address. */ - MEMCPY(buffer + ieee_header_len + lowpan6_header_len, (u8_t*)p->payload + 24, 16); - lowpan6_header_len += 16; - } - - /* Move to payload. */ - pbuf_header(p, -IP6_HLEN); - - /* Compress UDP header? */ - if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) { - /* @todo support optional checksum compression */ - - buffer[ieee_header_len + lowpan6_header_len] = 0xf0; - - /* determine port compression mode. */ - if ((((u8_t *)p->payload)[0] == 0xf0) && ((((u8_t *)p->payload)[1] & 0xf0) == 0xb0) && - (((u8_t *)p->payload)[2] == 0xf0) && ((((u8_t *)p->payload)[3] & 0xf0) == 0xb0)) { - /* Compress source and dest ports. */ - buffer[ieee_header_len + lowpan6_header_len++] |= 0x03; - buffer[ieee_header_len + lowpan6_header_len++] = ((((u8_t *)p->payload)[1] & 0x0f) << 4) | (((u8_t *)p->payload)[3] & 0x0f); - } else if (((u8_t *)p->payload)[0] == 0xf0) { - /* Compress source port. */ - buffer[ieee_header_len + lowpan6_header_len++] |= 0x02; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[1]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[2]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[3]; - } else if (((u8_t *)p->payload)[2] == 0xf0) { - /* Compress dest port. */ - buffer[ieee_header_len + lowpan6_header_len++] |= 0x01; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[0]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[1]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[3]; - } else { - /* append full ports. */ - lowpan6_header_len++; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[0]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[1]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[2]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[3]; - } - - /* elide length and copy checksum */ - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[6]; - buffer[ieee_header_len + lowpan6_header_len++] = ((u8_t *)p->payload)[7]; - - pbuf_header(p, -UDP_HLEN); - } - } - -#else /* LWIP_6LOWPAN_HC */ - /* Send uncompressed IPv6 header with appropriate dispatch byte. */ - lowpan6_header_len = 1; - buffer[ieee_header_len] = 0x41; /* IPv6 dispatch */ -#endif /* LWIP_6LOWPAN_HC */ - - /* Calculate remaining packet length */ - remaining_len = p->tot_len; - - if (remaining_len > 0x7FF) { - MIB2_STATS_NETIF_INC(netif, ifoutdiscards); - /* datagram_size must fit into 11 bit */ - pbuf_free(p_frag); - return ERR_VAL; - } - - /* Fragment, or 1 packet? */ - if (remaining_len > (127 - ieee_header_len - lowpan6_header_len - 3)) { /* 127 - header - 1 byte dispatch - 2 bytes CRC */ - /* We must move the 6LowPAN header to make room for the FRAG header. */ - i = lowpan6_header_len; - while (i-- != 0) { - buffer[ieee_header_len + i + 4] = buffer[ieee_header_len + i]; - } - - /* Now we need to fragment the packet. FRAG1 header first */ - buffer[ieee_header_len] = 0xc0 | (((p->tot_len + lowpan6_header_len) >> 8) & 0x7); - buffer[ieee_header_len + 1] = (p->tot_len + lowpan6_header_len) & 0xff; - - datagram_tag++; - buffer[ieee_header_len + 2] = datagram_tag & 0xff; - buffer[ieee_header_len + 3] = (datagram_tag >> 8) & 0xff; - - /* Fragment follows. */ - frag_len = (127 - ieee_header_len - 4 - 2) & 0xf8; - - pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len + 4, frag_len - lowpan6_header_len, 0); - remaining_len -= frag_len - lowpan6_header_len; - datagram_offset = frag_len; - - /* 2 bytes CRC */ -#if LWIP_6LOWPAN_HW_CRC - /* Leave blank, will be filled by HW. */ -#else /* LWIP_6LOWPAN_HW_CRC */ - /* @todo calculate CRC */ -#endif /* LWIP_6LOWPAN_HW_CRC */ - - /* Calculate frame length */ - p_frag->len = p_frag->tot_len = ieee_header_len + 4 + frag_len + 2; /* add 2 dummy bytes for crc*/ - - /* send the packet */ - MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); - LWIP_DEBUGF(LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); - err = netif->linkoutput(netif, p_frag); - - while ((remaining_len > 0) && (err == ERR_OK)) { - /* new frame, new seq num for ACK */ - buffer[2] = frame_seq_num++; - - buffer[ieee_header_len] |= 0x20; /* Change FRAG1 to FRAGN */ - - buffer[ieee_header_len + 4] = (u8_t)(datagram_offset >> 3); /* datagram offset in FRAGN header (datagram_offset is max. 11 bit) */ - - frag_len = (127 - ieee_header_len - 5 - 2) & 0xf8; - if (frag_len > remaining_len) { - frag_len = remaining_len; - } - - pbuf_copy_partial(p, buffer + ieee_header_len + 5, frag_len, p->tot_len - remaining_len); - remaining_len -= frag_len; - datagram_offset += frag_len; - - /* 2 bytes CRC */ -#if LWIP_6LOWPAN_HW_CRC - /* Leave blank, will be filled by HW. */ -#else /* LWIP_6LOWPAN_HW_CRC */ - /* @todo calculate CRC */ -#endif /* LWIP_6LOWPAN_HW_CRC */ - - /* Calculate frame length */ - p_frag->len = p_frag->tot_len = frag_len + 5 + ieee_header_len + 2; - - /* send the packet */ - MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); - LWIP_DEBUGF(LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); - err = netif->linkoutput(netif, p_frag); - } - } else { - /* It fits in one frame. */ - frag_len = remaining_len; - - /* Copy IPv6 packet */ - pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len, frag_len, 0); - remaining_len = 0; - - /* 2 bytes CRC */ -#if LWIP_6LOWPAN_HW_CRC - /* Leave blank, will be filled by HW. */ -#else /* LWIP_6LOWPAN_HW_CRC */ - /* @todo calculate CRC */ -#endif /* LWIP_6LOWPAN_HW_CRC */ - - /* Calculate frame length */ - p_frag->len = p_frag->tot_len = frag_len + lowpan6_header_len + ieee_header_len + 2; - - /* send the packet */ - MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); - LWIP_DEBUGF(LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); - err = netif->linkoutput(netif, p_frag); - } - - pbuf_free(p_frag); - - return err; -} - -err_t -lowpan6_set_context(u8_t idx, const ip6_addr_t * context) -{ - if (idx >= LWIP_6LOWPAN_NUM_CONTEXTS) { - return ERR_ARG; - } - - ip6_addr_set(&lowpan6_context[idx], context); - - return ERR_OK; -} - -#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS -err_t -lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low) -{ - short_mac_addr.addr[0] = addr_high; - short_mac_addr.addr[1] = addr_low; - - return ERR_OK; -} -#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ - -#if LWIP_IPV4 -err_t -lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) -{ - (void)netif; - (void)q; - (void)ipaddr; - - return ERR_IF; -} -#endif /* LWIP_IPV4 */ - -/** - * Resolve and fill-in IEEE 802.15.4 address header for outgoing IPv6 packet. - * - * Perform Header Compression and fragment if necessary. - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param q The pbuf(s) containing the IP packet to be sent. - * @param ip6addr The IP address of the packet destination. - * - * @return err_t - */ -err_t -lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr) -{ - err_t result; - const u8_t *hwaddr; - struct ieee_802154_addr src, dest; -#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS - ip6_addr_t ip6_src; - struct ip6_hdr * ip6_hdr; -#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ - -#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS - /* Check if we can compress source address (use aligned copy) */ - ip6_hdr = (struct ip6_hdr *)q->payload; - ip6_addr_set(&ip6_src, &ip6_hdr->src); - if (lowpan6_get_address_mode(&ip6_src, &short_mac_addr) == 3) { - src.addr_len = 2; - src.addr[0] = short_mac_addr.addr[0]; - src.addr[1] = short_mac_addr.addr[1]; - } else -#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ - { - src.addr_len = netif->hwaddr_len; - SMEMCPY(src.addr, netif->hwaddr, netif->hwaddr_len); - } - - /* multicast destination IP address? */ - if (ip6_addr_ismulticast(ip6addr)) { - MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); - /* We need to send to the broadcast address.*/ - return lowpan6_frag(netif, q, &src, &ieee_802154_broadcast); - } - - /* We have a unicast destination IP address */ - /* @todo anycast? */ - -#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS - if (src.addr_len == 2) { - /* If source address was compressable to short_mac_addr, and dest has same subnet and - * is also compressable to 2-bytes, assume we can infer dest as a short address too. */ - dest.addr_len = 2; - dest.addr[0] = ((u8_t *)q->payload)[38]; - dest.addr[1] = ((u8_t *)q->payload)[39]; - if ((src.addr_len == 2) && (ip6_addr_netcmp(&ip6_hdr->src, &ip6_hdr->dest)) && - (lowpan6_get_address_mode(ip6addr, &dest) == 3)) { - MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); - return lowpan6_frag(netif, q, &src, &dest); - } - } -#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ - - /* Ask ND6 what to do with the packet. */ - result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr); - if (result != ERR_OK) { - MIB2_STATS_NETIF_INC(netif, ifoutdiscards); - return result; - } - - /* If no hardware address is returned, nd6 has queued the packet for later. */ - if (hwaddr == NULL) { - return ERR_OK; - } - - /* Send out the packet using the returned hardware address. */ - dest.addr_len = netif->hwaddr_len; - SMEMCPY(dest.addr, hwaddr, netif->hwaddr_len); - MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); - return lowpan6_frag(netif, q, &src, &dest); -} - -static struct pbuf * -lowpan6_decompress(struct pbuf * p, struct ieee_802154_addr * src, struct ieee_802154_addr * dest) -{ - struct pbuf * q; - u8_t * lowpan6_buffer; - s8_t lowpan6_offset; - struct ip6_hdr *ip6hdr; - s8_t i; - s8_t ip6_offset = IP6_HLEN; - - - q = pbuf_alloc(PBUF_IP, p->len + IP6_HLEN + UDP_HLEN, PBUF_POOL); - if (q == NULL) { - pbuf_free(p); - return NULL; - } - - lowpan6_buffer = (u8_t *)p->payload; - ip6hdr = (struct ip6_hdr *)q->payload; - - lowpan6_offset = 2; - if (lowpan6_buffer[1] & 0x80) { - lowpan6_offset++; - } - - /* Set IPv6 version, traffic class and flow label. */ - if ((lowpan6_buffer[0] & 0x18) == 0x00) { - IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset], ((lowpan6_buffer[lowpan6_offset+1] & 0x0f) << 16) | (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset+3]); - lowpan6_offset += 4; - } else if ((lowpan6_buffer[0] & 0x18) == 0x08) { - IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset] & 0xc0, ((lowpan6_buffer[lowpan6_offset] & 0x0f) << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset+2]); - lowpan6_offset += 3; - } else if ((lowpan6_buffer[0] & 0x18) == 0x10) { - IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset],0); - lowpan6_offset += 1; - } else if ((lowpan6_buffer[0] & 0x18) == 0x18) { - IP6H_VTCFL_SET(ip6hdr, 6, 0, 0); - } - - /* Set Next Header */ - if ((lowpan6_buffer[0] & 0x04) == 0x00) { - IP6H_NEXTH_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]); - } else { - /* We should fill this later with NHC decoding */ - IP6H_NEXTH_SET(ip6hdr, 0); - } - - /* Set Hop Limit */ - if ((lowpan6_buffer[0] & 0x03) == 0x00) { - IP6H_HOPLIM_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]); - } else if ((lowpan6_buffer[0] & 0x03) == 0x01) { - IP6H_HOPLIM_SET(ip6hdr, 1); - } else if ((lowpan6_buffer[0] & 0x03) == 0x02) { - IP6H_HOPLIM_SET(ip6hdr, 64); - } else if ((lowpan6_buffer[0] & 0x03) == 0x03) { - IP6H_HOPLIM_SET(ip6hdr, 255); - } - - /* Source address decoding. */ - if ((lowpan6_buffer[1] & 0x40) == 0x00) { - /* Stateless compression */ - if ((lowpan6_buffer[1] & 0x30) == 0x00) { - /* copy full address */ - MEMCPY(&ip6hdr->src.addr[0], lowpan6_buffer + lowpan6_offset, 16); - lowpan6_offset += 16; - } else if ((lowpan6_buffer[1] & 0x30) == 0x10) { - ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); - ip6hdr->src.addr[1] = 0; - MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8); - lowpan6_offset += 8; - } else if ((lowpan6_buffer[1] & 0x30) == 0x20) { - ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); - ip6hdr->src.addr[1] = 0; - ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | - lowpan6_buffer[lowpan6_offset+1]); - lowpan6_offset += 2; - } else if ((lowpan6_buffer[1] & 0x30) == 0x30) { - ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); - ip6hdr->src.addr[1] = 0; - if (src->addr_len == 2) { - ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]); - } else { - ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) | - (src->addr[2] << 8) | src->addr[3]); - ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) | - (src->addr[6] << 8) | src->addr[7]); - } - } - } else { - /* Stateful compression */ - if ((lowpan6_buffer[1] & 0x30) == 0x00) { - /* ANY address */ - ip6hdr->src.addr[0] = 0; - ip6hdr->src.addr[1] = 0; - ip6hdr->src.addr[2] = 0; - ip6hdr->src.addr[3] = 0; - } else { - /* Set prefix from context info */ - if (lowpan6_buffer[1] & 0x80) { - i = (lowpan6_buffer[2] >> 4) & 0x0f; - } else { - i = 0; - } - if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) { - /* Error */ - pbuf_free(p); - pbuf_free(q); - return NULL; - } - - ip6hdr->src.addr[0] = lowpan6_context[i].addr[0]; - ip6hdr->src.addr[1] = lowpan6_context[i].addr[1]; - } - - if ((lowpan6_buffer[1] & 0x30) == 0x10) { - MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8); - lowpan6_offset += 8; - } else if ((lowpan6_buffer[1] & 0x30) == 0x20) { - ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset+1]); - lowpan6_offset += 2; - } else if ((lowpan6_buffer[1] & 0x30) == 0x30) { - if (src->addr_len == 2) { - ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]); - } else { - ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) | (src->addr[2] << 8) | src->addr[3]); - ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) | (src->addr[6] << 8) | src->addr[7]); - } - } - } - - /* Destination address decoding. */ - if (lowpan6_buffer[1] & 0x08) { - /* Multicast destination */ - if (lowpan6_buffer[1] & 0x04) { - /* @todo support stateful multicast addressing */ - pbuf_free(p); - pbuf_free(q); - return NULL; - } - - if ((lowpan6_buffer[1] & 0x03) == 0x00) { - /* copy full address */ - MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16); - lowpan6_offset += 16; - } else if ((lowpan6_buffer[1] & 0x03) == 0x01) { - ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | (lowpan6_buffer[lowpan6_offset++] << 16)); - ip6hdr->dest.addr[1] = 0; - ip6hdr->dest.addr[2] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]); - ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 24) | (lowpan6_buffer[lowpan6_offset + 1] << 16) | (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset + 3]); - lowpan6_offset += 4; - } else if ((lowpan6_buffer[1] & 0x03) == 0x02) { - ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | lowpan6_buffer[lowpan6_offset++]); - ip6hdr->dest.addr[1] = 0; - ip6hdr->dest.addr[2] = 0; - ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset + 2]); - lowpan6_offset += 3; - } else if ((lowpan6_buffer[1] & 0x03) == 0x03) { - ip6hdr->dest.addr[0] = PP_HTONL(0xff020000UL); - ip6hdr->dest.addr[1] = 0; - ip6hdr->dest.addr[2] = 0; - ip6hdr->dest.addr[3] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]); - } - - } else { - if (lowpan6_buffer[1] & 0x04) { - /* Stateful destination compression */ - /* Set prefix from context info */ - if (lowpan6_buffer[1] & 0x80) { - i = lowpan6_buffer[2] & 0x0f; - } else { - i = 0; - } - if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) { - /* Error */ - pbuf_free(p); - pbuf_free(q); - return NULL; - } - - ip6hdr->dest.addr[0] = lowpan6_context[i].addr[0]; - ip6hdr->dest.addr[1] = lowpan6_context[i].addr[1]; - } else { - /* Link local address compression */ - ip6hdr->dest.addr[0] = PP_HTONL(0xfe800000UL); - ip6hdr->dest.addr[1] = 0; - } - - if ((lowpan6_buffer[1] & 0x03) == 0x00) { - /* copy full address */ - MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16); - lowpan6_offset += 16; - } else if ((lowpan6_buffer[1] & 0x03) == 0x01) { - MEMCPY(&ip6hdr->dest.addr[2], lowpan6_buffer + lowpan6_offset, 8); - lowpan6_offset += 8; - } else if ((lowpan6_buffer[1] & 0x03) == 0x02) { - ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset + 1]); - lowpan6_offset += 2; - } else if ((lowpan6_buffer[1] & 0x03) == 0x03) { - if (dest->addr_len == 2) { - ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL); - ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (dest->addr[0] << 8) | dest->addr[1]); - } else { - ip6hdr->dest.addr[2] = lwip_htonl(((dest->addr[0] ^ 2) << 24) | (dest->addr[1] << 16) | dest->addr[2] << 8 | dest->addr[3]); - ip6hdr->dest.addr[3] = lwip_htonl((dest->addr[4] << 24) | (dest->addr[5] << 16) | dest->addr[6] << 8 | dest->addr[7]); - } - } - } - - - /* Next Header Compression (NHC) decoding? */ - if (lowpan6_buffer[0] & 0x04) { - if ((lowpan6_buffer[lowpan6_offset] & 0xf8) == 0xf0) { - struct udp_hdr *udphdr; - - /* UDP compression */ - IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_UDP); - udphdr = (struct udp_hdr *)((u8_t *)q->payload + ip6_offset); - - if (lowpan6_buffer[lowpan6_offset] & 0x04) { - /* @todo support checksum decompress */ - pbuf_free(p); - pbuf_free(q); - return NULL; - } - - /* Decompress ports */ - i = lowpan6_buffer[lowpan6_offset++] & 0x03; - if (i == 0) { - udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); - udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 2] << 8 | lowpan6_buffer[lowpan6_offset + 3]); - lowpan6_offset += 4; - } else if (i == 0x01) { - udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); - udphdr->dest = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset + 2]); - lowpan6_offset += 3; - } else if (i == 0x02) { - udphdr->src = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset]); - udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 1] << 8 | lowpan6_buffer[lowpan6_offset + 2]); - lowpan6_offset += 3; - } else if (i == 0x03) { - udphdr->src = lwip_htons(0xf0b0 | ((lowpan6_buffer[lowpan6_offset] >> 4) & 0x0f)); - udphdr->dest = lwip_htons(0xf0b0 | (lowpan6_buffer[lowpan6_offset] & 0x0f)); - lowpan6_offset += 1; - } - - udphdr->chksum = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); - lowpan6_offset += 2; - udphdr->len = lwip_htons(p->tot_len - lowpan6_offset + UDP_HLEN); - - ip6_offset += UDP_HLEN; - } else { - /* @todo support NHC other than UDP */ - pbuf_free(p); - pbuf_free(q); - return NULL; - } - } - - /* Now we copy leftover contents from p to q, so we have all L2 and L3 headers (and L4?) in a single PBUF. - * Replace p with q, and free p */ - pbuf_header(p, -lowpan6_offset); - MEMCPY((u8_t*)q->payload + ip6_offset, p->payload, p->len); - q->len = q->tot_len = ip6_offset + p->len; - if (p->next != NULL) { - pbuf_cat(q, p->next); - } - p->next = NULL; - pbuf_free(p); - - /* Infer IPv6 payload length for header */ - IP6H_PLEN_SET(ip6hdr, q->tot_len - IP6_HLEN); - - /* all done */ - return q; -} - -err_t -lowpan6_input(struct pbuf * p, struct netif *netif) -{ - u8_t * puc; - s8_t i; - struct ieee_802154_addr src, dest; - u16_t datagram_size, datagram_offset, datagram_tag; - struct lowpan6_reass_helper *lrh, *lrh_temp; - - MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); - - /* Analyze header. @todo validate. */ - puc = (u8_t*)p->payload; - datagram_offset = 5; - if ((puc[1] & 0x0c) == 0x0c) { - dest.addr_len = 8; - for (i = 0; i < 8; i++) { - dest.addr[i] = puc[datagram_offset + 7 - i]; - } - datagram_offset += 8; - } else { - dest.addr_len = 2; - dest.addr[0] = puc[datagram_offset + 1]; - dest.addr[1] = puc[datagram_offset]; - datagram_offset += 2; - } - - datagram_offset += 2; /* skip PAN ID. */ - - if ((puc[1] & 0xc0) == 0xc0) { - src.addr_len = 8; - for (i = 0; i < 8; i++) { - src.addr[i] = puc[datagram_offset + 7 - i]; - } - datagram_offset += 8; - } else { - src.addr_len = 2; - src.addr[0] = puc[datagram_offset + 1]; - src.addr[1] = puc[datagram_offset]; - datagram_offset += 2; - } - - pbuf_header(p, -datagram_offset); /* hide IEEE802.15.4 header. */ - - /* Check dispatch. */ - puc = (u8_t*)p->payload; - - if ((*puc & 0xf8) == 0xc0) { - /* FRAG1 dispatch. add this packet to reassembly list. */ - datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1]; - datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3]; - - /* check for duplicate */ - lrh = reass_list; - while (lrh != NULL) { - if ((lrh->sender_addr.addr_len == src.addr_len) && - (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0)) { - /* address match with packet in reassembly. */ - if ((datagram_tag == lrh->datagram_tag) && (datagram_size == lrh->datagram_size)) { - MIB2_STATS_NETIF_INC(netif, ifindiscards); - /* duplicate fragment. */ - pbuf_free(p); - return ERR_OK; - } else { - /* We are receiving the start of a new datagram. Discard old one (incomplete). */ - lrh_temp = lrh->next_packet; - dequeue_datagram(lrh); - pbuf_free(lrh->pbuf); - mem_free(lrh); - - /* Check next datagram in queue. */ - lrh = lrh_temp; - } - } else { - /* Check next datagram in queue. */ - lrh = lrh->next_packet; - } - } - - pbuf_header(p, -4); /* hide frag1 dispatch */ - - lrh = (struct lowpan6_reass_helper *) mem_malloc(sizeof(struct lowpan6_reass_helper)); - if (lrh == NULL) { - MIB2_STATS_NETIF_INC(netif, ifindiscards); - pbuf_free(p); - return ERR_MEM; - } - - lrh->sender_addr.addr_len = src.addr_len; - for (i = 0; i < src.addr_len; i++) { - lrh->sender_addr.addr[i] = src.addr[i]; - } - lrh->datagram_size = datagram_size; - lrh->datagram_tag = datagram_tag; - lrh->pbuf = p; - lrh->next_packet = reass_list; - lrh->timer = 2; - reass_list = lrh; - - return ERR_OK; - } else if ((*puc & 0xf8) == 0xe0) { - /* FRAGN dispatch, find packet being reassembled. */ - datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1]; - datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3]; - datagram_offset = (u16_t)puc[4] << 3; - pbuf_header(p, -5); /* hide frag1 dispatch */ - - for (lrh = reass_list; lrh != NULL; lrh = lrh->next_packet) { - if ((lrh->sender_addr.addr_len == src.addr_len) && - (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0) && - (datagram_tag == lrh->datagram_tag) && - (datagram_size == lrh->datagram_size)) { - break; - } - } - if (lrh == NULL) { - /* rogue fragment */ - MIB2_STATS_NETIF_INC(netif, ifindiscards); - pbuf_free(p); - return ERR_OK; - } - - if (lrh->pbuf->tot_len < datagram_offset) { - /* duplicate, ignore. */ - pbuf_free(p); - return ERR_OK; - } else if (lrh->pbuf->tot_len > datagram_offset) { - MIB2_STATS_NETIF_INC(netif, ifindiscards); - /* We have missed a fragment. Delete whole reassembly. */ - dequeue_datagram(lrh); - pbuf_free(lrh->pbuf); - mem_free(lrh); - pbuf_free(p); - return ERR_OK; - } - pbuf_cat(lrh->pbuf, p); - p = NULL; - - /* is packet now complete?*/ - if (lrh->pbuf->tot_len >= lrh->datagram_size) { - /* dequeue from reass list. */ - dequeue_datagram(lrh); - - /* get pbuf */ - p = lrh->pbuf; - - /* release helper */ - mem_free(lrh); - } else { - return ERR_OK; - } - } - - if (p == NULL) { - return ERR_OK; - } - - /* We have a complete packet, check dispatch for headers. */ - puc = (u8_t*)p->payload; - - if (*puc == 0x41) { - /* This is a complete IPv6 packet, just skip dispatch byte. */ - pbuf_header(p, -1); /* hide dispatch byte. */ - } else if ((*puc & 0xe0 )== 0x60) { - /* IPv6 headers are compressed using IPHC. */ - p = lowpan6_decompress(p, &src, &dest); - if (p == NULL) { - MIB2_STATS_NETIF_INC(netif, ifindiscards); - return ERR_OK; - } - } else { - MIB2_STATS_NETIF_INC(netif, ifindiscards); - pbuf_free(p); - return ERR_OK; - } - - /* @todo: distinguish unicast/multicast */ - MIB2_STATS_NETIF_INC(netif, ifinucastpkts); - - return ip6_input(p, netif); -} - -err_t -lowpan6_if_init(struct netif *netif) -{ - netif->name[0] = 'L'; - netif->name[1] = '6'; -#if LWIP_IPV4 - netif->output = lowpan4_output; -#endif /* LWIP_IPV4 */ - netif->output_ip6 = lowpan6_output; - - MIB2_INIT_NETIF(netif, snmp_ifType_other, 0); - - /* maximum transfer unit */ - netif->mtu = 1280; - - /* broadcast capability */ - netif->flags = NETIF_FLAG_BROADCAST /* | NETIF_FLAG_LOWPAN6 */; - - return ERR_OK; -} - -err_t -lowpan6_set_pan_id(u16_t pan_id) -{ - ieee_802154_pan_id = pan_id; - - return ERR_OK; -} - -#if !NO_SYS -/** - * Pass a received packet to tcpip_thread for input processing - * - * @param p the received packet, p->payload pointing to the - * IEEE 802.15.4 header. - * @param inp the network interface on which the packet was received - */ -err_t -tcpip_6lowpan_input(struct pbuf *p, struct netif *inp) -{ - return tcpip_inpkt(p, inp, lowpan6_input); -} -#endif /* !NO_SYS */ - -#endif /* LWIP_IPV6 && LWIP_6LOWPAN */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/slipif.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/slipif.c deleted file mode 100644 index 6eb83c35a4adff7ae851a6f0687900796669df31..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/src/netif/slipif.c +++ /dev/null @@ -1,555 +0,0 @@ -/** - * @file - * SLIP Interface - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is built upon the file: src/arch/rtxc/netif/sioslip.c - * - * Author: Magnus Ivarsson - * Simon Goldschmidt - */ - - -/** - * @defgroup slipif SLIP netif - * @ingroup addons - * - * This is an arch independent SLIP netif. The specific serial hooks must be - * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send - * - * Usage: This netif can be used in three ways:\n - * 1) For NO_SYS==0, an RX thread can be used which blocks on sio_read() - * until data is received.\n - * 2) In your main loop, call slipif_poll() to check for new RX bytes, - * completed packets are fed into netif->input().\n - * 3) Call slipif_received_byte[s]() from your serial RX ISR and - * slipif_process_rxqueue() from your main loop. ISR level decodes - * packets and puts completed packets on a queue which is fed into - * the stack from the main loop (needs SYS_LIGHTWEIGHT_PROT for - * pbuf_alloc to work on ISR level!). - * - */ - -#include "netif/slipif.h" -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/sys.h" -#include "lwip/sio.h" - -#define SLIP_END 0xC0 /* 0300: start and end of every packet */ -#define SLIP_ESC 0xDB /* 0333: escape start (one byte escaped data follows) */ -#define SLIP_ESC_END 0xDC /* 0334: following escape: original byte is 0xC0 (END) */ -#define SLIP_ESC_ESC 0xDD /* 0335: following escape: original byte is 0xDB (ESC) */ - -/** Maximum packet size that is received by this netif */ -#ifndef SLIP_MAX_SIZE -#define SLIP_MAX_SIZE 1500 -#endif - -/** Define this to the interface speed for SNMP - * (sio_fd is the sio_fd_t returned by sio_open). - * The default value of zero means 'unknown'. - */ -#ifndef SLIP_SIO_SPEED -#define SLIP_SIO_SPEED(sio_fd) 0 -#endif - -enum slipif_recv_state { - SLIP_RECV_NORMAL, - SLIP_RECV_ESCAPE -}; - -struct slipif_priv { - sio_fd_t sd; - /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */ - struct pbuf *p, *q; - u8_t state; - u16_t i, recved; -#if SLIP_RX_FROM_ISR - struct pbuf *rxpackets; -#endif -}; - -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - * - * @param netif the lwip network interface structure for this slipif - * @param p the pbuf chain packet to send - * @return always returns ERR_OK since the serial layer does not provide return values - */ -static err_t -slipif_output(struct netif *netif, struct pbuf *p) -{ - struct slipif_priv *priv; - struct pbuf *q; - u16_t i; - u8_t c; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - LWIP_ASSERT("p != NULL", (p != NULL)); - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_output(%"U16_F"): sending %"U16_F" bytes\n", (u16_t)netif->num, p->tot_len)); - priv = (struct slipif_priv *)netif->state; - - /* Send pbuf out on the serial I/O device. */ - /* Start with packet delimiter. */ - sio_send(SLIP_END, priv->sd); - - for (q = p; q != NULL; q = q->next) { - for (i = 0; i < q->len; i++) { - c = ((u8_t *)q->payload)[i]; - switch (c) { - case SLIP_END: - /* need to escape this byte (0xC0 -> 0xDB, 0xDC) */ - sio_send(SLIP_ESC, priv->sd); - sio_send(SLIP_ESC_END, priv->sd); - break; - case SLIP_ESC: - /* need to escape this byte (0xDB -> 0xDB, 0xDD) */ - sio_send(SLIP_ESC, priv->sd); - sio_send(SLIP_ESC_ESC, priv->sd); - break; - default: - /* normal byte - no need for escaping */ - sio_send(c, priv->sd); - break; - } - } - } - /* End with packet delimiter. */ - sio_send(SLIP_END, priv->sd); - return ERR_OK; -} - -#if LWIP_IPV4 -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - * - * @param netif the lwip network interface structure for this slipif - * @param p the pbuf chain packet to send - * @param ipaddr the ip address to send the packet to (not used for slipif) - * @return always returns ERR_OK since the serial layer does not provide return values - */ -static err_t -slipif_output_v4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) -{ - LWIP_UNUSED_ARG(ipaddr); - return slipif_output(netif, p); -} -#endif /* LWIP_IPV4 */ - -#if LWIP_IPV6 -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - * - * @param netif the lwip network interface structure for this slipif - * @param p the pbuf chain packet to send - * @param ipaddr the ip address to send the packet to (not used for slipif) - * @return always returns ERR_OK since the serial layer does not provide return values - */ -static err_t -slipif_output_v6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr) -{ - LWIP_UNUSED_ARG(ipaddr); - return slipif_output(netif, p); -} -#endif /* LWIP_IPV6 */ - -/** - * Handle the incoming SLIP stream character by character - * - * @param netif the lwip network interface structure for this slipif - * @param c received character (multiple calls to this function will - * return a complete packet, NULL is returned before - used for polling) - * @return The IP packet when SLIP_END is received - */ -static struct pbuf* -slipif_rxbyte(struct netif *netif, u8_t c) -{ - struct slipif_priv *priv; - struct pbuf *t; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - priv = (struct slipif_priv *)netif->state; - - switch (priv->state) { - case SLIP_RECV_NORMAL: - switch (c) { - case SLIP_END: - if (priv->recved > 0) { - /* Received whole packet. */ - /* Trim the pbuf to the size of the received packet. */ - pbuf_realloc(priv->q, priv->recved); - - LINK_STATS_INC(link.recv); - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet (%"U16_F" bytes)\n", priv->recved)); - t = priv->q; - priv->p = priv->q = NULL; - priv->i = priv->recved = 0; - return t; - } - return NULL; - case SLIP_ESC: - priv->state = SLIP_RECV_ESCAPE; - return NULL; - default: - break; - } /* end switch (c) */ - break; - case SLIP_RECV_ESCAPE: - /* un-escape END or ESC bytes, leave other bytes - (although that would be a protocol error) */ - switch (c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - default: - break; - } - priv->state = SLIP_RECV_NORMAL; - break; - default: - break; - } /* end switch (priv->state) */ - - /* byte received, packet not yet completely received */ - if (priv->p == NULL) { - /* allocate a new pbuf */ - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); - priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - PBUF_LINK_ENCAPSULATION_HLEN), PBUF_POOL); - - if (priv->p == NULL) { - LINK_STATS_INC(link.drop); - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); - /* don't process any further since we got no pbuf to receive to */ - return NULL; - } - - if (priv->q != NULL) { - /* 'chain' the pbuf to the existing chain */ - pbuf_cat(priv->q, priv->p); - } else { - /* p is the first pbuf in the chain */ - priv->q = priv->p; - } - } - - /* this automatically drops bytes if > SLIP_MAX_SIZE */ - if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) { - ((u8_t *)priv->p->payload)[priv->i] = c; - priv->recved++; - priv->i++; - if (priv->i >= priv->p->len) { - /* on to the next pbuf */ - priv->i = 0; - if (priv->p->next != NULL && priv->p->next->len > 0) { - /* p is a chain, on to the next in the chain */ - priv->p = priv->p->next; - } else { - /* p is a single pbuf, set it to NULL so next time a new - * pbuf is allocated */ - priv->p = NULL; - } - } - } - return NULL; -} - -/** Like slipif_rxbyte, but passes completed packets to netif->input - * - * @param netif The lwip network interface structure for this slipif - * @param c received character - */ -static void -slipif_rxbyte_input(struct netif *netif, u8_t c) -{ - struct pbuf *p; - p = slipif_rxbyte(netif, c); - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } -} - -#if SLIP_USE_RX_THREAD -/** - * The SLIP input thread. - * - * Feed the IP layer with incoming packets - * - * @param nf the lwip network interface structure for this slipif - */ -static void -slipif_loop_thread(void *nf) -{ - u8_t c; - struct netif *netif = (struct netif *)nf; - struct slipif_priv *priv = (struct slipif_priv *)netif->state; - - while (1) { - if (sio_read(priv->sd, &c, 1) > 0) { - slipif_rxbyte_input(netif, c); - } - } -} -#endif /* SLIP_USE_RX_THREAD */ - -/** - * SLIP netif initialization - * - * Call the arch specific sio_open and remember - * the opened device in the state field of the netif. - * - * @param netif the lwip network interface structure for this slipif - * @return ERR_OK if serial line could be opened, - * ERR_MEM if no memory could be allocated, - * ERR_IF is serial line couldn't be opened - * - * @note netif->num must contain the number of the serial port to open - * (0 by default). If netif->state is != NULL, it is interpreted as an - * u8_t pointer pointing to the serial port number instead of netif->num. - * - */ -err_t -slipif_init(struct netif *netif) -{ - struct slipif_priv *priv; - u8_t sio_num; - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); - - /* Allocate private data */ - priv = (struct slipif_priv *)mem_malloc(sizeof(struct slipif_priv)); - if (!priv) { - return ERR_MEM; - } - - netif->name[0] = 's'; - netif->name[1] = 'l'; -#if LWIP_IPV4 - netif->output = slipif_output_v4; -#endif /* LWIP_IPV4 */ -#if LWIP_IPV6 - netif->output_ip6 = slipif_output_v6; -#endif /* LWIP_IPV6 */ - netif->mtu = SLIP_MAX_SIZE; - - /* netif->state or netif->num contain the port number */ - if (netif->state != NULL) { - sio_num = *(u8_t*)netif->state; - } else { - sio_num = netif->num; - } - /* Try to open the serial port. */ - priv->sd = sio_open(sio_num); - if (!priv->sd) { - /* Opening the serial port failed. */ - mem_free(priv); - return ERR_IF; - } - - /* Initialize private data */ - priv->p = NULL; - priv->q = NULL; - priv->state = SLIP_RECV_NORMAL; - priv->i = 0; - priv->recved = 0; -#if SLIP_RX_FROM_ISR - priv->rxpackets = NULL; -#endif - - netif->state = priv; - - /* initialize the snmp variables and counters inside the struct netif */ - MIB2_INIT_NETIF(netif, snmp_ifType_slip, SLIP_SIO_SPEED(priv->sd)); - -#if SLIP_USE_RX_THREAD - /* Create a thread to poll the serial line. */ - sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif, - SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO); -#endif /* SLIP_USE_RX_THREAD */ - return ERR_OK; -} - -/** - * Polls the serial device and feeds the IP layer with incoming packets. - * - * @param netif The lwip network interface structure for this slipif - */ -void -slipif_poll(struct netif *netif) -{ - u8_t c; - struct slipif_priv *priv; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - priv = (struct slipif_priv *)netif->state; - - while (sio_tryread(priv->sd, &c, 1) > 0) { - slipif_rxbyte_input(netif, c); - } -} - -#if SLIP_RX_FROM_ISR -/** - * Feeds the IP layer with incoming packets that were receive - * - * @param netif The lwip network interface structure for this slipif - */ -void -slipif_process_rxqueue(struct netif *netif) -{ - struct slipif_priv *priv; - SYS_ARCH_DECL_PROTECT(old_level); - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - priv = (struct slipif_priv *)netif->state; - - SYS_ARCH_PROTECT(old_level); - while (priv->rxpackets != NULL) { - struct pbuf *p = priv->rxpackets; -#if SLIP_RX_QUEUE - /* dequeue packet */ - struct pbuf *q = p; - while ((q->len != q->tot_len) && (q->next != NULL)) { - q = q->next; - } - priv->rxpackets = q->next; - q->next = NULL; -#else /* SLIP_RX_QUEUE */ - priv->rxpackets = NULL; -#endif /* SLIP_RX_QUEUE */ - SYS_ARCH_UNPROTECT(old_level); - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - SYS_ARCH_PROTECT(old_level); - } -} - -/** Like slipif_rxbyte, but queues completed packets. - * - * @param netif The lwip network interface structure for this slipif - * @param data Received serial byte - */ -static void -slipif_rxbyte_enqueue(struct netif *netif, u8_t data) -{ - struct pbuf *p; - struct slipif_priv *priv = (struct slipif_priv *)netif->state; - SYS_ARCH_DECL_PROTECT(old_level); - - p = slipif_rxbyte(netif, data); - if (p != NULL) { - SYS_ARCH_PROTECT(old_level); - if (priv->rxpackets != NULL) { -#if SLIP_RX_QUEUE - /* queue multiple pbufs */ - struct pbuf *q = p; - while (q->next != NULL) { - q = q->next; - } - q->next = p; - } else { -#else /* SLIP_RX_QUEUE */ - pbuf_free(priv->rxpackets); - } - { -#endif /* SLIP_RX_QUEUE */ - priv->rxpackets = p; - } - SYS_ARCH_UNPROTECT(old_level); - } -} - -/** - * Process a received byte, completed packets are put on a queue that is - * fed into IP through slipif_process_rxqueue(). - * - * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled. - * - * @param netif The lwip network interface structure for this slipif - * @param data received character - */ -void -slipif_received_byte(struct netif *netif, u8_t data) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - slipif_rxbyte_enqueue(netif, data); -} - -/** - * Process multiple received byte, completed packets are put on a queue that is - * fed into IP through slipif_process_rxqueue(). - * - * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled. - * - * @param netif The lwip network interface structure for this slipif - * @param data received character - * @param len Number of received characters - */ -void -slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len) -{ - u8_t i; - u8_t *rxdata = data; - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - for (i = 0; i < len; i++, rxdata++) { - slipif_rxbyte_enqueue(netif, *rxdata); - } -} -#endif /* SLIP_RX_FROM_ISR */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/Makefile b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/Makefile deleted file mode 100644 index 67ffb1957eb3718b6b56d304781d96a3ef0a5d72..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# Copyright (c) 2001, 2002 Swedish Institute of Computer Science. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -# SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -# OF SUCH DAMAGE. -# -# This file is part of the lwIP TCP/IP stack. -# -# Author: Adam Dunkels -# - -all compile: lwip_fuzz -.PHONY: all clean - -CC=afl-gcc -LDFLAGS=-lm -CFLAGS=-O0 - -CONTRIBDIR=../../../lwip-contrib -include $(CONTRIBDIR)/ports/unix/Common.mk - -clean: - rm -f *.o $(LWIPLIBCOMMON) lwip_fuzz *.s .depend* *.core core - -depend dep: .depend - -include .depend - -.depend: fuzz.c $(LWIPFILES) $(APPFILES) - $(CCDEP) $(CFLAGS) -MM $^ > .depend || rm -f .depend - -lwip_fuzz: .depend $(LWIPLIBCOMMON) fuzz.o - $(CC) $(CFLAGS) -o lwip_fuzz fuzz.o $(LWIPLIBCOMMON) $(LDFLAGS) diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/README b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/README deleted file mode 100644 index 1d1e3d8deb43ccb35a29bb2c54c560d3d884e5d4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/README +++ /dev/null @@ -1,34 +0,0 @@ - -Fuzzing the lwIP stack (afl-fuzz requires linux/unix or similar) - -This directory contains a small app that reads Ethernet frames from stdin and -processes them. It is used together with the 'american fuzzy lop' tool (found -at http://lcamtuf.coredump.cx/afl/) and the sample inputs to test how -unexpected inputs are handled. The afl tool will read the known inputs, and -try to modify them to exercise as many code paths as possible, by instrumenting -the code and keeping track of which code is executed. - -Just running make will produce the test program. - -Then run afl with: - -afl-fuzz -i inputs/ -o output ./lwip_fuzz - -and it should start working. It will probably complain about CPU scheduler, -set AFL_SKIP_CPUFREQ=1 to ignore it. -If it complains about invalid "/proc/sys/kernel/core_pattern" setting, try -executing "sudo bash -c 'echo core > /proc/sys/kernel/core_pattern'". - -The input is split into different subdirectories since they test different -parts of the code, and since you want to run one instance of afl-fuzz on each -core. - -When afl finds a crash or a hang, the input that caused it will be placed in -the output directory. If you have hexdump and text2pcap tools installed, -running output_to_pcap.sh will create pcap files for each input -file to simplify viewing in wireshark. - -The lwipopts.h file needs to have checksum checking off, otherwise almost every -packet will be discarded because of that. The other options can be tuned to -expose different parts of the code. - diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/fuzz.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/fuzz.c deleted file mode 100644 index 1627f7aca6476b18390eee86b6edfdf12d0b603c..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/fuzz.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ - -#include "lwip/init.h" -#include "lwip/netif.h" -#include "netif/etharp.h" -#if LWIP_IPV6 -#include "lwip/ethip6.h" -#include "lwip/nd6.h" -#endif -#include -#include - -/* no-op send function */ -static err_t lwip_tx_func(struct netif *netif, struct pbuf *p) -{ - LWIP_UNUSED_ARG(netif); - LWIP_UNUSED_ARG(p); - return ERR_OK; -} - -static err_t testif_init(struct netif *netif) -{ - netif->name[0] = 'f'; - netif->name[1] = 'z'; - netif->output = etharp_output; - netif->linkoutput = lwip_tx_func; - netif->mtu = 1500; - netif->hwaddr_len = 6; - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - netif->hwaddr[0] = 0x00; - netif->hwaddr[1] = 0x23; - netif->hwaddr[2] = 0xC1; - netif->hwaddr[3] = 0xDE; - netif->hwaddr[4] = 0xD0; - netif->hwaddr[5] = 0x0D; - -#if LWIP_IPV6 - netif->output_ip6 = ethip6_output; - netif->ip6_autoconfig_enabled = 1; - netif_create_ip6_linklocal_address(netif, 1); - netif->flags |= NETIF_FLAG_MLD6; -#endif - - return ERR_OK; -} - -static void input_pkt(struct netif *netif, const u8_t *data, size_t len) -{ - struct pbuf *p, *q; - err_t err; - - LWIP_ASSERT("pkt too big", len <= 0xFFFF); - p = pbuf_alloc(PBUF_RAW, (u16_t)len, PBUF_POOL); - LWIP_ASSERT("alloc failed", p); - for(q = p; q != NULL; q = q->next) { - MEMCPY(q->payload, data, q->len); - data += q->len; - } - err = netif->input(p, netif); - if (err != ERR_OK) { - pbuf_free(p); - } -} - -int main(int argc, char** argv) -{ - struct netif net_test; - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - u8_t pktbuf[2000]; - size_t len; - - lwip_init(); - - IP4_ADDR(&addr, 172, 30, 115, 84); - IP4_ADDR(&netmask, 255, 255, 255, 0); - IP4_ADDR(&gw, 172, 30, 115, 1); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - -#if LWIP_IPV6 - nd6_tmr(); /* tick nd to join multicast groups */ -#endif - - if(argc > 1) { - FILE* f; - const char* filename; - os_printf("reading input from file... "); - fflush(stdout); - filename = argv[1]; - LWIP_ASSERT("invalid filename", filename != NULL); - f = fopen(filename, "rb"); - LWIP_ASSERT("open failed", f != NULL); - len = fread(pktbuf, 1, sizeof(pktbuf), f); - fclose(f); - os_printf("testing file: \"%s\"...\r\n", filename); - } else { - len = fread(pktbuf, 1, sizeof(pktbuf), stdin); - } - input_pkt(&net_test, pktbuf, len); - - return 0; -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/arp/arp_req.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/arp/arp_req.bin deleted file mode 100644 index b317334f9e2fbe8cffe7624e453ae4c782fc6de7..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/arp/arp_req.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/icmp/icmp_ping.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/icmp/icmp_ping.bin deleted file mode 100644 index 87e1ea795e571f48fd3611079ab8c5a972851db8..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/icmp/icmp_ping.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/neighbor_solicitation.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/neighbor_solicitation.bin deleted file mode 100644 index d2f921c36371c68bd768f0d8e777c309cba5b908..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/neighbor_solicitation.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/router_adv.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/router_adv.bin deleted file mode 100644 index 3aa961569a54adf109e99d9a3cb300beaf96c430..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/ipv6/router_adv.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/tcp/tcp_syn.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/tcp/tcp_syn.bin deleted file mode 100644 index d77f6d23bd23079976c54e9e3bf5fdaa0ee8ffc1..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/tcp/tcp_syn.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/udp/udp_port_5000.bin b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/udp/udp_port_5000.bin deleted file mode 100644 index d77e26752b9c9163d7d404502df7b121f10520b5..0000000000000000000000000000000000000000 Binary files a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/inputs/udp/udp_port_5000.bin and /dev/null differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/lwipopts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/lwipopts.h deleted file mode 100644 index 4aff09bad6d31286f2ed8430d3ea1a41c1f7d17a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/lwipopts.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_LWIPOPTS_H__ -#define LWIP_HDR_LWIPOPTS_H__ - -/* Prevent having to link sys_arch.c (we don't test the API layers in unit tests) */ -#define NO_SYS 1 -#define LWIP_NETCONN 0 -#define LWIP_SOCKET 0 -#define SYS_LIGHTWEIGHT_PROT 0 - -#define LWIP_IPV6 1 -#define IPV6_FRAG_COPYHEADER 1 -#define LWIP_IPV6_DUP_DETECT_ATTEMPTS 0 - -/* Enable DHCP to test it */ -#define LWIP_DHCP 1 - -/* Turn off checksum verification of fuzzed data */ -#define CHECKSUM_CHECK_IP 0 -#define CHECKSUM_CHECK_UDP 0 -#define CHECKSUM_CHECK_TCP 0 -#define CHECKSUM_CHECK_ICMP 0 -#define CHECKSUM_CHECK_ICMP6 0 - -/* Minimal changes to opt.h required for tcp unit tests: */ -#define MEM_SIZE 16000 -#define TCP_SND_QUEUELEN 40 -#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN -#define TCP_SND_BUF (12 * TCP_MSS) -#define TCP_WND (10 * TCP_MSS) -#define LWIP_WND_SCALE 1 -#define TCP_RCV_SCALE 0 -#define PBUF_POOL_SIZE 400 /* pbuf tests need ~200KByte */ - -/* Minimal changes to opt.h required for etharp unit tests: */ -#define ETHARP_SUPPORT_STATIC_ENTRIES 1 - -#endif /* LWIP_HDR_LWIPOPTS_H__ */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/output_to_pcap.sh b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/output_to_pcap.sh deleted file mode 100644 index c999ff0392939d145f6d4c3fa2968c7c2175145a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/output_to_pcap.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash - -if [ -z "$1" ] -then - echo "This script will make pcap files from the afl-fuzz crash/hang files" - echo "It needs hexdump and text2pcap" - echo "Please give output directory as argument" - exit 2 -fi - -for i in `ls $1/crashes/id*` -do - PCAPNAME=`echo $i | grep pcap` - if [ -z "$PCAPNAME" ]; then - hexdump -C $i > $1/$$.tmp - text2pcap $1/$$.tmp ${i}.pcap - fi -done -for i in `ls $1/hangs/id*` -do - PCAPNAME=`echo $i | grep pcap` - if [ -z "$PCAPNAME" ]; then - hexdump -C $i > $1/$$.tmp - text2pcap $1/$$.tmp ${i}.pcap - fi -done -rm -f $1/$$.tmp - -echo -echo "Created pcap files:" -ls $1/*/*.pcap diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.c deleted file mode 100644 index 66b4877e3fb37bc7a16b0c9814d2b57aeae680b4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.c +++ /dev/null @@ -1,121 +0,0 @@ -#include "test_mem.h" - -#include "lwip/mem.h" -#include "lwip/stats.h" - -#if !LWIP_STATS || !MEM_STATS -#error "This tests needs MEM-statistics enabled" -#endif -#if LWIP_DNS -#error "This test needs DNS turned off (as it mallocs on init)" -#endif - -/* Setups/teardown functions */ - -static void -mem_setup(void) -{ -} - -static void -mem_teardown(void) -{ -} - - -/* Test functions */ - -/** Call mem_malloc, mem_free and mem_trim and check stats */ -START_TEST(test_mem_one) -{ -#define SIZE1 16 -#define SIZE1_2 12 -#define SIZE2 16 - void *p1, *p2; - mem_size_t s1, s2; - LWIP_UNUSED_ARG(_i); - - fail_unless(lwip_stats.mem.used == 0); - - p1 = mem_malloc(SIZE1); - fail_unless(p1 != NULL); - fail_unless(lwip_stats.mem.used >= SIZE1); - s1 = lwip_stats.mem.used; - - p2 = mem_malloc(SIZE2); - fail_unless(p2 != NULL); - fail_unless(lwip_stats.mem.used >= SIZE2 + s1); - s2 = lwip_stats.mem.used; - - mem_trim(p1, SIZE1_2); - - mem_free(p2); - fail_unless(lwip_stats.mem.used <= s2 - SIZE2); - - mem_free(p1); - fail_unless(lwip_stats.mem.used == 0); -} -END_TEST - -static void malloc_keep_x(int x, int num, int size, int freestep) -{ - int i; - void* p[16]; - LWIP_ASSERT("invalid size", size >= 0 && size < (mem_size_t)-1); - memset(p, 0, sizeof(p)); - for(i = 0; i < num && i < 16; i++) { - p[i] = mem_malloc((mem_size_t)size); - fail_unless(p[i] != NULL); - } - for(i = 0; i < num && i < 16; i += freestep) { - if (i == x) { - continue; - } - mem_free(p[i]); - p[i] = NULL; - } - for(i = 0; i < num && i < 16; i++) { - if (i == x) { - continue; - } - if (p[i] != NULL) { - mem_free(p[i]); - p[i] = NULL; - } - } - fail_unless(p[x] != NULL); - mem_free(p[x]); -} - -START_TEST(test_mem_random) -{ - const int num = 16; - int x; - int size; - int freestep; - LWIP_UNUSED_ARG(_i); - - fail_unless(lwip_stats.mem.used == 0); - - for (x = 0; x < num; x++) { - for (size = 1; size < 32; size++) { - for (freestep = 1; freestep <= 3; freestep++) { - fail_unless(lwip_stats.mem.used == 0); - malloc_keep_x(x, num, size, freestep); - fail_unless(lwip_stats.mem.used == 0); - } - } - } -} -END_TEST - -/** Create the suite including all tests for this module */ -Suite * -mem_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_mem_one), - TESTFUNC(test_mem_random) - }; - return create_suite("MEM", tests, sizeof(tests)/sizeof(testfunc), mem_setup, mem_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.h deleted file mode 100644 index 325134c30a5af4d52f1da629eb387037e6b18ade..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_mem.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_MEM_H -#define LWIP_HDR_TEST_MEM_H - -#include "../lwip_check.h" - -Suite *mem_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.c deleted file mode 100644 index 9315c4c635b7679493698b90cded1e03e7505f54..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.c +++ /dev/null @@ -1,239 +0,0 @@ -#include "test_pbuf.h" - -#include "lwip/pbuf.h" -#include "lwip/stats.h" - -#if !LWIP_STATS || !MEM_STATS ||!MEMP_STATS -#error "This tests needs MEM- and MEMP-statistics enabled" -#endif -#if LWIP_DNS -#error "This test needs DNS turned off (as it mallocs on init)" -#endif -#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || !LWIP_WND_SCALE -#error "This test needs TCP OOSEQ queueing and window scaling enabled" -#endif - -/* Setups/teardown functions */ - -static void -pbuf_setup(void) -{ -} - -static void -pbuf_teardown(void) -{ -} - - -#define TESTBUFSIZE_1 65535 -#define TESTBUFSIZE_2 65530 -#define TESTBUFSIZE_3 50050 -static u8_t testbuf_1[TESTBUFSIZE_1]; -static u8_t testbuf_1a[TESTBUFSIZE_1]; -static u8_t testbuf_2[TESTBUFSIZE_2]; -static u8_t testbuf_2a[TESTBUFSIZE_2]; -static u8_t testbuf_3[TESTBUFSIZE_3]; -static u8_t testbuf_3a[TESTBUFSIZE_3]; - -/* Test functions */ - -/** Call pbuf_copy on a pbuf with zero length */ -START_TEST(test_pbuf_copy_zero_pbuf) -{ - struct pbuf *p1, *p2, *p3; - err_t err; - LWIP_UNUSED_ARG(_i); - - fail_unless(lwip_stats.mem.used == 0); - fail_unless(MEMP_STATS_GET(used, MEMP_PBUF_POOL) == 0); - - p1 = pbuf_alloc(PBUF_RAW, 1024, PBUF_RAM); - fail_unless(p1 != NULL); - fail_unless(p1->ref == 1); - - p2 = pbuf_alloc(PBUF_RAW, 2, PBUF_POOL); - fail_unless(p2 != NULL); - fail_unless(p2->ref == 1); - p2->len = p2->tot_len = 0; - - pbuf_cat(p1, p2); - fail_unless(p1->ref == 1); - fail_unless(p2->ref == 1); - - p3 = pbuf_alloc(PBUF_RAW, p1->tot_len, PBUF_POOL); - err = pbuf_copy(p3, p1); - fail_unless(err == ERR_VAL); - - pbuf_free(p1); - pbuf_free(p3); - fail_unless(lwip_stats.mem.used == 0); - - fail_unless(lwip_stats.mem.used == 0); - fail_unless(MEMP_STATS_GET(used, MEMP_PBUF_POOL) == 0); -} -END_TEST - -START_TEST(test_pbuf_split_64k_on_small_pbufs) -{ - struct pbuf *p, *rest=NULL; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, 1, PBUF_POOL); - pbuf_split_64k(p, &rest); - fail_unless(p->tot_len == 1); - pbuf_free(p); -} -END_TEST - -START_TEST(test_pbuf_queueing_bigger_than_64k) -{ - int i; - err_t err; - struct pbuf *p1, *p2, *p3, *rest2=NULL, *rest3=NULL; - LWIP_UNUSED_ARG(_i); - - for(i = 0; i < TESTBUFSIZE_1; i++) { - testbuf_1[i] = (u8_t)rand(); - } - for(i = 0; i < TESTBUFSIZE_2; i++) { - testbuf_2[i] = (u8_t)rand(); - } - for(i = 0; i < TESTBUFSIZE_3; i++) { - testbuf_3[i] = (u8_t)rand(); - } - - p1 = pbuf_alloc(PBUF_RAW, TESTBUFSIZE_1, PBUF_POOL); - fail_unless(p1 != NULL); - p2 = pbuf_alloc(PBUF_RAW, TESTBUFSIZE_2, PBUF_POOL); - fail_unless(p2 != NULL); - p3 = pbuf_alloc(PBUF_RAW, TESTBUFSIZE_3, PBUF_POOL); - fail_unless(p3 != NULL); - err = pbuf_take(p1, testbuf_1, TESTBUFSIZE_1); - fail_unless(err == ERR_OK); - err = pbuf_take(p2, testbuf_2, TESTBUFSIZE_2); - fail_unless(err == ERR_OK); - err = pbuf_take(p3, testbuf_3, TESTBUFSIZE_3); - fail_unless(err == ERR_OK); - - pbuf_cat(p1, p2); - pbuf_cat(p1, p3); - - pbuf_split_64k(p1, &rest2); - fail_unless(p1->tot_len == TESTBUFSIZE_1); - fail_unless(rest2->tot_len == (u16_t)((TESTBUFSIZE_2+TESTBUFSIZE_3) & 0xFFFF)); - pbuf_split_64k(rest2, &rest3); - fail_unless(rest2->tot_len == TESTBUFSIZE_2); - fail_unless(rest3->tot_len == TESTBUFSIZE_3); - - pbuf_copy_partial(p1, testbuf_1a, TESTBUFSIZE_1, 0); - pbuf_copy_partial(rest2, testbuf_2a, TESTBUFSIZE_2, 0); - pbuf_copy_partial(rest3, testbuf_3a, TESTBUFSIZE_3, 0); - for(i = 0; i < TESTBUFSIZE_1; i++) - fail_unless(testbuf_1[i] == testbuf_1a[i]); - for(i = 0; i < TESTBUFSIZE_2; i++) - fail_unless(testbuf_2[i] == testbuf_2a[i]); - for(i = 0; i < TESTBUFSIZE_3; i++) - fail_unless(testbuf_3[i] == testbuf_3a[i]); - - pbuf_free(p1); - pbuf_free(rest2); - pbuf_free(rest3); -} -END_TEST - -/* Test for bug that writing with pbuf_take_at() did nothing - * and returned ERR_OK when writing at beginning of a pbuf - * in the chain. - */ -START_TEST(test_pbuf_take_at_edge) -{ - err_t res; - u8_t *out; - int i; - u8_t testdata[] = { 0x01, 0x08, 0x82, 0x02 }; - struct pbuf *p = pbuf_alloc(PBUF_RAW, 1024, PBUF_POOL); - struct pbuf *q = p->next; - LWIP_UNUSED_ARG(_i); - /* alloc big enough to get a chain of pbufs */ - fail_if(p->tot_len == p->len); - memset(p->payload, 0, p->len); - memset(q->payload, 0, q->len); - - /* copy data to the beginning of first pbuf */ - res = pbuf_take_at(p, &testdata, sizeof(testdata), 0); - fail_unless(res == ERR_OK); - - out = (u8_t*)p->payload; - for (i = 0; i < (int)sizeof(testdata); i++) { - fail_unless(out[i] == testdata[i], - "Bad data at pos %d, was %02X, expected %02X", i, out[i], testdata[i]); - } - - /* copy data to the just before end of first pbuf */ - res = pbuf_take_at(p, &testdata, sizeof(testdata), p->len - 1); - fail_unless(res == ERR_OK); - - out = (u8_t*)p->payload; - fail_unless(out[p->len - 1] == testdata[0], - "Bad data at pos %d, was %02X, expected %02X", p->len - 1, out[p->len - 1], testdata[0]); - out = (u8_t*)q->payload; - for (i = 1; i < (int)sizeof(testdata); i++) { - fail_unless(out[i-1] == testdata[i], - "Bad data at pos %d, was %02X, expected %02X", p->len - 1 + i, out[i-1], testdata[i]); - } - - /* copy data to the beginning of second pbuf */ - res = pbuf_take_at(p, &testdata, sizeof(testdata), p->len); - fail_unless(res == ERR_OK); - - out = (u8_t*)p->payload; - for (i = 0; i < (int)sizeof(testdata); i++) { - fail_unless(out[i] == testdata[i], - "Bad data at pos %d, was %02X, expected %02X", p->len+i, out[i], testdata[i]); - } -} -END_TEST - -/* Verify pbuf_put_at()/pbuf_get_at() when using - * offsets equal to beginning of new pbuf in chain - */ -START_TEST(test_pbuf_get_put_at_edge) -{ - u8_t *out; - u8_t testdata = 0x01; - u8_t getdata; - struct pbuf *p = pbuf_alloc(PBUF_RAW, 1024, PBUF_POOL); - struct pbuf *q = p->next; - LWIP_UNUSED_ARG(_i); - /* alloc big enough to get a chain of pbufs */ - fail_if(p->tot_len == p->len); - memset(p->payload, 0, p->len); - memset(q->payload, 0, q->len); - - /* put byte at the beginning of second pbuf */ - pbuf_put_at(p, p->len, testdata); - - out = (u8_t*)q->payload; - fail_unless(*out == testdata, - "Bad data at pos %d, was %02X, expected %02X", p->len, *out, testdata); - - getdata = pbuf_get_at(p, p->len); - fail_unless(*out == getdata, - "pbuf_get_at() returned bad data at pos %d, was %02X, expected %02X", p->len, getdata, *out); -} -END_TEST - -/** Create the suite including all tests for this module */ -Suite * -pbuf_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_pbuf_copy_zero_pbuf), - TESTFUNC(test_pbuf_split_64k_on_small_pbufs), - TESTFUNC(test_pbuf_queueing_bigger_than_64k), - TESTFUNC(test_pbuf_take_at_edge), - TESTFUNC(test_pbuf_get_put_at_edge) - }; - return create_suite("PBUF", tests, sizeof(tests)/sizeof(testfunc), pbuf_setup, pbuf_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.h deleted file mode 100644 index da7730a4c8598f1fe1abf30d10b46ae1fce26fff..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/core/test_pbuf.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_PBUF_H -#define LWIP_HDR_TEST_PBUF_H - -#include "../lwip_check.h" - -Suite *pbuf_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.c deleted file mode 100644 index dd17c6044dd36ffcf201956bd3ce4b90cdee18f4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.c +++ /dev/null @@ -1,1024 +0,0 @@ -#include "test_dhcp.h" - -#include "lwip/netif.h" -#include "lwip/dhcp.h" -#include "lwip/prot/dhcp.h" -#include "lwip/etharp.h" -#include "netif/ethernet.h" - -struct netif net_test; - -static const u8_t broadcast[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; - -static const u8_t magic_cookie[] = { 0x63, 0x82, 0x53, 0x63 }; - -static u8_t dhcp_offer[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* To unit */ - 0x00, 0x0F, 0xEE, 0x30, 0xAB, 0x22, /* From Remote host */ - 0x08, 0x00, /* Protocol: IP */ - 0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x36, 0xcc, 0xc3, 0xaa, 0xbd, 0xab, 0xc3, 0xaa, 0xbd, 0xc8, /* IP header */ - 0x00, 0x43, 0x00, 0x44, 0x01, 0x34, 0x00, 0x00, /* UDP header */ - - 0x02, /* Type == Boot reply */ - 0x01, 0x06, /* Hw Ethernet, 6 bytes addrlen */ - 0x00, /* 0 hops */ - 0xAA, 0xAA, 0xAA, 0xAA, /* Transaction id, will be overwritten */ - 0x00, 0x00, /* 0 seconds elapsed */ - 0x00, 0x00, /* Flags (unicast) */ - 0x00, 0x00, 0x00, 0x00, /* Client ip */ - 0xc3, 0xaa, 0xbd, 0xc8, /* Your IP */ - 0xc3, 0xaa, 0xbd, 0xab, /* DHCP server ip */ - 0x00, 0x00, 0x00, 0x00, /* relay agent */ - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MAC addr + padding */ - - /* Empty server name and boot file name */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x63, 0x82, 0x53, 0x63, /* Magic cookie */ - 0x35, 0x01, 0x02, /* Message type: Offer */ - 0x36, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* Server identifier (IP) */ - 0x33, 0x04, 0x00, 0x00, 0x00, 0x78, /* Lease time 2 minutes */ - 0x03, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* Router IP */ - 0x01, 0x04, 0xff, 0xff, 0xff, 0x00, /* Subnet mask */ - 0xff, /* End option */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Padding */ -}; - -static u8_t dhcp_ack[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* To unit */ - 0x00, 0x0f, 0xEE, 0x30, 0xAB, 0x22, /* From remote host */ - 0x08, 0x00, /* Proto IP */ - 0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x36, 0xcc, 0xc3, 0xaa, 0xbd, 0xab, 0xc3, 0xaa, 0xbd, 0xc8, /* IP header */ - 0x00, 0x43, 0x00, 0x44, 0x01, 0x34, 0x00, 0x00, /* UDP header */ - 0x02, /* Bootp reply */ - 0x01, 0x06, /* Hw type Eth, len 6 */ - 0x00, /* 0 hops */ - 0xAA, 0xAA, 0xAA, 0xAA, - 0x00, 0x00, /* 0 seconds elapsed */ - 0x00, 0x00, /* Flags (unicast) */ - 0x00, 0x00, 0x00, 0x00, /* Client IP */ - 0xc3, 0xaa, 0xbd, 0xc8, /* Your IP */ - 0xc3, 0xaa, 0xbd, 0xab, /* DHCP server IP */ - 0x00, 0x00, 0x00, 0x00, /* Relay agent */ - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Macaddr + padding */ - - /* Empty server name and boot file name */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x63, 0x82, 0x53, 0x63, /* Magic cookie */ - 0x35, 0x01, 0x05, /* Dhcp message type ack */ - 0x36, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* DHCP server identifier */ - 0x33, 0x04, 0x00, 0x00, 0x00, 0x78, /* Lease time 2 minutes */ - 0x03, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* Router IP */ - 0x01, 0x04, 0xff, 0xff, 0xff, 0x00, /* Netmask */ - 0xff, /* End marker */ - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Padding */ -}; - -static const u8_t arpreply[] = { - 0x00, 0x23, 0xC1, 0xDE, 0xD0, 0x0D, /* dst mac */ - 0x00, 0x32, 0x44, 0x20, 0x01, 0x02, /* src mac */ - 0x08, 0x06, /* proto arp */ - 0x00, 0x01, /* hw eth */ - 0x08, 0x00, /* proto ip */ - 0x06, /* hw addr len 6 */ - 0x04, /* proto addr len 4 */ - 0x00, 0x02, /* arp reply */ - 0x00, 0x32, 0x44, 0x20, 0x01, 0x02, /* sender mac */ - 0xc3, 0xaa, 0xbd, 0xc8, /* sender ip */ - 0x00, 0x23, 0xC1, 0xDE, 0xD0, 0x0D, /* target mac */ - 0x00, 0x00, 0x00, 0x00, /* target ip */ -}; - -static int txpacket; -static enum tcase { - TEST_LWIP_DHCP, - TEST_LWIP_DHCP_NAK, - TEST_LWIP_DHCP_RELAY, - TEST_LWIP_DHCP_NAK_NO_ENDMARKER, - TEST_LWIP_DHCP_INVALID_OVERLOAD -} tcase; - -static int debug = 0; -static void setdebug(int a) {debug = a;} - -static int tick = 0; -static void tick_lwip(void) -{ - tick++; - if (tick % 5 == 0) { - dhcp_fine_tmr(); - } - if (tick % 600 == 0) { - dhcp_coarse_tmr(); - } -} - -static void send_pkt(struct netif *netif, const u8_t *data, size_t len) -{ - struct pbuf *p, *q; - LWIP_ASSERT("pkt too big", len <= 0xFFFF); - p = pbuf_alloc(PBUF_RAW, (u16_t)len, PBUF_POOL); - - if (debug) { - /* Dump data */ - u32_t i; - os_printf("RX data (len %d)", p->tot_len); - for (i = 0; i < len; i++) { - os_printf(" %02X", data[i]); - } - os_printf("\n"); - } - - fail_unless(p != NULL); - for(q = p; q != NULL; q = q->next) { - memcpy(q->payload, data, q->len); - data += q->len; - } - netif->input(p, netif); -} - -static err_t lwip_tx_func(struct netif *netif, struct pbuf *p); - -static err_t testif_init(struct netif *netif) -{ - netif->name[0] = 'c'; - netif->name[1] = 'h'; - netif->output = etharp_output; - netif->linkoutput = lwip_tx_func; - netif->mtu = 1500; - netif->hwaddr_len = 6; - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - netif->hwaddr[0] = 0x00; - netif->hwaddr[1] = 0x23; - netif->hwaddr[2] = 0xC1; - netif->hwaddr[3] = 0xDE; - netif->hwaddr[4] = 0xD0; - netif->hwaddr[5] = 0x0D; - - return ERR_OK; -} - -static void dhcp_setup(void) -{ - txpacket = 0; -} - -static void dhcp_teardown(void) -{ -} - -static void check_pkt(struct pbuf *p, u32_t pos, const u8_t *mem, u32_t len) -{ - u8_t *data; - - fail_if((pos + len) > p->tot_len); - while (pos > p->len && p->next) { - pos -= p->len; - p = p->next; - } - fail_if(p == NULL); - fail_unless(pos + len <= p->len); /* All data we seek within same pbuf */ - - data = (u8_t*)p->payload; - fail_if(memcmp(&data[pos], mem, len), "data at pos %d, len %d in packet %d did not match", pos, len, txpacket); -} - -static void check_pkt_fuzzy(struct pbuf *p, u32_t startpos, const u8_t *mem, u32_t len) -{ - int found; - u32_t i; - u8_t *data; - - fail_if((startpos + len) > p->tot_len); - while (startpos > p->len && p->next) { - startpos -= p->len; - p = p->next; - } - fail_if(p == NULL); - fail_unless(startpos + len <= p->len); /* All data we seek within same pbuf */ - - found = 0; - data = (u8_t*)p->payload; - for (i = startpos; i <= (p->len - len); i++) { - if (memcmp(&data[i], mem, len) == 0) { - found = 1; - break; - } - } - fail_unless(found); -} - -static err_t lwip_tx_func(struct netif *netif, struct pbuf *p) -{ - fail_unless(netif == &net_test); - txpacket++; - - if (debug) { - struct pbuf *pp = p; - /* Dump data */ - os_printf("TX data (pkt %d, len %d, tick %d)", txpacket, p->tot_len, tick); - do { - int i; - for (i = 0; i < pp->len; i++) { - os_printf(" %02X", ((u8_t *) pp->payload)[i]); - } - if (pp->next) { - pp = pp->next; - } - } while (pp->next); - os_printf("\n"); - } - - switch (tcase) { - case TEST_LWIP_DHCP: - switch (txpacket) { - case 1: - case 2: - { - const u8_t ipproto[] = { 0x08, 0x00 }; - const u8_t bootp_start[] = { 0x01, 0x01, 0x06, 0x00}; /* bootp request, eth, hwaddr len 6, 0 hops */ - const u8_t ipaddrs[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - check_pkt(p, 0, broadcast, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, ipproto, sizeof(ipproto)); /* eth level proto: ip */ - - check_pkt(p, 42, bootp_start, sizeof(bootp_start)); - - check_pkt(p, 53, ipaddrs, sizeof(ipaddrs)); - - check_pkt(p, 70, netif->hwaddr, 6); /* mac addr inside bootp */ - - check_pkt(p, 278, magic_cookie, sizeof(magic_cookie)); - - /* Check dchp message type, can be at different positions */ - if (txpacket == 1) { - u8_t dhcp_discover_opt[] = { 0x35, 0x01, 0x01 }; - check_pkt_fuzzy(p, 282, dhcp_discover_opt, sizeof(dhcp_discover_opt)); - } else if (txpacket == 2) { - u8_t dhcp_request_opt[] = { 0x35, 0x01, 0x03 }; - u8_t requested_ipaddr[] = { 0x32, 0x04, 0xc3, 0xaa, 0xbd, 0xc8 }; /* Ask for offered IP */ - - check_pkt_fuzzy(p, 282, dhcp_request_opt, sizeof(dhcp_request_opt)); - check_pkt_fuzzy(p, 282, requested_ipaddr, sizeof(requested_ipaddr)); - } - break; - } - case 3: - case 4: - case 5: - { - const u8_t arpproto[] = { 0x08, 0x06 }; - - check_pkt(p, 0, broadcast, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, arpproto, sizeof(arpproto)); /* eth level proto: ip */ - break; - } - default: - fail(); - break; - } - break; - - case TEST_LWIP_DHCP_NAK: - { - const u8_t ipproto[] = { 0x08, 0x00 }; - const u8_t bootp_start[] = { 0x01, 0x01, 0x06, 0x00}; /* bootp request, eth, hwaddr len 6, 0 hops */ - const u8_t ipaddrs[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - const u8_t dhcp_nak_opt[] = { 0x35, 0x01, 0x04 }; - const u8_t requested_ipaddr[] = { 0x32, 0x04, 0xc3, 0xaa, 0xbd, 0xc8 }; /* offered IP */ - - fail_unless(txpacket == 4); - check_pkt(p, 0, broadcast, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, ipproto, sizeof(ipproto)); /* eth level proto: ip */ - - check_pkt(p, 42, bootp_start, sizeof(bootp_start)); - - check_pkt(p, 53, ipaddrs, sizeof(ipaddrs)); - - check_pkt(p, 70, netif->hwaddr, 6); /* mac addr inside bootp */ - - check_pkt(p, 278, magic_cookie, sizeof(magic_cookie)); - - check_pkt_fuzzy(p, 282, dhcp_nak_opt, sizeof(dhcp_nak_opt)); /* NAK the ack */ - - check_pkt_fuzzy(p, 282, requested_ipaddr, sizeof(requested_ipaddr)); - break; - } - - case TEST_LWIP_DHCP_RELAY: - switch (txpacket) { - case 1: - case 2: - { - const u8_t ipproto[] = { 0x08, 0x00 }; - const u8_t bootp_start[] = { 0x01, 0x01, 0x06, 0x00}; /* bootp request, eth, hwaddr len 6, 0 hops */ - const u8_t ipaddrs[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - check_pkt(p, 0, broadcast, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, ipproto, sizeof(ipproto)); /* eth level proto: ip */ - - check_pkt(p, 42, bootp_start, sizeof(bootp_start)); - - check_pkt(p, 53, ipaddrs, sizeof(ipaddrs)); - - check_pkt(p, 70, netif->hwaddr, 6); /* mac addr inside bootp */ - - check_pkt(p, 278, magic_cookie, sizeof(magic_cookie)); - - /* Check dchp message type, can be at different positions */ - if (txpacket == 1) { - u8_t dhcp_discover_opt[] = { 0x35, 0x01, 0x01 }; - check_pkt_fuzzy(p, 282, dhcp_discover_opt, sizeof(dhcp_discover_opt)); - } else if (txpacket == 2) { - u8_t dhcp_request_opt[] = { 0x35, 0x01, 0x03 }; - u8_t requested_ipaddr[] = { 0x32, 0x04, 0x4f, 0x8a, 0x33, 0x05 }; /* Ask for offered IP */ - - check_pkt_fuzzy(p, 282, dhcp_request_opt, sizeof(dhcp_request_opt)); - check_pkt_fuzzy(p, 282, requested_ipaddr, sizeof(requested_ipaddr)); - } - break; - } - case 3: - case 4: - case 5: - case 6: - { - const u8_t arpproto[] = { 0x08, 0x06 }; - - check_pkt(p, 0, broadcast, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, arpproto, sizeof(arpproto)); /* eth level proto: ip */ - break; - } - case 7: - { - const u8_t fake_arp[6] = { 0x12, 0x34, 0x56, 0x78, 0x9a, 0xab }; - const u8_t ipproto[] = { 0x08, 0x00 }; - const u8_t bootp_start[] = { 0x01, 0x01, 0x06, 0x00}; /* bootp request, eth, hwaddr len 6, 0 hops */ - const u8_t ipaddrs[] = { 0x00, 0x4f, 0x8a, 0x33, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - const u8_t dhcp_request_opt[] = { 0x35, 0x01, 0x03 }; - - check_pkt(p, 0, fake_arp, 6); /* eth level dest: broadcast */ - check_pkt(p, 6, netif->hwaddr, 6); /* eth level src: unit mac */ - - check_pkt(p, 12, ipproto, sizeof(ipproto)); /* eth level proto: ip */ - - check_pkt(p, 42, bootp_start, sizeof(bootp_start)); - - check_pkt(p, 53, ipaddrs, sizeof(ipaddrs)); - - check_pkt(p, 70, netif->hwaddr, 6); /* mac addr inside bootp */ - - check_pkt(p, 278, magic_cookie, sizeof(magic_cookie)); - - /* Check dchp message type, can be at different positions */ - check_pkt_fuzzy(p, 282, dhcp_request_opt, sizeof(dhcp_request_opt)); - break; - } - default: - fail(); - break; - } - break; - - default: - break; - } - - return ERR_OK; -} - -/* - * Test basic happy flow DHCP session. - * Validate that xid is checked. - */ -START_TEST(test_dhcp) -{ - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - int i; - u32_t xid; - LWIP_UNUSED_ARG(_i); - - tcase = TEST_LWIP_DHCP; - setdebug(0); - - IP4_ADDR(&addr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 0, 0, 0, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - - dhcp_start(&net_test); - - fail_unless(txpacket == 1); /* DHCP discover sent */ - xid = netif_dhcp_data(&net_test)->xid; /* Write bad xid, not using htonl! */ - memcpy(&dhcp_offer[46], &xid, 4); - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - fail_unless(txpacket == 1, "TX %d packets, expected 1", txpacket); /* Nothing more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); - memcpy(&dhcp_offer[46], &xid, 4); /* insert correct transaction id */ - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - fail_unless(txpacket == 2, "TX %d packets, expected 2", txpacket); /* DHCP request sent */ - xid = netif_dhcp_data(&net_test)->xid; /* Write bad xid, not using htonl! */ - memcpy(&dhcp_ack[46], &xid, 4); - send_pkt(&net_test, dhcp_ack, sizeof(dhcp_ack)); - - fail_unless(txpacket == 2, "TX %d packets, still expected 2", txpacket); /* No more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - memcpy(&dhcp_ack[46], &xid, 4); /* insert transaction id */ - send_pkt(&net_test, dhcp_ack, sizeof(dhcp_ack)); - - for (i = 0; i < 20; i++) { - tick_lwip(); - } - fail_unless(txpacket == 5, "TX %d packets, expected 5", txpacket); /* ARP requests sent */ - - /* Interface up */ - fail_unless(netif_is_up(&net_test)); - - /* Now it should have taken the IP */ - IP4_ADDR(&addr, 195, 170, 189, 200); - IP4_ADDR(&netmask, 255, 255, 255, 0); - IP4_ADDR(&gw, 195, 170, 189, 171); - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - netif_remove(&net_test); -} -END_TEST - -/* - * Test that IP address is not taken and NAK is sent if someone - * replies to ARP requests for the offered address. - */ -START_TEST(test_dhcp_nak) -{ - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - u32_t xid; - LWIP_UNUSED_ARG(_i); - - tcase = TEST_LWIP_DHCP; - setdebug(0); - - IP4_ADDR(&addr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 0, 0, 0, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - - dhcp_start(&net_test); - - fail_unless(txpacket == 1); /* DHCP discover sent */ - xid = netif_dhcp_data(&net_test)->xid; /* Write bad xid, not using htonl! */ - memcpy(&dhcp_offer[46], &xid, 4); - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - fail_unless(txpacket == 1); /* Nothing more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); - memcpy(&dhcp_offer[46], &xid, 4); /* insert correct transaction id */ - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - fail_unless(txpacket == 2); /* DHCP request sent */ - xid = netif_dhcp_data(&net_test)->xid; /* Write bad xid, not using htonl! */ - memcpy(&dhcp_ack[46], &xid, 4); - send_pkt(&net_test, dhcp_ack, sizeof(dhcp_ack)); - - fail_unless(txpacket == 2); /* No more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - memcpy(&dhcp_ack[46], &xid, 4); /* insert transaction id */ - send_pkt(&net_test, dhcp_ack, sizeof(dhcp_ack)); - - fail_unless(txpacket == 3); /* ARP request sent */ - - tcase = TEST_LWIP_DHCP_NAK; /* Switch testcase */ - - /* Send arp reply, mark offered IP as taken */ - send_pkt(&net_test, arpreply, sizeof(arpreply)); - - fail_unless(txpacket == 4); /* DHCP nak sent */ - - netif_remove(&net_test); -} -END_TEST - -/* - * Test case based on captured data where - * replies are sent from a different IP than the - * one the client unicasted to. - */ -START_TEST(test_dhcp_relayed) -{ - u8_t relay_offer[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, - 0x00, 0x22, 0x93, 0x5a, 0xf7, 0x60, - 0x08, 0x00, 0x45, 0x00, - 0x01, 0x38, 0xfd, 0x53, 0x00, 0x00, 0x40, 0x11, - 0x78, 0x46, 0x4f, 0x8a, 0x32, 0x02, 0x4f, 0x8a, - 0x33, 0x05, 0x00, 0x43, 0x00, 0x44, 0x01, 0x24, - 0x00, 0x00, 0x02, 0x01, 0x06, 0x00, 0x51, 0x35, - 0xb6, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x4f, 0x8a, 0x33, 0x05, 0x00, 0x00, - 0x00, 0x00, 0x0a, 0xb5, 0x04, 0x01, 0x00, 0x23, - 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, - 0x53, 0x63, 0x01, 0x04, 0xff, 0xff, 0xfe, 0x00, - 0x03, 0x04, 0x4f, 0x8a, 0x32, 0x01, 0x06, 0x08, - 0x4f, 0x8a, 0x00, 0xb4, 0x55, 0x08, 0x1f, 0xd1, - 0x1c, 0x04, 0x4f, 0x8a, 0x33, 0xff, 0x33, 0x04, - 0x00, 0x00, 0x54, 0x49, 0x35, 0x01, 0x02, 0x36, - 0x04, 0x0a, 0xb5, 0x04, 0x01, 0xff - }; - - u8_t relay_ack1[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x22, - 0x93, 0x5a, 0xf7, 0x60, 0x08, 0x00, 0x45, 0x00, - 0x01, 0x38, 0xfd, 0x55, 0x00, 0x00, 0x40, 0x11, - 0x78, 0x44, 0x4f, 0x8a, 0x32, 0x02, 0x4f, 0x8a, - 0x33, 0x05, 0x00, 0x43, 0x00, 0x44, 0x01, 0x24, - 0x00, 0x00, 0x02, 0x01, 0x06, 0x00, 0x51, 0x35, - 0xb6, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x4f, 0x8a, 0x33, 0x05, 0x00, 0x00, - 0x00, 0x00, 0x0a, 0xb5, 0x04, 0x01, 0x00, 0x23, - 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, - 0x53, 0x63, 0x01, 0x04, 0xff, 0xff, 0xfe, 0x00, - 0x03, 0x04, 0x4f, 0x8a, 0x32, 0x01, 0x06, 0x08, - 0x4f, 0x8a, 0x00, 0xb4, 0x55, 0x08, 0x1f, 0xd1, - 0x1c, 0x04, 0x4f, 0x8a, 0x33, 0xff, 0x33, 0x04, - 0x00, 0x00, 0x54, 0x49, 0x35, 0x01, 0x05, 0x36, - 0x04, 0x0a, 0xb5, 0x04, 0x01, 0xff - }; - - u8_t relay_ack2[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, - 0x00, 0x22, 0x93, 0x5a, 0xf7, 0x60, - 0x08, 0x00, 0x45, 0x00, - 0x01, 0x38, 0xfa, 0x18, 0x00, 0x00, 0x40, 0x11, - 0x7b, 0x81, 0x4f, 0x8a, 0x32, 0x02, 0x4f, 0x8a, - 0x33, 0x05, 0x00, 0x43, 0x00, 0x44, 0x01, 0x24, - 0x00, 0x00, 0x02, 0x01, 0x06, 0x00, 0x49, 0x8b, - 0x6e, 0xab, 0x00, 0x00, 0x00, 0x00, 0x4f, 0x8a, - 0x33, 0x05, 0x4f, 0x8a, 0x33, 0x05, 0x00, 0x00, - 0x00, 0x00, 0x0a, 0xb5, 0x04, 0x01, 0x00, 0x23, - 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, - 0x53, 0x63, 0x01, 0x04, 0xff, 0xff, 0xfe, 0x00, - 0x03, 0x04, 0x4f, 0x8a, 0x32, 0x01, 0x06, 0x08, - 0x4f, 0x8a, 0x00, 0xb4, 0x55, 0x08, 0x1f, 0xd1, - 0x1c, 0x04, 0x4f, 0x8a, 0x33, 0xff, 0x33, 0x04, - 0x00, 0x00, 0x54, 0x60, 0x35, 0x01, 0x05, 0x36, - 0x04, 0x0a, 0xb5, 0x04, 0x01, 0xff }; - - const u8_t arp_resp[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* DEST */ - 0x00, 0x22, 0x93, 0x5a, 0xf7, 0x60, /* SRC */ - 0x08, 0x06, /* Type: ARP */ - 0x00, 0x01, /* HW: Ethernet */ - 0x08, 0x00, /* PROTO: IP */ - 0x06, /* HW size */ - 0x04, /* PROTO size */ - 0x00, 0x02, /* OPCODE: Reply */ - - 0x12, 0x34, 0x56, 0x78, 0x9a, 0xab, /* Target MAC */ - 0x4f, 0x8a, 0x32, 0x01, /* Target IP */ - - 0x00, 0x23, 0xc1, 0x00, 0x06, 0x50, /* src mac */ - 0x4f, 0x8a, 0x33, 0x05, /* src ip */ - - /* Padding follows.. */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 }; - - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - int i; - u32_t xid; - LWIP_UNUSED_ARG(_i); - - tcase = TEST_LWIP_DHCP_RELAY; - setdebug(0); - - IP4_ADDR(&addr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 0, 0, 0, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - - dhcp_start(&net_test); - - fail_unless(txpacket == 1); /* DHCP discover sent */ - - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - fail_unless(txpacket == 1); /* Nothing more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); - memcpy(&relay_offer[46], &xid, 4); /* insert correct transaction id */ - send_pkt(&net_test, relay_offer, sizeof(relay_offer)); - - /* request sent? */ - fail_unless(txpacket == 2, "txpkt = %d, should be 2", txpacket); - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - memcpy(&relay_ack1[46], &xid, 4); /* insert transaction id */ - send_pkt(&net_test, relay_ack1, sizeof(relay_ack1)); - - for (i = 0; i < 25; i++) { - tick_lwip(); - } - fail_unless(txpacket == 5, "txpkt should be 5, is %d", txpacket); /* ARP requests sent */ - - /* Interface up */ - fail_unless(netif_is_up(&net_test)); - - /* Now it should have taken the IP */ - IP4_ADDR(&addr, 79, 138, 51, 5); - IP4_ADDR(&netmask, 255, 255, 254, 0); - IP4_ADDR(&gw, 79, 138, 50, 1); - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - fail_unless(txpacket == 5, "txpacket = %d", txpacket); - - for (i = 0; i < 108000 - 25; i++) { - tick_lwip(); - } - - fail_unless(netif_is_up(&net_test)); - fail_unless(txpacket == 6, "txpacket = %d", txpacket); - - /* We need to send arp response here.. */ - - send_pkt(&net_test, arp_resp, sizeof(arp_resp)); - - fail_unless(txpacket == 7, "txpacket = %d", txpacket); - fail_unless(netif_is_up(&net_test)); - - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - memcpy(&relay_ack2[46], &xid, 4); /* insert transaction id */ - send_pkt(&net_test, relay_ack2, sizeof(relay_ack2)); - - for (i = 0; i < 100000; i++) { - tick_lwip(); - } - - fail_unless(txpacket == 7, "txpacket = %d", txpacket); - - netif_remove(&net_test); - -} -END_TEST - -START_TEST(test_dhcp_nak_no_endmarker) -{ - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - - u8_t dhcp_nack_no_endmarker[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x54, 0x75, - 0xd0, 0x26, 0xd0, 0x0d, 0x08, 0x00, 0x45, 0x00, - 0x01, 0x15, 0x38, 0x86, 0x00, 0x00, 0xff, 0x11, - 0xc0, 0xa8, 0xc0, 0xa8, 0x01, 0x01, 0xff, 0xff, - 0xff, 0xff, 0x00, 0x43, 0x00, 0x44, 0x01, 0x01, - 0x00, 0x00, 0x02, 0x01, 0x06, 0x00, 0x7a, 0xcb, - 0xba, 0xf2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, - 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, - 0x53, 0x63, 0x35, 0x01, 0x06, 0x36, 0x04, 0xc0, - 0xa8, 0x01, 0x01, 0x31, 0xef, 0xad, 0x72, 0x31, - 0x43, 0x4e, 0x44, 0x30, 0x32, 0x35, 0x30, 0x43, - 0x52, 0x47, 0x44, 0x38, 0x35, 0x36, 0x3c, 0x08, - 0x4d, 0x53, 0x46, 0x54, 0x20, 0x35, 0x2e, 0x30, - 0x37, 0x0d, 0x01, 0x0f, 0x03, 0x06, 0x2c, 0x2e, - 0x2f, 0x1f, 0x21, 0x79, 0xf9, 0x2b, 0xfc, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x71, - 0xf3, 0x5b, 0xe2, 0x71, 0x2e, 0x01, 0x08, 0x03, - 0x04, 0xc0, 0xa8, 0x01, 0x01, 0xff, 0xeb, 0x1e, - 0x44, 0xec, 0xeb, 0x1e, 0x30, 0x37, 0x0c, 0x01, - 0x0f, 0x03, 0x06, 0x2c, 0x2e, 0x2f, 0x1f, 0x21, - 0x79, 0xf9, 0x2b, 0xff, 0x25, 0xc0, 0x09, 0xd6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - }; - u32_t xid; - LWIP_UNUSED_ARG(_i); - - tcase = TEST_LWIP_DHCP_NAK_NO_ENDMARKER; - setdebug(0); - - IP4_ADDR(&addr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 0, 0, 0, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - - dhcp_start(&net_test); - - fail_unless(txpacket == 1); /* DHCP discover sent */ - xid = netif_dhcp_data(&net_test)->xid; /* Write bad xid, not using htonl! */ - memcpy(&dhcp_offer[46], &xid, 4); - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - - fail_unless(txpacket == 1); /* Nothing more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); - memcpy(&dhcp_offer[46], &xid, 4); /* insert correct transaction id */ - send_pkt(&net_test, dhcp_offer, sizeof(dhcp_offer)); - - fail_unless(netif_dhcp_data(&net_test)->state == DHCP_STATE_REQUESTING); - - fail_unless(txpacket == 2); /* No more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - memcpy(&dhcp_nack_no_endmarker[46], &xid, 4); /* insert transaction id */ - send_pkt(&net_test, dhcp_nack_no_endmarker, sizeof(dhcp_nack_no_endmarker)); - - /* NAK should put us in another state for a while, no other way detecting it */ - fail_unless(netif_dhcp_data(&net_test)->state != DHCP_STATE_REQUESTING); - - netif_remove(&net_test); -} -END_TEST - -START_TEST(test_dhcp_invalid_overload) -{ - u8_t dhcp_offer_invalid_overload[] = { - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* To unit */ - 0x00, 0x0F, 0xEE, 0x30, 0xAB, 0x22, /* From Remote host */ - 0x08, 0x00, /* Protocol: IP */ - 0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x36, 0xcc, 0xc3, 0xaa, 0xbd, 0xab, 0xc3, 0xaa, 0xbd, 0xc8, /* IP header */ - 0x00, 0x43, 0x00, 0x44, 0x01, 0x34, 0x00, 0x00, /* UDP header */ - - 0x02, /* Type == Boot reply */ - 0x01, 0x06, /* Hw Ethernet, 6 bytes addrlen */ - 0x00, /* 0 hops */ - 0xAA, 0xAA, 0xAA, 0xAA, /* Transaction id, will be overwritten */ - 0x00, 0x00, /* 0 seconds elapsed */ - 0x00, 0x00, /* Flags (unicast) */ - 0x00, 0x00, 0x00, 0x00, /* Client ip */ - 0xc3, 0xaa, 0xbd, 0xc8, /* Your IP */ - 0xc3, 0xaa, 0xbd, 0xab, /* DHCP server ip */ - 0x00, 0x00, 0x00, 0x00, /* relay agent */ - 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MAC addr + padding */ - - /* Empty server name */ - 0x34, 0x01, 0x02, 0xff, /* Overload: SNAME + END */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* Empty boot file name */ - 0x34, 0x01, 0x01, 0xff, /* Overload FILE + END */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x63, 0x82, 0x53, 0x63, /* Magic cookie */ - 0x35, 0x01, 0x02, /* Message type: Offer */ - 0x36, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* Server identifier (IP) */ - 0x33, 0x04, 0x00, 0x00, 0x00, 0x78, /* Lease time 2 minutes */ - 0x03, 0x04, 0xc3, 0xaa, 0xbd, 0xab, /* Router IP */ - 0x01, 0x04, 0xff, 0xff, 0xff, 0x00, /* Subnet mask */ - 0x34, 0x01, 0x03, /* Overload: FILE + SNAME */ - 0xff, /* End option */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Padding */ - }; - ip4_addr_t addr; - ip4_addr_t netmask; - ip4_addr_t gw; - u32_t xid; - LWIP_UNUSED_ARG(_i); - - tcase = TEST_LWIP_DHCP_INVALID_OVERLOAD; - setdebug(0); - - IP4_ADDR(&addr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 0, 0, 0, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_add(&net_test, &addr, &netmask, &gw, &net_test, testif_init, ethernet_input); - netif_set_up(&net_test); - - dhcp_start(&net_test); - - fail_unless(txpacket == 1); /* DHCP discover sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); - memcpy(&dhcp_offer_invalid_overload[46], &xid, 4); /* insert correct transaction id */ - dhcp_offer_invalid_overload[311] = 3; - send_pkt(&net_test, dhcp_offer_invalid_overload, sizeof(dhcp_offer_invalid_overload)); - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - fail_unless(txpacket == 1); /* Nothing more sent */ - - dhcp_offer_invalid_overload[311] = 2; - send_pkt(&net_test, dhcp_offer_invalid_overload, sizeof(dhcp_offer_invalid_overload)); - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - fail_unless(txpacket == 1); /* Nothing more sent */ - - dhcp_offer_invalid_overload[311] = 1; - send_pkt(&net_test, dhcp_offer_invalid_overload, sizeof(dhcp_offer_invalid_overload)); - /* IP addresses should be zero */ - fail_if(memcmp(&addr, &net_test.ip_addr, sizeof(ip4_addr_t))); - fail_if(memcmp(&netmask, &net_test.netmask, sizeof(ip4_addr_t))); - fail_if(memcmp(&gw, &net_test.gw, sizeof(ip4_addr_t))); - fail_unless(txpacket == 1); /* Nothing more sent */ - - dhcp_offer_invalid_overload[311] = 0; - send_pkt(&net_test, dhcp_offer_invalid_overload, sizeof(dhcp_offer)); - - fail_unless(netif_dhcp_data(&net_test)->state == DHCP_STATE_REQUESTING); - - fail_unless(txpacket == 2); /* No more sent */ - xid = htonl(netif_dhcp_data(&net_test)->xid); /* xid updated */ - - netif_remove(&net_test); -} -END_TEST - -/** Create the suite including all tests for this module */ -Suite * -dhcp_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_dhcp), - TESTFUNC(test_dhcp_nak), - TESTFUNC(test_dhcp_relayed), - TESTFUNC(test_dhcp_nak_no_endmarker), - TESTFUNC(test_dhcp_invalid_overload) - }; - return create_suite("DHCP", tests, sizeof(tests)/sizeof(testfunc), dhcp_setup, dhcp_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.h deleted file mode 100644 index 0d88fa1b6953b29b7229216039a59186af4958cd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/dhcp/test_dhcp.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_DHCP_H -#define LWIP_HDR_TEST_DHCP_H - -#include "../lwip_check.h" - -Suite* dhcp_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.c deleted file mode 100644 index 59d73b9b455c72ff46fcd840d1588423ed4462db..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.c +++ /dev/null @@ -1,269 +0,0 @@ -#include "test_etharp.h" - -#include "lwip/udp.h" -#include "lwip/etharp.h" -#include "netif/ethernet.h" -#include "lwip/stats.h" - -#if !LWIP_STATS || !UDP_STATS || !MEMP_STATS || !ETHARP_STATS -#error "This tests needs UDP-, MEMP- and ETHARP-statistics enabled" -#endif -#if !ETHARP_SUPPORT_STATIC_ENTRIES -#error "This test needs ETHARP_SUPPORT_STATIC_ENTRIES enabled" -#endif - -static struct netif test_netif; -static ip4_addr_t test_ipaddr, test_netmask, test_gw; -struct eth_addr test_ethaddr = {{1,1,1,1,1,1}}; -struct eth_addr test_ethaddr2 = {{1,1,1,1,1,2}}; -struct eth_addr test_ethaddr3 = {{1,1,1,1,1,3}}; -struct eth_addr test_ethaddr4 = {{1,1,1,1,1,4}}; -static int linkoutput_ctr; - -/* Helper functions */ -static void -etharp_remove_all(void) -{ - int i; - /* call etharp_tmr often enough to have all entries cleaned */ - for(i = 0; i < 0xff; i++) { - etharp_tmr(); - } -} - -static err_t -default_netif_linkoutput(struct netif *netif, struct pbuf *p) -{ - fail_unless(netif == &test_netif); - fail_unless(p != NULL); - linkoutput_ctr++; - return ERR_OK; -} - -static err_t -default_netif_init(struct netif *netif) -{ - fail_unless(netif != NULL); - netif->linkoutput = default_netif_linkoutput; - netif->output = etharp_output; - netif->mtu = 1500; - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - netif->hwaddr_len = ETHARP_HWADDR_LEN; - return ERR_OK; -} - -static void -default_netif_add(void) -{ - IP4_ADDR(&test_gw, 192,168,0,1); - IP4_ADDR(&test_ipaddr, 192,168,0,1); - IP4_ADDR(&test_netmask, 255,255,0,0); - - fail_unless(netif_default == NULL); - netif_set_default(netif_add(&test_netif, &test_ipaddr, &test_netmask, - &test_gw, NULL, default_netif_init, NULL)); - netif_set_up(&test_netif); -} - -static void -default_netif_remove(void) -{ - fail_unless(netif_default == &test_netif); - netif_remove(&test_netif); -} - -static void -create_arp_response(ip4_addr_t *adr) -{ - int k; - struct eth_hdr *ethhdr; - struct etharp_hdr *etharphdr; - struct pbuf *p = pbuf_alloc(PBUF_RAW, sizeof(struct eth_hdr) + sizeof(struct etharp_hdr), PBUF_RAM); - if(p == NULL) { - FAIL_RET(); - } - ethhdr = (struct eth_hdr*)p->payload; - etharphdr = (struct etharp_hdr*)(ethhdr + 1); - - ethhdr->dest = test_ethaddr; - ethhdr->src = test_ethaddr2; - ethhdr->type = htons(ETHTYPE_ARP); - - etharphdr->hwtype = htons(/*HWTYPE_ETHERNET*/ 1); - etharphdr->proto = htons(ETHTYPE_IP); - etharphdr->hwlen = ETHARP_HWADDR_LEN; - etharphdr->protolen = sizeof(ip4_addr_t); - etharphdr->opcode = htons(ARP_REPLY); - - SMEMCPY(ðarphdr->sipaddr, adr, sizeof(ip4_addr_t)); - SMEMCPY(ðarphdr->dipaddr, &test_ipaddr, sizeof(ip4_addr_t)); - - k = 6; - while(k > 0) { - k--; - /* Write the ARP MAC-Addresses */ - etharphdr->shwaddr.addr[k] = test_ethaddr2.addr[k]; - etharphdr->dhwaddr.addr[k] = test_ethaddr.addr[k]; - /* Write the Ethernet MAC-Addresses */ - ethhdr->dest.addr[k] = test_ethaddr.addr[k]; - ethhdr->src.addr[k] = test_ethaddr2.addr[k]; - } - - ethernet_input(p, &test_netif); -} - -/* Setups/teardown functions */ - -static void -etharp_setup(void) -{ - etharp_remove_all(); - default_netif_add(); -} - -static void -etharp_teardown(void) -{ - etharp_remove_all(); - default_netif_remove(); -} - - -/* Test functions */ - -START_TEST(test_etharp_table) -{ -#if ETHARP_SUPPORT_STATIC_ENTRIES - err_t err; -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - s8_t idx; - const ip4_addr_t *unused_ipaddr; - struct eth_addr *unused_ethaddr; - struct udp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - if (netif_default != &test_netif) { - fail("This test needs a default netif"); - } - - linkoutput_ctr = 0; - - pcb = udp_new(); - fail_unless(pcb != NULL); - if (pcb != NULL) { - ip4_addr_t adrs[ARP_TABLE_SIZE + 2]; - int i; - for(i = 0; i < ARP_TABLE_SIZE + 2; i++) { - IP4_ADDR(&adrs[i], 192,168,0,i+2); - } - /* fill ARP-table with dynamic entries */ - for(i = 0; i < ARP_TABLE_SIZE; i++) { - struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, 10, PBUF_RAM); - fail_unless(p != NULL); - if (p != NULL) { - err_t err2; - ip_addr_t dst; - ip_addr_copy_from_ip4(dst, adrs[i]); - err2 = udp_sendto(pcb, p, &dst, 123); - fail_unless(err2 == ERR_OK); - /* etharp request sent? */ - fail_unless(linkoutput_ctr == (2*i) + 1); - pbuf_free(p); - - /* create an ARP response */ - create_arp_response(&adrs[i]); - /* queued UDP packet sent? */ - fail_unless(linkoutput_ctr == (2*i) + 2); - - idx = etharp_find_addr(NULL, &adrs[i], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == i); - etharp_tmr(); - } - } - linkoutput_ctr = 0; -#if ETHARP_SUPPORT_STATIC_ENTRIES - /* create one static entry */ - err = etharp_add_static_entry(&adrs[ARP_TABLE_SIZE], &test_ethaddr3); - fail_unless(err == ERR_OK); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == 0); - fail_unless(linkoutput_ctr == 0); -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - - linkoutput_ctr = 0; - /* fill ARP-table with dynamic entries */ - for(i = 0; i < ARP_TABLE_SIZE; i++) { - struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, 10, PBUF_RAM); - fail_unless(p != NULL); - if (p != NULL) { - err_t err2; - ip_addr_t dst; - ip_addr_copy_from_ip4(dst, adrs[i]); - err2 = udp_sendto(pcb, p, &dst, 123); - fail_unless(err2 == ERR_OK); - /* etharp request sent? */ - fail_unless(linkoutput_ctr == (2*i) + 1); - pbuf_free(p); - - /* create an ARP response */ - create_arp_response(&adrs[i]); - /* queued UDP packet sent? */ - fail_unless(linkoutput_ctr == (2*i) + 2); - - idx = etharp_find_addr(NULL, &adrs[i], &unused_ethaddr, &unused_ipaddr); - if (i < ARP_TABLE_SIZE - 1) { - fail_unless(idx == i+1); - } else { - /* the last entry must not overwrite the static entry! */ - fail_unless(idx == 1); - } - etharp_tmr(); - } - } -#if ETHARP_SUPPORT_STATIC_ENTRIES - /* create a second static entry */ - err = etharp_add_static_entry(&adrs[ARP_TABLE_SIZE+1], &test_ethaddr4); - fail_unless(err == ERR_OK); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == 0); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE+1], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == 2); - /* and remove it again */ - err = etharp_remove_static_entry(&adrs[ARP_TABLE_SIZE+1]); - fail_unless(err == ERR_OK); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == 0); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE+1], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == -1); -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - - /* check that static entries don't time out */ - etharp_remove_all(); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == 0); - -#if ETHARP_SUPPORT_STATIC_ENTRIES - /* remove the first static entry */ - err = etharp_remove_static_entry(&adrs[ARP_TABLE_SIZE]); - fail_unless(err == ERR_OK); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == -1); - idx = etharp_find_addr(NULL, &adrs[ARP_TABLE_SIZE+1], &unused_ethaddr, &unused_ipaddr); - fail_unless(idx == -1); -#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ - - udp_remove(pcb); - } -} -END_TEST - - -/** Create the suite including all tests for this module */ -Suite * -etharp_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_etharp_table) - }; - return create_suite("ETHARP", tests, sizeof(tests)/sizeof(testfunc), etharp_setup, etharp_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.h deleted file mode 100644 index 2dd772d8d0d268e55844410e810a2e207d0a9921..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/etharp/test_etharp.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_ETHARP_H -#define LWIP_HDR_TEST_ETHARP_H - -#include "../lwip_check.h" - -Suite* etharp_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_check.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_check.h deleted file mode 100644 index 0c218d1d1687f11aec0d328bc4bafd4d160f376d..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_check.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef LWIP_HDR_LWIP_CHECK_H -#define LWIP_HDR_LWIP_CHECK_H - -/* Common header file for lwIP unit tests using the check framework */ - -#include -#include -#include - -#define FAIL_RET() do { fail(); return; } while(0) -#define EXPECT(x) fail_unless(x) -#define EXPECT_RET(x) do { fail_unless(x); if(!(x)) { return; }} while(0) -#define EXPECT_RETX(x, y) do { fail_unless(x); if(!(x)) { return y; }} while(0) -#define EXPECT_RETNULL(x) EXPECT_RETX(x, NULL) - -typedef struct { - TFun func; - const char *name; -} testfunc; - -#define TESTFUNC(x) {(x), "" # x "" } - -/* Modified function from check.h, supplying function name */ -#define tcase_add_named_test(tc,tf) \ - _tcase_add_test((tc),(tf).func,(tf).name,0, 0, 0, 1) - -/** typedef for a function returning a test suite */ -typedef Suite* (suite_getter_fn)(void); - -/** Create a test suite */ -Suite* create_suite(const char* name, testfunc *tests, size_t num_tests, SFun setup, SFun teardown); - -#ifdef LWIP_UNITTESTS_LIB -int lwip_unittests_run(void) -#endif - -#endif /* LWIP_HDR_LWIP_CHECK_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_unittests.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_unittests.c deleted file mode 100644 index 46fd4308e18c24c250d4eba2a788b62170c37b7b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwip_unittests.c +++ /dev/null @@ -1,70 +0,0 @@ -#include "lwip_check.h" - -#include "udp/test_udp.h" -#include "tcp/test_tcp.h" -#include "tcp/test_tcp_oos.h" -#include "core/test_mem.h" -#include "core/test_pbuf.h" -#include "etharp/test_etharp.h" -#include "dhcp/test_dhcp.h" -#include "mdns/test_mdns.h" - -#include "lwip/init.h" - -Suite* create_suite(const char* name, testfunc *tests, size_t num_tests, SFun setup, SFun teardown) -{ - size_t i; - Suite *s = suite_create(name); - - for(i = 0; i < num_tests; i++) { - TCase *tc_core = tcase_create(name); - if ((setup != NULL) || (teardown != NULL)) { - tcase_add_checked_fixture(tc_core, setup, teardown); - } - tcase_add_named_test(tc_core, tests[i]); - suite_add_tcase(s, tc_core); - } - return s; -} - -#ifdef LWIP_UNITTESTS_LIB -int lwip_unittests_run(void) -#else -int main(void) -#endif -{ - int number_failed; - SRunner *sr; - size_t i; - suite_getter_fn* suites[] = { - udp_suite, - tcp_suite, - tcp_oos_suite, - mem_suite, - pbuf_suite, - etharp_suite, - dhcp_suite, - mdns_suite - }; - size_t num = sizeof(suites)/sizeof(void*); - LWIP_ASSERT("No suites defined", num > 0); - - lwip_init(); - - sr = srunner_create((suites[0])()); - for(i = 1; i < num; i++) { - srunner_add_suite(sr, ((suite_getter_fn*)suites[i])()); - } - -#ifdef LWIP_UNITTESTS_NOFORK - srunner_set_fork_status(sr, CK_NOFORK); -#endif -#ifdef LWIP_UNITTESTS_FORK - srunner_set_fork_status(sr, CK_FORK); -#endif - - srunner_run_all(sr, CK_NORMAL); - number_failed = srunner_ntests_failed(sr); - srunner_free(sr); - return (number_failed == 0) ? EXIT_SUCCESS : EXIT_FAILURE; -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwipopts.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwipopts.h deleted file mode 100644 index 25252b426c4342e3740f07c433e4eb586e8ca0cd..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/lwipopts.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Simon Goldschmidt - * - */ -#ifndef LWIP_HDR_LWIPOPTS_H -#define LWIP_HDR_LWIPOPTS_H - -/* Prevent having to link sys_arch.c (we don't test the API layers in unit tests) */ -#define NO_SYS 1 -#define SYS_LIGHTWEIGHT_PROT 0 -#define LWIP_NETCONN 0 -#define LWIP_SOCKET 0 - -/* Enable DHCP to test it, disable UDP checksum to easier inject packets */ -#define LWIP_DHCP 1 - -/* Minimal changes to opt.h required for tcp unit tests: */ -#define MEM_SIZE 16000 -#define TCP_SND_QUEUELEN 40 -#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN -#define TCP_SND_BUF (12 * TCP_MSS) -#define TCP_WND (10 * TCP_MSS) -#define LWIP_WND_SCALE 1 -#define TCP_RCV_SCALE 0 -#define PBUF_POOL_SIZE 400 /* pbuf tests need ~200KByte */ - -/* Enable IGMP and MDNS for MDNS tests */ -#define LWIP_IGMP 1 -#define LWIP_MDNS_RESPONDER 1 -#define LWIP_NUM_NETIF_CLIENT_DATA (LWIP_MDNS_RESPONDER) - -/* Minimal changes to opt.h required for etharp unit tests: */ -#define ETHARP_SUPPORT_STATIC_ENTRIES 1 - -#endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.c deleted file mode 100644 index ca9be64ea10a4e2707321d578d625ebb3bfb7d19..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.c +++ /dev/null @@ -1,915 +0,0 @@ -/* - * Copyright (c) 2015 Verisure Innovation AB - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Erik Ekman - * - */ - -#include "test_mdns.h" - -#include "lwip/pbuf.h" -#include "lwip/apps/mdns.h" -#include "lwip/apps/mdns_priv.h" - -START_TEST(readname_basic) -{ - static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == sizeof(data)); - fail_unless(domain.length == sizeof(data)); - fail_if(memcmp(&domain.name, data, sizeof(data))); -} -END_TEST - -START_TEST(readname_anydata) -{ - static const u8_t data[] = { 0x05, 0x00, 0xFF, 0x08, 0xc0, 0x0f, 0x04, 0x7f, 0x80, 0x82, 0x88, 0x00 }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == sizeof(data)); - fail_unless(domain.length == sizeof(data)); - fail_if(memcmp(&domain.name, data, sizeof(data))); -} -END_TEST - -START_TEST(readname_short_buf) -{ - static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a' }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_long_label) -{ - static const u8_t data[] = { - 0x05, 'm', 'u', 'l', 't', 'i', - 0x52, 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_overflow) -{ - static const u8_t data[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_jump_earlier) -{ - static const u8_t data[] = { - /* Some padding needed, not supported to jump to bytes containing dns header */ - /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 10 */ 0x0f, 0x0e, 0x05, 'l', 'o', 'c', 'a', 'l', 0x00, 0xab, - /* 20 */ 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc0, 0x0c - }; - static const u8_t fullname[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 20, &domain); - pbuf_free(p); - fail_unless(offset == sizeof(data)); - fail_unless(domain.length == sizeof(fullname)); - - fail_if(memcmp(&domain.name, fullname, sizeof(fullname))); -} -END_TEST - -START_TEST(readname_jump_earlier_jump) -{ - static const u8_t data[] = { - /* Some padding needed, not supported to jump to bytes containing dns header */ - /* 0x00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 0x08 */ 0x00, 0x00, 0x00, 0x00, 0x03, 0x0b, 0x0a, 0xf2, - /* 0x10 */ 0x04, 'c', 'a', 's', 't', 0x00, 0xc0, 0x10, - /* 0x18 */ 0x05, 'm', 'u', 'l', 't', 'i', 0xc0, 0x16 - }; - static const u8_t fullname[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0x18, &domain); - pbuf_free(p); - fail_unless(offset == sizeof(data)); - fail_unless(domain.length == sizeof(fullname)); - - fail_if(memcmp(&domain.name, fullname, sizeof(fullname))); -} -END_TEST - -START_TEST(readname_jump_maxdepth) -{ - static const u8_t data[] = { - /* Some padding needed, not supported to jump to bytes containing dns header */ - /* 0x00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 0x08 */ 0x00, 0x00, 0x00, 0x00, 0x03, 0x0b, 0x0a, 0xf2, - /* 0x10 */ 0x04, 'n', 'a', 'm', 'e', 0xc0, 0x27, 0x03, - /* 0x18 */ 0x03, 'd', 'n', 's', 0xc0, 0x10, 0xc0, 0x10, - /* 0x20 */ 0x04, 'd', 'e', 'e', 'p', 0xc0, 0x18, 0x00, - /* 0x28 */ 0x04, 'c', 'a', 's', 't', 0xc0, 0x20, 0xb0, - /* 0x30 */ 0x05, 'm', 'u', 'l', 't', 'i', 0xc0, 0x28 - }; - static const u8_t fullname[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', - 0x04, 'd', 'e', 'e', 'p', 0x03, 'd', 'n', 's', - 0x04, 'n', 'a', 'm', 'e', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0x30, &domain); - pbuf_free(p); - fail_unless(offset == sizeof(data)); - fail_unless(domain.length == sizeof(fullname)); - - fail_if(memcmp(&domain.name, fullname, sizeof(fullname))); -} -END_TEST - -START_TEST(readname_jump_later) -{ - static const u8_t data[] = { - /* 0x00 */ 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc0, 0x10, 0x00, 0x01, 0x40, - /* 0x10 */ 0x05, 'l', 'o', 'c', 'a', 'l', 0x00, 0xab - }; - static const u8_t fullname[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == 13); - fail_unless(domain.length == sizeof(fullname)); - - fail_if(memcmp(&domain.name, fullname, sizeof(fullname))); -} -END_TEST - -START_TEST(readname_half_jump) -{ - static const u8_t data[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc0 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_jump_toolong) -{ - static const u8_t data[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc2, 0x10, 0x00, 0x01, 0x40 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 0, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_jump_loop_label) -{ - static const u8_t data[] = { - /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 10 */ 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc0, 0x10 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 10, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(readname_jump_loop_jump) -{ - static const u8_t data[] = { - /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 10 */ 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0xc0, 0x15 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - offset = mdns_readname(p, 10, &domain); - pbuf_free(p); - fail_unless(offset == MDNS_READNAME_ERROR); -} -END_TEST - -START_TEST(add_label_basic) -{ - static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 }; - struct mdns_domain domain; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - fail_unless(domain.length == sizeof(data)); - fail_if(memcmp(&domain.name, data, sizeof(data))); -} -END_TEST - -START_TEST(add_label_long_label) -{ - static const char *toolong = "abcdefghijklmnopqrstuvwxyz0123456789-abcdefghijklmnopqrstuvwxyz0123456789-abcdefghijklmnopqrstuvwxyz0123456789-"; - struct mdns_domain domain; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, toolong, (u8_t)strlen(toolong)); - fail_unless(res == ERR_VAL); -} -END_TEST - -START_TEST(add_label_full) -{ - static const char *label = "0123456789abcdef0123456789abcdef"; - struct mdns_domain domain; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 33); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 66); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 99); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 132); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 165); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 198); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 231); - res = mdns_domain_add_label(&domain, label, (u8_t)strlen(label)); - fail_unless(res == ERR_VAL); - fail_unless(domain.length == 231); - res = mdns_domain_add_label(&domain, label, 25); - fail_unless(res == ERR_VAL); - fail_unless(domain.length == 231); - res = mdns_domain_add_label(&domain, label, 24); - fail_unless(res == ERR_VAL); - fail_unless(domain.length == 231); - res = mdns_domain_add_label(&domain, label, 23); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 255); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - fail_unless(domain.length == 256); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_VAL); - fail_unless(domain.length == 256); -} -END_TEST - -START_TEST(domain_eq_basic) -{ - static const u8_t data[] = { - 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 - }; - struct mdns_domain domain1, domain2; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain1, 0, sizeof(domain1)); - res = mdns_domain_add_label(&domain1, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, NULL, 0); - fail_unless(res == ERR_OK); - fail_unless(domain1.length == sizeof(data)); - - memset(&domain2, 0, sizeof(domain2)); - res = mdns_domain_add_label(&domain2, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, NULL, 0); - fail_unless(res == ERR_OK); - - fail_unless(mdns_domain_eq(&domain1, &domain2)); -} -END_TEST - -START_TEST(domain_eq_diff) -{ - struct mdns_domain domain1, domain2; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain1, 0, sizeof(domain1)); - res = mdns_domain_add_label(&domain1, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, "base", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, NULL, 0); - fail_unless(res == ERR_OK); - - memset(&domain2, 0, sizeof(domain2)); - res = mdns_domain_add_label(&domain2, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, NULL, 0); - fail_unless(res == ERR_OK); - - fail_if(mdns_domain_eq(&domain1, &domain2)); -} -END_TEST - -START_TEST(domain_eq_case) -{ - struct mdns_domain domain1, domain2; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain1, 0, sizeof(domain1)); - res = mdns_domain_add_label(&domain1, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, NULL, 0); - fail_unless(res == ERR_OK); - - memset(&domain2, 0, sizeof(domain2)); - res = mdns_domain_add_label(&domain2, "MulTI", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, "casT", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, NULL, 0); - fail_unless(res == ERR_OK); - - fail_unless(mdns_domain_eq(&domain1, &domain2)); -} -END_TEST - -START_TEST(domain_eq_anydata) -{ - static const u8_t data1[] = { 0x05, 0xcc, 0xdc, 0x00, 0xa0 }; - static const u8_t data2[] = { 0x7f, 0x8c, 0x01, 0xff, 0xcf }; - struct mdns_domain domain1, domain2; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain1, 0, sizeof(domain1)); - res = mdns_domain_add_label(&domain1, (const char*)data1, sizeof(data1)); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, "cast", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, (const char*)data2, sizeof(data2)); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, NULL, 0); - fail_unless(res == ERR_OK); - - memset(&domain2, 0, sizeof(domain2)); - res = mdns_domain_add_label(&domain2, (const char*)data1, sizeof(data1)); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, "casT", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, (const char*)data2, sizeof(data2)); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, NULL, 0); - fail_unless(res == ERR_OK); - - fail_unless(mdns_domain_eq(&domain1, &domain2)); -} -END_TEST - -START_TEST(domain_eq_length) -{ - struct mdns_domain domain1, domain2; - err_t res; - LWIP_UNUSED_ARG(_i); - - memset(&domain1, 0, sizeof(domain1)); - memset(domain1.name, 0xAA, sizeof(MDNS_DOMAIN_MAXLEN)); - res = mdns_domain_add_label(&domain1, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain1, "cast", 4); - fail_unless(res == ERR_OK); - - memset(&domain2, 0, sizeof(domain2)); - memset(domain2.name, 0xBB, sizeof(MDNS_DOMAIN_MAXLEN)); - res = mdns_domain_add_label(&domain2, "multi", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain2, "cast", 4); - fail_unless(res == ERR_OK); - - fail_unless(mdns_domain_eq(&domain1, &domain2)); -} -END_TEST - -START_TEST(compress_full_match) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x06, 'f', 'o', 'o', 'b', 'a', 'r', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 0 bytes, then a jump to addr 2 */ - fail_unless(length == 0); - fail_unless(offset == 2); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_full_match_subset) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x02, 'g', 'o', 0x06, 'f', 'o', 'o', 'b', 'a', 'r', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 0 bytes, then a jump to addr 5 */ - fail_unless(length == 0); - fail_unless(offset == 5); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_full_match_jump) -{ - static const u8_t data[] = { - /* 0x00 */ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - /* 0x10 */ 0x04, 'l', 'w', 'i', 'p', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00, 0xc0, 0x00, 0x02, 0x00, - /* 0x20 */ 0x06, 'f', 'o', 'o', 'b', 'a', 'r', 0xc0, 0x15 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 0x20; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 0 bytes, then a jump to addr 0x20 */ - fail_unless(length == 0); - fail_unless(offset == 0x20); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_no_match) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x04, 'l', 'w', 'i', 'p', 0x05, 'w', 'i', 'k', 'i', 'a', 0x03, 'c', 'o', 'm', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - /* Write all bytes, no jump */ - fail_unless(length == domain.length); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_2nd_label) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x06, 'f', 'o', 'o', 'b', 'a', 'r', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "lwip", 4); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 5 bytes, then a jump to addr 9 */ - fail_unless(length == 5); - fail_unless(offset == 9); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_2nd_label_short) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x04, 'l', 'w', 'i', 'p', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 5 bytes, then a jump to addr 7 */ - fail_unless(length == 7); - fail_unless(offset == 7); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_jump_to_jump) -{ - static const u8_t data[] = { - /* 0x00 */ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - /* 0x10 */ 0x04, 'l', 'w', 'i', 'p', 0x05, 'l', 'o', 'c', 'a', 'l', 0x00, 0xc0, 0x00, 0x02, 0x00, - /* 0x20 */ 0x07, 'b', 'a', 'n', 'a', 'n', 'a', 's', 0xc0, 0x15 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 0x20; - length = mdns_compress_domain(p, &offset, &domain); - /* Dont compress if jump would be to a jump */ - fail_unless(length == domain.length); - - offset = 0x10; - length = mdns_compress_domain(p, &offset, &domain); - /* Write 7 bytes, then a jump to addr 0x15 */ - fail_unless(length == 7); - fail_unless(offset == 0x15); - - pbuf_free(p); -} -END_TEST - -START_TEST(compress_long_match) -{ - static const u8_t data[] = { - 0x00, 0x00, - 0x06, 'f', 'o', 'o', 'b', 'a', 'r', 0x05, 'l', 'o', 'c', 'a', 'l', 0x03, 'c', 'o', 'm', 0x00 - }; - struct pbuf *p; - struct mdns_domain domain; - u16_t offset; - u16_t length; - err_t res; - LWIP_UNUSED_ARG(_i); - - p = pbuf_alloc(PBUF_RAW, sizeof(data), PBUF_ROM); - p->payload = (void *)(size_t)data; - fail_if(p == NULL); - - memset(&domain, 0, sizeof(domain)); - res = mdns_domain_add_label(&domain, "foobar", 6); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, "local", 5); - fail_unless(res == ERR_OK); - res = mdns_domain_add_label(&domain, NULL, 0); - fail_unless(res == ERR_OK); - - offset = 2; - length = mdns_compress_domain(p, &offset, &domain); - fail_unless(length == domain.length); - - pbuf_free(p); -} -END_TEST - -Suite* mdns_suite(void) -{ - testfunc tests[] = { - TESTFUNC(readname_basic), - TESTFUNC(readname_anydata), - TESTFUNC(readname_short_buf), - TESTFUNC(readname_long_label), - TESTFUNC(readname_overflow), - TESTFUNC(readname_jump_earlier), - TESTFUNC(readname_jump_earlier_jump), - TESTFUNC(readname_jump_maxdepth), - TESTFUNC(readname_jump_later), - TESTFUNC(readname_half_jump), - TESTFUNC(readname_jump_toolong), - TESTFUNC(readname_jump_loop_label), - TESTFUNC(readname_jump_loop_jump), - - TESTFUNC(add_label_basic), - TESTFUNC(add_label_long_label), - TESTFUNC(add_label_full), - - TESTFUNC(domain_eq_basic), - TESTFUNC(domain_eq_diff), - TESTFUNC(domain_eq_case), - TESTFUNC(domain_eq_anydata), - TESTFUNC(domain_eq_length), - - TESTFUNC(compress_full_match), - TESTFUNC(compress_full_match_subset), - TESTFUNC(compress_full_match_jump), - TESTFUNC(compress_no_match), - TESTFUNC(compress_2nd_label), - TESTFUNC(compress_2nd_label_short), - TESTFUNC(compress_jump_to_jump), - TESTFUNC(compress_long_match), - }; - return create_suite("MDNS", tests, sizeof(tests)/sizeof(testfunc), NULL, NULL); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.h deleted file mode 100644 index c3df339140b3e086121873437f2822f3d36f9df6..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/mdns/test_mdns.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_MDNS_H__ -#define LWIP_HDR_TEST_MDNS_H__ - -#include "../lwip_check.h" - -Suite* mdns_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.c deleted file mode 100644 index 64121ca8f326da38d51961a04e15f82964a002e1..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.c +++ /dev/null @@ -1,314 +0,0 @@ -#include "tcp_helper.h" - -#include "lwip/priv/tcp_priv.h" -#include "lwip/stats.h" -#include "lwip/pbuf.h" -#include "lwip/inet_chksum.h" -#include "lwip/ip_addr.h" - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif - -/** Remove all pcbs on the given list. */ -static void -tcp_remove(struct tcp_pcb* pcb_list) -{ - struct tcp_pcb *pcb = pcb_list; - struct tcp_pcb *pcb2; - - while(pcb != NULL) { - pcb2 = pcb; - pcb = pcb->next; - tcp_abort(pcb2); - } -} - -/** Remove all pcbs on listen-, active- and time-wait-list (bound- isn't exported). */ -void -tcp_remove_all(void) -{ - tcp_remove(tcp_listen_pcbs.pcbs); - tcp_remove(tcp_active_pcbs); - tcp_remove(tcp_tw_pcbs); - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_PCB_LISTEN) == 0); - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_SEG) == 0); - fail_unless(MEMP_STATS_GET(used, MEMP_PBUF_POOL) == 0); -} - -/** Create a TCP segment usable for passing to tcp_input */ -static struct pbuf* -tcp_create_segment_wnd(ip_addr_t* src_ip, ip_addr_t* dst_ip, - u16_t src_port, u16_t dst_port, void* data, size_t data_len, - u32_t seqno, u32_t ackno, u8_t headerflags, u16_t wnd) -{ - struct pbuf *p, *q; - struct ip_hdr* iphdr; - struct tcp_hdr* tcphdr; - u16_t pbuf_len = (u16_t)(sizeof(struct ip_hdr) + sizeof(struct tcp_hdr) + data_len); - LWIP_ASSERT("data_len too big", data_len <= 0xFFFF); - - p = pbuf_alloc(PBUF_RAW, pbuf_len, PBUF_POOL); - EXPECT_RETNULL(p != NULL); - /* first pbuf must be big enough to hold the headers */ - EXPECT_RETNULL(p->len >= (sizeof(struct ip_hdr) + sizeof(struct tcp_hdr))); - if (data_len > 0) { - /* first pbuf must be big enough to hold at least 1 data byte, too */ - EXPECT_RETNULL(p->len > (sizeof(struct ip_hdr) + sizeof(struct tcp_hdr))); - } - - for(q = p; q != NULL; q = q->next) { - memset(q->payload, 0, q->len); - } - - iphdr = (struct ip_hdr*)p->payload; - /* fill IP header */ - iphdr->dest.addr = ip_2_ip4(dst_ip)->addr; - iphdr->src.addr = ip_2_ip4(src_ip)->addr; - IPH_VHL_SET(iphdr, 4, IP_HLEN / 4); - IPH_TOS_SET(iphdr, 0); - IPH_LEN_SET(iphdr, htons(p->tot_len)); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - /* let p point to TCP header */ - pbuf_header(p, -(s16_t)sizeof(struct ip_hdr)); - - tcphdr = (struct tcp_hdr*)p->payload; - tcphdr->src = htons(src_port); - tcphdr->dest = htons(dst_port); - tcphdr->seqno = htonl(seqno); - tcphdr->ackno = htonl(ackno); - TCPH_HDRLEN_SET(tcphdr, sizeof(struct tcp_hdr)/4); - TCPH_FLAGS_SET(tcphdr, headerflags); - tcphdr->wnd = htons(wnd); - - if (data_len > 0) { - /* let p point to TCP data */ - pbuf_header(p, -(s16_t)sizeof(struct tcp_hdr)); - /* copy data */ - pbuf_take(p, data, (u16_t)data_len); - /* let p point to TCP header again */ - pbuf_header(p, sizeof(struct tcp_hdr)); - } - - /* calculate checksum */ - - tcphdr->chksum = ip_chksum_pseudo(p, - IP_PROTO_TCP, p->tot_len, src_ip, dst_ip); - - pbuf_header(p, sizeof(struct ip_hdr)); - - return p; -} - -/** Create a TCP segment usable for passing to tcp_input */ -struct pbuf* -tcp_create_segment(ip_addr_t* src_ip, ip_addr_t* dst_ip, - u16_t src_port, u16_t dst_port, void* data, size_t data_len, - u32_t seqno, u32_t ackno, u8_t headerflags) -{ - return tcp_create_segment_wnd(src_ip, dst_ip, src_port, dst_port, data, - data_len, seqno, ackno, headerflags, TCP_WND); -} - -/** Create a TCP segment usable for passing to tcp_input - * - IP-addresses, ports, seqno and ackno are taken from pcb - * - seqno and ackno can be altered with an offset - */ -struct pbuf* -tcp_create_rx_segment(struct tcp_pcb* pcb, void* data, size_t data_len, u32_t seqno_offset, - u32_t ackno_offset, u8_t headerflags) -{ - return tcp_create_segment(&pcb->remote_ip, &pcb->local_ip, pcb->remote_port, pcb->local_port, - data, data_len, pcb->rcv_nxt + seqno_offset, pcb->lastack + ackno_offset, headerflags); -} - -/** Create a TCP segment usable for passing to tcp_input - * - IP-addresses, ports, seqno and ackno are taken from pcb - * - seqno and ackno can be altered with an offset - * - TCP window can be adjusted - */ -struct pbuf* tcp_create_rx_segment_wnd(struct tcp_pcb* pcb, void* data, size_t data_len, - u32_t seqno_offset, u32_t ackno_offset, u8_t headerflags, u16_t wnd) -{ - return tcp_create_segment_wnd(&pcb->remote_ip, &pcb->local_ip, pcb->remote_port, pcb->local_port, - data, data_len, pcb->rcv_nxt + seqno_offset, pcb->lastack + ackno_offset, headerflags, wnd); -} - -/** Safely bring a tcp_pcb into the requested state */ -void -tcp_set_state(struct tcp_pcb* pcb, enum tcp_state state, ip_addr_t* local_ip, - ip_addr_t* remote_ip, u16_t local_port, u16_t remote_port) -{ - u32_t iss; - - /* @todo: are these all states? */ - /* @todo: remove from previous list */ - pcb->state = state; - - iss = tcp_next_iss(pcb); - pcb->snd_wl2 = iss; - pcb->snd_nxt = iss; - pcb->lastack = iss; - pcb->snd_lbb = iss; - - if (state == ESTABLISHED) { - TCP_REG(&tcp_active_pcbs, pcb); - ip_addr_copy(pcb->local_ip, *local_ip); - pcb->local_port = local_port; - ip_addr_copy(pcb->remote_ip, *remote_ip); - pcb->remote_port = remote_port; - } else if(state == LISTEN) { - TCP_REG(&tcp_listen_pcbs.pcbs, pcb); - ip_addr_copy(pcb->local_ip, *local_ip); - pcb->local_port = local_port; - } else if(state == TIME_WAIT) { - TCP_REG(&tcp_tw_pcbs, pcb); - ip_addr_copy(pcb->local_ip, *local_ip); - pcb->local_port = local_port; - ip_addr_copy(pcb->remote_ip, *remote_ip); - pcb->remote_port = remote_port; - } else { - fail(); - } -} - -void -test_tcp_counters_err(void* arg, err_t err) -{ - struct test_tcp_counters* counters = (struct test_tcp_counters*)arg; - EXPECT_RET(arg != NULL); - counters->err_calls++; - counters->last_err = err; -} - -static void -test_tcp_counters_check_rxdata(struct test_tcp_counters* counters, struct pbuf* p) -{ - struct pbuf* q; - u32_t i, received; - if(counters->expected_data == NULL) { - /* no data to compare */ - return; - } - EXPECT_RET(counters->recved_bytes + p->tot_len <= counters->expected_data_len); - received = counters->recved_bytes; - for(q = p; q != NULL; q = q->next) { - char *data = (char*)q->payload; - for(i = 0; i < q->len; i++) { - EXPECT_RET(data[i] == counters->expected_data[received]); - received++; - } - } - EXPECT(received == counters->recved_bytes + p->tot_len); -} - -err_t -test_tcp_counters_recv(void* arg, struct tcp_pcb* pcb, struct pbuf* p, err_t err) -{ - struct test_tcp_counters* counters = (struct test_tcp_counters*)arg; - EXPECT_RETX(arg != NULL, ERR_OK); - EXPECT_RETX(pcb != NULL, ERR_OK); - EXPECT_RETX(err == ERR_OK, ERR_OK); - - if (p != NULL) { - if (counters->close_calls == 0) { - counters->recv_calls++; - test_tcp_counters_check_rxdata(counters, p); - counters->recved_bytes += p->tot_len; - } else { - counters->recv_calls_after_close++; - counters->recved_bytes_after_close += p->tot_len; - } - pbuf_free(p); - } else { - counters->close_calls++; - } - EXPECT(counters->recv_calls_after_close == 0 && counters->recved_bytes_after_close == 0); - return ERR_OK; -} - -/** Allocate a pcb and set up the test_tcp_counters_* callbacks */ -struct tcp_pcb* -test_tcp_new_counters_pcb(struct test_tcp_counters* counters) -{ - struct tcp_pcb* pcb = tcp_new(); - if (pcb != NULL) { - /* set up args and callbacks */ - tcp_arg(pcb, counters); - tcp_recv(pcb, test_tcp_counters_recv); - tcp_err(pcb, test_tcp_counters_err); - pcb->snd_wnd = TCP_WND; - pcb->snd_wnd_max = TCP_WND; - } - return pcb; -} - -/** Calls tcp_input() after adjusting current_iphdr_dest */ -void test_tcp_input(struct pbuf *p, struct netif *inp) -{ - struct ip_hdr *iphdr = (struct ip_hdr*)p->payload; - /* these lines are a hack, don't use them as an example :-) */ - ip_addr_copy_from_ip4(*ip_current_dest_addr(), iphdr->dest); - ip_addr_copy_from_ip4(*ip_current_src_addr(), iphdr->src); - ip_current_netif() = inp; - ip_data.current_ip4_header = iphdr; - - /* since adding IPv6, p->payload must point to tcp header, not ip header */ - pbuf_header(p, -(s16_t)sizeof(struct ip_hdr)); - - tcp_input(p, inp); - - ip_addr_set_zero(ip_current_dest_addr()); - ip_addr_set_zero(ip_current_src_addr()); - ip_current_netif() = NULL; - ip_data.current_ip4_header = NULL; -} - -static err_t test_tcp_netif_output(struct netif *netif, struct pbuf *p, - const ip4_addr_t *ipaddr) -{ - struct test_tcp_txcounters *txcounters = (struct test_tcp_txcounters*)netif->state; - LWIP_UNUSED_ARG(ipaddr); - if (txcounters != NULL) - { - txcounters->num_tx_calls++; - txcounters->num_tx_bytes += p->tot_len; - if (txcounters->copy_tx_packets) { - struct pbuf *p_copy = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); - err_t err; - EXPECT(p_copy != NULL); - err = pbuf_copy(p_copy, p); - EXPECT(err == ERR_OK); - if (txcounters->tx_packets == NULL) { - txcounters->tx_packets = p_copy; - } else { - pbuf_cat(txcounters->tx_packets, p_copy); - } - } - } - return ERR_OK; -} - -void test_tcp_init_netif(struct netif *netif, struct test_tcp_txcounters *txcounters, - ip_addr_t *ip_addr, ip_addr_t *netmask) -{ - struct netif *n; - memset(netif, 0, sizeof(struct netif)); - if (txcounters != NULL) { - memset(txcounters, 0, sizeof(struct test_tcp_txcounters)); - netif->state = txcounters; - } - netif->output = test_tcp_netif_output; - netif->flags |= NETIF_FLAG_UP | NETIF_FLAG_LINK_UP; - ip_addr_copy_from_ip4(netif->netmask, *ip_2_ip4(netmask)); - ip_addr_copy_from_ip4(netif->ip_addr, *ip_2_ip4(ip_addr)); - for (n = netif_list; n != NULL; n = n->next) { - if (n == netif) { - return; - } - } - netif->next = NULL; - netif_list = netif; -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.h deleted file mode 100644 index 04974818e7171ad945256e07c4ac325217d41fc1..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/tcp_helper.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef LWIP_HDR_TCP_HELPER_H -#define LWIP_HDR_TCP_HELPER_H - -#include "../lwip_check.h" -#include "lwip/arch.h" -#include "lwip/tcp.h" -#include "lwip/netif.h" - -/* counters used for test_tcp_counters_* callback functions */ -struct test_tcp_counters { - u32_t recv_calls; - u32_t recved_bytes; - u32_t recv_calls_after_close; - u32_t recved_bytes_after_close; - u32_t close_calls; - u32_t err_calls; - err_t last_err; - char* expected_data; - u32_t expected_data_len; -}; - -struct test_tcp_txcounters { - u32_t num_tx_calls; - u32_t num_tx_bytes; - u8_t copy_tx_packets; - struct pbuf *tx_packets; -}; - -/* Helper functions */ -void tcp_remove_all(void); - -struct pbuf* tcp_create_segment(ip_addr_t* src_ip, ip_addr_t* dst_ip, - u16_t src_port, u16_t dst_port, void* data, size_t data_len, - u32_t seqno, u32_t ackno, u8_t headerflags); -struct pbuf* tcp_create_rx_segment(struct tcp_pcb* pcb, void* data, size_t data_len, - u32_t seqno_offset, u32_t ackno_offset, u8_t headerflags); -struct pbuf* tcp_create_rx_segment_wnd(struct tcp_pcb* pcb, void* data, size_t data_len, - u32_t seqno_offset, u32_t ackno_offset, u8_t headerflags, u16_t wnd); -void tcp_set_state(struct tcp_pcb* pcb, enum tcp_state state, ip_addr_t* local_ip, - ip_addr_t* remote_ip, u16_t local_port, u16_t remote_port); -void test_tcp_counters_err(void* arg, err_t err); -err_t test_tcp_counters_recv(void* arg, struct tcp_pcb* pcb, struct pbuf* p, err_t err); - -struct tcp_pcb* test_tcp_new_counters_pcb(struct test_tcp_counters* counters); - -void test_tcp_input(struct pbuf *p, struct netif *inp); - -void test_tcp_init_netif(struct netif *netif, struct test_tcp_txcounters *txcounters, - ip_addr_t *ip_addr, ip_addr_t *netmask); - - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.c deleted file mode 100644 index d99b807d96763874f40f017ff65a0d89dc10401f..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.c +++ /dev/null @@ -1,744 +0,0 @@ -#include "test_tcp.h" - -#include "lwip/priv/tcp_priv.h" -#include "lwip/stats.h" -#include "tcp_helper.h" -#include "lwip/inet_chksum.h" - -#ifdef _MSC_VER -#pragma warning(disable: 4307) /* we explicitly wrap around TCP seqnos */ -#endif - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif -#if TCP_SND_BUF <= TCP_WND -#error "This tests needs TCP_SND_BUF to be > TCP_WND" -#endif - -static u8_t test_tcp_timer; - -/* our own version of tcp_tmr so we can reset fast/slow timer state */ -static void -test_tcp_tmr(void) -{ - tcp_fasttmr(); - if (++test_tcp_timer & 1) { - tcp_slowtmr(); - } -} - -/* Setups/teardown functions */ - -static void -tcp_setup(void) -{ - /* reset iss to default (6510) */ - tcp_ticks = 0; - tcp_ticks = 0 - (tcp_next_iss(NULL) - 6510); - tcp_next_iss(NULL); - tcp_ticks = 0; - - test_tcp_timer = 0; - tcp_remove_all(); -} - -static void -tcp_teardown(void) -{ - netif_list = NULL; - netif_default = NULL; - tcp_remove_all(); -} - - -/* Test functions */ - -/** Call tcp_new() and tcp_abort() and test memp stats */ -START_TEST(test_tcp_new_abort) -{ - struct tcp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); - - pcb = tcp_new(); - fail_unless(pcb != NULL); - if (pcb != NULL) { - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - fail_unless(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); - } -} -END_TEST - -/** Create an ESTABLISHED pcb and check if receive callback is called */ -START_TEST(test_tcp_recv_inseq) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf* p; - char data[] = {1, 2, 3, 4}; - ip_addr_t remote_ip, local_ip, netmask; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - struct test_tcp_txcounters txcounters; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create a segment */ - p = tcp_create_rx_segment(pcb, counters.expected_data, data_len, 0, 0, 0); - EXPECT(p != NULL); - if (p != NULL) { - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - } - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - -/** Check that we handle malformed tcp headers, and discard the pbuf(s) */ -START_TEST(test_tcp_malformed_header) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf* p; - char data[] = {1, 2, 3, 4}; - ip_addr_t remote_ip, local_ip, netmask; - u16_t data_len, chksum; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - struct test_tcp_txcounters txcounters; - struct tcp_hdr *hdr; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create a segment */ - p = tcp_create_rx_segment(pcb, counters.expected_data, data_len, 0, 0, 0); - - pbuf_header(p, -(s16_t)sizeof(struct ip_hdr)); - - hdr = (struct tcp_hdr *)p->payload; - TCPH_HDRLEN_FLAGS_SET(hdr, 15, 0x3d1); - - hdr->chksum = 0; - - chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, - &remote_ip, &local_ip); - - hdr->chksum = chksum; - - pbuf_header(p, sizeof(struct ip_hdr)); - - EXPECT(p != NULL); - EXPECT(p->next == NULL); - if (p != NULL) { - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - } - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - - -/** Provoke fast retransmission by duplicate ACKs and then recover by ACKing all sent data. - * At the end, send more data. */ -START_TEST(test_tcp_fast_retx_recover) -{ - struct netif netif; - struct test_tcp_txcounters txcounters; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf* p; - char data1[] = { 1, 2, 3, 4}; - char data2[] = { 5, 6, 7, 8}; - char data3[] = { 9, 10, 11, 12}; - char data4[] = {13, 14, 15, 16}; - char data5[] = {17, 18, 19, 20}; - char data6[TCP_MSS] = {21, 22, 23, 24}; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - err_t err; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - memset(&counters, 0, sizeof(counters)); - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->mss = TCP_MSS; - /* disable initial congestion window (we don't send a SYN here...) */ - pcb->cwnd = pcb->snd_wnd; - - /* send data1 */ - err = tcp_write(pcb, data1, sizeof(data1), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT_RET(txcounters.num_tx_calls == 1); - EXPECT_RET(txcounters.num_tx_bytes == sizeof(data1) + sizeof(struct tcp_hdr) + sizeof(struct ip_hdr)); - memset(&txcounters, 0, sizeof(txcounters)); - /* "recv" ACK for data1 */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 4, TCP_ACK); - EXPECT_RET(p != NULL); - test_tcp_input(p, &netif); - EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(pcb->unacked == NULL); - /* send data2 */ - err = tcp_write(pcb, data2, sizeof(data2), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT_RET(txcounters.num_tx_calls == 1); - EXPECT_RET(txcounters.num_tx_bytes == sizeof(data2) + sizeof(struct tcp_hdr) + sizeof(struct ip_hdr)); - memset(&txcounters, 0, sizeof(txcounters)); - /* duplicate ACK for data1 (data2 is lost) */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - EXPECT_RET(p != NULL); - test_tcp_input(p, &netif); - EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(pcb->dupacks == 1); - /* send data3 */ - err = tcp_write(pcb, data3, sizeof(data3), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /* nagle enabled, no tx calls */ - EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(txcounters.num_tx_bytes == 0); - memset(&txcounters, 0, sizeof(txcounters)); - /* 2nd duplicate ACK for data1 (data2 and data3 are lost) */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - EXPECT_RET(p != NULL); - test_tcp_input(p, &netif); - EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(pcb->dupacks == 2); - /* queue data4, don't send it (unsent-oversize is != 0) */ - err = tcp_write(pcb, data4, sizeof(data4), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - /* 3nd duplicate ACK for data1 (data2 and data3 are lost) -> fast retransmission */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - EXPECT_RET(p != NULL); - test_tcp_input(p, &netif); - /*EXPECT_RET(txcounters.num_tx_calls == 1);*/ - EXPECT_RET(pcb->dupacks == 3); - memset(&txcounters, 0, sizeof(txcounters)); - /* @todo: check expected data?*/ - - /* send data5, not output yet */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - /*err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK);*/ - EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(txcounters.num_tx_bytes == 0); - memset(&txcounters, 0, sizeof(txcounters)); - { - int i = 0; - do - { - err = tcp_write(pcb, data6, TCP_MSS, TCP_WRITE_FLAG_COPY); - i++; - }while(err == ERR_OK); - EXPECT_RET(err != ERR_OK); - } - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /*EXPECT_RET(txcounters.num_tx_calls == 0); - EXPECT_RET(txcounters.num_tx_bytes == 0);*/ - memset(&txcounters, 0, sizeof(txcounters)); - - /* send even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /* ...and even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /* ...and even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /* ...and even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - - /* send ACKs for data2 and data3 */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 12, TCP_ACK); - EXPECT_RET(p != NULL); - test_tcp_input(p, &netif); - /*EXPECT_RET(txcounters.num_tx_calls == 0);*/ - - /* ...and even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - /* ...and even more data */ - err = tcp_write(pcb, data5, sizeof(data5), TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - -#if 0 - /* create expected segment */ - p1 = tcp_create_rx_segment(pcb, counters.expected_data, data_len, 0, 0, 0); - EXPECT_RET(p != NULL); - if (p != NULL) { - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT_RET(counters.close_calls == 0); - EXPECT_RET(counters.recv_calls == 1); - EXPECT_RET(counters.recved_bytes == data_len); - EXPECT_RET(counters.err_calls == 0); - } -#endif - /* make sure the pcb is freed */ - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - -static u8_t tx_data[TCP_WND*2]; - -static void -check_seqnos(struct tcp_seg *segs, int num_expected, u32_t *seqnos_expected) -{ - struct tcp_seg *s = segs; - int i; - for (i = 0; i < num_expected; i++, s = s->next) { - EXPECT_RET(s != NULL); - EXPECT(s->tcphdr->seqno == htonl(seqnos_expected[i])); - } - EXPECT(s == NULL); -} - -/** Send data with sequence numbers that wrap around the u32_t range. - * Then, provoke fast retransmission by duplicate ACKs and check that all - * segment lists are still properly sorted. */ -START_TEST(test_tcp_fast_rexmit_wraparound) -{ - struct netif netif; - struct test_tcp_txcounters txcounters; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf* p; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - err_t err; -#define SEQNO1 (0xFFFFFF00 - TCP_MSS) -#define ISS 6510 - u16_t i, sent_total = 0; - u32_t seqnos[] = { - SEQNO1, - SEQNO1 + (1 * TCP_MSS), - SEQNO1 + (2 * TCP_MSS), - SEQNO1 + (3 * TCP_MSS), - SEQNO1 + (4 * TCP_MSS), - SEQNO1 + (5 * TCP_MSS)}; - LWIP_UNUSED_ARG(_i); - - for (i = 0; i < sizeof(tx_data); i++) { - tx_data[i] = (u8_t)i; - } - - /* initialize local vars */ - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - memset(&counters, 0, sizeof(counters)); - - /* create and initialize the pcb */ - tcp_ticks = SEQNO1 - ISS; - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->mss = TCP_MSS; - /* disable initial congestion window (we don't send a SYN here...) */ - pcb->cwnd = 2*TCP_MSS; - /* start in congestion advoidance */ - pcb->ssthresh = pcb->cwnd; - - /* send 6 mss-sized segments */ - for (i = 0; i < 6; i++) { - err = tcp_write(pcb, &tx_data[sent_total], TCP_MSS, TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - sent_total += TCP_MSS; - } - check_seqnos(pcb->unsent, 6, seqnos); - EXPECT(pcb->unacked == NULL); - err = tcp_output(pcb); - EXPECT(txcounters.num_tx_calls == 2); - EXPECT(txcounters.num_tx_bytes == 2 * (TCP_MSS + 40U)); - memset(&txcounters, 0, sizeof(txcounters)); - - check_seqnos(pcb->unacked, 2, seqnos); - check_seqnos(pcb->unsent, 4, &seqnos[2]); - - /* ACK the first segment */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, TCP_MSS, TCP_ACK); - test_tcp_input(p, &netif); - /* ensure this didn't trigger a retransmission. Only one - segment should be transmitted because cwnd opened up by - TCP_MSS and a fraction since we are in congestion avoidance */ - EXPECT(txcounters.num_tx_calls == 1); - EXPECT(txcounters.num_tx_bytes == TCP_MSS + 40U); - memset(&txcounters, 0, sizeof(txcounters)); - check_seqnos(pcb->unacked, 2, &seqnos[1]); - check_seqnos(pcb->unsent, 3, &seqnos[3]); - - /* 3 dupacks */ - EXPECT(pcb->dupacks == 0); - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - test_tcp_input(p, &netif); - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(pcb->dupacks == 1); - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - test_tcp_input(p, &netif); - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(pcb->dupacks == 2); - /* 3rd dupack -> fast rexmit */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - test_tcp_input(p, &netif); - EXPECT(pcb->dupacks == 3); - EXPECT(txcounters.num_tx_calls == 4); - memset(&txcounters, 0, sizeof(txcounters)); - EXPECT(pcb->unsent == NULL); - check_seqnos(pcb->unacked, 5, &seqnos[1]); - - /* make sure the pcb is freed */ - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - -/** Send data with sequence numbers that wrap around the u32_t range. - * Then, provoke RTO retransmission and check that all - * segment lists are still properly sorted. */ -START_TEST(test_tcp_rto_rexmit_wraparound) -{ - struct netif netif; - struct test_tcp_txcounters txcounters; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - err_t err; -#define SEQNO1 (0xFFFFFF00 - TCP_MSS) -#define ISS 6510 - u16_t i, sent_total = 0; - u32_t seqnos[] = { - SEQNO1, - SEQNO1 + (1 * TCP_MSS), - SEQNO1 + (2 * TCP_MSS), - SEQNO1 + (3 * TCP_MSS), - SEQNO1 + (4 * TCP_MSS), - SEQNO1 + (5 * TCP_MSS)}; - LWIP_UNUSED_ARG(_i); - - for (i = 0; i < sizeof(tx_data); i++) { - tx_data[i] = (u8_t)i; - } - - /* initialize local vars */ - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - memset(&counters, 0, sizeof(counters)); - - /* create and initialize the pcb */ - tcp_ticks = 0; - tcp_ticks = 0 - tcp_next_iss(NULL); - tcp_ticks = SEQNO1 - tcp_next_iss(NULL); - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->mss = TCP_MSS; - /* disable initial congestion window (we don't send a SYN here...) */ - pcb->cwnd = 2*TCP_MSS; - - /* send 6 mss-sized segments */ - for (i = 0; i < 6; i++) { - err = tcp_write(pcb, &tx_data[sent_total], TCP_MSS, TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - sent_total += TCP_MSS; - } - check_seqnos(pcb->unsent, 6, seqnos); - EXPECT(pcb->unacked == NULL); - err = tcp_output(pcb); - EXPECT(txcounters.num_tx_calls == 2); - EXPECT(txcounters.num_tx_bytes == 2 * (TCP_MSS + 40U)); - memset(&txcounters, 0, sizeof(txcounters)); - - check_seqnos(pcb->unacked, 2, seqnos); - check_seqnos(pcb->unsent, 4, &seqnos[2]); - - /* call the tcp timer some times */ - for (i = 0; i < 10; i++) { - test_tcp_tmr(); - EXPECT(txcounters.num_tx_calls == 0); - } - /* 11th call to tcp_tmr: RTO rexmit fires */ - test_tcp_tmr(); - EXPECT(txcounters.num_tx_calls == 1); - check_seqnos(pcb->unacked, 1, seqnos); - check_seqnos(pcb->unsent, 5, &seqnos[1]); - - /* fake greater cwnd */ - pcb->cwnd = pcb->snd_wnd; - /* send more data */ - err = tcp_output(pcb); - EXPECT(err == ERR_OK); - /* check queues are sorted */ - EXPECT(pcb->unsent == NULL); - check_seqnos(pcb->unacked, 6, seqnos); - - /* make sure the pcb is freed */ - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - -/** Provoke fast retransmission by duplicate ACKs and then recover by ACKing all sent data. - * At the end, send more data. */ -static void test_tcp_tx_full_window_lost(u8_t zero_window_probe_from_unsent) -{ - struct netif netif; - struct test_tcp_txcounters txcounters; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - err_t err; - u16_t sent_total, i; - u8_t expected = 0xFE; - - for (i = 0; i < sizeof(tx_data); i++) { - u8_t d = (u8_t)i; - if (d == 0xFE) { - d = 0xF0; - } - tx_data[i] = d; - } - if (zero_window_probe_from_unsent) { - tx_data[TCP_WND] = expected; - } else { - tx_data[0] = expected; - } - - /* initialize local vars */ - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, &txcounters, &local_ip, &netmask); - memset(&counters, 0, sizeof(counters)); - memset(&txcounters, 0, sizeof(txcounters)); - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->mss = TCP_MSS; - /* disable initial congestion window (we don't send a SYN here...) */ - pcb->cwnd = pcb->snd_wnd; - - /* send a full window (minus 1 packets) of TCP data in MSS-sized chunks */ - sent_total = 0; - if ((TCP_WND - TCP_MSS) % TCP_MSS != 0) { - u16_t initial_data_len = (TCP_WND - TCP_MSS) % TCP_MSS; - err = tcp_write(pcb, &tx_data[sent_total], initial_data_len, TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT(txcounters.num_tx_calls == 1); - EXPECT(txcounters.num_tx_bytes == initial_data_len + 40U); - memset(&txcounters, 0, sizeof(txcounters)); - sent_total += initial_data_len; - } - for (; sent_total < (TCP_WND - TCP_MSS); sent_total += TCP_MSS) { - err = tcp_write(pcb, &tx_data[sent_total], TCP_MSS, TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT(txcounters.num_tx_calls == 1); - EXPECT(txcounters.num_tx_bytes == TCP_MSS + 40U); - memset(&txcounters, 0, sizeof(txcounters)); - } - EXPECT(sent_total == (TCP_WND - TCP_MSS)); - - /* now ACK the packet before the first */ - p = tcp_create_rx_segment(pcb, NULL, 0, 0, 0, TCP_ACK); - test_tcp_input(p, &netif); - /* ensure this didn't trigger a retransmission */ - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(txcounters.num_tx_bytes == 0); - - EXPECT(pcb->persist_backoff == 0); - /* send the last packet, now a complete window has been sent */ - err = tcp_write(pcb, &tx_data[sent_total], TCP_MSS, TCP_WRITE_FLAG_COPY); - sent_total += TCP_MSS; - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT(txcounters.num_tx_calls == 1); - EXPECT(txcounters.num_tx_bytes == TCP_MSS + 40U); - memset(&txcounters, 0, sizeof(txcounters)); - EXPECT(pcb->persist_backoff == 0); - - if (zero_window_probe_from_unsent) { - /* ACK all data but close the TX window */ - p = tcp_create_rx_segment_wnd(pcb, NULL, 0, 0, TCP_WND, TCP_ACK, 0); - test_tcp_input(p, &netif); - /* ensure this didn't trigger any transmission */ - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(txcounters.num_tx_bytes == 0); - EXPECT(pcb->persist_backoff == 1); - } - - /* send one byte more (out of window) -> persist timer starts */ - err = tcp_write(pcb, &tx_data[sent_total], 1, TCP_WRITE_FLAG_COPY); - EXPECT_RET(err == ERR_OK); - err = tcp_output(pcb); - EXPECT_RET(err == ERR_OK); - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(txcounters.num_tx_bytes == 0); - memset(&txcounters, 0, sizeof(txcounters)); - if (!zero_window_probe_from_unsent) { - /* no persist timer unless a zero window announcement has been received */ - EXPECT(pcb->persist_backoff == 0); - } else { - EXPECT(pcb->persist_backoff == 1); - - /* call tcp_timer some more times to let persist timer count up */ - for (i = 0; i < 4; i++) { - test_tcp_tmr(); - EXPECT(txcounters.num_tx_calls == 0); - EXPECT(txcounters.num_tx_bytes == 0); - } - - /* this should trigger the zero-window-probe */ - txcounters.copy_tx_packets = 1; - test_tcp_tmr(); - txcounters.copy_tx_packets = 0; - EXPECT(txcounters.num_tx_calls == 1); - EXPECT(txcounters.num_tx_bytes == 1 + 40U); - EXPECT(txcounters.tx_packets != NULL); - if (txcounters.tx_packets != NULL) { - u8_t sent; - u16_t ret; - ret = pbuf_copy_partial(txcounters.tx_packets, &sent, 1, 40U); - EXPECT(ret == 1); - EXPECT(sent == expected); - } - if (txcounters.tx_packets != NULL) { - pbuf_free(txcounters.tx_packets); - txcounters.tx_packets = NULL; - } - } - - /* make sure the pcb is freed */ - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT_RET(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} - -START_TEST(test_tcp_tx_full_window_lost_from_unsent) -{ - LWIP_UNUSED_ARG(_i); - test_tcp_tx_full_window_lost(1); -} -END_TEST - -START_TEST(test_tcp_tx_full_window_lost_from_unacked) -{ - LWIP_UNUSED_ARG(_i); - test_tcp_tx_full_window_lost(0); -} -END_TEST - -/** Create the suite including all tests for this module */ -Suite * -tcp_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_tcp_new_abort), - TESTFUNC(test_tcp_recv_inseq), - TESTFUNC(test_tcp_malformed_header), - TESTFUNC(test_tcp_fast_retx_recover), - TESTFUNC(test_tcp_fast_rexmit_wraparound), - TESTFUNC(test_tcp_rto_rexmit_wraparound), - TESTFUNC(test_tcp_tx_full_window_lost_from_unacked), - TESTFUNC(test_tcp_tx_full_window_lost_from_unsent) - }; - return create_suite("TCP", tests, sizeof(tests)/sizeof(testfunc), tcp_setup, tcp_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.h deleted file mode 100644 index f28ee56530e92fe34af900d30ddc694799163b1e..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_TCP_H -#define LWIP_HDR_TEST_TCP_H - -#include "../lwip_check.h" - -Suite *tcp_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.c deleted file mode 100644 index be61172251e7860501246fa03c6e22e6cd8e008a..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.c +++ /dev/null @@ -1,1049 +0,0 @@ -#include "test_tcp_oos.h" - -#include "lwip/priv/tcp_priv.h" -#include "lwip/stats.h" -#include "tcp_helper.h" - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif -#if !TCP_QUEUE_OOSEQ -#error "This tests needs TCP_QUEUE_OOSEQ enabled" -#endif - -/** CHECK_SEGMENTS_ON_OOSEQ: - * 1: check count, seqno and len of segments on pcb->ooseq (strict) - * 0: only check that bytes are received in correct order (less strict) */ -#define CHECK_SEGMENTS_ON_OOSEQ 1 - -#if CHECK_SEGMENTS_ON_OOSEQ -#define EXPECT_OOSEQ(x) EXPECT(x) -#else -#define EXPECT_OOSEQ(x) -#endif - -/* helper functions */ - -/** Get the numbers of segments on the ooseq list */ -static int tcp_oos_count(struct tcp_pcb* pcb) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - while(seg != NULL) { - num++; - seg = seg->next; - } - return num; -} - -#if TCP_OOSEQ_MAX_PBUFS && (TCP_OOSEQ_MAX_PBUFS < ((TCP_WND / TCP_MSS) + 1)) && (PBUF_POOL_BUFSIZE >= (TCP_MSS + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) -/** Get the numbers of pbufs on the ooseq list */ -static int tcp_oos_pbuf_count(struct tcp_pcb* pcb) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - while(seg != NULL) { - num += pbuf_clen(seg->p); - seg = seg->next; - } - return num; -} -#endif - -/** Get the seqno of a segment (by index) on the ooseq list - * - * @param pcb the pcb to check for ooseq segments - * @param seg_index index of the segment on the ooseq list - * @return seqno of the segment - */ -static u32_t -tcp_oos_seg_seqno(struct tcp_pcb* pcb, int seg_index) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - - /* then check the actual segment */ - while(seg != NULL) { - if(num == seg_index) { - return seg->tcphdr->seqno; - } - num++; - seg = seg->next; - } - fail(); - return 0; -} - -/** Get the tcplen (datalen + SYN/FIN) of a segment (by index) on the ooseq list - * - * @param pcb the pcb to check for ooseq segments - * @param seg_index index of the segment on the ooseq list - * @return tcplen of the segment - */ -static int -tcp_oos_seg_tcplen(struct tcp_pcb* pcb, int seg_index) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - - /* then check the actual segment */ - while(seg != NULL) { - if(num == seg_index) { - return TCP_TCPLEN(seg); - } - num++; - seg = seg->next; - } - fail(); - return -1; -} - -/** Get the tcplen (datalen + SYN/FIN) of all segments on the ooseq list - * - * @param pcb the pcb to check for ooseq segments - * @return tcplen of all segment - */ -static int -tcp_oos_tcplen(struct tcp_pcb* pcb) -{ - int len = 0; - struct tcp_seg* seg = pcb->ooseq; - - /* then check the actual segment */ - while(seg != NULL) { - len += TCP_TCPLEN(seg); - seg = seg->next; - } - return len; -} - -/* Setup/teardown functions */ - -static void -tcp_oos_setup(void) -{ - tcp_remove_all(); -} - -static void -tcp_oos_teardown(void) -{ - tcp_remove_all(); - netif_list = NULL; - netif_default = NULL; -} - - - -/* Test functions */ - -/** create multiple segments and pass them to tcp_input in a wrong - * order to see if ooseq-caching works correctly - * FIN is received in out-of-sequence segments only */ -START_TEST(test_tcp_recv_ooseq_FIN_OOSEQ) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_8_9, *p_4_8, *p_4_10, *p_2_14, *p_fin, *pinseq; - char data[] = { - 1, 2, 3, 4, - 5, 6, 7, 8, - 9, 10, 11, 12, - 13, 14, 15, 16}; - ip_addr_t remote_ip, local_ip, netmask; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create segments */ - /* pinseq is sent as last segment! */ - pinseq = tcp_create_rx_segment(pcb, &data[0], 4, 0, 0, TCP_ACK); - /* p1: 8 bytes before FIN */ - /* seqno: 8..16 */ - p_8_9 = tcp_create_rx_segment(pcb, &data[8], 8, 8, 0, TCP_ACK|TCP_FIN); - /* p2: 4 bytes before p1, including the first 4 bytes of p1 (partly duplicate) */ - /* seqno: 4..11 */ - p_4_8 = tcp_create_rx_segment(pcb, &data[4], 8, 4, 0, TCP_ACK); - /* p3: same as p2 but 2 bytes longer */ - /* seqno: 4..13 */ - p_4_10 = tcp_create_rx_segment(pcb, &data[4], 10, 4, 0, TCP_ACK); - /* p4: 14 bytes before FIN, includes data from p1 and p2, plus partly from pinseq */ - /* seqno: 2..15 */ - p_2_14 = tcp_create_rx_segment(pcb, &data[2], 14, 2, 0, TCP_ACK); - /* FIN, seqno 16 */ - p_fin = tcp_create_rx_segment(pcb, NULL, 0,16, 0, TCP_ACK|TCP_FIN); - EXPECT(pinseq != NULL); - EXPECT(p_8_9 != NULL); - EXPECT(p_4_8 != NULL); - EXPECT(p_4_10 != NULL); - EXPECT(p_2_14 != NULL); - EXPECT(p_fin != NULL); - if ((pinseq != NULL) && (p_8_9 != NULL) && (p_4_8 != NULL) && (p_4_10 != NULL) && (p_2_14 != NULL) && (p_fin != NULL)) { - /* pass the segment to tcp_input */ - test_tcp_input(p_8_9, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - test_tcp_input(p_4_8, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - test_tcp_input(p_4_10, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - test_tcp_input(p_2_14, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 15); /* includes FIN */ - - /* pass the segment to tcp_input */ - test_tcp_input(p_fin, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 15); /* includes FIN */ - - /* pass the segment to tcp_input */ - test_tcp_input(pinseq, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 1); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - } - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - - -/** create multiple segments and pass them to tcp_input in a wrong - * order to see if ooseq-caching works correctly - * FIN is received IN-SEQUENCE at the end */ -START_TEST(test_tcp_recv_ooseq_FIN_INSEQ) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_1_2, *p_4_8, *p_3_11, *p_2_12, *p_15_1, *p_15_1a, *pinseq, *pinseqFIN; - char data[] = { - 1, 2, 3, 4, - 5, 6, 7, 8, - 9, 10, 11, 12, - 13, 14, 15, 16}; - ip_addr_t remote_ip, local_ip, netmask; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create segments */ - /* p1: 7 bytes - 2 before FIN */ - /* seqno: 1..2 */ - p_1_2 = tcp_create_rx_segment(pcb, &data[1], 2, 1, 0, TCP_ACK); - /* p2: 4 bytes before p1, including the first 4 bytes of p1 (partly duplicate) */ - /* seqno: 4..11 */ - p_4_8 = tcp_create_rx_segment(pcb, &data[4], 8, 4, 0, TCP_ACK); - /* p3: same as p2 but 2 bytes longer and one byte more at the front */ - /* seqno: 3..13 */ - p_3_11 = tcp_create_rx_segment(pcb, &data[3], 11, 3, 0, TCP_ACK); - /* p4: 13 bytes - 2 before FIN - should be ignored as contained in p1 and p3 */ - /* seqno: 2..13 */ - p_2_12 = tcp_create_rx_segment(pcb, &data[2], 12, 2, 0, TCP_ACK); - /* pinseq is the first segment that is held back to create ooseq! */ - /* seqno: 0..3 */ - pinseq = tcp_create_rx_segment(pcb, &data[0], 4, 0, 0, TCP_ACK); - /* p5: last byte before FIN */ - /* seqno: 15 */ - p_15_1 = tcp_create_rx_segment(pcb, &data[15], 1, 15, 0, TCP_ACK); - /* p6: same as p5, should be ignored */ - p_15_1a= tcp_create_rx_segment(pcb, &data[15], 1, 15, 0, TCP_ACK); - /* pinseqFIN: last 2 bytes plus FIN */ - /* only segment containing seqno 14 and FIN */ - pinseqFIN = tcp_create_rx_segment(pcb, &data[14], 2, 14, 0, TCP_ACK|TCP_FIN); - EXPECT(pinseq != NULL); - EXPECT(p_1_2 != NULL); - EXPECT(p_4_8 != NULL); - EXPECT(p_3_11 != NULL); - EXPECT(p_2_12 != NULL); - EXPECT(p_15_1 != NULL); - EXPECT(p_15_1a != NULL); - EXPECT(pinseqFIN != NULL); - if ((pinseq != NULL) && (p_1_2 != NULL) && (p_4_8 != NULL) && (p_3_11 != NULL) && (p_2_12 != NULL) - && (p_15_1 != NULL) && (p_15_1a != NULL) && (pinseqFIN != NULL)) { - /* pass the segment to tcp_input */ - test_tcp_input(p_1_2, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - - /* pass the segment to tcp_input */ - test_tcp_input(p_4_8, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 8); - - /* pass the segment to tcp_input */ - test_tcp_input(p_3_11, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - /* p_3_11 has removed p_4_8 from ooseq */ - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 3); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 11); - - /* pass the segment to tcp_input */ - test_tcp_input(p_2_12, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 12); - - /* pass the segment to tcp_input */ - test_tcp_input(pinseq, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - - /* pass the segment to tcp_input */ - test_tcp_input(p_15_1, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 15); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - - /* pass the segment to tcp_input */ - test_tcp_input(p_15_1a, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - /* check ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 15); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - - /* pass the segment to tcp_input */ - test_tcp_input(pinseqFIN, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 1); - EXPECT(counters.recv_calls == 2); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - } - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} -END_TEST - -static char data_full_wnd[TCP_WND + TCP_MSS]; - -/** create multiple segments and pass them to tcp_input with the first segment missing - * to simulate overruning the rxwin with ooseq queueing enabled */ -START_TEST(test_tcp_recv_ooseq_overrun_rxwin) -{ -#if !TCP_OOSEQ_MAX_BYTES && !TCP_OOSEQ_MAX_PBUFS - int i, k; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *pinseq, *p_ovr; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - int datalen = 0; - int datalen2; - - for(i = 0; i < (int)sizeof(data_full_wnd); i++) { - data_full_wnd[i] = (char)i; - } - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = TCP_WND; - counters.expected_data = data_full_wnd; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->rcv_nxt = 0x8000; - - /* create segments */ - /* pinseq is sent as last segment! */ - pinseq = tcp_create_rx_segment(pcb, &data_full_wnd[0], TCP_MSS, 0, 0, TCP_ACK); - - for(i = TCP_MSS, k = 0; i < TCP_WND; i += TCP_MSS, k++) { - int count, expected_datalen; - struct pbuf *p = tcp_create_rx_segment(pcb, &data_full_wnd[TCP_MSS*(k+1)], - TCP_MSS, TCP_MSS*(k+1), 0, TCP_ACK); - EXPECT_RET(p != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - count = tcp_oos_count(pcb); - EXPECT_OOSEQ(count == k+1); - datalen = tcp_oos_tcplen(pcb); - if (i + TCP_MSS < TCP_WND) { - expected_datalen = (k+1)*TCP_MSS; - } else { - expected_datalen = TCP_WND - TCP_MSS; - } - if (datalen != expected_datalen) { - EXPECT_OOSEQ(datalen == expected_datalen); - } - } - - /* pass in one more segment, cleary overrunning the rxwin */ - p_ovr = tcp_create_rx_segment(pcb, &data_full_wnd[TCP_MSS*(k+1)], TCP_MSS, TCP_MSS*(k+1), 0, TCP_ACK); - EXPECT_RET(p_ovr != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p_ovr, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == k); - datalen2 = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen == datalen2); - - /* now pass inseq */ - test_tcp_input(pinseq, &netif); - EXPECT(pcb->ooseq == NULL); - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -#endif /* !TCP_OOSEQ_MAX_BYTES && !TCP_OOSEQ_MAX_PBUFS */ - LWIP_UNUSED_ARG(_i); -} -END_TEST - -/** similar to above test, except seqno starts near the max rxwin */ -START_TEST(test_tcp_recv_ooseq_overrun_rxwin_edge) -{ -#if !TCP_OOSEQ_MAX_BYTES && !TCP_OOSEQ_MAX_PBUFS - int i, k; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *pinseq, *p_ovr; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - int datalen = 0; - int datalen2; - - for(i = 0; i < (int)sizeof(data_full_wnd); i++) { - data_full_wnd[i] = (char)i; - } - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = TCP_WND; - counters.expected_data = data_full_wnd; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->rcv_nxt = 0xffffffff - (TCP_WND / 2); - - /* create segments */ - /* pinseq is sent as last segment! */ - pinseq = tcp_create_rx_segment(pcb, &data_full_wnd[0], TCP_MSS, 0, 0, TCP_ACK); - - for(i = TCP_MSS, k = 0; i < TCP_WND; i += TCP_MSS, k++) { - int count, expected_datalen; - struct pbuf *p = tcp_create_rx_segment(pcb, &data_full_wnd[TCP_MSS*(k+1)], - TCP_MSS, TCP_MSS*(k+1), 0, TCP_ACK); - EXPECT_RET(p != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - count = tcp_oos_count(pcb); - EXPECT_OOSEQ(count == k+1); - datalen = tcp_oos_tcplen(pcb); - if (i + TCP_MSS < TCP_WND) { - expected_datalen = (k+1)*TCP_MSS; - } else { - expected_datalen = TCP_WND - TCP_MSS; - } - if (datalen != expected_datalen) { - EXPECT_OOSEQ(datalen == expected_datalen); - } - } - - /* pass in one more segment, cleary overrunning the rxwin */ - p_ovr = tcp_create_rx_segment(pcb, &data_full_wnd[TCP_MSS*(k+1)], TCP_MSS, TCP_MSS*(k+1), 0, TCP_ACK); - EXPECT_RET(p_ovr != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p_ovr, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == k); - datalen2 = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen == datalen2); - - /* now pass inseq */ - test_tcp_input(pinseq, &netif); - EXPECT(pcb->ooseq == NULL); - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -#endif /* !TCP_OOSEQ_MAX_BYTES && !TCP_OOSEQ_MAX_PBUFS */ - LWIP_UNUSED_ARG(_i); -} -END_TEST - -START_TEST(test_tcp_recv_ooseq_max_bytes) -{ -#if TCP_OOSEQ_MAX_BYTES && (TCP_OOSEQ_MAX_BYTES < (TCP_WND + 1)) && (PBUF_POOL_BUFSIZE >= (TCP_MSS + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) - int i, k; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_ovr; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - int datalen = 0; - int datalen2; - - for(i = 0; i < sizeof(data_full_wnd); i++) { - data_full_wnd[i] = (char)i; - } - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = TCP_WND; - counters.expected_data = data_full_wnd; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->rcv_nxt = 0x8000; - - /* don't 'recv' the first segment (1 byte) so that all other segments will be ooseq */ - - /* create segments and 'recv' them */ - for(k = 1, i = 1; k < TCP_OOSEQ_MAX_BYTES; k += TCP_MSS, i++) { - int count; - struct pbuf *p = tcp_create_rx_segment(pcb, &data_full_wnd[k], - TCP_MSS, k, 0, TCP_ACK); - EXPECT_RET(p != NULL); - EXPECT_RET(p->next == NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - count = tcp_oos_pbuf_count(pcb); - EXPECT_OOSEQ(count == i); - datalen = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen == (i * TCP_MSS)); - } - - /* pass in one more segment, overrunning the limit */ - p_ovr = tcp_create_rx_segment(pcb, &data_full_wnd[k+1], 1, k+1, 0, TCP_ACK); - EXPECT_RET(p_ovr != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p_ovr, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue (ensure the new segment was not accepted) */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == (i-1)); - datalen2 = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen2 == ((i-1) * TCP_MSS)); - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -#endif /* TCP_OOSEQ_MAX_BYTES && (TCP_OOSEQ_MAX_BYTES < (TCP_WND + 1)) && (PBUF_POOL_BUFSIZE >= (TCP_MSS + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) */ - LWIP_UNUSED_ARG(_i); -} -END_TEST - -START_TEST(test_tcp_recv_ooseq_max_pbufs) -{ -#if TCP_OOSEQ_MAX_PBUFS && (TCP_OOSEQ_MAX_PBUFS < ((TCP_WND / TCP_MSS) + 1)) && (PBUF_POOL_BUFSIZE >= (TCP_MSS + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) - int i; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_ovr; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - int datalen = 0; - int datalen2; - - for(i = 0; i < sizeof(data_full_wnd); i++) { - data_full_wnd[i] = (char)i; - } - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = TCP_WND; - counters.expected_data = data_full_wnd; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->rcv_nxt = 0x8000; - - /* don't 'recv' the first segment (1 byte) so that all other segments will be ooseq */ - - /* create segments and 'recv' them */ - for(i = 1; i <= TCP_OOSEQ_MAX_PBUFS; i++) { - int count; - struct pbuf *p = tcp_create_rx_segment(pcb, &data_full_wnd[i], - 1, i, 0, TCP_ACK); - EXPECT_RET(p != NULL); - EXPECT_RET(p->next == NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - count = tcp_oos_pbuf_count(pcb); - EXPECT_OOSEQ(count == i); - datalen = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen == i); - } - - /* pass in one more segment, overrunning the limit */ - p_ovr = tcp_create_rx_segment(pcb, &data_full_wnd[i+1], 1, i+1, 0, TCP_ACK); - EXPECT_RET(p_ovr != NULL); - /* pass the segment to tcp_input */ - test_tcp_input(p_ovr, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue (ensure the new segment was not accepted) */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == (i-1)); - datalen2 = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(datalen2 == (i-1)); - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -#endif /* TCP_OOSEQ_MAX_PBUFS && (TCP_OOSEQ_MAX_BYTES < (TCP_WND + 1)) && (PBUF_POOL_BUFSIZE >= (TCP_MSS + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) */ - LWIP_UNUSED_ARG(_i); -} -END_TEST - -static void -check_rx_counters(struct tcp_pcb *pcb, struct test_tcp_counters *counters, u32_t exp_close_calls, u32_t exp_rx_calls, - u32_t exp_rx_bytes, u32_t exp_err_calls, int exp_oos_count, int exp_oos_len) -{ - int oos_len; - EXPECT(counters->close_calls == exp_close_calls); - EXPECT(counters->recv_calls == exp_rx_calls); - EXPECT(counters->recved_bytes == exp_rx_bytes); - EXPECT(counters->err_calls == exp_err_calls); - /* check that pbuf is queued in ooseq */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == exp_oos_count); - oos_len = tcp_oos_tcplen(pcb); - EXPECT_OOSEQ(exp_oos_len == oos_len); -} - -/* this test uses 4 packets: - * - data (len=TCP_MSS) - * - FIN - * - data after FIN (len=1) (invalid) - * - 2nd FIN (invalid) - * - * the parameter 'delay_packet' is a bitmask that choses which on these packets is ooseq - */ -static void test_tcp_recv_ooseq_double_FINs(int delay_packet) -{ - int i, k; - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_normal_fin, *p_data_after_fin, *p, *p_2nd_fin_ooseq; - ip_addr_t remote_ip, local_ip, netmask; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - u32_t exp_rx_calls = 0, exp_rx_bytes = 0, exp_close_calls = 0, exp_oos_pbufs = 0, exp_oos_tcplen = 0; - int first_dropped = 0xff; - - for(i = 0; i < (int)sizeof(data_full_wnd); i++) { - data_full_wnd[i] = (char)i; - } - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP_ADDR4(&local_ip, 192, 168, 1, 1); - IP_ADDR4(&remote_ip, 192, 168, 1, 2); - IP_ADDR4(&netmask, 255, 255, 255, 0); - test_tcp_init_netif(&netif, NULL, &local_ip, &netmask); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = TCP_WND; - counters.expected_data = data_full_wnd; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - pcb->rcv_nxt = 0x8000; - - /* create segments */ - p = tcp_create_rx_segment(pcb, &data_full_wnd[0], TCP_MSS, 0, 0, TCP_ACK); - p_normal_fin = tcp_create_rx_segment(pcb, NULL, 0, TCP_MSS, 0, TCP_ACK|TCP_FIN); - k = 1; - p_data_after_fin = tcp_create_rx_segment(pcb, &data_full_wnd[TCP_MSS+1], k, TCP_MSS+1, 0, TCP_ACK); - p_2nd_fin_ooseq = tcp_create_rx_segment(pcb, NULL, 0, TCP_MSS+1+k, 0, TCP_ACK|TCP_FIN); - - if(delay_packet & 1) { - /* drop normal data */ - first_dropped = 1; - } else { - /* send normal data */ - test_tcp_input(p, &netif); - exp_rx_calls++; - exp_rx_bytes += TCP_MSS; - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 2) { - /* drop FIN */ - if(first_dropped > 2) { - first_dropped = 2; - } - } else { - /* send FIN */ - test_tcp_input(p_normal_fin, &netif); - if (first_dropped < 2) { - /* already dropped packets, this one is ooseq */ - exp_oos_pbufs++; - exp_oos_tcplen++; - } else { - /* inseq */ - exp_close_calls++; - } - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 4) { - /* drop data-after-FIN */ - if(first_dropped > 3) { - first_dropped = 3; - } - } else { - /* send data-after-FIN */ - test_tcp_input(p_data_after_fin, &netif); - if (first_dropped < 3) { - /* already dropped packets, this one is ooseq */ - if (delay_packet & 2) { - /* correct FIN was ooseq */ - exp_oos_pbufs++; - exp_oos_tcplen += k; - } - } else { - /* inseq: no change */ - } - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 8) { - /* drop 2nd-FIN */ - if(first_dropped > 4) { - first_dropped = 4; - } - } else { - /* send 2nd-FIN */ - test_tcp_input(p_2nd_fin_ooseq, &netif); - if (first_dropped < 3) { - /* already dropped packets, this one is ooseq */ - if (delay_packet & 2) { - /* correct FIN was ooseq */ - exp_oos_pbufs++; - exp_oos_tcplen++; - } - } else { - /* inseq: no change */ - } - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 1) { - /* dropped normal data before */ - test_tcp_input(p, &netif); - exp_rx_calls++; - exp_rx_bytes += TCP_MSS; - if((delay_packet & 2) == 0) { - /* normal FIN was NOT delayed */ - exp_close_calls++; - exp_oos_pbufs = exp_oos_tcplen = 0; - } - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 2) { - /* dropped normal FIN before */ - test_tcp_input(p_normal_fin, &netif); - exp_close_calls++; - exp_oos_pbufs = exp_oos_tcplen = 0; - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 4) { - /* dropped data-after-FIN before */ - test_tcp_input(p_data_after_fin, &netif); - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - if(delay_packet & 8) { - /* dropped 2nd-FIN before */ - test_tcp_input(p_2nd_fin_ooseq, &netif); - } - /* check if counters are as expected */ - check_rx_counters(pcb, &counters, exp_close_calls, exp_rx_calls, exp_rx_bytes, 0, exp_oos_pbufs, exp_oos_tcplen); - - /* check that ooseq data has been dumped */ - EXPECT(pcb->ooseq == NULL); - - /* make sure the pcb is freed */ - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 1); - tcp_abort(pcb); - EXPECT(MEMP_STATS_GET(used, MEMP_TCP_PCB) == 0); -} - -/** create multiple segments and pass them to tcp_input with the first segment missing - * to simulate overruning the rxwin with ooseq queueing enabled */ -#define FIN_TEST(name, num) \ - START_TEST(name) \ - { \ - LWIP_UNUSED_ARG(_i); \ - test_tcp_recv_ooseq_double_FINs(num); \ - } \ - END_TEST -FIN_TEST(test_tcp_recv_ooseq_double_FIN_0, 0) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_1, 1) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_2, 2) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_3, 3) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_4, 4) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_5, 5) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_6, 6) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_7, 7) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_8, 8) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_9, 9) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_10, 10) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_11, 11) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_12, 12) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_13, 13) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_14, 14) -FIN_TEST(test_tcp_recv_ooseq_double_FIN_15, 15) - - -/** Create the suite including all tests for this module */ -Suite * -tcp_oos_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_tcp_recv_ooseq_FIN_OOSEQ), - TESTFUNC(test_tcp_recv_ooseq_FIN_INSEQ), - TESTFUNC(test_tcp_recv_ooseq_overrun_rxwin), - TESTFUNC(test_tcp_recv_ooseq_overrun_rxwin_edge), - TESTFUNC(test_tcp_recv_ooseq_max_bytes), - TESTFUNC(test_tcp_recv_ooseq_max_pbufs), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_0), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_1), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_2), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_3), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_4), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_5), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_6), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_7), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_8), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_9), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_10), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_11), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_12), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_13), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_14), - TESTFUNC(test_tcp_recv_ooseq_double_FIN_15) - }; - return create_suite("TCP_OOS", tests, sizeof(tests)/sizeof(testfunc), tcp_oos_setup, tcp_oos_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.h deleted file mode 100644 index 5b82013b73bc7b5f552dc8f110a6ab7cd4ffa0d4..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/tcp/test_tcp_oos.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_TCP_OOS_H -#define LWIP_HDR_TEST_TCP_OOS_H - -#include "../lwip_check.h" - -Suite *tcp_oos_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.c deleted file mode 100644 index 147822f49240227014c2cd7d568f0aee323ad014..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.c +++ /dev/null @@ -1,68 +0,0 @@ -#include "test_udp.h" - -#include "lwip/udp.h" -#include "lwip/stats.h" - -#if !LWIP_STATS || !UDP_STATS || !MEMP_STATS -#error "This tests needs UDP- and MEMP-statistics enabled" -#endif - -/* Helper functions */ -static void -udp_remove_all(void) -{ - struct udp_pcb *pcb = udp_pcbs; - struct udp_pcb *pcb2; - - while(pcb != NULL) { - pcb2 = pcb; - pcb = pcb->next; - udp_remove(pcb2); - } - fail_unless(MEMP_STATS_GET(used, MEMP_UDP_PCB) == 0); -} - -/* Setups/teardown functions */ - -static void -udp_setup(void) -{ - udp_remove_all(); -} - -static void -udp_teardown(void) -{ - udp_remove_all(); -} - - -/* Test functions */ - -START_TEST(test_udp_new_remove) -{ - struct udp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - fail_unless(MEMP_STATS_GET(used, MEMP_UDP_PCB) == 0); - - pcb = udp_new(); - fail_unless(pcb != NULL); - if (pcb != NULL) { - fail_unless(MEMP_STATS_GET(used, MEMP_UDP_PCB) == 1); - udp_remove(pcb); - fail_unless(MEMP_STATS_GET(used, MEMP_UDP_PCB) == 0); - } -} -END_TEST - - -/** Create the suite including all tests for this module */ -Suite * -udp_suite(void) -{ - testfunc tests[] = { - TESTFUNC(test_udp_new_remove), - }; - return create_suite("UDP", tests, sizeof(tests)/sizeof(testfunc), udp_setup, udp_teardown); -} diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.h b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.h deleted file mode 100644 index 5426bf42e7263cfbbdda3374c9831fdc632c0892..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/unit/udp/test_udp.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef LWIP_HDR_TEST_UDP_H -#define LWIP_HDR_TEST_UDP_H - -#include "../lwip_check.h" - -Suite* udp_suite(void); - -#endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/tcp_server.c b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/tcp_server.c index 38730f853925713a4603d0c06c976b7a81b608a2..99db37cf081edfedde6b1b738926461f68b2ab5a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/tcp_server.c +++ b/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/tcp_server.c @@ -101,7 +101,7 @@ exit: tcp_server_log( "TCP client thread exit with err: %d", err ); if ( buf != NULL ) - os_free( buf ); + os_free_loose( buf ); close( fd ); rtos_delete_thread( NULL ); diff --git a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/inc/tls_config.h b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/inc/tls_config.h index 4a83cceb4c0f53df6ab601504b91a17f040256b0..4319b7bb12e0d95ef69d1eb3d0275af2b7e37ee5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/inc/tls_config.h +++ b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/inc/tls_config.h @@ -197,7 +197,7 @@ extern void tls_mbedtls_mem_free(void *ptr); #include "mbedtls/check_config.h" #define tls_malloc os_malloc -#define tls_free os_free +#define tls_free os_free_loose #define tls_realloc os_realloc #define tls_calloc os_calloc @@ -2904,7 +2904,7 @@ extern void tls_mbedtls_mem_free(void *ptr); #include "check_config.h" #define tls_malloc os_malloc -#define tls_free os_free +#define tls_free os_free_loose #define tls_realloc os_realloc #define tls_calloc os_calloc #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/src/tls_mem.c b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/src/tls_mem.c index b0b0deeef2f00c367e49fd88c474f4b3d2332e98..fb31d28e9353e8a3bde7d9ed4a2c83cbf2095dd6 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/src/tls_mem.c +++ b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls-port/src/tls_mem.c @@ -14,7 +14,7 @@ void *tls_mbedtls_mem_calloc(size_t n, size_t size) void tls_mbedtls_mem_free(void *ptr) { - os_free(ptr); + os_free_loose(ptr); } #endif /* !MBEDTLS_PLATFORM_MEMORY */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/include/mbedtls/platform.h b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/include/mbedtls/platform.h index 78fd329e322e710bbd09f9628cec074869c60338..dc53b7996aacca83a7a934aa497b2dba34b2dd69 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/include/mbedtls/platform.h +++ b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/include/mbedtls/platform.h @@ -126,7 +126,7 @@ int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ), void (*free_func)( void * ) ); #endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */ #else /* !MBEDTLS_PLATFORM_MEMORY */ -#define mbedtls_free os_free +#define mbedtls_free os_free_loose #define mbedtls_calloc os_calloc #endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/library/ssl_cli.c b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/library/ssl_cli.c index c8c5ff7b767c678543e8310baa36d7fdce6f2cfd..1dbee1bd45ec31ca4c21caf69070b17f88075eff 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/library/ssl_cli.c +++ b/drivers/hal/beken/beken72XX_HAL/func/mbedtls/mbedtls/library/ssl_cli.c @@ -32,7 +32,7 @@ #else #include #define mbedtls_calloc os_calloc -#define mbedtls_free os_free +#define mbedtls_free os_free_loose #endif #include "mbedtls/debug.h" diff --git a/drivers/hal/beken/beken72XX_HAL/func/music_player/Mp3Lib/buffers.c b/drivers/hal/beken/beken72XX_HAL/func/music_player/Mp3Lib/buffers.c index d0b52e78d96c0307a57913a317575a88b3aaff79..f46215c395f096804e49f0eceb966d801541d3e5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/music_player/Mp3Lib/buffers.c +++ b/drivers/hal/beken/beken72XX_HAL/func/music_player/Mp3Lib/buffers.c @@ -232,19 +232,19 @@ void FreeBuffers(MP3DecInfo *mp3DecInfo) return; l2i = (L2DecodeContext *)(mp3DecInfo->L2DecInfo); - os_free(mp3DecInfo->FrameHeaderPS); - os_free(mp3DecInfo->SideInfoPS); - os_free(mp3DecInfo->ScaleFactorInfoPS); - os_free(mp3DecInfo->HuffmanInfoPS); - os_free(mp3DecInfo->DequantInfoPS); + os_free_loose(mp3DecInfo->FrameHeaderPS); + os_free_loose(mp3DecInfo->SideInfoPS); + os_free_loose(mp3DecInfo->ScaleFactorInfoPS); + os_free_loose(mp3DecInfo->HuffmanInfoPS); + os_free_loose(mp3DecInfo->DequantInfoPS); l2i->inbuf = NULL; l2i->inbuf_ptr = NULL; l2i->sb_samples = NULL; - os_free(mp3DecInfo->L2DecInfo); - os_free(mp3DecInfo->IMDCTInfoPS); - os_free(mp3DecInfo->SubbandInfoPS); - os_free(mp3DecInfo); + os_free_loose(mp3DecInfo->L2DecInfo); + os_free_loose(mp3DecInfo->IMDCTInfoPS); + os_free_loose(mp3DecInfo->SubbandInfoPS); + os_free_loose(mp3DecInfo); } #endif /* CONFIG_APP_MP3PLAYER */ //EOF diff --git a/drivers/hal/beken/beken72XX_HAL/func/music_player/app_music.c b/drivers/hal/beken/beken72XX_HAL/func/music_player/app_music.c index b0e5629f9d1b030e614fa166d3ada695f4d11fd1..010f954216467659afed976f514d1923446210b1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/music_player/app_music.c +++ b/drivers/hal/beken/beken72XX_HAL/func/music_player/app_music.c @@ -94,7 +94,7 @@ static void mp3_mem_uninit(void) if(readBuf) { APP_MUSIC_PRT("mp3 mem free 1\r\n"); - os_free(readBuf); + os_free_loose(readBuf); readBuf = NULL; mp3decinfo->mainBuf = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/music_player/fs_fat/ffsystem.c b/drivers/hal/beken/beken72XX_HAL/func/music_player/fs_fat/ffsystem.c index b893dd4ae8240651adad9ff0d6b6c00e04b45ef0..90097b626fadead64b6bdd634e83761df0c4611b 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/music_player/fs_fat/ffsystem.c +++ b/drivers/hal/beken/beken72XX_HAL/func/music_player/fs_fat/ffsystem.c @@ -29,7 +29,7 @@ void ff_memfree ( void* mblock /* Pointer to the memory block to free */ ) { - os_free(mblock); /* Free the memory block with POSIX API */ + os_free_loose(mblock); /* Free the memory block with POSIX API */ } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/net_param_intf/net_param.c b/drivers/hal/beken/beken72XX_HAL/func/net_param_intf/net_param.c index 5790c28967872dfec5ac10cbcd2a1b2a3f04ef1c..d2b64c43739c0dfc1f60cbbe6185bba63d30f52e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/net_param_intf/net_param.c +++ b/drivers/hal/beken/beken72XX_HAL/func/net_param_intf/net_param.c @@ -102,7 +102,7 @@ UINT32 get_info_item(NET_INFO_ITEM item,UINT8 *ptr0,UINT8 *ptr1, UINT8 *ptr2) INFO_ITEM_ST head; bk_logic_partition_t *pt; UINT32 ret = 0; - + if(!search_info_tbl(NULL,&len)) return ret; @@ -159,7 +159,7 @@ UINT32 get_info_item(NET_INFO_ITEM item,UINT8 *ptr0,UINT8 *ptr1, UINT8 *ptr2) ret = 0; break; } - + ddev_close(flash_handle); return ret; @@ -257,7 +257,7 @@ UINT32 save_info_item(NET_INFO_ITEM item,UINT8 *ptr0,UINT8*ptr1,UINT8 *ptr2) bk_flash_write(BK_PARTITION_NET_PARAM,0,tmpptr,cfg_tbl_len); bk_flash_enable_security(FLASH_UNPROTECT_LAST_BLOCK); - os_free(wrbuf); + os_free_loose(wrbuf); return 1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/client/paho_mqtt_udp.c b/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/client/paho_mqtt_udp.c index 9ac8a0a02f58d193aad0eebef7cf5f3f4f6d8e1b..d3488a680bfb132dc23cd97d3e30c076346a2eb8 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/client/paho_mqtt_udp.c +++ b/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/client/paho_mqtt_udp.c @@ -162,7 +162,7 @@ static int mqtt_resolve_uri(MQTT_CLIENT_T *c, struct addrinfo **res) _exit: if (host_addr_new != NULL) { - os_free(host_addr_new); + os_free_loose(host_addr_new); host_addr_new = NULL; } return rc; @@ -928,7 +928,7 @@ int mqtt_cmd(MQTT_CLIENT_T *c, const char *cmd) _exit: if (data) - os_free(data); + os_free_loose(data); return rc; } @@ -971,7 +971,7 @@ int mqtt_publish_with_topic(MQTT_CLIENT_T *c, const char *topicName, MQTTMessage exit: if (data) - os_free(data); + os_free_loose(data); return rc; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/mqtt_ui/mqtt_client_core.c b/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/mqtt_ui/mqtt_client_core.c index dd421692729d1ab8e6210ba6c46efb49ebcf32a1..cb082c5a40e26acb9f7f1eed12dac2db1be5328a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/mqtt_ui/mqtt_client_core.c +++ b/drivers/hal/beken/beken72XX_HAL/func/paho-mqtt/mqtt_ui/mqtt_client_core.c @@ -80,12 +80,12 @@ static int mqtt_client_send_disconnect_packet(mqtt_client_session* cs) len = MQTTSerialize_disconnect(cs->buf, cs->buf_size); if (len > 0) { - rtos_enter_critical(); + os_ubase_t level = os_irq_lock(); if(!list_empty( &cs->node)) { list_del_init( &cs->node ); } - rtos_exit_critical(); + os_irq_unlock(level); rc = mqtt_send_packet(cs, len,cs->command_timeout_ms); // send the disconnect packet if(rc == SUCCESS) @@ -302,7 +302,7 @@ exit: mqtt_senssion_unlock(c->lock) ; if (mqt) { - os_free(mqt); + os_free_loose(mqt); } return MQTT_ERR; } @@ -547,15 +547,15 @@ void mqtt_core_handler(void) int len, rc; mqtt_msg_queue_t *mqt = NULL; - rtos_enter_critical(); + os_ubase_t level = os_irq_lock(); if(list_empty( &mqtt_hd)) { - rtos_exit_critical(); + os_irq_unlock(level); return; } node = mqtt_hd.next; cs = list_entry(node,struct mqtt_client_session,node); - rtos_exit_critical(); + os_irq_unlock(level); if(cs == NULL) { return; @@ -569,16 +569,16 @@ void mqtt_core_handler(void) if((cs->is_connected == 0) ||(cs->net_is_connected == 0)) { - rtos_enter_critical(); + level = os_irq_lock(); if(!list_empty( &cs->node)) { list_del_init( &cs->node ); } - rtos_exit_critical(); + os_irq_unlock(level); goto exit; } - rtos_enter_critical(); + level = os_irq_lock(); if(!list_empty( &cs->msg_hd )) { node = cs->msg_hd.next; @@ -590,7 +590,7 @@ void mqtt_core_handler(void) { mqt = NULL; } - rtos_exit_critical(); + os_irq_unlock(level); if(mqt != NULL) { @@ -601,7 +601,7 @@ void mqtt_core_handler(void) if(mqt != NULL) { - os_free(mqt); + os_free_loose(mqt); mqt = NULL; } } @@ -744,9 +744,9 @@ int matt_client_connect(mqtt_client_session* cs, MQTTPacket_connectData* options { cs->online_callback(cs); } - rtos_enter_critical(); + os_ubase_t level = os_irq_lock(); list_add_tail(&cs->node,&mqtt_hd); - rtos_exit_critical(); + os_irq_unlock(level); mqtt_senssion_unlock(cs->lock) ; @@ -780,7 +780,7 @@ int mqtt_client_disconnect(mqtt_client_session* cs) { list_del_init( &cs->node ); } - rtos_exit_critical(); + os_irq_unlock(level); len = MQTTSerialize_disconnect(cs->buf, cs->buf_size); if (len > 0) @@ -919,12 +919,12 @@ int mqtt_client_session_deinit(mqtt_client_session* cs) cs->lock = NULL; } - rtos_enter_critical(); + os_ubase_t level = os_irq_lock(); if(!list_empty( &cs->node)) { list_del_init( &cs->node ); } - rtos_exit_critical(); + os_irq_unlock(level); mqtt_net_disconnect(cs); diff --git a/drivers/hal/beken/beken72XX_HAL/func/power_save/power_save.c b/drivers/hal/beken/beken72XX_HAL/func/power_save/power_save.c index 02a4f4570aabcd7e5237603e475e783dfe7a1d68..2ae542d683b58738f8006f6402a144403a8feb42 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/power_save/power_save.c +++ b/drivers/hal/beken/beken72XX_HAL/func/power_save/power_save.c @@ -20,6 +20,8 @@ #include "mcu_ps_pub.h" #include "error.h" #include "start_type_pub.h" +#include "os_memory.h" +#include "os_assert.h" volatile static PS_MODE_STATUS bk_ps_mode = PS_NO_PS_MODE; static UINT32 last_wk_tick = 0; @@ -431,7 +433,7 @@ void power_save_me_ps_first_set_state ( UINT8 state ) VIF_INF_PTR vif_entry; struct ke_msg *kmsg_dst; struct me_set_ps_disable_req *me_ps_ptr; - os_printf ( "%s:%d \r\n", __FUNCTION__, __LINE__ ); + param_len = sizeof ( struct me_set_ps_disable_req ); vif_entry = ( VIF_INF_PTR ) rwm_mgmt_is_vif_first_used(); @@ -463,7 +465,6 @@ void power_save_me_ps_first_set_state ( UINT8 state ) void power_save_me_ps_set_state ( UINT8 state , UINT8 vif_idx ) { - os_printf ( "%s:%d \r\n", __FUNCTION__, __LINE__ ); { struct me_set_ps_disable_req *me_ps_ptr = KE_MSG_ALLOC ( ME_SET_PS_DISABLE_REQ, TASK_ME, TASK_NONE, me_set_ps_disable_req ); @@ -988,7 +989,7 @@ void *power_save_rf_ps_wkup_semlist_create ( void ) return 0; } - ret = rtos_init_semaphore ( &sem_list->wkup_sema, 1 ); + ret = rtos_init_semaphore( &sem_list->wkup_sema, 1 ); ASSERT ( 0 == ret ); return sem_list; } @@ -1025,8 +1026,8 @@ void power_save_rf_ps_wkup_semlist_get ( void *sem_list ) co_list_extract ( &bk_ps_info.wk_list, & ( ( PS_DO_WKUP_SEM * ) sem_list )->list ); GLOBAL_INT_RESTORE(); ret = rtos_deinit_semaphore ( & ( ( PS_DO_WKUP_SEM * ) sem_list )->wkup_sema ); - ASSERT ( 0 == ret ); - os_free ( sem_list ); + OS_ASSERT(0 == ret); + os_free_loose(sem_list); sem_list = NULL; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/rf_use/arbitrate.c b/drivers/hal/beken/beken72XX_HAL/func/rf_use/arbitrate.c index 5bf669eb468ac9ab7018e6a9472546542a94d1ef..81d244c03b49284147ade96e9e5316f38880a4a0 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/rf_use/arbitrate.c +++ b/drivers/hal/beken/beken72XX_HAL/func/rf_use/arbitrate.c @@ -183,7 +183,7 @@ void wifi_send_data_reset(void) if(wifi_node) { - os_free(wifi_node); + os_free_loose(wifi_node); wifi_node = NULL; } else @@ -627,7 +627,7 @@ static void rf_thread_main(void *arg) if(wifi_node) { txl_frame_exchange_chain(wifi_node->first_thd, wifi_node->last_thd, wifi_node->access_category); - os_free(wifi_node); + os_free_loose(wifi_node); wifi_node = NULL; } } @@ -654,7 +654,7 @@ static void rf_thread_main(void *arg) txl_frame_exchange_chain(wifi_node->first_thd, wifi_node->last_thd, wifi_node->access_category); - os_free(wifi_node); + os_free_loose(wifi_node); wifi_node = NULL; } else @@ -673,7 +673,7 @@ static void rf_thread_main(void *arg) { txl_frame_exchange_chain(wifi_node->first_thd, wifi_node->last_thd, wifi_node->access_category); - os_free(wifi_node); + os_free_loose(wifi_node); wifi_node = NULL; } rf_time_wifi = RF_WIFI_TIME_MAX; @@ -685,7 +685,7 @@ static void rf_thread_main(void *arg) { txl_frame_exchange_chain(wifi_node->first_thd, wifi_node->last_thd, wifi_node->access_category); - os_free(wifi_node); + os_free_loose(wifi_node); wifi_node = NULL; } @@ -705,7 +705,7 @@ static void rf_thread_main(void *arg) if (msg.msg_param) { - os_free(msg.msg_param); + os_free_loose(msg.msg_param); msg.msg_param = NULL; } } @@ -886,7 +886,7 @@ static void rf_thread_main(void *arg) if (msg.msg_param) { - os_free(msg.msg_param); + os_free_loose(msg.msg_param); msg.msg_param = NULL; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_ieee80211.c b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_ieee80211.c index cdad72feedd0d955954e9d8b3a8063b66fdad424..1004538237b82405704d657c0f625966a9c0ab41 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_ieee80211.c +++ b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_ieee80211.c @@ -4,6 +4,7 @@ #include "rwnx.h" #include "rw_msdu.h" #include "mem_pub.h" +#include "error.h" typedef struct _wifi_cn_code_st_ { diff --git a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msdu.c b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msdu.c index 23c06e67032fbfd2d140e40e2057edbae335cf07..a31c61f12eec90437eeb60bbf3fe6301a2925a26 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msdu.c +++ b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msdu.c @@ -87,7 +87,7 @@ void rwm_flush_rx_list(void) node_ptr = rwm_pop_rx_list(); if(node_ptr) { - os_free(node_ptr); + os_free_loose(node_ptr); } else { @@ -109,7 +109,7 @@ void rwm_tx_confirm(void *param) os_null_printf("flush_desc:0x%x\r\n", txdesc->host.msdu_node); - os_free(txdesc->host.msdu_node); + os_free_loose(txdesc->host.msdu_node); txdesc->host.msdu_node = NULL; } } @@ -235,7 +235,7 @@ alloc_exit: void rwm_node_free(MSDU_NODE_T *node) { ASSERT(node); - os_free(node); + os_free_loose(node); } UINT8 *rwm_rx_buf_alloc(UINT32 len) @@ -365,7 +365,7 @@ void rwm_flush_txing_list(UINT8 sta_idx) while(1) { node_ptr = rwm_pop_txing_list(sta_idx); if(node_ptr) - os_free(node_ptr); + os_free_loose(node_ptr); else break; } @@ -883,7 +883,7 @@ UINT32 rwm_uploaded_data_handle(UINT8 *upper_buf, UINT32 len) #endif ret = count; - os_free(node_ptr); + os_free_loose(node_ptr); node_ptr = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_rx.c b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_rx.c index cd15e58d2157ab4ccf753befd554438133d24d41..3250627374e58d3d1f0fbe67f0e648785ccac8a8 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_rx.c +++ b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_rx.c @@ -14,7 +14,7 @@ #include "ieee802_11_defs.h" #include "wlan_ui_pub.h" #include "mcu_ps_pub.h" -#include "driver.h" +#include "wpa_supplicant-2.9\src\drivers\driver.h" #if CFG_NEW_SUPP #include "signal.h" #include "ctrl_iface.h" @@ -34,6 +34,7 @@ uint32_t resultful_scan_cfm = 0; uint8_t *ind_buf_ptr = 0; struct co_list rw_msg_rx_head; +struct co_list rw_msg_test_head; struct co_list rw_msg_tx_head; rw_evt_type connect_flag = RW_EVT_STA_IDLE; @@ -62,7 +63,7 @@ UINT8 *sr_malloc_result_item(UINT32 vies_len) /* free scan result item */ void sr_free_result_item(UINT8 *item_ptr) { - os_free(item_ptr); + os_free_loose(item_ptr); } UINT8 *sr_malloc_shell(void) @@ -82,7 +83,7 @@ UINT8 *sr_malloc_shell(void) void sr_free_shell(UINT8 *shell_ptr) { - os_free(shell_ptr); + os_free_loose(shell_ptr); } void sr_free_all(SCAN_RST_UPLOAD_T *scan_rst) @@ -118,6 +119,7 @@ void mr_kmsg_init(void) { co_list_init(&rw_msg_tx_head); co_list_init(&rw_msg_rx_head); + co_list_init(&rw_msg_test_head); } UINT32 mr_kmsg_fwd(struct ke_msg *msg) @@ -125,11 +127,16 @@ UINT32 mr_kmsg_fwd(struct ke_msg *msg) GLOBAL_INT_DECLARATION(); GLOBAL_INT_DISABLE(); + co_list_push_back(&rw_msg_rx_head, &msg->hdr); + //co_list_push_back(&rw_msg_test_head, &msg->hdr); + GLOBAL_INT_RESTORE(); app_set_sema(); + //os_task_msleep(100); + return 0; } @@ -143,7 +150,7 @@ UINT32 mr_kmsg_fuzzy_handle(void) UINT32 ret = 0; struct ke_msg *msg; struct co_list_hdr *node; - + GLOBAL_INT_DECLARATION(); GLOBAL_INT_DISABLE(); @@ -166,7 +173,7 @@ UINT32 mr_kmsg_exact_handle(UINT16 rsp) UINT32 ret = 0; struct ke_msg *msg; struct co_list_hdr *node; - + GLOBAL_INT_DECLARATION(); GLOBAL_INT_DISABLE(); @@ -894,15 +901,17 @@ void rwnx_recv_msg(void) FUNC_1PARAM_PTR fn = bk_wlan_get_status_cb(); GLOBAL_INT_DECLARATION(); - while(1) { uint8_t find = 0; - + rx_node = co_list_pop_front(&rw_msg_rx_head); + + //os_printf("rwnx_recv_msg %p\r\n", rx_node); + if(!rx_node) break; - + rx_msg = (struct ke_msg *)rx_node; GLOBAL_INT_DISABLE(); @@ -925,6 +934,8 @@ void rwnx_recv_msg(void) if(find) { + //os_printf("rwnx_recv_msg find\r\n"); + int ret; GLOBAL_INT_DISABLE(); co_list_extract(&rw_msg_rx_head, rx_node); @@ -951,15 +962,16 @@ void rwnx_recv_msg(void) (*fn)(¶m); mhdr_set_station_status(param); } - os_kprintf("ap stop end.\n"); + os_printf("ap stop end.\n"); break; default: break; } } - + ret = rtos_set_semaphore(&tx_msg->semaphore); + //os_printf("c: %d\r\n", ret); ASSERT(0 == ret); } else diff --git a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_tx.c b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_tx.c index 68926f01b50d2e70ed33a23bed6fa7bff83fddf0..de5888ace210934b06afeb4ab364ac17f1803ccc 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_tx.c +++ b/drivers/hal/beken/beken72XX_HAL/func/rwnx_intf/rw_msg_tx.c @@ -62,22 +62,21 @@ int rw_msg_send(const void *msg_params, uint16_t reqid, void *cfm) need_cfm = 1; } - + ret = bmsg_ioctl_sender((void*)msg_params); if (kNoErr != ret) { os_printf("%s failed send %d\n", __FUNCTION__, msg->id); - os_free((void*)msg_params); + os_free_loose((void*)msg_params); goto failed_or_timeout; } else if (need_cfm) { ret = rtos_get_semaphore(&tx_msg->semaphore, 5 * MICROSECONDS); - + if (0 != ret) { - os_printf("%s timeout for %d\n", __FUNCTION__, reqid); GLOBAL_INT_DISABLE(); co_list_extract(&rw_msg_tx_head, &tx_msg->hdr); GLOBAL_INT_RESTORE(); @@ -88,9 +87,8 @@ int rw_msg_send(const void *msg_params, uint16_t reqid, void *cfm) ret = rtos_deinit_semaphore(&tx_msg->semaphore); ASSERT(0 == ret); - os_free(tx_msg); + os_free_loose(tx_msg); } - return 0; failed_or_timeout: @@ -99,8 +97,9 @@ failed_or_timeout: ret = rtos_deinit_semaphore(&tx_msg->semaphore); ASSERT(0 == ret); - os_free(tx_msg); + os_free_loose(tx_msg); } + return -1; } @@ -372,9 +371,9 @@ int rw_msg_send_apm_stop_req(u8 vif_index) if ((!req) || (!cfm)) { if(cfm) - os_free(cfm); + os_free_loose(cfm); if(req) - os_free(req); + os_free_loose(req); return -1; } @@ -388,7 +387,7 @@ int rw_msg_send_apm_stop_req(u8 vif_index) { bk_printf("[T]APM_STOP_CFM\n"); } - os_free(cfm); + os_free_loose(cfm); return ret; } @@ -544,6 +543,7 @@ int rw_msg_send_key_add(KEY_PARAM_T *param, struct mm_key_add_cfm *cfm) key_add_req->cipher_suite = param->cipher_suite; /* Send the MM_KEY_ADD_REQ message to LMAC FW */ + //os_kprintf("sta_idx %d, key_idx %d, inst_nbr %d, key.length %d, cipher_suite %d\r\n", key_add_req->sta_idx, key_add_req->key_idx, key_add_req->inst_nbr, key_add_req->key.length, key_add_req->cipher_suite); return rw_msg_send(key_add_req, MM_KEY_ADD_CFM, cfm); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/saradc_intf/saradc_intf.c b/drivers/hal/beken/beken72XX_HAL/func/saradc_intf/saradc_intf.c index c1c4d6b4c3f73a74ecfdbf950de79f36c099e808..73c504b70f07ea4f09049df5ab3c8d9bfc3b1d15 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/saradc_intf/saradc_intf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/saradc_intf/saradc_intf.c @@ -215,7 +215,7 @@ void tadc_entity_deinit(TADC_ENTITY_T **adc_entity) (*adc_entity)->obj_list_mutex = NULL; } - os_free((*adc_entity)); + os_free_loose((*adc_entity)); *adc_entity = NULL; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/sd_music/sdcard_test.c b/drivers/hal/beken/beken72XX_HAL/func/sd_music/sdcard_test.c index cfd7e43d79d7f57fa0e4985184ef045b9e6f66e5..6af177a7db28333b849a1aafe7f2bd56219693c2 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/sd_music/sdcard_test.c +++ b/drivers/hal/beken/beken72XX_HAL/func/sd_music/sdcard_test.c @@ -73,7 +73,7 @@ UINT32 test_sdcard_read(UINT32 blk) } os_printf("\r\nread over\r\n"); - os_free(testbuf); + os_free_loose(testbuf); return ret; } @@ -94,7 +94,7 @@ UINT32 test_sdcard_write(UINT32 blk) testbuf[i]=0x50; //blk = 0x20000;//just for test ret = ddev_write(sdcard_hdl, testbuf, 1, blk); - os_free(testbuf); + os_free_loose(testbuf); return ret; } void sdcard_intf_close(void) diff --git a/drivers/hal/beken/beken72XX_HAL/func/sdio_intf/sdio_intf.c b/drivers/hal/beken/beken72XX_HAL/func/sdio_intf/sdio_intf.c index 1bd6a2f507e6ea1628109861f16e771c23a94927..35cd99b0e492bebc8d31a8ac8fd26f46a5e1e8bb 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/sdio_intf/sdio_intf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/sdio_intf/sdio_intf.c @@ -385,7 +385,7 @@ UINT32 resp_conversion_mgmt_tx_cfm(struct ke_msg *msg, STM32_FRAME_HDR **frm_ppt ke_mgmt_packet_tx((unsigned char *)cfm_ptr->hostid, cfm_ptr->length, 0); if(cfm_ptr->rsp_frm_new) { - os_free((void *)cfm_ptr->hostid); + os_free_loose((void *)cfm_ptr->hostid); } } #endif @@ -751,7 +751,7 @@ UINT32 sdio_emb_kmsg_fwd(struct ke_msg *msg) if(frm_ptr) { - os_free(frm_ptr); + os_free_loose(frm_ptr); } tx_ok: diff --git a/drivers/hal/beken/beken72XX_HAL/func/sensor/SConscript b/drivers/hal/beken/beken72XX_HAL/func/sensor/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..1c33c946a81cf850a2c4a773688ce33cd1ad7ee4 --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/func/sensor/SConscript @@ -0,0 +1,33 @@ +from build_tools import * +Import('OS_ROOT') +Import('BEKEN_CFG') + +cwd = PresentDir() + +src = [] +src += ["sensor.c"] + +path = [] +path += [cwd + '/'] + +#sys_config = os.path.join(cwd, '..', '..', '..', 'config', 'sys_config.h') +sys_config = BEKEN_CFG +options = LocalOptions(sys_config) + +sensor_lib_name = 'sensor' + +libs = [sensor_lib_name] +libpath = [cwd + '/'] + + +if (IsLocalDefined(options, 'CFG_WIFI_SENSOR') == 0): + group = [] +else: + group_use_lib = AddCodeGroup('beken_sensor_lib', [], depend = ['SOC_FAMILY_BK72XX'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + + group_build_lib = AddCodeGroup('beken_sensor', src, depend = ['BUILD_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath, LIBNAME = 'lib' + sensor_lib_name + '.a') + + group = group_use_lib + group_build_lib + + +Return('group') \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/func/sensor/weave.yaml b/drivers/hal/beken/beken72XX_HAL/func/sensor/weave.yaml deleted file mode 100644 index 47a7e3c7d5c62925ee4409337a7caec036596a91..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/sensor/weave.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# 组名 -group_name: beken_sensor_lib - -# 依赖宏控 -depend_macro: - - SOC_FAMILY_BK72XX - -# 编译连接信息 -build_option: - cpppath: - - . - libs: - - sensor - libpath: - - . -# 子目录 -add_subdirectory: - - beken_sensor ? {is_define(['BEKEN_CFG',CFG_WIFI_SENSOR])} diff --git a/drivers/hal/beken/beken72XX_HAL/func/temp_detect/temp_detect.c b/drivers/hal/beken/beken72XX_HAL/func/temp_detect/temp_detect.c index 301f79474b4245941056fd2b56c00be9a40b4e76..2b669e28d28c5dcb0abac2c09aa14692afdce3c0 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/temp_detect/temp_detect.c +++ b/drivers/hal/beken/beken72XX_HAL/func/temp_detect/temp_detect.c @@ -313,14 +313,21 @@ static void temp_detect_polling_handler(void) g_temp_detect_config.detect_thre); #if CFG_USE_STA_PS + ps_set_temp_prevent(); UINT32 reg = RF_HOLD_BY_TEMP_BIT; + sddev_control(SCTRL_DEV_NAME, CMD_RF_HOLD_BIT_SET, ®); + bk_wlan_dtim_rf_ps_mode_do_wakeup(); + rwnx_cal_do_temp_detect(cur_val, thre, &g_temp_detect_config.last_detect_val); + ps_clear_temp_prevent(); + reg = RF_HOLD_BY_TEMP_BIT; sddev_control(SCTRL_DEV_NAME, CMD_RF_HOLD_BIT_CLR, ®); + #endif if(g_temp_detect_config.detect_intval_change == ADC_TMEP_DETECT_INTVAL_CHANGE) @@ -356,7 +363,9 @@ static void temp_detect_main( beken_thread_arg_t data ) g_temp_detect_config.last_xtal_val = (UINT32)(data); #if (CFG_SOC_NAME != SOC_BK7231) g_temp_detect_config.xtal_thre_val = ADC_XTAL_DIST_INTIAL_VAL; + g_temp_detect_config.xtal_init_val = sddev_control(SCTRL_DEV_NAME, CMD_SCTRL_GET_XTALH_CTUNE, NULL); + os_printf("xtal inital:%d, %d, %d\r\n", g_temp_detect_config.last_xtal_val, g_temp_detect_config.xtal_thre_val, g_temp_detect_config.xtal_init_val); #endif // (CFG_SOC_NAME != SOC_BK7231) @@ -365,15 +374,18 @@ static void temp_detect_main( beken_thread_arg_t data ) g_temp_detect_config.detect_intval * 1000, temp_detect_timer_handler, (void *)0); + ASSERT(kNoErr == err); err = rtos_start_timer(&g_temp_detect_config.detect_timer); - + ASSERT(kNoErr == err); while(1) { TEMP_MSG_T msg; + err = rtos_pop_from_queue(&tempd_msg_que, &msg, BEKEN_WAIT_FOREVER); + if(kNoErr == err) { switch(msg.temp_msg) @@ -416,6 +428,7 @@ static void temp_detect_main( beken_thread_arg_t data ) } tempd_exit: + err = rtos_deinit_timer(&g_temp_detect_config.detect_timer); ASSERT(kNoErr == err); diff --git a/drivers/hal/beken/beken72XX_HAL/func/usb_plug/usb_plug.c b/drivers/hal/beken/beken72XX_HAL/func/usb_plug/usb_plug.c index 8e6e639cb42a97264e348681519391e18ef27f1b..904413c473b233690e834a429a9775db2fec0e8b 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/usb_plug/usb_plug.c +++ b/drivers/hal/beken/beken72XX_HAL/func/usb_plug/usb_plug.c @@ -174,7 +174,7 @@ static int vbat_voltage_get(void) ul_valueIn = ul_valueDout * 4200 / dvbatref; os_printf("vbat %d\r\n", (int)ul_valueIn); - os_free(usData); + os_free_loose(usData); return ul_valueIn; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.c b/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.c index 4f0d5bca898affeb68cd9915ae34801029e67134..11888e179095cbf4fb40f3a1963ab9f35dfbf5a2 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.c +++ b/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.c @@ -81,7 +81,7 @@ OSStatus bk_uart_initialize_test( bk_uart_t uart, uint8_t config, ring_buffer_t return bk_uart_initialize(uart, &test_uart_config[config], optional_rx_buffer); } -OSStatus bk_uart_initialize( bk_uart_t uart, const bk_uart_config_t *config, ring_buffer_t *optional_rx_buffer ) +OSStatus bk_uart_initialize( bk_uart_t uart, const uart_config_t *config, ring_buffer_t *optional_rx_buffer ) { UINT32 ret; UINT32 status; diff --git a/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.h b/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.h index d0018b157ab4be73e5f7fd3b35e3d978f82a866c..acc376e5d5ebbcd4652a324570f4d6e9cb8ada3e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.h +++ b/drivers/hal/beken/beken72XX_HAL/func/user_driver/BkDriverUart.h @@ -84,7 +84,7 @@ OSStatus bk_uart_initialize_test( bk_uart_t uart, uint8_t config, ring_buffer_t * @return kNoErr : on success. * @return kGeneralErr : if an error occurred with any step */ -OSStatus bk_uart_initialize( bk_uart_t uart, const bk_uart_config_t *config, ring_buffer_t *optional_rx_buffer ); +OSStatus bk_uart_initialize( bk_uart_t uart, const uart_config_t *config, ring_buffer_t *optional_rx_buffer ); /**@brief Deinitialises a UART interface * diff --git a/drivers/hal/beken/beken72XX_HAL/func/utf8/conv_utf8.c b/drivers/hal/beken/beken72XX_HAL/func/utf8/conv_utf8.c index 330920dd8cedcf8daf469d6b2577a5548966fcec..dd470af567502d0f589f5072f938c5649855d8e1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/utf8/conv_utf8.c +++ b/drivers/hal/beken/beken72XX_HAL/func/utf8/conv_utf8.c @@ -192,7 +192,7 @@ char* Utf8ToGb2312(char* utf8) memcpy(utf8, temp, j); //printf("%s", utf8); - os_free(temp); + os_free_loose(temp); return utf8; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/vad/SConscript b/drivers/hal/beken/beken72XX_HAL/func/vad/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..71d7fc6d590a23374972c88380cc099927e44a59 --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/func/vad/SConscript @@ -0,0 +1,24 @@ +from build_tools import * +Import('OS_ROOT') + +cwd = PresentDir() + +src = Glob('*.c') +path = [] +path += [cwd + '/'] + + +vad_lib_name = 'vad' + +libs = [vad_lib_name] +libpath = [cwd + '/'] + + +group_use_lib = AddCodeGroup('beken_vad_lib', [], depend = ['SOC_FAMILY_BK72XX'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + +group_build_lib = AddCodeGroup('beken_vad', src, depend = ['BUILD_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath, LIBNAME = 'lib' + vad_lib_name + '.a') + +group = group_use_lib + group_build_lib + + +Return('group') diff --git a/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_buffer.c b/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_buffer.c index 6332a259fa13e2b5f5b117d073641f08c1ee2c29..e2c232b254f27f044a9ec59b919a3ce636e070cb 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_buffer.c +++ b/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_buffer.c @@ -192,7 +192,7 @@ int video_buffer_open (void) if(rtos_init_semaphore(&g_vbuf->aready_semaphore, 1) != kNoErr) { os_printf("vbuf init semaph failed\r\n"); - os_free(g_vbuf); + os_free_loose(g_vbuf); g_vbuf = NULL; return 0; } @@ -223,7 +223,7 @@ int video_buffer_open (void) { os_printf("video_transfer_init failed\r\n"); rtos_deinit_semaphore(&g_vbuf->aready_semaphore); - os_free(g_vbuf); + os_free_loose(g_vbuf); g_vbuf = NULL; return ret; } @@ -265,7 +265,7 @@ int video_buffer_close (void) g_vbuf->aready_semaphore = NULL; GLOBAL_INT_RESTORE(); - os_free(g_vbuf); + os_free_loose(g_vbuf); g_vbuf = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_transfer.c b/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_transfer.c index 0a2660018793a6b0f9030e574d31ab3ce5c5321b..94bfdaf89cd54294929b3f1cef25f935e89f92a2 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_transfer.c +++ b/drivers/hal/beken/beken72XX_HAL/func/video_transfer/video_transfer.c @@ -404,7 +404,7 @@ tvideo_exit: if(tvideo_pool.pool) { - os_free(tvideo_pool.pool); + os_free_loose(tvideo_pool.pool); tvideo_pool.pool = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/weave.yaml b/drivers/hal/beken/beken72XX_HAL/func/weave.yaml deleted file mode 100644 index 467cff735f6d46a798f44f0bfa3ba0ec5e23236b..0000000000000000000000000000000000000000 --- a/drivers/hal/beken/beken72XX_HAL/func/weave.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# 子目录 -add_subdirectory: - - ./* \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_cli.c b/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_cli.c index d3713ece6d6f4963f5ee8ca03ec25a132e3068b7..e76dca35b0ca069fa46b6da293ed9f872ac5c2d9 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_cli.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_cli.c @@ -465,7 +465,7 @@ static void cli_main( uint32_t data ) } os_printf("CLI exited\r\n"); - os_free(pCli); + os_free_loose(pCli); pCli = NULL; bk_uart_set_rx_callback(CLI_UART, NULL, NULL); @@ -892,7 +892,7 @@ void sta_Command(char *pcWriteBuffer, int xWriteBufferLen, int argc, char **argv if(oob_ssid_tp) { demo_sta_app_init((char*)oob_ssid_tp, connect_key); - os_free(oob_ssid_tp); + os_free_loose(oob_ssid_tp); } else { @@ -2905,7 +2905,7 @@ static void adc_command(char *pcWriteBuffer, int xWriteBufferLen, int argc, char if(p_ADC_drv_desc->pData == NULL) { os_printf("malloc1 failed!\r\n"); - os_free(p_ADC_drv_desc); + os_free_loose(p_ADC_drv_desc); return; } @@ -2937,14 +2937,14 @@ static void adc_command(char *pcWriteBuffer, int xWriteBufferLen, int argc, char if(SARADC_FAILURE == ddev_control(saradc_handle, SARADC_CMD_SET_CAL_VAL, (VOID *)&p_ADC_cal)) { os_printf("set calibrate value failture\r\n"); - os_free(p_ADC_drv_desc->pData); - os_free(p_ADC_drv_desc); + os_free_loose(p_ADC_drv_desc->pData); + os_free_loose(p_ADC_drv_desc); return; } os_printf("set calibrate success\r\n"); os_printf("type:[%s] value:[0x%x]\r\n", (p_ADC_cal.mode ? "high":"low"), p_ADC_cal.val); - os_free(p_ADC_drv_desc->pData); - os_free(p_ADC_drv_desc); + os_free_loose(p_ADC_drv_desc->pData); + os_free_loose(p_ADC_drv_desc); } else if(0 == os_strcmp(argv[1], "write")) { @@ -2979,7 +2979,7 @@ static void adc_command(char *pcWriteBuffer, int xWriteBufferLen, int argc, char if(p_ADC_drv_desc->pData == NULL) { os_printf("malloc1 failed!\r\n"); - os_free(p_ADC_drv_desc); + os_free_loose(p_ADC_drv_desc); return; } @@ -2996,8 +2996,8 @@ static void adc_command(char *pcWriteBuffer, int xWriteBufferLen, int argc, char voltage = saradc_calculate(p_ADC_drv_desc->pData[4]); os_printf("voltage is [%f]\r\n", voltage); - os_free(p_ADC_drv_desc->pData); - os_free(p_ADC_drv_desc); + os_free_loose(p_ADC_drv_desc->pData); + os_free_loose(p_ADC_drv_desc); return; }*/ @@ -3152,7 +3152,7 @@ int cli_init(void) init_general_err: if(pCli) { - os_free(pCli); + os_free_loose(pCli); pCli = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_ui.c b/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_ui.c index 84917f9070448de4e08d719062652bb29c24e563..2ea603578ac868da8ef903e21cabb47dc4db8330 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_ui.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wlan_ui/wlan_ui.c @@ -88,12 +88,12 @@ static void rwnx_remove_added_interface(void) ERR_RETURN: if(cfm) { - os_free(cfm); + os_free_loose(cfm); } if(apm_cfm) { - os_free(apm_cfm); + os_free_loose(apm_cfm); } } @@ -352,19 +352,19 @@ void bk_reboot(void) bk_misc_update_set_type(RESET_SOURCE_REBOOT); - GLOBAL_INT_DECLARATION(); + //GLOBAL_INT_DECLARATION(); - GLOBAL_INT_DISABLE(); + //GLOBAL_INT_DISABLE(); sddev_control(WDT_DEV_NAME, WCMD_POWER_DOWN, NULL); - os_printf("wdt reboot\r\n"); + #if (CFG_SOC_NAME == SOC_BK7231N) delay_ms(100); //add delay for bk_writer BEKEN_DO_REBOOT cmd #endif sddev_control(WDT_DEV_NAME, WCMD_SET_PERIOD, &wdt_val); sddev_control(WDT_DEV_NAME, WCMD_POWER_UP, NULL); while(1); - GLOBAL_INT_RESTORE(); + //GLOBAL_INT_RESTORE(); } void bk_wlan_ap_init(network_InitTypeDef_st *inNetworkInitPara) @@ -441,7 +441,6 @@ void bk_wlan_ap_init(network_InitTypeDef_st *inNetworkInitPara) UINT32 reg = RF_HOLD_BY_AP_BIT; sddev_control(SCTRL_DEV_NAME, CMD_RF_HOLD_BIT_SET, ®); } - sa_ap_init(); } @@ -450,10 +449,10 @@ OSStatus bk_wlan_start_ap(network_InitTypeDef_st *inNetworkInitParaAP) #if !CFG_NEW_SUPP int ret, flag ,empty; GLOBAL_INT_DECLARATION(); - while( 1 ) { GLOBAL_INT_DISABLE(); + flag = mm_bcn_get_tx_cfm(); empty = is_apm_bss_config_empty(); if ( flag == 0 && empty == 1) @@ -473,9 +472,9 @@ OSStatus bk_wlan_start_ap(network_InitTypeDef_st *inNetworkInitParaAP) bk_wlan_ap_init(inNetworkInitParaAP); ret = hostapd_main_entry(2, 0); + if(ret) { - os_printf("bk_wlan_start softap failed!!\r\n"); bk_wlan_stop(BK_SOFT_AP); return -1; } @@ -488,8 +487,8 @@ OSStatus bk_wlan_start_ap(network_InitTypeDef_st *inNetworkInitParaAP) inNetworkInitParaAP->net_mask, inNetworkInitParaAP->gateway_ip_addr, inNetworkInitParaAP->dns_server_ip_addr); - uap_ip_start(); + uap_ip_start(); sm_build_broadcast_deauthenticate(); #else /* CFG_NEW_SUPP */ /* stop lwip netif */ @@ -659,7 +658,6 @@ OSStatus bk_wlan_start(network_InitTypeDef_st *inNetworkInitPara) #if CFG_ROLE_LAUNCH lreq.req_type = LAUNCH_REQ_AP; lreq.descr = *inNetworkInitPara; - rl_ap_request_enter(&lreq, 0); #else bk_wlan_start_ap(inNetworkInitPara); @@ -715,6 +713,7 @@ void bk_wlan_start_scan(void) rw_msg_send_scanu_req(&scan_param); #endif + } @@ -1237,7 +1236,7 @@ OSStatus bk_wlan_get_link_status(LinkStatusTypeDef *outStatus) ret = rw_msg_get_bss_info(vif_idx, (void *)cfm); if(ret) { - os_free(cfm); + os_free_loose(cfm); return kGeneralErr; } @@ -1248,7 +1247,7 @@ OSStatus bk_wlan_get_link_status(LinkStatusTypeDef *outStatus) ssid_len = MIN(SSID_MAX_LEN, os_strlen((char*)(cfm->ssid))); os_memcpy(outStatus->ssid, cfm->ssid, ssid_len); - os_free(cfm); + os_free_loose(cfm); return kNoErr; } @@ -1658,16 +1657,18 @@ int bk_wlan_dtim_rf_ps_mode_do_wakeup() ) { power_save_rf_ps_wkup_semlist_wait(sem_list); + GLOBAL_INT_RESTORE(); } else { + GLOBAL_INT_RESTORE(); power_save_rf_ps_wkup_semlist_destroy(sem_list); - os_free(sem_list); - sem_list = NULL; + os_free_loose(sem_list); + sem_list = NULL; } - GLOBAL_INT_RESTORE(); - + //GLOBAL_INT_RESTORE();os_sem_wait will assert if not block + power_save_rf_ps_wkup_semlist_get(sem_list); return ret; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/fake_socket.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/fake_socket.c index e80295cea142d988b9dd6acf05fc168234626d37..e97dd5026deb66bbc6cd63e39e2ef1c3c6eea86c 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/fake_socket.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/fake_socket.c @@ -55,7 +55,7 @@ int ke_sk_send(SOCKET sk, const unsigned char *buf, int len, int flag) return ret; malloc_buf_exit: - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = NULL; tx_exit: @@ -92,12 +92,12 @@ int ke_sk_recv(SOCKET sk, const unsigned char *buf, int len, int flag) ret = count; - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; dl_list_del(&sk_msg->data); - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = 0; break; @@ -260,7 +260,7 @@ int fsocket_send(SOCKET sk, const unsigned char *buf, int len, S_TYPE_PTR type) return ret; malloc_buf_exit: - os_free(sk_msg); + os_free_loose(sk_msg); tx_exit: return ret; @@ -297,12 +297,12 @@ int fsocket_recv(SOCKET sk, const unsigned char *buf, int len, int flag) os_memcpy((void *)buf, (void *)sk_msg->msg, count); ret = count; - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; dl_list_del(&sk_msg->data); - os_free(sk_msg); + os_free_loose(sk_msg); sk_msg = 0; break; @@ -335,12 +335,12 @@ void fsocket_close(SOCKET sk) if(sk_msg->msg) { - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; } - os_free(sk_msg); + os_free_loose(sk_msg); } dl_list_for_each_safe(sk_msg, tmp, &element->sk_rx_msg, SOCKET_MSG, data) @@ -349,17 +349,17 @@ void fsocket_close(SOCKET sk) if(sk_msg->msg) { - os_free(sk_msg->msg); + os_free_loose(sk_msg->msg); sk_msg->msg = 0; sk_msg->len = 0; } - os_free(sk_msg); + os_free_loose(sk_msg); } dl_list_del(&element->sk_element); - os_free(element); + os_free_loose(element); element = 0; GLOBAL_INT_RESTORE(); diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/sk_intf.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/sk_intf.c index 4ba69f5e719a6c3ae377da365dc1a3949e6a434b..c936101922cf1d1fc51df7d9fc5827387c911b7e 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/sk_intf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/bk_patch/sk_intf.c @@ -50,7 +50,7 @@ void handle_dummy_read(int sock, void *eloop_ctx, void *sock_ctx) dummy_exit: if(buf) { - os_free(buf); + os_free_loose(buf); } return; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/hostapd/main_none.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/hostapd/main_none.c index 6b17efbde6c67c0ebee0f857d9e7fa230122682c..d122514a27b650ffe3a42e06dd3d8467db95f4e2 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/hostapd/main_none.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/hostapd/main_none.c @@ -18,11 +18,13 @@ #include "param_config.h" #include "wlan_ui_pub.h" #include "rtos_pub.h" +#include "str_pub.h" #include "error.h" #include "wlan_ui_pub.h" #include "ap/ap_drv_ops.h" #include "common/eapol_common.h" #include "signal.h" + #if CFG_NEW_SUPP #include "wpa_ctrl.h" #endif @@ -123,7 +125,7 @@ struct hostapd_config *hostapd_config_read(const char *fname) bss->wpa_key_mgmt = 0; if (g_ap_param_ptr->cipher_suite > BK_SECURITY_TYPE_WEP) { const char *wpa_key = (char *)g_ap_param_ptr->key; - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = os_strdup(wpa_key); if (bss->ssid.wpa_passphrase) { hostapd_config_clear_wpa_psk(&bss->ssid.wpa_psk); @@ -186,7 +188,7 @@ static int hostapd_config_parse_key_mgmt(int line, const char *value) else { wpa_printf(MSG_ERROR, "Line %d: invalid key_mgmt '%s'", line, start); - os_free(buf); + os_free_loose(buf); return -1; } @@ -195,7 +197,7 @@ static int hostapd_config_parse_key_mgmt(int line, const char *value) start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, "Line %d: no key_mgmt values " "configured.", line); @@ -277,7 +279,7 @@ static int hostapd_parse_intlist(int **int_list, char *val) int count; char *pos, *end; - os_free(*int_list); + os_free_loose(*int_list); *int_list = NULL; pos = val; @@ -396,7 +398,7 @@ static int hostapd_config_fill(struct hostapd_config *conf, line, len); return 1; } - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = os_strdup(pos); if (bss->ssid.wpa_passphrase) { hostapd_config_clear_wpa_psk(&bss->ssid.wpa_psk); @@ -415,7 +417,7 @@ static int hostapd_config_fill(struct hostapd_config *conf, return 1; } bss->ssid.wpa_psk->group = 1; - os_free(bss->ssid.wpa_passphrase); + os_free_loose(bss->ssid.wpa_passphrase); bss->ssid.wpa_passphrase = NULL; bss->ssid.wpa_psk_set = 1; } else if (os_strcmp(buf, "wpa_key_mgmt") == 0) { @@ -671,7 +673,7 @@ static int hostapd_driver_init(struct hostapd_iface *iface) params.own_addr = hapd->own_addr; hapd->drv_priv = hapd->driver->hapd_init(hapd, ¶ms); - os_free(params.bridge); + os_free_loose(params.bridge); if (hapd->drv_priv == NULL) { wpa_printf(MSG_ERROR, "%s driver initialization failed.", hapd->driver->name); @@ -708,7 +710,7 @@ static int hostapd_driver_init(struct hostapd_iface *iface) if (hapd->driver->set_wowlan(hapd->drv_priv, triggs)) wpa_printf(MSG_ERROR, "set_wowlan failed"); } - os_free(triggs); + os_free_loose(triggs); #endif } @@ -793,7 +795,7 @@ static void hostapd_global_deinit(const char *pid_file, int eloop_initialized) if(wpa_drivers[i]->global_deinit) wpa_drivers[i]->global_deinit(s_hapd_global.drv_priv[i]); } - os_free(s_hapd_global.drv_priv); + os_free_loose(s_hapd_global.drv_priv); s_hapd_global.drv_priv = NULL; eloop_free_resource(); @@ -844,7 +846,7 @@ int hostapd_main_exit(void) hostapd_interface_deinit_free(g_hapd_interfaces.iface[i]); g_hapd_interfaces.iface[i] = NULL; } - os_free(g_hapd_interfaces.iface); + os_free_loose(g_hapd_interfaces.iface); g_hapd_interfaces.iface = NULL; g_hapd_interfaces.count = 0; @@ -901,7 +903,7 @@ int hostapd_main_entry(int argc, char *argv[]) //os_memcpy(ap_iface_buf, CFG_AP_IFACE_CONFIG,(strlen(CFG_AP_IFACE_CONFIG) + 1)); if (os_program_init()) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); return -1; } @@ -927,14 +929,14 @@ int hostapd_main_entry(int argc, char *argv[]) g_hapd_interfaces.iface = os_calloc(g_hapd_interfaces.count + num_bss_configs, sizeof(struct hostapd_iface *)); if (g_hapd_interfaces.iface == NULL) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); fatal_prf("malloc failed\r\n"); return -1; } } if (hostapd_global_init(&g_hapd_interfaces, entropy_file)) { - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); fatal_prf("Failed to initialize global context\r\n"); return -1; } @@ -1015,7 +1017,7 @@ int hostapd_main_entry(int argc, char *argv[]) ret = 0; - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); //ap_iface_buf = NULL; return ret; @@ -1034,7 +1036,7 @@ out: hostapd_interface_deinit_free(g_hapd_interfaces.iface[i]); g_hapd_interfaces.iface[i] = NULL; } - os_free(g_hapd_interfaces.iface); + os_free_loose(g_hapd_interfaces.iface); g_hapd_interfaces.iface = NULL; g_hapd_interfaces.count = 0; #ifdef CONFIG_DPP @@ -1044,10 +1046,10 @@ out: eloop_cancel_timeout(hostapd_periodic, &g_hapd_interfaces, NULL); hostapd_global_deinit(pid_file, 1); - os_free(pid_file); + os_free_loose(pid_file); pid_file = NULL; - //os_free(ap_iface_buf); + //os_free_loose(ap_iface_buf); //ap_iface_buf = NULL; if (log_file) diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_config.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_config.c index cf52b26570a2beb9540a2b88f5edc8436dd6156e..c4e1559d9fc4fbb3c0fc5b3cf48ec7de694a68a8 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_config.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_config.c @@ -26,7 +26,7 @@ static void hostapd_config_free_vlan(struct hostapd_bss_config *bss) while (vlan) { prev = vlan; vlan = vlan->next; - os_free(prev); + os_free_loose(prev); } bss->vlan = NULL; @@ -143,14 +143,14 @@ struct hostapd_config * hostapd_config_defaults(void) if (conf == NULL || bss == NULL) { wpa_printf(MSG_ERROR, "Failed to allocate memory for " "configuration data."); - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss = os_calloc(1, sizeof(struct hostapd_bss_config *)); if (conf->bss == NULL) { - os_free(conf); - os_free(bss); + os_free_loose(conf); + os_free_loose(bss); return NULL; } conf->bss[0] = bss; @@ -296,7 +296,7 @@ static void hostapd_config_free_anqp_elem(struct hostapd_bss_config *conf) list))) { dl_list_del(&elem->list); wpabuf_free(elem->payload); - os_free(elem); + os_free_loose(elem); } } #endif @@ -313,8 +313,8 @@ static void hostapd_config_free_sae_passwords(struct hostapd_bss_config *conf) tmp = pw; pw = pw->next; str_clear_free(tmp->password); - os_free(tmp->identifier); - os_free(tmp); + os_free_loose(tmp->identifier); + os_free_loose(tmp); } } #endif @@ -327,7 +327,7 @@ static void hostapd_dpp_controller_conf_free(struct dpp_controller_conf *conf) while (conf) { prev = conf; conf = conf->next; - os_free(prev); + os_free_loose(prev); } } #endif /* CONFIG_DPP2 */ @@ -343,14 +343,14 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) str_clear_free(conf->ssid.wpa_passphrase); hostapd_config_free_wep(&conf->ssid.wep); #ifdef CONFIG_FULL_DYNAMIC_VLAN - os_free(conf->ssid.vlan_tagged_interface); + os_free_loose(conf->ssid.vlan_tagged_interface); #endif /* CONFIG_FULL_DYNAMIC_VLAN */ - os_free(conf->rsn_preauth_interfaces); + os_free_loose(conf->rsn_preauth_interfaces); #ifdef CONFIG_FULL_HOSTAPD - os_free(conf->ctrl_interface); + os_free_loose(conf->ctrl_interface); hostapd_config_free_vlan(conf); - os_free(conf->time_zone); + os_free_loose(conf->time_zone); #endif #ifdef CONFIG_IEEE80211R_AP @@ -363,7 +363,7 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) while (r0kh) { r0kh_prev = r0kh; r0kh = r0kh->next; - os_free(r0kh_prev); + os_free_loose(r0kh_prev); } r1kh = conf->r1kh_list; @@ -371,7 +371,7 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) while (r1kh) { r1kh_prev = r1kh; r1kh = r1kh->next; - os_free(r1kh_prev); + os_free_loose(r1kh_prev); } } #endif /* CONFIG_IEEE80211R_AP */ @@ -384,21 +384,21 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) wpabuf_free(conf->assocresp_elements); #ifdef CONFIG_SAE_AP - os_free(conf->sae_groups); + os_free_loose(conf->sae_groups); #endif #ifdef CONFIG_OWE - os_free(conf->owe_groups); + os_free_loose(conf->owe_groups); #endif /* CONFIG_OWE */ #ifdef CONFIG_FULL_HOSTAPD - os_free(conf->wowlan_triggers); - os_free(conf->server_id); + os_free_loose(conf->wowlan_triggers); + os_free_loose(conf->server_id); #endif - os_free(conf->no_probe_resp_if_seen_on); - os_free(conf->no_auth_if_seen_on); + os_free_loose(conf->no_probe_resp_if_seen_on); + os_free_loose(conf->no_auth_if_seen_on); #ifdef CONFIG_DPP - os_free(conf->dpp_connector); + os_free_loose(conf->dpp_connector); wpabuf_free(conf->dpp_netaccesskey); wpabuf_free(conf->dpp_csign); #ifdef CONFIG_DPP2 @@ -410,7 +410,7 @@ void hostapd_config_free_bss(struct hostapd_bss_config *conf) hostapd_config_free_sae_passwords(conf); #endif - os_free(conf); + os_free_loose(conf); } @@ -427,16 +427,16 @@ void hostapd_config_free(struct hostapd_config *conf) for (i = 0; i < conf->num_bss; i++) hostapd_config_free_bss(conf->bss[i]); - os_free(conf->bss); - os_free(conf->supported_rates); - os_free(conf->basic_rates); - os_free(conf->acs_ch_list.range); - os_free(conf->driver_params); + os_free_loose(conf->bss); + os_free_loose(conf->supported_rates); + os_free_loose(conf->basic_rates); + os_free_loose(conf->acs_ch_list.range); + os_free_loose(conf->driver_params); #ifdef CONFIG_ACS - os_free(conf->acs_chan_bias); + os_free_loose(conf->acs_chan_bias); #endif /* CONFIG_ACS */ - os_free(conf); + os_free_loose(conf); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_drv_ops.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_drv_ops.c index 0d82a6a146b0405fefa80a892b3bf92c3448fe3c..29796b0a3bb121e55f2f10d648678f9d94be6141 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_drv_ops.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_drv_ops.c @@ -1,939 +1,943 @@ -/* - * hostapd - Driver operations - * Copyright (c) 2009-2010, Jouni Malinen - * - * This software may be distributed under the terms of the BSD license. - * See README for more details. - */ - -#include "utils/includes.h" - -#include "utils/common.h" -#include "common/ieee802_11_defs.h" -#include "common/hw_features_common.h" -#include "wps/wps.h" -#include "ap/hostapd.h" -#include "ieee802_11.h" -#include "ap/sta_info.h" -#include "ap_config.h" -#include "p2p_hostapd.h" -#include "wpa_auth.h" -#include "ap_drv_ops.h" - - -u32 hostapd_sta_flags_to_drv(u32 flags) -{ - int res = 0; - if (flags & WLAN_STA_AUTHORIZED) - res |= WPA_STA_AUTHORIZED; - if (flags & WLAN_STA_WMM) - res |= WPA_STA_WMM; - if (flags & WLAN_STA_SHORT_PREAMBLE) - res |= WPA_STA_SHORT_PREAMBLE; - if (flags & WLAN_STA_MFP) - res |= WPA_STA_MFP; - if (flags & WLAN_STA_AUTH) - res |= WPA_STA_AUTHENTICATED; - if (flags & WLAN_STA_ASSOC) - res |= WPA_STA_ASSOCIATED; - return res; -} - - -static int add_buf(struct wpabuf **dst, const struct wpabuf *src) -{ - if (!src) - return 0; - if (wpabuf_resize(dst, wpabuf_len(src)) != 0) - return -1; - wpabuf_put_buf(*dst, src); - return 0; -} - - -static int add_buf_data(struct wpabuf **dst, const u8 *data, size_t len) -{ - if (!data || !len) - return 0; - if (wpabuf_resize(dst, len) != 0) - return -1; - wpabuf_put_data(*dst, data, len); - return 0; -} - - -int hostapd_build_ap_extra_ies(struct hostapd_data *hapd, - struct wpabuf **beacon_ret, - struct wpabuf **proberesp_ret, - struct wpabuf **assocresp_ret) -{ -#ifdef CONFIG_FULL_HOSTAPD - struct wpabuf *beacon = NULL, *proberesp = NULL, *assocresp = NULL; - u8 buf[200], *pos; - - *beacon_ret = *proberesp_ret = *assocresp_ret = NULL; - - pos = buf; - pos = hostapd_eid_time_adv(hapd, pos); - if (add_buf_data(&beacon, buf, pos - buf) < 0) - goto fail; - pos = hostapd_eid_time_zone(hapd, pos); - if (add_buf_data(&proberesp, buf, pos - buf) < 0) - goto fail; - - pos = buf; - pos = hostapd_eid_ext_capab(hapd, pos); - if (add_buf_data(&assocresp, buf, pos - buf) < 0) - goto fail; - pos = hostapd_eid_interworking(hapd, pos); - pos = hostapd_eid_adv_proto(hapd, pos); - pos = hostapd_eid_roaming_consortium(hapd, pos); - if (add_buf_data(&beacon, buf, pos - buf) < 0 || - add_buf_data(&proberesp, buf, pos - buf) < 0) - goto fail; - - -#ifdef CONFIG_P2P - if (add_buf(&beacon, hapd->p2p_beacon_ie) < 0 || - add_buf(&proberesp, hapd->p2p_probe_resp_ie) < 0) - goto fail; -#endif /* CONFIG_P2P */ - -#ifdef CONFIG_P2P_MANAGER - if (hapd->conf->p2p & P2P_MANAGE) { - if (wpabuf_resize(&beacon, 100) == 0) { - u8 *start, *p; - start = wpabuf_put(beacon, 0); - p = hostapd_eid_p2p_manage(hapd, start); - wpabuf_put(beacon, p - start); - } - - if (wpabuf_resize(&proberesp, 100) == 0) { - u8 *start, *p; - start = wpabuf_put(proberesp, 0); - p = hostapd_eid_p2p_manage(hapd, start); - wpabuf_put(proberesp, p - start); - } - } -#endif /* CONFIG_P2P_MANAGER */ - -#ifdef CONFIG_WPS - if (hapd->conf->wps_state) { - struct wpabuf *a = wps_build_assoc_resp_ie(); - add_buf(&assocresp, a); - wpabuf_free(a); - } -#endif /* CONFIG_WPS */ - -#ifdef CONFIG_P2P_MANAGER - if (hapd->conf->p2p & P2P_MANAGE) { - if (wpabuf_resize(&assocresp, 100) == 0) { - u8 *start, *p; - start = wpabuf_put(assocresp, 0); - p = hostapd_eid_p2p_manage(hapd, start); - wpabuf_put(assocresp, p - start); - } - } -#endif /* CONFIG_P2P_MANAGER */ - -#ifdef CONFIG_WIFI_DISPLAY - if (hapd->p2p_group) { - struct wpabuf *a; - a = p2p_group_assoc_resp_ie(hapd->p2p_group, P2P_SC_SUCCESS); - add_buf(&assocresp, a); - wpabuf_free(a); - } -#endif /* CONFIG_WIFI_DISPLAY */ - -#ifdef CONFIG_HS20 - pos = hostapd_eid_hs20_indication(hapd, buf); - if (add_buf_data(&beacon, buf, pos - buf) < 0 || - add_buf_data(&proberesp, buf, pos - buf) < 0) - goto fail; - - pos = hostapd_eid_osen(hapd, buf); - if (add_buf_data(&beacon, buf, pos - buf) < 0 || - add_buf_data(&proberesp, buf, pos - buf) < 0) - goto fail; -#endif /* CONFIG_HS20 */ - -#ifdef CONFIG_MBO - if (hapd->conf->mbo_enabled || - OCE_STA_CFON_ENABLED(hapd) || OCE_AP_ENABLED(hapd)) { - pos = hostapd_eid_mbo(hapd, buf, sizeof(buf)); - if (add_buf_data(&beacon, buf, pos - buf) < 0 || - add_buf_data(&proberesp, buf, pos - buf) < 0 || - add_buf_data(&assocresp, buf, pos - buf) < 0) - goto fail; - } -#endif /* CONFIG_MBO */ - -#ifdef CONFIG_OWE - pos = hostapd_eid_owe_trans(hapd, buf, sizeof(buf)); - if (add_buf_data(&beacon, buf, pos - buf) < 0 || - add_buf_data(&proberesp, buf, pos - buf) < 0) - goto fail; -#endif /* CONFIG_OWE */ - - add_buf(&beacon, hapd->conf->vendor_elements); - add_buf(&proberesp, hapd->conf->vendor_elements); - add_buf(&assocresp, hapd->conf->assocresp_elements); - - *beacon_ret = beacon; - *proberesp_ret = proberesp; - *assocresp_ret = assocresp; - - return 0; - -fail: - wpabuf_free(beacon); - wpabuf_free(proberesp); - wpabuf_free(assocresp); - return -1; - -#else - *beacon_ret = *proberesp_ret = *assocresp_ret = NULL; - - return 0; -#endif -} - - -void hostapd_free_ap_extra_ies(struct hostapd_data *hapd, - struct wpabuf *beacon, - struct wpabuf *proberesp, - struct wpabuf *assocresp) -{ - wpabuf_free(beacon); - wpabuf_free(proberesp); - wpabuf_free(assocresp); -} - - -int hostapd_reset_ap_wps_ie(struct hostapd_data *hapd) -{ - if (hapd->driver == NULL || hapd->driver->set_ap_wps_ie == NULL) - return 0; - - return hapd->driver->set_ap_wps_ie(hapd->drv_priv, NULL, NULL, NULL); -} - - -int hostapd_set_ap_wps_ie(struct hostapd_data *hapd) -{ - struct wpabuf *beacon = 0, *proberesp = 0, *assocresp = 0; - int ret; - - if (hapd->driver == NULL || hapd->driver->set_ap_wps_ie == NULL) - return 0; - - if (hostapd_build_ap_extra_ies(hapd, &beacon, &proberesp, &assocresp) < 0) - return -1; - - ret = hapd->driver->set_ap_wps_ie(hapd->drv_priv, beacon, proberesp, - assocresp); - - hostapd_free_ap_extra_ies(hapd, beacon, proberesp, assocresp); - - return ret; -} - - -int hostapd_set_authorized(struct hostapd_data *hapd, - struct sta_info *sta, int authorized) -{ - if (authorized) { - return hostapd_sta_set_flags(hapd, sta->addr, - hostapd_sta_flags_to_drv( - sta->flags), - WPA_STA_AUTHORIZED, ~0); - } - - return hostapd_sta_set_flags(hapd, sta->addr, - hostapd_sta_flags_to_drv(sta->flags), - 0, ~WPA_STA_AUTHORIZED); -} - - -int hostapd_set_sta_flags(struct hostapd_data *hapd, struct sta_info *sta) -{ - int set_flags, total_flags, flags_and, flags_or; - total_flags = hostapd_sta_flags_to_drv(sta->flags); - set_flags = WPA_STA_SHORT_PREAMBLE | WPA_STA_WMM | WPA_STA_MFP; - if (((!hapd->conf->ieee802_1x && !hapd->conf->wpa) || - sta->auth_alg == WLAN_AUTH_FT) && - sta->flags & WLAN_STA_AUTHORIZED) - set_flags |= WPA_STA_AUTHORIZED; - flags_or = total_flags & set_flags; - flags_and = total_flags | ~set_flags; - return hostapd_sta_set_flags(hapd, sta->addr, total_flags, - flags_or, flags_and); -} - - -int hostapd_set_drv_ieee8021x(struct hostapd_data *hapd, const char *ifname, - int enabled) -{ - struct wpa_bss_params params; - os_memset(¶ms, 0, sizeof(params)); - params.ifname = ifname; - params.enabled = enabled; - if (enabled) { - params.wpa = hapd->conf->wpa; - params.ieee802_1x = hapd->conf->ieee802_1x; - params.wpa_group = hapd->conf->wpa_group; - if ((hapd->conf->wpa & (WPA_PROTO_WPA | WPA_PROTO_RSN)) == - (WPA_PROTO_WPA | WPA_PROTO_RSN)) - params.wpa_pairwise = hapd->conf->wpa_pairwise | - hapd->conf->rsn_pairwise; - else if (hapd->conf->wpa & WPA_PROTO_RSN) - params.wpa_pairwise = hapd->conf->rsn_pairwise; - else if (hapd->conf->wpa & WPA_PROTO_WPA) - params.wpa_pairwise = hapd->conf->wpa_pairwise; - params.wpa_key_mgmt = hapd->conf->wpa_key_mgmt; - params.rsn_preauth = hapd->conf->rsn_preauth; -#ifdef CONFIG_IEEE80211W_AP - params.ieee80211w = hapd->conf->ieee80211w; -#endif /* CONFIG_IEEE80211W_AP */ - } - return hostapd_set_ieee8021x(hapd, ¶ms); -} - -#ifdef CONFIG_FULL_HOSTAPD -int hostapd_vlan_if_add(struct hostapd_data *hapd, const char *ifname) -{ - char force_ifname[IFNAMSIZ]; - u8 if_addr[ETH_ALEN]; - return hostapd_if_add(hapd, WPA_IF_AP_VLAN, ifname, hapd->own_addr, - NULL, NULL, force_ifname, if_addr, NULL, 0); -} - - -int hostapd_vlan_if_remove(struct hostapd_data *hapd, const char *ifname) -{ - return hostapd_if_remove(hapd, WPA_IF_AP_VLAN, ifname); -} - - -int hostapd_set_wds_sta(struct hostapd_data *hapd, char *ifname_wds, - const u8 *addr, int aid, int val) -{ - const char *bridge = NULL; - - if (hapd->driver == NULL || hapd->driver->set_wds_sta == NULL) - return -1; - if (hapd->conf->wds_bridge[0]) - bridge = hapd->conf->wds_bridge; - else if (hapd->conf->bridge[0]) - bridge = hapd->conf->bridge; - return hapd->driver->set_wds_sta(hapd->drv_priv, addr, aid, val, - bridge, ifname_wds); -} -#endif - -int hostapd_add_sta_node(struct hostapd_data *hapd, const u8 *addr, - u16 auth_alg) -{ - if (hapd->driver == NULL || hapd->driver->add_sta_node == NULL) - return 0; - return hapd->driver->add_sta_node(hapd->drv_priv, addr, auth_alg); -} - - -int hostapd_sta_auth(struct hostapd_data *hapd, const u8 *addr, - u16 seq, u16 status, const u8 *ie, size_t len) -{ - struct wpa_driver_sta_auth_params params; - if (hapd->driver == NULL || hapd->driver->sta_auth == NULL) - return 0; - - os_memset(¶ms, 0, sizeof(params)); - - - params.own_addr = hapd->own_addr; - params.addr = addr; - params.seq = seq; - params.status = status; - params.ie = ie; - params.len = len; - - return hapd->driver->sta_auth(hapd->drv_priv, ¶ms); -} - - -int hostapd_sta_assoc(struct hostapd_data *hapd, const u8 *addr, - int reassoc, u16 status, const u8 *ie, size_t len) -{ - if (hapd->driver == NULL || hapd->driver->sta_assoc == NULL) - return 0; - return hapd->driver->sta_assoc(hapd->drv_priv, hapd->own_addr, addr, - reassoc, status, ie, len); -} - - -int hostapd_sta_add(struct hostapd_data *hapd, - const u8 *addr, u16 aid, u16 capability, - const u8 *supp_rates, size_t supp_rates_len, - u16 listen_interval, - const struct ieee80211_ht_capabilities *ht_capab, - const struct ieee80211_vht_capabilities *vht_capab, - const struct ieee80211_he_capabilities *he_capab, - size_t he_capab_len, - u32 flags, u8 qosinfo, u8 vht_opmode, int supp_p2p_ps, - int set) -{ - struct hostapd_sta_add_params params; - - if (hapd->driver == NULL) - return 0; - if (hapd->driver->sta_add == NULL) - return 0; - - os_memset(¶ms, 0, sizeof(params)); - params.addr = addr; - params.aid = aid; - params.capability = capability; - params.supp_rates = supp_rates; - params.supp_rates_len = supp_rates_len; - params.listen_interval = listen_interval; - params.ht_capabilities = ht_capab; - params.vht_capabilities = vht_capab; - params.he_capab = he_capab; - params.he_capab_len = he_capab_len; - params.vht_opmode_enabled = !!(flags & WLAN_STA_VHT_OPMODE_ENABLED); - params.vht_opmode = vht_opmode; - params.flags = hostapd_sta_flags_to_drv(flags); - params.qosinfo = qosinfo; - params.support_p2p_ps = supp_p2p_ps; - params.set = set; - return hapd->driver->sta_add(hapd->drv_priv, ¶ms); -} - - -int hostapd_add_tspec(struct hostapd_data *hapd, const u8 *addr, - u8 *tspec_ie, size_t tspec_ielen) -{ - if (hapd->driver == NULL || hapd->driver->add_tspec == NULL) - return 0; - return hapd->driver->add_tspec(hapd->drv_priv, addr, tspec_ie, - tspec_ielen); -} - - -int hostapd_set_privacy(struct hostapd_data *hapd, int enabled) -{ - if (hapd->driver == NULL || hapd->driver->set_privacy == NULL) - return 0; - return hapd->driver->set_privacy(hapd->drv_priv, enabled); -} - - -int hostapd_set_generic_elem(struct hostapd_data *hapd, const u8 *elem, - size_t elem_len) -{ - if (hapd->driver == NULL || hapd->driver->set_generic_elem == NULL) - return 0; - return hapd->driver->set_generic_elem(hapd->drv_priv, elem, elem_len); -} - - -int hostapd_get_ssid(struct hostapd_data *hapd, u8 *buf, size_t len) -{ - if (hapd->driver == NULL || hapd->driver->hapd_get_ssid == NULL) - return 0; - return hapd->driver->hapd_get_ssid(hapd->drv_priv, buf, len); -} - - -int hostapd_set_ssid(struct hostapd_data *hapd, const u8 *buf, size_t len) -{ - if (hapd->driver == NULL || hapd->driver->hapd_set_ssid == NULL) - return 0; - return hapd->driver->hapd_set_ssid(hapd->drv_priv, buf, len); -} - - -int hostapd_if_add(struct hostapd_data *hapd, enum wpa_driver_if_type type, - const char *ifname, const u8 *addr, void *bss_ctx, - void **drv_priv, char *force_ifname, u8 *if_addr, - const char *bridge, int use_existing) -{ - if (hapd->driver == NULL || hapd->driver->if_add == NULL) - return -1; - return hapd->driver->if_add(hapd->drv_priv, type, ifname, addr, - bss_ctx, drv_priv, force_ifname, if_addr, - bridge, use_existing, 1); -} - - -int hostapd_if_remove(struct hostapd_data *hapd, enum wpa_driver_if_type type, - const char *ifname) -{ - if (hapd->driver == NULL || hapd->drv_priv == NULL || - hapd->driver->if_remove == NULL) - return -1; - return hapd->driver->if_remove(hapd->drv_priv, type, ifname); -} - - -int hostapd_set_ieee8021x(struct hostapd_data *hapd, - struct wpa_bss_params *params) -{ - if (hapd->driver == NULL || hapd->driver->set_ieee8021x == NULL) - return 0; - return hapd->driver->set_ieee8021x(hapd->drv_priv, params); -} - - -int hostapd_get_seqnum(const char *ifname, struct hostapd_data *hapd, - const u8 *addr, int idx, u8 *seq) -{ - if (hapd->driver == NULL || hapd->driver->get_seqnum == NULL) - return 0; - return hapd->driver->get_seqnum(ifname, hapd->drv_priv, addr, idx, - seq); -} - - -int hostapd_flush(struct hostapd_data *hapd) -{ - if (hapd->driver == NULL || hapd->driver->flush == NULL) - return 0; - return hapd->driver->flush(hapd->drv_priv); -} - - -int hostapd_set_freq(struct hostapd_data *hapd, enum hostapd_hw_mode mode, - int freq, int channel, int ht_enabled, int vht_enabled, - int he_enabled, - int sec_channel_offset, int oper_chwidth, - int center_segment0, int center_segment1) -{ - struct hostapd_freq_params data; - struct hostapd_hw_modes *cmode = hapd->iface->current_mode; - - if (hostapd_set_freq_params(&data, mode, freq, channel, ht_enabled, - vht_enabled, he_enabled, sec_channel_offset, - oper_chwidth, - center_segment0, center_segment1, - cmode ? cmode->vht_capab : 0, -#ifdef CONFIG_IEEE80211AX - cmode ? &cmode->he_capab[IEEE80211_MODE_AP] : -#endif - NULL)) - return -1; - - if (hapd->driver == NULL) - return 0; - if (hapd->driver->set_freq == NULL) - return 0; - return hapd->driver->set_freq(hapd->drv_priv, &data); -} - -int hostapd_set_rts(struct hostapd_data *hapd, int rts) -{ - if (hapd->driver == NULL || hapd->driver->set_rts == NULL) - return 0; - return hapd->driver->set_rts(hapd->drv_priv, rts); -} - - -int hostapd_set_frag(struct hostapd_data *hapd, int frag) -{ - if (hapd->driver == NULL || hapd->driver->set_frag == NULL) - return 0; - return hapd->driver->set_frag(hapd->drv_priv, frag); -} - - -int hostapd_sta_set_flags(struct hostapd_data *hapd, u8 *addr, - int total_flags, int flags_or, int flags_and) -{ - if (hapd->driver == NULL || hapd->driver->sta_set_flags == NULL) - return 0; - return hapd->driver->sta_set_flags(hapd->drv_priv, addr, total_flags, - flags_or, flags_and); -} - - -int hostapd_sta_set_airtime_weight(struct hostapd_data *hapd, const u8 *addr, - unsigned int weight) -{ - if (!hapd->driver || !hapd->driver->sta_set_airtime_weight) - return 0; - return hapd->driver->sta_set_airtime_weight(hapd->drv_priv, addr, - weight); -} - - -int hostapd_set_country(struct hostapd_data *hapd, const char *country) -{ - if (hapd->driver == NULL || - hapd->driver->set_country == NULL) - return 0; - return hapd->driver->set_country(hapd->drv_priv, country); -} - - -int hostapd_set_tx_queue_params(struct hostapd_data *hapd, int queue, int aifs, - int cw_min, int cw_max, int burst_time) -{ - if (hapd->driver == NULL || hapd->driver->set_tx_queue_params == NULL) - return 0; - return hapd->driver->set_tx_queue_params(hapd->drv_priv, queue, aifs, - cw_min, cw_max, burst_time); -} - - -struct hostapd_hw_modes * -hostapd_get_hw_feature_data(struct hostapd_data *hapd, u16 *num_modes, - u16 *flags, u8 *dfs_domain) -{ - if (hapd->driver == NULL || - hapd->driver->get_hw_feature_data == NULL) - return NULL; - return hapd->driver->get_hw_feature_data(hapd->drv_priv, num_modes, - flags, dfs_domain); -} - - -int hostapd_driver_commit(struct hostapd_data *hapd) -{ - if (hapd->driver == NULL || hapd->driver->commit == NULL) - return 0; - return hapd->driver->commit(hapd->drv_priv); -} - - -int hostapd_drv_none(struct hostapd_data *hapd) -{ - return hapd->driver && os_strcmp(hapd->driver->name, "none") == 0; -} - - -int hostapd_driver_scan(struct hostapd_data *hapd, - struct wpa_driver_scan_params *params) -{ - if (hapd->driver && hapd->driver->scan2) - return hapd->driver->scan2(hapd->drv_priv, params); - return -1; -} - - -struct wpa_scan_results * hostapd_driver_get_scan_results( - struct hostapd_data *hapd) -{ - if (hapd->driver && hapd->driver->get_scan_results2) - return hapd->driver->get_scan_results2(hapd->drv_priv); - return NULL; -} - - -int hostapd_driver_set_noa(struct hostapd_data *hapd, u8 count, int start, - int duration) -{ - if (hapd->driver && hapd->driver->set_noa) - return hapd->driver->set_noa(hapd->drv_priv, count, start, - duration); - return -1; -} - - -int hostapd_drv_set_key(const char *ifname, struct hostapd_data *hapd, - enum wpa_alg alg, const u8 *addr, - int key_idx, int set_tx, - const u8 *seq, size_t seq_len, - const u8 *key, size_t key_len) -{ - if (hapd->driver == NULL || hapd->driver->set_key == NULL) - return 0; - return hapd->driver->set_key(ifname, hapd->drv_priv, alg, addr, - key_idx, set_tx, seq, seq_len, key, - key_len); -} - - -int hostapd_drv_send_mlme(struct hostapd_data *hapd, - const void *msg, size_t len, int noack) -{ - if (!hapd->driver || !hapd->driver->send_mlme || !hapd->drv_priv) - return 0; - return hapd->driver->send_mlme(hapd->drv_priv, msg, len, noack, 0, - NULL, 0); -} - - -int hostapd_drv_send_mlme_csa(struct hostapd_data *hapd, - const void *msg, size_t len, int noack, - const u16 *csa_offs, size_t csa_offs_len) -{ - if (hapd->driver == NULL || hapd->driver->send_mlme == NULL) - return 0; - return hapd->driver->send_mlme(hapd->drv_priv, msg, len, noack, 0, - csa_offs, csa_offs_len); -} - - -int hostapd_drv_sta_deauth(struct hostapd_data *hapd, - const u8 *addr, int reason) -{ - if (!hapd->driver || !hapd->driver->sta_deauth || !hapd->drv_priv) - return 0; - return hapd->driver->sta_deauth(hapd->drv_priv, hapd->own_addr, addr, - reason); -} - - -int hostapd_drv_sta_disassoc(struct hostapd_data *hapd, - const u8 *addr, int reason) -{ - if (!hapd->driver || !hapd->driver->sta_disassoc || !hapd->drv_priv) - return 0; - return hapd->driver->sta_disassoc(hapd->drv_priv, hapd->own_addr, addr, - reason); -} - - -int hostapd_drv_wnm_oper(struct hostapd_data *hapd, enum wnm_oper oper, - const u8 *peer, u8 *buf, u16 *buf_len) -{ - if (hapd->driver == NULL || hapd->driver->wnm_oper == NULL) - return -1; - return hapd->driver->wnm_oper(hapd->drv_priv, oper, peer, buf, - buf_len); -} - - -int hostapd_drv_send_action(struct hostapd_data *hapd, unsigned int freq, - unsigned int wait, const u8 *dst, const u8 *data, - size_t len) -{ - const u8 *bssid; - const u8 wildcard_bssid[ETH_ALEN] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - }; - - if (!hapd->driver || !hapd->driver->send_action || !hapd->drv_priv) - return 0; - bssid = hapd->own_addr; - if (!is_multicast_ether_addr(dst) && - len > 0 && data[0] == WLAN_ACTION_PUBLIC) { - struct sta_info *sta; - - /* - * Public Action frames to a STA that is not a member of the BSS - * shall use wildcard BSSID value. - */ - sta = ap_get_sta(hapd, dst); - if (!sta || !(sta->flags & WLAN_STA_ASSOC)) - bssid = wildcard_bssid; - } else if (is_broadcast_ether_addr(dst) && - len > 0 && data[0] == WLAN_ACTION_PUBLIC) { - /* - * The only current use case of Public Action frames with - * broadcast destination address is DPP PKEX. That case is - * directing all devices and not just the STAs within the BSS, - * so have to use the wildcard BSSID value. - */ - bssid = wildcard_bssid; - } - return hapd->driver->send_action(hapd->drv_priv, freq, wait, dst, - hapd->own_addr, bssid, data, len, 0); -} - - -int hostapd_drv_send_action_addr3_ap(struct hostapd_data *hapd, - unsigned int freq, - unsigned int wait, const u8 *dst, - const u8 *data, size_t len) -{ - if (hapd->driver == NULL || hapd->driver->send_action == NULL) - return 0; - return hapd->driver->send_action(hapd->drv_priv, freq, wait, dst, - hapd->own_addr, hapd->own_addr, data, - len, 0); -} - - -#ifdef CONFIG_FULL_HOSTAPD -int hostapd_start_dfs_cac(struct hostapd_iface *iface, - enum hostapd_hw_mode mode, int freq, - int channel, int ht_enabled, int vht_enabled, - int he_enabled, - int sec_channel_offset, int oper_chwidth, - int center_segment0, int center_segment1) -{ - struct hostapd_data *hapd = iface->bss[0]; - struct hostapd_freq_params data; - int res; - struct hostapd_hw_modes *cmode = iface->current_mode; - - if (!hapd->driver || !hapd->driver->start_dfs_cac || !cmode) - return 0; - - if (!iface->conf->ieee80211h) { - wpa_printf(MSG_ERROR, "Can't start DFS CAC, DFS functionality " - "is not enabled"); - return -1; - } - - if (hostapd_set_freq_params(&data, mode, freq, channel, ht_enabled, - vht_enabled, he_enabled, sec_channel_offset, - oper_chwidth, center_segment0, - center_segment1, - cmode->vht_capab, - &cmode->he_capab[IEEE80211_MODE_AP])) { - wpa_printf(MSG_ERROR, "Can't set freq params"); - return -1; - } - - res = hapd->driver->start_dfs_cac(hapd->drv_priv, &data); - if (!res) { - iface->cac_started = 1; - os_get_reltime(&iface->dfs_cac_start); - } - - return res; -} -#endif - -int hostapd_drv_set_qos_map(struct hostapd_data *hapd, - const u8 *qos_map_set, u8 qos_map_set_len) -{ - if (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv) - return 0; - return hapd->driver->set_qos_map(hapd->drv_priv, qos_map_set, - qos_map_set_len); -} - - -static void hostapd_get_hw_mode_any_channels(struct hostapd_data *hapd, - struct hostapd_hw_modes *mode, - int acs_ch_list_all, - int **freq_list) -{ - int i; - - for (i = 0; i < mode->num_channels; i++) { - struct hostapd_channel_data *chan = &mode->channels[i]; - - if ((acs_ch_list_all || - freq_range_list_includes(&hapd->iface->conf->acs_ch_list, - chan->chan)) && - !(chan->flag & HOSTAPD_CHAN_DISABLED) && - !(hapd->iface->conf->acs_exclude_dfs && - (chan->flag & HOSTAPD_CHAN_RADAR))) - int_array_add_unique(freq_list, chan->freq); - } -} - - -void hostapd_get_ext_capa(struct hostapd_iface *iface) -{ - struct hostapd_data *hapd = iface->bss[0]; - - if (!hapd->driver || !hapd->driver->get_ext_capab) - return; - - hapd->driver->get_ext_capab(hapd->drv_priv, WPA_IF_AP_BSS, - &iface->extended_capa, - &iface->extended_capa_mask, - &iface->extended_capa_len); -} - - -int hostapd_drv_do_acs(struct hostapd_data *hapd) -{ - struct drv_acs_params params; - int ret, i, acs_ch_list_all = 0; - u8 *channels = NULL; - unsigned int num_channels = 0; - struct hostapd_hw_modes *mode; - int *freq_list = NULL; - - if (hapd->driver == NULL || hapd->driver->do_acs == NULL) - return 0; - - os_memset(¶ms, 0, sizeof(params)); - params.hw_mode = hapd->iface->conf->hw_mode; - - /* - * If no chanlist config parameter is provided, include all enabled - * channels of the selected hw_mode. - */ - if (!hapd->iface->conf->acs_ch_list.num) - acs_ch_list_all = 1; - - mode = hapd->iface->current_mode; - if (mode) { - channels = os_malloc(mode->num_channels); - if (channels == NULL) - return -1; - - for (i = 0; i < mode->num_channels; i++) { - struct hostapd_channel_data *chan = &mode->channels[i]; - if (!acs_ch_list_all && - !freq_range_list_includes( - &hapd->iface->conf->acs_ch_list, - chan->chan)) - continue; - if (hapd->iface->conf->acs_exclude_dfs && - (chan->flag & HOSTAPD_CHAN_RADAR)) - continue; - if (!(chan->flag & HOSTAPD_CHAN_DISABLED)) { - channels[num_channels++] = chan->chan; - int_array_add_unique(&freq_list, chan->freq); - } - } - } else { - for (i = 0; i < hapd->iface->num_hw_features; i++) { - mode = &hapd->iface->hw_features[i]; - hostapd_get_hw_mode_any_channels(hapd, mode, - acs_ch_list_all, - &freq_list); - } - } - - params.ch_list = channels; - params.ch_list_len = num_channels; - params.freq_list = freq_list; - - params.ht_enabled = !!(hapd->iface->conf->ieee80211n); - params.ht40_enabled = !!(hapd->iface->conf->ht_capab & - HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET); - params.vht_enabled = !!(hapd->iface->conf->ieee80211ac); - params.ch_width = 20; - if (hapd->iface->conf->ieee80211n && params.ht40_enabled) - params.ch_width = 40; - -#if defined(CONFIG_IEEE80211AC) || defined(CONFIG_IEEE80211AX) - /* Note: VHT20 is defined by combination of ht_capab & oper_chwidth - */ - if ((hapd->iface->conf->ieee80211ax || - hapd->iface->conf->ieee80211ac) && - params.ht40_enabled) { - u8 oper_chwidth = hostapd_get_oper_chwidth(hapd->iface->conf); - - if (oper_chwidth == CHANWIDTH_80MHZ) - params.ch_width = 80; - else if (oper_chwidth == CHANWIDTH_160MHZ || - oper_chwidth == CHANWIDTH_80P80MHZ) - params.ch_width = 160; - } -#endif - - ret = hapd->driver->do_acs(hapd->drv_priv, ¶ms); - os_free(channels); - - return ret; -} - - -int hostapd_drv_update_dh_ie(struct hostapd_data *hapd, const u8 *peer, - u16 reason_code, const u8 *ie, size_t ielen) -{ - if (!hapd->driver || !hapd->driver->update_dh_ie || !hapd->drv_priv) - return 0; - return hapd->driver->update_dh_ie(hapd->drv_priv, peer, reason_code, - ie, ielen); -} +/* + * hostapd - Driver operations + * Copyright (c) 2009-2010, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +#include "utils/includes.h" + +#include "utils/common.h" +#include "common/ieee802_11_defs.h" +#include "common/hw_features_common.h" +#include "wps/wps.h" +#include "ap/hostapd.h" +#include "ieee802_11.h" +#include "ap/sta_info.h" +#include "ap_config.h" +#include "p2p_hostapd.h" +#include "wpa_auth.h" +#include "ap_drv_ops.h" + + +u32 hostapd_sta_flags_to_drv(u32 flags) +{ + int res = 0; + if (flags & WLAN_STA_AUTHORIZED) + res |= WPA_STA_AUTHORIZED; + if (flags & WLAN_STA_WMM) + res |= WPA_STA_WMM; + if (flags & WLAN_STA_SHORT_PREAMBLE) + res |= WPA_STA_SHORT_PREAMBLE; + if (flags & WLAN_STA_MFP) + res |= WPA_STA_MFP; + if (flags & WLAN_STA_AUTH) + res |= WPA_STA_AUTHENTICATED; + if (flags & WLAN_STA_ASSOC) + res |= WPA_STA_ASSOCIATED; + return res; +} + + +static int add_buf(struct wpabuf **dst, const struct wpabuf *src) +{ + if (!src) + return 0; + if (wpabuf_resize(dst, wpabuf_len(src)) != 0) + return -1; + wpabuf_put_buf(*dst, src); + return 0; +} + + +static int add_buf_data(struct wpabuf **dst, const u8 *data, size_t len) +{ + if (!data || !len) + return 0; + if (wpabuf_resize(dst, len) != 0) + return -1; + wpabuf_put_data(*dst, data, len); + return 0; +} + + +int hostapd_build_ap_extra_ies(struct hostapd_data *hapd, + struct wpabuf **beacon_ret, + struct wpabuf **proberesp_ret, + struct wpabuf **assocresp_ret) +{ +#ifdef CONFIG_FULL_HOSTAPD + struct wpabuf *beacon = NULL, *proberesp = NULL, *assocresp = NULL; + u8 buf[200], *pos; + + *beacon_ret = *proberesp_ret = *assocresp_ret = NULL; + + pos = buf; + pos = hostapd_eid_time_adv(hapd, pos); + if (add_buf_data(&beacon, buf, pos - buf) < 0) + goto fail; + pos = hostapd_eid_time_zone(hapd, pos); + if (add_buf_data(&proberesp, buf, pos - buf) < 0) + goto fail; + + pos = buf; + pos = hostapd_eid_ext_capab(hapd, pos); + if (add_buf_data(&assocresp, buf, pos - buf) < 0) + goto fail; + pos = hostapd_eid_interworking(hapd, pos); + pos = hostapd_eid_adv_proto(hapd, pos); + pos = hostapd_eid_roaming_consortium(hapd, pos); + if (add_buf_data(&beacon, buf, pos - buf) < 0 || + add_buf_data(&proberesp, buf, pos - buf) < 0) + goto fail; + + +#ifdef CONFIG_P2P + if (add_buf(&beacon, hapd->p2p_beacon_ie) < 0 || + add_buf(&proberesp, hapd->p2p_probe_resp_ie) < 0) + goto fail; +#endif /* CONFIG_P2P */ + +#ifdef CONFIG_P2P_MANAGER + if (hapd->conf->p2p & P2P_MANAGE) { + if (wpabuf_resize(&beacon, 100) == 0) { + u8 *start, *p; + start = wpabuf_put(beacon, 0); + p = hostapd_eid_p2p_manage(hapd, start); + wpabuf_put(beacon, p - start); + } + + if (wpabuf_resize(&proberesp, 100) == 0) { + u8 *start, *p; + start = wpabuf_put(proberesp, 0); + p = hostapd_eid_p2p_manage(hapd, start); + wpabuf_put(proberesp, p - start); + } + } +#endif /* CONFIG_P2P_MANAGER */ + +#ifdef CONFIG_WPS + if (hapd->conf->wps_state) { + struct wpabuf *a = wps_build_assoc_resp_ie(); + add_buf(&assocresp, a); + wpabuf_free(a); + } +#endif /* CONFIG_WPS */ + +#ifdef CONFIG_P2P_MANAGER + if (hapd->conf->p2p & P2P_MANAGE) { + if (wpabuf_resize(&assocresp, 100) == 0) { + u8 *start, *p; + start = wpabuf_put(assocresp, 0); + p = hostapd_eid_p2p_manage(hapd, start); + wpabuf_put(assocresp, p - start); + } + } +#endif /* CONFIG_P2P_MANAGER */ + +#ifdef CONFIG_WIFI_DISPLAY + if (hapd->p2p_group) { + struct wpabuf *a; + a = p2p_group_assoc_resp_ie(hapd->p2p_group, P2P_SC_SUCCESS); + add_buf(&assocresp, a); + wpabuf_free(a); + } +#endif /* CONFIG_WIFI_DISPLAY */ + +#ifdef CONFIG_HS20 + pos = hostapd_eid_hs20_indication(hapd, buf); + if (add_buf_data(&beacon, buf, pos - buf) < 0 || + add_buf_data(&proberesp, buf, pos - buf) < 0) + goto fail; + + pos = hostapd_eid_osen(hapd, buf); + if (add_buf_data(&beacon, buf, pos - buf) < 0 || + add_buf_data(&proberesp, buf, pos - buf) < 0) + goto fail; +#endif /* CONFIG_HS20 */ + +#ifdef CONFIG_MBO + if (hapd->conf->mbo_enabled || + OCE_STA_CFON_ENABLED(hapd) || OCE_AP_ENABLED(hapd)) { + pos = hostapd_eid_mbo(hapd, buf, sizeof(buf)); + if (add_buf_data(&beacon, buf, pos - buf) < 0 || + add_buf_data(&proberesp, buf, pos - buf) < 0 || + add_buf_data(&assocresp, buf, pos - buf) < 0) + goto fail; + } +#endif /* CONFIG_MBO */ + +#ifdef CONFIG_OWE + pos = hostapd_eid_owe_trans(hapd, buf, sizeof(buf)); + if (add_buf_data(&beacon, buf, pos - buf) < 0 || + add_buf_data(&proberesp, buf, pos - buf) < 0) + goto fail; +#endif /* CONFIG_OWE */ + + add_buf(&beacon, hapd->conf->vendor_elements); + add_buf(&proberesp, hapd->conf->vendor_elements); + add_buf(&assocresp, hapd->conf->assocresp_elements); + + *beacon_ret = beacon; + *proberesp_ret = proberesp; + *assocresp_ret = assocresp; + + return 0; + +fail: + wpabuf_free(beacon); + wpabuf_free(proberesp); + wpabuf_free(assocresp); + return -1; + +#else + *beacon_ret = *proberesp_ret = *assocresp_ret = NULL; + + return 0; +#endif +} + + +void hostapd_free_ap_extra_ies(struct hostapd_data *hapd, + struct wpabuf *beacon, + struct wpabuf *proberesp, + struct wpabuf *assocresp) +{ + wpabuf_free(beacon); + wpabuf_free(proberesp); + wpabuf_free(assocresp); +} + + +int hostapd_reset_ap_wps_ie(struct hostapd_data *hapd) +{ + if (hapd->driver == NULL || hapd->driver->set_ap_wps_ie == NULL) + return 0; + + return hapd->driver->set_ap_wps_ie(hapd->drv_priv, NULL, NULL, NULL); +} + + +int hostapd_set_ap_wps_ie(struct hostapd_data *hapd) +{ + struct wpabuf *beacon = 0, *proberesp = 0, *assocresp = 0; + int ret; + + if (hapd->driver == NULL || hapd->driver->set_ap_wps_ie == NULL) + return 0; + + if (hostapd_build_ap_extra_ies(hapd, &beacon, &proberesp, &assocresp) < 0) + return -1; + + ret = hapd->driver->set_ap_wps_ie(hapd->drv_priv, beacon, proberesp, + assocresp); + + hostapd_free_ap_extra_ies(hapd, beacon, proberesp, assocresp); + + return ret; +} + + +int hostapd_set_authorized(struct hostapd_data *hapd, + struct sta_info *sta, int authorized) +{ + if (authorized) { + return hostapd_sta_set_flags(hapd, sta->addr, + hostapd_sta_flags_to_drv( + sta->flags), + WPA_STA_AUTHORIZED, ~0); + } + + return hostapd_sta_set_flags(hapd, sta->addr, + hostapd_sta_flags_to_drv(sta->flags), + 0, ~WPA_STA_AUTHORIZED); +} + + +int hostapd_set_sta_flags(struct hostapd_data *hapd, struct sta_info *sta) +{ + int set_flags, total_flags, flags_and, flags_or; + total_flags = hostapd_sta_flags_to_drv(sta->flags); + set_flags = WPA_STA_SHORT_PREAMBLE | WPA_STA_WMM | WPA_STA_MFP; + if (((!hapd->conf->ieee802_1x && !hapd->conf->wpa) || + sta->auth_alg == WLAN_AUTH_FT) && + sta->flags & WLAN_STA_AUTHORIZED) + set_flags |= WPA_STA_AUTHORIZED; + flags_or = total_flags & set_flags; + flags_and = total_flags | ~set_flags; + return hostapd_sta_set_flags(hapd, sta->addr, total_flags, + flags_or, flags_and); +} + + +int hostapd_set_drv_ieee8021x(struct hostapd_data *hapd, const char *ifname, + int enabled) +{ + struct wpa_bss_params params; + os_memset(¶ms, 0, sizeof(params)); + params.ifname = ifname; + params.enabled = enabled; + if (enabled) { + params.wpa = hapd->conf->wpa; + params.ieee802_1x = hapd->conf->ieee802_1x; + params.wpa_group = hapd->conf->wpa_group; + if ((hapd->conf->wpa & (WPA_PROTO_WPA | WPA_PROTO_RSN)) == + (WPA_PROTO_WPA | WPA_PROTO_RSN)) + params.wpa_pairwise = hapd->conf->wpa_pairwise | + hapd->conf->rsn_pairwise; + else if (hapd->conf->wpa & WPA_PROTO_RSN) + params.wpa_pairwise = hapd->conf->rsn_pairwise; + else if (hapd->conf->wpa & WPA_PROTO_WPA) + params.wpa_pairwise = hapd->conf->wpa_pairwise; + params.wpa_key_mgmt = hapd->conf->wpa_key_mgmt; + params.rsn_preauth = hapd->conf->rsn_preauth; +#ifdef CONFIG_IEEE80211W_AP + params.ieee80211w = hapd->conf->ieee80211w; +#endif /* CONFIG_IEEE80211W_AP */ + } + return hostapd_set_ieee8021x(hapd, ¶ms); +} + +#ifdef CONFIG_FULL_HOSTAPD +int hostapd_vlan_if_add(struct hostapd_data *hapd, const char *ifname) +{ + char force_ifname[IFNAMSIZ]; + u8 if_addr[ETH_ALEN]; + return hostapd_if_add(hapd, WPA_IF_AP_VLAN, ifname, hapd->own_addr, + NULL, NULL, force_ifname, if_addr, NULL, 0); +} + + +int hostapd_vlan_if_remove(struct hostapd_data *hapd, const char *ifname) +{ + return hostapd_if_remove(hapd, WPA_IF_AP_VLAN, ifname); +} + + +int hostapd_set_wds_sta(struct hostapd_data *hapd, char *ifname_wds, + const u8 *addr, int aid, int val) +{ + const char *bridge = NULL; + + if (hapd->driver == NULL || hapd->driver->set_wds_sta == NULL) + return -1; + if (hapd->conf->wds_bridge[0]) + bridge = hapd->conf->wds_bridge; + else if (hapd->conf->bridge[0]) + bridge = hapd->conf->bridge; + return hapd->driver->set_wds_sta(hapd->drv_priv, addr, aid, val, + bridge, ifname_wds); +} +#endif + +int hostapd_add_sta_node(struct hostapd_data *hapd, const u8 *addr, + u16 auth_alg) +{ + if (hapd->driver == NULL || hapd->driver->add_sta_node == NULL) + return 0; + return hapd->driver->add_sta_node(hapd->drv_priv, addr, auth_alg); +} + + +int hostapd_sta_auth(struct hostapd_data *hapd, const u8 *addr, + u16 seq, u16 status, const u8 *ie, size_t len) +{ + struct wpa_driver_sta_auth_params params; + if (hapd->driver == NULL || hapd->driver->sta_auth == NULL) + return 0; + + os_memset(¶ms, 0, sizeof(params)); + + + params.own_addr = hapd->own_addr; + params.addr = addr; + params.seq = seq; + params.status = status; + params.ie = ie; + params.len = len; + + return hapd->driver->sta_auth(hapd->drv_priv, ¶ms); +} + + +int hostapd_sta_assoc(struct hostapd_data *hapd, const u8 *addr, + int reassoc, u16 status, const u8 *ie, size_t len) +{ + if (hapd->driver == NULL || hapd->driver->sta_assoc == NULL) + return 0; + return hapd->driver->sta_assoc(hapd->drv_priv, hapd->own_addr, addr, + reassoc, status, ie, len); +} + + +int hostapd_sta_add(struct hostapd_data *hapd, + const u8 *addr, u16 aid, u16 capability, + const u8 *supp_rates, size_t supp_rates_len, + u16 listen_interval, + const struct ieee80211_ht_capabilities *ht_capab, + const struct ieee80211_vht_capabilities *vht_capab, + const struct ieee80211_he_capabilities *he_capab, + size_t he_capab_len, + u32 flags, u8 qosinfo, u8 vht_opmode, int supp_p2p_ps, + int set) +{ + struct hostapd_sta_add_params params; + + if (hapd->driver == NULL) + return 0; + if (hapd->driver->sta_add == NULL) + return 0; + + os_memset(¶ms, 0, sizeof(params)); + params.addr = addr; + params.aid = aid; + params.capability = capability; + params.supp_rates = supp_rates; + params.supp_rates_len = supp_rates_len; + params.listen_interval = listen_interval; + params.ht_capabilities = ht_capab; + params.vht_capabilities = vht_capab; + params.he_capab = he_capab; + params.he_capab_len = he_capab_len; + params.vht_opmode_enabled = !!(flags & WLAN_STA_VHT_OPMODE_ENABLED); + params.vht_opmode = vht_opmode; + params.flags = hostapd_sta_flags_to_drv(flags); + params.qosinfo = qosinfo; + params.support_p2p_ps = supp_p2p_ps; + params.set = set; + return hapd->driver->sta_add(hapd->drv_priv, ¶ms); +} + + +int hostapd_add_tspec(struct hostapd_data *hapd, const u8 *addr, + u8 *tspec_ie, size_t tspec_ielen) +{ + if (hapd->driver == NULL || hapd->driver->add_tspec == NULL) + return 0; + return hapd->driver->add_tspec(hapd->drv_priv, addr, tspec_ie, + tspec_ielen); +} + + +int hostapd_set_privacy(struct hostapd_data *hapd, int enabled) +{ + if (hapd->driver == NULL || hapd->driver->set_privacy == NULL) + return 0; + return hapd->driver->set_privacy(hapd->drv_priv, enabled); +} + + +int hostapd_set_generic_elem(struct hostapd_data *hapd, const u8 *elem, + size_t elem_len) +{ + if (hapd->driver == NULL || hapd->driver->set_generic_elem == NULL) + return 0; + return hapd->driver->set_generic_elem(hapd->drv_priv, elem, elem_len); +} + + +int hostapd_get_ssid(struct hostapd_data *hapd, u8 *buf, size_t len) +{ + if (hapd->driver == NULL || hapd->driver->hapd_get_ssid == NULL) + return 0; + return hapd->driver->hapd_get_ssid(hapd->drv_priv, buf, len); +} + + +int hostapd_set_ssid(struct hostapd_data *hapd, const u8 *buf, size_t len) +{ + if (hapd->driver == NULL || hapd->driver->hapd_set_ssid == NULL) + return 0; + return hapd->driver->hapd_set_ssid(hapd->drv_priv, buf, len); +} + + +int hostapd_if_add(struct hostapd_data *hapd, enum wpa_driver_if_type type, + const char *ifname, const u8 *addr, void *bss_ctx, + void **drv_priv, char *force_ifname, u8 *if_addr, + const char *bridge, int use_existing) +{ + if (hapd->driver == NULL || hapd->driver->if_add == NULL) + return -1; + return hapd->driver->if_add(hapd->drv_priv, type, ifname, addr, + bss_ctx, drv_priv, force_ifname, if_addr, + bridge, use_existing, 1); +} + + +int hostapd_if_remove(struct hostapd_data *hapd, enum wpa_driver_if_type type, + const char *ifname) +{ + if (hapd->driver == NULL || hapd->drv_priv == NULL || + hapd->driver->if_remove == NULL) + return -1; + return hapd->driver->if_remove(hapd->drv_priv, type, ifname); +} + + +int hostapd_set_ieee8021x(struct hostapd_data *hapd, + struct wpa_bss_params *params) +{ + if (hapd->driver == NULL || hapd->driver->set_ieee8021x == NULL) + return 0; + return hapd->driver->set_ieee8021x(hapd->drv_priv, params); +} + + +int hostapd_get_seqnum(const char *ifname, struct hostapd_data *hapd, + const u8 *addr, int idx, u8 *seq) +{ + if (hapd->driver == NULL || hapd->driver->get_seqnum == NULL) + return 0; + return hapd->driver->get_seqnum(ifname, hapd->drv_priv, addr, idx, + seq); +} + + +int hostapd_flush(struct hostapd_data *hapd) +{ + if (hapd->driver == NULL || hapd->driver->flush == NULL) + return 0; + return hapd->driver->flush(hapd->drv_priv); +} + + +int hostapd_set_freq(struct hostapd_data *hapd, enum hostapd_hw_mode mode, + int freq, int channel, int ht_enabled, int vht_enabled, + int he_enabled, + int sec_channel_offset, int oper_chwidth, + int center_segment0, int center_segment1) +{ + struct hostapd_freq_params data; + struct hostapd_hw_modes *cmode = hapd->iface->current_mode; + + if (hostapd_set_freq_params(&data, mode, freq, channel, ht_enabled, + vht_enabled, he_enabled, sec_channel_offset, + oper_chwidth, + center_segment0, center_segment1, + cmode ? cmode->vht_capab : 0, +#ifdef CONFIG_IEEE80211AX + cmode ? &cmode->he_capab[IEEE80211_MODE_AP] : +#endif + NULL)) + return -1; + + if (hapd->driver == NULL) + return 0; + if (hapd->driver->set_freq == NULL) + return 0; + return hapd->driver->set_freq(hapd->drv_priv, &data); +} + +int hostapd_set_rts(struct hostapd_data *hapd, int rts) +{ + if (hapd->driver == NULL || hapd->driver->set_rts == NULL) + return 0; + return hapd->driver->set_rts(hapd->drv_priv, rts); +} + + +int hostapd_set_frag(struct hostapd_data *hapd, int frag) +{ + if (hapd->driver == NULL || hapd->driver->set_frag == NULL) + return 0; + return hapd->driver->set_frag(hapd->drv_priv, frag); +} + + +int hostapd_sta_set_flags(struct hostapd_data *hapd, u8 *addr, + int total_flags, int flags_or, int flags_and) +{ + if (hapd->driver == NULL || hapd->driver->sta_set_flags == NULL) + return 0; + return hapd->driver->sta_set_flags(hapd->drv_priv, addr, total_flags, + flags_or, flags_and); +} + + +int hostapd_sta_set_airtime_weight(struct hostapd_data *hapd, const u8 *addr, + unsigned int weight) +{ + if (!hapd->driver || !hapd->driver->sta_set_airtime_weight) + return 0; + return hapd->driver->sta_set_airtime_weight(hapd->drv_priv, addr, + weight); +} + + +int hostapd_set_country(struct hostapd_data *hapd, const char *country) +{ + if (hapd->driver == NULL || + hapd->driver->set_country == NULL) + return 0; + return hapd->driver->set_country(hapd->drv_priv, country); +} + + +int hostapd_set_tx_queue_params(struct hostapd_data *hapd, int queue, int aifs, + int cw_min, int cw_max, int burst_time) +{ + if (hapd->driver == NULL || hapd->driver->set_tx_queue_params == NULL) + return 0; + return hapd->driver->set_tx_queue_params(hapd->drv_priv, queue, aifs, + cw_min, cw_max, burst_time); +} + + +struct hostapd_hw_modes * +hostapd_get_hw_feature_data(struct hostapd_data *hapd, u16 *num_modes, + u16 *flags, u8 *dfs_domain) +{ + if (hapd->driver == NULL || + hapd->driver->get_hw_feature_data == NULL) + return NULL; + return hapd->driver->get_hw_feature_data(hapd->drv_priv, num_modes, + flags, dfs_domain); +} + + +int hostapd_driver_commit(struct hostapd_data *hapd) +{ + if (hapd->driver == NULL || hapd->driver->commit == NULL) + return 0; + return hapd->driver->commit(hapd->drv_priv); +} + + +int hostapd_drv_none(struct hostapd_data *hapd) +{ + return hapd->driver && os_strcmp(hapd->driver->name, "none") == 0; +} + + +int hostapd_driver_scan(struct hostapd_data *hapd, + struct wpa_driver_scan_params *params) +{ + if (hapd->driver && hapd->driver->scan2) + return hapd->driver->scan2(hapd->drv_priv, params); + return -1; +} + + +struct wpa_scan_results * hostapd_driver_get_scan_results( + struct hostapd_data *hapd) +{ + if (hapd->driver && hapd->driver->get_scan_results2) + return hapd->driver->get_scan_results2(hapd->drv_priv); + return NULL; +} + + +int hostapd_driver_set_noa(struct hostapd_data *hapd, u8 count, int start, + int duration) +{ + if (hapd->driver && hapd->driver->set_noa) + return hapd->driver->set_noa(hapd->drv_priv, count, start, + duration); + return -1; +} + + +int hostapd_drv_set_key(const char *ifname, struct hostapd_data *hapd, + enum wpa_alg alg, const u8 *addr, + int key_idx, int set_tx, + const u8 *seq, size_t seq_len, + const u8 *key, size_t key_len) +{ + if (hapd->driver == NULL || hapd->driver->set_key == NULL) + { + + return 0; + } + + return hapd->driver->set_key(ifname, hapd->drv_priv, alg, addr, + key_idx, set_tx, seq, seq_len, key, + key_len); +} + + +int hostapd_drv_send_mlme(struct hostapd_data *hapd, + const void *msg, size_t len, int noack) +{ + if (!hapd->driver || !hapd->driver->send_mlme || !hapd->drv_priv) + return 0; + return hapd->driver->send_mlme(hapd->drv_priv, msg, len, noack, 0, + NULL, 0); +} + + +int hostapd_drv_send_mlme_csa(struct hostapd_data *hapd, + const void *msg, size_t len, int noack, + const u16 *csa_offs, size_t csa_offs_len) +{ + if (hapd->driver == NULL || hapd->driver->send_mlme == NULL) + return 0; + return hapd->driver->send_mlme(hapd->drv_priv, msg, len, noack, 0, + csa_offs, csa_offs_len); +} + + +int hostapd_drv_sta_deauth(struct hostapd_data *hapd, + const u8 *addr, int reason) +{ + if (!hapd->driver || !hapd->driver->sta_deauth || !hapd->drv_priv) + return 0; + return hapd->driver->sta_deauth(hapd->drv_priv, hapd->own_addr, addr, + reason); +} + + +int hostapd_drv_sta_disassoc(struct hostapd_data *hapd, + const u8 *addr, int reason) +{ + if (!hapd->driver || !hapd->driver->sta_disassoc || !hapd->drv_priv) + return 0; + return hapd->driver->sta_disassoc(hapd->drv_priv, hapd->own_addr, addr, + reason); +} + + +int hostapd_drv_wnm_oper(struct hostapd_data *hapd, enum wnm_oper oper, + const u8 *peer, u8 *buf, u16 *buf_len) +{ + if (hapd->driver == NULL || hapd->driver->wnm_oper == NULL) + return -1; + return hapd->driver->wnm_oper(hapd->drv_priv, oper, peer, buf, + buf_len); +} + + +int hostapd_drv_send_action(struct hostapd_data *hapd, unsigned int freq, + unsigned int wait, const u8 *dst, const u8 *data, + size_t len) +{ + const u8 *bssid; + const u8 wildcard_bssid[ETH_ALEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }; + + if (!hapd->driver || !hapd->driver->send_action || !hapd->drv_priv) + return 0; + bssid = hapd->own_addr; + if (!is_multicast_ether_addr(dst) && + len > 0 && data[0] == WLAN_ACTION_PUBLIC) { + struct sta_info *sta; + + /* + * Public Action frames to a STA that is not a member of the BSS + * shall use wildcard BSSID value. + */ + sta = ap_get_sta(hapd, dst); + if (!sta || !(sta->flags & WLAN_STA_ASSOC)) + bssid = wildcard_bssid; + } else if (is_broadcast_ether_addr(dst) && + len > 0 && data[0] == WLAN_ACTION_PUBLIC) { + /* + * The only current use case of Public Action frames with + * broadcast destination address is DPP PKEX. That case is + * directing all devices and not just the STAs within the BSS, + * so have to use the wildcard BSSID value. + */ + bssid = wildcard_bssid; + } + return hapd->driver->send_action(hapd->drv_priv, freq, wait, dst, + hapd->own_addr, bssid, data, len, 0); +} + + +int hostapd_drv_send_action_addr3_ap(struct hostapd_data *hapd, + unsigned int freq, + unsigned int wait, const u8 *dst, + const u8 *data, size_t len) +{ + if (hapd->driver == NULL || hapd->driver->send_action == NULL) + return 0; + return hapd->driver->send_action(hapd->drv_priv, freq, wait, dst, + hapd->own_addr, hapd->own_addr, data, + len, 0); +} + + +#ifdef CONFIG_FULL_HOSTAPD +int hostapd_start_dfs_cac(struct hostapd_iface *iface, + enum hostapd_hw_mode mode, int freq, + int channel, int ht_enabled, int vht_enabled, + int he_enabled, + int sec_channel_offset, int oper_chwidth, + int center_segment0, int center_segment1) +{ + struct hostapd_data *hapd = iface->bss[0]; + struct hostapd_freq_params data; + int res; + struct hostapd_hw_modes *cmode = iface->current_mode; + + if (!hapd->driver || !hapd->driver->start_dfs_cac || !cmode) + return 0; + + if (!iface->conf->ieee80211h) { + wpa_printf(MSG_ERROR, "Can't start DFS CAC, DFS functionality " + "is not enabled"); + return -1; + } + + if (hostapd_set_freq_params(&data, mode, freq, channel, ht_enabled, + vht_enabled, he_enabled, sec_channel_offset, + oper_chwidth, center_segment0, + center_segment1, + cmode->vht_capab, + &cmode->he_capab[IEEE80211_MODE_AP])) { + wpa_printf(MSG_ERROR, "Can't set freq params"); + return -1; + } + + res = hapd->driver->start_dfs_cac(hapd->drv_priv, &data); + if (!res) { + iface->cac_started = 1; + os_get_reltime(&iface->dfs_cac_start); + } + + return res; +} +#endif + +int hostapd_drv_set_qos_map(struct hostapd_data *hapd, + const u8 *qos_map_set, u8 qos_map_set_len) +{ + if (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv) + return 0; + return hapd->driver->set_qos_map(hapd->drv_priv, qos_map_set, + qos_map_set_len); +} + + +static void hostapd_get_hw_mode_any_channels(struct hostapd_data *hapd, + struct hostapd_hw_modes *mode, + int acs_ch_list_all, + int **freq_list) +{ + int i; + + for (i = 0; i < mode->num_channels; i++) { + struct hostapd_channel_data *chan = &mode->channels[i]; + + if ((acs_ch_list_all || + freq_range_list_includes(&hapd->iface->conf->acs_ch_list, + chan->chan)) && + !(chan->flag & HOSTAPD_CHAN_DISABLED) && + !(hapd->iface->conf->acs_exclude_dfs && + (chan->flag & HOSTAPD_CHAN_RADAR))) + int_array_add_unique(freq_list, chan->freq); + } +} + + +void hostapd_get_ext_capa(struct hostapd_iface *iface) +{ + struct hostapd_data *hapd = iface->bss[0]; + + if (!hapd->driver || !hapd->driver->get_ext_capab) + return; + + hapd->driver->get_ext_capab(hapd->drv_priv, WPA_IF_AP_BSS, + &iface->extended_capa, + &iface->extended_capa_mask, + &iface->extended_capa_len); +} + + +int hostapd_drv_do_acs(struct hostapd_data *hapd) +{ + struct drv_acs_params params; + int ret, i, acs_ch_list_all = 0; + u8 *channels = NULL; + unsigned int num_channels = 0; + struct hostapd_hw_modes *mode; + int *freq_list = NULL; + + if (hapd->driver == NULL || hapd->driver->do_acs == NULL) + return 0; + + os_memset(¶ms, 0, sizeof(params)); + params.hw_mode = hapd->iface->conf->hw_mode; + + /* + * If no chanlist config parameter is provided, include all enabled + * channels of the selected hw_mode. + */ + if (!hapd->iface->conf->acs_ch_list.num) + acs_ch_list_all = 1; + + mode = hapd->iface->current_mode; + if (mode) { + channels = os_malloc(mode->num_channels); + if (channels == NULL) + return -1; + + for (i = 0; i < mode->num_channels; i++) { + struct hostapd_channel_data *chan = &mode->channels[i]; + if (!acs_ch_list_all && + !freq_range_list_includes( + &hapd->iface->conf->acs_ch_list, + chan->chan)) + continue; + if (hapd->iface->conf->acs_exclude_dfs && + (chan->flag & HOSTAPD_CHAN_RADAR)) + continue; + if (!(chan->flag & HOSTAPD_CHAN_DISABLED)) { + channels[num_channels++] = chan->chan; + int_array_add_unique(&freq_list, chan->freq); + } + } + } else { + for (i = 0; i < hapd->iface->num_hw_features; i++) { + mode = &hapd->iface->hw_features[i]; + hostapd_get_hw_mode_any_channels(hapd, mode, + acs_ch_list_all, + &freq_list); + } + } + + params.ch_list = channels; + params.ch_list_len = num_channels; + params.freq_list = freq_list; + + params.ht_enabled = !!(hapd->iface->conf->ieee80211n); + params.ht40_enabled = !!(hapd->iface->conf->ht_capab & + HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET); + params.vht_enabled = !!(hapd->iface->conf->ieee80211ac); + params.ch_width = 20; + if (hapd->iface->conf->ieee80211n && params.ht40_enabled) + params.ch_width = 40; + +#if defined(CONFIG_IEEE80211AC) || defined(CONFIG_IEEE80211AX) + /* Note: VHT20 is defined by combination of ht_capab & oper_chwidth + */ + if ((hapd->iface->conf->ieee80211ax || + hapd->iface->conf->ieee80211ac) && + params.ht40_enabled) { + u8 oper_chwidth = hostapd_get_oper_chwidth(hapd->iface->conf); + + if (oper_chwidth == CHANWIDTH_80MHZ) + params.ch_width = 80; + else if (oper_chwidth == CHANWIDTH_160MHZ || + oper_chwidth == CHANWIDTH_80P80MHZ) + params.ch_width = 160; + } +#endif + + ret = hapd->driver->do_acs(hapd->drv_priv, ¶ms); + os_free_loose(channels); + + return ret; +} + + +int hostapd_drv_update_dh_ie(struct hostapd_data *hapd, const u8 *peer, + u16 reason_code, const u8 *ie, size_t ielen) +{ + if (!hapd->driver || !hapd->driver->update_dh_ie || !hapd->drv_priv) + return 0; + return hapd->driver->update_dh_ie(hapd->drv_priv, peer, reason_code, + ie, ielen); +} diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_list.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_list.c index 1930231a46e2a8a3af079d352ded4465e098039c..de285c0bf3f95d7cc5fc13f99511c1c0cb1b46ec 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_list.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ap_list.c @@ -122,7 +122,7 @@ static void ap_free_ap(struct hostapd_iface *iface, struct ap_info *ap) ap_ap_list_del(iface, ap); iface->num_ap--; - os_free(ap); + os_free_loose(ap); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/beacon.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/beacon.c index d414655292608a1ba5a9bfd68906b7493b59289b..542e5fa4e5c8f16946d10332e486a0cdfb645f46 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/beacon.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/beacon.c @@ -930,7 +930,7 @@ void handle_probe_req(struct hostapd_data *hapd, if (ret < 0) wpa_printf(MSG_INFO, "handle_probe_req: send failed"); - os_free(resp); + os_free_loose(resp); wpa_printf(MSG_EXCESSIVE, "STA " MACSTR " sent probe request for %s " "SSID", MAC2STR(mgmt->sa), @@ -984,7 +984,8 @@ void sta_track_del(struct hostapd_sta_info *info) wpabuf_free(info->probe_ie_taxonomy); info->probe_ie_taxonomy = NULL; #endif /* CONFIG_TAXONOMY */ - os_free(info); + if(info) + os_free_loose(info); } @@ -1034,8 +1035,8 @@ int ieee802_11_build_ap_params(struct hostapd_data *hapd, tailpos = tail = os_malloc(tail_len); if (head == NULL || tail == NULL) { wpa_printf(MSG_ERROR, "Failed to set beacon data"); - os_free(head); - os_free(tail); + os_free_loose(head); + os_free_loose(tail); return -1; } @@ -1279,11 +1280,11 @@ int ieee802_11_build_ap_params(struct hostapd_data *hapd, void ieee802_11_free_ap_params(struct wpa_driver_ap_params *params) { - os_free(params->tail); + os_free_loose(params->tail); params->tail = NULL; - os_free(params->head); + os_free_loose(params->head); params->head = NULL; - os_free(params->proberesp); + os_free_loose(params->proberesp); params->proberesp = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/drv_callbacks.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/drv_callbacks.c index 3ef0765824b95bf05c7e3776cf19008a6c2d694a..439acb1473a1fe67aa48e9f76e99fa2af4da54b8 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/drv_callbacks.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/drv_callbacks.c @@ -1061,7 +1061,7 @@ static int hostapd_mgmt_rx(struct hostapd_data *hapd, struct rx_mgmt *rx_mgmt) wpa_snprintf_hex(hex, hex_len, rx_mgmt->frame, rx_mgmt->frame_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "MGMT-RX %s", hex); - os_free(hex); + os_free_loose(hex); } return 1; } @@ -1378,7 +1378,7 @@ static void hostapd_event_wds_sta_interface_status(struct hostapd_data *hapd, struct sta_info *sta = ap_get_sta(hapd, addr); if (sta) { - os_free(sta->ifname_wds); + os_free_loose(sta->ifname_wds); if (istatus == INTERFACE_ADDED) sta->ifname_wds = os_strdup(ifname); else diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hostapd.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hostapd.c index 28ef7d14ecc4e741a3d49a7e6e30bcfb0e8653ca..7662c42bbced81b7141040c0a02a4cb6a7a2dc40 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hostapd.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hostapd.c @@ -227,7 +227,7 @@ int hostapd_reload_config(struct hostapd_iface *iface) } hostapd_remove_iface(interfaces, hapd->conf->iface); iface = hostapd_init(interfaces, fname); - os_free(fname); + os_free_loose(fname); hostapd_config_free(newconf); if (!iface) { wpa_printf(MSG_ERROR, @@ -335,7 +335,8 @@ static int hostapd_broadcast_wep_set(struct hostapd_data *hapd) static void hostapd_free_hapd_data(struct hostapd_data *hapd) { - os_free(hapd->probereq_cb); + if(hapd->probereq_cb) + os_free_loose(hapd->probereq_cb); hapd->probereq_cb = NULL; hapd->num_probereq_cb = 0; @@ -435,7 +436,7 @@ static void hostapd_free_hapd_data(struct hostapd_data *hapd) struct hostapd_sae_commit_queue, list))) { dl_list_del(&q->list); - os_free(q); + os_free_loose(q); } } eloop_cancel_timeout(auth_sae_process_commit, hapd, NULL); @@ -492,9 +493,11 @@ static void hostapd_cleanup_iface_partial(struct hostapd_iface *iface) hostapd_free_hw_features(iface->hw_features, iface->num_hw_features); iface->hw_features = NULL; iface->current_mode = NULL; - os_free(iface->current_rates); + if(iface->current_rates) + os_free_loose(iface->current_rates); iface->current_rates = NULL; - os_free(iface->basic_rates); + if(iface->basic_rates) + os_free_loose(iface->basic_rates); iface->basic_rates = NULL; ap_list_deinit(iface); sta_track_deinit(iface); @@ -519,10 +522,10 @@ static void hostapd_cleanup_iface(struct hostapd_iface *iface) hostapd_config_free(iface->conf); iface->conf = NULL; - os_free(iface->config_fname); - os_free(iface->bss); + os_free_loose(iface->config_fname); + os_free_loose(iface->bss); wpa_printf(MSG_DEBUG, "%s: free iface=%p", __func__, iface); - os_free(iface); + os_free_loose(iface); } @@ -1023,7 +1026,7 @@ static int hostapd_set_acl_list(struct hostapd_data *hapd, err = hostapd_drv_set_acl(hapd, acl_params); - os_free(acl_params); + os_free_loose(acl_params); return err; } @@ -1206,7 +1209,6 @@ static int setup_interface(struct hostapd_iface *iface) } } #endif - return setup_interface2(iface); } @@ -1706,14 +1708,12 @@ int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err) int hostapd_setup_interface(struct hostapd_iface *iface) { int ret; - ret = setup_interface(iface); if (ret) { - wpa_printf(MSG_ERROR, "%s: Unable to setup interface.", + os_kprintf("%s: Unable to setup interface.", iface->bss[0]->conf->iface); return -1; } - return 0; } @@ -1810,7 +1810,7 @@ void hostapd_interface_free(struct hostapd_iface *iface) break; wpa_printf(MSG_DEBUG, "%s: free hapd %p", __func__, iface->bss[j]); - os_free(iface->bss[j]); + os_free_loose(iface->bss[j]); } hostapd_cleanup_iface(iface); } @@ -1883,11 +1883,11 @@ fail: if (conf) hostapd_config_free(conf); if (hapd_iface) { - os_free(hapd_iface->config_fname); - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->config_fname); + os_free_loose(hapd_iface->bss); wpa_printf(MSG_DEBUG, "%s: free iface %p", __func__, hapd_iface); - os_free(hapd_iface); + os_free_loose(hapd_iface); } return NULL; } @@ -2281,10 +2281,10 @@ static int hostapd_data_alloc(struct hostapd_iface *hapd_iface, if (hapd == NULL) { while (i > 0) { i--; - os_free(hapd_iface->bss[i]); + os_free_loose(hapd_iface->bss[i]); hapd_iface->bss[i] = NULL; } - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->bss); hapd_iface->bss = NULL; return -1; } @@ -2372,7 +2372,7 @@ int hostapd_add_iface(struct hapd_interfaces *interfaces, char *buf) __func__, hapd, hapd->conf->iface); hostapd_config_free_bss(hapd->conf); hapd->conf = NULL; - os_free(hapd); + os_free_loose(hapd); return -1; } } @@ -2458,10 +2458,10 @@ fail: __func__, hapd_iface->bss[i], hapd->conf->iface); hostapd_cleanup(hapd); - os_free(hapd); + os_free_loose(hapd); hapd_iface->bss[i] = NULL; } - os_free(hapd_iface->bss); + os_free_loose(hapd_iface->bss); hapd_iface->bss = NULL; } if (new_iface) { @@ -2489,7 +2489,7 @@ static int hostapd_remove_bss(struct hostapd_iface *iface, unsigned int idx) __func__, hapd, hapd->conf->iface); hostapd_config_free_bss(hapd->conf); hapd->conf = NULL; - os_free(hapd); + os_free_loose(hapd); iface->num_bss--; @@ -2677,17 +2677,17 @@ int hostapd_csa_in_progress(struct hostapd_iface *iface) #ifdef NEED_AP_MLME static void free_beacon_data(struct beacon_data *beacon) { - os_free(beacon->head); + os_free_loose(beacon->head); beacon->head = NULL; - os_free(beacon->tail); + os_free_loose(beacon->tail); beacon->tail = NULL; - os_free(beacon->probe_resp); + os_free_loose(beacon->probe_resp); beacon->probe_resp = NULL; - os_free(beacon->beacon_ies); + os_free_loose(beacon->beacon_ies); beacon->beacon_ies = NULL; - os_free(beacon->proberesp_ies); + os_free_loose(beacon->proberesp_ies); beacon->proberesp_ies = NULL; - os_free(beacon->assocresp_ies); + os_free_loose(beacon->assocresp_ies); beacon->assocresp_ies = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hw_features.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hw_features.c index db1d969fb37d0cceb4e78de28d3f2784a378088b..e0f4f544dffe74eb918d6d755c0fc151e709472d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hw_features.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/hw_features.c @@ -37,11 +37,11 @@ void hostapd_free_hw_features(struct hostapd_hw_modes *hw_features, return; for (i = 0; i < num_hw_features; i++) { - os_free(hw_features[i].channels); - os_free(hw_features[i].rates); + os_free_loose(hw_features[i].channels); + os_free_loose(hw_features[i].rates); } - os_free(hw_features); + os_free_loose(hw_features); } @@ -195,13 +195,13 @@ int hostapd_prepare_rates(struct hostapd_iface *iface, i++; if (i) i++; /* -1 termination */ - os_free(iface->basic_rates); + os_free_loose(iface->basic_rates); iface->basic_rates = os_malloc(i * sizeof(int)); if (iface->basic_rates) os_memcpy(iface->basic_rates, basic_rates, i * sizeof(int)); if (iface->current_rates) - os_free(iface->current_rates); + os_free_loose(iface->current_rates); iface->num_rates = 0; iface->current_rates = @@ -464,7 +464,7 @@ static void ap_ht40_scan_retry(void *eloop_data, void *user_data) ret = hostapd_driver_scan(iface->bss[0], ¶ms); iface->num_ht40_scan_tries++; - os_free(params.freqs); + os_free_loose(params.freqs); if (ret == -ERRBUSY && iface->num_ht40_scan_tries < HT2040_COEX_SCAN_RETRY) { @@ -515,7 +515,7 @@ static int ieee80211n_check_40mhz(struct hostapd_iface *iface) #endif ret = hostapd_driver_scan(iface->bss[0], ¶ms); - os_free(params.freqs); + os_free_loose(params.freqs); if (ret == -ERRBUSY) { wpa_printf(MSG_ERROR, diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11.c index 4bd98b9ebf934993939d051a2d59208fa4ed301f..b1ce1a7c299b7e40c48dc1650d9dcc87f4f79d9c 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11.c @@ -264,7 +264,7 @@ static u16 auth_shared_key(struct hostapd_data *hapd, struct sta_info *sta, return WLAN_STATUS_UNSPECIFIED_FAILURE; if (os_get_random(key, sizeof(key)) < 0) { - os_free(sta->challenge); + os_free_loose(sta->challenge); sta->challenge = NULL; return WLAN_STATUS_UNSPECIFIED_FAILURE; } @@ -294,7 +294,7 @@ static u16 auth_shared_key(struct hostapd_data *hapd, struct sta_info *sta, "authentication OK (shared key)"); sta->flags |= WLAN_STA_AUTH; wpa_auth_sm_event(sta->wpa_sm, WPA_AUTH); - os_free(sta->challenge); + os_free_loose(sta->challenge); sta->challenge = NULL; return 0; @@ -340,7 +340,7 @@ static int send_auth_reply(struct hostapd_data *hapd, else reply_res = WLAN_STATUS_SUCCESS; - os_free(buf); + os_free_loose(buf); return reply_res; } @@ -1265,7 +1265,7 @@ void auth_sae_process_commit(void *eloop_ctx, void *user_ctx) dl_list_del(&q->list); handle_auth(hapd, (const struct ieee80211_mgmt *) q->msg, q->len, q->rssi, 1); - os_free(q); + os_free_loose(q); if (eloop_is_timeout_registered(auth_sae_process_commit, hapd, NULL)) return; @@ -1317,7 +1317,7 @@ static void auth_sae_queue(struct hostapd_data *hapd, "SAE: Replace queued message from same STA with same transaction number"); dl_list_add(&q2->list, &q->list); dl_list_del(&q2->list); - os_free(q2); + os_free_loose(q2); goto queued; } } @@ -1820,8 +1820,8 @@ static void handle_auth(struct hostapd_data *hapd, } fail: - os_free(identity); - os_free(radius_cui); + os_free_loose(identity); + os_free_loose(radius_cui); hostapd_free_psk_list(psk); reply_res = send_auth_reply(hapd, mgmt->sa, mgmt->bssid, auth_alg, @@ -2016,7 +2016,7 @@ static u16 check_ext_capab(struct hostapd_data *hapd, struct sta_info *sta, if (ext_capab_ie_len > 0) { sta->ecsa_supported = !!(ext_capab_ie[0] & BIT(2)); - os_free(sta->ext_capability); + os_free_loose(sta->ext_capability); sta->ext_capability = os_malloc(1 + ext_capab_ie_len); if (sta->ext_capability) { sta->ext_capability[0] = ext_capab_ie_len; @@ -2161,7 +2161,7 @@ static u16 owe_process_assoc_req(struct hostapd_data *hapd, /* PMK = HKDF-expand(prk, "OWE Key Generation", n) */ - os_free(sta->owe_pmk); + os_free_loose(sta->owe_pmk); sta->owe_pmk = os_malloc(hash_len); if (!sta->owe_pmk) { os_memset(prk, 0, SHA512_MAC_LEN); @@ -2179,7 +2179,7 @@ static u16 owe_process_assoc_req(struct hostapd_data *hapd, os_strlen(info), sta->owe_pmk, hash_len); os_memset(prk, 0, SHA512_MAC_LEN); if (res < 0) { - os_free(sta->owe_pmk); + os_free_loose(sta->owe_pmk); sta->owe_pmk = NULL; return WLAN_STATUS_UNSPECIFIED_FAILURE; } @@ -2982,7 +2982,7 @@ static u16 send_assoc_resp(struct hostapd_data *hapd, struct sta_info *sta, } done: - os_free(buf); + os_free_loose(buf); return res; } @@ -3367,7 +3367,7 @@ static void handle_assoc(struct hostapd_data *hapd, reply_res = send_assoc_resp(hapd, sta, mgmt->sa, resp, reassoc, pos, left, rssi); - os_free(tmp); + os_free_loose(tmp); /* * Remove the station in case tranmission of a success response fails @@ -3711,7 +3711,7 @@ static int handle_action(struct hostapd_data *hapd, wpa_printf(MSG_ERROR, "IEEE 802.11: Failed to send " "Action frame"); } - os_free(resp); + os_free_loose(resp); } return 1; @@ -4051,7 +4051,7 @@ static void handle_assoc_cb(struct hostapd_data *hapd, wpabuf_len(sta->pending_eapol_rx->buf)); } wpabuf_free(sta->pending_eapol_rx->buf); - os_free(sta->pending_eapol_rx); + os_free_loose(sta->pending_eapol_rx); sta->pending_eapol_rx = NULL; } #endif @@ -4195,7 +4195,7 @@ void ieee802_11_mgmt_cb(struct hostapd_data *hapd, const u8 *buf, size_t len, wpa_msg(hapd->msg_ctx, MSG_INFO, "MGMT-TX-STATUS stype=%u ok=%d buf=%s", stype, ok, hex); - os_free(hex); + os_free_loose(hex); } return; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_auth.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_auth.c index 874c2184ac733e82b43fdce72cbf8e49a7897822..2de1d3d6e568f15f3e65cb153fddff1b97b17b94 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_auth.c @@ -53,10 +53,10 @@ struct hostapd_acl_query_data { #ifndef CONFIG_NO_RADIUS static void hostapd_acl_cache_free_entry(struct hostapd_cached_radius_acl *e) { - os_free(e->identity); - os_free(e->radius_cui); + os_free_loose(e->identity); + os_free_loose(e->radius_cui); hostapd_free_psk_list(e->psk); - os_free(e); + os_free_loose(e); } @@ -137,8 +137,8 @@ static void hostapd_acl_query_free(struct hostapd_acl_query_data *query) { if (query == NULL) return; - os_free(query->auth_msg); - os_free(query); + os_free_loose(query->auth_msg); + os_free_loose(query); } @@ -248,7 +248,7 @@ int hostapd_check_acl(struct hostapd_data *hapd, const u8 *addr, * Returns: HOSTAPD_ACL_ACCEPT, HOSTAPD_ACL_REJECT, or HOSTAPD_ACL_PENDING * * The caller is responsible for freeing the returned *identity and *radius_cui - * values with os_free(). + * values with os_free_loose(). */ int hostapd_allowed_address(struct hostapd_data *hapd, const u8 *addr, const u8 *msg, size_t len, u32 *session_timeout, @@ -308,11 +308,11 @@ int hostapd_allowed_address(struct hostapd_data *hapd, const u8 *addr, /* pending query in RADIUS retransmit queue; * do not generate a new one */ if (identity) { - os_free(*identity); + os_free_loose(*identity); *identity = NULL; } if (radius_cui) { - os_free(*radius_cui); + os_free_loose(*radius_cui); *radius_cui = NULL; } return HOSTAPD_ACL_PENDING; @@ -493,9 +493,9 @@ static void decode_tunnel_passwords(struct hostapd_data *hapd, psk = NULL; } skip: - os_free(psk); + os_free_loose(psk); free_pass: - os_free(passphrase); + os_free_loose(passphrase); } } @@ -697,6 +697,6 @@ void hostapd_free_psk_list(struct hostapd_sta_wpa_psk_short *psk) while (psk) { struct hostapd_sta_wpa_psk_short *prev = psk; psk = psk->next; - os_free(prev); + os_free_loose(prev); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_he.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_he.c index a51f3fcb0eae4e0fcd7c765c22ae53e9b55b69ba..1c4b0f4fed7c84603b958da45635581de6c5abb4 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_he.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_he.c @@ -327,7 +327,7 @@ u16 copy_sta_he_capab(struct hostapd_data *hapd, struct sta_info *sta, !check_valid_he_mcs(hapd, he_capab, opmode) || he_capab_len > sizeof(struct ieee80211_he_capabilities)) { sta->flags &= ~WLAN_STA_HE; - os_free(sta->he_capab); + os_free_loose(sta->he_capab); sta->he_capab = NULL; return WLAN_STATUS_SUCCESS; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_ht.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_ht.c index 73903a2daed7c99f15eba8e1d81aaed458ec8e7e..54798ba4dac975c687998c1543cda0c32ae89e55 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_ht.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_ht.c @@ -389,7 +389,7 @@ u16 copy_sta_ht_capab(struct hostapd_data *hapd, struct sta_info *sta, if (!ht_capab || !(sta->flags & WLAN_STA_WMM) || !hapd->iconf->ieee80211n || hapd->conf->disable_11n) { sta->flags &= ~WLAN_STA_HT; - os_free(sta->ht_capabilities); + os_free_loose(sta->ht_capabilities); sta->ht_capabilities = NULL; return WLAN_STATUS_SUCCESS; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_shared.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_shared.c index 77cd018ee502b68f64073aa228852d87775bfdd8..83d94ce90abbfe7b1dd30b10a41a93d5e84bc146 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_shared.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_shared.c @@ -83,7 +83,7 @@ void ieee802_11_send_sa_query_req(struct hostapd_data *hapd, } if (ocv_insert_extended_oci(&ci, oci_ie) < 0) { - os_free(oci_ie); + os_free_loose(oci_ie); return; } } @@ -93,7 +93,7 @@ void ieee802_11_send_sa_query_req(struct hostapd_data *hapd, if (!mgmt) { wpa_printf(MSG_DEBUG, "Failed to allocate buffer for SA Query Response frame"); - os_free(oci_ie); + os_free_loose(oci_ie); return; } @@ -116,8 +116,8 @@ void ieee802_11_send_sa_query_req(struct hostapd_data *hapd, if (hostapd_drv_send_mlme(hapd, mgmt, end - (u8 *) mgmt, 0) < 0) wpa_printf(MSG_INFO, "ieee802_11_send_sa_query_req: send failed"); - os_free(mgmt); - os_free(oci_ie); + os_free_loose(mgmt); + os_free_loose(oci_ie); } @@ -161,7 +161,7 @@ static void ieee802_11_send_sa_query_resp(struct hostapd_data *hapd, } if (ocv_insert_extended_oci(&ci, oci_ie) < 0) { - os_free(oci_ie); + os_free_loose(oci_ie); return; } } @@ -171,7 +171,7 @@ static void ieee802_11_send_sa_query_resp(struct hostapd_data *hapd, if (!resp) { wpa_printf(MSG_DEBUG, "Failed to allocate buffer for SA Query Response frame"); - os_free(oci_ie); + os_free_loose(oci_ie); return; } @@ -197,8 +197,8 @@ static void ieee802_11_send_sa_query_resp(struct hostapd_data *hapd, if (hostapd_drv_send_mlme(hapd, resp, end - (u8 *) resp, 0) < 0) wpa_printf(MSG_INFO, "ieee80211_mgmt_sa_query_request: send failed"); - os_free(resp); - os_free(oci_ie); + os_free_loose(resp); + os_free_loose(oci_ie); } @@ -871,7 +871,7 @@ void ap_copy_sta_supp_op_classes(struct sta_info *sta, { if (!supp_op_classes) return; - os_free(sta->supp_op_classes); + os_free_loose(sta->supp_op_classes); sta->supp_op_classes = os_malloc(1 + supp_op_classes_len); if (!sta->supp_op_classes) return; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_vht.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_vht.c index 269345fbf85b68883112abab6d925efe844ff257..d4d97f3dd47a920883663e1da37876c7c320f480 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_vht.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/ieee802_11_vht.c @@ -337,7 +337,7 @@ u16 copy_sta_vht_capab(struct hostapd_data *hapd, struct sta_info *sta, !hapd->iconf->ieee80211ac || hapd->conf->disable_11ac || !check_valid_vht_mcs(hapd->iface->current_mode, vht_capab)) { sta->flags &= ~WLAN_STA_VHT; - os_free(sta->vht_capabilities); + os_free_loose(sta->vht_capabilities); sta->vht_capabilities = NULL; return WLAN_STATUS_SUCCESS; } @@ -361,7 +361,7 @@ u16 copy_sta_vht_oper(struct hostapd_data *hapd, struct sta_info *sta, const u8 *vht_oper) { if (!vht_oper) { - os_free(sta->vht_operation); + os_free_loose(sta->vht_operation); sta->vht_operation = NULL; return WLAN_STATUS_SUCCESS; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/pmksa_cache_auth.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/pmksa_cache_auth.c index 684ef48038bde961486fe306ef52df7748f6f093..dbb1087b74eabd75b19c6e25c383268aea90bd97 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/pmksa_cache_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/pmksa_cache_auth.c @@ -40,8 +40,8 @@ static void pmksa_cache_set_expiration(struct rsn_pmksa_cache *pmksa); static void _pmksa_cache_free_entry(struct rsn_pmksa_cache_entry *entry) { - os_free(entry->vlan_desc); - os_free(entry->identity); + os_free_loose(entry->vlan_desc); + os_free_loose(entry->identity); wpabuf_free(entry->cui); #ifndef CONFIG_NO_RADIUS radius_free_class(&entry->radius_class); @@ -187,7 +187,7 @@ void pmksa_cache_to_eapol_data(struct hostapd_data *hapd, return; if (entry->identity) { - os_free(eapol->identity); + os_free_loose(eapol->identity); eapol->identity = os_malloc(entry->identity_len); if (eapol->identity) { eapol->identity_len = entry->identity_len; @@ -464,7 +464,7 @@ void pmksa_cache_auth_deinit(struct rsn_pmksa_cache *pmksa) pmksa->pmksa = NULL; for (i = 0; i < PMKID_HASH_SIZE; i++) pmksa->pmkid[i] = NULL; - os_free(pmksa); + os_free_loose(pmksa); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/sta_info.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/sta_info.c index 96e71bea9fe1665339759f8a57ad6ae99cc58b72..83728a81eec48d3338c6dab9c9a381d961b6e9c6 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/sta_info.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/sta_info.c @@ -287,10 +287,10 @@ void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta) } #endif /* CONFIG_NO_VLAN */ - os_free(sta->challenge); + os_free_loose(sta->challenge); #ifdef CONFIG_IEEE80211W_AP - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); #endif /* CONFIG_IEEE80211W_AP */ @@ -301,21 +301,21 @@ void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta) wpabuf_free(sta->wps_ie); wpabuf_free(sta->p2p_ie); - os_free(sta->ht_capabilities); - os_free(sta->vht_capabilities); - os_free(sta->vht_operation); - os_free(sta->he_capab); + os_free_loose(sta->ht_capabilities); + os_free_loose(sta->vht_capabilities); + os_free_loose(sta->vht_operation); + os_free_loose(sta->he_capab); hostapd_free_psk_list(sta->psk); #ifdef CONFIG_SAE_AP sae_clear_data(sta->sae); - os_free(sta->sae); + os_free_loose(sta->sae); #endif /* CONFIG_SAE_AP */ #ifdef CONFIG_MBO mbo_ap_sta_free(sta); #endif - os_free(sta->supp_op_classes); + os_free_loose(sta->supp_op_classes); #ifdef CONFIG_OWE bin_clear_free(sta->owe_pmk, sta->owe_pmk_len); @@ -327,15 +327,15 @@ void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta) sta->dpp_pfs = NULL; #endif /* CONFIG_DPP2 */ - os_free(sta->ext_capability); + os_free_loose(sta->ext_capability); #ifdef CONFIG_WNM_AP eloop_cancel_timeout(ap_sta_reset_steer_flag_timer, hapd, sta); #endif /* CONFIG_WNM_AP */ - os_free(sta->ifname_wds); + os_free_loose(sta->ifname_wds); - os_free(sta); + os_free_loose(sta); } @@ -391,6 +391,7 @@ void ap_handle_timer(void *eloop_ctx, void *timeout_ctx) if ((sta->flags & WLAN_STA_ASSOC) && (sta->timeout_next == STA_NULLFUNC || sta->timeout_next == STA_DISASSOC)) { + int inactive_sec; /* * Add random value to timeout so that we don't end up bouncing @@ -399,6 +400,7 @@ void ap_handle_timer(void *eloop_ctx, void *timeout_ctx) */ int fuzz = 0; /*os_random() % 20;*/ inactive_sec = hostapd_drv_get_inact_sec(hapd, sta->addr); + inactive_sec = 1; //os_printf("inactive_sec:%d fuzz:%d\r\n", inactive_sec, fuzz); if (inactive_sec == -1) { os_printf("Check inactivity: Could not " @@ -434,7 +436,6 @@ void ap_handle_timer(void *eloop_ctx, void *timeout_ctx) "inactive too long: %d sec, max allowed: %d", MAC2STR(sta->addr), inactive_sec, hapd->conf->ap_max_inactivity); - if (hapd->conf->skip_inactivity_poll) sta->timeout_next = STA_DISASSOC; } @@ -470,7 +471,6 @@ skip_poll: sta->flags & WLAN_STA_WMM); } else if (sta->timeout_next != STA_REMOVE) { int deauth = sta->timeout_next == STA_DEAUTH; - if (!deauth && !(sta->flags & WLAN_STA_ASSOC)) { /* Cannot disassociate not-associated STA, so move * directly to deauthentication. */ @@ -653,7 +653,7 @@ struct sta_info * ap_sta_add(struct hostapd_data *hapd, const u8 *addr) #ifdef CONFIG_FULL_HOSTAPD sta->acct_interim_interval = hapd->conf->acct_interim_interval; if (accounting_sta_get_id(hapd, sta) < 0) { - os_free(sta); + os_free_loose(sta); return NULL; } #endif @@ -1036,7 +1036,7 @@ int ap_check_sa_query_timeout(struct hostapd_data *hapd, struct sta_info *sta) HOSTAPD_LEVEL_DEBUG, "association SA Query timed out"); sta->sa_query_timed_out = 1; - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); sta->sa_query_trans_id = NULL; sta->sa_query_count = 0; eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); @@ -1107,7 +1107,7 @@ void ap_sta_start_sa_query(struct hostapd_data *hapd, struct sta_info *sta) void ap_sta_stop_sa_query(struct hostapd_data *hapd, struct sta_info *sta) { eloop_cancel_timeout(ap_sa_query_timer, hapd, sta); - os_free(sta->sa_query_trans_id); + os_free_loose(sta->sa_query_trans_id); sta->sa_query_trans_id = NULL; sta->sa_query_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth.c index 256236e1c07d0c8570d19ace9211dd9accc5c63d..f7da1259ea27a71e48b7c27a6c3391a096dc76ce 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth.c @@ -140,6 +140,7 @@ static inline int wpa_auth_set_key(struct wpa_authenticator *wpa_auth, { if (wpa_auth->cb->set_key == NULL) return -1; + return wpa_auth->cb->set_key(wpa_auth->cb_ctx, vlan_id, alg, addr, idx, key, key_len); } @@ -225,7 +226,7 @@ void wpa_auth_vlogger(struct wpa_authenticator *wpa_auth, const u8 *addr, wpa_auth_logger(wpa_auth, addr, level, format); - os_free(format); + os_free_loose(format); } #endif @@ -408,7 +409,7 @@ static struct wpa_group * wpa_group_init(struct wpa_authenticator *wpa_auth, if (wpa_group_init_gmk_and_counter(wpa_auth, group) < 0) { wpa_printf(MSG_ERROR, "Failed to get random data for WPA " "initialization."); - os_free(group); + os_free_loose(group); return NULL; } @@ -451,14 +452,14 @@ struct wpa_authenticator * wpa_init(const u8 *addr, if (wpa_auth_gen_wpa_ie(wpa_auth)) { wpa_printf(MSG_ERROR, "Could not generate WPA IE."); - os_free(wpa_auth); + os_free_loose(wpa_auth); return NULL; } wpa_auth->group = wpa_group_init(wpa_auth, 0, 1); if (wpa_auth->group == NULL) { - os_free(wpa_auth->wpa_ie); - os_free(wpa_auth); + os_free_loose(wpa_auth->wpa_ie); + os_free_loose(wpa_auth); return NULL; } @@ -466,9 +467,9 @@ struct wpa_authenticator * wpa_init(const u8 *addr, wpa_auth); if (wpa_auth->pmksa == NULL) { wpa_printf(MSG_ERROR, "PMKSA cache initialization failed."); - os_free(wpa_auth->group); - os_free(wpa_auth->wpa_ie); - os_free(wpa_auth); + os_free_loose(wpa_auth->group); + os_free_loose(wpa_auth->wpa_ie); + os_free_loose(wpa_auth); return NULL; } @@ -476,10 +477,10 @@ struct wpa_authenticator * wpa_init(const u8 *addr, wpa_auth->ft_pmk_cache = wpa_ft_pmk_cache_init(); if (wpa_auth->ft_pmk_cache == NULL) { wpa_printf(MSG_ERROR, "FT PMK cache initialization failed."); - os_free(wpa_auth->group); - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->group); + os_free_loose(wpa_auth->wpa_ie); pmksa_cache_auth_deinit(wpa_auth->pmksa); - os_free(wpa_auth); + os_free_loose(wpa_auth); return NULL; } #endif /* CONFIG_IEEE80211R_AP */ @@ -550,16 +551,16 @@ void wpa_deinit(struct wpa_authenticator *wpa_auth) #endif /* CONFIG_P2P */ - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->wpa_ie); group = wpa_auth->group; while (group) { prev = group; group = group->next; - os_free(prev); + os_free_loose(prev); } - os_free(wpa_auth); + os_free_loose(wpa_auth); } @@ -700,11 +701,11 @@ static void wpa_free_sta_sm(struct wpa_state_machine *sm) sm->GUpdateStationKeys = FALSE; } #ifdef CONFIG_IEEE80211R_AP - os_free(sm->assoc_resp_ftie); + os_free_loose(sm->assoc_resp_ftie); wpabuf_free(sm->ft_pending_req_ies); #endif /* CONFIG_IEEE80211R_AP */ - os_free(sm->last_rx_eapol_key); - os_free(sm->wpa_ie); + os_free_loose(sm->last_rx_eapol_key); + os_free_loose(sm->wpa_ie); wpa_group_put(sm->wpa_auth, sm->group); #ifdef CONFIG_DPP2 wpabuf_clear_free(sm->dpp_z); @@ -1335,7 +1336,7 @@ continue_processing: wpa_replay_counter_mark_invalid(sm->key_replay, NULL); } - os_free(sm->last_rx_eapol_key); + os_free_loose(sm->last_rx_eapol_key); sm->last_rx_eapol_key = os_memdup(data, data_len); if (sm->last_rx_eapol_key == NULL) return; @@ -1540,7 +1541,7 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, } else if (encr && kde) { buf = os_zalloc(key_data_len); if (buf == NULL) { - os_free(hdr); + os_free_loose(hdr); return; } pos = buf; @@ -1560,8 +1561,8 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, (unsigned int) sm->PTK.kek_len); if (aes_wrap(sm->PTK.kek, sm->PTK.kek_len, (key_data_len - 8) / 8, buf, key_data)) { - os_free(hdr); - os_free(buf); + os_free_loose(hdr); + os_free_loose(buf); return; } WPA_PUT_BE16(key_mic + mic_len, key_data_len); @@ -1581,11 +1582,11 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, WPA_PUT_BE16(key_mic + mic_len, key_data_len); #endif /* CONFIG_NO_RC4 */ } else { - os_free(hdr); - os_free(buf); + os_free_loose(hdr); + os_free_loose(buf); return; } - os_free(buf); + os_free_loose(buf); } if (key_info & WPA_KEY_INFO_MIC) { @@ -1593,14 +1594,14 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, wpa_auth_logger(wpa_auth, sm->addr, LOGGER_DEBUG, "PTK not valid when sending EAPOL-Key " "frame"); - os_free(hdr); + os_free_loose(hdr); return; } if (wpa_eapol_key_mic(sm->PTK.kck, sm->PTK.kck_len, sm->wpa_key_mgmt, version, (u8 *) hdr, len, key_mic) < 0) { - os_free(hdr); + os_free_loose(hdr); return; } } @@ -1609,7 +1610,7 @@ void __wpa_send_eapol(struct wpa_authenticator *wpa_auth, 1); wpa_auth_send_eapol(wpa_auth, sm->addr, (u8 *) hdr, len, sm->pairwise_set); - os_free(hdr); + os_free_loose(hdr); } @@ -3222,7 +3223,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) if (res < 0) { wpa_printf(MSG_ERROR, "FT: Failed to insert " "PMKR1Name into RSN IE in EAPOL-Key data"); - os_free(kde); + os_free_loose(kde); return; } pos -= wpa_ie_len; @@ -3239,7 +3240,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) pos = ieee80211w_kde_add(sm, pos); #ifdef CONFIG_OCV if (ocv_oci_add(sm, &pos) < 0) { - os_free(kde); + os_free_loose(kde); return; } #endif @@ -3267,7 +3268,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) if (res < 0) { wpa_printf(MSG_ERROR, "FT: Failed to insert FTIE " "into EAPOL-Key Key Data"); - os_free(kde); + os_free_loose(kde); return; } pos += res; @@ -3305,7 +3306,7 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING) WPA_KEY_INFO_ACK | WPA_KEY_INFO_INSTALL | WPA_KEY_INFO_KEY_TYPE, _rsc, sm->ANonce, kde, pos - kde, keyidx, encr); - os_free(kde); + os_free_loose(kde); } @@ -3563,7 +3564,7 @@ SM_STATE(WPA_PTK_GROUP, REKEYNEGOTIATING) gtk, gsm->GTK_len); pos = ieee80211w_kde_add(sm, pos); if (ocv_oci_add(sm, &pos) < 0) { - os_free(kde_buf); + os_free_loose(kde_buf); return; } kde_len = pos - kde; @@ -3580,7 +3581,7 @@ SM_STATE(WPA_PTK_GROUP, REKEYNEGOTIATING) (!sm->Pair ? WPA_KEY_INFO_INSTALL : 0), rsc, NULL, kde, kde_len, gsm->GN, 1); - os_free(kde_buf); + os_free_loose(kde_buf); } @@ -4555,7 +4556,7 @@ static void wpa_group_free(struct wpa_authenticator *wpa_auth, if (prev->next == group) { /* This never frees the special first group as needed */ prev->next = group->next; - os_free(group); + os_free_loose(group); break; } prev = prev->next; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_glue.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_glue.c index d01a903522ef282697ba2cbafd0b291d4cb22d03..e9e20f44361b6d374594bff6e22cb94fd0d54713 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_glue.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_glue.c @@ -411,7 +411,7 @@ static int hostapd_wpa_auth_send_eapol(void *ctx, const u8 *addr, wpa_snprintf_hex(hex, hex_len, data, data_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(addr), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -496,7 +496,7 @@ static void hostapd_wpa_ft_rrb_rx_later(void *eloop_ctx, void *timeout_ctx) data->data_len); } dl_list_del(&data->list); - os_free(data); + os_free_loose(data); } } @@ -579,7 +579,7 @@ static int hostapd_wpa_auth_send_ether(void *ctx, const u8 *dst, u16 proto, wpa_snprintf_hex(hex, hex_len, data, data_len); wpa_msg(hapd->msg_ctx, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(dst), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -617,7 +617,7 @@ static int hostapd_wpa_auth_send_ether(void *ctx, const u8 *dst, u16 proto, os_memcpy(buf + 1, data, data_len); ret = l2_packet_send(hapd->l2, dst, proto, (u8 *) buf, sizeof(*buf) + data_len); - os_free(buf); + os_free_loose(buf); return ret; } @@ -649,7 +649,7 @@ static int hostapd_wpa_auth_send_ft_action(void *ctx, const u8 *dst, os_memcpy(&m->u, data, data_len); res = hostapd_drv_send_mlme(hapd, (u8 *) m, mlen, 0); - os_free(m); + os_free_loose(m); return res; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_ie.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_ie.c index fdf72a78380c0680bf7179fb0eb10aadacdd8596..20ed267fe53851b39804ec3a152cc5e661a403ec 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_ie.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/ap/wpa_auth_ie.c @@ -447,7 +447,7 @@ int wpa_auth_gen_wpa_ie(struct wpa_authenticator *wpa_auth) wpa_hexdump(MSG_DEBUG, "WPA: Forced own IE(s) for testing", wpa_auth->conf.own_ie_override, wpa_auth->conf.own_ie_override_len); - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->wpa_ie); wpa_auth->wpa_ie = os_malloc(wpa_auth->conf.own_ie_override_len); if (wpa_auth->wpa_ie == NULL) @@ -490,7 +490,7 @@ int wpa_auth_gen_wpa_ie(struct wpa_authenticator *wpa_auth) pos += res; } - os_free(wpa_auth->wpa_ie); + os_free_loose(wpa_auth->wpa_ie); wpa_auth->wpa_ie = os_malloc(pos - buf); if (wpa_auth->wpa_ie == NULL) return -1; @@ -955,7 +955,7 @@ int wpa_validate_wpa_ie(struct wpa_authenticator *wpa_auth, #endif /* CONFIG_DPP */ if (sm->wpa_ie == NULL || sm->wpa_ie_len < wpa_ie_len) { - os_free(sm->wpa_ie); + os_free_loose(sm->wpa_ie); sm->wpa_ie = os_malloc(wpa_ie_len); if (sm->wpa_ie == NULL) return WPA_ALLOC_FAIL; @@ -982,7 +982,7 @@ int wpa_validate_osen(struct wpa_authenticator *wpa_auth, sm->wpa = WPA_VERSION_WPA2; if (sm->wpa_ie == NULL || sm->wpa_ie_len < osen_ie_len) { - os_free(sm->wpa_ie); + os_free_loose(sm->wpa_ie); sm->wpa_ie = os_malloc(osen_ie_len); if (sm->wpa_ie == NULL) return -1; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/dpp.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/dpp.c index dcbc80b6b84b2964090bcdf76122d78da178cc94..9cd4baa40febbce0f3dc9544748acf7fea6a28a5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/dpp.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/dpp.c @@ -788,10 +788,10 @@ void dpp_bootstrap_info_free(struct dpp_bootstrap_info *info) { if (!info) return; - os_free(info->uri); - os_free(info->info); + os_free_loose(info->uri); + os_free_loose(info->info); EVP_PKEY_free(info->pubkey); - os_free(info); + os_free_loose(info); } @@ -992,7 +992,7 @@ static int dpp_parse_uri_pk(struct dpp_bootstrap_info *bi, const char *info) if (sha256_vector(1, (const u8 **) &data, &data_len, bi->pubkey_hash) < 0) { wpa_printf(MSG_DEBUG, "DPP: Failed to hash public key"); - os_free(data); + os_free_loose(data); return -1; } wpa_hexdump(MSG_DEBUG, "DPP: Public key hash", @@ -1016,7 +1016,7 @@ static int dpp_parse_uri_pk(struct dpp_bootstrap_info *bi, const char *info) p = data; pkey = d2i_PUBKEY(NULL, &p, data_len); - os_free(data); + os_free_loose(data); if (!pkey) { wpa_printf(MSG_DEBUG, @@ -1190,7 +1190,7 @@ static void dpp_debug_print_key(const char *title, EVP_PKEY *key) txt[res] = '\0'; wpa_printf(MSG_DEBUG, "%s: %s", title, txt); } - os_free(txt); + os_free_loose(txt); } BIO_free(out); @@ -1510,7 +1510,7 @@ char * dpp_keygen(struct dpp_bootstrap_info *bi, const char *curve, } return (char *) base64; fail: - os_free(base64); + os_free_loose(base64); wpabuf_free(der); return NULL; } @@ -2207,11 +2207,11 @@ static int dpp_autogen_bootstrap_key(struct dpp_authentication *auth) auth->tmp_own_bi = auth->own_bi = bi; - os_free(pk); + os_free_loose(pk); return 0; fail: - os_free(pk); + os_free_loose(pk); dpp_bootstrap_info_free(bi); return -1; } @@ -4294,7 +4294,7 @@ void dpp_configuration_free(struct dpp_configuration *conf) if (!conf) return; str_clear_free(conf->passphrase); - os_free(conf->group_id); + os_free_loose(conf->group_id); bin_clear_free(conf, sizeof(*conf)); } @@ -4466,14 +4466,14 @@ void dpp_auth_deinit(struct dpp_authentication *auth) wpabuf_free(auth->req_msg); wpabuf_free(auth->resp_msg); wpabuf_free(auth->conf_req); - os_free(auth->connector); + os_free_loose(auth->connector); wpabuf_free(auth->net_access_key); wpabuf_free(auth->c_sign_key); dpp_bootstrap_info_free(auth->tmp_own_bi); #ifdef CONFIG_TESTING_OPTIONS - os_free(auth->config_obj_override); - os_free(auth->discovery_override); - os_free(auth->groups_override); + os_free_loose(auth->config_obj_override); + os_free_loose(auth->discovery_override); + os_free_loose(auth->groups_override); #endif /* CONFIG_TESTING_OPTIONS */ bin_clear_free(auth, sizeof(*auth)); } @@ -4548,8 +4548,8 @@ static int dpp_build_jwk(struct wpabuf *buf, const char *name, EVP_PKEY *key, ret = 0; fail: wpabuf_free(pub); - os_free(x); - os_free(y); + os_free_loose(x); + os_free_loose(y); return ret; } @@ -4779,10 +4779,10 @@ skip_groups: out: EVP_MD_CTX_destroy(md_ctx); ECDSA_SIG_free(sig); - os_free(signed1); - os_free(signed2); - os_free(signed3); - os_free(signature); + os_free_loose(signed1); + os_free_loose(signed2); + os_free_loose(signed3); + os_free_loose(signature); wpabuf_free(dppcon); return buf; fail: @@ -5092,7 +5092,7 @@ dpp_conf_req_rx(struct dpp_authentication *auth, const u8 *attr_start, fail: json_free(root); - os_free(unwrapped); + os_free_loose(unwrapped); return resp; } @@ -5706,9 +5706,9 @@ dpp_process_signed_connector(struct dpp_signed_connector_info *info, fail: EC_KEY_free(eckey); EVP_MD_CTX_destroy(md_ctx); - os_free(prot_hdr); + os_free_loose(prot_hdr); wpabuf_free(kid); - os_free(signature); + os_free_loose(signature); ECDSA_SIG_free(sig); BN_free(r); BN_free(s); @@ -5776,7 +5776,7 @@ static int dpp_parse_cred_dpp(struct dpp_authentication *auth, goto fail; } - os_free(auth->connector); + os_free_loose(auth->connector); auth->connector = os_strdup(signed_connector); dpp_copy_csign(auth, csign_pub); @@ -5785,7 +5785,7 @@ static int dpp_parse_cred_dpp(struct dpp_authentication *auth, ret = 0; fail: EVP_PKEY_free(csign_pub); - os_free(info.payload); + os_free_loose(info.payload); return ret; } @@ -6004,7 +6004,7 @@ int dpp_conf_resp_rx(struct dpp_authentication *auth, ret = 0; fail: - os_free(unwrapped); + os_free_loose(unwrapped); return ret; } @@ -6154,8 +6154,8 @@ void dpp_configurator_free(struct dpp_configurator *conf) if (!conf) return; EVP_PKEY_free(conf->csign); - os_free(conf->kid); - os_free(conf); + os_free_loose(conf->kid); + os_free_loose(conf); } @@ -6204,7 +6204,7 @@ dpp_keygen_configurator(const char *curve, const u8 *privkey, if (!conf->curve) { wpa_printf(MSG_INFO, "DPP: Unsupported curve: %s", curve); - os_free(conf); + os_free_loose(conf); return NULL; } } @@ -6598,9 +6598,9 @@ fail: if (ret != DPP_STATUS_OK) os_memset(intro, 0, sizeof(*intro)); os_memset(Nx, 0, sizeof(Nx)); - os_free(own_conn); - os_free(signed_connector); - os_free(info.payload); + os_free_loose(own_conn); + os_free_loose(signed_connector); + os_free_loose(info.payload); EVP_PKEY_free(own_key); wpabuf_free(own_key_pub); EVP_PKEY_free(peer_key); @@ -7212,7 +7212,7 @@ static int dpp_pkex_derive_z(const u8 *mac_init, const u8 *mac_resp, z, hash_len); else res = -1; - os_free(info); + os_free_loose(info); os_memset(prk, 0, hash_len); if (res < 0) return -1; @@ -7705,7 +7705,7 @@ struct wpabuf * dpp_pkex_rx_exchange_resp(struct dpp_pkex *pkex, pkex->exchange_done = 1; - /* ECDH: J = a * Y’ */ + /* ECDH: J = a * Y?*/ Y_ec = EC_KEY_new(); if (!Y_ec || EC_KEY_set_group(Y_ec, group) != 1 || @@ -7721,7 +7721,7 @@ struct wpabuf * dpp_pkex_rx_exchange_resp(struct dpp_pkex *pkex, wpa_hexdump_key(MSG_DEBUG, "DPP: ECDH shared secret (J.x)", Jx, Jx_len); - /* u = HMAC(J.x, MAC-Initiator | A.x | Y’.x | X.x ) */ + /* u = HMAC(J.x, MAC-Initiator | A.x | Y?x | X.x ) */ A_pub = dpp_get_pubkey_point(pkex->own_bi->pubkey, 0); Y_pub = dpp_get_pubkey_point(pkex->y, 0); X_pub = dpp_get_pubkey_point(pkex->x, 0); @@ -7739,7 +7739,7 @@ struct wpabuf * dpp_pkex_rx_exchange_resp(struct dpp_pkex *pkex, goto fail; wpa_hexdump(MSG_DEBUG, "DPP: u", u, curve->hash_len); - /* K = x * Y’ */ + /* K = x * Y?*/ if (dpp_ecdh(pkex->x, pkex->y, Kx, &Kx_len) < 0) goto fail; @@ -8045,7 +8045,7 @@ struct wpabuf * dpp_pkex_rx_commit_reveal_req(struct dpp_pkex *pkex, goto fail; out: - os_free(unwrapped); + os_free_loose(unwrapped); wpabuf_free(A_pub); wpabuf_free(B_pub); wpabuf_free(X_pub); @@ -8184,7 +8184,7 @@ out: wpabuf_free(B_pub); wpabuf_free(X_pub); wpabuf_free(Y_pub); - os_free(unwrapped); + os_free_loose(unwrapped); return ret; fail: goto out; @@ -8196,14 +8196,14 @@ void dpp_pkex_free(struct dpp_pkex *pkex) if (!pkex) return; - os_free(pkex->identifier); - os_free(pkex->code); + os_free_loose(pkex->identifier); + os_free_loose(pkex->code); EVP_PKEY_free(pkex->x); EVP_PKEY_free(pkex->y); EVP_PKEY_free(pkex->peer_bootstrap_key); wpabuf_free(pkex->exchange_req); wpabuf_free(pkex->exchange_resp); - os_free(pkex); + os_free_loose(pkex); } @@ -8249,11 +8249,11 @@ char * dpp_corrupt_connector_signature(const char *connector) pos); out: - os_free(signature); - os_free(signed3); + os_free_loose(signature); + os_free_loose(signed3); return tmp; fail: - os_free(tmp); + os_free_loose(tmp); tmp = NULL; goto out; } @@ -8338,7 +8338,7 @@ void dpp_pfs_free(struct dpp_pfs *pfs) crypto_ecdh_deinit(pfs->ecdh); wpabuf_free(pfs->ie); wpabuf_clear_free(pfs->secret); - os_free(pfs); + os_free_loose(pfs); } #endif /* CONFIG_DPP2 */ @@ -8470,11 +8470,11 @@ int dpp_bootstrap_gen(struct dpp_global *dpp, const char *cmd) ret = bi->id; bi = NULL; fail: - os_free(curve); - os_free(pk); - os_free(chan); - os_free(mac); - os_free(info); + os_free_loose(curve); + os_free_loose(pk); + os_free_loose(chan); + os_free_loose(mac); + os_free_loose(info); str_clear_free(key); bin_clear_free(privkey, privkey_len); dpp_bootstrap_info_free(bi); @@ -8657,7 +8657,7 @@ int dpp_configurator_add(struct dpp_global *dpp, const char *cmd) ret = conf->id; conf = NULL; fail: - os_free(curve); + os_free_loose(curve); str_clear_free(key); bin_clear_free(privkey, privkey_len); dpp_configurator_free(conf); @@ -8731,7 +8731,7 @@ static void dpp_connection_free(struct dpp_connection *conn) wpabuf_free(conn->msg); wpabuf_free(conn->msg_out); dpp_auth_deinit(conn->auth); - os_free(conn); + os_free_loose(conn); } @@ -8759,7 +8759,7 @@ static void dpp_relay_controller_free(struct dpp_relay_controller *ctrl) dl_list_for_each_safe(conn, tmp, &ctrl->conn, struct dpp_connection, list) dpp_connection_remove(conn); - os_free(ctrl); + os_free_loose(ctrl); } @@ -8822,7 +8822,7 @@ void dpp_global_clear(struct dpp_global *dpp) void dpp_global_deinit(struct dpp_global *dpp) { dpp_global_clear(dpp); - os_free(dpp); + os_free_loose(dpp); } @@ -9287,8 +9287,8 @@ static void dpp_controller_free(struct dpp_controller *ctrl) close(ctrl->sock); eloop_unregister_sock(ctrl->sock, EVENT_TYPE_READ); } - os_free(ctrl->configurator_params); - os_free(ctrl); + os_free_loose(ctrl->configurator_params); + os_free_loose(ctrl); } @@ -9901,7 +9901,7 @@ static void dpp_controller_tcp_cb(int sd, void *eloop_ctx, void *sock_ctx) fail: close(fd); - os_free(conn); + os_free_loose(conn); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/notifier.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/notifier.c index f3da2eeb454d7b2716149593b83e3d092b4c4373..b436f6223ade8d610f94e8920d710b8bf83f6a76 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/notifier.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/notifier.c @@ -40,7 +40,7 @@ void remove_notifier(struct notifier **notif, notify_func func, void *arg) for (; (np = *notif) != 0; notif = &np->next) { if (np->func == func && np->arg == arg) { *notif = np->next; - os_free(np); + os_free_loose(np); break; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/sae.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/sae.c index fdb75907e1591a2684552632e5c3acc75a2fe7f8..b04dfb9ea9d77f7c0c355899145cad1328b3ae23 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/sae.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/sae.c @@ -135,7 +135,7 @@ void sae_clear_temp_data(struct sae_data *sae) crypto_ec_point_deinit(tmp->own_commit_element_ecc, 0); crypto_ec_point_deinit(tmp->peer_commit_element_ecc, 0); wpabuf_free(tmp->anti_clogging_token); - os_free(tmp->pw_id); + os_free_loose(tmp->pw_id); bin_clear_free(tmp, sizeof(*tmp)); sae->tmp = NULL; } @@ -194,7 +194,7 @@ static struct crypto_bignum * sae_get_rand(struct sae_data *sae) os_memset(val, 0, order_len); out: #ifdef CONFIG_SAE_SMALL_STACK - os_free(val); + os_free_loose(val); #endif return bn; } @@ -640,7 +640,7 @@ static int sae_derive_pwe_ecc(struct sae_data *sae, const u8 *addr1, fail: crypto_bignum_deinit(qr, 0); crypto_bignum_deinit(qnr, 0); - os_free(dummy_password); + os_free_loose(dummy_password); bin_clear_free(tmp_password, password_len); crypto_bignum_deinit(x, 1); os_memset(x_bin, 0, sizeof(x_bin)); @@ -1025,7 +1025,7 @@ int sae_process_commit(struct sae_data *sae) #endif sae_derive_keys(sae, k) < 0) { #ifdef CONFIG_SAE_SMALL_STACK - os_free(k); + os_free_loose(k); #endif return -1; } @@ -1035,7 +1035,7 @@ int sae_process_commit(struct sae_data *sae) #endif #ifdef CONFIG_SAE_SMALL_STACK - os_free(k); + os_free_loose(k); #endif return 0; } @@ -1369,7 +1369,7 @@ static int sae_parse_password_identifier(struct sae_data *sae, sae->tmp->pw_id); return WLAN_STATUS_UNKNOWN_PASSWORD_IDENTIFIER; } - os_free(sae->tmp->pw_id); + os_free_loose(sae->tmp->pw_id); sae->tmp->pw_id = NULL; return WLAN_STATUS_SUCCESS; /* No Password Identifier */ } @@ -1383,7 +1383,7 @@ static int sae_parse_password_identifier(struct sae_data *sae, return WLAN_STATUS_UNKNOWN_PASSWORD_IDENTIFIER; } - os_free(sae->tmp->pw_id); + os_free_loose(sae->tmp->pw_id); sae->tmp->pw_id = os_malloc(pos[1]); if (!sae->tmp->pw_id) return WLAN_STATUS_UNSPECIFIED_FAILURE; @@ -1471,8 +1471,8 @@ static void sae_cn_confirm(struct sae_data *sae, const u8 *sc, scalar_b1 = os_malloc(SAE_MAX_PRIME_LEN); scalar_b2 = os_malloc(SAE_MAX_PRIME_LEN); if (!scalar_b1 || !scalar_b2) { - os_free(scalar_b1); - os_free(scalar_b2); + os_free_loose(scalar_b1); + os_free_loose(scalar_b2); return; } #else @@ -1504,8 +1504,8 @@ static void sae_cn_confirm(struct sae_data *sae, const u8 *sc, hmac_sha256_vector(sae->tmp->kck, sizeof(sae->tmp->kck), 5, addr, len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(scalar_b1); - os_free(scalar_b2); + os_free_loose(scalar_b1); + os_free_loose(scalar_b2); #endif } @@ -1523,8 +1523,8 @@ static void sae_cn_confirm_ecc(struct sae_data *sae, const u8 *sc, element_b1 = os_malloc(2 * SAE_MAX_ECC_PRIME_LEN); element_b2 = os_malloc(2 * SAE_MAX_ECC_PRIME_LEN); if (!element_b1 || !element_b2) { - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); return; } #else @@ -1540,8 +1540,8 @@ static void sae_cn_confirm_ecc(struct sae_data *sae, const u8 *sc, sae_cn_confirm(sae, sc, scalar1, element_b1, 2 * sae->tmp->prime_len, scalar2, element_b2, 2 * sae->tmp->prime_len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); #endif } @@ -1559,8 +1559,8 @@ static void sae_cn_confirm_ffc(struct sae_data *sae, const u8 *sc, element_b1 = os_malloc(SAE_MAX_PRIME_LEN); element_b2 = os_malloc(SAE_MAX_PRIME_LEN); if (!element_b1 || !element_b2) { - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); return; } #else @@ -1576,8 +1576,8 @@ static void sae_cn_confirm_ffc(struct sae_data *sae, const u8 *sc, sae_cn_confirm(sae, sc, scalar1, element_b1, sae->tmp->prime_len, scalar2, element_b2, sae->tmp->prime_len, confirm); #ifdef CONFIG_SAE_SMALL_STACK - os_free(element_b1); - os_free(element_b2); + os_free_loose(element_b1); + os_free_loose(element_b2); #endif } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_common.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_common.c index 2d346fb284f98c3249aca211b80786bcc2788b0a..60b5a7b37c853b8c532fb5b6737afe3a9164ad0d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_common.c @@ -2491,7 +2491,7 @@ int wpa_parse_cipher(const char *value) else if (os_strcmp(start, "BIP-CMAC-256") == 0) val |= WPA_CIPHER_BIP_CMAC_256; else { - os_free(buf); + os_free_loose(buf); return -1; } @@ -2499,7 +2499,7 @@ int wpa_parse_cipher(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); return val; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_psk_cache.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_psk_cache.c index 0d8f305b9fdc3de22c12e81088a995fed7168773..9fc1f781be6ecb15ccd64d01741fe5b9e1865746 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_psk_cache.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/common/wpa_psk_cache.c @@ -33,8 +33,8 @@ static void wpa_psk_cache_expire(struct wpa_psk_cache *cache) while (dl_list_len(&cache->all) > WPA_PSK_ENTRIES) { item = dl_list_first(&cache->all, struct wpa_psk_cache_item, node); dl_list_del(&item->node); // delete first entry - os_free(item->passphrase); - os_free(item->ssid); + os_free_loose(item->passphrase); + os_free_loose(item->ssid); os_printf("vanish one\n"); } } @@ -128,9 +128,9 @@ static int ___wpa_psk_cache_add(struct wpa_psk_cache *cache, item->ssid_len = ssid_len; item->passphrase = os_strdup(passphrase); if (!item->ssid || !item->passphrase) { - os_free(item->ssid); - os_free(item->passphrase); - os_free(item); + os_free_loose(item->ssid); + os_free_loose(item->passphrase); + os_free_loose(item); goto out; } @@ -277,7 +277,7 @@ int wpa_psk_request(u8 *ssid, size_t ssid_len, char *passphrase, u8 *psk, size_t { struct wpa_psk_cache *cache = psk_cache; int complete = 0; - + rtos_get_semaphore(&cache->sema, BEKEN_WAIT_FOREVER); if (ssid_len == cache->item.ssid_len && @@ -290,8 +290,8 @@ int wpa_psk_request(u8 *ssid, size_t ssid_len, char *passphrase, u8 *psk, size_t } /* a new request */ - os_free(cache->item.ssid); - os_free(cache->item.passphrase); + os_free_loose(cache->item.ssid); + os_free_loose(cache->item.passphrase); if (os_strlen(passphrase) == 2 * PMK_LEN) { /* passphrase is hex string of psk, convert it to binary */ @@ -350,8 +350,8 @@ void wpa_psk_cal_thread(void *arg) rtos_set_semaphore(&cache->sema); if (!ssid || !passphrase) { - os_free(ssid); - os_free(passphrase); + os_free_loose(ssid); + os_free_loose(passphrase); break; } @@ -371,8 +371,8 @@ void wpa_psk_cal_thread(void *arg) rtos_set_semaphore(&cache->sema); - os_free(ssid); - os_free(passphrase); + os_free_loose(ssid); + os_free_loose(passphrase); if (done) break; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-dec.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-dec.c index e1420291c9e860f8894c68774835404ee45816a8..7bf0bfcff7ee2ddd1ce01dde9ef2a902865aee45 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-dec.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-dec.c @@ -66,7 +66,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) return NULL; res = rijndaelKeySetupDec(rk, key, len * 8); if (res < 0) { - os_free(rk); + os_free_loose(rk); return NULL; } rk[AES_PRIV_NR_POS] = res; @@ -160,6 +160,6 @@ int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { os_memset(ctx, 0, AES_PRIV_SIZE); - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-enc.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-enc.c index 8a22860457d77a2aae3211ee1c9ec3c13c41a16f..c84f3bc55704e06331b32ec4796858bbb4f0d589 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-enc.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/aes-internal-enc.c @@ -106,7 +106,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) return NULL; res = rijndaelKeySetupEnc(rk, key, len * 8); if (res < 0) { - os_free(rk); + os_free_loose(rk); return NULL; } rk[AES_PRIV_NR_POS] = res; @@ -125,6 +125,6 @@ int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { os_memset(ctx, 0, AES_PRIV_SIZE); - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_ali.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_ali.c index cc830ab69ec78314b5e573b8fff84e01cdc02334..4f139b1b5b0d6705a5caf8274f50c07d23426b1f 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_ali.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_ali.c @@ -29,7 +29,7 @@ int des_encrypt(const u8 *clear, const u8 *key, u8 *cypher) ali_des_init(DES_ECB, true, key, 64, NULL, context); ali_des_process(clear, cypher, 8, context); - os_free(context); + os_free_loose(context); return 0; } @@ -55,7 +55,7 @@ int md5_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac) } ali_hash_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -80,7 +80,7 @@ int sha1_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac) } ali_hash_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -104,7 +104,7 @@ int hmac_sha1_vector(const u8 *key, size_t key_len, size_t num_elem, } ali_hmac_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -137,7 +137,7 @@ int hmac_md5_vector(const u8 *key, size_t key_len, size_t num_elem, } ali_hmac_final(mac, context); - os_free(context); + os_free_loose(context); return 0; } @@ -166,7 +166,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) len, NULL, context); if (ret != 0) { - os_free(context); + os_free_loose(context); return NULL; } return context; @@ -181,7 +181,7 @@ int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } void * aes_decrypt_init(const u8 *key, size_t len) @@ -202,7 +202,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) len, NULL, context); if (ret != 0) { - os_free(context); + os_free_loose(context); return NULL; } return context; @@ -217,7 +217,7 @@ int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } #elif CFG_USE_MBEDTLS #include "mbedtls/platform.h" @@ -367,7 +367,7 @@ void *aes_encrypt_init(const u8 *key, size_t len) ret = mbedtls_aes_setkey_enc(aes, key, len * 8); if (ret != 0) { CRYPTO_DBG("%s:%d mbedtls_aes_setkey_enc failed\n", __FUNCTION__, __LINE__); - os_free(aes); + os_free_loose(aes); return NULL; } @@ -383,7 +383,7 @@ int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } void * aes_decrypt_init(const u8 *key, size_t len) @@ -401,7 +401,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) ret = mbedtls_aes_setkey_dec(aes, key, len * 8); if (ret != 0) { CRYPTO_DBG("%s:%d mbedtls_aes_setkey_dec failed\n", __FUNCTION__, __LINE__); - os_free(aes); + os_free_loose(aes); return NULL; } @@ -417,6 +417,6 @@ int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_wolfssl.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_wolfssl.c index e639fc607cdb23ca61b737809e3ac184f0bcdd8e..0ed0764d8b1c0c37c44da2a730c4d26116bb7dc5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_wolfssl.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/crypto_wolfssl.c @@ -317,7 +317,7 @@ void * aes_encrypt_init(const u8 *key, size_t len) return NULL; if (wc_AesSetKey(aes, key, len, NULL, AES_ENCRYPTION) < 0) { - os_free(aes); + os_free_loose(aes); return NULL; } @@ -334,7 +334,7 @@ int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt) void aes_encrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } @@ -350,7 +350,7 @@ void * aes_decrypt_init(const u8 *key, size_t len) return NULL; if (wc_AesSetKey(aes, key, len, NULL, AES_DECRYPTION) < 0) { - os_free(aes); + os_free_loose(aes); return NULL; } @@ -367,7 +367,7 @@ int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain) void aes_decrypt_deinit(void *ctx) { - os_free(ctx); + os_free_loose(ctx); } @@ -506,14 +506,14 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, case 32: break; default: - os_free(ctx); + os_free_loose(ctx); return NULL; } if (wc_AesSetKey(&ctx->enc.aes, key, key_len, iv, AES_ENCRYPTION) || wc_AesSetKey(&ctx->dec.aes, key, key_len, iv, AES_DECRYPTION)) { - os_free(ctx); + os_free_loose(ctx); return NULL; } break; @@ -523,7 +523,7 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, if (key_len != DES3_KEYLEN || wc_Des3_SetKey(&ctx->enc.des3, key, iv, DES_ENCRYPTION) || wc_Des3_SetKey(&ctx->dec.des3, key, iv, DES_DECRYPTION)) { - os_free(ctx); + os_free_loose(ctx); return NULL; } break; @@ -531,7 +531,7 @@ struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg, case CRYPTO_CIPHER_ALG_RC2: case CRYPTO_CIPHER_ALG_DES: default: - os_free(ctx); + os_free_loose(ctx); return NULL; } @@ -603,7 +603,7 @@ int crypto_cipher_decrypt(struct crypto_cipher *ctx, const u8 *crypt, void crypto_cipher_deinit(struct crypto_cipher *ctx) { - os_free(ctx); + os_free_loose(ctx); } #endif @@ -792,7 +792,7 @@ int crypto_dh_init(u8 generator, const u8 *prime, size_t prime_len, u8 *privkey, wc_InitDhKey(dh); if (wc_InitRng(&rng) != 0) { - os_free(dh); + os_free_loose(dh); return -1; } @@ -819,7 +819,7 @@ int crypto_dh_init(u8 generator, const u8 *prime, size_t prime_len, u8 *privkey, ret = 0; done: wc_FreeDhKey(dh); - os_free(dh); + os_free_loose(dh); wc_FreeRng(&rng); return ret; } @@ -851,7 +851,7 @@ int crypto_dh_derive_secret(u8 generator, const u8 *prime, size_t prime_len, ret = 0; done: wc_FreeDhKey(dh); - os_free(dh); + os_free_loose(dh); return ret; } @@ -921,7 +921,7 @@ struct crypto_hash * crypto_hash_init(enum crypto_hash_alg alg, const u8 *key, ret = hash; hash = NULL; done: - os_free(hash); + os_free_loose(hash); return ret; } @@ -1014,7 +1014,7 @@ struct crypto_bignum * crypto_bignum_init(void) a = os_malloc(sizeof(*a)); if (!a || mp_init(a) != MP_OKAY) { - os_free(a); + os_free_loose(a); a = NULL; } @@ -1034,7 +1034,7 @@ struct crypto_bignum * crypto_bignum_init_set(const u8 *buf, size_t len) return NULL; if (mp_read_unsigned_bin(a, buf, len) != MP_OKAY) { - os_free(a); + os_free_loose(a); a = NULL; } @@ -1050,7 +1050,7 @@ void crypto_bignum_deinit(struct crypto_bignum *n, int clear) if (clear) mp_forcezero((mp_int *) n); mp_clear((mp_int *) n); - os_free((mp_int *) n); + os_free_loose((mp_int *) n); } @@ -1348,7 +1348,7 @@ void crypto_ec_deinit(struct crypto_ec* e) mp_clear(&e->prime); mp_clear(&e->a); wc_ecc_free(&e->key); - os_free(e); + os_free_loose(e); } @@ -1627,7 +1627,7 @@ done: if (!calced) { if (y2) { mp_clear(y2); - os_free(y2); + os_free_loose(y2); } mp_clear(&t); } @@ -1702,7 +1702,7 @@ void crypto_ecdh_deinit(struct crypto_ecdh *ecdh) { if (ecdh) { crypto_ec_deinit(ecdh->ec); - os_free(ecdh); + os_free_loose(ecdh); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls.h b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls.h index c8b1a824ed54d830b11b022ae18cc8428c5d4560..6c12b3024a6d3914a1d4eebc6ada8a06b70692eb 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls.h +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls.h @@ -284,7 +284,7 @@ int tls_connection_established(void *tls_ctx, struct tls_connection *conn); * Returns: Allocated string buffer containing the peer certificate serial * number or %NULL on error. * - * The caller is responsible for freeing the returned buffer with os_free(). + * The caller is responsible for freeing the returned buffer with os_free_loose(). */ char * tls_connection_peer_serial_num(void *tls_ctx, struct tls_connection *conn); diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls_wolfssl.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls_wolfssl.c index d222d142767d2fcc9ac818b309ccfd06fc9beda4..bf03398dc78d20d2ec98e9f59e0c8c6337d20fd1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls_wolfssl.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/crypto/tls_wolfssl.c @@ -218,9 +218,9 @@ void * tls_init(const struct tls_config *conf) if (!ssl_ctx) { tls_ref_count--; if (context != tls_global) - os_free(context); + os_free_loose(context); if (tls_ref_count == 0) { - os_free(tls_global); + os_free_loose(tls_global); tls_global = NULL; } } @@ -260,14 +260,14 @@ void tls_deinit(void *ssl_ctx) struct tls_context *context = wolfSSL_CTX_get_ex_data(ssl_ctx, 0); if (context != tls_global) - os_free(context); + os_free_loose(context); wolfSSL_CTX_free((WOLFSSL_CTX *) ssl_ctx); tls_ref_count--; if (tls_ref_count == 0) { wolfSSL_Cleanup(); - os_free(tls_global); + os_free_loose(tls_global); tls_global = NULL; } } @@ -303,7 +303,7 @@ struct tls_connection * tls_connection_init(void *tls_ctx) return NULL; conn->ssl = wolfSSL_new(ssl_ctx); if (!conn->ssl) { - os_free(conn); + os_free_loose(conn); return NULL; } @@ -331,13 +331,13 @@ void tls_connection_deinit(void *tls_ctx, struct tls_connection *conn) /* parts */ wolfSSL_free(conn->ssl); - os_free(conn->subject_match); - os_free(conn->alt_subject_match); - os_free(conn->suffix_match); - os_free(conn->domain_match); + os_free_loose(conn->subject_match); + os_free_loose(conn->alt_subject_match); + os_free_loose(conn->suffix_match); + os_free_loose(conn->domain_match); /* self */ - os_free(conn); + os_free_loose(conn); } @@ -383,7 +383,7 @@ static int tls_connection_set_subject_match(struct tls_connection *conn, const char *suffix_match, const char *domain_match) { - os_free(conn->subject_match); + os_free_loose(conn->subject_match); conn->subject_match = NULL; if (subject_match) { conn->subject_match = os_strdup(subject_match); @@ -391,7 +391,7 @@ static int tls_connection_set_subject_match(struct tls_connection *conn, return -1; } - os_free(conn->alt_subject_match); + os_free_loose(conn->alt_subject_match); conn->alt_subject_match = NULL; if (alt_subject_match) { conn->alt_subject_match = os_strdup(alt_subject_match); @@ -399,7 +399,7 @@ static int tls_connection_set_subject_match(struct tls_connection *conn, return -1; } - os_free(conn->suffix_match); + os_free_loose(conn->suffix_match); conn->suffix_match = NULL; if (suffix_match) { conn->suffix_match = os_strdup(suffix_match); @@ -407,7 +407,7 @@ static int tls_connection_set_subject_match(struct tls_connection *conn, return -1; } - os_free(conn->domain_match); + os_free_loose(conn->domain_match); conn->domain_match = NULL; if (domain_match) { conn->domain_match = os_strdup(domain_match); @@ -564,7 +564,7 @@ static int tls_connection_private_key(void *tls_ctx, } wolfSSL_CTX_set_default_passwd_cb(ctx, NULL); - os_free(passwd); + os_free_loose(passwd); if (!ok) return -1; @@ -937,7 +937,7 @@ static void wolfssl_tls_cert_event(struct tls_connection *conn, context->event_cb(context->cb_ctx, TLS_PEER_CERTIFICATE, &ev); wpabuf_free(cert); for (alt = 0; alt < num_alt_subject; alt++) - os_free(alt_subject[alt]); + os_free_loose(alt_subject[alt]); } @@ -1413,7 +1413,7 @@ static int tls_global_private_key(void *ssl_ctx, const char *private_key, wpa_printf(MSG_DEBUG, "SSL: Loaded global private key"); - os_free(passwd); + os_free_loose(passwd); wolfSSL_CTX_set_default_passwd_cb(ctx, NULL); return ret; @@ -1490,7 +1490,7 @@ int ocsp_status_cb(void *unused, const char *url, int url_sz, void ocsp_resp_free_cb(void *ocsp_stapling_response, unsigned char *response) { - os_free(response); + os_free_loose(response); } #endif /* HAVE_OCSP */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver.h b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver.h index 6974c4ea935f2ebef024f8aca66f20188aec9e29..db3ef11e5f4ba42d56d7f79e55a29475d8125061 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver.h +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver.h @@ -438,7 +438,7 @@ struct wpa_driver_scan_params { * * The driver wrapper is allowed to take this allocated buffer into its * own use by setting the pointer to %NULL. In that case, the driver - * wrapper is responsible for freeing the buffer with os_free() once it + * wrapper is responsible for freeing the buffer with os_free_loose() once it * is not needed anymore. */ struct wpa_driver_scan_filter { @@ -4696,7 +4696,7 @@ enum wpa_event_type { * stored in struct survey_results. The results provide at most one * survey entry for each frequency and at minimum will provide one * survey entry for one frequency. The survey data can be os_malloc()'d - * and then os_free()'d, so the event callback must only copy data. + * and then os_free_loose()'d, so the event callback must only copy data. */ EVENT_SURVEY, diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_beken.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_beken.c index 1aa147a301cc8cd0150cdcacbd05f146117e960b..1a4b64a4a9e2dab8cceb45caadbc6169e951f6b0 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_beken.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_beken.c @@ -237,7 +237,7 @@ static void handle_read(int sock, void *eloop_ctx, void *sock_ctx) read_exit: if(buf) { - os_free(buf); + os_free_loose(buf); } return; @@ -273,7 +273,6 @@ static int hostap_init_sockets(struct hostap_driver_data *drv, u8 *own_addr) { return -1; } - return hostap_get_ifhwaddr(drv->sock, drv->iface, own_addr); } @@ -418,7 +417,7 @@ static int wpa_driver_hostap_set_key(const char *ifname, void *priv, break; default: os_printf("%s: unsupport alg %d\n", __func__, alg); - os_free(buf); + os_free_loose(buf); return -1; } param->u.crypt.flags = set_tx ? HOSTAP_CRYPT_FLAG_SET_TX_KEY : 0; @@ -432,8 +431,8 @@ static int wpa_driver_hostap_set_key(const char *ifname, void *priv, { ret = -1; } - os_free(buf); - + os_free_loose(buf); + return ret; } @@ -469,7 +468,7 @@ static int hostap_get_seqnum(const char *ifname, void *priv, const u8 *addr, { os_memcpy(seq, param->u.crypt.seq, 8); } - os_free(buf); + os_free_loose(buf); return ret; } @@ -753,7 +752,7 @@ static int hostapd_ioctl_set_generic_elem(struct hostap_driver_data *drv) param->u.generic_elem.data, elem_len); res = hostapd_ioctl(drv, param, blen); - os_free(param); + os_free_loose(param); return res; } @@ -764,7 +763,7 @@ static int hostap_set_generic_elem(void *priv, { struct hostap_driver_data *drv = priv; - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; drv->generic_ie_len = 0; if (elem) @@ -792,7 +791,7 @@ static int hostap_set_ap_wps_ie(void *priv, const struct wpabuf *beacon, * more information. */ - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; drv->wps_ie_len = 0; if (proberesp) @@ -895,7 +894,7 @@ static void hostapd_wireless_event_wireless(struct hostap_driver_data *drv, buf[iwe->u.data.length] = '\0'; hostapd_wireless_event_wireless_custom(drv, buf); - os_free(buf); + os_free_loose(buf); break; } @@ -960,7 +959,7 @@ static int hostap_get_we_version(struct hostap_driver_data *drv) if (ioctl_inet(drv->ioctl_sock, drv->vif_index, SIOCGIWRANGE, (unsigned long)&iwr) < 0) { - os_free(range); + os_free_loose(range); return -1; } else if (iwr.u.data.length >= minlen && @@ -969,7 +968,7 @@ static int hostap_get_we_version(struct hostap_driver_data *drv) drv->we_version = range->we_version_compiled; } - os_free(range); + os_free_loose(range); return 0; } @@ -988,9 +987,9 @@ static int hostap_wireless_event_init(struct hostap_driver_data *drv) drv->netlink = 0; if (drv->netlink == NULL) { - os_free(cfg); + os_free_loose(cfg); } - + return 0; } @@ -1003,7 +1002,7 @@ static void *hostap_init(struct hostapd_data *hapd, drv = os_zalloc(sizeof(struct hostap_driver_data)); if (drv == NULL) { - os_printf("Could not allocate memory for hostapd driver data\n"); + os_kprintf("Could not allocate memory for hostapd driver data\n"); return NULL; } @@ -1014,42 +1013,42 @@ static void *hostap_init(struct hostapd_data *hapd, os_memcpy(drv->own_addr, params->own_addr, ETH_ALEN); ret = wpa_driver_hostap_init_vif(drv, NL80211_IFTYPE_AP); + if(ret || (drv->vif_index == 0xff)) { - os_printf("Could not found vif indix: %d\n", drv->vif_index); - os_free(drv); + os_kprintf("Could not found vif indix: %d\n", drv->vif_index); + os_free_loose(drv); return NULL; } drv->ioctl_sock = fsocket_init(PF_INET, SOCK_DGRAM, drv->vif_index); - + if (hostap_ioctl_prism2param(drv, PRISM2_PARAM_HOSTAPD, 1)) { - wpa_printf(MSG_ERROR, - "Could not enable hostapd mode for interface %s", + os_kprintf("Could not enable hostapd mode for interface %s", drv->iface); fsocket_close(drv->ioctl_sock); - os_free(drv); + os_free_loose(drv); drv = NULL; return NULL; } - + ret = wpa_driver_hostap_start_apm(drv); + if(ret) { - os_printf("wpa_driver_hostap_start_apm failed\n"); + os_kprintf("wpa_driver_hostap_start_apm failed\n"); return NULL; } - + if (hostap_init_sockets(drv, params->own_addr) || hostap_wireless_event_init(drv)) { fsocket_close(drv->ioctl_sock); - os_free(drv); + os_free_loose(drv); drv = NULL; - return NULL; } - + return drv; } @@ -1082,13 +1081,13 @@ static void hostap_driver_deinit(void *priv) l2_packet_deinit(drv->sock_xmit); drv->sock_xmit = NULL; - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; - os_free(drv); + os_free_loose(drv); drv = NULL; } @@ -1144,7 +1143,7 @@ int hostap_channel_switch(void *priv, struct csa_settings *settings) if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } @@ -1157,11 +1156,11 @@ int hostap_channel_switch(void *priv, struct csa_settings *settings) param->u.reg_csa_event.arg = (void *)SIGCSA; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } - os_free(buf); + os_free_loose(buf); return 0; } @@ -1237,9 +1236,9 @@ static struct hostapd_hw_modes *hostap_get_hw_feature_data(void *priv, mode->channels = os_zalloc(clen); mode->rates = os_zalloc(rlen); if (mode->channels == NULL || mode->rates == NULL) { - os_free(mode->channels); - os_free(mode->rates); - os_free(mode); + os_free_loose(mode->channels); + os_free_loose(mode->rates); + os_free_loose(mode); return NULL; } @@ -1319,7 +1318,7 @@ int hostap_set_ap(void *priv, struct wpa_driver_ap_params *params) ret = hostapd_ioctl(drv, ¶m, sizeof(param)); - os_free(beacon); + os_free_loose(beacon); return ret; } @@ -1427,7 +1426,7 @@ static void *wpa_driver_init(void *ctx, const char *ifname) ret = wpa_driver_hostap_init_vif(drv, NL80211_IFTYPE_STATION); if(ret || (drv->vif_index == 0xff)) { os_printf("Could not found vif indix: %d\n", drv->vif_index); - os_free(drv); + os_free_loose(drv); return NULL; } @@ -1470,13 +1469,13 @@ static void wpa_driver_deinit(void *priv) fsocket_close(drv->sock); } - os_free(drv->generic_ie); + os_free_loose(drv->generic_ie); drv->generic_ie = NULL; - os_free(drv->wps_ie); + os_free_loose(drv->wps_ie); drv->wps_ie = NULL; - os_free(drv); + os_free_loose(drv); drv = NULL; } @@ -1552,7 +1551,7 @@ int wpa_driver_scan2(void *priv, struct wpa_driver_scan_params *params) ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } @@ -1597,26 +1596,26 @@ struct wpa_scan_results *wpa_driver_get_scan_results2(void *priv) if(!ret) { - os_free(buf); + os_free_loose(buf); return results; } fail_result: if(results && results->res) { - os_free(results->res); + os_free_loose(results->res); results->res = NULL; } if(results) { - os_free(results); + os_free_loose(results); results = NULL; } if(buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -1701,7 +1700,7 @@ int wpa_driver_associate(void *priv, struct wpa_driver_associate_params *params) if (hostapd_ioctl(drv, param, blen)) ret = -1; - os_free(buf); + os_free_loose(buf); return ret; } @@ -1726,11 +1725,11 @@ int wpa_driver_get_bssid(void *priv, u8 *bssid) param->vif_idx = drv->vif_index; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } os_memcpy(bssid, param->u.bss_info.bssid, ETH_ALEN); - os_free(buf); + os_free_loose(buf); return 0; } @@ -1754,13 +1753,13 @@ int wpa_driver_get_ssid(void *priv, u8 *ssid) param->vif_idx = drv->vif_index; if (hostapd_ioctl(drv, param, blen)) { - os_free(buf); + os_free_loose(buf); return -1; } len = MIN(SSID_MAX_LEN, os_strlen((char *)param->u.bss_info.ssid)); os_memcpy(ssid, param->u.bss_info.ssid, len); - os_free(buf); + os_free_loose(buf); return len; } @@ -1813,7 +1812,7 @@ int wpa_driver_set_operstate(void *priv, int state) if(hostapd_ioctl(drv, param, blen)) { ret = -1; } - os_free(buf); + os_free_loose(buf); #endif return ret; @@ -1884,7 +1883,7 @@ int wpa_driver_authenticate(void *priv, struct wpa_driver_auth_params *params) if (hostapd_ioctl(drv, param, blen)) ret = -1; - os_free(buf); + os_free_loose(buf); return ret; } @@ -1959,7 +1958,7 @@ int wpa_driver_send_action(void *priv, unsigned int freq, unsigned int wait, res = fsocket_send(drv->sock, buf, total_len, type_ptr); - os_free(buf); + os_free_loose(buf); return res; } @@ -1988,7 +1987,7 @@ int wpa_driver_deauthenticate(void *priv, const u8 *addr, u16 reason_code) ret = -1; } - os_free(buf); + os_free_loose(buf); return ret; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_common.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_common.c index f2fd0b3a095dc37ccaa3e34f104bd0b88cb26bc4..945efdb3c63d20994fbd827dc8f398f3f0c03cd5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/drivers/driver_common.c @@ -19,14 +19,14 @@ void wpa_scan_results_free(struct wpa_scan_results *res) for (i = 0; i < res->num; i++) { - os_free(res->res[i]); + os_free_loose(res->res[i]); res->res[i] = 0; } - os_free(res->res); + os_free_loose(res->res); res->res = 0; - os_free(res); + os_free_loose(res); res = 0; } @@ -238,7 +238,7 @@ wpa_get_wowlan_triggers(const char *wowlan_triggers, wpa_printf(MSG_DEBUG, "Unknown/unsupported wowlan trigger '%s'", start); - os_free(triggers); + os_free_loose(triggers); triggers = NULL; goto out; } @@ -250,7 +250,7 @@ wpa_get_wowlan_triggers(const char *wowlan_triggers, #undef CHECK_TRIGGER out: - os_free(buf); + os_free_loose(buf); return triggers; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/l2_packet/l2_packet_none.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/l2_packet/l2_packet_none.c index d6dd46385ea52ab9cd478761a39f8345ee0b6ef3..8199830b3ed21ba7ec57b97b44742571192b5a6a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/l2_packet/l2_packet_none.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/l2_packet/l2_packet_none.c @@ -17,6 +17,7 @@ #include "mac.h" #include "rw_msdu.h" #include "uart_pub.h" +#include "error.h" struct l2_packet_data { char ifname[17]; @@ -54,7 +55,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, if(!type_ptr) { ret = -1; if(type_ptr){ - os_free(type_ptr); + os_free_loose(type_ptr); } goto send_exit; } @@ -85,6 +86,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, fsocket_send(l2->fd, data_buf, data_len, type_ptr); if (sync) { + os_printf("%s %d\r\n", __FUNCTION__, __LINE__); ret = rtos_get_semaphore(&cb.sema, 5*1000 /*BEKEN_NEVER_TIMEOUT*/); if (ret != kNoErr) { os_printf("%s: send failed\r\n", __func__); @@ -96,7 +98,7 @@ int __l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, send_exit: if(data_buf){ - os_free(data_buf); + os_free_loose(data_buf); } return ret; @@ -140,7 +142,7 @@ static void l2_packet_receive(int sock, void *eloop_ctx, void *sock_ctx) recv_exit: if(buf) - os_free(buf); + os_free_loose(buf); return; } @@ -204,7 +206,7 @@ void l2_packet_deinit(struct l2_packet_data *l2) fsocket_close(l2->fd); } - os_free(l2); + os_free_loose(l2); l2 = NULL; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/pmksa_cache.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/pmksa_cache.c index e47e507e6905a53fc22885434d7f965b80c38ab2..206a9ec9606574db38384fa01010418d6cfe0558 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/pmksa_cache.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/pmksa_cache.c @@ -190,7 +190,7 @@ pmksa_cache_add_entry(struct rsn_pmksa_cache *pmksa, PMKID_LEN) == 0) { wpa_printf(MSG_DEBUG, "WPA: reusing previous " "PMKSA entry"); - os_free(entry); + os_free_loose(entry); return pos; } if (prev == NULL) @@ -329,10 +329,10 @@ void pmksa_cache_deinit(struct rsn_pmksa_cache *pmksa) while (entry) { prev = entry; entry = entry->next; - os_free(prev); + os_free_loose(prev); } pmksa_cache_set_expiration(pmksa); - os_free(pmksa); + os_free_loose(pmksa); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa.c index 1e6c5190c51fa3bd5255fe6e5b34eb427d8ccdc3..92962ad80c673fb0efdab063b976fc9bf25ade67 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa.c @@ -144,14 +144,14 @@ int wpa_eapol_key_send(struct wpa_sm *sm, struct wpa_ptk *ptk, if (aes_siv_encrypt(ptk->kek, ptk->kek_len, s_key_data, key_data_len, 1, aad, aad_len, key_data) < 0) { - os_free(buf); + os_free_loose(buf); goto out; } wpa_hexdump(MSG_DEBUG, "WPA: Encrypted Key Data from SIV", key_data, AES_BLOCK_SIZE + key_data_len); - os_free(msg); + os_free_loose(msg); msg = buf; msg_len = buf_len; #else /* CONFIG_FILS */ @@ -163,7 +163,7 @@ int wpa_eapol_key_send(struct wpa_sm *sm, struct wpa_ptk *ptk, ret = wpa_sm_ether_send(sm, dest, proto, msg, msg_len); eapol_sm_notify_tx_eapol_key(sm->eapol); out: - os_free(msg); + os_free_loose(msg); return ret; } @@ -448,7 +448,7 @@ static int wpa_supplicant_get_pmk(struct wpa_sm *sm, if (buf) { wpa_sm_ether_send(sm, sm->bssid, ETH_P_EAPOL, buf, buflen); - os_free(buf); + os_free_loose(buf); return -2; } @@ -506,7 +506,7 @@ int wpa_supplicant_send_2_of_4(struct wpa_sm *sm, const unsigned char *dst, res = wpa_insert_pmkid(rsn_ie_buf, &wpa_ie_len, sm->pmk_r1_name); if (res < 0) { - os_free(rsn_ie_buf); + os_free_loose(rsn_ie_buf); return -1; } @@ -528,7 +528,7 @@ int wpa_supplicant_send_2_of_4(struct wpa_sm *sm, const unsigned char *dst, NULL, hdrlen + wpa_ie_len, &rlen, (void *) &reply); if (rbuf == NULL) { - os_free(rsn_ie_buf); + os_free_loose(rsn_ie_buf); return -1; } @@ -553,7 +553,7 @@ int wpa_supplicant_send_2_of_4(struct wpa_sm *sm, const unsigned char *dst, key_mic = (u8 *) (reply + 1); WPA_PUT_BE16(key_mic + mic_len, wpa_ie_len); /* Key Data Length */ os_memcpy(key_mic + mic_len + 2, wpa_ie, wpa_ie_len); /* Key Data */ - os_free(rsn_ie_buf); + os_free_loose(rsn_ie_buf); os_memcpy(reply->key_nonce, nonce, WPA_NONCE_LEN); @@ -713,12 +713,12 @@ static void wpa_supplicant_process_1_of_4(struct wpa_sm *sm, kde, kde_len, ptk) < 0) goto failed; - os_free(kde_buf); + os_free_loose(kde_buf); os_memcpy(sm->anonce, key->key_nonce, WPA_NONCE_LEN); return; failed: - os_free(kde_buf); + os_free_loose(kde_buf); wpa_sm_deauthenticate(sm, WLAN_REASON_UNSPECIFIED); } @@ -1816,13 +1816,13 @@ static int wpa_supplicant_send_2_of_2(struct wpa_sm *sm, if (wpa_sm_channel_info(sm, &ci) != 0) { wpa_printf(MSG_WARNING, "Failed to get channel info for OCI element in EAPOL-Key 2/2"); - os_free(rbuf); + os_free_loose(rbuf); return -1; } pos = key_mic + mic_len + 2; /* Key Data */ if (ocv_insert_oci_kde(&ci, &pos) < 0) { - os_free(rbuf); + os_free_loose(rbuf); return -1; } } @@ -2670,7 +2670,7 @@ struct wpa_sm * wpa_sm_init(struct wpa_sm_ctx *ctx) if (sm->pmksa == NULL) { wpa_msg(sm->ctx->msg_ctx, MSG_ERROR, "RSN: PMKSA cache initialization failed"); - os_free(sm); + os_free_loose(sm); return NULL; } @@ -2689,13 +2689,13 @@ void wpa_sm_deinit(struct wpa_sm *sm) pmksa_cache_deinit(sm->pmksa); eloop_cancel_timeout(wpa_sm_start_preauth, sm, NULL); eloop_cancel_timeout(wpa_sm_rekey_ptk, sm, NULL); - os_free(sm->assoc_wpa_ie); - os_free(sm->ap_wpa_ie); - os_free(sm->ap_rsn_ie); + os_free_loose(sm->assoc_wpa_ie); + os_free_loose(sm->ap_wpa_ie); + os_free_loose(sm->ap_rsn_ie); wpa_sm_drop_sa(sm); - os_free(sm->ctx); + os_free_loose(sm->ctx); #ifdef CONFIG_IEEE80211R - os_free(sm->assoc_resp_ies); + os_free_loose(sm->assoc_resp_ies); #endif /* CONFIG_IEEE80211R */ #ifdef CONFIG_TESTING_OPTIONS wpabuf_free(sm->test_assoc_ie); @@ -2712,7 +2712,7 @@ void wpa_sm_deinit(struct wpa_sm *sm) #ifdef CONFIG_DPP2 wpabuf_clear_free(sm->dpp_z); #endif /* CONFIG_DPP2 */ - os_free(sm); + os_free_loose(sm); } @@ -3228,7 +3228,7 @@ int wpa_sm_set_assoc_wpa_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->assoc_wpa_ie); + os_free_loose(sm->assoc_wpa_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing own WPA/RSN IE"); @@ -3262,7 +3262,7 @@ int wpa_sm_set_ap_wpa_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->ap_wpa_ie); + os_free_loose(sm->ap_wpa_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing AP WPA IE"); @@ -3296,7 +3296,7 @@ int wpa_sm_set_ap_rsn_ie(struct wpa_sm *sm, const u8 *ie, size_t len) if (sm == NULL) return -1; - os_free(sm->ap_rsn_ie); + os_free_loose(sm->ap_rsn_ie); if (ie == NULL || len == 0) { wpa_dbg(sm->ctx->msg_ctx, MSG_DEBUG, "WPA: clearing AP RSN IE"); diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa_i.h b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa_i.h index d86734b0df55925d47acba040be952a63e949368..1d1e52ca90a907617c3925f4543a388017cd7da1 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa_i.h +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/rsn_supp/wpa_i.h @@ -200,6 +200,9 @@ static inline int wpa_sm_set_key(struct wpa_sm *sm, enum wpa_alg alg, const u8 *key, size_t key_len) { WPA_ASSERT(sm->ctx->set_key); + + os_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + return sm->ctx->set_key(sm->ctx->ctx, alg, addr, key_idx, set_tx, seq, seq_len, key, key_len); } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/common.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/common.c index 27bf435d96910f56cedf505d88b5aa3f8fb7ba63..dae50a09a6cded2c55f3964e56fd7d054a873bfe 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/common.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/common.c @@ -667,12 +667,12 @@ char * wpa_config_parse_string(const char *value, size_t *len) str = os_malloc(tlen + 1); if (str == NULL) { - os_free(tstr); + os_free_loose(tstr); return NULL; } *len = printf_decode((u8 *) str, tlen + 1, tstr); - os_free(tstr); + os_free_loose(tstr); return str; } else { @@ -685,7 +685,7 @@ char * wpa_config_parse_string(const char *value, size_t *len) if (str == NULL) return NULL; if (hexstr2bin(value, str, tlen)) { - os_free(str); + os_free_loose(str); return NULL; } str[tlen] = '\0'; @@ -793,7 +793,7 @@ int freq_range_list_parse(struct wpa_freq_range_list *res, const char *value) n = os_realloc_array(freq, count + 1, sizeof(struct wpa_freq_range)); if (n == NULL) { - os_free(freq); + os_free_loose(freq); return -1; } freq = n; @@ -811,7 +811,7 @@ int freq_range_list_parse(struct wpa_freq_range_list *res, const char *value) count++; } - os_free(res->range); + os_free_loose(res->range); res->range = freq; res->num = count; @@ -864,7 +864,7 @@ char * freq_range_list_str(const struct wpa_freq_range_list *list) i == 0 ? "" : ",", range->min, range->max); if (os_snprintf_error(end - pos, res)) { - os_free(buf); + os_free_loose(buf); return NULL; } pos += res; @@ -893,7 +893,7 @@ void int_array_concat(int **res, const int *a) n = os_realloc_array(*res, reslen + alen + 1, sizeof(int)); if (n == NULL) { - os_free(*res); + os_free_loose(*res); *res = NULL; return; } @@ -954,7 +954,7 @@ void int_array_add_unique(int **res, int a) n = os_realloc_array(*res, reslen + 2, sizeof(int)); if (n == NULL) { - os_free(*res); + os_free_loose(*res); *res = NULL; return; } @@ -971,7 +971,7 @@ void str_clear_free(char *str) if (str) { size_t len = os_strlen(str); forced_memzero(str, len); - os_free(str); + os_free_loose(str); } } @@ -980,7 +980,7 @@ void bin_clear_free(void *bin, size_t len) { if (bin) { forced_memzero(bin, len); - os_free(bin); + os_free_loose(bin); } } @@ -1189,7 +1189,7 @@ int ssid_parse(const char *buf, struct wpa_ssid_value *ssid) } else { end = os_strchr(tmp + 1, '"'); if (!end) { - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -1202,8 +1202,8 @@ int ssid_parse(const char *buf, struct wpa_ssid_value *ssid) os_memcpy(ssid->ssid, res, len); } - os_free(tmp); - os_free(res); + os_free_loose(tmp); + os_free_loose(res); return ssid->ssid_len ? 0 : -1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/eloop.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/eloop.c index f402534648d995d008785edb36b675cbc3170d00..af27492a9056830dbcd7eff1f5c3bf592007e8bf 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/eloop.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/eloop.c @@ -130,7 +130,7 @@ static void eloop_sock_table_destroy(struct eloop_sock_table *table) wpa_trace_dump("eloop sock", &table->table[i]); } - os_free(table->table); + os_free_loose(table->table); } } @@ -206,7 +206,7 @@ int eloop_register_timeout(unsigned int secs, if (os_get_reltime(&timeout->time) < 0) { - os_free(timeout); + os_free_loose(timeout); os_printf("------------os_get_reltimeErr\r\n"); return -1; } @@ -219,7 +219,7 @@ int eloop_register_timeout(unsigned int secs, * to be infinite, i.e., the timeout would never happen. */ os_printf("------------ELOOP: Too long timeout\r\n"); - os_free(timeout); + os_free_loose(timeout); return 0; } @@ -246,7 +246,7 @@ int eloop_register_timeout(unsigned int secs, void eloop_remove_timeout(struct eloop_timeout *timeout) { dl_list_del(&timeout->list); - os_free(timeout); + os_free_loose(timeout); } int eloop_cancel_timeout(eloop_timeout_handler handler, @@ -752,7 +752,7 @@ void eloop_destroy(void) eloop_sock_table_destroy(&eloop.writers); eloop_sock_table_destroy(&eloop.exceptions); if(eloop.signal_count == 0) { - os_free(eloop.signals); + os_free_loose(eloop.signals); eloop.signals = NULL; } } @@ -766,7 +766,7 @@ void eloop_free_resource(void) eloop_sock_table_destroy(&eloop.writers); eloop_sock_table_destroy(&eloop.exceptions); if(eloop.signal_count == 0) { - os_free(eloop.signals); + os_free_loose(eloop.signals); eloop.signals = NULL; } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/os.h b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/os.h index 86df7208183afe0a435ad6dc5a722499351666e8..ab92a64473a2c216884428900d2d14ad15a2e9f5 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/os.h +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/os.h @@ -240,7 +240,7 @@ int os_unsetenv(const char *name); * * This function allocates memory and reads the given file to this buffer. Both * binary and text files can be read with this function. The caller is - * responsible for freeing the returned buffer with os_free(). + * responsible for freeing the returned buffer with os_free_loose(). */ char * os_readfile(const char *name, size_t *len); @@ -263,7 +263,7 @@ int os_fdatasync(FILE *stream); * @size: Number of bytes to allocate * Returns: Pointer to allocated and zeroed memory or %NULL on failure * - * Caller is responsible for freeing the returned buffer with os_free(). + * Caller is responsible for freeing the returned buffer with os_free_loose(). */ //void * os_zalloc(size_t size); @@ -277,7 +277,7 @@ int os_fdatasync(FILE *stream); * allocation is used for an array. The main benefit over os_zalloc() is in * having an extra check to catch integer overflows in multiplication. * - * Caller is responsible for freeing the returned buffer with os_free(). + * Caller is responsible for freeing the returned buffer with os_free_loose(). */ #if 0 diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpa_debug.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpa_debug.c index fffb91c71ab63b684831e53d5fed00a42733842b..2483b99875a428f14efe6793fbbf7d622a7d3cfd 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpa_debug.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpa_debug.c @@ -71,7 +71,7 @@ void wpa_dbg(void *ctx, int level, const char *fmt, ...) len = vsnprintf(buf, buflen, fmt, ap); va_end(ap); bk_send_string(uart_print_port, buf); - os_free(buf); + os_free_loose(buf); os_printf("\r\n"); } @@ -376,7 +376,7 @@ void wpa_msg_global_only(void *ctx, int level, const char *fmt, ...) wpa_printf(level, "%s", buf); if (wpa_msg_cb) wpa_msg_cb(ctx, level, WPA_MSG_ONLY_GLOBAL, buf, len); - os_free(buf); + os_free_loose(buf); } #endif /* CONFIG_NO_WPA_MSG */ diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpabuf.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpabuf.c index a814a4063a230516d7037abac497599213ea063d..8d39f5098cbfb20df1b039794519d2ef530719bc 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpabuf.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/src/utils/wpabuf.c @@ -190,14 +190,14 @@ void wpabuf_free(struct wpabuf *buf) wpa_trace_show("wpabuf_free magic mismatch"); } if (buf->flags & WPABUF_FLAG_EXT_DATA) - os_free(buf->buf); - os_free(trace); + os_free_loose(buf->buf); + os_free_loose(trace); #else /* WPA_TRACE */ if (buf == NULL) return; if (buf->flags & WPABUF_FLAG_EXT_DATA) - os_free(buf->buf); - os_free(buf); + os_free_loose(buf->buf); + os_free_loose(buf); #endif /* WPA_TRACE */ } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/blacklist.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/blacklist.c index c035bc7b1a9c0d4b6e8a8e29c3522b58d0ffdb70..5524b010d0d6cc20504597aa1c01064a12afc529 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/blacklist.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/blacklist.c @@ -108,7 +108,7 @@ int wpa_blacklist_del(struct wpa_supplicant *wpa_s, const u8 *bssid) } wpa_printf(MSG_DEBUG, "Removed BSSID " MACSTR " from " "blacklist", MAC2STR(bssid)); - os_free(e); + os_free_loose(e); return 0; } prev = e; @@ -136,7 +136,7 @@ void wpa_blacklist_clear(struct wpa_supplicant *wpa_s) e = e->next; wpa_printf(MSG_DEBUG, "Removed BSSID " MACSTR " from " "blacklist (clear)", MAC2STR(prev->bssid)); - os_free(prev); + os_free_loose(prev); } wpa_s->extra_blacklist_count += max_count; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/bss.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/bss.c index 576db9d51b9c08a6f2466747c14081038a60a1ea..4a4ca6bb8c98112f831eb001ae863cf4849d2261 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/bss.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/bss.c @@ -176,7 +176,7 @@ static void wpa_bss_anqp_free(struct wpa_bss_anqp *anqp) struct wpa_bss_anqp_elem, list))) { dl_list_del(&elem->list); wpabuf_free(elem->payload); - os_free(elem); + os_free_loose(elem); } #endif /* CONFIG_INTERWORKING */ #ifdef CONFIG_HS20 @@ -190,7 +190,7 @@ static void wpa_bss_anqp_free(struct wpa_bss_anqp *anqp) wpabuf_free(anqp->hs20_osu_providers_nai_list); #endif /* CONFIG_HS20 */ - os_free(anqp); + os_free_loose(anqp); } @@ -244,7 +244,7 @@ void wpa_bss_remove(struct wpa_supplicant *wpa_s, struct wpa_bss *bss, wpa_ssid_txt(bss->ssid, bss->ssid_len), reason); wpas_notify_bss_removed(wpa_s, bss->bssid, bss->id); wpa_bss_anqp_free(bss->anqp); - os_free(bss); + os_free_loose(bss); } @@ -1310,7 +1310,7 @@ int wpa_bss_get_max_rate(const struct wpa_bss *bss) * @rates: Buffer for returning a pointer to the rates list (units of 500 kbps) * Returns: number of legacy TX rates or -1 on failure * - * The caller is responsible for freeing the returned buffer with os_free() in + * The caller is responsible for freeing the returned buffer with os_free_loose() in * case of success. */ int wpa_bss_get_bit_rates(const struct wpa_bss *bss, u8 **rates) diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/cmd_wlan.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/cmd_wlan.c index a0b76b603924a1637b2fa5d7560a665aa0edac5c..7f956fb4ec54cad52cca847f878915794d54b9f3 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/cmd_wlan.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/cmd_wlan.c @@ -254,7 +254,7 @@ static int cmd_wpas_parse_key_mgmt(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { os_printf("No key_mgmt values configured\n"); @@ -304,7 +304,7 @@ static int cmd_wpas_parse_cipher(const char *value) else if (os_strcmp(start, "GTK_NOT_USED") == 0) val |= WPA_CIPHER_GTK_NOT_USED; else { - os_free(buf); + os_free_loose(buf); return -1; } @@ -312,7 +312,7 @@ static int cmd_wpas_parse_cipher(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); return val; } @@ -360,7 +360,7 @@ static int cmd_wpas_parse_proto(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); /* softAP work on open mode. */ #if 0 @@ -411,7 +411,7 @@ static int cmd_wpas_parse_auth_alg(const char *value) break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { os_printf("No auth_alg values configured\n"); @@ -716,7 +716,7 @@ int cmd_wlan_sta_exec(char *cmd) ret = wlan_sta_scan_result(&results); if (ret == 0) cmd_wlan_sta_print_scan_results(&results); - os_free(results.ApList); + os_free_loose(results.ApList); } else if (os_strncmp(cmd, "scan interval ", 14) == 0) { int sec; if (cmd_wpas_parse_int(cmd + 14, 0, INT32_MAX, &sec) != 0) { @@ -764,7 +764,7 @@ int cmd_wlan_sta_exec(char *cmd) ret = wlan_sta_ap_info(ap); if (ret == 0) cmd_wlan_sta_print_ap(ap); - os_free(ap); + os_free_loose(ap); } else if (os_strncmp(cmd, "genpsk ", 7) == 0) { uint8_t i; char *argv[2]; @@ -1160,7 +1160,7 @@ int cmd_wlan_ap_exec(char *cmd) ret = wlan_ap_sta_info(&stas); if (ret == 0) cmd_wlan_ap_print_sta_info(&stas); - os_free(stas.sta); + os_free_loose(stas.sta); } else { os_printf("unknown cmd '%s'\n", cmd); return -1; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/config.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/config.c index 0a1c9f427163a3ecb486b01518897bf411504df5..a53d167a7576111420b925bee895ddce7ebc6906 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/config.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/config.c @@ -92,7 +92,7 @@ static int wpa_config_parse_str(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: too short %s (len=%lu " "min_len=%ld)", line, data->name, (unsigned long) res_len, (long) data->param3); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -100,7 +100,7 @@ static int wpa_config_parse_str(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: too long %s (len=%lu " "max_len=%ld)", line, data->name, (unsigned long) res_len, (long) data->param4); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -118,11 +118,11 @@ set: (*dst && tmp && prev_len == res_len && os_memcmp(*dst, tmp, res_len) == 0)) { /* No change to the previously configured value */ - os_free(tmp); + os_free_loose(tmp); return 1; } - os_free(*dst); + os_free_loose(*dst); *dst = tmp; if (data->param2) *dst_len = res_len; @@ -247,7 +247,7 @@ static char * wpa_config_write_int(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, "%d", *src); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -278,7 +278,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, wpa_printf(MSG_ERROR, "Line %d: Invalid %s address '%s'", line, name, value); - os_free(buf); + os_free_loose(buf); return -1; } /* continue anyway since this could have been from a @@ -289,7 +289,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, } else { n = os_realloc_array(buf, count + 1, 2 * ETH_ALEN); if (n == NULL) { - os_free(buf); + os_free_loose(buf); return -1; } buf = n; @@ -306,7 +306,7 @@ static int wpa_config_parse_addr_list(const struct parse_data *data, pos = os_strchr(pos, ' '); } - os_free(*list); + os_free_loose(*list); *list = buf; *num = count; @@ -339,7 +339,7 @@ static char * wpa_config_write_addr_list(const struct parse_data *data, *pos++ = ' '; res = hwaddr_mask_txt(pos, end - pos, a, m); if (res < 0) { - os_free(value); + os_free_loose(value); return NULL; } pos += res; @@ -385,7 +385,7 @@ static char * wpa_config_write_bssid(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, MACSTR, MAC2STR(ssid->bssid)); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -430,7 +430,7 @@ static char * wpa_config_write_bssid_hint(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, MACSTR, MAC2STR(ssid->bssid_hint)); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } return value; @@ -491,7 +491,7 @@ static int wpa_config_parse_psk(const struct parse_data *data, str_clear_free(ssid->passphrase); ssid->passphrase = NULL; ssid->psk_set = 0; - os_free(ssid->ext_psk); + os_free_loose(ssid->ext_psk); ssid->ext_psk = os_strdup(value + 4); if (ssid->ext_psk == NULL) return -1; @@ -574,7 +574,7 @@ static char * wpa_config_write_psk(const struct parse_data *data, return NULL; res = os_snprintf(buf, len, "ext:%s", ssid->ext_psk); if (os_snprintf_error(len, res)) { - os_free(buf); + os_free_loose(buf); buf = NULL; } return buf; @@ -633,7 +633,7 @@ static int wpa_config_parse_proto(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -686,7 +686,7 @@ static char * wpa_config_write_proto(const struct parse_data *data, } if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -795,7 +795,7 @@ static int wpa_config_parse_key_mgmt(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -1024,7 +1024,7 @@ static char * wpa_config_write_key_mgmt(const struct parse_data *data, #endif /* CONFIG_OWE */ if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -1065,7 +1065,7 @@ static char * wpa_config_write_cipher(int cipher) return NULL; if (wpa_write_ciphers(buf, buf + 50, cipher, " ") < 0) { - os_free(buf); + os_free_loose(buf); return NULL; } @@ -1216,7 +1216,7 @@ static int wpa_config_parse_auth_alg(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); if (val == 0) { wpa_printf(MSG_ERROR, @@ -1275,7 +1275,7 @@ static char * wpa_config_write_auth_alg(const struct parse_data *data, } if (pos == buf) { - os_free(buf); + os_free_loose(buf); buf = NULL; } @@ -1305,7 +1305,7 @@ static int * wpa_config_parse_int_array(const char *value) size_t i; n = os_realloc_array(freqs, len * 2 + 1, sizeof(int)); if (n == NULL) { - os_free(freqs); + os_free_loose(freqs); return NULL; } for (i = len; i <= len * 2; i++) @@ -1335,10 +1335,10 @@ static int wpa_config_parse_scan_freq(const struct parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(ssid->scan_freq); + os_free_loose(ssid->scan_freq); ssid->scan_freq = freqs; return 0; @@ -1355,10 +1355,10 @@ static int wpa_config_parse_freq_list(const struct parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(ssid->freq_list); + os_free_loose(ssid->freq_list); ssid->freq_list = freqs; return 0; @@ -1443,8 +1443,8 @@ static int wpa_config_parse_eap(const struct parse_data *data, methods = os_realloc_array(methods, num_methods + 1, sizeof(*methods)); if (methods == NULL) { - os_free(tmp); - os_free(buf); + os_free_loose(tmp); + os_free_loose(buf); return -1; } methods[num_methods].method = eap_peer_get_type( @@ -1468,12 +1468,12 @@ static int wpa_config_parse_eap(const struct parse_data *data, break; start = end + 1; } - os_free(buf); + os_free_loose(buf); tmp = methods; methods = os_realloc_array(methods, num_methods + 1, sizeof(*methods)); if (methods == NULL) { - os_free(tmp); + os_free_loose(tmp); return -1; } methods[num_methods].vendor = EAP_VENDOR_IETF; @@ -1502,13 +1502,13 @@ static int wpa_config_parse_eap(const struct parse_data *data, } } if (match == num_methods) { - os_free(methods); + os_free_loose(methods); return 1; } } wpa_hexdump(MSG_MSGDUMP, "eap methods", (u8 *) methods, num_methods * sizeof(*methods)); - os_free(ssid->eap.eap_methods); + os_free_loose(ssid->eap.eap_methods); ssid->eap.eap_methods = methods; return errors ? -1 : 0; } @@ -1616,7 +1616,7 @@ static int wpa_config_parse_password(const struct parse_data *data, return -1; if (hexstr2bin(value + 5, hash, 16)) { - os_free(hash); + os_free_loose(hash); wpa_printf(MSG_ERROR, "Line %d: Invalid password hash", line); return -1; } @@ -1692,7 +1692,7 @@ static int wpa_config_parse_wep_key(u8 *key, size_t *len, int line, if (*len > MAX_WEP_KEY_LEN) { wpa_printf(MSG_ERROR, "Line %d: Too long WEP key %d '%s'.", line, idx, value); - os_free(buf); + os_free_loose(buf); return -1; } if (*len && *len != 5 && *len != 13 && *len != 16) { @@ -1827,7 +1827,7 @@ static char * wpa_config_write_go_p2p_dev_addr(const struct parse_data *data, return NULL; res = os_snprintf(value, 20, MACSTR, MAC2STR(ssid->go_p2p_dev_addr)); if (os_snprintf_error(20, res)) { - os_free(value); + os_free_loose(value); return NULL; } value[20 - 1] = '\0'; @@ -1878,14 +1878,14 @@ static int wpa_config_parse_psk_list(const struct parse_data *data, if (hwaddr_aton(pos, p->addr)) { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list address '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } pos += 17; if (*pos != '-') { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } pos++; @@ -1893,7 +1893,7 @@ static int wpa_config_parse_psk_list(const struct parse_data *data, if (hexstr2bin(pos, p->psk, PMK_LEN) || pos[PMK_LEN * 2] != '\0') { wpa_printf(MSG_ERROR, "Line %d: Invalid psk_list PSK '%s'", line, pos); - os_free(p); + os_free_loose(p); return -1; } @@ -1928,11 +1928,11 @@ static int wpa_config_parse_mesh_basic_rates(const struct parse_data *data, return -1; } if (rates[0] == 0) { - os_free(rates); + os_free_loose(rates); rates = NULL; } - os_free(ssid->mesh_basic_rates); + os_free_loose(ssid->mesh_basic_rates); ssid->mesh_basic_rates = rates; return 0; @@ -2453,7 +2453,7 @@ int wpa_config_update_prio_list(struct wpa_config *config) struct wpa_ssid *ssid; int ret = 0; - os_free(config->pssid); + os_free_loose(config->pssid); config->pssid = NULL; config->num_prio = 0; @@ -2479,34 +2479,34 @@ void wpa_config_free_ssid(struct wpa_ssid *ssid) { struct psk_list_entry *psk; - os_free(ssid->ssid); + os_free_loose(ssid->ssid); str_clear_free(ssid->passphrase); - os_free(ssid->ext_psk); + os_free_loose(ssid->ext_psk); str_clear_free(ssid->sae_password); - os_free(ssid->sae_password_id); + os_free_loose(ssid->sae_password_id); #ifdef IEEE8021X_EAPOL eap_peer_config_free(&ssid->eap); #endif /* IEEE8021X_EAPOL */ - os_free(ssid->id_str); - os_free(ssid->scan_freq); - os_free(ssid->freq_list); - os_free(ssid->bgscan); - os_free(ssid->p2p_client_list); - os_free(ssid->bssid_blacklist); - os_free(ssid->bssid_whitelist); + os_free_loose(ssid->id_str); + os_free_loose(ssid->scan_freq); + os_free_loose(ssid->freq_list); + os_free_loose(ssid->bgscan); + os_free_loose(ssid->p2p_client_list); + os_free_loose(ssid->bssid_blacklist); + os_free_loose(ssid->bssid_whitelist); #ifdef CONFIG_HT_OVERRIDES - os_free(ssid->ht_mcs); + os_free_loose(ssid->ht_mcs); #endif /* CONFIG_HT_OVERRIDES */ #ifdef CONFIG_MESH - os_free(ssid->mesh_basic_rates); + os_free_loose(ssid->mesh_basic_rates); #endif /* CONFIG_MESH */ - os_free(ssid->dpp_connector); + os_free_loose(ssid->dpp_connector); bin_clear_free(ssid->dpp_netaccesskey, ssid->dpp_netaccesskey_len); - os_free(ssid->dpp_csign); + os_free_loose(ssid->dpp_csign); while (NULL != (psk = dl_list_first(&ssid->psk_list, struct psk_list_entry, list))) { dl_list_del(&psk->list); @@ -2520,30 +2520,30 @@ void wpa_config_free_cred(struct wpa_cred *cred) { size_t i; - os_free(cred->realm); + os_free_loose(cred->realm); str_clear_free(cred->username); str_clear_free(cred->password); - os_free(cred->ca_cert); - os_free(cred->client_cert); - os_free(cred->private_key); + os_free_loose(cred->ca_cert); + os_free_loose(cred->client_cert); + os_free_loose(cred->private_key); str_clear_free(cred->private_key_passwd); - os_free(cred->imsi); + os_free_loose(cred->imsi); str_clear_free(cred->milenage); for (i = 0; i < cred->num_domain; i++) - os_free(cred->domain[i]); - os_free(cred->domain); - os_free(cred->domain_suffix_match); - os_free(cred->eap_method); - os_free(cred->phase1); - os_free(cred->phase2); - os_free(cred->excluded_ssid); - os_free(cred->roaming_partner); - os_free(cred->provisioning_sp); + os_free_loose(cred->domain[i]); + os_free_loose(cred->domain); + os_free_loose(cred->domain_suffix_match); + os_free_loose(cred->eap_method); + os_free_loose(cred->phase1); + os_free_loose(cred->phase2); + os_free_loose(cred->excluded_ssid); + os_free_loose(cred->roaming_partner); + os_free_loose(cred->provisioning_sp); for (i = 0; i < cred->num_req_conn_capab; i++) - os_free(cred->req_conn_capab_port[i]); - os_free(cred->req_conn_capab_port); - os_free(cred->req_conn_capab_proto); - os_free(cred); + os_free_loose(cred->req_conn_capab_port[i]); + os_free_loose(cred->req_conn_capab_port); + os_free_loose(cred->req_conn_capab_proto); + os_free_loose(cred); } @@ -2570,43 +2570,43 @@ void wpa_config_free(struct wpa_config *config) wpabuf_free(config->wps_vendor_ext_m1); for (i = 0; i < MAX_WPS_VENDOR_EXT; i++) wpabuf_free(config->wps_vendor_ext[i]); - os_free(config->ctrl_interface); - os_free(config->ctrl_interface_group); - os_free(config->opensc_engine_path); - os_free(config->pkcs11_engine_path); - os_free(config->pkcs11_module_path); - os_free(config->openssl_ciphers); - os_free(config->pcsc_reader); + os_free_loose(config->ctrl_interface); + os_free_loose(config->ctrl_interface_group); + os_free_loose(config->opensc_engine_path); + os_free_loose(config->pkcs11_engine_path); + os_free_loose(config->pkcs11_module_path); + os_free_loose(config->openssl_ciphers); + os_free_loose(config->pcsc_reader); str_clear_free(config->pcsc_pin); - os_free(config->driver_param); - os_free(config->device_name); - os_free(config->manufacturer); - os_free(config->model_name); - os_free(config->model_number); - os_free(config->serial_number); - os_free(config->config_methods); - os_free(config->p2p_ssid_postfix); - os_free(config->pssid); - os_free(config->p2p_pref_chan); - os_free(config->p2p_no_go_freq.range); - os_free(config->autoscan); - os_free(config->freq_list); + os_free_loose(config->driver_param); + os_free_loose(config->device_name); + os_free_loose(config->manufacturer); + os_free_loose(config->model_name); + os_free_loose(config->model_number); + os_free_loose(config->serial_number); + os_free_loose(config->config_methods); + os_free_loose(config->p2p_ssid_postfix); + os_free_loose(config->pssid); + os_free_loose(config->p2p_pref_chan); + os_free_loose(config->p2p_no_go_freq.range); + os_free_loose(config->autoscan); + os_free_loose(config->freq_list); wpabuf_free(config->wps_nfc_dh_pubkey); wpabuf_free(config->wps_nfc_dh_privkey); wpabuf_free(config->wps_nfc_dev_pw); - os_free(config->ext_password_backend); - os_free(config->sae_groups); + os_free_loose(config->ext_password_backend); + os_free_loose(config->sae_groups); wpabuf_free(config->ap_vendor_elements); - os_free(config->osu_dir); - os_free(config->bgscan); - os_free(config->wowlan_triggers); - os_free(config->fst_group_id); - os_free(config->sched_scan_plans); + os_free_loose(config->osu_dir); + os_free_loose(config->bgscan); + os_free_loose(config->wowlan_triggers); + os_free_loose(config->fst_group_id); + os_free_loose(config->sched_scan_plans); #ifdef CONFIG_MBO - os_free(config->non_pref_chan); + os_free_loose(config->non_pref_chan); #endif /* CONFIG_MBO */ - os_free(config); + os_free_loose(config); } @@ -2852,7 +2852,7 @@ int wpa_config_set_quoted(struct wpa_ssid *ssid, const char *var, buf[len + 1] = '"'; buf[len + 2] = '\0'; ret = wpa_config_set(ssid, var, buf, 0); - os_free(buf); + os_free_loose(buf); return ret; } @@ -2896,13 +2896,13 @@ char ** wpa_config_get_all(struct wpa_ssid *ssid, int get_keys) if (value == NULL) continue; if (os_strlen(value) == 0) { - os_free(value); + os_free_loose(value); continue; } key = os_strdup(field->name); if (key == NULL) { - os_free(value); + os_free_loose(value); goto err; } @@ -2916,8 +2916,8 @@ char ** wpa_config_get_all(struct wpa_ssid *ssid, int get_keys) err: for (i = 0; props[i]; i++) - os_free(props[i]); - os_free(props); + os_free_loose(props[i]); + os_free_loose(props); return NULL; #endif /* NO_CONFIG_WRITE */ } @@ -2952,7 +2952,7 @@ char * wpa_config_get(struct wpa_ssid *ssid, const char *var) wpa_printf(MSG_ERROR, "Found newline in value for %s; not returning it", var); - os_free(ret); + os_free_loose(ret); ret = NULL; } @@ -3000,7 +3000,7 @@ char * wpa_config_get_no_key(struct wpa_ssid *ssid, const char *var) return os_strdup("*"); } - os_free(res); + os_free_loose(res); return NULL; } return res; @@ -3091,7 +3091,7 @@ static int wpa_config_set_cred_req_conn_capab(struct wpa_cred *cred, while (*pos) { nports = os_realloc_array(ports, num_ports + 1, sizeof(int)); if (nports == NULL) { - os_free(ports); + os_free_loose(ports); return -1; } ports = nports; @@ -3105,7 +3105,7 @@ static int wpa_config_set_cred_req_conn_capab(struct wpa_cred *cred, nports = os_realloc_array(ports, num_ports + 1, sizeof(int)); if (nports == NULL) { - os_free(ports); + os_free_loose(ports); return -1; } ports = nports; @@ -3201,7 +3201,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "realm") == 0) { - os_free(cred->realm); + os_free_loose(cred->realm); cred->realm = val; return 0; } @@ -3220,19 +3220,19 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "ca_cert") == 0) { - os_free(cred->ca_cert); + os_free_loose(cred->ca_cert); cred->ca_cert = val; return 0; } if (os_strcmp(var, "client_cert") == 0) { - os_free(cred->client_cert); + os_free_loose(cred->client_cert); cred->client_cert = val; return 0; } if (os_strcmp(var, "private_key") == 0) { - os_free(cred->private_key); + os_free_loose(cred->private_key); cred->private_key = val; return 0; } @@ -3244,7 +3244,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "imsi") == 0) { - os_free(cred->imsi); + os_free_loose(cred->imsi); cred->imsi = val; return 0; } @@ -3256,7 +3256,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "domain_suffix_match") == 0) { - os_free(cred->domain_suffix_match); + os_free_loose(cred->domain_suffix_match); cred->domain_suffix_match = val; return 0; } @@ -3267,7 +3267,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_domain + 1, sizeof(char *)); if (new_domain == NULL) { - os_free(val); + os_free_loose(val); return -1; } new_domain[cred->num_domain++] = val; @@ -3276,13 +3276,13 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, } if (os_strcmp(var, "phase1") == 0) { - os_free(cred->phase1); + os_free_loose(cred->phase1); cred->phase1 = val; return 0; } if (os_strcmp(var, "phase2") == 0) { - os_free(cred->phase2); + os_free_loose(cred->phase2); cred->phase2 = val; return 0; } @@ -3292,12 +3292,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, wpa_printf(MSG_ERROR, "Line %d: invalid " "roaming_consortium length %d (3..15 " "expected)", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } os_memcpy(cred->roaming_consortium, val, len); cred->roaming_consortium_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -3307,12 +3307,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, wpa_printf(MSG_ERROR, "Line %d: invalid " "required_roaming_consortium length %d " "(3..15 expected)", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } os_memcpy(cred->required_roaming_consortium, val, len); cred->required_roaming_consortium_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -3322,7 +3322,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, if (len > SSID_MAX_LEN) { wpa_printf(MSG_ERROR, "Line %d: invalid " "excluded_ssid length %d", line, (int) len); - os_free(val); + os_free_loose(val); return -1; } @@ -3330,7 +3330,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_excluded_ssid + 1, sizeof(struct excluded_ssid)); if (e == NULL) { - os_free(val); + os_free_loose(val); return -1; } cred->excluded_ssid = e; @@ -3339,7 +3339,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, os_memcpy(e->ssid, val, len); e->ssid_len = len; - os_free(val); + os_free_loose(val); return 0; } @@ -3352,7 +3352,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, cred->num_roaming_partner + 1, sizeof(struct roaming_partner)); if (p == NULL) { - os_free(val); + os_free_loose(val); return -1; } cred->roaming_partner = p; @@ -3361,12 +3361,12 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(val, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; if (pos - val - 1 >= (int) sizeof(p->fqdn)) { - os_free(val); + os_free_loose(val); return -1; } os_memcpy(p->fqdn, val, pos - val); @@ -3375,7 +3375,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(pos, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; @@ -3384,25 +3384,25 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, pos = os_strchr(pos, ','); if (pos == NULL) { - os_free(val); + os_free_loose(val); return -1; } *pos++ = '\0'; if (os_strlen(pos) >= sizeof(p->country)) { - os_free(val); + os_free_loose(val); return -1; } os_memcpy(p->country, pos, os_strlen(pos) + 1); cred->num_roaming_partner++; - os_free(val); + os_free_loose(val); return 0; } if (os_strcmp(var, "provisioning_sp") == 0) { - os_free(cred->provisioning_sp); + os_free_loose(cred->provisioning_sp); cred->provisioning_sp = val; return 0; } @@ -3412,7 +3412,7 @@ int wpa_config_set_cred(struct wpa_cred *cred, const char *var, line, var); } - os_free(val); + os_free_loose(val); return -1; } @@ -3428,7 +3428,7 @@ static char * alloc_int_str(int val) return NULL; res = os_snprintf(buf, bufsize, "%d", val); if (os_snprintf_error(bufsize, res)) { - os_free(buf); + os_free_loose(buf); buf = NULL; } return buf; @@ -3921,7 +3921,7 @@ static int wpa_global_config_parse_str(const struct global_parse_data *data, return -1; dst = (char **) (((u8 *) config) + (long) data->param1); - os_free(*dst); + os_free_loose(*dst); *dst = tmp; wpa_printf(MSG_DEBUG, "%s='%s'", data->name, *dst); @@ -3945,7 +3945,7 @@ static int wpa_config_process_bgscan(const struct global_parse_data *data, } res = wpa_global_config_parse_str(data, config, line, tmp); - os_free(tmp); + os_free_loose(tmp); return res; } @@ -3979,10 +3979,10 @@ static int wpa_config_process_freq_list(const struct global_parse_data *data, if (freqs == NULL) return -1; if (freqs[0] == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } - os_free(config->freq_list); + os_free_loose(config->freq_list); config->freq_list = freqs; return 0; } @@ -4072,7 +4072,7 @@ static int wpa_config_process_sae_groups( return -1; } - os_free(config->sae_groups); + os_free_loose(config->sae_groups); config->sae_groups = groups; return 0; @@ -4122,7 +4122,7 @@ static int wpa_config_process_no_ctrl_interface( struct wpa_config *config, int line, const char *pos) { wpa_printf(MSG_DEBUG, "no_ctrl_interface -> ctrl_interface=NULL"); - os_free(config->ctrl_interface); + os_free_loose(config->ctrl_interface); config->ctrl_interface = NULL; return 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/ctrl_iface.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/ctrl_iface.c index c2d4658bdda5abb3fdd47e5c1249f57c93c90515..63a2f3344cd85d3576ed6a18831744267924986a 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/ctrl_iface.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/ctrl_iface.c @@ -140,7 +140,7 @@ static int wpa_supplicant_ctrl_iface_select_network( int *freqs = freq_range_to_channel_list(wpa_s, pos + 6); if (freqs) { wpa_s->scan_req = MANUAL_SCAN_REQ; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = freqs; } } @@ -616,7 +616,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) #endif wpa_s->num_ssids_from_scan_req = ssid_count; - os_free(wpa_s->ssids_from_scan_req); + os_free_loose(wpa_s->ssids_from_scan_req); if (ssid_count) { wpa_s->ssids_from_scan_req = ssid; ssid = NULL; @@ -640,7 +640,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) wpa_s->scan_id_count = scan_id_count; os_memcpy(wpa_s->scan_id, scan_id, scan_id_count * sizeof(int)); wpa_s->scan_res_handler = scan_res_handler; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = manual_scan_freqs; manual_scan_freqs = NULL; @@ -668,7 +668,7 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) wpa_s->scan_id_count = scan_id_count; os_memcpy(wpa_s->scan_id, scan_id, scan_id_count * sizeof(int)); wpa_s->scan_res_handler = scan_res_handler; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = manual_scan_freqs; manual_scan_freqs = NULL; @@ -691,8 +691,8 @@ static int wpas_ctrl_scan(struct wpa_supplicant *wpa_s, char *params) } done: - os_free(manual_scan_freqs); - os_free(ssid); + os_free_loose(manual_scan_freqs); + os_free_loose(ssid); return ret; } @@ -835,7 +835,7 @@ int wpa_supplicant_ctrl_iface_set_network(struct wpa_supplicant *wpa_s, wlan_sta wpa_sm_pmksa_cache_flush(wpa_s->wpa, ssid); } if (ssid->ssid) - os_free(ssid->ssid); + os_free_loose(ssid->ssid); ssid->ssid = (u8 *)dup_binstr(config->u.ssid.ssid, config->u.ssid.ssid_len); ssid->ssid_len = config->u.ssid.ssid_len; break; @@ -914,7 +914,7 @@ int wpa_supplicant_ctrl_iface_set_network(struct wpa_supplicant *wpa_s, wlan_sta case WLAN_STA_FIELD_SAE_GROUPS: { int *groups = os_malloc(sizeof(config->u.sae_groups)); if (groups) { - os_free(wpa_s->conf->sae_groups); + os_free_loose(wpa_s->conf->sae_groups); os_memcpy(groups, config->u.sae_groups, sizeof(config->u.sae_groups)); wpa_s->conf->sae_groups = groups; //while (*groups) { @@ -1202,7 +1202,7 @@ exit: if (msg->sema) rtos_set_semaphore(&msg->sema); if (msg->flags & WPAH_FLAG_FREE) - os_free((void *)msg->argu); + os_free_loose((void *)msg->argu); #undef CHECK_WPA_S @@ -1304,7 +1304,7 @@ exit: if (msg->sema) rtos_set_semaphore(&msg->sema); if (msg->flags & WPAH_FLAG_FREE) - os_free((void *)msg->argu); + os_free_loose((void *)msg->argu); #undef CHECK_WPA_S diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/events.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/events.c index 93eee300c1a55a9be5f1d9d8507bb7f1fc7b3848..20a56ddfe361e405c0d870f20f941b963a30c2be 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/events.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/events.c @@ -1169,7 +1169,7 @@ struct wpa_ssid * wpa_scan_res_match(struct wpa_supplicant *wpa_s, #if CFG_SUPPORT_BSSID_CONNECT } else if (0 == ssid->ssid_len) { if (NULL != ssid->ssid) { - os_free(ssid->ssid); + os_free_loose(ssid->ssid); } ssid->ssid = dup_binstr(bss->ssid, bss->ssid_len); if (NULL != ssid->ssid) { @@ -3991,7 +3991,7 @@ static void wpa_supplicant_notify_avoid_freq(struct wpa_supplicant *wpa_s, } #endif /* CONFIG_P2P */ - os_free(str); + os_free_loose(str); } @@ -4612,7 +4612,7 @@ void wpa_supplicant_event_sta(void *ctx, enum wpa_event_type event, wpa_msg(wpa_s, MSG_INFO, "MGMT-RX freq=%d datarate=%u ssi_signal=%d %s", rx->freq, rx->datarate, rx->ssi_signal, hex); - os_free(hex); + os_free_loose(hex); } break; } @@ -5070,7 +5070,7 @@ void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event, if (!wpa_i) return; wpa_s = wpa_supplicant_add_iface(ctx, wpa_i, NULL); - os_free(wpa_i); + os_free_loose(wpa_i); if (wpa_s) wpa_s->matched = 1; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/main_supplicant.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/main_supplicant.c index 4b91b91c67d750401b09a7fd2334aa5fe846fe35..d2a8d3fba0414f201233c8d4cb08338d34620f4d 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/main_supplicant.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/main_supplicant.c @@ -164,12 +164,12 @@ int supplicant_main_exit(void) } if (wpas_ifaces) { - os_free(wpas_ifaces); + os_free_loose(wpas_ifaces); wpas_ifaces = 0; } if (wpas_connect_ssid) { - os_free(wpas_connect_ssid); + os_free_loose(wpas_connect_ssid); wpas_connect_ssid = 0; } @@ -290,7 +290,7 @@ int supplicant_main_entry(char *oob_ssid) } out: - os_free(wpas_ifaces); + os_free_loose(wpas_ifaces); wpas_ifaces = 0; return exitcode; diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/notify.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/notify.c index f181911c8a42c14d339ee7b19956f6a779fa39d8..928d54cc989ddeb2be2a17fa257a38efda5a7341 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/notify.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/notify.c @@ -896,7 +896,7 @@ void wpas_notify_certification(struct wpa_supplicant *wpa_s, WPA_EVENT_EAP_PEER_CERT "depth=%d subject='%s' cert=%s", cert->depth, cert->subject, cert_hex); - os_free(cert_hex); + os_free_loose(cert_hex); } } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/sme.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/sme.c index 1eb73d855aacfed59beb6005eb4d20189c9f2730..762e1306b23ec794f4c28cd8cc0e89dcee6c59ab 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/sme.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/sme.c @@ -610,7 +610,7 @@ static void sme_send_authentication(struct wpa_supplicant *wpa_s, wpa_dbg(wpa_s, MSG_DEBUG, "WPA: Failed to add WPA IE"); } - os_free(wpa_ie); + os_free_loose(wpa_ie); } #ifdef CONFIG_FULL_SUPPLICANT @@ -1338,7 +1338,7 @@ void sme_event_auth(struct wpa_supplicant *wpa_s, union wpa_event_data *data) data->auth.auth_transaction, data->auth.status_code, ie_txt ? " ie=" : "", ie_txt ? ie_txt : ""); - os_free(ie_txt); + os_free_loose(ie_txt); #ifdef CONFIG_FILS if (wpa_s->sme.auth_alg == WPA_AUTH_ALG_FILS || @@ -1745,7 +1745,7 @@ pfs_fail: rm_en_len > sizeof(wpa_s->sme.assoc_req_ie)) { wpa_printf(MSG_ERROR, "SME: Not enough buffer room for FT IEs in Association Request frame"); - os_free(rm_en_dup); + os_free_loose(rm_en_dup); return; } @@ -1764,7 +1764,7 @@ pfs_fail: if (rm_en_dup) { os_memcpy(wpos, rm_en_dup, rm_en_len); wpos += rm_en_len; - os_free(rm_en_dup); + os_free_loose(rm_en_dup); } os_memcpy(wpos, pos, end - pos); wpa_s->sme.assoc_req_ie_len += wpa_s->sme.ft_ies_len + @@ -1854,7 +1854,7 @@ int sme_update_ft_ies(struct wpa_supplicant *wpa_s, const u8 *md, { if (md == NULL || ies == NULL) { wpa_dbg(wpa_s, MSG_DEBUG, "SME: Remove mobility domain"); - os_free(wpa_s->sme.ft_ies); + os_free_loose(wpa_s->sme.ft_ies); wpa_s->sme.ft_ies = NULL; wpa_s->sme.ft_ies_len = 0; wpa_s->sme.ft_used = 0; @@ -1863,7 +1863,7 @@ int sme_update_ft_ies(struct wpa_supplicant *wpa_s, const u8 *md, os_memcpy(wpa_s->sme.mobility_domain, md, MOBILITY_DOMAIN_ID_LEN); wpa_hexdump(MSG_DEBUG, "SME: FT IEs", ies, ies_len); - os_free(wpa_s->sme.ft_ies); + os_free_loose(wpa_s->sme.ft_ies); wpa_s->sme.ft_ies = os_memdup(ies, ies_len); if (wpa_s->sme.ft_ies == NULL) return -1; @@ -2260,7 +2260,7 @@ static void sme_obss_scan_timeout(void *eloop_ctx, void *timeout_ctx) wpa_printf(MSG_DEBUG, "SME OBSS: Failed to trigger scan"); else wpa_s->sme.sched_obss_scan = 1; - os_free(params.freqs); + os_free_loose(params.freqs); eloop_register_timeout(wpa_s->sme.obss_scan_int, 0, sme_obss_scan_timeout, wpa_s, NULL); @@ -2452,7 +2452,7 @@ static void sme_stop_sa_query(struct wpa_supplicant *wpa_s) if (wpa_s->sme.sa_query_trans_id) wpa_dbg(wpa_s, MSG_DEBUG, "SME: Stop SA Query"); eloop_cancel_timeout(sme_sa_query_timer, wpa_s, NULL); - os_free(wpa_s->sme.sa_query_trans_id); + os_free_loose(wpa_s->sme.sa_query_trans_id); wpa_s->sme.sa_query_trans_id = NULL; wpa_s->sme.sa_query_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wmm_ac.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wmm_ac.c index 38800cc77fb70438e98585aee35085893c4acc41..6606f8ba0fdee318e6c652736a9375a00397fc29 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wmm_ac.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wmm_ac.c @@ -98,7 +98,7 @@ static int wmm_ac_add_ts(struct wpa_supplicant *wpa_s, const u8 *addr, " TSID=%u admitted time=%u, ret=%d", MAC2STR(addr), tsid, admitted_time, ret); if (ret < 0) { - os_free(_tspec); + os_free_loose(_tspec); return -1; } } @@ -134,7 +134,7 @@ static void wmm_ac_del_ts_idx(struct wpa_supplicant *wpa_s, u8 ac, wpa_msg(wpa_s, MSG_INFO, WMM_AC_EVENT_TSPEC_REMOVED "tsid=%d addr=" MACSTR, tsid, MAC2STR(wpa_s->bssid)); - os_free(wpa_s->tspecs[ac][dir]); + os_free_loose(wpa_s->tspecs[ac][dir]); wpa_s->tspecs[ac][dir] = NULL; } @@ -152,7 +152,7 @@ static void wmm_ac_del_req(struct wpa_supplicant *wpa_s, int failed) eloop_cancel_timeout(wmm_ac_addts_req_timeout, wpa_s, req); wpa_s->addts_request = NULL; - os_free(req); + os_free_loose(req); } @@ -520,7 +520,7 @@ static void wmm_ac_deinit(struct wpa_supplicant *wpa_s) /* delete pending add_ts request */ wmm_ac_del_req(wpa_s, 1); - os_free(wpa_s->wmm_ac_assoc_info); + os_free_loose(wpa_s->wmm_ac_assoc_info); wpa_s->wmm_ac_assoc_info = NULL; } @@ -623,7 +623,7 @@ int wpas_wmm_ac_addts(struct wpa_supplicant *wpa_s, wpa_s, addts_req); return 0; err: - os_free(addts_req); + os_free_loose(addts_req); return -1; } @@ -963,7 +963,7 @@ void wmm_ac_clear_saved_tspecs(struct wpa_supplicant *wpa_s) { if (wpa_s->last_tspecs) { wpa_printf(MSG_DEBUG, "WMM AC: Clear saved tspecs"); - os_free(wpa_s->last_tspecs); + os_free_loose(wpa_s->last_tspecs); wpa_s->last_tspecs = NULL; wpa_s->last_tspecs_count = 0; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_scan.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_scan.c index cb8d2ee0bdc821329b4d8efad430be7ec91784f8..0fbd5fc8f7e8113d06ce9a2f6a15ae369ea3e7da 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_scan.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_scan.c @@ -1012,7 +1012,7 @@ static void wpa_supplicant_scan(void *eloop_ctx, void *timeout_ctx) int_array_concat(¶ms.freqs, tssid->scan_freq); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } freqs_set = 1; @@ -1094,7 +1094,7 @@ ssid_list_set: "generated frequency list"); params.freqs = wpa_s->next_scan_freqs; } else - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; #endif /* CONFIG_FULL_SUPPLICANT */ wpa_setband_scan_freqs(wpa_s, ¶ms); @@ -1119,7 +1119,7 @@ ssid_list_set: "current operating channels since " "scan_cur_freq is enabled"); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } } @@ -1211,7 +1211,7 @@ scan: if (num > 0 && num == wpa_s->num_multichan_concurrent) { wpa_dbg(wpa_s, MSG_DEBUG, "Scan only the current operating channels since all channels are already used"); } else { - os_free(params.freqs); + os_free_loose(params.freqs); params.freqs = NULL; } } @@ -1228,8 +1228,8 @@ scan: } wpabuf_free(extra_ie); - os_free(params.freqs); - os_free(params.filter_ssids); + os_free_loose(params.freqs); + os_free_loose(params.filter_ssids); if (ret) { wpa_msg(wpa_s, MSG_WARNING, "Failed to initiate AP scan"); @@ -1509,7 +1509,7 @@ int wpa_supplicant_req_sched_scan(struct wpa_supplicant *wpa_s) { wpa_dbg(wpa_s, MSG_DEBUG, "Not enough room for SSID " "filter for sched_scan - drop filter"); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); params.filter_ssids = NULL; params.num_filter_ssids = 0; } @@ -1546,7 +1546,7 @@ int wpa_supplicant_req_sched_scan(struct wpa_supplicant *wpa_s) } if (params.num_filter_ssids == 0) { - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); params.filter_ssids = NULL; } @@ -1642,7 +1642,7 @@ scan: ret = wpa_supplicant_start_sched_scan(wpa_s, scan_params); wpabuf_free(extra_ie); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); if (ret) { wpa_msg(wpa_s, MSG_WARNING, "Failed to initiate sched scan"); if (prev_state != wpa_s->wpa_state) @@ -2111,7 +2111,7 @@ void filter_scan_res(struct wpa_supplicant *wpa_s, res->res[i]->bssid)) { res->res[j++] = res->res[i]; } else { - os_free(res->res[i]); + os_free_loose(res->res[i]); res->res[i] = NULL; } } @@ -2566,21 +2566,21 @@ void wpa_scan_free_params(struct wpa_driver_scan_params *params) return; for (i = 0; i < params->num_ssids; i++) - os_free((u8 *) params->ssids[i].ssid); - os_free((u8 *) params->extra_ies); - os_free(params->freqs); - os_free(params->filter_ssids); - os_free(params->sched_scan_plans); + os_free_loose((u8 *) params->ssids[i].ssid); + os_free_loose((u8 *) params->extra_ies); + os_free_loose(params->freqs); + os_free_loose(params->filter_ssids); + os_free_loose(params->sched_scan_plans); /* * Note: params->mac_addr_mask points to same memory allocation and * must not be freed separately. */ - os_free((u8 *) params->mac_addr); + os_free_loose((u8 *) params->mac_addr); - os_free((u8 *) params->bssid); + os_free_loose((u8 *) params->bssid); - os_free(params); + os_free_loose(params); } #if 0 @@ -2738,7 +2738,7 @@ int wpas_start_pno(struct wpa_supplicant *wpa_s) wpa_scan_set_relative_rssi_params(wpa_s, ¶ms); ret = wpa_supplicant_start_sched_scan(wpa_s, ¶ms); - os_free(params.filter_ssids); + os_free_loose(params.filter_ssids); if (ret == 0) wpa_s->pno = 1; else @@ -2775,17 +2775,17 @@ void wpas_mac_addr_rand_scan_clear(struct wpa_supplicant *wpa_s, wpa_s->mac_addr_rand_enable &= ~type; if (type & MAC_ADDR_RAND_SCAN) { - os_free(wpa_s->mac_addr_scan); + os_free_loose(wpa_s->mac_addr_scan); wpa_s->mac_addr_scan = NULL; } if (type & MAC_ADDR_RAND_SCHED_SCAN) { - os_free(wpa_s->mac_addr_sched_scan); + os_free_loose(wpa_s->mac_addr_sched_scan); wpa_s->mac_addr_sched_scan = NULL; } if (type & MAC_ADDR_RAND_PNO) { - os_free(wpa_s->mac_addr_pno); + os_free_loose(wpa_s->mac_addr_pno); wpa_s->mac_addr_pno = NULL; } } @@ -2824,7 +2824,7 @@ int wpas_mac_addr_rand_scan_set(struct wpa_supplicant *wpa_s, wpa_printf(MSG_INFO, "scan: Invalid MAC randomization type=0x%x", type); - os_free(tmp); + os_free_loose(tmp); return -1; } @@ -2864,7 +2864,7 @@ int wpas_sched_scan_plans_set(struct wpa_supplicant *wpa_s, const char *cmd) if (!cmd[0]) { wpa_printf(MSG_DEBUG, "Clear sched scan plans"); - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = NULL; wpa_s->sched_scan_plans_num = 0; return 0; @@ -2952,14 +2952,14 @@ int wpas_sched_scan_plans_set(struct wpa_supplicant *wpa_s, const char *cmd) num = wpa_s->max_sched_scan_plans; } - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = scan_plans; wpa_s->sched_scan_plans_num = num; return 0; fail: - os_free(scan_plans); + os_free_loose(scan_plans); wpa_printf(MSG_ERROR, "invalid scan plans list"); return -1; #else diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_supplicant.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_supplicant.c index a0652f4c65971d2fc55d5604e94be67237de6336..4ae1553b05fe8fae2800796061605681abea8aee 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_supplicant.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpa_supplicant.c @@ -250,7 +250,7 @@ void wpa_supplicant_cancel_auth_timeout(struct wpa_supplicant *wpa_s) eloop_cancel_timeout(wpa_supplicant_timeout, wpa_s, NULL); wpa_blacklist_del(wpa_s, wpa_s->bssid); #ifdef CONFIG_FILS - os_free(wpa_s->last_con_fail_realm); + os_free_loose(wpa_s->last_con_fail_realm); wpa_s->last_con_fail_realm = NULL; wpa_s->last_con_fail_realm_len = 0; #endif @@ -408,11 +408,11 @@ void free_hw_features(struct wpa_supplicant *wpa_s) return; for (i = 0; i < wpa_s->hw.num_modes; i++) { - os_free(wpa_s->hw.modes[i].channels); - os_free(wpa_s->hw.modes[i].rates); + os_free_loose(wpa_s->hw.modes[i].channels); + os_free_loose(wpa_s->hw.modes[i].rates); } - os_free(wpa_s->hw.modes); + os_free_loose(wpa_s->hw.modes); wpa_s->hw.modes = NULL; } @@ -426,7 +426,7 @@ void free_bss_tmp_disallowed(struct wpa_supplicant *wpa_s) struct wpa_bss_tmp_disallowed, list) { eloop_cancel_timeout(wpa_bss_tmp_disallow_timeout, wpa_s, bss); dl_list_del(&bss->list); - os_free(bss); + os_free_loose(bss); } } #endif @@ -440,7 +440,7 @@ void wpas_flush_fils_hlp_req(struct wpa_supplicant *wpa_s) list)) != NULL) { dl_list_del(&req->list); wpabuf_free(req->pkt); - os_free(req); + os_free_loose(req); } } #endif @@ -469,14 +469,14 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wpas_notify_network_removed(wpa_s, ssid); } - os_free(wpa_s->confname); + os_free_loose(wpa_s->confname); wpa_s->confname = NULL; - os_free(wpa_s->confanother); + os_free_loose(wpa_s->confanother); wpa_s->confanother = NULL; #ifdef CONFIG_FILS - os_free(wpa_s->last_con_fail_realm); + os_free_loose(wpa_s->last_con_fail_realm); wpa_s->last_con_fail_realm = NULL; wpa_s->last_con_fail_realm_len = 0; #endif @@ -540,15 +540,15 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wpa_supplicant_cancel_sched_scan(wpa_s); - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; - os_free(wpa_s->manual_scan_freqs); + os_free_loose(wpa_s->manual_scan_freqs); wpa_s->manual_scan_freqs = NULL; - os_free(wpa_s->select_network_scan_freqs); + os_free_loose(wpa_s->select_network_scan_freqs); wpa_s->select_network_scan_freqs = NULL; - os_free(wpa_s->manual_sched_scan_freqs); + os_free_loose(wpa_s->manual_sched_scan_freqs); wpa_s->manual_sched_scan_freqs = NULL; #ifdef CONFIG_RANDOM_MAC @@ -559,12 +559,12 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) ieee802_1x_dealloc_kay_sm(wpa_s); #ifdef CONFIG_FULL_SUPPLICANT - os_free(wpa_s->bssid_filter); + os_free_loose(wpa_s->bssid_filter); wpa_s->bssid_filter = NULL; - os_free(wpa_s->disallow_aps_bssid); + os_free_loose(wpa_s->disallow_aps_bssid); wpa_s->disallow_aps_bssid = NULL; - os_free(wpa_s->disallow_aps_ssid); + os_free_loose(wpa_s->disallow_aps_ssid); wpa_s->disallow_aps_ssid = NULL; #endif @@ -578,7 +578,7 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) wpa_s->ext_pw = NULL; #endif - os_free(wpa_s->last_scan_res); + os_free_loose(wpa_s->last_scan_res); wpa_s->last_scan_res = NULL; #ifdef CONFIG_HS20 @@ -595,7 +595,7 @@ static void wpa_supplicant_cleanup(struct wpa_supplicant *wpa_s) #ifdef CONFIG_FULL_SUPPLICANT wpa_s->sched_scan_plans_num = 0; - os_free(wpa_s->sched_scan_plans); + os_free_loose(wpa_s->sched_scan_plans); wpa_s->sched_scan_plans = NULL; free_bss_tmp_disallowed(wpa_s); @@ -779,6 +779,10 @@ void wpa_supplicant_set_state(struct wpa_supplicant *wpa_s, { enum wpa_states old_state = wpa_s->wpa_state; + os_printf("State: %s -> %s wpa_supplicant_set_state\r\n", + wpa_supplicant_state_txt(wpa_s->wpa_state), + wpa_supplicant_state_txt(state)); + wpa_dbg(wpa_s, MSG_DEBUG, "State: %s -> %s", wpa_supplicant_state_txt(wpa_s->wpa_state), wpa_supplicant_state_txt(state)); @@ -1777,7 +1781,7 @@ void wpas_connect_work_free(struct wpa_connect_work *cwork) { if (cwork == NULL) return; - os_free(cwork); + os_free_loose(cwork); } @@ -2045,7 +2049,7 @@ void wpa_supplicant_associate(struct wpa_supplicant *wpa_s, if (radio_add_work(wpa_s, bss ? bss->freq : 0, "connect", 1, wpas_start_assoc_cb, cwork) < 0) { - os_free(cwork); + os_free_loose(cwork); } #endif } @@ -2537,7 +2541,7 @@ static u8 * wpas_populate_assoc_ies( wpa_ie, &wpa_ie_len)) { wpa_msg(wpa_s, MSG_WARNING, "WPA: Failed to set WPA " "key management and encryption suites"); - os_free(wpa_ie); + os_free_loose(wpa_ie); return NULL; } #ifdef CONFIG_HS20 @@ -2549,7 +2553,7 @@ static u8 * wpas_populate_assoc_ies( wpa_ie, &wpa_ie_len)) { wpa_msg(wpa_s, MSG_WARNING, "WPA: Failed to set WPA " "key management and encryption suites"); - os_free(wpa_ie); + os_free_loose(wpa_ie); return NULL; } #endif /* CONFIG_HS20 */ @@ -2572,7 +2576,7 @@ static u8 * wpas_populate_assoc_ies( wpa_msg(wpa_s, MSG_WARNING, "WPA: Failed to set WPA " "key management and encryption suites (no " "scan results)"); - os_free(wpa_ie); + os_free_loose(wpa_ie); return NULL; } #ifdef CONFIG_WPS @@ -2900,7 +2904,7 @@ pfs_fail: if (multi_ap_ie_len == 0) { wpa_printf(MSG_ERROR, "Multi-AP: Failed to build Multi-AP IE"); - os_free(wpa_ie); + os_free_loose(wpa_ie); return NULL; } wpa_ie_len += multi_ap_ie_len; @@ -2934,13 +2938,13 @@ static void wpas_update_fils_connect_params(struct wpa_supplicant *wpa_s) return; if (params.auth_alg != WPA_AUTH_ALG_FILS) { - os_free(wpa_ie); + os_free_loose(wpa_ie); return; } wpa_s->auth_alg = params.auth_alg; wpa_drv_update_connect_params(wpa_s, ¶ms, mask); - os_free(wpa_ie); + os_free_loose(wpa_ie); } #endif /* CONFIG_FILS && IEEE8021X_EAPOL */ @@ -2968,7 +2972,7 @@ void wpas_update_mbo_connect_params(struct wpa_supplicant *wpa_s) return; wpa_drv_update_connect_params(wpa_s, ¶ms, WPA_DRV_UPDATE_ASSOC_IES); - os_free(wpa_ie); + os_free_loose(wpa_ie); } #endif /* CONFIG_MBO */ @@ -3293,7 +3297,7 @@ static void wpas_start_assoc_cb(struct wpa_radio_work *work, int deinit) if (wpas_p2p_handle_frequency_conflicts( wpa_s, params.freq.freq, ssid) < 0) { wpas_connect_work_done(wpa_s); - os_free(wpa_ie); + os_free_loose(wpa_ie); return; } } @@ -3313,7 +3317,7 @@ static void wpas_start_assoc_cb(struct wpa_radio_work *work, int deinit) } ret = wpa_drv_associate(wpa_s, ¶ms); - os_free(wpa_ie); + os_free_loose(wpa_ie); if (ret < 0) { wpa_msg(wpa_s, MSG_INFO, "Association request to the driver " "failed"); @@ -3748,7 +3752,7 @@ void wpa_supplicant_select_network(struct wpa_supplicant *wpa_s, * Don't optimize next scan freqs since a new ESS has been * selected. */ - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = NULL; } else { wpa_s->connect_without_scan = NULL; @@ -4883,7 +4887,7 @@ static void radio_work_free(struct wpa_radio_work *work) } dl_list_del(&work->list); - os_free(work); + os_free_loose(work); } @@ -5121,7 +5125,7 @@ static void radio_remove_interface(struct wpa_supplicant *wpa_s) wpa_printf(MSG_DEBUG, "Remove radio %s", radio->name); eloop_cancel_timeout(radio_start_next_work, radio, NULL); - os_free(radio); + os_free_loose(radio); } @@ -5367,19 +5371,19 @@ static int wpa_supplicant_init_iface(struct wpa_supplicant *wpa_s, * line. */ if (iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = os_strdup(iface->ctrl_interface); } if (iface->driver_param) { - os_free(wpa_s->conf->driver_param); + os_free_loose(wpa_s->conf->driver_param); wpa_s->conf->driver_param = os_strdup(iface->driver_param); } if (iface->p2p_mgmt && !iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = NULL; } #endif @@ -5397,19 +5401,19 @@ static int wpa_supplicant_init_iface(struct wpa_supplicant *wpa_s, * line. */ if (iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = os_strdup(iface->ctrl_interface); } if (iface->driver_param) { - os_free(wpa_s->conf->driver_param); + os_free_loose(wpa_s->conf->driver_param); wpa_s->conf->driver_param = os_strdup(iface->driver_param); } if (iface->p2p_mgmt && !iface->ctrl_interface) { - os_free(wpa_s->conf->ctrl_interface); + os_free_loose(wpa_s->conf->ctrl_interface); wpa_s->conf->ctrl_interface = NULL; } #endif @@ -5714,13 +5718,13 @@ static void wpa_supplicant_deinit_iface(struct wpa_supplicant *wpa_s, wpa_s->conf = NULL; } - os_free(wpa_s->ssids_from_scan_req); + os_free_loose(wpa_s->ssids_from_scan_req); #if !CFG_NEW_SUPP wpa_s->ssids_from_scan_req = 0; wpas_connect_ssid = 0; #endif - os_free(wpa_s); + os_free_loose(wpa_s); } @@ -5779,7 +5783,7 @@ static int wpa_supplicant_match_existing(struct wpa_global *global) iface = wpa_supplicant_match_iface(global, ifi->if_name); if (iface) { wpa_s = wpa_supplicant_add_iface(global, iface, NULL); - os_free(iface); + os_free_loose(iface); if (wpa_s) wpa_s->matched = 1; } @@ -5937,7 +5941,7 @@ int wpa_supplicant_remove_iface(struct wpa_global *global, #ifdef CONFIG_MESH if (mesh_if_created) { wpa_drv_if_remove(parent, WPA_IF_MESH, ifname); - os_free(ifname); + os_free_loose(ifname); } #endif /* CONFIG_MESH */ @@ -6216,7 +6220,7 @@ void wpa_supplicant_deinit(struct wpa_global *global) if(wpa_drivers[i]->global_deinit) wpa_drivers[i]->global_deinit(global->drv_priv[i]); } - os_free(global->drv_priv); + os_free_loose(global->drv_priv); random_deinit(); @@ -6225,27 +6229,27 @@ void wpa_supplicant_deinit(struct wpa_global *global) #ifdef CONFIG_FULL_SUPPLICANT if (global->params.pid_file) { os_daemonize_terminate(global->params.pid_file); - os_free(global->params.pid_file); + os_free_loose(global->params.pid_file); } - os_free(global->params.ctrl_interface); - os_free(global->params.ctrl_interface_group); - os_free(global->params.override_driver); - os_free(global->params.override_ctrl_interface); + os_free_loose(global->params.ctrl_interface); + os_free_loose(global->params.ctrl_interface_group); + os_free_loose(global->params.override_driver); + os_free_loose(global->params.override_ctrl_interface); #endif #ifdef CONFIG_MATCH_IFACE - os_free(global->params.match_ifaces); + os_free_loose(global->params.match_ifaces); #endif /* CONFIG_MATCH_IFACE */ #ifdef CONFIG_P2P - os_free(global->params.conf_p2p_dev); + os_free_loose(global->params.conf_p2p_dev); #endif /* CONFIG_P2P */ #ifdef CONFIG_P2P - os_free(global->p2p_disallow_freq.range); - os_free(global->p2p_go_avoid_freq.range); - os_free(global->add_psk); + os_free_loose(global->p2p_disallow_freq.range); + os_free_loose(global->p2p_go_avoid_freq.range); + os_free_loose(global->add_psk); #endif - os_free(global); + os_free_loose(global); wpa_debug_close_syslog(); wpa_debug_close_file(); wpa_debug_close_linux_tracing(); @@ -6318,7 +6322,7 @@ static int * get_bss_freqs_in_ess(struct wpa_supplicant *wpa_s) } if (num_freqs == 0) { - os_free(freqs); + os_free_loose(freqs); freqs = NULL; } @@ -6381,7 +6385,7 @@ void wpas_connection_failed(struct wpa_supplicant *wpa_s, const u8 *bssid) * used in this ESS based on previous scans to speed up * common load balancing use case. */ - os_free(wpa_s->next_scan_freqs); + os_free_loose(wpa_s->next_scan_freqs); wpa_s->next_scan_freqs = freqs; } } @@ -6796,7 +6800,7 @@ int get_shared_radio_freqs(struct wpa_supplicant *wpa_s, for (i = 0; i < num; i++) freq_array[i] = freqs_data[i].freq; - os_free(freqs_data); + os_free_loose(freqs_data); return num; } @@ -6933,7 +6937,7 @@ static int wpa_set_driver_tmp_disallow_list(struct wpa_supplicant *wpa_s) num_bssid++; } ret = wpa_drv_set_bssid_blacklist(wpa_s, num_bssid, bssids); - os_free(bssids); + os_free_loose(bssids); return ret; } @@ -6948,7 +6952,7 @@ static void wpa_bss_tmp_disallow_timeout(void *eloop_ctx, void *timeout_ctx) struct wpa_bss_tmp_disallowed, list) { if (bss == tmp) { dl_list_del(&tmp->list); - os_free(tmp); + os_free_loose(tmp); wpa_set_driver_tmp_disallow_list(wpa_s); break; } diff --git a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpas_glue.c b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpas_glue.c index 84319d6cd656a1aa9d4f8f0c295343ffed29f057..c2461cf099490b9325db14d03430e1aa200c5b35 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpas_glue.c +++ b/drivers/hal/beken/beken72XX_HAL/func/wpa_supplicant-2.9/wpa_supplicant/wpas_glue.c @@ -79,7 +79,7 @@ static int wpa_ether_send(struct wpa_supplicant *wpa_s, const u8 *dest, wpa_snprintf_hex(hex, hex_len, buf, len); wpa_msg(wpa_s, MSG_INFO, "EAPOL-TX " MACSTR " %s", MAC2STR(dest), hex); - os_free(hex); + os_free_loose(hex); return 0; } #endif /* CONFIG_TESTING_OPTIONS */ @@ -186,7 +186,7 @@ static int wpa_supplicant_eapol_send(void *ctx, int type, const u8 *buf, wpa_printf(MSG_DEBUG, "TX EAPOL: dst=" MACSTR, MAC2STR(dst)); wpa_hexdump(MSG_MSGDUMP, "TX EAPOL", msg, msglen); res = wpa_ether_send(wpa_s, dst, ETH_P_EAPOL, msg, msglen); - os_free(msg); + os_free_loose(msg); return res; } @@ -620,7 +620,7 @@ static int wpa_supplicant_send_ft_action(void *ctx, u8 action, ret = wpa_drv_send_action(wpa_s, wpa_s->assoc_freq, 0, wpa_s->bssid, wpa_s->own_addr, wpa_s->bssid, data, data_len, 0); - os_free(data); + os_free_loose(data); return ret; } @@ -858,7 +858,7 @@ void wpas_send_ctrl_req(struct wpa_supplicant *wpa_s, struct wpa_ssid *ssid, len = os_snprintf(buf, buflen, "%s-%d:%s needed for SSID ", field_name, ssid->id, txt); if (os_snprintf_error(buflen, len)) { - os_free(buf); + os_free_loose(buf); return; } if (ssid->ssid && buflen > len + ssid->ssid_len) { @@ -868,7 +868,7 @@ void wpas_send_ctrl_req(struct wpa_supplicant *wpa_s, struct wpa_ssid *ssid, } buf[buflen - 1] = '\0'; wpa_msg(wpa_s, MSG_INFO, WPA_CTRL_REQ "%s", buf); - os_free(buf); + os_free_loose(buf); } @@ -1038,7 +1038,7 @@ static void wpa_supplicant_set_anon_id(void *ctx, const u8 *id, size_t len) wpa_snprintf_hex(str, len * 2 + 1, id, len); res = wpa_config_set(wpa_s->current_ssid, "anonymous_identity", str, 0); - os_free(str); + os_free_loose(str); if (res < 0) return; } @@ -1097,7 +1097,7 @@ int wpa_supplicant_init_eapol(struct wpa_supplicant *wpa_s) ctx->cb_ctx = wpa_s; wpa_s->eapol = eapol_sm_init(ctx); if (wpa_s->eapol == NULL) { - os_free(ctx); + os_free_loose(ctx); wpa_printf(MSG_ERROR, "Failed to initialize EAPOL state " "machines."); return -1; @@ -1149,7 +1149,7 @@ static void wpa_supplicant_fils_hlp_rx(void *ctx, const u8 *dst, const u8 *src, wpa_snprintf_hex(hex, hexlen, pkt, pkt_len); wpa_msg(wpa_s, MSG_INFO, FILS_HLP_RX "dst=" MACSTR " src=" MACSTR " frame=%s", MAC2STR(dst), MAC2STR(src), hex); - os_free(hex); + os_free_loose(hex); } @@ -1219,7 +1219,7 @@ int wpa_supplicant_init_wpa(struct wpa_supplicant *wpa_s) if (wpa_s->wpa == NULL) { wpa_printf(MSG_ERROR, "Failed to initialize WPA state " "machine"); - os_free(ctx); + os_free_loose(ctx); return -1; } #endif /* CONFIG_NO_WPA */ diff --git a/drivers/hal/beken/beken72XX_HAL/ip/lmac/src/hal/hal_desc.h b/drivers/hal/beken/beken72XX_HAL/ip/lmac/src/hal/hal_desc.h index 2144ffcba6aace07167b4ac2f44c04bdbdd9d9dd..c8fd397c98cd77585509501e8b8a874bebcaba8d 100644 --- a/drivers/hal/beken/beken72XX_HAL/ip/lmac/src/hal/hal_desc.h +++ b/drivers/hal/beken/beken72XX_HAL/ip/lmac/src/hal/hal_desc.h @@ -21,6 +21,9 @@ * @ingroup HAL * @brief HW descriptor definitions * @{ + + 1 dma.h (E:\OneOS_Submodule\drivers\hal\beken\beken72XX_HAL\driver\dma) + 2 dma.h (E:\OneOS_Submodule\drivers\dma) ***************************************************************************************** */ @@ -36,7 +39,7 @@ // for mac frame definitions #include "mac_frame.h" // for dma_desc -#include "dma.h" +#include "..\..\..\..\driver\dma\dma.h" // for CO_BIT #include "co_math.h" // for co_list_hdr diff --git a/drivers/hal/beken/beken72XX_HAL/ip/weave.yaml b/drivers/hal/beken/beken72XX_HAL/ip/weave.yaml index 67153a57f67025d62619b987346dfc8976f1978f..3591c1aa0c8f74e3e6e3361dc6fdb17d098e7479 100644 --- a/drivers/hal/beken/beken72XX_HAL/ip/weave.yaml +++ b/drivers/hal/beken/beken72XX_HAL/ip/weave.yaml @@ -1,4 +1,118 @@ -# 子目录 -add_subdirectory: - - beken_usb_lib ? {(not is_define('CFG_SOC_NAME', SOC_BK7231N)) and (not is_define('CFG_USB', 0))} - - beken_usb ? {(not is_define('CFG_SOC_NAME', SOC_BK7231N)) and (not is_define('CFG_USB', 0))} \ No newline at end of file +# 组名 +group_name: beken_ip_lib + +# 依赖宏控 +depend_macro: + - BOARD_BK7231N + +# 编译连接信息 +build_option: + cpppath: + - common + - ke + - mac + - lmac/src/hal + - lmac/src/mm + - lmac/src/ps + - lmac/src/rd + - lmac/src/rx + - lmac/src/scan + - lmac/src/sta + - lmac/src/tx + - lmac/src/vif + - lmac/src/rx/rxl + - lmac/src/tx/txl + - lmac/src/rwnx + - lmac/src/p2p + - lmac/src/chan + - lmac/src/td + - lmac/src/tpc + - lmac/src/tdls + - umac/src/bam + - umac/src/llc + - umac/src/me + - umac/src/rxu + - umac/src/scanu + - umac/src/sm + - umac/src/txu + - umac/src/apm + - umac/src/rc + - umac/src/mesh + libs: + - libip_7231n_sta + libpath: + - . + cppdefines: + - . + +# 源码 +source_file: + - common/co_dlist.c + - common/co_list.c + - common/co_math.c + - common/co_pool.c + - common/co_ring.c + - ke/ke_env.c + - ke/ke_event.c + - ke/ke_msg.c + - ke/ke_queue.c + - ke/ke_task.c + - ke/ke_timer.c + - lmac/src/chan/chan.c + - lmac/src/hal/hal_desc.c + - lmac/src/hal/hal_dma.c + - lmac/src/hal/hal_machw.c + - lmac/src/hal/hal_mib.c + - lmac/src/mm/mm.c + - lmac/src/mm/mm_bcn.c + - lmac/src/mm/mm_task.c + - lmac/src/mm/mm_timer.c + - lmac/src/p2p/p2p.c + - lmac/src/ps/ps.c + - lmac/src/rd/rd.c + - lmac/src/rwnx/rwnx.c + - lmac/src/rx/rx_swdesc.c + - lmac/src/rx/rxl/rxl_cntrl.c + - lmac/src/rx/rxl/rxl_hwdesc.c + - lmac/src/scan/scan.c + - lmac/src/scan/scan_shared.c + - lmac/src/scan/scan_task.c + - lmac/src/sta/sta_mgmt.c + - lmac/src/td/td.c + - lmac/src/tdls/tdls.c + - lmac/src/tdls/tdls_task.c + - lmac/src/tpc/tpc.c + - lmac/src/tx/tx_swdesc.c + - lmac/src/tx/txl/txl_buffer.c + - lmac/src/tx/txl/txl_buffer_shared.c + - lmac/src/tx/txl/txl_cfm.c + - lmac/src/tx/txl/txl_cntrl.c + - lmac/src/tx/txl/txl_frame.c + - lmac/src/tx/txl/txl_frame_shared.c + - lmac/src/tx/txl/txl_hwdesc.c + - lmac/src/vif/vif_mgmt.c + - mac/mac.c + - mac/mac_ie.c + - umac/src/apm/apm.c + - umac/src/apm/apm_task.c + - umac/src/bam/bam.c + - umac/src/bam/bam_task.c + - umac/src/me/me.c + - umac/src/me/me_mgmtframe.c + - umac/src/me/me_mic.c + - umac/src/me/me_task.c + - umac/src/me/me_utils.c + - umac/src/rc/rc.c + - umac/src/rc/rc_basic.c + - umac/src/rxu/rxu_cntrl.c + - umac/src/scanu/scanu.c + - umac/src/scanu/scanu_shared.c + - umac/src/scanu/scanu_task.c + - umac/src/sm/sm.c + - umac/src/sm/sm_task.c + - umac/src/txu/txu_cntrl.c + +#静态库 + libs: + - xxx + libpath: \ No newline at end of file diff --git a/drivers/hal/beken/beken72XX_HAL/libbeken_sdk_gcc.a b/drivers/hal/beken/beken72XX_HAL/libbeken_sdk_gcc.a index ede8a24158fa78e913545e36fc578616efc300e0..ca1c7d9f74a5ed0df9a6251f519642a0ab454e0b 100644 Binary files a/drivers/hal/beken/beken72XX_HAL/libbeken_sdk_gcc.a and b/drivers/hal/beken/beken72XX_HAL/libbeken_sdk_gcc.a differ diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/ate/rtt_ate_app.c b/drivers/hal/beken/beken72XX_HAL/oneos/ate/rtt_ate_app.c index cc13833757501ff4b3c42f6f5db155149125750c..7fee2824d352070cbaa3d5136097649228be32f1 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/ate/rtt_ate_app.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/ate/rtt_ate_app.c @@ -8,7 +8,8 @@ #include "arm_arch.h" #include "uart.h" #include "os_task.h" -#include "os_device.h" +#include "device.h" + // #define ATE_USE_DEGUB @@ -64,7 +65,7 @@ void ate_gpio_init(void) return; } - os_task_delay(os_tick_from_ms(2)); + os_task_msleep(2); gpio_ctrl( CMD_GPIO_CFG, ¶m); } @@ -115,7 +116,7 @@ uint32_t ate_mode_check(void) void ate_app_init(void) { uint32_t mode = 0; - os_ubase_t level; + os_base_t level; level = os_hw_interrupt_disable(); diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/bk_oneos_clock.c b/drivers/hal/beken/beken72XX_HAL/oneos/bk_oneos_clock.c index d793ed2cff78e1b998a8078c924bc134a8483fb2..bc825c76e17a398a3eab7cf2345d664ab33b3987 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/bk_oneos_clock.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/bk_oneos_clock.c @@ -100,14 +100,10 @@ UINT32 rtt_update_tick(UINT32 tick) { if (tick) { - os_enter_critical(); - /* adjust OS tick */ os_tick_set_value(os_tick_get_value() + tick); /* check system timer */ os_timer_check(); - - os_exit_critical(); } } #endif diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/include/mem_pub.h b/drivers/hal/beken/beken72XX_HAL/oneos/include/mem_pub.h index 844da5df51d0283f964cead236526fa94fde1c18..5452762ea6b53f41f7c1bed1fadb96700b479d2a 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/include/mem_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/oneos/include/mem_pub.h @@ -5,12 +5,12 @@ #include // oneos adapte for beken driver -extern int32_t os_memcmp(const void *str1, const void *str2, os_size_t count); -extern void *os_memmove(void *dst, const void *src, os_size_t count); +extern int32_t os_memcmp(const void *area1, const void *area2, os_size_t count); +extern void *os_memmove(void *dst, const void *src, os_size_t count); extern void *os_memcpy(void *dst, const void *src, os_size_t count); extern void *os_memset(void *src, uint8_t val, os_size_t count); extern void *os_malloc(os_size_t nbytes); -extern void os_free(void *ptr); +extern void os_free_loose(void *ptr); extern void *os_realloc(void *ptr, os_size_t nbytes); // beken special function diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/include/rtos_pub.h b/drivers/hal/beken/beken72XX_HAL/oneos/include/rtos_pub.h index dbb22e2734efa6517c499f8c75d2e9dda216af83..d7cee94c6420ae3eaf3ba78acf40b37b7c24be0e 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/include/rtos_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/oneos/include/rtos_pub.h @@ -3,15 +3,38 @@ #include "include.h" #include "typedef.h" -#include "sys_rtos.h" -#include "error.h" - -#include "os_types.h" -#include "os_mailbox.h" +#include "os_mb.h" +#include "os_mq.h" #include "os_memory.h" #pragma once +#define RT_NULL (0) + +/* RT-Thread error code definitions */ +#define RT_EOK 0 /**< There is no error */ +#define RT_ERROR 1 /**< A generic error happens */ +#define RT_ETIMEOUT 2 /**< Timed out */ +#define RT_EFULL 3 /**< The resource is full */ +#define RT_EEMPTY 4 /**< The resource is empty */ +#define RT_ENOMEM 5 /**< No memory */ +#define RT_ENOSYS 6 /**< No system */ +#define RT_EBUSY 7 /**< Busy */ +#define RT_EIO 8 /**< IO error */ +#define RT_EINTR 9 /**< Interrupted system call */ +#define RT_EINVAL 10 /**< Invalid argument */ + +/** + * IPC flags and control command definitions + */ +#define RT_IPC_FLAG_FIFO 0x00 /**< FIFOed IPC. @ref IPC. */ +#define RT_IPC_FLAG_PRIO 0x01 /**< PRIOed IPC. @ref IPC. */ + +typedef long rt_base_t; /**< Nbit CPU related date type */ + +typedef rt_base_t rt_err_t; /**< Type for error number */ + + #define RTOS_SUCCESS (1) #define RTOS_FAILURE (0) @@ -44,25 +67,6 @@ // #define _xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction ) xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction ) #endif -/* -// adapte oneos types -#ifndef uint8_t -typedef uint8_t uint8_t; -#endif - -#ifndef uint16_t -typedef uint16_t uint16_t; -#endif - -#ifndef uint32_t -typedef uint32_t uint32_t; -#endif - -#ifndef uint64_t -typedef uint64_t uint64_t; -#endif -*/ - typedef int OSStatus; typedef void (*timer_handler_t)( void*); typedef OSStatus (*event_handler_t)( void* arg ); @@ -76,18 +80,8 @@ typedef uint32_t beken_event_flags_t; typedef void * beken_semaphore_t; typedef void * beken_mutex_t; typedef void * beken_thread_t; -//typedef void * beken_queue_t; typedef void * beken_event_t; // OS event: beken_semaphore_t, beken_mutex_t or beken_queue_t -struct beken_queue -{ - os_mailbox_id handle; - os_mp_t* mp; - uint32_t message_size; - uint32_t number_of_messages; -}; -typedef struct beken_queue* beken_queue_t; - typedef enum { WAIT_FOR_ANY_EVENT, @@ -101,6 +95,28 @@ typedef struct void * arg; }beken_timer_t; +/** + * message queue structure + */ +struct rt_messagequeue +{ + os_msgqueue_dummy_t os_mq; + os_bool_t is_static; + void *start_addr; +}; +typedef struct rt_messagequeue *rt_mq_t; +typedef struct rt_messagequeue *beken_queue_t; + +/** + * Semaphore structure + */ +struct rt_semaphore +{ + os_semaphore_dummy_t os_sem; + os_bool_t is_static; +}; +typedef struct rt_semaphore *rt_sem_t; + typedef struct { beken_thread_t thread; @@ -132,11 +148,20 @@ typedef void (*beken_thread_function_t)( beken_thread_arg_t arg ); extern beken_worker_thread_t beken_hardware_io_worker_thread; extern beken_worker_thread_t beken_worker_thread; - +/** @brief Enter a critical session, all interrupts are disabled + * + * @return none + */ +void rtos_enter_critical( void ); OSStatus beken_time_get_time(beken_time_t* time_ptr); OSStatus beken_time_set_time(beken_time_t* time_ptr); +void rtos_exit_critical( void ); + +/** + * @} + */ /** @defgroup BEKEN_RTOS_Thread _BK_ RTOS Thread Management Functions * @brief Provide thread creation, delete, suspend, resume, and other RTOS management API @@ -186,6 +211,29 @@ OSStatus rtos_create_thread( beken_thread_t* thread, uint8_t priority, const cha */ OSStatus rtos_delete_thread( beken_thread_t* thread ); +/** @brief Creates a worker thread + * + * Creates a worker thread + * A worker thread is a thread in whose context timed and asynchronous events + * execute. + * + * @param worker_thread : a pointer to the worker thread to be created + * @param priority : thread priority + * @param stack_size : thread's stack size in number of bytes + * @param event_queue_size : number of events can be pushed into the queue + * + * @return kNoErr : on success. + * @return kGeneralErr : if an error occurred + */ + + +/** @brief Deletes a worker thread + * + * @param worker_thread : a pointer to the worker thread to be created + * + * @return kNoErr : on success. + * @return kGeneralErr : if an error occurred + */ /** @brief Suspend a thread @@ -197,6 +245,24 @@ OSStatus rtos_delete_thread( beken_thread_t* thread ); */ void rtos_suspend_thread(beken_thread_t* thread); + + +/** @brief Suspend all other thread + * + * @param none + * + * @return none + */ + + +/** @brief Rresume all other thread + * + * @param none + * + * @return none + */ + + /** @brief Sleeps until another thread has terminated * * @Details Causes the current thread to sleep until the specified other thread @@ -239,7 +305,7 @@ BOOL rtos_is_current_thread( beken_thread_t* thread ); /** @brief Get current thread handler * - * @return Current BK RTOS thread handler + * @return Current RTOS thread handler */ beken_thread_t* rtos_get_current_thread( void ); @@ -268,7 +334,13 @@ void rtos_thread_msleep(uint32_t milliseconds); OSStatus rtos_delay_milliseconds( uint32_t num_ms ); - +/** @brief Print Thread status into buffer + * + * @param buffer, point to buffer to store thread status + * @param length, length of the buffer + * + * @return none + */ /** * @} @@ -287,8 +359,8 @@ OSStatus rtos_delay_milliseconds( uint32_t num_ms ); * @return kNoErr : on success. * @return kGeneralErr : if an error occurred */ -OSStatus rtos_init_semaphore( beken_semaphore_t* semaphore, int maxCount ); -OSStatus rtos_init_semaphore_ex( beken_semaphore_t* semaphore, const char *name, int maxCount, int initCount ); +OSStatus rtos_init_semaphore( beken_semaphore_t *semaphore, int maxCount ); +OSStatus rtos_init_semaphore_ex( beken_semaphore_t *semaphore, const char *name, int maxCount, int initCount ); /** @brief Set (post/put/increment) a semaphore @@ -298,7 +370,7 @@ OSStatus rtos_init_semaphore_ex( beken_semaphore_t* semaphore, const char *name, * @return kNoErr : on success. * @return kGeneralErr : if an error occurred */ -OSStatus rtos_set_semaphore( beken_semaphore_t* semaphore ); +OSStatus rtos_set_semaphore( beken_semaphore_t *semaphore ); /** @brief Get (wait/decrement) a semaphore @@ -313,8 +385,8 @@ OSStatus rtos_set_semaphore( beken_semaphore_t* semaphore ); * @return kNoErr : on success. * @return kGeneralErr : if an error occurred */ -OSStatus rtos_get_semaphore( beken_semaphore_t* semaphore, uint32_t timeout_ms ); -int rtos_get_sema_count( beken_semaphore_t* semaphore ); +OSStatus rtos_get_semaphore( beken_semaphore_t *semaphore, uint32_t timeout_ms ); +int rtos_get_sema_count( beken_semaphore_t *semaphore ); /** @brief De-initialise a semaphore @@ -326,7 +398,7 @@ int rtos_get_sema_count( beken_semaphore_t* semaphore ); * @return kNoErr : on success. * @return kGeneralErr : if an error occurred */ -OSStatus rtos_deinit_semaphore( beken_semaphore_t* semaphore ); +OSStatus rtos_deinit_semaphore( beken_semaphore_t *semaphore ); /** * @} */ @@ -471,7 +543,58 @@ BOOL rtos_is_queue_full( beken_queue_t* queue ); * @} */ -/** @defgroup BEKEN_RTOS_TIMER MICO RTOS Timer Functions + +/** @defgroup BEKEN_RTOS_EVENT _BK_ RTOS Event Functions + * @{ + */ + +/** + * @brief Sends an asynchronous event to the associated worker thread + * + * @param worker_thread :the worker thread in which context the callback should execute from + * @param function : the callback function to be called from the worker thread + * @param arg : the argument to be passed to the callback function + * + * @return kNoErr : on success. + * @return kGeneralErr : if an error occurred + */ + +/** Requests a function be called at a regular interval + * + * This function registers a function that will be called at a regular + * interval. Since this is based on the RTOS time-slice scheduling, the + * accuracy is not high, and is affected by processor load. + * + * @param event_object : pointer to a event handle which will be initialised + * @param worker_thread : pointer to the worker thread in whose context the + * callback function runs on + * @param function : the callback function that is to be called regularly + * @param time_ms : the time period between function calls in milliseconds + * @param arg : an argument that will be supplied to the function when + * it is called + * + * @return kNoErr : on success. + * @return kGeneralErr : if an error occurred + */ + + +/** Removes a request for a regular function execution + * + * This function de-registers a function that has previously been set-up + * with @ref rtos_register_timed_event. + * + * @param event_object : the event handle used with @ref rtos_register_timed_event + * + * @return kNoErr : on success. + * @return kGeneralErr : if an error occurred + */ + + +/** + * @} + */ + +/** @defgroup BEKEN_RTOS_TIMER _BK_ RTOS Timer Functions * @brief Provide management APIs for timer such as init,start,stop,reload and dinit. * @{ */ @@ -564,13 +687,37 @@ OSStatus rtos_reload_timer( beken_timer_t* timer ); */ OSStatus rtos_deinit_timer( beken_timer_t* timer ); + +/** @brief Check if an RTOS timer is running + * + * @param timer : a pointer to the RTOS timer handle + * + * @return true : if running. + * @return false : if not running + */ BOOL rtos_is_timer_running( beken_timer_t* timer ); +/** @brief Initialize an endpoint for a RTOS event, a file descriptor + * will be created, can be used for select + * + * @param event_handle : beken_semaphore_t, beken_mutex_t or beken_queue_t + * + * @retval On success, a file descriptor for RTOS event is returned. + * On error, -1 is returned. + */ + +/** @brief De-initialise an endpoint created from a RTOS event + * + * @param fd : file descriptor for RTOS event + * + * @retval 0 for success. On error, -1 is returned. + */ + /** * @} */ - +void os_free_loose(void *ptr); uint32_t rtos_get_free_mem(); #endif // __RTOS_PUB__ diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/include/str_pub.h b/drivers/hal/beken/beken72XX_HAL/oneos/include/str_pub.h index 430dc4a2c31ca6134243f06eb354e71a4c37ea81..4eb02080416cde0edc873a025577e873de575caa 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/include/str_pub.h +++ b/drivers/hal/beken/beken72XX_HAL/oneos/include/str_pub.h @@ -2,30 +2,35 @@ #define _STR_PUB_H_ #include -#include -#include "typedef.h" - -/* Adpt oneos string functions for beken drivers. */ - -extern os_size_t os_strlen(const char *str); -extern int32_t os_strcmp(const char *str1, const char *str2); -extern int32_t os_strncmp(const char *str1, const char *str2, os_size_t count); -extern int32_t os_snprintf(char *buf, os_size_t size, const char *fmt, ...); -extern int32_t os_vsnprintf(char *buf, os_size_t size, const char *fmt, va_list args); -extern char *os_strncpy(char *dst, const char *src, os_size_t count); -extern char *os_strcpy(char *dst, const char *src); -extern char *os_strchr(const char *str, char ch); -extern char *os_strstr(const char *str1, const char *str2); - -#ifdef OS_USING_HEAP -extern char *os_strdup(const char *str); -#endif /* OS_USING_HEAP */ - -// beken special functions + +os_size_t os_strlen(const char *str); + +INT32 os_strcmp(const char *s1, const char *s2); + +int32_t os_strncmp(const char *str1, const char *str2, os_size_t count); + +int32_t os_snprintf(char *buf, os_size_t size, const char *fmt, ...); + +int32_t os_vsnprintf(char *buf, os_size_t size, const char *fmt, va_list args); + +char *os_strncpy(char *dst, const char *src, os_size_t count); + UINT32 os_strtoul(const char *nptr, char **endptr, int base); + +char *os_strcpy(char *dst, const char *src); + +char *os_strchr(const char *s, int c); + +char *os_strdup(const char *s); + int os_strcasecmp(const char *s1, const char *s2); + int os_strncasecmp(const char *s1, const char *s2, size_t n); + char *os_strrchr(const char *s, int c); + +char *os_strstr(const char *haystack, const char *needle); + size_t os_strlcpy(char *dest, const char *src, size_t siz); #endif // _STR_PUB_H_ diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/include/sys_rtos.h b/drivers/hal/beken/beken72XX_HAL/oneos/include/sys_rtos.h index 25e4fdef1dc7340016ed813a9ae7f9d2e052d5e7..dc9362a92cab4ebfd891b0b70c3f11ac5e61c9e1 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/include/sys_rtos.h +++ b/drivers/hal/beken/beken72XX_HAL/oneos/include/sys_rtos.h @@ -2,7 +2,6 @@ #define __RTOS_H__ #include -#include #include #endif diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/mem_arch.c b/drivers/hal/beken/beken72XX_HAL/oneos/mem_arch.c index 01b01ebc548681e9387854ab59e927933373693b..c5c977928532ce09212a74deda973153e48d32eb 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/mem_arch.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/mem_arch.c @@ -26,8 +26,14 @@ #include extern void *os_malloc(os_size_t nbytes); -extern void *os_memset(void *src, uint8_t val, os_size_t count); -extern int32_t os_memcmp(const void *str1, const void *str2, os_size_t count); +void *os_memset(void *b, int c, UINT32 len) +{ + return (void *)memset(b, c, (unsigned int)len); +} +void *os_memcpy(void *out, const void *in, UINT32 n) +{ + return memcpy(out, in, n); +} #if (CFG_SUPPORT_RTT) && (CFG_SOC_NAME == SOC_BK7221U) @@ -46,9 +52,66 @@ void * os_zalloc(size_t size) return n; } +uint32_t os_memcmp(const void *area1, const void *area2, os_size_t count) +{ + const uint8_t *area1_tmp; + const uint8_t *area2_tmp; + uint32_t ret; + + area1_tmp = (const uint8_t *)area1; + area2_tmp = (const uint8_t *)area2; + ret = 0; + + for ( ; count > 0; area1_tmp++, area2_tmp++, count--) + { + ret = *area1_tmp - *area2_tmp; + if (ret != 0) + { + break; + } + } + + return ret; +} + int os_memcmp_const(const void *a, const void *b, size_t len) { return os_memcmp(a, b, len); } +void *os_memmove(void *dst, const void *src, os_size_t count) +{ + char *dst_tmp; + const char *src_tmp; + + dst_tmp = (char *)dst; + src_tmp = (const char *)src; + + /* Copy backwards */ + if ((dst_tmp > src_tmp) && (dst_tmp < src_tmp + count)) + { + dst_tmp += count; + src_tmp += count; + + while (count--) + { + dst_tmp--; + src_tmp--; + *dst_tmp = *src_tmp; + } + } + /* Copy forwards */ + else + { + while (count--) + { + *dst_tmp = *src_tmp; + dst_tmp++; + src_tmp++; + } + } + + return dst; +} + // EOF diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_pub.c b/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_pub.c index 8fa4c397b91c5a9916c0d30b3e174a978fd508c5..dbe5cfab9c82028c9f8f5c164a0534bef0f4bc2d 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_pub.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_pub.c @@ -32,20 +32,33 @@ #include "os_sem.h" #include "os_mutex.h" #include +#include "os_timer.h" +#include "os_assert.h" #define THREAD_TIMESLICE 5 #define RTOS_DEBUG 0 #if RTOS_DEBUG -#define RTOS_DBG(...) os_kprintf("[RTOS]"),os_kprintf(__VA_ARGS__) +#define RTOS_DBG(...) os_printf("[RTOS]"),os_printf(__VA_ARGS__) #else #define RTOS_DBG(...) #endif +os_mutex_id bk_mutex_dynamic = OS_NULL; + /****************************************************** * Function Definitions ******************************************************/ + +void bk_mutex_init(void) +{ + if (bk_mutex_dynamic == OS_NULL) + { + bk_mutex_dynamic = os_mutex_create(OS_NULL, "mutex_dynamic", OS_TRUE); + } +} + OSStatus rtos_create_thread( beken_thread_t* thread, uint8_t priority, const char* name, beken_thread_function_t function, uint32_t stack_size, beken_thread_arg_t arg ) { @@ -54,8 +67,9 @@ OSStatus rtos_create_thread( beken_thread_t* thread, uint8_t priority, const cha RTOS_DBG("can not create null thread\n"); return kGeneralErr; } - - *thread = os_task_create(name, function, arg, stack_size, priority, THREAD_TIMESLICE); + + *thread = os_task_create(OS_NULL, OS_NULL, stack_size, name, function, arg, priority); + if(*thread != OS_NULL) { os_task_startup(*thread); @@ -65,18 +79,19 @@ OSStatus rtos_create_thread( beken_thread_t* thread, uint8_t priority, const cha os_kprintf("create thread fail\n"); RTOS_DBG("create thread fail\n"); + return kGeneralErr; } RTOS_DBG("create thread %s\n", name); - + return kNoErr; } OSStatus rtos_delete_thread( beken_thread_t* thread ) { if(thread != OS_NULL) - { + { os_task_destroy(*thread); } else @@ -93,85 +108,148 @@ OSStatus rtos_delete_thread( beken_thread_t* thread ) void rtos_thread_sleep(uint32_t seconds) { - os_task_delay(os_tick_from_ms(seconds * 1000)); + os_task_msleep(seconds * 1000); } -static uint32_t rtos_sem_cnt = 0; -static uint32_t rtos_mutex_cnt = 0; - -OSStatus rtos_init_semaphore( beken_semaphore_t* semaphore, int maxCount ) +rt_sem_t rt_sem_create(const char *name, uint32_t value, uint8_t flag) { - *semaphore = os_semaphore_create(OS_NULL, "rtos_sem", 0, 1); - RTOS_DBG("rtos_init_semaphore:%8x\n", *semaphore); - rtos_sem_cnt++; + rt_sem_t sem; + os_err_t ret; - return (*semaphore != OS_NULL) ? kNoErr : kGeneralErr; + OS_ASSERT(value < OS_SEM_MAX_VALUE); + + sem = (rt_sem_t)os_malloc(sizeof(struct rt_semaphore)); + if (OS_NULL == sem) + { + return RT_NULL; + } + + if (OS_NULL == os_semaphore_create(&sem->os_sem, name, (uint16_t)value, OS_SEM_MAX_VALUE)) + { + os_free(sem); + return RT_NULL; + } + + if (RT_IPC_FLAG_PRIO == flag) + { + ret = os_semaphore_set_wake_type(&sem->os_sem, OS_SEM_WAKE_TYPE_PRIO); + } + else + { + ret = os_semaphore_set_wake_type(&sem->os_sem, OS_SEM_WAKE_TYPE_FIFO); + } + if (OS_SUCCESS != ret) + { + return RT_NULL; + } + + sem->is_static = OS_FALSE; + + return sem; } -OSStatus rtos_init_semaphore_ex( beken_semaphore_t* semaphore, const char *name, int maxCount, int initCount ) +rt_err_t rt_sem_delete(rt_sem_t sem) { - *semaphore = os_semaphore_create(OS_NULL, name, initCount, 1); - RTOS_DBG("rtos_init_semaphore_ex:%s %8x\n", name, *semaphore); - rtos_sem_cnt++; + os_err_t ret; + OS_ASSERT(sem); + OS_ASSERT(OS_FALSE == sem->is_static); - return (*semaphore != OS_NULL) ? kNoErr : kGeneralErr; + ret = os_semaphore_destroy(&sem->os_sem); + os_free(sem); + if (OS_SUCCESS != ret) + { + return -RT_ERROR; + } + + return RT_EOK; } -OSStatus rtos_get_semaphore(beken_semaphore_t* semaphore, uint32_t timeout_ms ) +rt_err_t rt_sem_take(rt_sem_t sem, int32_t time) { - os_err_t result; + os_tick_t timeout; + os_err_t ret; - result = os_semaphore_wait(*semaphore, os_tick_from_ms(timeout_ms)); + OS_ASSERT(sem); - if(result == OS_SUCCESS) + /*For OneOS,only support -1 for timeout,so set timeout is -1 when timeout is less than zero*/ + if (time < 0) { - return kNoErr; + timeout = OS_WAIT_FOREVER; + } + else if (0 == time) + { + timeout = OS_NO_WAIT; } else { - struct os_object *object = (struct os_object *)(*semaphore); - RTOS_DBG("%s take semaphore failed %d \n", object->name, result); - return kTimeoutErr; + timeout = (os_tick_t)time; + } + + ret = os_semaphore_wait(&sem->os_sem, timeout); + if (OS_SUCCESS != ret) + { + if (OS_BUSY == ret || OS_TIMEOUT == ret) + { + return -RT_ETIMEOUT; + } + + return -RT_ERROR; } + + return RT_EOK; } -int rtos_get_sema_count(beken_semaphore_t* semaphore ) +rt_err_t rt_sem_trytake(rt_sem_t sem) { - RTOS_DBG("rtos_get_sema_count\n"); - os_semaphore_id sem = *semaphore; - - return sem->count; + return rt_sem_take(sem, 0); } - -int rtos_set_semaphore( beken_semaphore_t* semaphore) +rt_err_t rt_sem_release(rt_sem_t sem) { - os_err_t result; + OS_ASSERT(sem); - result = os_semaphore_post(*semaphore); - if(result != OS_SUCCESS) + if (OS_SUCCESS != os_semaphore_post(&sem->os_sem)) { - RTOS_DBG("release semaphore failed %d \n", result); - return kGeneralErr; + return -RT_ERROR; } + return RT_EOK; +} + +OSStatus rtos_init_semaphore( beken_semaphore_t *semaphore, int maxCount ) +{ + *semaphore = (struct rt_semaphore *) rt_sem_create("rtos_sem", 0, OS_NULL); - return kNoErr; + return (*semaphore != OS_NULL) ? kNoErr : kGeneralErr; } -OSStatus rtos_deinit_semaphore(beken_semaphore_t *semaphore ) +OSStatus rtos_init_semaphore_ex( beken_semaphore_t *semaphore, const char *name, int maxCount, int initCount ) { - RTOS_DBG("rtos_deinit_semaphore:%8x\n", *semaphore); - if(semaphore != OS_NULL) - { - RTOS_DBG("rtos_deinit_sucess:%8x\n"); - os_sem_destroy(*semaphore); - rtos_sem_cnt--; - *semaphore = OS_NULL; - return kNoErr; + *semaphore = (struct rt_semaphore *) rt_sem_create(name, initCount, OS_NULL); - } + return (*semaphore != OS_NULL) ? kNoErr : kGeneralErr; +} - return kGeneralErr; +OSStatus rtos_get_semaphore(beken_semaphore_t *semaphore, uint32_t timeout_ms ) +{ + return rt_sem_take((struct rt_semaphore *)*semaphore, timeout_ms); +} + +int rtos_get_sema_count(beken_semaphore_t *semaphore ) +{ + RTOS_DBG("rtos_get_sema_count\n"); + os_semaphore_id sem = *semaphore; + + return sem->count_dummy; +} + +int rtos_set_semaphore( beken_semaphore_t *semaphore) +{ + return rt_sem_release((struct rt_semaphore *)*semaphore); +} + +OSStatus rtos_deinit_semaphore(beken_semaphore_t *semaphore ) +{ + return rt_sem_delete((struct rt_semaphore *)*semaphore); } OSStatus rtos_init_mutex( beken_mutex_t* mutex ) @@ -179,20 +257,20 @@ OSStatus rtos_init_mutex( beken_mutex_t* mutex ) RTOS_DBG("rtos_init_mutex\n"); /* Mutex uses priority inheritance */ - *mutex = os_mutex_create("rtos_mutex", OS_IPC_FLAG_PRIO,OS_FALSE); + *mutex = os_mutex_create(OS_NULL, "rtos_mutex",OS_FALSE); + if ( *mutex == OS_NULL ) { return kGeneralErr; } - rtos_mutex_cnt++; - return kNoErr; } OSStatus rtos_lock_mutex( beken_mutex_t* mutex) { RTOS_DBG("rtos_lock_mutex\n"); + os_mutex_lock(*mutex, BEKEN_WAIT_FOREVER); return OS_SUCCESS; @@ -201,6 +279,7 @@ OSStatus rtos_lock_mutex( beken_mutex_t* mutex) OSStatus rtos_unlock_mutex( beken_mutex_t* mutex) { RTOS_DBG("rtos_unlock_mutex\n"); + os_mutex_unlock(*mutex); return OS_SUCCESS; @@ -211,195 +290,214 @@ OSStatus rtos_deinit_mutex( beken_mutex_t* mutex) if(*mutex != OS_NULL) { os_mutex_destroy(*mutex); - rtos_mutex_cnt--; + *mutex = OS_NULL; } return OS_SUCCESS; } -OSStatus rtos_init_queue(beken_queue_t* queue, const char* name, uint32_t message_size, uint32_t number_of_messages) +rt_mq_t rt_mq_create(const char *name, os_size_t msg_size, os_size_t max_msgs, uint8_t flag) { - beken_queue_t mq = OS_NULL; + rt_mq_t mq; + os_size_t pool_size; + os_size_t align_msg_size; + void *msgpool; - mq = os_malloc(sizeof(struct beken_queue)); - if(OS_NULL == mq) - return kGeneralErr; - - os_memset(mq, 0, sizeof(struct beken_queue)); - *queue = mq; + OS_ASSERT(msg_size >= OS_ALIGN_SIZE); + OS_ASSERT(max_msgs > 0); - RTOS_DBG("rtos_init_queue!\r\n"); - mq->handle = os_mailbox_create_dynamic("rtos_queue", number_of_messages); - if (mq->handle == OS_NULL) - { - RTOS_DBG("rt_mailbox_create: 0x%08X!\r\n", mq->handle); - goto _exit; - } - RTOS_DBG("mq->handle:%08p!\r\n", mq->handle); - RTOS_DBG("rt_mp_create!\r\n"); - mq->mp = os_mp_create("rtos_queue", number_of_messages, message_size); - if (mq->mp == OS_NULL) - { - RTOS_DBG("rt_mempool_create: 0x%08X!\r\n", mq->mp); - goto _exit; - } - - RTOS_DBG("rt_mp_create done!\r\n"); - - mq->message_size = message_size; - mq->number_of_messages = number_of_messages; + mq = (rt_mq_t)os_malloc(sizeof(struct rt_messagequeue)); + if (OS_NULL == mq) + { + return RT_NULL; + } - return kNoErr; + align_msg_size = OS_ALIGN_UP(msg_size, OS_ALIGN_SIZE); + pool_size = max_msgs * (align_msg_size + sizeof(dummy_mq_msg_t)); -_exit: - if(mq->handle != OS_NULL) + msgpool = os_malloc(pool_size); + if (OS_NULL == msgpool) { - os_mailbox_destroy(mq->handle); - mq->handle = OS_NULL; + os_free(mq); + return RT_NULL; } - if(mq->mp != OS_NULL) + if (OS_NULL == os_msgqueue_create_static(&mq->os_mq, name, msgpool, pool_size, msg_size)) { - os_mp_destroy(mq->mp); - mq->mp = OS_NULL; + os_free(msgpool); + os_free(mq); + + return RT_NULL; } - - if(mq != OS_NULL) - { - os_free(mq); - mq = OS_NULL; - } - return kGeneralErr; + + mq->is_static = OS_FALSE; + mq->start_addr = msgpool; + + return mq; } -OSStatus rtos_push_to_queue(beken_queue_t* queue, void* message, UINT32 timeout_ms) +rt_err_t rt_mq_delete(rt_mq_t mq) { os_err_t ret; - void *msg_tmp = OS_NULL; - beken_queue_t mq = *queue; - msg_tmp = os_mp_alloc(mq->mp, os_tick_from_ms(timeout_ms)); - if(msg_tmp) - { - os_memcpy(msg_tmp, message, mq->message_size); - ret = os_mailbox_send(mq->handle, (UINT32)msg_tmp, os_tick_from_ms(timeout_ms)); - if(ret != OS_SUCCESS) - { - RTOS_DBG("%s rt_mailbox_send_wait ret:%d!\r\n", __FUNCTION__, ret); - return kGeneralErr; - } - } - else - { - RTOS_DBG("%s rt_mp_alloc failed! queue->message_size: %d\r\n", __FUNCTION__, mq->message_size); - return kGeneralErr; - } + OS_ASSERT(mq); + OS_ASSERT(OS_FALSE == mq->is_static); + OS_ASSERT(mq->start_addr); - return kNoErr; + ret = os_msgqueue_destroy(&mq->os_mq); + os_free(mq->start_addr); + os_free(mq); + if (OS_SUCCESS != ret) + { + return -RT_ERROR; + } + return RT_EOK; } -OSStatus rtos_push_to_queue_front(beken_queue_t* queue, void* message, uint32_t timeout_ms) +rt_err_t rt_mq_send(rt_mq_t mq, void *buffer, os_size_t size) { - beken_queue_t mq = *queue; - - os_kprintf("\nrtos_push_to_queue_front not implement!!!\n"); + os_err_t ret; - return kGeneralErr; + OS_ASSERT(mq); + OS_ASSERT(buffer); + OS_ASSERT(size); + + ret = os_msgqueue_send(&mq->os_mq, buffer, size, OS_NO_WAIT); + if (OS_SUCCESS != ret) + { + if (OS_FULL == ret) + { + return -RT_EFULL; + } + + return RT_ERROR; + } + + return RT_EOK; } -OSStatus rtos_pop_from_queue(beken_queue_t* queue, void* message, uint32_t timeout_ms) +rt_err_t rt_mq_urgent(rt_mq_t mq, void *buffer, os_size_t size) { - void *msg_tmp = OS_NULL; - beken_queue_t mq = *queue; - os_err_t result; + os_err_t ret; - result = os_mailbox_recv(mq->handle, (uint32_t *)&msg_tmp, os_tick_from_ms(timeout_ms)); - if(result != OS_SUCCESS) - { - RTOS_DBG("%s rt_mailbox_recv ret:%d, ms:=%d!\r\n", __FUNCTION__, result, os_tick_from_ms(timeout_ms)); - RTOS_DBG("mq->handle:0x%08p!\r\n", mq->handle); - return kGeneralErr; - } + OS_ASSERT(mq); + OS_ASSERT(buffer); + OS_ASSERT(size); - if(msg_tmp) - { - os_memcpy(message, msg_tmp, mq->message_size); - os_mp_free(msg_tmp); - } - else - { - RTOS_DBG("%s rt_mailbox_recv item:0x%08X!\r\n", __FUNCTION__, msg_tmp); - return kGeneralErr; - } + ret = os_msgqueue_send_urgent(&mq->os_mq, buffer, size, OS_NO_WAIT); + if (OS_SUCCESS != ret) + { + if (OS_FULL == ret) + { + return -RT_EFULL; + } + + return RT_ERROR; + } - return kNoErr; + return RT_EOK; } -OSStatus rtos_deinit_queue(beken_queue_t* queue) +rt_err_t rt_mq_recv(rt_mq_t mq, void *buffer, os_size_t size, int32_t timeout) { - beken_queue_t mq = *queue; + os_size_t recv_size; + os_tick_t timeout_tmp; + os_err_t ret; + OS_ASSERT(mq); + OS_ASSERT(buffer); + OS_ASSERT(size); - if(mq->handle != OS_NULL) + /*For OneOS,only support -1 for timeout,so set timeout is -1 when timeout is less than zero*/ + if (timeout < 0) + { + timeout_tmp = OS_WAIT_FOREVER; + } + else if (0 == timeout) + { + timeout_tmp = OS_NO_WAIT; + } + else { - os_mailbox_destroy(mq->handle); - mq->handle =OS_NULL; + timeout_tmp = (os_tick_t)timeout; } - if(mq->mp != OS_NULL) + ret = os_msgqueue_recv(&mq->os_mq, buffer, size, timeout_tmp, &recv_size); + if (OS_SUCCESS != ret) { - os_mp_destroy(mq->mp); - mq->mp = OS_NULL; + if (OS_EMPTY == ret || OS_TIMEOUT == ret) + { + return -RT_ETIMEOUT; + } + + return -RT_ERROR; } - mq->message_size = 0; - mq->number_of_messages = 0; + return RT_EOK; +} + +OSStatus rtos_init_queue(beken_queue_t *queue, const char* name, uint32_t message_size, uint32_t number_of_messages) +{ + *queue = rt_mq_create(name, message_size, number_of_messages, OS_NULL); - os_free(mq); - mq = OS_NULL; return kNoErr; } -BOOL rtos_is_queue_empty(beken_queue_t* queue ) +OSStatus rtos_push_to_queue(beken_queue_t *queue, void* message, UINT32 timeout_ms) +{ + beken_queue_t mq = *queue; + return rt_mq_send(mq, message, mq->os_mq.max_msg_size_dummy); +} + +OSStatus rtos_push_to_queue_front(beken_queue_t* queue, void* message, uint32_t timeout_ms) +{ + beken_queue_t mq = *queue; + + os_kprintf("\nrtos_push_to_queue_front not implement!!!\n"); + + return kGeneralErr; +} + +OSStatus rtos_pop_from_queue(beken_queue_t* queue, void* message, uint32_t timeout_ms) +{ + beken_queue_t mq = *queue; + return rt_mq_recv(mq, message, mq->os_mq.max_msg_size_dummy, os_tick_from_ms(timeout_ms)); +} + +OSStatus rtos_deinit_queue(beken_queue_t *queue) +{ + beken_queue_t mq = *queue; + return rt_mq_delete(mq); +} + +BOOL rtos_is_queue_empty(beken_queue_t *queue ) { - uint32_t level; beken_queue_t mq = *queue; - os_enter_critical(); - if(mq->handle->entry == 0) + if(mq->os_mq.used_msgs_dummy == 0) { - os_exit_critical(); - return true; } - - os_exit_critical(); return false; } BOOL rtos_is_queue_full(beken_queue_t* queue) { - uint32_t level; beken_queue_t mq = *queue; - os_enter_critical(); - if(mq->handle->entry == mq->handle->size) + if(mq->os_mq.queue_depth_dummy == 0) { - os_exit_critical(); - return true; } - os_exit_critical(); - return false; } OSStatus rtos_delay_milliseconds( uint32_t num_ms) { - os_task_delay(os_tick_from_ms(num_ms)); + os_task_msleep(num_ms); } static void timer_oneshot_callback(void* parameter) @@ -424,9 +522,9 @@ OSStatus rtos_start_oneshot_timer( beken2_timer_t* timer) if(timer->handle != OS_NULL) { - os_timer_start(timer->handle); + os_timer_start(timer->handle); return OS_SUCCESS; - } + } return OS_FAILURE; } @@ -452,10 +550,10 @@ BOOL rtos_is_oneshot_timer_init(beken2_timer_t* timer) BOOL rtos_is_oneshot_timer_running(beken2_timer_t* timer) { - os_timer_t *os_timer = (os_timer_t *)(timer->handle); + os_timer_id *os_timer = (os_timer_id *)(timer->handle); RTOS_DBG("oneshot_timer is runing \n"); - return os_timer->parent.flag & OS_TIMER_FLAG_ACTIVATED ? true : false; + return os_timer_is_active(*os_timer); } OSStatus rtos_oneshot_reload_timer( beken2_timer_t* timer) @@ -489,26 +587,27 @@ OSStatus rtos_init_oneshot_timer( beken2_timer_t *timer, timer->right_arg = rarg; timer->beken_magic = BEKEN_MAGIC_WORD; - timer->handle = os_timer_create("rtos_oneshot_time", + timer->handle = os_timer_create(OS_NULL, + "rtos_oneshot_time", timer_oneshot_callback, timer, os_tick_from_ms(time_ms), - OS_TIMER_FLAG_ONE_SHOT|OS_TIMER_FLAG_SOFT_TIMER); + OS_TIMER_FLAG_ONE_SHOT); + if ( timer->handle == NULL ) { ret = kGeneralErr; } else { - //((os_timer_t*)(timer->handle))->user_timer = timer; RTOS_DBG("create oneshot_timer %x\n",timer->handle); } - + return ret; } -void rtos_deinit_free_beken_timer(os_timer_t *t) +void rtos_deinit_free_beken_timer(os_timer_id t) { /* ((beken2_timer_t *)(t->user_timer))->handle = 0; @@ -522,14 +621,15 @@ void rtos_deinit_free_beken_timer(os_timer_t *t) OSStatus rtos_deinit_oneshot_timer( beken2_timer_t* timer ) { OSStatus ret = kNoErr; - register os_ubase_t level; + RTOS_DBG("delete oneshot_timer %x\n",timer->handle); /* disable interrupt */ - level = os_hw_interrupt_disable(); - os_timer_t *os_timer = (os_timer_t*)(timer->handle); - - if(os_timer_destroy((os_timer_t*)timer->handle) != OS_SUCCESS) + //os_ubase_t level = os_irq_lock(); + + os_timer_id *os_timer = (os_timer_id*)(timer->handle); + + if(os_timer_destroy(*(os_timer_id*)timer->handle) != OS_SUCCESS) { ret = OS_FAILURE; } @@ -542,8 +642,8 @@ OSStatus rtos_deinit_oneshot_timer( beken2_timer_t* timer ) timer->beken_magic = 0; } /* enable interrupt */ - os_hw_interrupt_enable(level); - + //os_irq_unlock(level); + return ret; } @@ -592,10 +692,10 @@ BOOL rtos_is_timer_init(beken_timer_t* timer) BOOL rtos_is_timer_running(beken_timer_t* timer) { - os_timer_t *os_timer = (os_timer_t*)(timer->handle); + os_timer_id os_timer = (os_timer_id)(timer->handle); RTOS_DBG("period_timer is runing \n"); - return os_timer->parent.flag & OS_TIMER_FLAG_ACTIVATED ? true : false; + return os_timer_is_active(os_timer); } OSStatus rtos_reload_timer( beken_timer_t* timer) @@ -610,7 +710,6 @@ OSStatus rtos_reload_timer( beken_timer_t* timer) else { os_timer_start(timer->handle); - // os_kprintf("timer is stop, start timer \r\n"); } return kNoErr; } @@ -620,7 +719,7 @@ OSStatus rtos_change_period( beken_timer_t* timer, uint32_t time_ms) uint32_t timeout_value; timeout_value = os_tick_from_ms(time_ms); - os_timer_control(timer->handle, OS_TIMER_CTRL_SET_TIME, (void *)&timeout_value); + os_timer_start(timer->handle); return kNoErr; @@ -634,11 +733,13 @@ OSStatus rtos_init_timer( beken_timer_t* timer, uint32_t time_ms, timer_handler_ timer->function = function; timer->arg = arg; - timer->handle = os_timer_create("rtos_period_time", + timer->handle = os_timer_create(OS_NULL, + "rtos_period_time", timer_period_callback, timer, os_tick_from_ms(time_ms), - OS_TIMER_FLAG_PERIODIC|OS_TIMER_FLAG_SOFT_TIMER); + OS_TIMER_FLAG_PERIODIC); + if ( timer->handle == NULL ) { ret = kNoErr; @@ -647,7 +748,7 @@ OSStatus rtos_init_timer( beken_timer_t* timer, uint32_t time_ms, timer_handler_ { //((os_timer_t*)(timer->handle))->user_timer = timer; } - + return ret; } @@ -659,11 +760,13 @@ OSStatus rtos_init_timer_ex( beken_timer_t* timer, const char* name, uint32_t ti timer->function = function; timer->arg = arg; - timer->handle = os_timer_create(name, + timer->handle = os_timer_create(OS_NULL, + name, timer_period_callback, timer, os_tick_from_ms(time_ms), - OS_TIMER_FLAG_PERIODIC|OS_TIMER_FLAG_SOFT_TIMER); + OS_TIMER_FLAG_PERIODIC); + if ( timer->handle == NULL ) { ret = kNoErr; @@ -672,7 +775,7 @@ OSStatus rtos_init_timer_ex( beken_timer_t* timer, const char* name, uint32_t ti { //((rt_timer_t)(timer->handle))->user_timer = timer; } - + return ret; } @@ -681,7 +784,7 @@ OSStatus rtos_deinit_timer( beken_timer_t* timer ) OSStatus ret = kNoErr; RTOS_DBG("delete period_timer \n"); - if(os_timer_destroy((os_timer_t*)timer->handle) != OS_SUCCESS) + if(os_timer_destroy((os_timer_id)timer->handle) != OS_SUCCESS) { ret = kGeneralErr; } @@ -708,14 +811,48 @@ uint32_t rtos_get_time(void) } uint32_t rtos_get_free_mem() { -#ifdef OS_USING_HEAP - uint32_t total; - uint32_t used; - os_memory_info(&total, &used, NULL); + return 0; +} - return total - used; -#else +os_ubase_t rt_hw_interrupt_disable(void) +{ return 0; -#endif +} + +void rt_hw_interrupt_enable(os_ubase_t level) +{ + return; +} + +struct rt_hw_register +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t fp; + uint32_t ip; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t spsr; + uint32_t cpsr; +}; + +#include "start_type_pub.h" + +void os_free_loose(void *ptr) +{ + if(ptr) + { + os_free(ptr); + } } diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_task.c b/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_task.c index 1ea422ed100da97ec07066c3f9f5f8722742414e..64a22057cdc595a949670db76dac83bb20eaa48f 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_task.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/source/rtos_task.c @@ -1,5 +1,5 @@ /** - * RTOS + * RTOS测试用例 */ #include "sys_rtos.h" @@ -23,13 +23,13 @@ /** - * Ϣв + * 消息队列测试 */ static beken_queue_t mq; static beken_thread_t queue_thread_revive; static beken_thread_t queue_thread_send; -#define MSG_SIZE 12 /* Ϣ */ -#define MSG_NUM 10 /* Ϣ */ +#define MSG_SIZE 12 /* 消息长度 */ +#define MSG_NUM 10 /* 消息数量 */ static beken_semaphore_t sem; static beken_semaphore_t sem_send; @@ -37,38 +37,36 @@ static beken_semaphore_t sem_recv; static beken_mutex_t mutex; - -//OSStatus rtos_init_mutex( beken_mutex_t* mutex ) - - - static void thread_queue_recive_entry(void* parameter) { uint8_t buf[MSG_SIZE]; while(1) { - rtos_get_semaphore(&sem,200); - //rtos_get_semaphore(&sem_send,1000); - //rtos_lock_mutex(&mutex); - os_kprintf("recive 1111 thread test!!!\n"); + if(rtos_get_semaphore(&sem,200)) + os_kprintf("get sem timeout 111\r\n"); + if(rtos_get_semaphore(&sem_send,1000)) + os_kprintf("get sem timeout 222\r\n"); + + rtos_lock_mutex(&mutex); + os_kprintf("recive 1111 thread test!!!\r\n"); os_memset(&buf[0], 0 , sizeof(buf)); if(rtos_pop_from_queue(&mq, &buf[0], 100) == kNoErr) { - os_kprintf("recive thread:recive msg = %s\n", &buf); + os_kprintf("recive thread:recive msg = %s\r\n", &buf); } else { - os_kprintf("recive thread:failed\n"); + os_kprintf("recive thread:failed\r\n"); } - os_kprintf("recive 2222 thread test!!!\n"); + os_kprintf("recive 2222 thread test!!!\r\n"); rtos_delay_milliseconds(100); - //rtos_unlock_mutex(&mutex); - //rtos_set_semaphore(&sem_recv); + rtos_unlock_mutex(&mutex); + rtos_set_semaphore(&sem_recv); rtos_set_semaphore(&sem); } } @@ -79,10 +77,12 @@ static void thread_queue_send_entry(void* parameter) while(1) { - rtos_get_semaphore(&sem,200); - //rtos_get_semaphore(&sem_recv,1000); - //rtos_lock_mutex(&mutex); - os_kprintf("send 1111 thread test!!!\n"); + if(rtos_get_semaphore(&sem,200)) + os_kprintf("get sem timeout 333\r\n"); + if(rtos_get_semaphore(&sem_recv,1000)) + os_kprintf("get sem timeout 444\r\n"); + rtos_lock_mutex(&mutex); + os_kprintf("send 1111 thread test!!!\r\n"); os_memset(&buf[0], 0 , sizeof(buf)); for(int i = 0; i < MSG_SIZE - 1; i++) @@ -91,37 +91,38 @@ static void thread_queue_send_entry(void* parameter) } if(!rtos_is_queue_full(&mq)) { - os_kprintf("send thread:%s\n", &buf[0]); + os_kprintf("send thread:%s\r\n", &buf[0]); rtos_push_to_queue(&mq, &buf[0], 0); } else { - os_kprintf("send thread: queue full\n"); + os_kprintf("send thread: queue full\r\n"); rtos_delay_milliseconds(100); return; } - os_kprintf("send 2222 thread test!!!\n"); + os_kprintf("send 2222 thread test!!!\r\n"); os_memset(&buf[0], 0 , sizeof(buf)); - - //rtos_unlock_mutex(&mutex); - //rtos_set_semaphore(&sem_send); + + rtos_delay_milliseconds(100); + + rtos_unlock_mutex(&mutex); + rtos_set_semaphore(&sem_send); rtos_set_semaphore(&sem); } } int msg_queue_simple_init(void) -{ - +{ uint8_t buf[MSG_SIZE]; os_err_t result; - /* ʼϢ */ + /* 初始化消息队?*/ result = rtos_init_queue(&mq, "msg_queue", MSG_SIZE, MSG_NUM); if(result != kNoErr) { - os_kprintf("init rtos queue failed\n"); + os_kprintf("init rtos queue failed\r\n"); } rtos_init_semaphore_ex(&sem,"sem",1,1); @@ -130,10 +131,10 @@ int msg_queue_simple_init(void) rtos_init_mutex(&mutex); - /* recive߳ */ + /* 创建recive线程 */ rtos_create_thread(&queue_thread_revive,3, "recv_thread", thread_queue_recive_entry, 1024, OS_NULL); - /* send߳ */ + /* 创建send线程 */ rtos_create_thread(&queue_thread_send, 4, "send_thread", thread_queue_send_entry, 1024, OS_NULL); } @@ -141,7 +142,7 @@ SH_CMD_EXPORT(msg_queue_simple_init,msg_queue_simple_init,"msq queue simple"); /** - * ʱ + * 定时器测? */ // static beken_thread_t one_shot_tim; static beken2_timer_t one_shot; diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/str_arch.c b/drivers/hal/beken/beken72XX_HAL/oneos/str_arch.c index 4c81c22343522c00a4929df87073d978375017d8..435a41d995fd7f2d07a686f3358d1e6f520c1ea1 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/str_arch.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/str_arch.c @@ -31,10 +31,6 @@ #include "str_pub.h" #include "mem_pub.h" - -extern int32_t os_strcmp(const char *str1, const char *str2); -extern int32_t os_strncmp(const char *str1, const char *str2, os_size_t count); - #define _U 0x01 /* upper */ #define _L 0x02 /* lower */ #define _D 0x04 /* digit */ @@ -207,5 +203,135 @@ char *os_strrchr(const char *s, int c) return strrchr(s, c); } +INT32 os_strcmp(const char *s1, const char *s2) +{ + uint8_t value1; + uint8_t value2; + + for ( ; *s1 == *s2; s1++, s2++) + { + if (*s1 == '\0') + { + return 0; + } + } + + value1 = *((const uint8_t *)s1); + value2 = *((const uint8_t *)s2); + + return (value1 - value2); +} + +int32_t os_strncmp(const char *str1, const char *str2, os_size_t count) +{ + uint8_t value1; + uint8_t value2; + + for ( ; count > 0; str1++, str2++, count--) + { + if (*str1 != *str2) + { + value1 = *((const uint8_t *)str1); + value2 = *((const uint8_t *)str2); + + return (value1 - value2); + } + else if (*str1 == '\0') + { + return 0; + } + } + + return 0; +} + +char *os_strncpy(char *dst, const char *src, os_size_t count) +{ + char *dst_tmp; + + for (dst_tmp = dst; (count > 0) && (*src != '\0'); count--) + { + *dst_tmp = *src; + dst_tmp++; + src++; + } + + for ( ; count > 0; count--) + { + *dst_tmp = '\0'; + dst_tmp++; + } + + return dst; +} + +char *os_strcpy(char *dst, const char *src) +{ + char *dst_tmp; + + dst_tmp = dst; + while (1) + { + *dst_tmp = *src; + if (*dst_tmp != '\0') + { + dst_tmp++; + src++; + } + else + { + break; + } + } + + return dst; +} + +os_size_t os_strlen(const char *str) +{ + const char *str_tmp; + + for (str_tmp = str; *str_tmp != '\0'; str_tmp++) + { + ; + } + + return (str_tmp - str); +} + +/** + *********************************************************************************************************************** + * @brief This function will duplicate a string. + * + * @param[in] str The string to be duplicated + * + * @return The duplicated string pointer. + * @retval OS_NULL Duplicate string failed. + * @retval else Duplicate string success. + *********************************************************************************************************************** + */ +char *os_strdup(const char *str) +{ + os_size_t len; + char *str_tmp; + + len = os_strlen(str) + 1; + str_tmp = (char *)os_malloc(len); + if (!str_tmp) + { + return OS_NULL; + } + + os_memcpy(str_tmp, str, len); + + return str_tmp; +} + +EXPORT_SYMBOL(os_strdup); +#if defined(__CC_ARM) || defined(__CLANG_ARM) +char *strdup(const char *s) __attribute__((alias("os_strdup"))); +#endif + + // EOF diff --git a/drivers/hal/beken/beken72XX_HAL/oneos/target_util.c b/drivers/hal/beken/beken72XX_HAL/oneos/target_util.c index d27905d3076e6f1691238ed5d0adde5af58f2c66..5c8de9316d696807d5fe33f7c7d587df65c546f8 100644 --- a/drivers/hal/beken/beken72XX_HAL/oneos/target_util.c +++ b/drivers/hal/beken/beken72XX_HAL/oneos/target_util.c @@ -27,12 +27,6 @@ #include "target_util_pub.h" #include - -extern os_err_t os_task_delay(os_tick_t tick); -extern os_tick_t os_tick_from_ms(uint32_t ms); - - - /******************************************************************************* * Function Implemantation *******************************************************************************/ @@ -57,7 +51,7 @@ void delay(INT32 num) */ void delay_ms(UINT32 ms_count) { - os_task_delay(os_tick_from_ms(ms_count)); + os_task_msleep(ms_count); } /* @@ -65,7 +59,7 @@ void delay_ms(UINT32 ms_count) */ void delay_sec(UINT32 ms_count) { - os_task_delay(os_tick_from_ms(ms_count * 1000)); + os_task_msleep(ms_count * 1000); } /* @@ -73,7 +67,7 @@ void delay_sec(UINT32 ms_count) */ void delay_tick(UINT32 tick_count) { - os_task_delay(tick_count); + os_task_tsleep(tick_count); } // EOF diff --git a/drivers/hal/beken/beken72XX_HAL/release/release.h b/drivers/hal/beken/beken72XX_HAL/release/release.h new file mode 100644 index 0000000000000000000000000000000000000000..20ac5d1b88a27d99ff86622f79d3f23224cd2fc4 --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/release/release.h @@ -0,0 +1,11 @@ +#ifndef _RELEASE_H_ +#define _RELEASE_H_ + +#include "sdk_revision.h" + +#define IP_11N_LIB_REV "4.3.3" /* The SW revision of IP 11n lib */ +#define BLE_4X_LIB_REV "4.2.1" /* The SW revision of BLE4.x lib */ +#define BLE_5X_LIB_REV "5.1.4" /* The SW revision of BLE5.x lib */ +#define USB_2X_LIB_REV "2.1.1" /* The SW revision of USB2.x lib */ + +#endif diff --git a/drivers/hal/beken/beken72XX_HAL/release/sdk_revision.h b/drivers/hal/beken/beken72XX_HAL/release/sdk_revision.h new file mode 100644 index 0000000000000000000000000000000000000000..de747fd0c7095ce8b034226faa69c184b4299142 --- /dev/null +++ b/drivers/hal/beken/beken72XX_HAL/release/sdk_revision.h @@ -0,0 +1 @@ +#define BEKEN_SDK_REV "3.0.7" diff --git a/drivers/hal/beken/beken72XX_HAL/weave.yaml b/drivers/hal/beken/beken72XX_HAL/weave.yaml index e2a105b8bcbf51c09d411f893b41d01b1c07863e..c8760fa1c32f15885217a88bb54f06fa7845d0d8 100644 --- a/drivers/hal/beken/beken72XX_HAL/weave.yaml +++ b/drivers/hal/beken/beken72XX_HAL/weave.yaml @@ -1,3 +1,302 @@ -# 子目录 -add_subdirectory: - - beken_sdk ? {is_define("SOC_FAMILY_BK72XX")} \ No newline at end of file +# 组名 +group_name: hal/beken_sdk + +# 依赖宏控 +depend_macro: + - BOARD_BK7231N + +# 编译连接信息 +build_option: + cpppath: + - oneos/include + - oneos/source + - oneos/ate + - ip/common + - ip/ke + - ip/mac + - ip/lmac/src/hal + - ip/lmac/src/mm + - ip/lmac/src/ps + - ip/lmac/src/rd + - ip/lmac/src/rx + - ip/lmac/src/scan + - ip/lmac/src/sta + - ip/lmac/src/tx + - ip/lmac/src/vif + - ip/lmac/src/rx/rxl + - ip/lmac/src/tx/txl + - ip/lmac/src/rwnx + - ip/lmac/src/p2p + - ip/lmac/src/chan + - ip/lmac/src/td + - ip/lmac/src/tpc + - ip/lmac/src/tdls + - ip/umac/src/bam + - ip/umac/src/llc + - ip/umac/src/me + - ip/umac/src/rxu + - ip/umac/src/scanu + - ip/umac/src/sm + - ip/umac/src/txu + - ip/umac/src/apm + - ip/umac/src/rc + - ip/umac/src/mesh + - func + - func/include + - func/rf_test + - func/joint_up + - func/temp_detect + - func/user_driver + - func/power_save + - func/ethernet_intf + - func/uart_debug + - func/ip/umac/src/apm + - func/rwnx_intf + - func/wpa_supplicant-2.9/src + - func/wpa_supplicant-2.9/bk_patch + - func/wpa_supplicant-2.9/hostapd + - func/wpa_supplicant-2.9/src/utils + - func/wpa_supplicant-2.9/src/drivers + - func/wpa_supplicant-2.9/src/common + - func/wpa_supplicant-2.9/src/common/ + - func/vad + - func/spidma_intf + - func/camera_intf + - func/video_transfer + - func/voice_transfer + - func/lwip_intf/dhcpd + - func/rf_use + - func/ble_wifi_exchange + - func/saradc_intf + - func/sensor + - driver/calendar + - driver/include + - func/wpa_supplicant-2.9 + - ../drivers/wlan/ + - app + - app/config + - app/standalone-ap + - app/standalone-station + - app/led + - app/app_demo + - common + - release + - demo + - driver/audio + - driver/codec + - driver/common + - driver/common/reg + - driver/dma + - driver/entry + - driver/fft + - driver/flash + - driver/general_dma + - driver/gpio + - driver/i2s + - driver/icu + - driver/include + - driver/intc + - driver/irda + - driver/macphy_bypass + - driver/phy + - driver/pwm + - driver/rc_beken + - driver/saradc + - driver/sdcard + - driver/sdio + - driver/spi + - driver/spidma + - driver/sys_ctrl + - driver/uart + - driver/wdt + - driver/rw_pub + - driver/jpeg + - driver/i2c + - driver/security + - driver/dma + - func/sdio_intf + libs: + - libip_7231n_sta + - libble_7231n + libpath: + - ip + - driver/ble_5_x_rw + cppdefines: + - CFG_SUPPORT_RTT + - ETHARP_SUPPORT_STATIC_ENTRIES + +# 源码 +source_file: + - driver/calendar/calendar.c + - driver/audio/ring_buffer_dma_write.c +# - driver/codec/driver_codec_es8374.c + - driver/common/dd.c + - driver/common/drv_model.c + - driver/dma/dma.c + - driver/entry/arch_main.c + - driver/fft/fft.c + - driver/flash/flash.c + - driver/general_dma/general_dma.c + - driver/gpio/gpio.c + - driver/i2s/i2s.c + - driver/icu/icu.c + - driver/intc/intc.c + - driver/irda/irda.c + - driver/macphy_bypass/mac_phy_bypass.c + - driver/phy/phy_trident.c + - driver/pwm/pwm.c + - driver/pwm/pwm_new.c + - driver/pwm/mcu_ps_timer.c + - driver/pwm/bk_timer.c + - driver/saradc/saradc.c + - driver/sdcard/sdcard.c + - driver/sdcard/sdio_driver.c + - driver/spi/spi.c + - driver/spidma/spidma.c + - driver/spi/spi_master.c + - driver/spi/spi_psram.c + - driver/spi/spi_flash.c + - driver/spi/spi_slave.c + - driver/jpeg/jpeg_encoder.c + - driver/i2c/i2c1.c + - driver/i2c/i2c2.c + - driver/sys_ctrl/sys_ctrl.c + - driver/uart/Retarget.c + - driver/uart/uart.c + - driver/wdt/wdt.c + - driver/rw_pub/rw_platf_pub.c + - driver/driver.c + - driver/qspi/qspi.c + - oneos/source/rtos_pub.c + - oneos/source/port.c + - oneos/source/port_asm.S + - oneos/source/rtos_task.c + - oneos/mem_arch.c + - oneos/bk_oneos_clock.c + - oneos/str_arch.c + - oneos/target_util.c + - oneos/ate/rtt_ate_app.c + - func/saradc_intf/saradc_intf.c + - app/config/param_config.c + - app/app.c + - app/standalone-ap/sa_ap.c + - app/standalone-station/sa_station.c + - demo/ieee802_11_demo.c + - func/func.c + - func/audio/audio_intf.c + - func/power_save/power_save.c + - func/power_save/mcu_ps.c + - func/power_save/manual_ps.c + - func/power_save/ap_idle.c + - func/rwnx_intf/rw_msg_rx.c + - func/net_param_intf/net_param.c + - func/misc/pseudo_random.c + - func/misc/start_type.c + - func/joint_up/role_launch.c + - func/bk7011_cal/bk7231_cal.c + - func/bk7011_cal/bk7231U_cal.c + - func/bk7011_cal/bk7231N_cal.c + - func/bk7011_cal/bk7221U_cal.c + - func/bk7011_cal/manual_cal_bk7231.c + - func/bk7011_cal/manual_cal_bk7231U.c + - func/ble_wifi_exchange/ble_wifi_port.c + - func/temp_detect/temp_detect.c + - func/rwnx_intf/rw_ieee80211.c + - func/rwnx_intf/rw_msdu.c + - func/rwnx_intf/rw_msg_tx.c + - func/rf_test/tx_evm.c + - func/rf_test/rx_sensitivity.c + - func/uart_debug/cmd_rx_sensitivity.c + - func/uart_debug/cmd_evm.c + - func/uart_debug/command_line.c + - func/user_driver/BkDriverFlash.c + - func/wlan_ui/wlan_ui.c + - func/hostapd_intf/hostapd_intf.c + - func/user_driver/BkDriverPwm.c + - func/user_driver/BkDriverQspi.c + - func/wpa_supplicant-2.9/wpa_supplicant/op_classes.c + - func/wpa_supplicant-2.9/bk_patch/ddrv.c + - func/wpa_supplicant-2.9/bk_patch/signal.c + - func/wpa_supplicant-2.9/bk_patch/sk_intf.c + - func/wpa_supplicant-2.9/bk_patch/fake_socket.c + - func/wpa_supplicant-2.9/hostapd/main_none.c + - func/wpa_supplicant-2.9/src/ap/ap_config.c + - func/wpa_supplicant-2.9/src/ap/ap_drv_ops.c + - func/wpa_supplicant-2.9/src/ap/ap_list.c + - func/wpa_supplicant-2.9/src/ap/ap_mlme.c +# - func/wpa_supplicant-2.9/src/ap/authsrv.c + - func/wpa_supplicant-2.9/src/ap/beacon.c +# - func/wpa_supplicant-2.9/src/ap/bss_load.c +# - func/wpa_supplicant-2.9/src/ap/dfs.c + - func/wpa_supplicant-2.9/src/ap/drv_callbacks.c +# - func/wpa_supplicant-2.9/src/ap/eap_user_db.c + - func/wpa_supplicant-2.9/src/ap/hostapd.c + - func/wpa_supplicant-2.9/src/ap/hw_features.c + - func/wpa_supplicant-2.9/src/ap/ieee802_11_auth.c + - func/wpa_supplicant-2.9/src/ap/ieee802_11.c + - func/wpa_supplicant-2.9/src/ap/ieee802_11_ht.c + - func/wpa_supplicant-2.9/src/ap/ieee802_11_shared.c + - func/wpa_supplicant-2.9/src/ap/ieee802_1x.c + - func/wpa_supplicant-2.9/src/ap/pmksa_cache_auth.c + - func/wpa_supplicant-2.9/src/ap/sta_info.c + - func/wpa_supplicant-2.9/src/ap/tkip_countermeasures.c + - func/wpa_supplicant-2.9/src/ap/utils.c + - func/wpa_supplicant-2.9/src/ap/wmm.c + - func/wpa_supplicant-2.9/src/ap/wpa_auth.c + - func/wpa_supplicant-2.9/src/ap/wpa_auth_glue.c + - func/wpa_supplicant-2.9/src/ap/wpa_auth_ie.c + - func/wpa_supplicant-2.9/src/common/hw_features_common.c + - func/wpa_supplicant-2.9/src/common/ieee802_11_common.c + - func/wpa_supplicant-2.9/src/common/wpa_common.c + - func/wpa_supplicant-2.9/src/crypto/aes-internal.c + - func/wpa_supplicant-2.9/src/crypto/aes-internal-dec.c + - func/wpa_supplicant-2.9/src/crypto/aes-internal-enc.c + - func/wpa_supplicant-2.9/src/crypto/aes-unwrap.c + - func/wpa_supplicant-2.9/src/crypto/aes-wrap.c + - func/wpa_supplicant-2.9/src/crypto/md5.c + - func/wpa_supplicant-2.9/src/crypto/md5-internal.c + - func/wpa_supplicant-2.9/src/crypto/rc4.c + - func/wpa_supplicant-2.9/src/crypto/sha1.c + - func/wpa_supplicant-2.9/src/crypto/sha1-internal.c + - func/wpa_supplicant-2.9/src/crypto/sha1-pbkdf2.c + - func/wpa_supplicant-2.9/src/crypto/sha1-prf.c + - func/wpa_supplicant-2.9/src/crypto/tls_none.c + - func/wpa_supplicant-2.9/src/drivers/driver_beken.c + - func/wpa_supplicant-2.9/src/drivers/driver_common.c + - func/wpa_supplicant-2.9/src/drivers/drivers.c +# - func/wpa_supplicant-2.9/src/eap_common/eap_common.c +# - func/wpa_supplicant-2.9/src/eapol_auth/eapol_auth_sm.c +# - func/wpa_supplicant-2.9/src/eap_server/eap_server.c +# - func/wpa_supplicant-2.9/src/eap_server/eap_server_methods.c + - func/wpa_supplicant-2.9/src/l2_packet/l2_packet_none.c +# - func/wpa_supplicant-2.9/src/rsn_supp/preauth.c + - func/wpa_supplicant-2.9/src/rsn_supp/wpa.c + - func/wpa_supplicant-2.9/src/rsn_supp/wpa_ie.c + - func/wpa_supplicant-2.9/src/utils/common.c + - func/wpa_supplicant-2.9/src/utils/eloop.c + - func/wpa_supplicant-2.9/src/utils/os_none.c + - func/wpa_supplicant-2.9/src/utils/wpabuf.c + - func/wpa_supplicant-2.9/src/utils/wpa_debug.c + - func/wpa_supplicant-2.9/wpa_supplicant/blacklist.c + - func/wpa_supplicant-2.9/wpa_supplicant/bss.c + - func/wpa_supplicant-2.9/wpa_supplicant/config.c + - func/wpa_supplicant-2.9/wpa_supplicant/config_none.c + - func/wpa_supplicant-2.9/wpa_supplicant/events.c + - func/wpa_supplicant-2.9/wpa_supplicant/main_supplicant.c + - func/wpa_supplicant-2.9/wpa_supplicant/notify.c + - func/wpa_supplicant-2.9/wpa_supplicant/wmm_ac.c + - func/wpa_supplicant-2.9/wpa_supplicant/wpa_scan.c + - func/wpa_supplicant-2.9/wpa_supplicant/wpas_glue.c + - func/wpa_supplicant-2.9/wpa_supplicant/wpa_supplicant.c + - func/spidma_intf/spidma_intf.c + - func/camera_intf/camera_intf.c + - func/video_transfer/video_transfer.c + - func/video_transfer/video_buffer.c +# - func/voice_transfer/voice_transfer.c + - func/lwip_intf/dhcpd/dhcp-server.c + - func/lwip_intf/dhcpd/dhcp-server-main.c +# - func/vad/vad.c +# - func/vad/vad_core.c +# - func/vad/wb_vad.c + - func/rf_use/arbitrate.c + - func/wpa_supplicant-2.9/src/common/wpa_psk_cache.c \ No newline at end of file diff --git a/drivers/hal/beken/drivers/Kconfig b/drivers/hal/beken/drivers/Kconfig index c074d3ac00bcda7d49628da51037a54d0e8e1dbf..05c4d2a74c7759561299c60e75150f31e95f463c 100644 --- a/drivers/hal/beken/drivers/Kconfig +++ b/drivers/hal/beken/drivers/Kconfig @@ -6,23 +6,35 @@ config BEKEN_DRV_DEBUG config BEKEN_USING_UART1 bool "Using UART 1" - select RT_USING_SERIAL - default n + select OS_USING_SERIAL + select OS_SOFT_DMA_SUPPORT_CIRCLE_MODE + default y + + if BEKEN_USING_UART1 + config BEKEN_UART1_BAUD + int "uart1 baud rate" + default 1000000 + endif config BEKEN_USING_UART2 bool "Using UART 2" - select RT_USING_SERIAL + select OS_USING_SERIAL default n + if BEKEN_USING_UART2 + config BEKEN_UART2_BAUD + int "uart2 baud rate" + default 115200 + endif config BEKEN_USING_WDT bool "Using WDT" - select RT_USING_WDT + select OS_USING_WDT default n config BEKEN_USING_IIC bool "Using IIC" - select RT_USING_I2C - select RT_USING_I2C_BITOPS + select OS_USING_I2C + select OS_USING_I2C_BITOPS default n config BEKEN_USING_FLASH @@ -35,12 +47,12 @@ config BEKEN_USING_PWM config BEKEN_USING_GPIO bool "Using GPIO" - select RT_USING_PIN + select OS_USING_PIN default n config BEKEN_USING_WLAN bool "Using Wi-Fi" - select RT_USING_WIFI + select OS_USING_WIFI default n if BEKEN_USING_WLAN @@ -48,15 +60,27 @@ config BEKEN_USING_WLAN int default 1 - config BEKEN_USING_WLAN_STA + config BSP_USING_BK_STA bool "Enable Station" - select RT_USING_WLAN_STA + select OS_USING_WLAN_STA default y - - config BEKEN_USING_WLAN_AP + + if BSP_USING_BK_STA + config OS_WLAN_DEVICE_STA_NAME + string "station device name" + default "w0" + endif + + config BSP_USING_BK_AP bool "Enable Soft_AP" - select RT_USING_WLAN_AP + select OS_USING_WLAN_AP default n + + if BSP_USING_BK_AP + config OS_WLAN_DEVICE_AP_NAME + string "ap device name" + default "ap" + endif config OS_WLAN_PROT_LWIP_PBUF_FORCE bool "Enable Beken wifi using pbuf" @@ -69,21 +93,21 @@ config BEKEN_USING_AUDIO config BEKEN_USING_SPI bool "Using SPI" - select RT_USING_SPI + select OS_USING_SPI default n if BEKEN_USING_SPI config BEKEN_USING_SPI_FLASH bool "Using SPI Flash" - select RT_USING_SFUD + select OS_USING_SFUD default n endif -config RT_USING_CPU_FFS +config OS_USING_CPU_FFS bool "Using CPU FFS" default n -config RT_MAIN_THREAD_STACK_SIZE +config OS_MAIN_THREAD_STACK_SIZE int "Set main thread stack size" default 2048 diff --git a/drivers/hal/beken/drivers/audio/weave.yaml b/drivers/hal/beken/drivers/audio/weave.yaml index 15f4fcdd3ef13b1398a354d8fd714a2d43d95974..33144f5dafd794bf3016919e50dcba472e280bb3 100644 --- a/drivers/hal/beken/drivers/audio/weave.yaml +++ b/drivers/hal/beken/drivers/audio/weave.yaml @@ -3,15 +3,18 @@ group_name: drv_audio # 依赖宏控 depend_macro: - - RT_USING_AUDIO + - BEKEN_USING_AUDIO # 编译连接信息 build_option: cpppath: - . - - + # 源码 source_file: - - ./*.c - - ./*.S \ No newline at end of file + - audio.c ? {is_define("BEKEN_USING_AUDIO")} + - audio_adc.c ? {is_define("BEKEN_USING_AUDIO")} + - audio_dac.c ? {is_define("BEKEN_USING_AUDIO")} + - audio_device.c ? {is_define("BEKEN_USING_AUDIO")} + - drv_audio_icodec.c ? {is_define("BEKEN_USING_AUDIO")} + - drv_audio_mic.c ? {is_define("BEKEN_USING_AUDIO")} \ No newline at end of file diff --git a/drivers/hal/beken/drivers/drv_flash.c b/drivers/hal/beken/drivers/drv_flash.c index bdeadd4b7dc1c1bdb08490e4f861f18b195690ee..4567ac47546bb006b07bb7483ac01c13b778c1d7 100644 --- a/drivers/hal/beken/drivers/drv_flash.c +++ b/drivers/hal/beken/drivers/drv_flash.c @@ -21,35 +21,40 @@ *********************************************************************************************************************** */ -#include #include -#include #include #include -#include #ifdef BEKEN_USING_FLASH - +#include "board.h" #include "typedef.h" #include "drv_flash.h" #include "flash.h" +#include "fal.h" +#include +#include "ports/flash_info.c" + +#include + +#define DBG_TAG "drv_flash" -#define DBG_SECTION_NAME "[FLASH]" -static os_mutex_id flash_mutex; +static struct os_mutex flash_mutex; int beken_flash_read(uint32_t address, void *data, uint32_t size) { if (size == 0) { - LOG_D(DBG_SECTION_NAME, "flash read len is NULL\n"); + LOG_D(DBG_TAG, "flash read len is NULL\n"); return -1; } - os_mutex_lock(flash_mutex,OS_IPC_WAITING_FOREVER); + LOG_E(DBG_TAG, "flash read lock\n"); + + os_mutex_lock(&flash_mutex,OS_WAIT_FOREVER); flash_read(data, size, address); - os_mutex_unlock(flash_mutex); + os_mutex_unlock(&flash_mutex); return 0; } @@ -57,23 +62,26 @@ int beken_flash_write(uint32_t address, const void *data, uint32_t size) { if (size == 0) { - LOG_D(DBG_SECTION_NAME, "flash write len is NULL\n"); + LOG_D(DBG_TAG, "flash write len is NULL\n"); return -1; } + LOG_E(DBG_TAG, "flash write lock\n"); - os_mutex_lock(flash_mutex,OS_IPC_WAITING_FOREVER); + os_mutex_lock(&flash_mutex,OS_WAIT_FOREVER); flash_write((char *)data, size, address); - os_mutex_unlock(flash_mutex); + os_mutex_unlock(&flash_mutex); return 0; } int beken_flash_erase(uint32_t address) { - os_mutex_lock(flash_mutex,OS_IPC_WAITING_FOREVER); + LOG_E(DBG_TAG, "flash erase lock\n"); + + os_mutex_lock(&flash_mutex,OS_WAIT_FOREVER); address &= (0xFFF000); flash_ctrl(CMD_FLASH_ERASE_SECTOR, &address); - os_mutex_unlock(flash_mutex); + os_mutex_unlock(&flash_mutex); return 0; } @@ -81,7 +89,9 @@ int beken_flash_erase(uint32_t address) /*erase current sector*/ int beken_flash_erase_with_len(uint32_t address, uint32_t size) { - os_mutex_lock(flash_mutex,OS_IPC_WAITING_FOREVER); + LOG_E(DBG_TAG, "flash erase_with_len lock\n"); + + os_mutex_lock(&flash_mutex,OS_WAIT_FOREVER); address &= (0xFFF000); uint32_t cnt = 0; uint32_t addrtmp = address; @@ -90,7 +100,7 @@ int beken_flash_erase_with_len(uint32_t address, uint32_t size) addrtmp += cnt*4096; flash_ctrl(CMD_FLASH_ERASE_SECTOR, &addrtmp); } - os_mutex_unlock(flash_mutex); + os_mutex_unlock(&flash_mutex); return 0; } @@ -98,11 +108,48 @@ int beken_flash_erase_with_len(uint32_t address, uint32_t size) static int beken_flash_init(void) { - flash_mutex = os_mutex_create(OS_NULL, "flash", OS_FALSE); - return (flash_mutex != OS_NULL) ? OS_SUCCESS : OS_FAILURE; + return os_mutex_create(&flash_mutex, "flash", OS_FALSE); +} + +OS_PREV_INIT(beken_flash_init, OS_INIT_SUBLEVEL_HIGH); + +static int beken_flash_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + fal_flash_t *fal_flash = os_calloc(1, sizeof(fal_flash_t)); + + if (fal_flash == OS_NULL) + { + os_kprintf("fal flash mem leak %s.\r\n", dev->name); + return -1; + } + + struct onchip_flash_info *flash_info = (struct onchip_flash_info *)dev->info; + + memcpy(fal_flash->name, dev->name, min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))); + + fal_flash->name[min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))] = 0; + + fal_flash->capacity = flash_info->capacity; + fal_flash->block_size = flash_info->block_size; + fal_flash->page_size = flash_info->page_size; + + fal_flash->ops.read_page = beken_flash_read, + fal_flash->ops.write_page = beken_flash_write, + fal_flash->ops.erase_block = beken_flash_erase, + + fal_flash->priv = flash_info; + + return fal_flash_register(fal_flash); } -OS_INIT_CALL(beken_flash_init, OS_INIT_LEVEL_PRE_DEVICE); +OS_DRIVER_INFO beken_flash_driver = +{ + .name = "Onchip_Flash_Type", + .probe = beken_flash_probe, +}; + +OS_DRIVER_DEFINE(beken_flash_driver, OS_INIT_LEVEL_DEVICE, OS_INIT_SUBLEVEL_HIGH); + #endif diff --git a/drivers/hal/beken/drivers/drv_flash_disk.c b/drivers/hal/beken/drivers/drv_flash_disk.c index 510e44f94952273cbe8bfa0f6bc3bf40602b4a30..b38b7ac528930d2e4879ca6da04a08b13ba4b551 100644 --- a/drivers/hal/beken/drivers/drv_flash_disk.c +++ b/drivers/hal/beken/drivers/drv_flash_disk.c @@ -1,6 +1,3 @@ -#include -#include -#include #include #define BEKEN_USING_FLASH_DISK @@ -13,21 +10,21 @@ #define SECTOR_SIZE (4096) #define DISK_SIZE (1024*1024) -static struct rt_device flash_disk_device; +static struct os_device flash_disk_device; -static rt_size_t flash_disk_read(rt_device_t dev, - rt_off_t pos, +static os_size_t flash_disk_read(os_device_t dev, + os_off_t pos, void *buffer, - rt_size_t size) + os_size_t size) { beken_flash_read(FLASH_BASE + SECTOR_SIZE * pos, buffer, SECTOR_SIZE * size); return size; } -static rt_size_t flash_disk_write(rt_device_t dev, - rt_off_t pos, +static os_size_t flash_disk_write(os_device_t dev, + os_off_t pos, const void *buffer, - rt_size_t size) + os_size_t size) { int i = 0; @@ -40,54 +37,54 @@ static rt_size_t flash_disk_write(rt_device_t dev, return size; } -static rt_err_t flash_disk_control(rt_device_t dev, int cmd, void *args) +static os_err_t flash_disk_control(os_device_t dev, int cmd, void *args) { - if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) + if (cmd == OS_DEVICE_CTRL_BLK_GETGEOME) { - struct rt_device_blk_geometry *geometry; + struct os_device_blk_geometry *geometry; - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; + geometry = (struct os_device_blk_geometry *)args; + if (geometry == OS_NULL) return -OS_ERROR; geometry->bytes_per_sector = SECTOR_SIZE; geometry->sector_count = DISK_SIZE / SECTOR_SIZE; geometry->block_size = SECTOR_SIZE; } - return RT_EOK; + return OS_SUCCESS; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops flash_disk_ops = +#ifdef OS_USING_DEVICE_OPS +const static struct os_device_ops flash_disk_ops = { - RT_NULL, - RT_NULL, - RT_NULL, + OS_NULL, + OS_NULL, + OS_NULL, flash_disk_read, flash_disk_write, flash_disk_control }; -#endif /* RT_USING_DEVICE_OPS */ +#endif /* OS_USING_DEVICE_OPS */ -static int rt_hw_flash_disk_init(void) +static int os_hw_flash_disk_init(void) { memset(&flash_disk_device, 0, sizeof(flash_disk_device)); - flash_disk_device.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS + flash_disk_device.type = OS_Device_Class_Block; +#ifdef OS_USING_DEVICE_OPS flash_disk_device.ops = &flash_disk_ops; #else - flash_disk_device.init = RT_NULL; - flash_disk_device.open = RT_NULL; - flash_disk_device.close = RT_NULL; + flash_disk_device.init = OS_NULL; + flash_disk_device.open = OS_NULL; + flash_disk_device.close = OS_NULL; flash_disk_device.read = flash_disk_read; flash_disk_device.write = flash_disk_write; flash_disk_device.control = flash_disk_control; -#endif /* RT_USING_DEVICE_OPS */ +#endif /* OS_USING_DEVICE_OPS */ /* register device */ - return rt_device_register(&flash_disk_device, "disk0", \ - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + return os_device_register(&flash_disk_device, "disk0", \ + OS_DEVICE_FLAG_RDWR | OS_DEVICE_FLAG_STANDALONE); } -INIT_DEVICE_EXPORT(rt_hw_flash_disk_init); +INIT_DEVICE_EXPORT(os_hw_flash_disk_init); #endif \ No newline at end of file diff --git a/drivers/hal/beken/drivers/drv_flash_disk_readonly.c b/drivers/hal/beken/drivers/drv_flash_disk_readonly.c index 3e027a56794e50a88f0083aa8ab5a20ab66f27a0..a5edce03125bcd4366de8822cf0652e47ad35529 100644 --- a/drivers/hal/beken/drivers/drv_flash_disk_readonly.c +++ b/drivers/hal/beken/drivers/drv_flash_disk_readonly.c @@ -1,6 +1,4 @@ -#include #include -#include #include #include "drv_flash.h" diff --git a/drivers/hal/beken/drivers/drv_gpio.c b/drivers/hal/beken/drivers/drv_gpio.c index d62df10536edda8f911fb19defe1ec9e09b6d957..713118cf509916520af37f23052647a2d208d376 100644 --- a/drivers/hal/beken/drivers/drv_gpio.c +++ b/drivers/hal/beken/drivers/drv_gpio.c @@ -20,24 +20,22 @@ * 2021-02-09 OneOS Team First Version *********************************************************************************************************************** */ -#include #include -#include -#include #include #include -#include "interrupt.h" #include "typedef.h" #include "drv_gpio.h" #include "gpio.h" #include "pin.h" #include "gpio_pub.h" +#include #ifdef BEKEN_USING_GPIO -#define DBG_SECTION_NAME "[GPIO]" +#define DBG_TAG "drv_gpio" + extern void *os_memset(void *buff, uint8_t val, os_size_t count); typedef void (*gpio_isr_handler_t)(void *param); @@ -61,15 +59,15 @@ static void gpio_irq_dispatch(unsigned char index) { struct _gpio_dev *_dev = &gpio_dev; - LOG_D(DBG_SECTION_NAME, "%s run...\n", __FUNCTION__); + LOG_D(DBG_TAG, "%s run...\n", __FUNCTION__); if (index >= GPIONUM) { - LOG_D(DBG_ERROR, "%s index[%d] Wrongful\n", __FUNCTION__, index); + LOG_E(DBG_TAG, "%s index[%d] Wrongful\n", __FUNCTION__, index); return; } if (_dev->irq_desc[index].handler != OS_NULL) { - LOG_D(DBG_SECTION_NAME, "gpio irq pin:%d\n", index); + LOG_D(DBG_TAG, "gpio irq pin:%d\n", index); _dev->irq_desc[index].handler(_dev->irq_desc[index].param); } } @@ -115,7 +113,7 @@ static int _gpio_read(struct os_device *device, os_base_t pin) static os_err_t _gpio_attach_irq(struct os_device *device, int32_t pin, uint32_t mode, void (*hdr)(void *args), void *args) { - LOG_D(DBG_SECTION_NAME, "attach irq pin:%d mode:%d\n", pin, mode); + LOG_D(DBG_TAG, "attach irq pin:%d mode:%d\n", pin, mode); if (pin >= GPIONUM) return OS_FAILURE; @@ -144,7 +142,7 @@ static os_err_t _gpio_attach_irq(struct os_device *device, int32_t pin, static os_err_t _gpio_dettach_irq(struct os_device *device, int32_t pin) { - LOG_D(DBG_SECTION_NAME, "dettach irq pin:%d\n", pin); + LOG_D(DBG_TAG, "dettach irq pin:%d\n", pin); if (pin >= GPIONUM) return OS_FAILURE; @@ -157,7 +155,7 @@ static os_err_t _gpio_dettach_irq(struct os_device *device, int32_t pin) static os_err_t _gpio_irq_enable(struct os_device *device, os_base_t pin, uint32_t enabled) { - LOG_D(DBG_SECTION_NAME, "enable irq pin:%d enabled:%d\n", pin, enabled); + LOG_D(DBG_TAG, "enable irq pin:%d enabled:%d\n", pin, enabled); if (pin >= GPIONUM) return OS_FAILURE; @@ -188,6 +186,8 @@ int bk_hw_gpio_init(void) return OS_SUCCESS; } +OS_INIT_CALL(bk_hw_gpio_init, OS_INIT_LEVEL_POST_KERNEL, OS_INIT_SUBLEVEL_MIDDLE); + int bk_hw_gpio_exit(void) { @@ -195,6 +195,5 @@ int bk_hw_gpio_exit(void) os_device_unregister(gpio_dev.parent); } -OS_BOARD_INIT(bk_hw_gpio_init); #endif diff --git a/drivers/hal/beken/drivers/drv_i2s.c b/drivers/hal/beken/drivers/drv_i2s.c index eeadca627c8800df403302bd56fad101661d7e7a..7d961e11008e2ea7758e8e046ea4f10166d724b4 100644 --- a/drivers/hal/beken/drivers/drv_i2s.c +++ b/drivers/hal/beken/drivers/drv_i2s.c @@ -1,6 +1,4 @@ #include -#include -#include #include #include diff --git a/drivers/hal/beken/drivers/drv_uart.c b/drivers/hal/beken/drivers/drv_uart.c index 13e74e30d553a4c7630c9f148bfed7bd77bbbf29..c1181de18787df520c4610d5023e9cd99d505d12 100644 --- a/drivers/hal/beken/drivers/drv_uart.c +++ b/drivers/hal/beken/drivers/drv_uart.c @@ -13,329 +13,314 @@ * * @file drv_uart.c * - * @brief This file implements usart driver for beken + * @brief This file implements uart driver for nrf5 * * @revision * Date Author Notes - * 2020-12-20 OneOS Team First Version + * 2020-02-20 OneOS Team First Version *********************************************************************************************************************** */ - - -#include -#include -#include +#include +#include +#include +#include #include - -#include "bus.h" -#include "os_assert.h" -#include "serial.h" -#include "interrupt.h" -#include "typedef.h" #include "drv_uart.h" + +#include "os_stddef.h" + #include "uart.h" +#include "uart_pub.h" #include "icu_pub.h" -#include "board.h" #include "drv_model_pub.h" -#include "arm_arch.h" -#ifdef OS_USING_SERIAL +#ifndef REG_READ +#define REG_READ(addr) (*((volatile UINT32 *)(addr))) +#endif + +#ifndef REG_WRITE +#define REG_WRITE(addr, _data) (*((volatile UINT32 *)(addr)) = (_data)) +#endif + -struct device_uart +typedef struct bk_uart { - struct os_serial_device serial; - uint32_t port; - uint32_t irqno; - struct beken_uart_info *uart_info; - uint8_t *buff; - uint32_t count; - uint32_t size; - uint32_t state; - char name[OS_NAME_MAX]; -}; + struct os_serial_device serial_dev; + struct beken_uart_info *huart; + + soft_dma_t sdma; -static struct device_uart *g_uart[2]; + uint8_t *rx_buff; + uint32_t rx_index; + uint32_t rx_size; + const uint8_t *tx_buff; + uint32_t tx_count; + uint32_t tx_size; + + os_list_node_t list; +}bk_uart_t; + +static os_list_node_t bk_uart_list = OS_LIST_INIT(bk_uart_list); void beken_uart_isr_rx(unsigned char uport) { - struct os_serial_device *serial = OS_NULL; - struct device_uart * uart = OS_NULL; - unsigned int reg_addr = 0; - unsigned int reg_val = 0; - unsigned int fifo_status = 0; + struct bk_uart *uart = OS_NULL; - if(UART1_PORT == uport) - { - uart = g_uart[0]; - fifo_status = REG_UART1_FIFO_STATUS; - reg_val = REG_READ(REG_UART1_INTR_ENABLE); - reg_addr = REG_UART1_INTR_ENABLE; - } - else + os_list_for_each_entry(uart, &bk_uart_list, struct bk_uart, list) { - uart = g_uart[1]; - fifo_status = REG_UART2_FIFO_STATUS; - reg_val = REG_READ(REG_UART2_INTR_ENABLE); - reg_addr = REG_UART2_INTR_ENABLE; + if (uart->huart->port == uport){ + while(REG_READ(uart->huart->fifo_status) & FIFO_RD_READY) + { + uart->rx_buff[uart->rx_index++] = (uint8_t)uart_read_byte(uport); + + if (uart->rx_index == (uart->rx_size / 2)) + { + soft_dma_half_irq(&uart->sdma); + } + + if (uart->rx_index == uart->rx_size) + { + uart->rx_index = 0; + soft_dma_full_irq(&uart->sdma); + } + } + } } - - OS_ASSERT(uart != OS_NULL); +} - if(1 == uart->state) - { - while(REG_READ(fifo_status) & FIFO_RD_READY) - { // read all HW fifo data - if(uart->count < uart->size) - { - uart->buff[uart->count] = (uint8_t)uart_read_byte(uport); - uart->count ++; - } - else - { - break; - } - } - - if(uart->count == uart->size) - { - uart->state = 0; - - reg_val &= ~(RX_FIFO_NEED_READ_EN | UART_RX_STOP_END_EN); - REG_WRITE(reg_addr,reg_val); - } - } +static uint32_t bk_sdma_int_get_index(soft_dma_t *dma) +{ + bk_uart_t *uart = os_container_of(dma, bk_uart_t, sdma); + + return uart->rx_index; } -static os_err_t beken_uart_configure(struct os_serial_device *serial, struct serial_configure *cfg) +static os_err_t bk_sdma_int_init(soft_dma_t *dma) { - uint32_t addr, val; - struct device_uart * uart; - bk_uart_config_t config; + return OS_SUCCESS; +} - OS_ASSERT(serial != OS_NULL); - serial->config = *cfg; +static os_err_t bk_sdma_int_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + uint32_t reg_val = 0; + bk_uart_t *uart = os_container_of(dma, bk_uart_t, sdma); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); + uart->rx_buff = buff; + uart->rx_index = 0; + uart->rx_size = size; - OS_ASSERT((serial->config.data_bits >= DATA_BITS_5) && \ - (serial->config.data_bits <= DATA_BITS_8)); + reg_val = REG_READ(uart->huart->inter_reg_addr); + reg_val |= (RX_FIFO_NEED_READ_EN | UART_RX_STOP_END_EN); + REG_WRITE(uart->huart->inter_reg_addr, reg_val); - config.baud_rate = serial->config.baud_rate; - config.data_width = serial->config.data_bits - DATA_BITS_5; - config.parity = serial->config.parity; - config.stop_bits = serial->config.stop_bits; - config.flow_control = FLOW_CTRL_DISABLED; - config.flags = 0; - - uart_hw_set_change(uart->port, &config); + sddev_control(ICU_DEV_NAME, CMD_ICU_INT_ENABLE, &uart->huart->irq_uart_bit); return OS_SUCCESS; } -static int beken_uart_start_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +static uint32_t bk_sdma_int_stop(soft_dma_t *dma) { - return OS_SUCCESS; + uint32_t reg_val = 0; + bk_uart_t *uart = os_container_of(dma, bk_uart_t, sdma); + + reg_val = REG_READ(uart->huart->inter_reg_addr); + reg_val &= ~(RX_FIFO_NEED_READ_EN | UART_RX_STOP_END_EN); + REG_WRITE(uart->huart->inter_reg_addr, reg_val); + + return uart->rx_index; } -static int beken_uart_stop_send(struct os_serial_device *serial) +/* sdma callback */ +static void bk_uart_sdma_callback(soft_dma_t *dma) { - return OS_SUCCESS; + bk_uart_t *uart = os_container_of(dma, bk_uart_t, sdma); + + os_hw_serial_isr_rxdone((struct os_serial_device *)uart); } -static int beken_uart_start_recv(struct os_serial_device *serial, uint8_t *buff, os_size_t size) +static void bk_uart_sdma_init(struct bk_uart *uart, dma_ring_t *ring) { - unsigned int len = 0; - unsigned int uport = 0; - unsigned int reg_val = 0; - unsigned int reg_addr = 0; - int ret = 0; - struct device_uart *uart = OS_NULL; - unsigned int param; - - OS_ASSERT(serial != OS_NULL); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); - uport = uart->port; - - if (UART1_PORT == uport) - { - reg_val = REG_READ(REG_UART1_INTR_ENABLE); - reg_addr = REG_UART1_INTR_ENABLE; - param = IRQ_UART1_BIT; - } - else - { - reg_val = REG_READ(REG_UART2_INTR_ENABLE); - reg_addr = REG_UART2_INTR_ENABLE; - param = IRQ_UART2_BIT; - } + soft_dma_t *dma = &uart->sdma; + soft_dma_stop(dma); + + memset(&dma->hard_info, 0, sizeof(dma->hard_info)); + + dma->hard_info.mode = HARD_DMA_MODE_CIRCULAR; + dma->hard_info.max_size = 64 * 1024; + dma->hard_info.flag = HARD_DMA_FLAG_HALF_IRQ | HARD_DMA_FLAG_FULL_IRQ; + dma->hard_info.data_timeout = uart_calc_byte_timeout_us(uart->serial_dev.config.baud_rate); - uart->state = 1; - uart->buff = buff; - uart->count = 0; - uart->size = size; + dma->ops.get_index = bk_sdma_int_get_index; + dma->ops.dma_init = bk_sdma_int_init; + dma->ops.dma_start = bk_sdma_int_start; + dma->ops.dma_stop = bk_sdma_int_stop; - reg_val |= (RX_FIFO_NEED_READ_EN | UART_RX_STOP_END_EN); - REG_WRITE(reg_addr,reg_val); + dma->cbs.dma_half_callback = bk_uart_sdma_callback; + dma->cbs.dma_full_callback = bk_uart_sdma_callback; + dma->cbs.dma_timeout_callback = bk_uart_sdma_callback; - sddev_control(ICU_DEV_NAME, CMD_ICU_INT_ENABLE, ¶m); + soft_dma_init(dma); + soft_dma_start(dma, ring); + soft_dma_irq_enable(&uart->sdma, OS_TRUE); - return ret; } - -static int beken_uart_stop_recv(struct os_serial_device *serial) +static os_err_t bk_uart_init(struct os_serial_device *serial, struct serial_configure *cfg) { - unsigned int len = 0; - unsigned int uport = 0; - unsigned int reg_val = 0; - unsigned int reg_addr = 0; - int ret = 0; - struct device_uart *uart = OS_NULL; - - - OS_ASSERT(serial != OS_NULL); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); - uport = uart->port; - - if (UART1_PORT == uport) - { - reg_val = REG_READ(REG_UART1_INTR_ENABLE); - reg_addr = REG_UART1_INTR_ENABLE; - } - else - { - reg_val = REG_READ(REG_UART2_INTR_ENABLE); - reg_addr = REG_UART2_INTR_ENABLE; - } + uart_config_t config; + struct bk_uart *uart; - uart->state = 0; - uart->buff = OS_NULL; - reg_val &= ~(RX_FIFO_NEED_READ_EN | UART_RX_STOP_END_EN); - - REG_WRITE(reg_addr,reg_val); - - return ret; -} + OS_ASSERT(serial != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + uart = os_container_of(serial, struct bk_uart, serial_dev); + if(uart->huart == OS_NULL) + return OS_FAILURE; -static int beken_uart_recv_state(struct os_serial_device *serial) -{ - int state = 0; - unsigned int fifo_status_reg = 0; - struct device_uart *uart = OS_NULL; - os_ubase_t level; + serial->config = *cfg; + OS_ASSERT((serial->config.data_bits >= DATA_BITS_5) && \ + (serial->config.data_bits <= DATA_BITS_8)); + + config.baud_rate = serial->config.baud_rate; + config.data_width = serial->config.data_bits - DATA_BITS_5; + config.parity = serial->config.parity; + config.stop_bits = serial->config.stop_bits; + config.flow_control = FLOW_CTRL_DISABLED; + config.flags = 0; - OS_ASSERT(serial != OS_NULL); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); + uart_hw_set_change(uart->huart->port, &config); - state = uart->count; - if(0 == uart->state) - state |= OS_SERIAL_FLAG_RX_IDLE; + bk_uart_sdma_init(uart, &serial->rx_fifo->ring); - return state; + return OS_SUCCESS; } -static int beken_uart_poll_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) -{ - struct device_uart *uart = OS_NULL; - unsigned int len = 0; - unsigned int i = 0; - os_ubase_t level; - +static int bk_uart_poll_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + int i; + struct bk_uart *uart; + OS_ASSERT(serial != OS_NULL); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); - - level = os_hw_interrupt_disable(); - for(i = 0; i < size; ++i) - { - if(uart_write_byte(uart->port,buff[i])); - ++len; - } - os_hw_interrupt_enable(level); - return (size > len) ? len : size ; + uart = os_container_of(serial, struct bk_uart, serial_dev); + + OS_ASSERT(uart != OS_NULL); + + for (i = 0; i < size; i++) + { + os_base_t level = os_irq_lock(); + uart_write_byte(uart->huart->port, (char)buff[i]); + os_irq_unlock(level); + } + + return size; } -static int beken_uart_poll_recv(struct os_serial_device *serial, uint8_t *buff, os_size_t size) +void hal_bk_uart_uninit(uint32_t port) { - struct device_uart *uart = OS_NULL; - unsigned int i = 0; - os_ubase_t level; - - OS_ASSERT(serial != OS_NULL); - uart = serial->parent.user_data; - OS_ASSERT(uart != OS_NULL); + return; +} - level = os_hw_interrupt_disable(); - for(i = 0; i < size; ++i) - { - buff[i] = (uint8_t)uart_read_byte(uart->port); - } - os_hw_interrupt_enable(level); +static os_err_t bk_uart_deinit(struct os_serial_device *serial) +{ + struct bk_uart *uart; - return size ; -} + OS_ASSERT(serial != OS_NULL); + uart = os_container_of(serial, struct bk_uart, serial_dev); + if(uart->huart == OS_NULL) + return OS_FAILURE; -static const struct os_uart_ops beken_uart_ops = { - .configure = beken_uart_configure, + /* rx */ + hal_bk_uart_uninit(uart->huart->port); + soft_dma_stop(&uart->sdma); - .start_send = OS_NULL,//beken_uart_start_send - .stop_send = OS_NULL,//beken_uart_stop_send + /* tx */ - .start_recv = beken_uart_start_recv, - .stop_recv = beken_uart_stop_recv, - .recv_state = beken_uart_recv_state, - - .poll_send = beken_uart_poll_send, - .poll_recv = beken_uart_poll_recv, -}; + return OS_SUCCESS; +} +static const struct os_uart_ops bk_uart_ops = { + .init = bk_uart_init, + .deinit = bk_uart_deinit, + .start_send = OS_NULL, + .poll_send = bk_uart_poll_send, +}; -static int beken_uart_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +int bk_uart_probe(const os_driver_info_t *drv, const os_device_info_t *dev) { + os_err_t result = 0; + os_base_t level; + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; - os_err_t result = 0; - os_ubase_t level; + struct beken_uart_info *uart_info = (struct beken_uart_info *)dev->info; + struct bk_uart *uart = os_calloc(1, sizeof(struct bk_uart)); - struct device_uart *uart = os_calloc(1, sizeof(struct device_uart)); OS_ASSERT(uart); + uart->huart = uart_info; - uart->uart_info = (struct beken_uart_info *)dev->info; + struct os_serial_device *serial = &uart->serial_dev; - struct os_serial_device *serial = &uart->serial; - - serial->ops = &beken_uart_ops; + serial->ops = &bk_uart_ops; serial->config = config; - - uart->port = uart->uart_info->port; // UART_PORT; - uart->irqno = uart->uart_info->irqno; // IRQ_UART; - os_memcpy(uart->name, dev->name,sizeof(dev->name)); - if (UART1_PORT == uart->port) - g_uart[0] = uart; - else - g_uart[1] = uart; + if ( UART1_PORT == uart->huart->port){ + serial->config.baud_rate = BEKEN_UART1_BAUD; + } else { + serial->config.baud_rate = BEKEN_UART2_BAUD; + } + + level = os_irq_lock(); + os_list_add_tail(&bk_uart_list, &uart->list); + os_irq_unlock(level); - result = os_hw_serial_register(serial, dev->name, OS_DEVICE_FLAG_RDWR, uart); + result = os_hw_serial_register(serial, dev->name, NULL); + OS_ASSERT(result == OS_SUCCESS); return result; + } -OS_DRIVER_INFO beken_uart_driver = { - .name = "Uart_Type", - .probe = beken_uart_probe, +OS_DRIVER_INFO bk_uart_driver = { + .name = "uart_Type", + .probe = bk_uart_probe, }; -OS_DRIVER_DEFINE(beken_uart_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); -#endif +OS_DRIVER_DEFINE(bk_uart_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); + +#ifdef OS_USING_CONSOLE + +static struct beken_uart_info *console_uart = OS_NULL; + +void __os_hw_console_output(char *str) +{ + if (console_uart == OS_NULL ) + return; + while (*str) + { + uart_write_byte(console_uart->port, *str); + str++; + } +} + +static int bk_uart_early_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + if( !strcmp(dev->name, OS_CONSOLE_DEVICE_NAME) ) + console_uart = (struct beken_uart_info *)dev->info; + + return OS_SUCCESS; +} + +OS_DRIVER_INFO bk_uart_early_driver = { + .name = "uart_Type", + .probe = bk_uart_early_probe, +}; + +OS_DRIVER_DEFINE(bk_uart_early_driver, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_MIDDLE); + +#endif diff --git a/drivers/hal/beken/drivers/drv_uart.h b/drivers/hal/beken/drivers/drv_uart.h index 4e6e9e1a5d149f7cec55f01c32a0f2911cc9c814..4d444ba6fd603f05a98695302789e8b3ca678315 100644 --- a/drivers/hal/beken/drivers/drv_uart.h +++ b/drivers/hal/beken/drivers/drv_uart.h @@ -1,38 +1,39 @@ -/* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * http://www.apache.org/licenses/LICENSE-2.0 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. * - * Change Logs: - * Date Author Notes - * 2017-5-30 Bernard the first version + * @file drv_uart.h + * + * @brief This file implements the task functions. + * + * @revision + * Date Author Notes + * 2021-10-18 OneOS team First Version + *********************************************************************************************************************** */ - #ifndef __DRV_UART_H__ #define __DRV_UART_H__ +#include "os_types.h" + +void beken_uart_isr_rx(unsigned char uport); + struct beken_uart_info { uint32_t port; uint32_t irqno; + uint32_t inter_reg_addr; + uint32_t fifo_status; + uint32_t irq_uart_bit; }; - -int rt_hw_uart_init(void); -int rt_hw_uart_exit(void); - #endif /* __DRV_UART_H__ */ diff --git a/drivers/hal/beken/drivers/weave.yaml b/drivers/hal/beken/drivers/weave.yaml index 9b011c6ba9c2232795dd093e081a9c6ff1a5d426..1fc28ad34b9fc04ed3c35358b336de0db4b0e0d5 100644 --- a/drivers/hal/beken/drivers/weave.yaml +++ b/drivers/hal/beken/drivers/weave.yaml @@ -1,29 +1,38 @@ # 组名 -group_name: Drivers +group_name: hal/drivers # 依赖宏控 depend_macro: - - SOC_FAMILY_BK72XX + - MANUFACTOR_BEKEN # 编译连接信息 build_option: cpppath: - . - + - wlan # 源码 source_file: - - drv_adc.c ? {is_define('RT_USING_ADC')} - - drv_flash.c ? {is_define('BEKEN_USING_FLASH')} - - drv_gpio.c ? {is_define('BEKEN_USING_GPIO')} - - drv_iic.c ? {is_define('BEKEN_USING_IIC')} - - drv_pwm.c ? {is_define('BEKEN_USING_PWM')} - - drv_spi.c ? {is_define('BEKEN_USING_SPI')} - - drv_spi_flash.c ? {is_define('BEKEN_USING_SPI')} - - drv_spi_hslave.c ? {is_define('BEKEN_USING_SPI')} - - drv_spi_psram.c ? {is_define('BEKEN_USING_SPI')} - - drv_uart.c ? {is_define('BEKEN_USING_UART1')} and ? {is_define('BEKEN_USING_UART2')} - - drv_wdt.c ? {is_define('BEKEN_USING_WDT')} -# 子目录 -add_subdirectory: - - ./* \ No newline at end of file + - drv_flash.c ? {is_define(['OS_USING_FAL', 'BEKEN_USING_FLASH'])} + - drv_adc.c ? {is_define(['OS_USING_ADC'])} + - drv_uart.c ? {is_define(['BEKEN_USING_UART1','BEKEN_USING_UART2'])} + - drv_wdt.c ? {is_define(['BEKEN_USING_WDT'])} + - drv_iic.c ? {is_define(['BEKEN_USING_IIC'])} + - drv_pwm.c ? {is_define(['BEKEN_USING_PWM'])} + - drv_gpio.c ? {is_define(['BEKEN_USING_GPIO'])} + - drv_gpio.c ? {is_define(['BEKEN_USING_SPI'])} + - drv_spi.c ? {is_define(['BEKEN_USING_SPI'])} + - drv_spi_flash.c ? {is_define(['BEKEN_USING_SPI'])} + - drv_spi_hslave.c ? {is_define(['BEKEN_USING_SPI'])} + - drv_spi_psram.c ? {is_define(['BEKEN_USING_SPI'])} + - drv_i2s.c + - wlan/drv_wlan.c ? {is_define("BEKEN_USING_WLAN")} + - wlan/drv_wlan_fast_connect.c ? {is_define("BEKEN_USING_WLAN")} + - wlan/net.c ? {is_define("BEKEN_USING_WLAN")} +# - drv_pm.c +# - drv_sdio_sd.c +# - drv_sdram.c +# - drv_sys_ctrl.c +# - drv_psram.c +# - drv_flash_disk.c +# - drv_flash_disk_readonly.c diff --git a/drivers/hal/beken/drivers/wlan/drv_wlan.c b/drivers/hal/beken/drivers/wlan/drv_wlan.c index 167f29fc160a2ab14c9ea1c4f1c8b0fc393ca130..01a816d70c26f810793c0474c71905f3efa76f07 100644 --- a/drivers/hal/beken/drivers/wlan/drv_wlan.c +++ b/drivers/hal/beken/drivers/wlan/drv_wlan.c @@ -1,1215 +1,1107 @@ -/** - *********************************************************************************************************************** - * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with - * the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * @file drv_wlan.c - * - * @brief This file implements wlan driver for beken - * - * @revision - * Date Author Notes - * 2020-12-20 OneOS Team First Version - *********************************************************************************************************************** - */ - -#include "include.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include "netif/ethernetif.h" - -#include -#include -#include "netif/etharp.h" -#include "lwip_netif_address.h" -#include "sa_station.h" -#include "drv_model_pub.h" -#include "mem_pub.h" -#include "common.h" -#include "hostapd_cfg.h" - -#include "sk_intf.h" -#include "rw_pub.h" -#include "error.h" -#include "rtos_pub.h" -#include "param_config.h" -#include "wlan_ui_pub.h" - -#include -#include -#include -#include -#include -#include -#include "os_types.h" -#include "bus.h" -#include "os_errno.h" - -#include "drv_flash.h" -#include "drv_wlan.h" -#include "drv_wlan_fast_connect.h" - -#include "uart_pub.h" -#include "ieee802_11_defs.h" -#include "wlan_ui_pub.h" -#include "net_param_pub.h" -#include "role_launch.h" -#include "app.h" - -/* Define those to better describe your network interface. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -#ifdef BEKEN_DRV_DEBUG -#define DRV_WLAN_DBG(...) os_kprintf("[DRV_WLAN]"),os_kprintf(__VA_ARGS__) -#else -#define DRV_WLAN_DBG(...) -#endif - - -#define ETH_INTF_DEBUG 0 -#if ETH_INTF_DEBUG -#define ETH_INTF_PRT warning_prf -#define ETH_INTF_WARN warning_prf -#define ETH_INTF_FATAL fatal_prf -#else -#define ETH_INTF_PRT null_prf -#define ETH_INTF_WARN null_prf -#define ETH_INTF_FATAL null_prf -#endif - -#define OS_WLAN_DEVICE(eth) (struct os_wlan_device *)(eth) - -static char gs_dhcpd_server_ip[16] = "192.168.169.1"; -char* DHCPD_SERVER_IP = gs_dhcpd_server_ip; - -#ifdef BEKEN_USING_WLAN_STA -static struct os_wlan_device _g_sta_device; -static struct beken_wifi_info _g_sta_info; -#endif - -#ifdef BEKEN_USING_WLAN_AP -static struct os_wlan_device _g_ap_device; -static struct beken_wifi_info _g_ap_info; -#endif - -#define RT_WLAN_SSID_MAX_LEN 32 -#define SCAN_WAIT_OUT_TIME 2000 -static os_semaphore_id _g_scan_done_sem; -int start_connect_tick = 0; -int end_connect_tick = 0; -int g_beken_rssi = 0; - -static int g_sta_status = 0; -static int g_ap_status = 0; - - -static wifi_country_t country_code_CN = {.cc= "CN", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; -static wifi_country_t country_code_US = {.cc= "US", .schan=1, .nchan=11, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; -static wifi_country_t country_code_EP = {.cc= "EP", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; -static wifi_country_t country_code_JP = {.cc= "JP", .schan=1, .nchan=14, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; -static wifi_country_t country_code_AU = {.cc= "AU", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; - - -static os_err_t _wifi_easyjoin(os_device_t *dev, void *passwd); -static os_err_t beken_wlan_disconnect(struct os_wlan_device *wlan); - -extern void *net_get_sta_handle(void); -extern void *net_get_uap_handle(void); -extern void wifi_get_mac_address(char *mac, u8 type); -extern void *net_get_netif_handle(uint8_t iface); -extern int bmsg_tx_sender(struct pbuf *p, uint32_t vif_idx); -extern void bk_wlan_status_register_cb(FUNC_1PARAM_PTR cb); -extern struct netif* os_wlan_get_netif(struct os_wlan_device *wlan); -extern void dhcp_server_stop(void); -extern int wifi_set_mac_address(char *mac); -extern rw_evt_type mhdr_get_station_status(void); -extern os_bool_t os_wlan_is_connected(void); -extern os_bool_t os_wlan_ap_is_active(void); -extern int bk_wlan_power_save_set_level(BK_PS_LEVEL level); - - - -//#define MINI_DUMP -//#define ETH_RX_DUMP -//#define ETH_TX_DUMP - -#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) -static void packet_dump(const char *msg, const struct pbuf *p) -{ - const struct pbuf *q; - uint32_t i, j; - uint8_t *ptr; - - os_kprintf("%s %d byte\n", msg, p->tot_len); - -#ifdef MINI_DUMP - return; -#endif - - i = 0; - for (q = p; q != OS_NULL; q = q->next) - { - ptr = q->payload; - - for (j = 0; j < q->len; j++) - { - if ((i % 8) == 0) - { - os_kprintf(" "); - } - if ((i % 16) == 0) - { - os_kprintf("\r\n"); - } - os_kprintf("%02x ", *ptr); - - i++; - ptr++; - } - } - - os_kprintf("\n\n"); -} -#endif /* dump */ - -static os_err_t low_level_output(struct netif *netif, struct pbuf *p) -{ - int ret; - err_t err = ERR_OK; - uint8_t vif_idx = rwm_mgmt_get_netif2vif(netif); - -#ifdef ETH_TX_DUMP - packet_dump("TX dump", p); -#endif /* ETH_TX_DUMP */ - - if (!netif_is_link_up(netif)) - { - return ERR_IF; - } - - ret = bmsg_tx_sender(p, (uint32_t)vif_idx); - if (0 != ret) - { - err = ERR_TIMEOUT; - } - - return err; -} - - -void ethernetif_input(int iface, struct pbuf *p) -{ - struct eth_hdr *ethhdr = OS_NULL; - struct netif *netif = OS_NULL; - struct os_wlan_device *dev = OS_NULL; - -#ifdef ETH_RX_DUMP - packet_dump("RX dump", p); -#endif /* ETH_RX_DUMP */ - - if (p->len <= SIZEOF_ETH_HDR) - { - pbuf_free(p); - return; - } - - netif = rwm_mgmt_get_vif2netif((uint8_t)iface); - if (!netif) - { - ETH_INTF_PRT("ethernetif_input no netif found %d\r\n", iface); - pbuf_free(p); - p = NULL; - return; - } - -#ifdef BEKEN_USING_WLAN_STA - if(netif == os_wlan_get_netif(&_g_sta_device)) - dev = &_g_sta_device; -#endif -#ifdef BEKEN_USING_WLAN_AP - else if(netif == os_wlan_get_netif(&_g_ap_device)) - dev = &_g_ap_device; -#endif - - if (!dev) - { - ETH_INTF_PRT("ethernetif_input no wlan device found %d\r\n", iface); - pbuf_free(p); - p = NULL; - return; - } - - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - - switch (htons(ethhdr->type)) - { - /* IP or ARP packet? */ - case ETHTYPE_IP: - case ETHTYPE_ARP: -#if PPPOE_SUPPORT - /* PPPoE packet? */ - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: -#endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - //if (netif->input(p, netif) != ERR_OK) // ethernet_input - if(os_wlan_dev_report_data(dev,p, p->tot_len) != ERR_OK) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\r\n")); - pbuf_free(p); - p = NULL; - } - break; - - case ETHTYPE_EAPOL: - ke_l2_packet_tx(p->payload, p->len, iface); - pbuf_free(p); - p = NULL; - break; - - default: - pbuf_free(p); - p = NULL; - break; - } - -} - -/** - * OS LwIP Interface - */ - -struct netif *wlan_get_sta_netif(void) -{ -#ifdef BEKEN_USING_WLAN_STA - //return _g_sta_device.prot.netif; - return os_wlan_get_netif(&_g_sta_device); -#else - return OS_NULL; -#endif -} - -struct netif *wlan_get_uap_netif(void) -{ -#ifdef BEKEN_USING_WLAN_AP - //return _g_ap_device.parent.netif; - return os_wlan_get_netif(&_g_ap_device); -#else - return OS_NULL; -#endif -} - -// wlan event callbacks -static void wlan_event_handle(void *ctx) -{ - rw_evt_type event = *((rw_evt_type*)ctx); - - struct os_wlan_info info; - struct os_wlan_buff user_buff; - - if ((event < 0) || (event > RW_EVT_MAX)) - { - return; - } - - DRV_WLAN_DBG("===wlan_event_handle:%d===\r\n",event); - switch (event) - { -#ifdef BEKEN_USING_WLAN_STA - case RW_EVT_STA_CONNECTED: - end_connect_tick = os_tick_get(); - DRV_WLAN_DBG("[wlan_connect]:start tick = %d, connect done tick = %d, total = %d \n", start_connect_tick, end_connect_tick, end_connect_tick - start_connect_tick); - os_wlan_dev_indicate_event_handle(&_g_sta_device, OS_WLAN_DEV_EVT_CONNECT, OS_NULL); - break; - - case RW_EVT_STA_DISCONNECTED: - os_wlan_dev_indicate_event_handle(&_g_sta_device, OS_WLAN_DEV_EVT_DISCONNECT, OS_NULL); - break; - - case RW_EVT_STA_CONNECT_FAILED: - case RW_EVT_STA_PASSWORD_WRONG: - case RW_EVT_STA_NO_AP_FOUND: - if (_g_sta_info.mode == ADVANCED_MODE) - { - //wlan_fast_connect_info_erase(); - /* fast connected failed, switch to normal connect */ - _g_sta_info.mode = NORMAL_MODE; - } - - os_wlan_dev_indicate_event_handle(&_g_sta_device, OS_WLAN_DEV_EVT_CONNECT_FAIL, OS_NULL); - break; -#endif - -#ifdef BEKEN_USING_WLAN_AP - case RW_EVT_AP_CONNECTED: - // null data,only a parameter placeholder to insure OS_WLAN_DEV_EVT_AP_ASSOCIATED flow process - user_buff.data = &info; - user_buff.len = sizeof(struct os_wlan_info); - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_ASSOCIATED, &user_buff); - break; - - case RW_EVT_AP_DISCONNECTED: - // null data,only a parameter placeholder to insure RW_EVT_AP_DISCONNECTED flow process - user_buff.data = &info; - user_buff.len = sizeof(struct os_wlan_info); - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_DISASSOCIATED, &user_buff); - break; - - case RW_EVT_AP_CONNECT_FAILED: - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_ASSOCIATE_FAILED, OS_NULL); - break; - - case RW_EVT_AP_START_COMPLETE: - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_START, OS_NULL); - break; - - case RW_EVT_AP_STOP_COMPLETE: - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_STOP, OS_NULL); - break; -#endif - - default: - break; - } -} -static void scan_ap_callback(void *ctxt, uint8_t param) -{ - if (_g_scan_done_sem) - { - os_semaphore_post(_g_scan_done_sem); - DRV_WLAN_DBG("release scan done semaphore \n"); - } -} - -static int rt_wlan_malloc_scan_result(struct os_wlan_scan_result **scan_result, int num) -{ - struct os_wlan_scan_result *_scan_result; - int i; - int result = OS_SUCCESS; - -#if 0 - _scan_result = os_malloc(sizeof(struct os_wlan_scan_result)); - if (_scan_result == OS_NULL) - { - os_kprintf("rt_wlan_scan_result malloc failed!\r\n"); - result = -OS_FAILURE; - goto _exit; - } - os_memset(_scan_result, 0, sizeof(struct os_wlan_scan_result)); -#else - _scan_result = *scan_result; -#endif - - _scan_result->num = num; - _scan_result->info = os_malloc(sizeof(struct os_wlan_info) * num); - if (_scan_result->info == OS_NULL) - { - DRV_WLAN_DBG("rt_scan_rst table malloc failed!\r\n"); - result = -OS_FAILURE; - goto _exit; - } - os_memset(_scan_result->info, 0, sizeof(struct os_wlan_info) * num); - - return OS_SUCCESS; -_exit: - - if (_scan_result->info) - { - os_free(_scan_result->info); - _scan_result->info = OS_NULL; - } - - /* - if (_scan_result) - { - os_free(_scan_result); - _scan_result = OS_NULL; - } - *scan_result = OS_NULL; - */ - - return -OS_FAILURE; -} - -static const char *wlan_sec_type_string[] = -{ - "NONE", - "WEP", - "WPA-TKIP", - "WPA-AES", - "WPA2-TKIP", - "WPA2-AES", - "WPA2-MIX", - "AUTO" -}; - -int wlan_scan_done_handler(struct os_wlan_scan_result **scan_result) -{ - struct os_wlan_scan_result *_scan_result; - struct sta_scan_res *scan_rst_table; - char scan_rst_ap_num = 0; - int i; - - scan_rst_ap_num = bk_wlan_get_scan_ap_result_numbers(); - if (scan_rst_ap_num == 0) - { - DRV_WLAN_DBG("NULL AP \r\n"); - return -OS_FAILURE; - } - - scan_rst_table = (struct sta_scan_res *)os_malloc(sizeof(struct sta_scan_res) * scan_rst_ap_num); - if (scan_rst_table == OS_NULL) - { - DRV_WLAN_DBG("scan_rst_table malloc failed!\r\n"); - return -OS_FAILURE; - } - - bk_wlan_get_scan_ap_result(scan_rst_table, scan_rst_ap_num); - - if (rt_wlan_malloc_scan_result(scan_result, scan_rst_ap_num) != OS_SUCCESS) - { - DRV_WLAN_DBG("malloc memory for scan failed \n"); - return -OS_FAILURE; - } - _scan_result = *scan_result; - - DRV_WLAN_DBG("\r\n"); - for (i = 0; i < scan_rst_ap_num; i++) - { - os_strncpy(_scan_result->info[i].ssid.val, scan_rst_table[i].ssid, RT_WLAN_SSID_MAX_LEN); - _scan_result->info[i].ssid.len = strlen(scan_rst_table[i].ssid); - os_memcpy(_scan_result->info[i].bssid, scan_rst_table[i].bssid, 6); - _scan_result->info[i].channel = scan_rst_table[i].channel; - - DRV_WLAN_DBG("\033[36;22m ssid: %-32.*s security: %-s\r\n", 32, scan_rst_table[i].ssid, wlan_sec_type_string[scan_rst_table[i].security]); - - switch (scan_rst_table[i].security) - { - case BK_SECURITY_TYPE_NONE: - _scan_result->info[i].security = SECURITY_OPEN; - break; - - case BK_SECURITY_TYPE_WEP: - _scan_result->info[i].security = SECURITY_WEP_PSK; - break; - - case BK_SECURITY_TYPE_WPA_TKIP: - _scan_result->info[i].security = SECURITY_WPA_TKIP_PSK; - break; - - case BK_SECURITY_TYPE_WPA_AES: - _scan_result->info[i].security = SECURITY_WPA_AES_PSK; - break; - - case BK_SECURITY_TYPE_WPA2_TKIP: - _scan_result->info[i].security = SECURITY_WPA2_TKIP_PSK; - break; - - case BK_SECURITY_TYPE_WPA2_AES: - _scan_result->info[i].security = SECURITY_WPA2_AES_PSK; - break; - - case BK_SECURITY_TYPE_WPA2_MIXED: - _scan_result->info[i].security = SECURITY_WPA2_MIXED_PSK; - break; - - case BK_SECURITY_TYPE_AUTO: - // _scan_result.ap_table[i]->security = SECURITY_WEP_PSK; - break; - default: - break; - } - _scan_result->info[i].rssi = scan_rst_table[i].level; - } - DRV_WLAN_DBG("\033[0m\r\n"); - - if (scan_rst_table != NULL) - { - os_free(scan_rst_table); - scan_rst_table = NULL; - } - - return OS_SUCCESS; -} - -extern int wpa_get_psk(char *psk); -int _wifi_connect_done(void *ctx) -{ -#if 0 - LinkStatusTypeDef link_status; - struct wlan_fast_connect ap_info; - - memset(&link_status, 0, sizeof(LinkStatusTypeDef)); - memset(&ap_info, 0, sizeof(struct wlan_fast_connect)); - if (_g_sta_info.mode == NORMAL_MODE) - { - if ((bk_wlan_get_link_status(&link_status) == kNoErr) && (BK_SECURITY_TYPE_WEP != link_status.security)) - { - memcpy(ap_info.ssid, link_status.ssid, strnlen(link_status.ssid, 32)); - memcpy(ap_info.bssid, link_status.bssid, 6); - ap_info.channel = link_status.channel; - ap_info.security = link_status.security; - wpa_get_psk(ap_info.psk); - wlan_fast_connect_info_write(&ap_info); - } - } -#endif - -#ifdef BEKEN_USING_WLAN_STA - _g_sta_info.state = CONNECT_DONE; -#endif - - return 0; -} - -#if 0 -static int _wifi_power_manager(int level) -{ - return 0; -} -#else -extern int bk_wlan_dtim_rf_ps_timer_start(void); -extern int bk_wlan_dtim_rf_ps_timer_pause(void); -static int _wifi_power_manager(int level) -{ - switch (level) - { - case 0: - { - #if CFG_USE_MCU_PS - /* disable cpu sleep */ - bk_wlan_mcu_ps_mode_disable(); - #endif - #if CFG_USE_STA_PS - /* disable rf sleep */ - bk_wlan_dtim_rf_ps_mode_disable(); - /* pause rf timer */ - bk_wlan_dtim_rf_ps_timer_pause(); - #endif - break; - } - - case 1: - { - #if CFG_USE_MCU_PS - /* enable cpu sleep */ - bk_wlan_mcu_ps_mode_enable(); - #endif - #if CFG_USE_STA_PS - /* disable rf sleep */ - bk_wlan_dtim_rf_ps_mode_disable(); - /* pause rf timer */ - bk_wlan_dtim_rf_ps_timer_pause(); - #endif - break; - } - case 2: - { - #if CFG_USE_MCU_PS - /* disable cpu sleep */ - bk_wlan_mcu_ps_mode_disable(); - #endif - #if CFG_USE_STA_PS - /* enable rf sleep */ - bk_wlan_dtim_rf_ps_mode_enable(); - /* start rf timer */ - bk_wlan_dtim_rf_ps_timer_start(); - #endif - break; - } - - case 3: - { - #if CFG_USE_MCU_PS - /* enable cpu sleep */ - bk_wlan_mcu_ps_mode_enable(); - #endif - #if CFG_USE_STA_PS - /* enable rf sleep */ - bk_wlan_dtim_rf_ps_mode_enable(); - /* start rf timer */ - bk_wlan_dtim_rf_ps_timer_start(); - #endif - break; - } - - default: - break; - } -} -#endif - -#if LWIP_IPV4 && LWIP_IGMP -static err_t igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, u8_t action) -{ - uint8_t mac[6]; - const uint8_t *p = (const uint8_t *)ip4_addr; - - mac[0] = 0x01; - mac[1] = 0x00; - mac[2] = 0x5E; - mac[3] = *(p + 1) & 0x7F; - mac[4] = *(p + 2); - mac[5] = *(p + 3); - - if (1) - { - DRV_WLAN_DBG("%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip4addr_ntoa(ip4_addr)); - DRV_WLAN_DBG("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } - - //wifi_add_mcast_filter(mac); - - return 0; -} -#endif /* LWIP_IPV4 && LWIP_IGMP */ - -#if LWIP_IPV6 && LWIP_IPV6_MLD -static err_t mld_mac_filter(struct netif *netif, const ip6_addr_t *ip6_addr, u8_t action) -{ - uint8_t mac[6]; - const uint8_t *p = (const uint8_t *)&ip6_addr->addr[3]; - - mac[0] = 0x33; - mac[1] = 0x33; - mac[2] = *(p + 0); - mac[3] = *(p + 1); - mac[4] = *(p + 2); - mac[5] = *(p + 3); - - if (1) - { - DRV_WLAN_DBG("%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip6addr_ntoa(ip6_addr)); - DRV_WLAN_DBG("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } - - //wifi_add_mcast_filter(mac); - - return 0; -} -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ - - -static os_err_t beken_wlan_init(struct os_wlan_device *wlan ) -{ -#if 0 - struct eth_device *eth = (struct eth_device *)dev; -#if LWIP_IPV4 && LWIP_IGMP - netif_set_igmp_mac_filter(eth->netif, igmp_mac_filter); -#endif /* LWIP_IPV4 && LWIP_IGMP */ - -#if LWIP_IPV6 && LWIP_IPV6_MLD - netif_set_mld_mac_filter(eth->netif, mld_mac_filter); -#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ -#endif - /* Initialize semaphore for scan */ - _g_scan_done_sem = os_semaphore_create(OS_NULL, "scan_done", 0, 1); - - return OS_SUCCESS; -} - -static os_err_t beken_wlan_set_mode(struct os_wlan_device *wlan, os_wlan_mode_t mode) -{ - - return OS_SUCCESS; -} - -static os_err_t beken_wlan_scan(struct os_wlan_device *wlan, struct os_scan_info *scan_info) -{ - os_err_t ret = OS_SUCCESS; - struct os_wlan_scan_result *scan_result = os_wlan_scan_get_result(); - - bk_wlan_scan_ap_reg_cb(scan_ap_callback); - DRV_WLAN_DBG("%s L%d %s cmd: case WIFI_SCAN!\r\n", __FILE__, __LINE__, __FUNCTION__); - - if (os_strlen(scan_info->ssid.val) > 0) - { - UINT8 *ssid_ary[1]; - ssid_ary[0] = scan_info->ssid.val; - bk_wlan_start_assign_scan(ssid_ary, 1); - } - else - { - bk_wlan_start_scan(); - } - - if (os_semaphore_wait(_g_scan_done_sem, os_tick_from_ms(SCAN_WAIT_OUT_TIME)) != OS_SUCCESS) - { - DRV_WLAN_DBG("Wait scan_done semaphore timeout \n"); - } - - ret = wlan_scan_done_handler((struct os_wlan_scan_result **)&scan_result); - os_wlan_dev_indicate_event_handle(wlan,OS_WLAN_DEV_EVT_SCAN_DONE,OS_NULL); - -#if CFG_ROLE_LAUNCH - if(mhdr_get_station_status() == RW_EVT_STA_GOT_IP) - { - rl_pre_sta_set_status(RL_STATUS_STA_LAUNCHED); - } -#endif - - return ret; -} - -static os_err_t beken_wlan_scan_stop(struct os_wlan_device *wlan) -{ - extern int bk_wlan_stop_scan(void); - - return bk_wlan_stop_scan(); -} - - -static os_err_t beken_wlan_join(struct os_wlan_device *wlan, struct os_sta_info *sta_info) -{ - int ret = OS_SUCCESS; -#ifdef BEKEN_USING_WLAN_STA /* needed only by station */ - network_InitTypeDef_st wNetConfig; - const char *ssid = OS_NULL; - const uint8_t *bssid = OS_NULL; - int len; - - start_connect_tick = os_tick_get(); - DRV_WLAN_DBG("beken_wlan_join: start connect \n"); - _g_sta_info.mode = NORMAL_MODE; - _g_sta_info.state = CONNECT_DOING; - ssid = (char *)sta_info->ssid.val; - bssid = (char *)sta_info->bssid; - os_memset(&wNetConfig, 0x0, sizeof(network_InitTypeDef_st)); - - if ((ssid != NULL) && ('\0' != *ssid)) - { - len = os_strlen(ssid); - if (SSID_MAX_LEN < len) - { - DRV_WLAN_DBG("ssid name more than 32 Bytes\r\n"); - return -OS_FAILURE; - } - - os_strncpy((char *)wNetConfig.wifi_ssid, ssid, sizeof(wNetConfig.wifi_ssid)); - } -#if CFG_SUPPOET_BSSID_CONNECT - else if (((bssid[0] != 0xFF) - || (bssid[1] != 0xFF) - || (bssid[2] != 0xFF) - || (bssid[3] != 0xFF) - || (bssid[4] != 0xFF) - || (bssid[5] != 0xFF)) - && ((bssid[0] != 0x0) - || (bssid[1] != 0x0) - || (bssid[2] != 0x0) - || (bssid[3] != 0x0) - || (bssid[4] != 0x0) - || (bssid[5] != 0x0))) - { - os_memcpy((void *)wNetConfig.wifi_bssid, bssid, sizeof(wNetConfig.wifi_bssid)); - } -#endif - else - { - DRV_WLAN_DBG("ssid is null or bssid is invalid/disabled\r\n"); - return -OS_FAILURE; - } - - - if (sizeof(wNetConfig.wifi_key) < os_strlen(sta_info->key.val)) - { - DRV_WLAN_DBG("wifi key is more than %d Bytes\r\n", sizeof(wNetConfig.wifi_key)); - return -OS_FAILURE; - } - os_strncpy((char *)wNetConfig.wifi_key,(char *)sta_info->key.val,sizeof(wNetConfig.wifi_key)); - - - wNetConfig.wifi_mode = BK_STATION; - wNetConfig.dhcp_mode = DHCP_CLIENT; - wNetConfig.wifi_retry_interval = 100; - - DRV_WLAN_DBG("beken_wlan_join: ssid:%.*s bssid:%02x:%02x:%02x:%02x:%02x:%02x key:%.*s\r\n", - sizeof(wNetConfig.wifi_ssid), wNetConfig.wifi_ssid, - bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5], - sizeof(wNetConfig.wifi_key), wNetConfig.wifi_key); - ret = bk_wlan_start(&wNetConfig); - if(OS_SUCCESS == ret) - g_sta_status = 1; -#endif - - return ret; -} - -void beken_wlan_set_ap_ip(const char* ip) -{ - if (strlen(ip) > 15) - { - DRV_WLAN_DBG("beken_wlan_set_ap_ip to set ap ip[%s] too long, please check\r\n", ip); - return; - } - - memset((void *)DHCPD_SERVER_IP, sizeof(gs_dhcpd_server_ip), 0); - strcpy(DHCPD_SERVER_IP, ip); -} - -static os_err_t beken_wlan_softap(struct os_wlan_device *wlan, struct os_ap_info *ap_info) -{ - int ret = OS_SUCCESS; -#ifdef BEKEN_USING_WLAN_AP /* needed only by ap */ - network_InitTypeDef_st wNetConfig; - const char *ssid = OS_NULL; - int len; - - ssid = (char *)ap_info->ssid.val; - os_memset(&wNetConfig, 0x0, sizeof(network_InitTypeDef_st)); - - if (ssid == NULL) - { - DRV_WLAN_DBG("ssid is null\r\n"); - return -OS_FAILURE; - } - - len = os_strlen(ssid); - if (SSID_MAX_LEN < len) - { - DRV_WLAN_DBG("ssid name more than 32 Bytes\r\n"); - /* continue to use 32 bytes ssid, do not return err */ - len = SSID_MAX_LEN; - } - os_strncpy((char *)wNetConfig.wifi_ssid, ssid, sizeof(wNetConfig.wifi_ssid)); - - if (sizeof(wNetConfig.wifi_key) < os_strlen(ap_info->key.val)) - { - DRV_WLAN_DBG("wifi key is more than %d Bytes\r\n", sizeof(wNetConfig.wifi_key)); - return -OS_FAILURE; - } - os_strncpy((char *)wNetConfig.wifi_key,(char *)ap_info->key.val,sizeof(wNetConfig.wifi_key)); - - - wNetConfig.wifi_mode = BK_SOFT_AP; - wNetConfig.dhcp_mode = DHCP_SERVER; - wNetConfig.wifi_retry_interval = 100; - - os_strcpy((char *)wNetConfig.local_ip_addr, DHCPD_SERVER_IP); - os_strcpy((char *)wNetConfig.net_mask, "255.255.255.0"); - os_strcpy((char *)wNetConfig.gateway_ip_addr, DHCPD_SERVER_IP); - os_strcpy((char *)wNetConfig.dns_server_ip_addr, DHCPD_SERVER_IP); - - DRV_WLAN_DBG("_wifi_softap: ssid:%.*s key:%.*s\r\n", sizeof(wNetConfig.wifi_ssid), wNetConfig.wifi_ssid, sizeof(wNetConfig.wifi_key), wNetConfig.wifi_key); - - ret = bk_wlan_start(&wNetConfig); - - if(OS_SUCCESS == ret) - g_ap_status = 1; -#endif - return ret; -} - -static os_err_t beken_wlan_disconnect(struct os_wlan_device *wlan) -{ - os_wlan_mode_t mode; - -#if CFG_ROLE_LAUNCH - LAUNCH_REQ param; -#endif - - mode = wlan->mode; - - if (mode == OS_WLAN_STATION) - { - if(g_sta_status) - { -#if CFG_ROLE_LAUNCH - param.req_type = LAUNCH_REQ_DELIF_STA; - rl_sta_request_enter(¶m, 0); -#else - bk_wlan_stop(BK_STATION); -#endif - g_sta_status = 0; - } - else - { - os_wlan_dev_indicate_event_handle(&_g_sta_device, OS_WLAN_DEV_EVT_DISCONNECT, OS_NULL); - } - } - else if (mode == OS_WLAN_AP) - { - if(g_ap_status) - { - bk_wlan_stop(BK_SOFT_AP); - dhcp_server_stop(); - g_ap_status = 0; - } - else - { - os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_STOP, OS_NULL); - } - } - - return OS_SUCCESS; -} - - -static os_err_t beken_wlan_set_channel (struct os_wlan_device *wlan, int channel) -{ - return bk_wlan_set_channel(channel); -} - -static int beken_wlan_get_channel(struct os_wlan_device *wlan) -{ - extern int bk_wlan_get_channel(void); - - return bk_wlan_get_channel(); -} - -static os_err_t beken_wlan_set_mac(struct os_wlan_device *wlan, uint8_t mac[]) -{ - return wifi_set_mac_address(mac); -} - -static os_err_t beken_wlan_get_mac(struct os_wlan_device *wlan, uint8_t mac[]) -{ - int result = OS_SUCCESS; - struct beken_wifi_info *wifi_info = OS_NULL; - - wifi_info = (struct beken_wifi_info *)wlan->user_data; - - /* get MAC address */ - if (mac) - os_memcpy(mac, wifi_info->mac, 6); - else - result = OS_FAILURE; - - return result; -} - -int beken_wlan_get_rssi(struct os_wlan_device *wlan) -{ - return g_beken_rssi; -} - -os_err_t beken_wlan_set_country(struct os_wlan_device *wlan, os_country_code_t country_code) -{ - wifi_country_t *country; - - if(OS_COUNTRY_CHINA == country_code) - country = &country_code_CN; - else if(OS_COUNTRY_UNITED_STATES == country_code) - country = &country_code_US; - else if(OS_COUNTRY_GERMANY == country_code) - country = &country_code_EP; - else if(OS_COUNTRY_JAPAN == country_code) - country = &country_code_JP; - else - return OS_FAILURE; - - return bk_wlan_set_country(country); -} - -os_country_code_t beken_wlan_get_country(struct os_wlan_device *wlan) -{ - int result = OS_SUCCESS; - wifi_country_t country; - os_country_code_t country_code = 0; - - result = bk_wlan_get_country(&country); - if(OS_SUCCESS!= result) - return country_code; - - if("CN" == country.cc) - country_code = OS_COUNTRY_CHINA; - else if("US" == country.cc) - country_code = OS_COUNTRY_UNITED_STATES; - else if("EP" == country.cc) - country_code = OS_COUNTRY_GERMANY; - else if("JP" == country.cc) - country_code = OS_COUNTRY_JAPAN; - - return country_code; -} - -os_err_t beken_wlan_set_powersave(struct os_wlan_device *wlan, int level) -{ - return bk_wlan_power_save_set_level(level); -} - -int beken_wlan_get_powersave(struct os_wlan_device *wlan) -{ - extern BK_PS_LEVEL global_ps_level; - - return global_ps_level; -} - -static int beken_wlan_send_raw_frame(struct os_wlan_device *wlan, void *buff, int len) -{ - return bk_wlan_send_80211_raw_frame(buff,len); -} - - -static int beken_wlan_send(struct os_wlan_device *wlan, void *buff, int len) -{ - struct netif *netif = os_wlan_get_netif(wlan); - - return low_level_output(netif, (struct pbuf*)buff); -} - -static int beken_wlan_recv(struct os_wlan_device *wlan, void *buff, int len) -{ - return OS_SUCCESS; -} - - -static void app_demo_softap_rw_connected_event_func(void) -{ - os_kprintf("--------wlan ap [no password] connected event callback ----------\r\n"); -} - - -/*=================================================================================*/ -const static struct os_wlan_dev_ops beken_wlan_ops = -{ - .wlan_init = beken_wlan_init, //os_err_t (*wlan_init)(struct os_wlan_device *wlan); - .wlan_mode = beken_wlan_set_mode, //os_err_t (*wlan_mode)(struct os_wlan_device *wlan, os_wlan_mode_t mode); - .wlan_scan = beken_wlan_scan, //os_err_t (*wlan_scan)(struct os_wlan_device *wlan, struct os_scan_info *scan_info); - .wlan_join = beken_wlan_join, //os_err_t (*wlan_join)(struct os_wlan_device *wlan, struct os_sta_info *sta_info); - .wlan_softap = beken_wlan_softap, //os_err_t (*wlan_softap)(struct os_wlan_device *wlan, struct os_ap_info *ap_info); - .wlan_disconnect = beken_wlan_disconnect, //os_err_t (*wlan_disconnect)(struct os_wlan_device *wlan); - .wlan_ap_stop = beken_wlan_disconnect, //os_err_t (*wlan_ap_stop)(struct os_wlan_device *wlan); - .wlan_ap_deauth = OS_NULL, //os_err_t (*wlan_ap_deauth)(struct os_wlan_device *wlan, uint8_t mac[]); - .wlan_scan_stop = beken_wlan_scan_stop, //os_err_t (*wlan_scan_stop)(struct os_wlan_device *wlan); - .wlan_get_rssi = beken_wlan_get_rssi, //int (*wlan_get_rssi)(struct os_wlan_device *wlan); - .wlan_set_powersave = beken_wlan_set_powersave, //os_err_t (*wlan_set_powersave)(struct os_wlan_device *wlan, int level); - .wlan_get_powersave = beken_wlan_get_powersave, //int (*wlan_get_powersave)(struct os_wlan_device *wlan); - .wlan_cfg_promisc = OS_NULL, //os_err_t (*wlan_cfg_promisc)(struct os_wlan_device *wlan, os_bool_t start); - .wlan_cfg_filter = OS_NULL, //os_err_t (*wlan_cfg_filter)(struct os_wlan_device *wlan, struct os_wlan_filter *filter); - .wlan_cfg_mgnt_filter = OS_NULL, //os_err_t (*wlan_cfg_mgnt_filter)(struct os_wlan_device *wlan, os_bool_t start); - .wlan_set_channel = beken_wlan_set_channel, //os_err_t (*wlan_set_channel)(struct os_wlan_device *wlan, int channel); - .wlan_get_channel = beken_wlan_get_channel, //int (*wlan_get_channel)(struct os_wlan_device *wlan); - .wlan_set_country = beken_wlan_set_country, //os_err_t (*wlan_set_country)(struct os_wlan_device *wlan, os_country_code_t country_code); - .wlan_get_country = beken_wlan_get_country, //os_country_code_t (*wlan_get_country)(struct os_wlan_device *wlan); - .wlan_set_mac = beken_wlan_set_mac, //os_err_t (*wlan_set_mac)(struct os_wlan_device *wlan, uint8_t mac[]); - .wlan_get_mac = beken_wlan_get_mac, //os_err_t (*wlan_get_mac)(struct os_wlan_device *wlan, uint8_t mac[]); - .wlan_recv = beken_wlan_recv, //int (*wlan_recv)(struct os_wlan_device *wlan, void *buff, int len); -#ifdef OS_WLAN_PROT_LWIP_PBUF_FORCE /* send pbuf links or a packet */ - .wlan_send = OS_NULL,//beken_wlan_send, -#else - .wlan_send = OS_NULL,//beken_wlan_send_raw_frame, //int (*wlan_send)(struct os_wlan_device *wlan, void *buff, int len); -#endif - .wlan_send_raw_frame = OS_NULL,//beken_wlan_send_raw_frame, //int (*wlan_send_raw_frame)(struct os_wlan_device *wlan, void *buff, int len); -}; - - -/* register wlan device */ -static int beken_wlan_probe(const os_driver_info_t *drv, const os_device_info_t *dev) -{ - struct os_wlan_device *wlan = OS_NULL; - struct beken_wifi_info *wifi_info = OS_NULL; - struct beken_wifi_info *wifi_info_tmp = OS_NULL; - os_err_t result = OS_SUCCESS; - char temp_mac[6]; - - wifi_info_tmp = (struct beken_wifi_info *)dev->info; - - // load mac, init mac first - wifi_get_mac_address(temp_mac, CONFIG_ROLE_NULL); - -if (OS_WLAN_STATION == wifi_info_tmp->work_mode) -{ -#ifdef BEKEN_USING_WLAN_STA - wlan = &_g_sta_device; - wifi_info = &_g_sta_info; - wifi_get_mac_address(wifi_info->mac, CONFIG_ROLE_STA); - wifi_info->work_mode = wifi_info_tmp->work_mode; - wlan->mode = wifi_info_tmp->work_mode; - - result = os_wlan_dev_register(wlan, dev->name,&beken_wlan_ops,OS_WLAN_FLAG_STA_ONLY,wifi_info); - if (result != OS_SUCCESS) - { - DRV_WLAN_DBG("register station wlan device failed! \n"); - } - DRV_WLAN_DBG("register station wlan device sucess! \n"); -#endif -} -else -{ -#ifdef BEKEN_USING_WLAN_AP - wlan = &_g_ap_device; - wifi_info = &_g_ap_info; - wifi_get_mac_address(wifi_info->mac, CONFIG_ROLE_AP); - wifi_info->work_mode = wifi_info_tmp->work_mode; - wlan->mode = wifi_info_tmp->work_mode; - - result = os_wlan_dev_register(wlan, dev->name,&beken_wlan_ops,OS_WLAN_FLAG_AP_ONLY,wifi_info); - if (result != OS_SUCCESS) - { - DRV_WLAN_DBG("register soft-ap wlan device failed! \n"); - } - DRV_WLAN_DBG("register soft-ap wlan device sucess! \n"); - - //bk_ap_no_password_connected_register_cb(app_demo_softap_rw_connected_event_func); -#endif -} - - bk_wlan_status_register_cb(wlan_event_handle); - DRV_WLAN_DBG("beken wlan hw init\r\n"); - - return 0; -} - - -OS_DRIVER_INFO beken_wlan_driver = { - .name = "Wlan_Type", - .probe = beken_wlan_probe, -}; -OS_DRIVER_DEFINE(beken_wlan_driver, OS_INIT_LEVEL_DEVICE, OS_INIT_SUBLEVEL_LOW); - -/* init protocol and register to LWIP */ -static int beken_wlan_prot_init(void) -{ - os_device_t* device = OS_NULL; - struct os_wlan_device* wlan = OS_NULL; - struct netif* netif = OS_NULL; - - os_enter_critical(); - os_ubase_t level = os_hw_interrupt_disable(); - - app_start(); - /* set wifi work mode */ -#ifdef BEKEN_USING_WLAN_STA - os_wlan_set_mode(OS_WLAN_DEVICE_STA_NAME, OS_WLAN_STATION); - - { // beken LWIP special modifications - device = os_device_find(OS_WLAN_DEVICE_STA_NAME); - wlan = (struct os_wlan_device *)device; - netif = os_wlan_get_netif(wlan); - netif->linkoutput =(netif_linkoutput_fn)low_level_output; - } -#endif - -#ifdef BEKEN_USING_WLAN_AP - os_wlan_set_mode(OS_WLAN_DEVICE_AP_NAME, OS_WLAN_AP); - - { // beken LWIP special modifications - device = os_device_find(OS_WLAN_DEVICE_AP_NAME); - wlan = (struct os_wlan_device *)device; - netif = os_wlan_get_netif(wlan); - netif->linkoutput =(netif_linkoutput_fn)low_level_output; - } -#endif - os_hw_interrupt_enable(level); - os_exit_critical(); - - return 0; -} -OS_INIT_CALL(beken_wlan_prot_init, OS_INIT_LEVEL_APPLICATION); -// eof +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_wlan.c + * + * @brief This file implements wlan driver for beken + * + * @revision + * Date Author Notes + * 2020-12-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include "include.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include + +#include +#include +#include "netif/etharp.h" +#include "lwip_netif_address.h" +#include "sa_station.h" +#include "drv_model_pub.h" +#include "mem_pub.h" +#include "common.h" +#include "hostapd_cfg.h" + +#include "sk_intf.h" +#include "rw_pub.h" +#include "error.h" +#include "rtos_pub.h" +#include "param_config.h" +#include "wlan_ui_pub.h" + +#include +#include +#include +#include "os_types.h" +#include "bus.h" +#include "os_errno.h" +#include + +#include "drv_flash.h" +#include "drv_wlan.h" +#include "drv_wlan_fast_connect.h" + +#include "uart_pub.h" +#include "ieee802_11_defs.h" +#include "wlan_ui_pub.h" +#include "net_param_pub.h" +#include "role_launch.h" +#include "app.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "wlan_dev" +#include + +#define ETH_INTF_DEBUG 0 +#if ETH_INTF_DEBUG +#define ETH_INTF_PRT warning_prf +#define ETH_INTF_WARN warning_prf +#define ETH_INTF_FATAL fatal_prf +#else +#define ETH_INTF_PRT null_prf +#define ETH_INTF_WARN null_prf +#define ETH_INTF_FATAL null_prf +#endif + +#define OS_WLAN_DEVICE(eth) (struct os_wlan_device *)(eth) + +struct os_wlan_buff +{ + void *data; + uint32_t len; +}; + +struct eth_device +{ + /* inherit from os_device */ + struct os_device parent; + + /* network interface for lwip */ + struct netif *netif; + + uint16_t flags; + uint8_t link_changed; + uint8_t link_status; + + /* eth device interface */ + struct pbuf *(*eth_rx)(os_device_t *dev); + os_err_t (*eth_tx)(os_device_t *dev, struct pbuf *p); +}; + +static char gs_dhcpd_server_ip[16] = "192.168.169.1"; +char* DHCPD_SERVER_IP = gs_dhcpd_server_ip; + +#ifdef BSP_USING_BK_STA +struct os_wlan_device wlan_sta_dev; +#endif + +#ifdef BSP_USING_BK_AP +struct os_wlan_device wlan_ap_dev; +#endif + +#define RT_WLAN_SSID_MAX_LEN 32 +#define SCAN_WAIT_OUT_TIME 2000 +static os_semaphore_id _g_scan_done_sem; +int start_connect_tick = 0; +int end_connect_tick = 0; +int g_beken_rssi = 0; + +static int g_sta_status = 0; +static int g_ap_status = 0; + + +static wifi_country_t country_code_CN = {.cc= "CN", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; +static wifi_country_t country_code_US = {.cc= "US", .schan=1, .nchan=11, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; +static wifi_country_t country_code_EP = {.cc= "EP", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; +static wifi_country_t country_code_JP = {.cc= "JP", .schan=1, .nchan=14, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; +static wifi_country_t country_code_AU = {.cc= "AU", .schan=1, .nchan=13, .max_tx_power=0, .policy=WIFI_COUNTRY_POLICY_MANUAL}; + + +static os_err_t _wifi_easyjoin(os_device_t *dev, void *passwd); +static os_err_t beken_wlan_disconnect(struct os_wlan_device *wlan); + +extern void *net_get_sta_handle(void); +extern void *net_get_uap_handle(void); +extern void wifi_get_mac_address(char *mac, u8 type); +extern void *net_get_netif_handle(uint8_t iface); +extern int bmsg_tx_sender(struct pbuf *p, uint32_t vif_idx); +extern void bk_wlan_status_register_cb(FUNC_1PARAM_PTR cb); +extern void dhcp_server_stop(void); +extern int wifi_set_mac_address(char *mac); +extern rw_evt_type mhdr_get_station_status(void); +extern os_bool_t os_wlan_is_connected(void); +extern os_bool_t os_wlan_ap_is_active(void); +extern int bk_wlan_power_save_set_level(BK_PS_LEVEL level); + + + +//#define MINI_DUMP +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +static void packet_dump(const char *msg, const struct pbuf *p) +{ + const struct pbuf *q; + uint32_t i, j; + uint8_t *ptr; + + os_kprintf("%s %d byte\n", msg, p->tot_len); + +#ifdef MINI_DUMP + return; +#endif + + i = 0; + for (q = p; q != OS_NULL; q = q->next) + { + ptr = q->payload; + + for (j = 0; j < q->len; j++) + { + if ((i % 8) == 0) + { + os_kprintf(" "); + } + if ((i % 16) == 0) + { + os_kprintf("\r\n"); + } + os_kprintf("%02x ", *ptr); + + i++; + ptr++; + } + } + + os_kprintf("\n\n"); +} +#endif /* dump */ + +static os_err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + int ret; + err_t err = ERR_OK; + uint8_t vif_idx = rwm_mgmt_get_netif2vif(netif); + +#ifdef ETH_TX_DUMP + packet_dump("TX dump", p); +#endif /* ETH_TX_DUMP */ + + if (!netif_is_link_up(netif)) + { + return ERR_IF; + } + + ret = bmsg_tx_sender(p, (uint32_t)vif_idx); + if (0 != ret) + { + err = ERR_TIMEOUT; + } + + return err; +} + +struct os_lwip_info +{ + struct netif netif; + struct os_net_device *net_dev; + os_list_node_t list; +}; + + +struct netif* os_wlan_get_netif(struct os_wlan_device *wlan) +{ + struct os_lwip_info *lwip_info = (struct os_lwip_info *)wlan->net_dev.userdata; + + OS_ASSERT(lwip_info != OS_NULL); + + return &lwip_info->netif; +} + +/** + * OS LwIP Interface &bk_wlan_dev->wlan_sta_dev + */ + +struct netif *wlan_get_sta_netif(void) +{ +#ifdef BSP_USING_BK_STA + return os_wlan_get_netif(&wlan_sta_dev); +#else + return OS_NULL; +#endif +} + +struct netif *wlan_get_uap_netif(void) +{ +#ifdef BSP_USING_BK_AP + return os_wlan_get_netif(&wlan_ap_dev); +#else + return OS_NULL; +#endif +} + +void ethernetif_input(int iface, struct pbuf *p) +{ + struct eth_hdr *ethhdr = OS_NULL; + struct netif *netif = OS_NULL; + struct os_wlan_device *dev = OS_NULL; + +#ifdef ETH_RX_DUMP + packet_dump("RX dump", p); +#endif /* ETH_RX_DUMP */ + + if (p->len <= SIZEOF_ETH_HDR) + { + pbuf_free(p); + return; + } + + netif = rwm_mgmt_get_vif2netif((uint8_t)iface); + if (!netif) + { + pbuf_free(p); + p = NULL; + return; + } + +#ifdef BSP_USING_BK_STA + if(netif == wlan_get_sta_netif()) + dev = &wlan_sta_dev; +#endif +#ifdef BSP_USING_BK_AP + else if(netif == wlan_get_uap_netif()) + dev = &wlan_ap_dev; +#endif + + if (!dev) + { + LOG_E(DRV_EXT_TAG, "ethernetif_input no wlan device found %d\r\n", iface); + pbuf_free(p); + p = NULL; + return; + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + + switch (htons(ethhdr->type)) + { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if(os_wlan_report_data(dev,p->payload, p->tot_len) != ERR_OK) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\r\n")); + } + + pbuf_free(p); + p = NULL; + break; + + case 0x888EU: + ke_l2_packet_tx(p->payload, p->len, iface); + pbuf_free(p); + p = NULL; + break; + + default: + pbuf_free(p); + p = NULL; + break; + } +} + +// wlan event callbacks +static void wlan_event_handle(void *ctx) +{ + rw_evt_type event = *((rw_evt_type*)ctx); + + struct os_wlan_info info; + struct os_wlan_buff user_buff; + + if ((event < 0) || (event > RW_EVT_MAX)) + { + return; + } + + LOG_D(DRV_EXT_TAG, "===wlan_event_handle:%d===\r\n",event); + switch (event) + { +#ifdef BSP_USING_BK_STA + case RW_EVT_STA_CONNECTED: + end_connect_tick = os_tick_get_value(); + LOG_E(DRV_EXT_TAG, "[wlan_connect]:start tick = %d, connect done tick = %d, total = %d \n", start_connect_tick, end_connect_tick, end_connect_tick - start_connect_tick); + os_wlan_event_callback(&wlan_sta_dev, OS_WLAN_EVET_JOIN, OS_NULL); + break; + + case RW_EVT_STA_DISCONNECTED: + LOG_E(DRV_EXT_TAG,"connect fail"); + os_wlan_event_callback(&wlan_sta_dev, OS_WLAN_EVET_LEAVE, OS_NULL); + break; + + case RW_EVT_STA_CONNECT_FAILED: + case RW_EVT_STA_PASSWORD_WRONG: + case RW_EVT_STA_NO_AP_FOUND: + break; +#endif + +#ifdef BSP_USING_BK_AP + case RW_EVT_AP_CONNECTED: + user_buff.data = &info; + user_buff.len = sizeof(struct os_wlan_info); + break; + + case RW_EVT_AP_DISCONNECTED: + user_buff.data = &info; + user_buff.len = sizeof(struct os_wlan_info); + break; + + case RW_EVT_AP_CONNECT_FAILED: + break; + + case RW_EVT_AP_START_COMPLETE: + os_wlan_event_callback(&wlan_ap_dev, OS_WLAN_EVET_AP_START, OS_NULL); + break; + + case RW_EVT_AP_STOP_COMPLETE: + os_wlan_event_callback(&wlan_ap_dev, OS_WLAN_EVET_AP_STOP, OS_NULL); + break; +#endif + + default: + break; + } +} +static void scan_ap_callback(void *ctxt, uint8_t param) +{ + if (_g_scan_done_sem) + { + os_semaphore_post(_g_scan_done_sem); + LOG_D(DRV_EXT_TAG, "release scan done semaphore \n"); + } +} + +static int os_wlan_malloc_scan_result(struct os_wlan_scan_result **scan_result, int num) +{ + struct os_wlan_scan_result *_scan_result; + int i; + int result = OS_SUCCESS; + + _scan_result = *scan_result; + + _scan_result->count = num; + _scan_result->scan_info = os_malloc(sizeof(struct os_wlan_info) * num); + if (_scan_result->scan_info == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "rt_scan_rst table malloc failed!\r\n"); + result = -OS_FAILURE; + goto _exit; + } + os_memset(_scan_result->scan_info, 0, sizeof(struct os_wlan_info) * num); + + return OS_SUCCESS; +_exit: + + if (_scan_result->scan_info) + { + os_free(_scan_result->scan_info); + _scan_result->scan_info = OS_NULL; + } + + return -OS_FAILURE; +} + +static const char *wlan_sec_type_string[] = +{ + "NONE", + "WEP", + "WPA-TKIP", + "WPA-AES", + "WPA2-TKIP", + "WPA2-AES", + "WPA2-MIX", + "AUTO" +}; + +extern int wpa_get_psk(char *psk); +int _wifi_connect_done(void *ctx) +{ +#ifdef BSP_USING_BK_STA + //_g_sta_info.state = CONNECT_DONE; +#endif + + return 0; +} + +extern int bk_wlan_dtim_rf_ps_timer_start(void); +extern int bk_wlan_dtim_rf_ps_timer_pause(void); + +static int _wifi_power_manager(int level) +{ + switch (level) + { + case 0: + { + #if CFG_USE_MCU_PS + /* disable cpu sleep */ + bk_wlan_mcu_ps_mode_disable(); + #endif + #if CFG_USE_STA_PS + /* disable rf sleep */ + bk_wlan_dtim_rf_ps_mode_disable(); + /* pause rf timer */ + bk_wlan_dtim_rf_ps_timer_pause(); + #endif + break; + } + + case 1: + { + #if CFG_USE_MCU_PS + /* enable cpu sleep */ + bk_wlan_mcu_ps_mode_enable(); + #endif + #if CFG_USE_STA_PS + /* disable rf sleep */ + bk_wlan_dtim_rf_ps_mode_disable(); + /* pause rf timer */ + bk_wlan_dtim_rf_ps_timer_pause(); + #endif + break; + } + case 2: + { + #if CFG_USE_MCU_PS + /* disable cpu sleep */ + bk_wlan_mcu_ps_mode_disable(); + #endif + #if CFG_USE_STA_PS + /* enable rf sleep */ + bk_wlan_dtim_rf_ps_mode_enable(); + /* start rf timer */ + bk_wlan_dtim_rf_ps_timer_start(); + #endif + break; + } + + case 3: + { + #if CFG_USE_MCU_PS + /* enable cpu sleep */ + bk_wlan_mcu_ps_mode_enable(); + #endif + #if CFG_USE_STA_PS + /* enable rf sleep */ + bk_wlan_dtim_rf_ps_mode_enable(); + /* start rf timer */ + bk_wlan_dtim_rf_ps_timer_start(); + #endif + break; + } + + default: + break; + } +} + +#if LWIP_IPV4 && LWIP_IGMP +static err_t igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, u8_t action) +{ + uint8_t mac[6]; + const uint8_t *p = (const uint8_t *)ip4_addr; + + mac[0] = 0x01; + mac[1] = 0x00; + mac[2] = 0x5E; + mac[3] = *(p + 1) & 0x7F; + mac[4] = *(p + 2); + mac[5] = *(p + 3); + + if (1) + { + LOG_D(DRV_EXT_TAG, "%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip4addr_ntoa(ip4_addr)); + LOG_D(DRV_EXT_TAG, "%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return 0; +} +#endif /* LWIP_IPV4 && LWIP_IGMP */ + +#if LWIP_IPV6 && LWIP_IPV6_MLD +static err_t mld_mac_filter(struct netif *netif, const ip6_addr_t *ip6_addr, u8_t action) +{ + uint8_t mac[6]; + const uint8_t *p = (const uint8_t *)&ip6_addr->addr[3]; + + mac[0] = 0x33; + mac[1] = 0x33; + mac[2] = *(p + 0); + mac[3] = *(p + 1); + mac[4] = *(p + 2); + mac[5] = *(p + 3); + + if (1) + { + LOG_D(DRV_EXT_TAG, "%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip6addr_ntoa(ip6_addr)); + LOG_D(DRV_EXT_TAG, "%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return 0; +} +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + +static os_err_t beken_wlan_init(void) +{ + /* Initialize semaphore for scan */ + _g_scan_done_sem = os_semaphore_create(OS_NULL, "scan_done", 0, 1); + + return OS_SUCCESS; +} + +static os_err_t beken_wlan_set_mode(struct os_wlan_device *wlan, os_net_mode_t mode) +{ + return OS_SUCCESS; +} + +static void wlan_scan_done_handler(struct os_wlan_scan_result *scan_result) +{ + struct sta_scan_res *scan_rst_table; + char scan_rst_ap_num = 0; + int i; + + scan_rst_ap_num = bk_wlan_get_scan_ap_result_numbers(); + if (scan_rst_ap_num == 0) + { + LOG_E(DRV_EXT_TAG, "NULL AP \r\n"); + return; + } + + LOG_D(DRV_EXT_TAG, "scan_rst_ap_num %d \r\n", scan_rst_ap_num); + + scan_rst_table = (struct sta_scan_res *)os_malloc(sizeof(struct sta_scan_res) * scan_rst_ap_num); + if (scan_rst_table == OS_NULL) + { + LOG_D(DRV_EXT_TAG, "scan_rst_table malloc failed!\r\n"); + return; + } + + bk_wlan_get_scan_ap_result(scan_rst_table, scan_rst_ap_num); + + scan_result->scan_info = (struct os_wlan_scan_info*)os_calloc(scan_rst_ap_num, sizeof(struct os_wlan_scan_info)); + + scan_result->count = scan_rst_ap_num; + + for (i = 0; i < scan_rst_ap_num; i++) + { + os_strncpy(scan_result->scan_info[i].ssid.val, scan_rst_table[i].ssid, RT_WLAN_SSID_MAX_LEN); + scan_result->scan_info[i].ssid.len = strlen(scan_rst_table[i].ssid); + os_memcpy(scan_result->scan_info[i].bssid, scan_rst_table[i].bssid, 6); + scan_result->scan_info[i].channel = scan_rst_table[i].channel; + scan_result->scan_info[i].signal_strength = scan_rst_table[i].level; + + LOG_I(DRV_EXT_TAG, "\033[36;22m ssid: %-32.*s security: %-s\r\n", 32, scan_rst_table[i].ssid, wlan_sec_type_string[scan_rst_table[i].security]); + + switch (scan_rst_table[i].security) + { + case BK_SECURITY_TYPE_NONE: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_OPEN; + break; + + case BK_SECURITY_TYPE_WEP: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WEP_PSK; + break; + + case BK_SECURITY_TYPE_WPA_TKIP: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA_TKIP_PSK; + break; + + case BK_SECURITY_TYPE_WPA_AES: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA_AES_PSK; + break; + + case BK_SECURITY_TYPE_WPA2_TKIP: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA2_TKIP_PSK; + break; + + case BK_SECURITY_TYPE_WPA2_AES: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA2_AES_PSK; + break; + + case BK_SECURITY_TYPE_WPA2_MIXED: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA2_MIXED_PSK; + break; + + default: + scan_result->scan_info[i].security = OS_WLAN_SECURITY_WPA_AES_PSK; + break; + } + } + + LOG_D(DRV_EXT_TAG, "\033[0m\r\n"); + + if (scan_rst_table != NULL) + { + os_free(scan_rst_table); + scan_rst_table = NULL; + } + + return; +} + +static os_err_t beken_wlan_scan(struct os_wlan_device *wlan, uint32_t msec, struct os_wlan_scan_result *scan_result) +{ + os_err_t ret = OS_SUCCESS; + + bk_wlan_scan_ap_reg_cb(scan_ap_callback); + LOG_D(DRV_EXT_TAG, "%s L%d %s cmd: case WIFI_SCAN!\r\n", __FILE__, __LINE__, __FUNCTION__); + + bk_wlan_start_scan(); + + if (os_semaphore_wait(_g_scan_done_sem, os_tick_from_ms(SCAN_WAIT_OUT_TIME)) != OS_SUCCESS) + { + LOG_D(DRV_EXT_TAG, "Wait scan_done semaphore timeout \n"); + } + + wlan_scan_done_handler(scan_result); + + +#if CFG_ROLE_LAUNCH + if(mhdr_get_station_status() == RW_EVT_STA_GOT_IP) + { + rl_pre_sta_set_status(RL_STATUS_STA_LAUNCHED); + } +#endif + + return ret; +} + +static os_err_t beken_wlan_scan_clean_result(struct os_wlan_device *wlan, struct os_wlan_scan_result *info) +{ + os_free(info->scan_info); + + return OS_SUCCESS; +} + +static os_err_t beken_wlan_scan_stop(struct os_wlan_device *wlan) +{ + extern int bk_wlan_stop_scan(void); + + return bk_wlan_stop_scan(); +} + + +os_err_t beken_wlan_sta_start(struct os_wlan_device *wlan_dev) +{ + return OS_SUCCESS; +} + +static os_err_t beken_wlan_join(struct os_wlan_device *wlan_dev) +{ + int ret = OS_SUCCESS; +#ifdef BSP_USING_BK_STA /* needed only by station */ + network_InitTypeDef_st wNetConfig; + const char *ssid = OS_NULL; + int len; + + start_connect_tick = os_tick_get_value(); + LOG_D(DRV_EXT_TAG, "beken_wlan_join: start connect \n"); + + ssid = (char *)wlan_dev->info.ssid; + + os_memset(&wNetConfig, 0x0, sizeof(network_InitTypeDef_st)); + + if ((ssid != NULL) && ('\0' != *ssid)) + { + len = os_strlen(ssid); + if (SSID_MAX_LEN < len) + { + LOG_E(DRV_EXT_TAG, "ssid name more than 32 Bytes\r\n"); + return -OS_FAILURE; + } + + os_strncpy((char *)wNetConfig.wifi_ssid, ssid, sizeof(wNetConfig.wifi_ssid)); + } + else + { + LOG_E(DRV_EXT_TAG, "ssid is null or bssid is invalid/disabled\r\n"); + return -OS_FAILURE; + } + + + if (sizeof(wNetConfig.wifi_key) < os_strlen(wlan_dev->info.password)) + { + LOG_E(DRV_EXT_TAG, "wifi key is more than %d Bytes\r\n", sizeof(wNetConfig.wifi_key)); + return -OS_FAILURE; + } + + os_strncpy((char *)wNetConfig.wifi_key,(char *)wlan_dev->info.password,sizeof(wNetConfig.wifi_key)); + + wNetConfig.wifi_mode = BK_STATION; + wNetConfig.dhcp_mode = DHCP_CLIENT; + wNetConfig.wifi_retry_interval = 100; + + LOG_D(DRV_EXT_TAG, "beken_wlan_join: ssid:%.*s key:%.*s\r\n", + sizeof(wNetConfig.wifi_ssid), wNetConfig.wifi_ssid, + sizeof(wNetConfig.wifi_key), wNetConfig.wifi_key); + + ret = bk_wlan_start(&wNetConfig); + if(OS_SUCCESS == ret) + g_sta_status = 1; +#endif + + return ret; +} + + +void beken_wlan_set_ap_ip(const char* ip) +{ + if (strlen(ip) > 15) + { + LOG_E(DRV_EXT_TAG, "beken_wlan_set_ap_ip to set ap ip[%s] too long, please check\r\n", ip); + return; + } + + memset((void *)DHCPD_SERVER_IP, sizeof(gs_dhcpd_server_ip), 0); + strcpy(DHCPD_SERVER_IP, ip); +} + +static os_err_t beken_wlan_disconnect(struct os_wlan_device *wlan) +{ + os_net_mode_t mode; + +#if CFG_ROLE_LAUNCH + LAUNCH_REQ param; +#endif + + mode = wlan->net_dev.info.mode; + + if (mode == net_dev_mode_sta) + { + if(g_sta_status) + { +#if CFG_ROLE_LAUNCH + param.req_type = LAUNCH_REQ_DELIF_STA; + rl_sta_request_enter(¶m, 0); +#else + bk_wlan_stop(BK_STATION); +#endif + g_sta_status = 0; + } + else + { + //os_wlan_dev_indicate_event_handle(&_g_sta_device, OS_WLAN_DEV_EVT_DISCONNECT, OS_NULL); + } + } + else if (mode == net_dev_mode_ap) + { + if(g_ap_status) + { + bk_wlan_stop(BK_SOFT_AP); + dhcp_server_stop(); + g_ap_status = 0; + } + else + { + //os_wlan_dev_indicate_event_handle(&_g_ap_device, OS_WLAN_DEV_EVT_AP_STOP, OS_NULL); + } + } + + return OS_SUCCESS; +} + + +static os_err_t beken_wlan_set_channel (struct os_wlan_device *wlan, int channel) +{ + if (channel < 1 || channel >13) + { + LOG_E(DRV_EXT_TAG, "unsupport channel.[1~13]\r\n"); + } + + return bk_wlan_set_channel(channel); +} + +static int beken_wlan_get_channel(struct os_wlan_device *wlan) +{ + extern int bk_wlan_get_channel(void); + + return bk_wlan_get_channel(); +} + +static os_err_t beken_wlan_set_mac(struct os_wlan_device *wlan, uint8_t mac[]) +{ + return wifi_set_mac_address(mac); +} + +static os_err_t beken_wlan_get_mac(struct os_wlan_device *wlan_dev, uint8_t *mac) +{ + wifi_get_mac_address(mac, CONFIG_ROLE_STA); + + return OS_SUCCESS; +} + +int beken_wlan_get_rssi(struct os_wlan_device *wlan) +{ + return g_beken_rssi; +} + +os_err_t beken_wlan_set_powersave(struct os_wlan_device *wlan, int level) +{ + return bk_wlan_power_save_set_level(level); +} + +int beken_wlan_get_powersave(struct os_wlan_device *wlan) +{ + extern BK_PS_LEVEL global_ps_level; + + return global_ps_level; +} + +static int beken_wlan_send_raw_frame(struct os_wlan_device *wlan, void *buff, int len) +{ + return bk_wlan_send_80211_raw_frame(buff,len); +} + +static int beken_wlan_send(struct os_wlan_device *wlan, void *buff) +{ + struct netif *netif = os_wlan_get_netif(wlan); + + return low_level_output(netif, (struct pbuf*)buff); +} + +static int beken_wlan_recv(struct os_wlan_device *wlan, void *buff, int len) +{ + return OS_SUCCESS; +} + + +static void app_demo_softap_rw_connected_event_func(void) +{ + os_kprintf("--------wlan ap [no password] connected event callback ----------\r\n"); +} + +static os_err_t beken_wlan_softap(struct os_wlan_device *wlan_dev) +{ + int ret = OS_SUCCESS; +#ifdef BSP_USING_BK_AP /* needed only by ap */ + network_InitTypeDef_st wNetConfig; + const char *ssid = OS_NULL; + int len; + + ssid = (char *)wlan_dev->info.ssid; + os_memset(&wNetConfig, 0x0, sizeof(network_InitTypeDef_st)); + + if (ssid == NULL) + { + LOG_E(DRV_EXT_TAG, "ssid is null\r\n"); + return -OS_FAILURE; + } + + len = os_strlen(ssid); + if (SSID_MAX_LEN < len) + { + LOG_E(DRV_EXT_TAG, "ssid name more than 32 Bytes\r\n"); + /* continue to use 32 bytes ssid, do not return err */ + len = SSID_MAX_LEN; + } + os_strncpy((char *)wNetConfig.wifi_ssid, ssid, sizeof(wNetConfig.wifi_ssid)); + + if (sizeof(wNetConfig.wifi_key) < os_strlen(wlan_dev->info.password)) + { + LOG_E(DRV_EXT_TAG, "wifi key is more than %d Bytes\r\n", sizeof(wNetConfig.wifi_key)); + return -OS_FAILURE; + } + os_strncpy((char *)wNetConfig.wifi_key,(char *)wlan_dev->info.password,sizeof(wNetConfig.wifi_key)); + + + wNetConfig.wifi_mode = BK_SOFT_AP; + wNetConfig.dhcp_mode = DHCP_SERVER; + wNetConfig.wifi_retry_interval = 100; + + os_strcpy((char *)wNetConfig.local_ip_addr, DHCPD_SERVER_IP); + os_strcpy((char *)wNetConfig.net_mask, "255.255.255.0"); + os_strcpy((char *)wNetConfig.gateway_ip_addr, DHCPD_SERVER_IP); + os_strcpy((char *)wNetConfig.dns_server_ip_addr, DHCPD_SERVER_IP); + + LOG_D(DRV_EXT_TAG, "_wifi_softap: ssid:%.*s key:%.*s\r\n", sizeof(wNetConfig.wifi_ssid), wNetConfig.wifi_ssid, sizeof(wNetConfig.wifi_key), wNetConfig.wifi_key); + + bk_wlan_ap_set_default_channel( (uint8_t)wlan_dev->info.channel); + + ret = bk_wlan_start(&wNetConfig); + + if(OS_SUCCESS == ret) + g_ap_status = 1; + else + return OS_FAILURE; + + + +#endif + return ret; +} + +/*=================================================================================*/ +const static struct os_wlan_device_ops wlan_ops = +{ + .start = beken_wlan_softap, + .stop = beken_wlan_disconnect, + .get_mac = beken_wlan_get_mac, + .join = beken_wlan_join, + .check_join_status = OS_NULL, + .leave = beken_wlan_disconnect, + .irq_handler = OS_NULL, + .send = beken_wlan_send, + .wlan_scan = beken_wlan_scan, + .wlan_scan_stop = beken_wlan_scan_stop, +}; + + +#include "icu.h" +#include "icu_pub.h" +#include "drv_model.h" +#include "arm_arch.h" + +/* register wlan device */ +static int beken_wlan_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + struct beken_wifi_info *wifi_info_tmp = OS_NULL; + wifi_info_tmp = (struct beken_wifi_info *)dev->info; + + beken_wlan_init(); + + char temp_mac[6]; + wifi_get_mac_address(temp_mac, CONFIG_ROLE_NULL); + + if (net_dev_mode_sta == wifi_info_tmp->work_mode) + { +#ifdef BSP_USING_BK_STA + wlan_sta_dev.ops = &wlan_ops; + wlan_sta_dev.flags = OS_WLAN_FLAG_STA_ONLY; + wlan_sta_dev.net_dev.info.mode = net_dev_mode_sta; + wlan_sta_dev.net_dev.info.intf_type = net_dev_intf_ether; + wlan_sta_dev.net_dev.info.xfer_flag = OS_NET_XFER_TX_TASK; + wlan_sta_dev.net_dev.info.MTU = 1500; + + if (os_wlan_net_register(&wlan_sta_dev, dev->name) != OS_SUCCESS) + { + return OS_FAILURE; + } +#endif + } + else + { +#ifdef BSP_USING_BK_AP + wlan_ap_dev.ops = &wlan_ops; + wlan_ap_dev.flags = OS_WLAN_FLAG_AP_ONLY; + wlan_ap_dev.net_dev.info.mode = net_dev_mode_ap; + wlan_ap_dev.net_dev.info.intf_type = net_dev_intf_ether; + wlan_ap_dev.net_dev.info.xfer_flag = OS_NET_XFER_TX_TASK; + wlan_ap_dev.net_dev.info.MTU = 1500; + + wlan_ap_dev.info.security = OS_WLAN_SECURITY_WPA2_AES_PSK; + wlan_ap_dev.info.country = OS_WLAN_COUNTRY_CHINA; + + if (os_wlan_net_register(&wlan_ap_dev, dev->name) != OS_SUCCESS) + { + return OS_FAILURE; + } + } +#endif + + bk_wlan_status_register_cb(wlan_event_handle); + + return OS_SUCCESS; +} + + +OS_DRIVER_INFO beken_wlan_driver = { + .name = "Wlan_Type", + .probe = beken_wlan_probe, +}; +OS_DRIVER_DEFINE(beken_wlan_driver, OS_INIT_LEVEL_PRE_DEVICE,OS_INIT_SUBLEVEL_LOW); + +static int bk7231n_init(void) +{ +#ifdef OS_USING_BK_AP + struct os_wlan_device *wlan_dev = OS_NULL; + + wlan_dev = (struct os_wlan_device *)os_device_find(OS_WLAN_DEVICE_AP_NAME); + if (wlan_dev == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "wifi_dev cannot find!"); + return OS_SUCCESS; + } + + wlan_dev->info.ssid = BSP_USING_BK_AP_SSID; + wlan_dev->info.password = BSP_USING_BK_AP_PASSWORD; + wlan_dev->info.security = BSP_USING_BK_AP_SECURITY; + wlan_dev->info.country = OS_WLAN_COUNTRY_CHINA; + wlan_dev->info.channel = BSP_USING_BK_AP_CHANNEL; + + os_wlan_start(wlan_dev); +#endif +} +OS_INIT_CALL(bk7231n_init, OS_INIT_LEVEL_APPLICATION, OS_INIT_SUBLEVEL_LOW); + + +/* init protocol and register to LWIP */ +static int beken_wlan_prot_init(void) +{ + struct os_wlan_device* wlan = OS_NULL; + struct netif* netif = OS_NULL; + + app_start(); + + os_base_t level = os_irq_lock(); + + /* set wifi work mode */ +#ifdef BSP_USING_BK_STA + /* beken LWIP special modifications */ + wlan = (struct os_wlan_device *)&wlan_sta_dev; + netif = os_wlan_get_netif(wlan); + netif->linkoutput =(netif_linkoutput_fn)low_level_output; +#endif + +#ifdef BSP_USING_BK_AP + /* beken LWIP special modifications */ + wlan = (struct os_wlan_device *)&wlan_ap_dev; + netif = os_wlan_get_netif(wlan); + netif->linkoutput =(netif_linkoutput_fn)low_level_output; +#endif + + os_irq_unlock(level); + + return OS_SUCCESS; +} +OS_INIT_CALL(beken_wlan_prot_init, OS_INIT_LEVEL_APPLICATION, OS_INIT_SUBLEVEL_LOW); + +// eof diff --git a/drivers/hal/beken/drivers/wlan/drv_wlan.h b/drivers/hal/beken/drivers/wlan/drv_wlan.h index 794f1e34a5ad1fde459af2800ee0de82ab2e7ced..dfe4f3902bac480529f6131f5dfece2a205e4ca1 100644 --- a/drivers/hal/beken/drivers/wlan/drv_wlan.h +++ b/drivers/hal/beken/drivers/wlan/drv_wlan.h @@ -2,6 +2,8 @@ #define __DRV_WLAN_H__ #include "wlan_dev.h" +#include "os_mutex.h" + #define MAX_ADDR_LEN 6 @@ -19,14 +21,25 @@ enum CONNECT_STATE }; struct beken_wifi_info +{ + uint32_t mac[MAX_ADDR_LEN]; + uint32_t state; /* 0:done 1:doding 2:failed */ + uint32_t mode; /* 0:normal 1:advanced */ + os_net_mode_t work_mode; /* work as a station or ap */ +}; + +struct os_bk_wlan_device { uint8_t mac[MAX_ADDR_LEN]; - uint8_t state; /* 0:done 1:doding 2:failed */ - uint8_t mode; /* 0:normal 1:advanced */ - os_wlan_mode_t work_mode; /* work as a station or ap */ + struct os_wlan_device wlan_sta_dev; + struct os_wlan_device wlan_ap_dev; }; struct netif *wlan_get_sta_netif(void); struct netif *wlan_get_uap_netif(void); +int beken_wlan_irq_lock(void); +void beken_wlan_irq_unlock(int int_flag); + + #endif diff --git a/drivers/hal/beken/drivers/wlan/drv_wlan_fast_connect.c b/drivers/hal/beken/drivers/wlan/drv_wlan_fast_connect.c index f564098a96e6dc589dc542a7fcd52b35431d4050..a93b9ffb3db8b65e3b2dfb82b8cad52f3dfe8108 100644 --- a/drivers/hal/beken/drivers/wlan/drv_wlan_fast_connect.c +++ b/drivers/hal/beken/drivers/wlan/drv_wlan_fast_connect.c @@ -2,11 +2,8 @@ #include #include -#include -#include #include #include -#include #include "drv_wlan.h" #include "drv_flash.h" #include "drv_wlan_fast_connect.h" diff --git a/drivers/hal/beken/drivers/wlan/net.c b/drivers/hal/beken/drivers/wlan/net.c index 7142d6f334503e4da12bdbb8475c006de1336bdb..1e30edcd8ad429bbcb3dd24bb271ea83ae16e2c0 100644 --- a/drivers/hal/beken/drivers/wlan/net.c +++ b/drivers/hal/beken/drivers/wlan/net.c @@ -12,7 +12,7 @@ #include #include "lwip/prot/dhcp.h" -#include "ethernetif.h" +//#include "ethernetif.h" #include "sa_station.h" @@ -28,13 +28,10 @@ #include "rtos_pub.h" #include -#include -#include #include #include -#include #include "drv_wlan.h" -#include "sys/socket.h" +#include "lwip/sockets.h" #if CFG_ROLE_LAUNCH #include "role_launch.h" @@ -158,6 +155,7 @@ void net_ipv6stack_init(struct netif *netif) uint8_t mac[6]; NET_DBG("L%d, %s \r\n", __LINE__, __FUNCTION__); + os_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); netif->flags |= NETIF_IPV6_FLAG_UP; /* Set Multicast filter for IPV6 link local address @@ -221,6 +219,7 @@ static void wm_netif_status_static_callback(struct netif *n) else { // static IP fail; + NET_DBG("L%d, %s \r\n", __LINE__, __FUNCTION__); } } @@ -246,9 +245,9 @@ static void wm_netif_status_callback(struct netif *n) char str[IP4ADDR_STRLEN_MAX]; memset(str, 0, IP4ADDR_STRLEN_MAX); - os_enter_critical(); + os_ubase_t level = os_irq_lock(); memcpy(str, ipaddr_ntoa(&n->ip_addr), IP4ADDR_STRLEN_MAX); - os_exit_critical(); + os_irq_unlock(level); os_printf("IP UP: %s \r\n", ipaddr_ntoa(&n->ip_addr)); @@ -264,7 +263,7 @@ static void wm_netif_status_callback(struct netif *n) (*fn)(&val); } mhdr_set_station_status(RW_EVT_STA_GOT_IP); - ip_up_tick = os_tick_get(); + ip_up_tick = os_tick_get_value(); os_kprintf("[ip_up]:start tick = %d, ip_up tick = %d, total = %d \n", start_connect_tick, ip_up_tick, ip_up_tick - start_connect_tick); _wifi_connect_done(NULL); if (sta_ipup_cb != NULL) @@ -508,11 +507,11 @@ void ip_address_set(int iface, int dhcp, char *ip, char *mask, char *gw, char *d memset(&addr, 0, sizeof(struct ipv4_config)); if (dhcp == 1) - { + { addr.addr_type = ADDR_TYPE_DHCP; } else - { + { addr.addr_type = ADDR_TYPE_STATIC; tmp = inet_addr((char *)ip); addr.address = (tmp); @@ -569,10 +568,12 @@ int net_configure_address(struct ipv4_config *addr, void *intrfc_handle) if_handle->ipaddr.addr = addr->address; if_handle->nmask.addr = addr->netmask; if_handle->gw.addr = addr->gw; + netifapi_netif_set_addr(if_handle->netif, &if_handle->ipaddr, &if_handle->nmask, &if_handle->gw); netif_set_status_callback(if_handle->netif, - wm_netif_status_static_callback); + wm_netif_status_static_callback); + netifapi_netif_set_up(if_handle->netif); if (!strncmp(if_handle->netif->name, OS_WLAN_DEVICE_STA_NAME, sizeof(if_handle->netif->name))) { @@ -591,7 +592,7 @@ int net_configure_address(struct ipv4_config *addr, void *intrfc_handle) netif_set_status_callback(if_handle->netif, wm_netif_status_callback); - + netifapi_netif_set_up(if_handle->netif); netifapi_dhcp_start(if_handle->netif); @@ -620,7 +621,7 @@ int net_configure_address(struct ipv4_config *addr, void *intrfc_handle) else { // softap IP up, start dhcp server; - os_kprintf("please use dhcp start server\n"); + //_kprintf("please use dhcp start server\n"); //dhcpd_start(OS_WLAN_DEVICE_AP_NAME); // dhcp_server_start(net_get_uap_handle()); dhcp_server_start(if_handle); @@ -770,11 +771,9 @@ void net_wlan_add_netif(void *mac) u8 vif_idx; u8 *b = (u8 *)mac; - NET_DBG("L%d, %s \r\n", __LINE__, __FUNCTION__); - if (!b || (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5]))) return; - + vif_idx = rwm_mgmt_vif_mac2idx(mac); if (vif_idx == 0xff) @@ -782,6 +781,8 @@ void net_wlan_add_netif(void *mac) os_printf("net_wlan_add_netif not vif idx found\r\n"); return ; } + + wlan_get_uap_netif(); vif_entry = rwm_mgmt_vif_idx2ptr(vif_idx); if (!vif_entry) @@ -791,12 +792,12 @@ void net_wlan_add_netif(void *mac) } if (vif_entry->type == VIF_AP) - { - g_uap.netif = wlan_get_uap_netif(); + { + g_uap.netif = wlan_get_uap_netif(); wlan_if = &g_uap; } else if (vif_entry->type == VIF_STA) - { + { g_mlan.netif = wlan_get_sta_netif(); wlan_if = &g_mlan; } @@ -810,8 +811,8 @@ void net_wlan_add_netif(void *mac) wlan_if->netif->state = (void *)vif_entry; vif_entry->priv = wlan_if->netif; - /* set link_up for this netif */ - netif_set_link_up(wlan_if->netif); + /* set link_up for this netif */ + netif_set_link_up(wlan_if->netif); } void net_wlan_remove_netif(void *mac) diff --git a/drivers/hal/beken/scripts/.gitignore b/drivers/hal/beken/scripts/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..8d35cb3277ff6eb0d637147c09e95934604a431c --- /dev/null +++ b/drivers/hal/beken/scripts/.gitignore @@ -0,0 +1,2 @@ +__pycache__ +*.pyc diff --git a/drivers/hal/beken/scripts/prebuild.py b/drivers/hal/beken/scripts/prebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..4c25359370dd1ccb363d29c46b9493581ba70cf7 --- /dev/null +++ b/drivers/hal/beken/scripts/prebuild.py @@ -0,0 +1,17 @@ +import sys +import glob +import os.path +import re +from oneoslib.build_tools import * + +import importlib +import importlib.util + +def prebuild(prj_path, bsp_path = '/board/CubeMX_Config/Src/'): + print("project " + prj_path) + + loader = importlib.machinery.SourceFileLoader('prebuild.py', Env['OS_ROOT'] + '/drivers/boot/cotex-m/prebuild.py') + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + mod.gen_cotex_m_link_file(prj_path) diff --git a/drivers/hal/beken/weave.yaml b/drivers/hal/beken/weave.yaml index baed7dd737b13b5e62fa6a36eefcc61c3e873c19..d65242e9e38052421177e413e762a453e673d199 100644 --- a/drivers/hal/beken/weave.yaml +++ b/drivers/hal/beken/weave.yaml @@ -1,3 +1,3 @@ # 子目录 add_subdirectory: - - ./* ? {is_define("SOC_FAMILY_BK72XX")} + - ./* diff --git a/drivers/hal/cmiot/drivers/m4xxr/drv_usart.c b/drivers/hal/cmiot/drivers/m4xxr/drv_usart.c index 3690c24fe863e7e3bc7f8b5adf163fd0c7e027b8..8759f31af47439a5e8e676c583731ead59d506ad 100644 --- a/drivers/hal/cmiot/drivers/m4xxr/drv_usart.c +++ b/drivers/hal/cmiot/drivers/m4xxr/drv_usart.c @@ -86,6 +86,13 @@ static void uart_isr(struct os_serial_device *serial) } } } + + if (USART_GetIntStatus(uart->info->idx, USART_INT_IDLEF) != RESET) + { + USART_ReceiveData(uart->info->idx); + + soft_dma_timeout_irq(&uart->sdma); + } } void uart_irq(int device_num) @@ -387,7 +394,7 @@ static void cm_uart_sdma_init(struct cm_uart *uart, dma_ring_t *ring) memset(&dma->hard_info, 0, sizeof(dma->hard_info)); dma->hard_info.max_size = 64 * 1024; - dma->hard_info.flag = HARD_DMA_FLAG_FULL_IRQ; + dma->hard_info.flag = HARD_DMA_FLAG_FULL_IRQ | HARD_DMA_FLAG_TIMEOUT_IRQ; dma->hard_info.data_timeout = uart_calc_byte_timeout_us(uart->serial_dev.config.baud_rate); if (uart->info->dma_support == 0) @@ -524,6 +531,8 @@ static os_err_t _cm_uart_init(const struct cm32_usart_info *uart_info, struct se USART_EnableDMA(uart_info->idx, USART_DMAREQ_RX, ENABLE); } + USART_ConfigInt(uart_info->idx, USART_INT_IDLEF, ENABLE); + ECLIC_Configuration_uart(uart_info); return OS_SUCCESS; @@ -563,6 +572,8 @@ static os_err_t cm_uart_deinit(struct os_serial_device *serial) DMA_EnableChannel(uart->info->dma_channel, DISABLE); } + USART_ConfigInt(uart->info->idx, USART_INT_IDLEF, DISABLE); + soft_dma_stop(&uart->sdma); soft_dma_deinit(&uart->sdma); diff --git a/drivers/hal/gd32v/drivers/drv_hwtimer.c b/drivers/hal/gd32v/drivers/drv_hwtimer.c index 48304a11280f78d5b50ea46f3ec5ebe3cc8c7a60..9c0c5d799e59758c7f0e0b5e5f32e47c34128150 100644 --- a/drivers/hal/gd32v/drivers/drv_hwtimer.c +++ b/drivers/hal/gd32v/drivers/drv_hwtimer.c @@ -45,7 +45,9 @@ static void timer_irq_callback(struct gd32_timer *timer) if (timer_interrupt_flag_get(timer_periph, TIMER_INT_FLAG_UP) == SET) { timer_interrupt_flag_clear(timer_periph, TIMER_INT_FLAG_UP); +#ifdef OS_USING_CLOCKEVENT os_clockevent_isr((os_clockevent_t *)timer); +#endif } } diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_common_tables.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfea7460e9a79e5b20670d947e6a52a894b29801 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_const_structs.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..80a3e8bbe72b8c54f34a0f40aa1e01f2bfb3308f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_math.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9dd26aa8110a0a90babc7b297c5bc6d5eb4216 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armcc.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..4d9d0645d3f747970c52d076595c6fcd9187e6e5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armclang.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..162a400ea1b01605d779037e697abb2b678fc802 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_compiler.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..adfd3c2504294bbc9f70a3b3db978b3095961d65 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_gcc.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..2d9db15a5def3461f91ec54855611284379cde32 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_iccarm.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..931db1d5141e0361e621bb5796f12804ffdfbc5f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_version.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/core_cm4.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..7d56873532c3144c832911d9aba3f1944d32d290 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/core/mpu_armv7.h b/drivers/hal/nationstech/N32G43x/CMSIS/core/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..01422033d087616db42542f90a0ce27e42fd0ad4 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/core/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/n32g43x.h b/drivers/hal/nationstech/N32G43x/CMSIS/device/n32g43x.h new file mode 100644 index 0000000000000000000000000000000000000000..5fadf2ff6e95f10061ca6420a1a1ebed9d6c77c5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/n32g43x.h @@ -0,0 +1,7744 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_H__ +#define __N32G43X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32G43x_Library_Basic + * @{ + */ + +#if !defined USE_STDPERIPH_DRIVER +/* + * Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_STDPERIPH_DRIVER +#endif + +/* + * In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE +#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/* + * In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */ + +#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/ + +#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/ + +#define __N32G43x_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ +#define __N32G43x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __N32G43x_STDPERIPH_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ +#define __N32G43x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ + +/** + * @brief N32G43x Standard Peripheral Library version number + */ +#define __N32G43x_STDPERIPH_VERSION \ + ((__N32G43x_STDPERIPH_VERSION_MAIN << 24) | (__N32G43x_STDPERIPH_VERSION_SUB1 << 16) \ + | (__N32G43x_STDPERIPH_VERSION_SUB2 << 8) | (__N32G43x_STDPERIPH_VERSION_RC)) + +/* + * Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#ifdef N32G43X +#define __MPU_PRESENT 1 /*!< N32G43x devices does not provide an MPU */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#endif /* N32G43x */ +#define __NVIC_PRIO_BITS 4 /*!< N32G43x uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief N32G43x Interrupt Number Definition + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** N32G43x specific Interrupt Numbers ********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */ + RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */ + DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */ + DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */ + DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */ + DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */ + DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */ + DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */ + DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */ + ADC_IRQn = 19, /*!< ADC global Interrupt */ + USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */ + USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */ + COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + UART4_IRQn = 47, /*!< UART4 global Interrupt */ + UART5_IRQn = 48, /*!< UART5 global Interrupt */ + LPUART_IRQn = 49, /*!< LPUART global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + TIM6_IRQn = 51, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 52, /*!< TIM7 global Interrupt */ + CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */ + CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */ + LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */ + LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */ + SAC_IRQn = 60, /*!< SAC global Interrupt */ + MMU_IRQn = 61, /*!< MMU global Interrupt */ + TSC_IRQn = 62, /*!< TSC global Interrupt */ + RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */ + TIM9_IRQn = 64, /*!< TIM9 global interrupt */ + UCDR_IRQn = 65, /*!< UCDR error interrupt */ +} IRQn_Type; + +#include "core_cm4.h" +#include "system_n32g43x.h" +#include +#include + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, + INTStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/* N32G43x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t SAMPT1; + __IO uint32_t SAMPT2; + __IO uint32_t JOFFSET1; + __IO uint32_t JOFFSET2; + __IO uint32_t JOFFSET3; + __IO uint32_t JOFFSET4; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t RSEQ1; + __IO uint32_t RSEQ2; + __IO uint32_t RSEQ3; + __IO uint32_t JSEQ; + __IO uint32_t JDAT1; + __IO uint32_t JDAT2; + __IO uint32_t JDAT3; + __IO uint32_t JDAT4; + __IO uint32_t DAT; + __IO uint32_t DIFSEL; + __IO uint32_t CALFACT; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT3; +} ADC_Module; + +/** + * @brief OPAMP + */ +typedef struct +{ + __IO uint32_t CS1; + __IO uint32_t RES1[3]; + __IO uint32_t CS2; + __IO uint32_t RES2[3]; + __IO uint32_t LOCK; +} OPAMP_Module; + +/** + * @brief COMP_Single + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; +} COMP_SingleType; + +/** + * @brief COMP + */ +typedef struct +{ + __IO uint32_t INTEN; + __IO uint32_t LPCKSEL; + __IO uint32_t WINMODE; + __IO uint32_t LOCK; + COMP_SingleType Cmp1; + __IO uint32_t RES; + COMP_SingleType Cmp2; + __IO uint32_t CMP2OSEL; + __IO uint32_t VREFSCL; + __IO uint32_t TEST; + __IO uint32_t INTSTS; +} COMP_Module; + +/** + * @brief AFEC + */ + +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + //uint32_t RESERVED0; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; +} AFEC_Module; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMDT; + __IO uint32_t TMDL; + __IO uint32_t TMDH; +} CAN_TxMailBox_Param; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RMI; + __IO uint32_t RMDT; + __IO uint32_t RMDL; + __IO uint32_t RMDH; +} CAN_FIFOMailBox_Param; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_Param; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; + __IO uint32_t MSTS; + __IO uint32_t TSTS; + __IO uint32_t RFF0; + __IO uint32_t RFF1; + __IO uint32_t INTE; + __IO uint32_t ESTS; + __IO uint32_t BTIM; + uint32_t RESERVED0[88]; + CAN_TxMailBox_Param sTxMailBox[3]; + CAN_FIFOMailBox_Param sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMC; + __IO uint32_t FM1; + uint32_t RESERVED2; + __IO uint32_t FS1; + uint32_t RESERVED3; + __IO uint32_t FFA1; + uint32_t RESERVED4; + __IO uint32_t FA1; + uint32_t RESERVED5[8]; + CAN_FilterRegister_Param sFilterRegister[14]; +} CAN_Module; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t CRC32DAT; /*!< CRC data register */ + __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/ + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CRC32CTRL; /*!< CRC control register */ + __IO uint32_t CRC16CTRL; + __IO uint8_t CRC16DAT; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint16_t CRC16D; + uint16_t RESERVED4; + __IO uint8_t LRC; + uint8_t RESERVED5; + uint16_t RESERVED6; +} CRC_Module; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SOTTR; + __IO uint32_t DR12CH; + __IO uint32_t DL12CH; + __IO uint32_t DR8CH; + __IO uint32_t DATO; + +} DAC_Module; +/** + * @brief USB + */ + +typedef struct +{ + __IO uint32_t EP0; + __IO uint32_t EP1; + __IO uint32_t EP2; + __IO uint32_t EP3; + __IO uint32_t EP4; + __IO uint32_t EP5; + __IO uint32_t EP6; + __IO uint32_t EP7; + __IO uint32_t Reserve20h; + __IO uint32_t Reserve24h; + __IO uint32_t Reserve28h; + __IO uint32_t Reserve2Ch; + __IO uint32_t Reserve30h; + __IO uint32_t Reserve34h; + __IO uint32_t Reserve38h; + __IO uint32_t Reserve3Ch; + __IO uint32_t CTRL; + __IO uint32_t STS; + __IO uint32_t FN; + __IO uint32_t ADDR; + __IO uint32_t BUFTAB; +} USB_Module; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t CTRL; +} DBG_Module; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CHCFG; + __IO uint32_t TXNUM; + __IO uint32_t PADDR; + __IO uint32_t MADDR; + __IO uint32_t CHSEL; + +} DMA_ChannelType; + +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO DMA_ChannelType DMA_Channel[8]; +} DMA_Module; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMASK; /*offset 0x00*/ + __IO uint32_t EMASK; /*offset 0x04*/ + __IO uint32_t RT_CFG; /*offset 0x08*/ + __IO uint32_t FT_CFG; /*offset 0x0C*/ + __IO uint32_t SWIE; /*offset 0x10*/ + __IO uint32_t PEND; /*offset 0x14*/ + __IO uint32_t TS_SEL; /*offset 0x18*/ +} EXTI_Module; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t AC; + __IO uint32_t KEYR; + __IO uint32_t OPTKEY; + __IO uint32_t STS; + __IO uint32_t CTRL; + __IO uint32_t ADD; + __IO uint32_t OB2; + __IO uint32_t OB; + __IO uint32_t WRP; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t RESERVED2; + __IO uint32_t CAHR; +} FLASH_Module; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t WRP1_WRP0; + __IO uint32_t WRP3_WRP2; + __IO uint32_t USER2_RDP2; +} OB_Module; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t PMODE; /*offset 0x00*/ + __IO uint32_t POTYPE; /*offset 0x04*/ + __IO uint32_t SR; /*offset 0x08*/ + __IO uint32_t PUPD; /*offset 0x0C*/ + __IO uint32_t PID; /*offset 0x10*/ + __IO uint32_t POD; /*offset 0x14*/ + __IO uint32_t PBSC; /*offset 0x18*/ + __IO uint32_t PLOCK; /*offset 0x1C*/ + __IO uint32_t AFL; /*offset 0x20*/ + __IO uint32_t AFH; /*offset 0x24*/ + __IO uint32_t PBC; /*offset 0x28*/ + __IO uint32_t DS; /*offset 0x2C*/ + +} GPIO_Module; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t RMP_CFG; + __IO uint32_t EXTI_CFG[4]; +} AFIO_Module; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DAT; + uint16_t RESERVED4; + __IO uint16_t STS1; + uint16_t RESERVED5; + __IO uint16_t STS2; + uint16_t RESERVED6; + __IO uint16_t CLKCTRL; + uint16_t RESERVED7; + __IO uint16_t TMRISE; + uint16_t RESERVED8; +} I2C_Module; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t PREDIV; /*!< IWDG PREDIV */ + __IO uint32_t RELV; + __IO uint32_t STS; +} IWDG_Module; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; + __IO uint32_t STS1; + __IO uint32_t STS2; + __IO uint32_t STSCLR; +} PWR_Module; + +/** + * @brief Low-Power Timer + */ +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO uint32_t INTEN; + __IO uint32_t CFG; + __IO uint32_t CTRL; + __IO uint32_t COMPx; + __IO uint32_t ARR; + __IO uint32_t CNT; + +} LPTIM_Module; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t CLKINT; + __IO uint32_t APB2PRST; + __IO uint32_t APB1PRST; + __IO uint32_t AHBPCLKEN; + __IO uint32_t APB2PCLKEN; + __IO uint32_t APB1PCLKEN; + __IO uint32_t LDCTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t AHBPRST; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t RDCTRL; + __IO uint32_t Reserve0; + __IO uint32_t Reserve1; + __IO uint32_t PLLHSIPRE; + __IO uint32_t SRAM_CTRLSTS; +} RCC_Module; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved0; /*!< Reserved */ + __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */ + __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */ +} RTC_Module; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t STS; + uint16_t RESERVED2; + __IO uint16_t DAT; + uint16_t RESERVED3; + __IO uint16_t CRCPOLY; + uint16_t RESERVED4; + __IO uint16_t CRCRDAT; + uint16_t RESERVED5; + __IO uint16_t CRCTDAT; + uint16_t RESERVED6; + __IO uint16_t I2SCFG; + uint16_t RESERVED7; + __IO uint16_t I2SPREDIV; + uint16_t RESERVED8; +} SPI_Module; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint16_t SMCTRL; + uint16_t RESERVED1; + __IO uint16_t DINTEN; + uint16_t RESERVED2; + __IO uint32_t STS; + __IO uint16_t EVTGEN; + uint16_t RESERVED3; + __IO uint16_t CCMOD1; + uint16_t RESERVED4; + __IO uint16_t CCMOD2; + uint16_t RESERVED5; + __IO uint32_t CCEN; + __IO uint16_t CNT; + uint16_t RESERVED6; + __IO uint16_t PSC; + uint16_t RESERVED7; + __IO uint16_t AR; + uint16_t RESERVED8; + __IO uint16_t REPCNT; + uint16_t RESERVED9; + __IO uint16_t CCDAT1; + uint16_t RESERVED10; + __IO uint16_t CCDAT2; + uint16_t RESERVED11; + __IO uint16_t CCDAT3; + uint16_t RESERVED12; + __IO uint16_t CCDAT4; + uint16_t RESERVED13; + __IO uint16_t BKDT; + uint16_t RESERVED14; + __IO uint16_t DCTRL; + uint16_t RESERVED15; + __IO uint16_t DADDR; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t CCMOD3; + uint16_t RESERVED18; + __IO uint16_t CCDAT5; + uint16_t RESERVED19; + __IO uint16_t CCDAT6; + uint16_t RESERVED20; +} TIM_Module; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint16_t DAT; + uint16_t RESERVED1; + __IO uint16_t BRCF; + uint16_t RESERVED2; + __IO uint16_t CTRL1; + uint16_t RESERVED3; + __IO uint16_t CTRL2; + uint16_t RESERVED4; + __IO uint16_t CTRL3; + uint16_t RESERVED5; + __IO uint16_t GTP; + uint16_t RESERVED6; +} USART_Module; + +/** + * @brief Low-power Universal Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint8_t INTEN; + uint8_t RESERVED1; + uint16_t RESERVED2; + __IO uint16_t CTRL; + uint16_t RESERVED3; + __IO uint16_t BRCFG1; + uint16_t RESERVED4; + __IO uint8_t DAT; + uint8_t RESERVED5; + uint16_t RESERVED6; + __IO uint8_t BRCFG2; + uint8_t RESERVED7; + uint16_t RESERVED8; + __IO uint32_t WUDAT; +} LPUART_Module; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t STS; +} WWDG_Module; + +/** + * @brief Touch Sensor Controller + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CHNEN; + __IO uint32_t STS; + __IO uint32_t RESERVED; + __IO uint32_t ANA_CTRL; + __IO uint32_t ANA_SEL; + __IO uint32_t RESR[3]; +// __IO uint32_t RESR0; +// __IO uint32_t RESR1; +// __IO uint32_t RESR2; + __IO uint32_t THRHD[24]; +// __IO uint32_t THRHD0; +// __IO uint32_t THRHD1; +// __IO uint32_t THRHD2; +// __IO uint32_t THRHD3; +// __IO uint32_t THRHD4; +// __IO uint32_t THRHD5; +// __IO uint32_t THRHD6; +// __IO uint32_t THRHD7; +// __IO uint32_t THRHD8; +// __IO uint32_t THRHD9; +// __IO uint32_t THRHD10; +// __IO uint32_t THRHD11; +// __IO uint32_t THRHD12; +// __IO uint32_t THRHD13; +// __IO uint32_t THRHD14; +// __IO uint32_t THRHD15; +// __IO uint32_t THRHD16; +// __IO uint32_t THRHD17; +// __IO uint32_t THRHD18; +// __IO uint32_t THRHD19; +// __IO uint32_t THRHD20; +// __IO uint32_t THRHD21; +// __IO uint32_t THRHD22; +// __IO uint32_t THRHD23; + +} TSC_Module; + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */ +#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */ +#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */ +#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */ +#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000) + +/* APB1 */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000) +#define COMP_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define TSC_BASE (APB1PERIPH_BASE + 0x3400) +#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00) +#define LPUART_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00) +#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/* APB2 */ +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00) +#define UART4_BASE (APB2PERIPH_BASE + 0x5000) +#define UART5_BASE (APB2PERIPH_BASE + 0x5400) + +/* AHB */ +#define DMA_BASE (AHBPERIPH_BASE + 0x8000) +#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008) +#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C) +#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030) +#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044) +#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058) +#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C) +#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080) +#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094) +#define ADC_BASE (AHBPERIPH_BASE + 0x8800) +#define RCC_BASE (AHBPERIPH_BASE + 0x9000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0xB000) +#define SAC_BASE (AHBPERIPH_BASE + 0xC000) +#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400) +#define MMU_BASE (AHBPERIPH_BASE + 0xCC00) + +#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +#define TIM2 ((TIM_Module*)TIM2_BASE) +#define TIM3 ((TIM_Module*)TIM3_BASE) +#define TIM4 ((TIM_Module*)TIM4_BASE) +#define TIM5 ((TIM_Module*)TIM5_BASE) +#define TIM6 ((TIM_Module*)TIM6_BASE) +#define TIM7 ((TIM_Module*)TIM7_BASE) +#define AFEC ((AFEC_Module*)AFEC_BASE) +#define OPAMP ((OPAMP_Module*)OPAMP_BASE) +#define COMP ((COMP_Module*)COMP_BASE) +#define RTC ((RTC_Module*)RTC_BASE) +#define WWDG ((WWDG_Module*)WWDG_BASE) +#define IWDG ((IWDG_Module*)IWDG_BASE) +#define TSC ((TSC_Module*)TSC_BASE) +#define TIM9 ((TIM_Module*)TIM9_BASE) +#define USART2 ((USART_Module*)USART2_BASE) +#define USART3 ((USART_Module*)USART3_BASE) +#define LPTIM ((LPTIM_Module*)LPTIM_BASE) +#define LPUART ((LPUART_Module*)LPUART_BASE) +#define I2C1 ((I2C_Module*)I2C1_BASE) +#define I2C2 ((I2C_Module*)I2C2_BASE) +#define USB ((USB_Module*)USB_BASE) +#define CAN ((CAN_Module*)CAN_BASE) +#define PWR ((PWR_Module*)PWR_BASE) +#define DAC ((DAC_Module*)DAC_BASE) +#define AFIO ((AFIO_Module*)AFIO_BASE) +#define EXTI ((EXTI_Module*)EXTI_BASE) +#define GPIOA ((GPIO_Module*)GPIOA_BASE) +#define GPIOB ((GPIO_Module*)GPIOB_BASE) +#define GPIOC ((GPIO_Module*)GPIOC_BASE) +#define GPIOD ((GPIO_Module*)GPIOD_BASE) +#define TIM1 ((TIM_Module*)TIM1_BASE) +#define SPI1 ((SPI_Module*)SPI1_BASE) +#define TIM8 ((TIM_Module*)TIM8_BASE) +#define USART1 ((USART_Module*)USART1_BASE) +#define SPI2 ((SPI_Module*)SPI2_BASE) +#define UART4 ((USART_Module*)UART4_BASE) +#define UART5 ((USART_Module*)UART5_BASE) +#define DMA ((DMA_Module*)DMA_BASE) +#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE) +#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE) +#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE) +#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE) +#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE) +#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE) +#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE) +#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE) +#define ADC ((ADC_Module*)ADC_BASE) +#define RCC ((RCC_Module*)RCC_BASE) +#define FLASH ((FLASH_Module*)FLASH_R_BASE) +#define OBT ((OB_Module*)OB_BASE) +#define CRC ((CRC_Module*)CRC_BASE) + +#define DBG ((DBG_Module*)DBG_BASE) + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_CRC32DAT register *********************/ +#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_CRC32IDAT register ********************/ +#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CRC32CTRL register ********************/ +#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************** Bit definition for CRC16_CR register ********************/ +#define CRC16_CTRL_LITTLE ((uint8_t)0x02) +#define CRC16_CTRL_BIG ((uint8_t)0xFD) + +#define CRC16_CTRL_RESET ((uint8_t)0x04) +#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CTRL1 register ********************/ +#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */ +#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */ +#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */ + + +#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */ + +#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */ +#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */ +#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */ +#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */ +#define PWR_CTRL1_MRSEL1 ((uint16_t)0x0600) /*!< vddd Range1=1.1 V */ +#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */ +#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */ +/******************** Bit definition for PWR_CTRL2 register ********************/ +#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */ +#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */ +#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */ +#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */ +#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */ +#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */ +#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */ +#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */ +#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */ + +#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */ + + +/******************** Bit definition for PWR_CTRL3 register ********************/ +#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */ +#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */ +#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */ +#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */ +#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */ +#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */ +#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */ + +#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */ +#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */ +#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */ +#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */ +#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */ + +#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */ +#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */ +#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */ +/******************** Bit definition for PWR_STS1 register ********************/ +#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */ +#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */ +#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP3. */ +#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */ +#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */ + +/******************** Bit definition for PWR_STS2 register ********************/ +#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */ +#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */ +#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */ + +/******************** Bit definition for PWR_STSCLR register ********************/ +#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF3 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */ + + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTRL register ********************/ +#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */ +#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */ +#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +/******************* Bit definition for RCC_CFG register *******************/ +/*!< SW configuration */ +#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */ +#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */ + +/*!< AHBPRES configuration */ +#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */ +#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< APB1PRES configuration */ +#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */ +#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< APB2PRES configuration */ +#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */ +#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< PLLSRC configuration */ +#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */ +#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + +/*!< PLLXTPRE configuration */ +#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ +#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */ +#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */ +#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */ + +#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ +#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ +#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ +#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ +#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ +#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ +#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ +#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */ +#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ +#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ +#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ +#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ +#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ +#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ +#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ +#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ +#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ +#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ +#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ +#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ +#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ +#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ +#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ +#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ +#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ +#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ +#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ +#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ +#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ + +/*!< USBPRES configuration */ +#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */ +#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ +#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */ +#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */ + +/*!< MCO configuration */ +#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */ +#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */ +#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */ +#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ +#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ +#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ +#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */ + +/*!< MCOPRE configuration */ +#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by + software to generate MCOPRE clock.) */ +#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */ +#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */ + +#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */ +#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */ +#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */ +#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */ +#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */ +#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */ +#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */ +#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */ +#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */ +#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */ +#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */ +#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */ +#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */ +#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */ +#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */ + +/*!<****************** Bit definition for RCC_CLKINT register ********************/ +#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */ +#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */ +#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */ +#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */ +#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */ +#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ +#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */ +#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */ +#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRST register *****************/ +#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ +#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ +#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */ +#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */ +#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */ + +/***************** Bit definition for RCC_APB1PRST register *****************/ +#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ +#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */ +#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */ +#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */ +#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */ +#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */ + +/****************** Bit definition for RCC_AHBPCLKEN register ******************/ +#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */ +#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ +#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */ +#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */ +#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */ + +/****************** Bit definition for RCC_APB2PCLKEN register *****************/ +#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ +#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ +#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ +#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */ +#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */ +#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */ + +/***************** Bit definition for RCC_APB1PCLKEN register ******************/ +#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ +#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */ +#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */ +#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */ +#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */ +#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */ +#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */ + +/******************* Bit definition for RCC_LDCTRL register *******************/ +#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */ +#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */ +#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC clock source selection) */ + +#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */ +#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */ +#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */ + +/******************* Bit definition for RCC_CTRLSTS register ********************/ +#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */ +#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */ + +#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */ +#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */ + +#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */ +#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */ +#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */ +#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */ +#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */ +#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */ +#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */ + +#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */ +#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */ +#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */ +#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBPRST register ****************/ +#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */ +#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */ +#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */ + +/******************* Bit definition for RCC_CFG2 register ******************/ +/*!< ADCHPRE configuration */ +#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */ +#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */ +#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */ +#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */ +#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */ +#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */ +#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */ +#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */ +#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */ +#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ +#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ + +/*!< ADCPLLPRES configuration */ +#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */ +#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ +#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */ + +#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */ +#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */ +#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */ +#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */ +#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */ +#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */ +#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */ +#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */ +#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */ +#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */ +#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */ +#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */ +#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */ +#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */ + +/*!< ADC1MPRE configuration */ +#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */ +#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */ +#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */ +#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */ + +#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */ +#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */ +#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */ +#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */ +#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */ +#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */ +#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */ +#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */ +#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */ +#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */ +#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */ +#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */ +#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */ +#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */ +#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */ +#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */ +#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */ +#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */ +#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */ +#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */ +#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */ +#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */ +#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */ +#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */ +#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */ +#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */ +#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */ +#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */ +#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */ +#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */ +#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */ +#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */ + +/*!< ADC1MSEL configuration */ +#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */ + +#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */ +#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */ + +/*!< RNGCPRE configuration */ +#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */ +#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */ + +#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */ +#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */ +#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */ +#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */ +#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */ +#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */ +#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */ +#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */ +#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */ +#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */ +#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */ +#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */ +#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */ +#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */ +#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */ +#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */ +#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */ +#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */ +#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */ +#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */ +#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */ +#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */ +#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */ +#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */ +#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */ +#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */ +#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */ +#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */ +#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */ +#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */ +#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */ +#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */ + +/*!< TIMCLK_SEL configuration */ +#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */ + +#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */ +#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */ + +/******************* Bit definition for RCC_CFG3 register ******************/ +/*!< UCDREN configuration */ +#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */ + +#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */ +#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */ + +/*!< USBXTALESS configuration */ +#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */ + +#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */ +#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */ + +/*!< UCDR300MSEL configuration */ +#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */ + +#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */ +#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */ + +/*!< TRNG1MPRE configuration */ +#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */ +#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ +#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ +#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ + +#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */ +#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */ +#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */ +#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */ +#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */ +#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */ +#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */ +#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */ +#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */ +#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */ +#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */ +#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */ +#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */ +#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */ +#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */ +#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */ +#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */ +#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */ +#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */ +#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */ +#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */ +#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */ +#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */ +#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */ +#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */ +#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */ +#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */ +#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */ +#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */ +#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */ +#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */ + +/*!< TRNG1MSEL configuration */ +#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */ + +#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */ +#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */ + +/*!< TRNG1MEN configuration */ +#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */ +#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +/******************* Bit definition for RCC_RDCTRL register ******************/ +/*!< LPTIMSEL congiguration */ +#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */ +#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */ + +/*!< LPUARTSEL congiguration */ +#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */ +#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */ + +#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */ +#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */ +#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */ +#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */ + +/******************* Bit definition for RCC_PLLHSIPRE register ******************/ +/*!< PLLHSIPRE configuration */ +#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */ + +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */ + +/*!< PLLSRCDIV configuration */ +#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */ + +#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */ + +/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/ +#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */ +#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */ + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD \ + ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */ +#define SCB_ICSR_RETTOBASE \ + ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT \ + ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 \ + ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 \ + ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 \ + ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 \ + ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 \ + ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 \ + ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 \ + ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 \ + ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA \ + ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND \ + ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \ + Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN \ + ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N \ + ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 \ + ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 \ + ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 \ + ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED \ + ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO \ + ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL \ + ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED \ + ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTSTS register ********************/ +#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ +#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTCLR register *******************/ +#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ +#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CHCFG1 register *******************/ +#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG2 register *******************/ +#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG3 register *******************/ +#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CHCFG4 register *******************/ +#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CHCFG5 register *******************/ +#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG6 register *******************/ +#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG7 register *******************/ +#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG8 register *******************/ +#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_TXNUM1 register ******************/ +#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM2 register ******************/ +#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM3 register ******************/ +#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM4 register ******************/ +#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM5 register ******************/ +#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM6 register ******************/ +#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM7 register ******************/ +#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM8 register ******************/ +#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STS register ********************/ +#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */ +#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */ +#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */ + + +/******************* Bit definition for ADC_CTRL1 register ********************/ +#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTRL2 register ********************/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CTRL2_EXTJSEL \ + ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */ +#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPT1 register *******************/ +#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SAMPT2 register *******************/ +#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFFSET1 register *******************/ +#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFFSET2 register *******************/ +#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFFSET3 register *******************/ +#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFFSET4 register *******************/ +#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDGHIGH register ********************/ +#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDGLOW register ********************/ +#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSEQ1 register *******************/ +#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_RSEQ2 register *******************/ +#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_RSEQ3 register *******************/ +#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSEQ register *******************/ +#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */ +#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDAT1 register *******************/ +#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT2 register *******************/ +#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT3 register *******************/ +#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT4 register *******************/ +#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DAT register ********************/ +#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */ + +///******************** Bit definition for ADC_DIFSEL register ********************/ +//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */ +//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */ +//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */ +//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */ +//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */ +//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */ +//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */ +//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */ +//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */ +//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */ +//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */ +//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */ +//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */ +//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */ +//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */ +//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */ +//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */ +//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */ +//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */ +//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */ + +///******************** Bit definition for ADC_CALFACT register ********************/ +//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */ +//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */ +//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */ +//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */ +//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */ +//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */ +//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */ +//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */ + +//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */ +//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */ +//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */ +//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */ +//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */ +//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */ +//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */ +//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */ + +///******************** Bit definition for ADC_CTRL3 register ********************/ +//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */ +//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */ +//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */ + +//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */ +//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */ +//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */ +//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */ +//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */ +//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */ +//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */ +//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */ +//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */ +//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */ + +///******************** Bit definition for ADC_SAMPT3 register ********************/ +//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTRL register ********************/ +#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */ +#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */ +#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */ + +#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */ +#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */ +#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */ +#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */ + + + +/***************** Bit definition for DAC_SOTTR register ******************/ +#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */ + + +/***************** Bit definition for DAC_DR12CH register ******************/ +#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DL12CH register ******************/ +#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DR8CH register ******************/ +#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */ + + + + +/******************* Bit definition for DAC_DATO register *******************/ +#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */ + + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTRL1 register ********************/ +#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */ +#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */ +#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */ +#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */ +#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */ + +#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */ + +#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */ +#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */ +#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */ +#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */ +#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */ +#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */ + +#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/ +#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */ + +/******************* Bit definition for TIM_CTRL2 register ********************/ +#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */ +#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */ + +#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */ +#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */ + +/******************* Bit definition for TIM_SMCTRL register *******************/ +#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DINTEN register *******************/ +#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_STS register ********************/ +#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */ +#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */ +#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */ +#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */ +#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */ + +#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */ +#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */ + +/******************* Bit definition for TIM_EVTGEN register ********************/ +#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMOD1 register *******************/ +#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD2 register *******************/ +#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD3 register *******************/ +#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */ +#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */ + +#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */ + +#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */ +#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */ + +#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */ +#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +/******************* Bit definition for TIM_CCEN register *******************/ +#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */ + +#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */ +#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */ +#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */ +#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_AR register ********************/ +#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_REPCNT register ********************/ +#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCDAT1 register *******************/ +#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCDAT2 register *******************/ +#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCDAT3 register *******************/ +#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCDAT4 register *******************/ +#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_CCDAT5 register *******************/ +#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */ + +/******************* Bit definition for TIM_CCDAT6 register *******************/ +#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */ + +/******************* Bit definition for TIM_BKDT register *******************/ +#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCTRL register ********************/ +#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DADDR register *******************/ +#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ +/******************************************************************************/ +/* */ +/* Low Power Timer (LPTTIM) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for LPTIM_INTSTS register *******************/ +#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */ +#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */ + +/****************** Bit definition for LPTIM_INTCLR register *******************/ +#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */ +#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */ +#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */ +#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */ +#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */ + +/****************** Bit definition for LPTIM_INTEN register ********************/ +#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */ + +/****************** Bit definition for LPTIM_CFG register *******************/ +#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */ + +#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */ +#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */ +#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */ + +#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */ +#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */ + +#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */ +#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */ + +#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */ +#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */ +#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */ +#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */ + +#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */ +#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */ +#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */ +#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */ + +#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */ +#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */ + +#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */ +#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */ +#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */ +#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */ +#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */ +#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ +#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */ +/****************** Bit definition for LPTIM_CTRL register ********************/ +#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */ +#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */ +#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */ + +/****************** Bit definition for LPTIM_CMPT register *******************/ +#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */ + +/****************** Bit definition for LPTIM_AUTRLD register *******************/ +#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */ + +/****************** Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */ +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TSH register *******************/ +#define RTC_TSH_APM ((uint32_t)0x00400000) +#define RTC_TSH_HOT ((uint32_t)0x00300000) +#define RTC_TSH_HOT_0 ((uint32_t)0x00100000) +#define RTC_TSH_HOT_1 ((uint32_t)0x00200000) +#define RTC_TSH_HOU ((uint32_t)0x000F0000) +#define RTC_TSH_HOU_0 ((uint32_t)0x00010000) +#define RTC_TSH_HOU_1 ((uint32_t)0x00020000) +#define RTC_TSH_HOU_2 ((uint32_t)0x00040000) +#define RTC_TSH_HOU_3 ((uint32_t)0x00080000) +#define RTC_TSH_MIT ((uint32_t)0x00007000) +#define RTC_TSH_MIT_0 ((uint32_t)0x00001000) +#define RTC_TSH_MIT_1 ((uint32_t)0x00002000) +#define RTC_TSH_MIT_2 ((uint32_t)0x00004000) +#define RTC_TSH_MIU ((uint32_t)0x00000F00) +#define RTC_TSH_MIU_0 ((uint32_t)0x00000100) +#define RTC_TSH_MIU_1 ((uint32_t)0x00000200) +#define RTC_TSH_MIU_2 ((uint32_t)0x00000400) +#define RTC_TSH_MIU_3 ((uint32_t)0x00000800) +#define RTC_TSH_SCT ((uint32_t)0x00000070) +#define RTC_TSH_SCT_0 ((uint32_t)0x00000010) +#define RTC_TSH_SCT_1 ((uint32_t)0x00000020) +#define RTC_TSH_SCT_2 ((uint32_t)0x00000040) +#define RTC_TSH_SCU ((uint32_t)0x0000000F) +#define RTC_TSH_SCU_0 ((uint32_t)0x00000001) +#define RTC_TSH_SCU_1 ((uint32_t)0x00000002) +#define RTC_TSH_SCU_2 ((uint32_t)0x00000004) +#define RTC_TSH_SCU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_DATE register *******************/ +#define RTC_DATE_YRT ((uint32_t)0x00F00000) +#define RTC_DATE_YRT_0 ((uint32_t)0x00100000) +#define RTC_DATE_YRT_1 ((uint32_t)0x00200000) +#define RTC_DATE_YRT_2 ((uint32_t)0x00400000) +#define RTC_DATE_YRT_3 ((uint32_t)0x00800000) +#define RTC_DATE_YRU ((uint32_t)0x000F0000) +#define RTC_DATE_YRU_0 ((uint32_t)0x00010000) +#define RTC_DATE_YRU_1 ((uint32_t)0x00020000) +#define RTC_DATE_YRU_2 ((uint32_t)0x00040000) +#define RTC_DATE_YRU_3 ((uint32_t)0x00080000) +#define RTC_DATE_WDU ((uint32_t)0x0000E000) +#define RTC_DATE_WDU_0 ((uint32_t)0x00002000) +#define RTC_DATE_WDU_1 ((uint32_t)0x00004000) +#define RTC_DATE_WDU_2 ((uint32_t)0x00008000) +#define RTC_DATE_MOT ((uint32_t)0x00001000) +#define RTC_DATE_MOU ((uint32_t)0x00000F00) +#define RTC_DATE_MOU_0 ((uint32_t)0x00000100) +#define RTC_DATE_MOU_1 ((uint32_t)0x00000200) +#define RTC_DATE_MOU_2 ((uint32_t)0x00000400) +#define RTC_DATE_MOU_3 ((uint32_t)0x00000800) +#define RTC_DATE_DAT ((uint32_t)0x00000030) +#define RTC_DATE_DAT_0 ((uint32_t)0x00000010) +#define RTC_DATE_DAT_1 ((uint32_t)0x00000020) +#define RTC_DATE_DAU ((uint32_t)0x0000000F) +#define RTC_DATE_DAU_0 ((uint32_t)0x00000001) +#define RTC_DATE_DAU_1 ((uint32_t)0x00000002) +#define RTC_DATE_DAU_2 ((uint32_t)0x00000004) +#define RTC_DATE_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_CTRL register *******************/ +#define RTC_CTRL_COEN ((uint32_t)0x00800000) +#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000) +#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000) +#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000) +#define RTC_CTRL_OPOL ((uint32_t)0x00100000) +#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000) +#define RTC_CTRL_BAKP ((uint32_t)0x00040000) +#define RTC_CTRL_SU1H ((uint32_t)0x00020000) +#define RTC_CTRL_AD1H ((uint32_t)0x00010000) +#define RTC_CTRL_TSIEN ((uint32_t)0x00008000) +#define RTC_CTRL_WTIEN ((uint32_t)0x00004000) +#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000) +#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000) +#define RTC_CTRL_TSEN ((uint32_t)0x00000800) +#define RTC_CTRL_WTEN ((uint32_t)0x00000400) +#define RTC_CTRL_ALBEN ((uint32_t)0x00000200) +#define RTC_CTRL_ALAEN ((uint32_t)0x00000100) + +#define RTC_CTRL_HFMT ((uint32_t)0x00000040) +#define RTC_CTRL_BYPS ((uint32_t)0x00000020) +#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010) +#define RTC_CTRL_TEDGE ((uint32_t)0x00000008) +#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007) +#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001) +#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002) +#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004) + +/******************** Bits definition for RTC_INITSTS register ******************/ +#define RTC_INITSTS_RECPF ((uint32_t)0x00010000) +#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000) +#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000) +#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000) +#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000) +#define RTC_INITSTS_TISF ((uint32_t)0x00000800) +#define RTC_INITSTS_WTF ((uint32_t)0x00000400) +#define RTC_INITSTS_ALBF ((uint32_t)0x00000200) +#define RTC_INITSTS_ALAF ((uint32_t)0x00000100) +#define RTC_INITSTS_INITM ((uint32_t)0x00000080) +#define RTC_INITSTS_INITF ((uint32_t)0x00000040) +#define RTC_INITSTS_RSYF ((uint32_t)0x00000020) +#define RTC_INITSTS_INITSF ((uint32_t)0x00000010) +#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008) +#define RTC_INITSTS_WTWF ((uint32_t)0x00000004) +#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002) +#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_PRE register *****************/ +#define RTC_PRE_DIVA ((uint32_t)0x007F0000) +#define RTC_PRE_DIVS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_WKUPT register *****************/ +#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF) + + +/******************** Bits definition for RTC_ALARMA register ***************/ +#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMA_DTT ((uint32_t)0x30000000) +#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMA_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMA_APM ((uint32_t)0x00400000) +#define RTC_ALARMA_HOT ((uint32_t)0x00300000) +#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMA_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMA_MIT ((uint32_t)0x00007000) +#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMA_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMA_SET ((uint32_t)0x00000070) +#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMA_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_ALARMB register ***************/ +#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMB_DTT ((uint32_t)0x30000000) +#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMB_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMB_APM ((uint32_t)0x00400000) +#define RTC_ALARMB_HOT ((uint32_t)0x00300000) +#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMB_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMB_MIT ((uint32_t)0x00007000) +#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMB_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMB_SET ((uint32_t)0x00000070) +#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMB_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_WRP register ******************/ +#define RTC_WRP_PKEY ((uint32_t)0x000000FF) + +/******************** Bits definition for RTC_SUBS register ******************/ +#define RTC_SUBS_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_SCTRL register ***************/ +#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF) +#define RTC_SCTRL_AD1S ((uint32_t)0x80000000) + +/******************** Bits definition for RTC_TST register *****************/ +#define RTC_TST_APM ((uint32_t)0x00400000) +#define RTC_TST_HOT ((uint32_t)0x00300000) +#define RTC_TST_HOT_0 ((uint32_t)0x00100000) +#define RTC_TST_HOT_1 ((uint32_t)0x00200000) +#define RTC_TST_HOU ((uint32_t)0x000F0000) +#define RTC_TST_HOU_0 ((uint32_t)0x00010000) +#define RTC_TST_HOU_1 ((uint32_t)0x00020000) +#define RTC_TST_HOU_2 ((uint32_t)0x00040000) +#define RTC_TST_HOU_3 ((uint32_t)0x00080000) +#define RTC_TST_MIT ((uint32_t)0x00007000) +#define RTC_TST_MIT_0 ((uint32_t)0x00001000) +#define RTC_TST_MIT_1 ((uint32_t)0x00002000) +#define RTC_TST_MIT_2 ((uint32_t)0x00004000) +#define RTC_TST_MIU ((uint32_t)0x00000F00) +#define RTC_TST_MIU_0 ((uint32_t)0x00000100) +#define RTC_TST_MIU_1 ((uint32_t)0x00000200) +#define RTC_TST_MIU_2 ((uint32_t)0x00000400) +#define RTC_TST_MIU_3 ((uint32_t)0x00000800) +#define RTC_TST_SET ((uint32_t)0x00000070) +#define RTC_TST_SET_0 ((uint32_t)0x00000010) +#define RTC_TST_SET_1 ((uint32_t)0x00000020) +#define RTC_TST_SET_2 ((uint32_t)0x00000040) +#define RTC_TST_SEU ((uint32_t)0x0000000F) +#define RTC_TST_SEU_0 ((uint32_t)0x00000001) +#define RTC_TST_SEU_1 ((uint32_t)0x00000002) +#define RTC_TST_SEU_2 ((uint32_t)0x00000004) +#define RTC_TST_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSD register *****************/ +#define RTC_TSD_YRT ((uint32_t)0x00F00000) +#define RTC_TSD_YRT_0 ((uint32_t)0x00100000) +#define RTC_TSD_YRT_1 ((uint32_t)0x00200000) +#define RTC_TSD_YRT_2 ((uint32_t)0x00400000) +#define RTC_TSD_YRT_3 ((uint32_t)0x00800000) +#define RTC_TSD_YRU ((uint32_t)0x000F0000) +#define RTC_TSD_YRU_0 ((uint32_t)0x00010000) +#define RTC_TSD_YRU_1 ((uint32_t)0x00020000) +#define RTC_TSD_YRU_2 ((uint32_t)0x00040000) +#define RTC_TSD_YRU_3 ((uint32_t)0x00080000) + +#define RTC_TSD_WDU ((uint32_t)0x0000E000) +#define RTC_TSD_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSD_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSD_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSD_MOT ((uint32_t)0x00001000) +#define RTC_TSD_MOU ((uint32_t)0x00000F00) +#define RTC_TSD_MOU_0 ((uint32_t)0x00000100) +#define RTC_TSD_MOU_1 ((uint32_t)0x00000200) +#define RTC_TSD_MOU_2 ((uint32_t)0x00000400) +#define RTC_TSD_MOU_3 ((uint32_t)0x00000800) +#define RTC_TSD_DAT ((uint32_t)0x00000030) +#define RTC_TSD_DAT_0 ((uint32_t)0x00000010) +#define RTC_TSD_DAT_1 ((uint32_t)0x00000020) +#define RTC_TSD_DAU ((uint32_t)0x0000000F) +#define RTC_TSD_DAU_0 ((uint32_t)0x00000001) +#define RTC_TSD_DAU_1 ((uint32_t)0x00000002) +#define RTC_TSD_DAU_2 ((uint32_t)0x00000004) +#define RTC_TSD_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSSS register ****************/ +#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CALIB register *****************/ +#define RTC_CALIB_CP ((uint32_t)0x00008000) +#define RTC_CALIB_CW8 ((uint32_t)0x00004000) +#define RTC_CALIB_CW16 ((uint32_t)0x00002000) +#define RTC_CALIB_CM ((uint32_t)0x000001FF) +#define RTC_CALIB_CM_0 ((uint32_t)0x00000001) +#define RTC_CALIB_CM_1 ((uint32_t)0x00000002) +#define RTC_CALIB_CM_2 ((uint32_t)0x00000004) +#define RTC_CALIB_CM_3 ((uint32_t)0x00000008) +#define RTC_CALIB_CM_4 ((uint32_t)0x00000010) +#define RTC_CALIB_CM_5 ((uint32_t)0x00000020) +#define RTC_CALIB_CM_6 ((uint32_t)0x00000040) +#define RTC_CALIB_CM_7 ((uint32_t)0x00000080) +#define RTC_CALIB_CM_8 ((uint32_t)0x00000100) + +/******************** Bits definition for RTC_TMPCFG register ****************/ + +#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000) +#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000) +#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000) +#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000) +#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000) +#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000) +#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000) +#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000) +#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000) +#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000) +#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000) +#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800) +#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800) +#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000) +#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700) +#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080) +#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040) +#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020) +#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010) +#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008) +#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004) +#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002) +#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_ALRMASS register *************/ +#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_ALRMBSS register *************/ +#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_OPT register *******************/ +#define RTC_OPT_TYPE ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/ +#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008) +#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004) +#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCNT register *******************/ +#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF) +/******************** Bits definition for RTC_BKP1 register ****************/ +#define RTC_BKP1 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP2 register ****************/ +#define RTC_BKP2 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP3 register ****************/ +#define RTC_BKP3 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP4 register ****************/ +#define RTC_BKP4 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP5 register ****************/ +#define RTC_BKP5 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP6 register ****************/ +#define RTC_BKP6 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP7 register ****************/ +#define RTC_BKP7 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP8 register ****************/ +#define RTC_BKP8 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP9 register ****************/ +#define RTC_BKP9 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP10 register ****************/ +#define RTC_BKP10 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP11 register ***************/ +#define RTC_BKP11 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP12register ***************/ +#define RTC_BKP12 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP13 register ***************/ +#define RTC_BKP13 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP14 register ***************/ +#define RTC_BKP14 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP15 register ***************/ +#define RTC_BKP15 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP16 register ***************/ +#define RTC_BKP16 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP17register ***************/ +#define RTC_BKP17 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP18 register ***************/ +#define RTC_BKP18 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP19 register ***************/ +#define RTC_BKP19 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP20 register ***************/ +#define RTC_BKP20 ((uint32_t)0xFFFFFFFF) + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KEY register ********************/ +#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PREDIV register ********************/ +#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RELV register *******************/ +#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STS register ********************/ +#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTRL register ********************/ +#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFG register *******************/ +#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */ +#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STS register ********************/ +#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for XFMC_BCR1 register *******************/ +#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BCR2 register *******************/ +#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BTR1 register ******************/ +#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BTR2 register *******************/ +#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR1 register ******************/ +#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR2 register ******************/ +#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_PCR2 register *******************/ +#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for XFMC_PCR3 register *******************/ +#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for XFMC_SR2 register *******************/ +//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/******************* Bit definition for XFMC_SR3 register *******************/ +//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/****************** Bit definition for XFMC_PMEM2 register ******************/ +#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PMEM3 register ******************/ +#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT2 register ******************/ +#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT3 register ******************/ +#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_ECCR2 register ******************/ +#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for XFMC_ECCR3 register ******************/ +#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */ +#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCTRL register ********************/ +#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */ +#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */ +#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */ +#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */ + +/******************* Bit definition for CAN_MSTS register ********************/ +#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTS register ********************/ +#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFF0 register *******************/ +#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */ +#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */ +#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */ +#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFF1 register *******************/ +#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */ +#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */ +#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */ +#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTE register *******************/ +#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTIM register ********************/ +#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMC register ********************/ +#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1 register *******************/ +#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1 register *******************/ +#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1 register *******************/ +#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */ +#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */ +#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */ +#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */ +#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */ +#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */ +#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */ +#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */ +#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */ +#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */ +#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */ +#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */ +#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */ +#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */ +#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1 register *******************/ +#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTRL1 register ********************/ +#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTRL2 register ********************/ +#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STS register ********************/ +#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DAT register ********************/ +#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPOLY register ******************/ +#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_CRCRDAT register ******************/ +#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_CRCTDAT register ******************/ +#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFG register *****************/ +#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPREDIV register *******************/ +#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTRL1 register ********************/ +#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CTRL2 register ********************/ +#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DAT register ********************/ +#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_STS1 register ********************/ +#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_STS2 register ********************/ +#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CLKCTRL register ********************/ +#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_STS register *******************/ +#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DAT register *******************/ +#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRCF register *******************/ +#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTRL1 register *******************/ +#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */ +#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */ + +/****************** Bit definition for USART_CTRL2 register *******************/ +#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CTRL3 register *******************/ +#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ + +/****************** Bit definition for USART_GTP register ******************/ +#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Low-power Universal Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for LPUART_STS register ******************/ +#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */ +#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */ +#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */ +#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */ +#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */ +#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */ +#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */ +#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */ +#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */ + +/****************** Bit definition for LPUART_INTEN register ******************/ +#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */ +#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */ +#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */ +#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/ +#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */ +#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */ +#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */ + +/****************** Bit definition for LPUART_CTRL register ******************/ +#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */ +#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */ +#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */ +#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */ +#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */ +#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */ +#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */ +#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */ +#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */ +#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */ +#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */ +#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */ +#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */ + +/****************** Bit definition for LPUART_BRCFG1 register ******************/ +#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */ + +/****************** Bit definition for LPUART_DAT register ******************/ +#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */ + +/****************** Bit definition for LPUART_BRCFG2 register ******************/ +#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */ + +/****************** Bit definition for LPUART_WUDAT register ******************/ +#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBG_ID register *****************/ +#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBG_CTRL register *******************/ +#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ + +#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */ +#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */ +#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */ +#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/ +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_AC register ******************/ +#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */ +#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */ +#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */ +#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */ + +#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ +#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ +#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */ +#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */ +#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */ +#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */ +#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */ +#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */ + +/****************** Bit definition for FLASH_KEY register ******************/ +#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */ + +/***************** Bit definition for FLASH_OPTKEY register ****************/ +#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */ +#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */ +#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */ + +/******************* Bit definition for FLASH_CTRL register *******************/ +#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */ +#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */ +#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */ + +/******************* Bit definition for FLASH_ADD register *******************/ +#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OB2 register *******************/ +#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */ +#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */ +#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */ +#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */ + +/****************** Bit definition for FLASH_OB register *******************/ +#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */ + +#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */ +#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */ + +#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */ +#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */ +#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */ + +/****************** Bit definition for FLASH_WRP register ******************/ +#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/****************** Bit definition for FLASH_CAHR register ******************/ +#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */ +#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */ +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for OptionByte Data0 *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte Data1 *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte WRP0 ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP1 ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP2 ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP3 ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte RDP2 *******************/ +#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */ +#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */ + +/****************** Bit definition for OptionByte USER2 ******************/ +#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_PMODE register *******************/ + + +#define GPIO_PMODE0_Pos (0) +#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE0 GPIO_PMODE0_Msk +#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE1_Pos (2) +#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE1 GPIO_PMODE1_Msk +#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE2_Pos (4) +#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE2 GPIO_PMODE2_Msk +#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE3_Pos (6) +#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE3 GPIO_PMODE3_Msk +#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE4_Pos (8) +#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE4 GPIO_PMODE4_Msk +#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE5_Pos (10) +#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE5 GPIO_PMODE5_Msk +#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE6_Pos (12) +#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE6 GPIO_PMODE6_Msk +#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE7_Pos (14) +#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE7 GPIO_PMODE7_Msk +#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE8_Pos (16) +#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE8 GPIO_PMODE8_Msk +#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE9_Pos (18) +#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE9 GPIO_PMODE9_Msk +#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE10_Pos (20) +#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE10 GPIO_PMODE10_Msk +#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE11_Pos (22) +#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE11 GPIO_PMODE11_Msk +#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE12_Pos (24) +#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE12 GPIO_PMODE12_Msk +#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE13_Pos (26) +#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE13 GPIO_PMODE13_Msk +#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE14_Pos (28) +#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE14 GPIO_PMODE14_Msk +#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE15_Pos (30) +#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE15 GPIO_PMODE15_Msk +#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ + + + + +/****************** Bit definition for GPIO_POTYPER register *****************/ +#define GPIO_POTYPE_POT_0 (0x00000001) +#define GPIO_POTYPE_POT_1 (0x00000002) +#define GPIO_POTYPE_POT_2 (0x00000004) +#define GPIO_POTYPE_POT_3 (0x00000008) +#define GPIO_POTYPE_POT_4 (0x00000010) +#define GPIO_POTYPE_POT_5 (0x00000020) +#define GPIO_POTYPE_POT_6 (0x00000040) +#define GPIO_POTYPE_POT_7 (0x00000080) +#define GPIO_POTYPE_POT_8 (0x00000100) +#define GPIO_POTYPE_POT_9 (0x00000200) +#define GPIO_POTYPE_POT_10 (0x00000400) +#define GPIO_POTYPE_POT_11 (0x00000800) +#define GPIO_POTYPE_POT_12 (0x00001000) +#define GPIO_POTYPE_POT_13 (0x00002000) +#define GPIO_POTYPE_POT_14 (0x00004000) +#define GPIO_POTYPE_POT_15 (0x00008000) + + +/******************* Bit definition for GPIO_PUPDR register ******************/ +#define GPIO_PUPD0_Pos (0) +#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD0 GPIO_PUPD0_Msk +#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD1_Pos (2) +#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD1 GPIO_PUPD1_Msk +#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD2_Pos (4) +#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD2 GPIO_PUPD2_Msk +#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD3_Pos (6) +#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD3 GPIO_PUPD3_Msk +#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD4_Pos (8) +#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD4 GPIO_PUPD4_Msk +#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD5_Pos (10) +#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD5 GPIO_PUPD5_Msk +#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD6_Pos (12) +#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD6 GPIO_PUPD6_Msk +#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD7_Pos (14) +#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD7 GPIO_PUPD7_Msk +#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD8_Pos (16) +#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD8 GPIO_PUPD8_Msk +#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD9_Pos (18) +#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD9 GPIO_PUPD9_Msk +#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD10_Pos (20) +#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD10 GPIO_PUPD10_Msk +#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD11_Pos (22) +#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD11 GPIO_PUPD11_Msk +#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD12_Pos (24) +#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD12 GPIO_PUPD12_Msk +#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD13_Pos (26) +#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD13 GPIO_PUPD13_Msk +#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD14_Pos (28) +#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD14 GPIO_PUPD14_Msk +#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD15_Pos (30) +#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD15 GPIO_PUPD15_Msk +#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */ + + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_POD register *******************/ +#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/****************** Bit definition for GPIO_AFL register *******************/ +#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */ +#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */ +#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */ +#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */ +#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */ +#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */ +#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */ +#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */ + +/****************** Bit definition for GPIO_AFH register *******************/ +#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */ +#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */ +#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */ +#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */ +#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */ +#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */ +#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */ +#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */ + + +/******************* Bit definition for GPIO_DS register ******************/ +#define GPIO_DS0_Pos (0) +#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ +#define GPIO_DS0 GPIO_DS0_Msk +#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */ +#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */ +#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */ +#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ + +#define GPIO_DS1_Pos (2) +#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ +#define GPIO_DS1 GPIO_DS1_Msk +#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */ +#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */ +#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */ +#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ + +#define GPIO_DS2_Pos (4) +#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ +#define GPIO_DS2 GPIO_DS2_Msk +#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */ +#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */ +#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */ +#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ + +#define GPIO_DS3_Pos (6) +#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ +#define GPIO_DS3 GPIO_DS3_Msk +#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */ +#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */ +#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */ +#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ + +#define GPIO_DS4_Pos (8) +#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ +#define GPIO_DS4 GPIO_DS4_Msk +#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */ +#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */ +#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */ +#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ + +#define GPIO_DS5_Pos (10) +#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ +#define GPIO_DS5 GPIO_DS5_Msk +#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */ +#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */ +#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */ +#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ + +#define GPIO_DS6_Pos (12) +#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ +#define GPIO_DS6 GPIO_DS6_Msk +#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */ +#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */ +#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */ +#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ + +#define GPIO_DS7_Pos (14) +#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ +#define GPIO_DS7 GPIO_DS7_Msk +#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */ +#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */ +#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */ +#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ + + +#define GPIO_DS8_Pos (16) +#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ +#define GPIO_DS8 GPIO_DS8_Msk +#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */ +#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */ +#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */ +#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ + +#define GPIO_DS9_Pos (18) +#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ +#define GPIO_DS9 GPIO_DS9_Msk +#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */ +#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */ +#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */ +#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ + +#define GPIO_DS10_Pos (20) +#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ +#define GPIO_DS10 GPIO_DS10_Msk +#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */ +#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */ +#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */ +#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ + +#define GPIO_DS11_Pos (22) +#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ +#define GPIO_DS11 GPIO_DS11_Msk +#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */ +#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */ +#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */ +#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ + +#define GPIO_DS12_Pos (24) +#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ +#define GPIO_DS12 GPIO_DS12_Msk +#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */ +#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */ +#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */ +#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ + +#define GPIO_DS13_Pos (26) +#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ +#define GPIO_DS13 GPIO_DS13_Msk +#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */ +#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */ +#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */ +#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ + +#define GPIO_DS14_Pos (28) +#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ +#define GPIO_DS14 GPIO_DS14_Msk +#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */ +#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */ +#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */ +#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ + +#define GPIO_DS15_Pos (30) +#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ +#define GPIO_DS15 GPIO_DS15_Msk +#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */ +#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */ +#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */ +#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ + +/******************* Bit definition for GPIO_SR register *******************/ +#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */ +#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */ +#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */ +#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */ +#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */ +#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */ +#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */ +#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */ +#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */ +#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */ +#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */ +#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */ +#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */ +#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */ +#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */ +#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for AFIO_RMP_CFG register *****************/ +#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */ +#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */ +#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */ +#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */ +#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */ +#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */ +#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */ +#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */ +#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */ +#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */ +#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */ +#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ + +/*!< EXTI5 configuration */ +#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */ +#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */ +#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */ +#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */ +#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */ +#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */ +#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */ + +/*!< EXTI12 configuration */ +#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ + +/*!< EXTI13 configuration */ +#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ +#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ +#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ +#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ +#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ +#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ +#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ +#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ +#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ +#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ +#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ +#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ +#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ +#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ +#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ + + +/****************** Bit definition for EXTI_RT_CFG register *******************/ +#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ +#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ +#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ +#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ +#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ + + + +/****************** Bit definition for EXTI_FT_CFG register *******************/ +#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ +#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ +#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ +#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ +#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ + +/****************** Bit definition for EXTI_SWIE register ******************/ +#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ +#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ +#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ +#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ +#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ +#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ + +/******************* Bit definition for EXTI_PEND register ********************/ +#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ +#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ +#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ +#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ +#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ +#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ +#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ +#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ +#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ + +/******************************************************************************/ +/* */ +/* TSC Registers */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for TSC_CTRL register ****************/ +#define TSC_CTRL_TM2_ETR_CH1_Msk ((uint32_t)0x2000) +#define TSC_CTRL_TM2_ETR_CH1_Pos (13U) +#define TSC_CTRL_TM2_ETR_CH1 (TSC_CTRL_TM2_ETR_CH1_Msk) /*!FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x.s b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x.s new file mode 100644 index 0000000000000000000000000000000000000000..ac31cd6e13e86fdbed4131b4cf4cf496c00e521b --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x.s @@ -0,0 +1,371 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD 0 ; Reserved + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_EWARM.s b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_EWARM.s new file mode 100644 index 0000000000000000000000000000000000000000..e9a39bed20bf9ade38a8f772a03554f78f8b5ea8 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_EWARM.s @@ -0,0 +1,523 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel1_IRQHandler + B DMA_Channel1_IRQHandler + + PUBWEAK DMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel2_IRQHandler + B DMA_Channel2_IRQHandler + + PUBWEAK DMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel3_IRQHandler + B DMA_Channel3_IRQHandler + + PUBWEAK DMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel4_IRQHandler + B DMA_Channel4_IRQHandler + + PUBWEAK DMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel5_IRQHandler + B DMA_Channel5_IRQHandler + + PUBWEAK DMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel6_IRQHandler + B DMA_Channel6_IRQHandler + + PUBWEAK DMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel7_IRQHandler + B DMA_Channel7_IRQHandler + + PUBWEAK DMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel8_IRQHandler + B DMA_Channel8_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK COMP_1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_1_2_IRQHandler + B COMP_1_2_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK LPUART_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_IRQHandler + B LPUART_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK CAN_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_TX_IRQHandler + B CAN_TX_IRQHandler + + PUBWEAK CAN_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX0_IRQHandler + B CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK LPUART_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_WKUP_IRQHandler + B LPUART_WKUP_IRQHandler + + PUBWEAK LPTIM_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM_WKUP_IRQHandler + B LPTIM_WKUP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK SAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAC_IRQHandler + B SAC_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RAMC_PERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAMC_PERR_IRQHandler + B RAMC_PERR_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK UCDR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UCDR_IRQHandler + B UCDR_IRQHandler + + + END + diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_gcc.s b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..c7cf4ff1518a0e3a5ea911c167ce3814d3e64af7 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/startup/startup_n32g43x_gcc.s @@ -0,0 +1,457 @@ +/** + **************************************************************************** + Copyright (c) 2019, Nations Technologies Inc. + + All rights reserved. + **************************************************************************** + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the disclaimer below. + + Nations' name may not be used to endorse or promote products derived from + this software without specific prior written permission. + + DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + **/ + +* Amount of memory (in bytes) allocated for Stack +* Tailor this value to your application needs +* Stack Configuration +* Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +* +*/ + +/** +****************************************************************************** +* @file startup_n32g43x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT Nations Technologies Inc *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.c b/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.c new file mode 100644 index 0000000000000000000000000000000000000000..acc03fd190487b40372a3c9b94c5add017b8d1c6 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.c @@ -0,0 +1,615 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32g43x.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x.h" + +/* Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your + device's maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume + that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to + drive the System clock. If you are using different crystal you have to adapt + those functions accordingly. + */ + +#define SYSCLK_USE_MSI 0 +#define SYSCLK_USE_HSI 1 +#define SYSCLK_USE_HSE 2 +#define SYSCLK_USE_HSI_PLL 3 +#define SYSCLK_USE_HSE_PLL 4 + +#ifndef SYSCLK_FREQ +#define SYSCLK_FREQ 108000000 +#endif + +/* +* SYSCLK_SRC * +** SYSCLK_USE_MSI ** +** SYSCLK_USE_HSI ** +** SYSCLK_USE_HSE ** +** SYSCLK_USE_HSI_PLL ** +** SYSCLK_USE_HSE_PLL ** +*/ +#ifndef SYSCLK_SRC +#define SYSCLK_SRC SYSCLK_USE_HSE_PLL +#endif + +#define PLL_DIV2_DISABLE 0x00000000 +#define PLL_DIV2_ENABLE 0x00000002 + +#if SYSCLK_SRC == SYSCLK_USE_MSI + + #if (SYSCLK_FREQ == MSI_VALUE_L0) + #define MSI_CLK 0 + #elif (SYSCLK_FREQ == MSI_VALUE_L1) + #define MSI_CLK 1 + #elif (SYSCLK_FREQ == MSI_VALUE_L2) + #define MSI_CLK 2 + #elif (SYSCLK_FREQ == MSI_VALUE_L3) + #define MSI_CLK 3 + #elif (SYSCLK_FREQ == MSI_VALUE_L4) + #define MSI_CLK 4 + #elif (SYSCLK_FREQ == MSI_VALUE_L5) + #define MSI_CLK 5 + #elif (SYSCLK_FREQ == MSI_VALUE_L6) + #define MSI_CLK 6 + #else + #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6) + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI + + #if SYSCLK_FREQ != HSI_VALUE + #error SYSCL_FREQ must be set to HSI_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if SYSCLK_FREQ != HSE_VALUE + #error SYSCL_FREQ must be set to HSE_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL + + #ifndef HSI_VALUE + #error HSI_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE) + + #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE) + + #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#else +#error wrong value for SYSCLK_SRC +#endif + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ + +/******************************************************************************* + * Clock Definitions + *******************************************************************************/ +uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +static void SetSysClock(void); + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + */ +void SystemInit(void) +{ + /* FPU settings + * ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSEON, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */ + RCC->CFG &= (uint32_t)0x0700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; + + /* Enable ex mode */ + RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN; + RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN); + + /* Enable ICACHE and Prefetch Buffer */ + FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN); + + /* Checks whether the Low Voltage Mode status is SET or RESET */ + if((FLASH->AC & FLASH_AC_LVMF) != RESET) + { + /* FLASH Low Voltage Mode Disable */ + FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN); + } + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or + * configure other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any + * configuration based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the + * MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the + * HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the + * HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the + * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in n32g43x.h file (default value + * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real + * value may vary depending on the variations in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in n32g43x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in n32g43x.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to + * ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0; + uint8_t msi_clk = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + tmp = RCC->CFG & RCC_CFG_SCLKSTS; + + /* Get MSI clock + * -------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + SystemCoreClock = MSIClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor + * ----------------------*/ + pllmull = RCC->CFG & RCC_CFG_PLLMULFCT; + pllsource = RCC->CFG & RCC_CFG_PLLSRC; + plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV; + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSI_VALUE * pllmull; + } + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + if (plldiv2 == 0x02) + { + /* PLL source clock divided by 2 selected as PLL clock entry */ + SystemCoreClock >>= 1; + } + + break; + + default: + SystemCoreClock = MSIClockTable[msi_clk]; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 + * prescalers. + */ +static void SetSysClock(void) +{ + uint32_t rcc_cfg = 0; + uint32_t rcc_pllhsipre = 0; + uint32_t StartUpCounter = 0; + +#if (SYSCLK_SRC == SYSCLK_USE_MSI) + uint8_t i=0; + bool MSIStatus = 0; + /* Config MSI */ + RCC->CTRLSTS &= 0xFFFFFF8F; + /*Delay for while*/ + for(i=0;i<0x30;i++); + RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4); + /*Delay for while*/ + for(i=0;i<0x30;i++); + /* Enable MSI */ + RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN); + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD; + StartUpCounter++; + } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT)); + + MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET); + if (!MSIStatus) + { + /* If MSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL)) + + bool HSIStatus = 0; + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + /* If HSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL)) + + bool HSEStatus = 0; + /* Enable HSE */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET); + if (!HSEStatus) + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } +#endif + + /* If the system clock is greater than 64MHz, the voltage range of the main voltage regulator + must be configured as 1.1V */ + if(SYSCLK_FREQ >= 64000000) + { + /* Enables PWR peripheral clock */ + RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR; + /* Check PWR->CTRL1.MRSEL configuration */ + if((PWR->CTRL1 & ((uint32_t)PWR_CTRL1_MRSEL)) == ((uint32_t)PWR_CTRL1_MRSEL2)) + { + /* Config 1.1V */ + PWR->CTRL1 |= PWR_CTRL1_MRSEL1; + } + } + + /* Flash wait state + 0: HCLK <= 32M + 1: HCLK <= 64M + 2: HCLK <= 96M + 3: HCLK <= 128M + */ + FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY); + FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000); + + /* HCLK = SYSCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1; + + /* PCLK2 max 54M */ + if (SYSCLK_FREQ > 54000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1; + } + + /* PCLK1 max 27M */ + if (SYSCLK_FREQ > 54000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4; + } + else if (SYSCLK_FREQ > 27000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1; + } + +#if SYSCLK_SRC == SYSCLK_USE_MSI + /* Select MSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI; + + /* Wait till MSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI + /* Select HSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSE + /* Select HSE as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + /* clear bits */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT)); + RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV)); + + /* set PLL source */ + rcc_cfg = RCC->CFG; + rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE); + /* PLL DIV */ + rcc_pllhsipre = RCC->PLLHSIPRE; + + #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL + rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2); + #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); + #endif + + /* set PLL DIV */ + rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE); + + /* set PLL multiply factor */ + #if PLL_MUL <= 16 + rcc_cfg |= (PLL_MUL - 2) << 18; + #else + rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27); + #endif + + RCC->CFG = rcc_cfg; + RCC->PLLHSIPRE = rcc_pllhsipre; + + /* Enable PLL */ + RCC->CTRL |= RCC_CTRL_PLLEN; + + /* Wait till PLL is ready */ + while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C) + { + } +#endif +} diff --git a/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.h b/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.h new file mode 100644 index 0000000000000000000000000000000000000000..6f59b6429f2f4d8a31258707e30160812cd5016a --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/CMSIS/device/system_n32g43x.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32g43x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SYSTEM_N32G43X_H__ +#define __SYSTEM_N32G43X_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32G43X_System + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_N32G43X_H__ */ diff --git a/drivers/hal/nationstech/N32G43x/Kconfig b/drivers/hal/nationstech/N32G43x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..8ea16f2639198e68dbd406c52921e3cba3cf08af --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/Kconfig @@ -0,0 +1,16 @@ +config SERIES_N32G43X + bool + select ARCH_ARM_CORTEX_M4 + default n + +config SOC_N32G435RBL7 + bool + select MANUFACTOR_NATIONSTECH + select SERIES_N32G43X + default n + +config SOC_N32G436RBL7 + bool + select MANUFACTOR_NATIONSTECH + select SERIES_N32G43X + default n diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/misc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/misc.h new file mode 100644 index 0000000000000000000000000000000000000000..9123c57bcebfdbe80a29173b3f1e07dd8a61f536 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/misc.h @@ -0,0 +1,228 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @addtogroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete N32G43x Devices IRQ Channels list, please + refer to n32g43x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + +/** + * @} + */ + +/** @addtogroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption +priority | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption +priority | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption +priority | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption +priority | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption +priority | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Constants + * @{ + */ + +/** @addtogroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @addtogroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @addtogroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 \ + ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \ + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 \ + ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \ + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 \ + ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \ + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 \ + ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \ + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 \ + ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \ + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) \ + (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \ + || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @addtogroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) \ + (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_adc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..83cc7e98d3693e99fb937af161d79fe4a8119d0c --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_adc.h @@ -0,0 +1,545 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_adc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_ADC_H__ +#define __N32G43x_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" +#include + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ +#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while(0); +#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while(0); + +#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while(0); +#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while(0); + +/** @addtogroup ADC + * @{ + */ + +/** @addtogroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + + FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref + ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitType; +/** + * @} + */ + +/** @addtogroup ADC_Exported_Constants + * @{ + */ + +#define IsAdcModule(PERIPH) (((PERIPH) == ADC)) + +#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC)) + + + +/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) +#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) +#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) +#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) +#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) +#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) +#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) + + +#define IsAdcExtTrig(REGTRIG) \ + (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_data_align + * @{ + */ + +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) +#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) +/** + * @} + */ + +/** @addtogroup ADC_channels + * @{ + */ + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) + +#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0) +#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17) +#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18) + +#define IsAdcChannel(CHANNEL) \ + (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ + || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ + || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ + || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ + || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) +/** + * @} + */ + +/** @addtogroup ADC_sampling_time + * @{ + */ + +#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) +#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) +#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) +#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) +#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) +#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) +#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) +#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) +#define IsAdcSampleTime(TIME) \ + (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_239CYCLES5)) +/** + * @} + */ + +/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) +#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) +#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) +#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) +#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) +#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) +#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) + + +#define IsAdcExtInjTrig(INJTRIG) \ + (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_INJ_CH_1 ((uint8_t)0x14) +#define ADC_INJ_CH_2 ((uint8_t)0x18) +#define ADC_INJ_CH_3 ((uint8_t)0x1C) +#define ADC_INJ_CH_4 ((uint8_t)0x20) +#define IsAdcInjCh(CHANNEL) \ + (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ + || ((CHANNEL) == ADC_INJ_CH_4)) +/** + * @} + */ + +/** @addtogroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) +#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) +#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) +#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) +#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) +#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) +#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) + +#define IsAdcAnalogWatchdog(WATCHDOG) \ + (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_interrupts_definition + * @{ + */ + +#define ADC_INT_ENDC ((uint16_t)0x0220) +#define ADC_INT_AWD ((uint16_t)0x0140) +#define ADC_INT_JENDC ((uint16_t)0x0480) + +#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) +/** + * @} + */ + +/** @addtogroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_JENDC ((uint8_t)0x04) +#define ADC_FLAG_JSTR ((uint8_t)0x08) +#define ADC_FLAG_STR ((uint8_t)0x10) +#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) +#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) +#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) +#define IsAdcGetFlag(FLAG) \ + (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ + || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) +/** + * @} + */ + +/** @addtogroup ADC_thresholds + * @{ + */ +#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @addtogroup ADC_injected_offset + * @{ + */ + +#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @addtogroup ADC_injected_length + * @{ + */ + +#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_injected_rank + * @{ + */ + +#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_length + * @{ + */ + +#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @addtogroup ADC_regular_rank + * @{ + */ + +#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/************************** fllowing bit seg in ex register **********************/ +/**@addtogroup ADC_channels_ex_style + * @{ + */ + + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1_PA0 ((uint8_t)0x01) +#define ADC_CH_2_PA1 ((uint8_t)0x02) +#define ADC_CH_3_PA2 ((uint8_t)0x03) +#define ADC_CH_4_PA3 ((uint8_t)0x04) +#define ADC_CH_5_PA4 ((uint8_t)0x05) +#define ADC_CH_6_PA5 ((uint8_t)0x06) +#define ADC_CH_7_PA6 ((uint8_t)0x07) +#define ADC_CH_8_PA7 ((uint8_t)0x08) +#define ADC_CH_9_PB0 ((uint8_t)0x09) +#define ADC_CH_10_PB1 ((uint8_t)0x0A) +#define ADC_CH_11_PC0 ((uint8_t)0x0B) +#define ADC_CH_12_PC1 ((uint8_t)0x0C) +#define ADC_CH_13_PC2 ((uint8_t)0x0D) +#define ADC_CH_14_PC3 ((uint8_t)0x0E) +#define ADC_CH_15_PC4 ((uint8_t)0x0F) +#define ADC_CH_16_PC5 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) +/** + * @} + */ + +/**@addtogroup ADC_dif_sel_ch_definition + * @{ + */ +#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF) +#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001) +#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) +#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) +#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) +#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) +#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) +#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) +#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) +#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) +#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) +#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) +#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) +#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) +#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) +#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) +#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) +#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) +#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) +#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) +/** + * @} + */ + +/**@addtogroup ADC_calfact_definition + * @{ + */ +#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) +#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) +/** + * @} + */ + +/**@addtogroup ADC_ctrl3_definition + * @{ + */ +#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) +#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) +#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) +#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) +#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) +#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) +#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) +#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) +#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) +typedef enum +{ + ADC_CTRL3_CKMOD_AHB = 0, + ADC_CTRL3_CKMOD_PLL = 1, +} ADC_CTRL3_CKMOD; +typedef enum +{ + ADC_CTRL3_RES_12BIT = 3, + ADC_CTRL3_RES_10BIT = 2, + ADC_CTRL3_RES_8BIT = 1, + ADC_CTRL3_RES_6BIT = 0, +} ADC_CTRL3_RES; +typedef struct +{ + FunctionalState DeepPowerModEn; + FunctionalState JendcIntEn; + FunctionalState EndcIntEn; + ADC_CTRL3_CKMOD ClkMode; + FunctionalState CalAtuoLoadEn; + bool DifModCal; + ADC_CTRL3_RES ResBit; + bool Samp303Style; +} ADC_InitTypeEx; +/** + * @} + */ + +/**@addtogroup ADC_bit_num_definition + * @{ + */ +#define ADC_RST_BIT_12 ((uint32_t)0x03) +#define ADC_RST_BIT_10 ((uint32_t)0x02) +#define ADC_RST_BIT_8 ((uint32_t)0x01) +#define ADC_RESULT_BIT_6 ((uint32_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC_flags_ex_definition + * @{ + */ +#define ADC_FLAG_RDY ((uint8_t)0x20) +#define ADC_FLAG_PD_RDY ((uint8_t)0x40) +#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_Module* ADCx); +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_InitStruct(ADC_InitType* ADC_InitStruct); +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); +void ADC_StartCalibration(ADC_Module* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); +uint16_t ADC_GetDat(ADC_Module* ADCx); +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); +void ADC_EnableTempSensorVrefint(FunctionalState Cmd); +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); + +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); + +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_ADC_H__ */ + +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_can.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_can.h new file mode 100644 index 0000000000000000000000000000000000000000..2e1e39e1594308544d11c031d47f2c3eb87f9ea5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_can.h @@ -0,0 +1,670 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_can.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_CAN_H__ +#define __N32G43X_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @addtogroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t OperatingMode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t RSJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t TBS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t TBS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitType; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t Filter_Scale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState Filter_Act; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitType; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMessage; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMessage; + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Constants + * @{ + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @addtogroup OperatingMode + * @{ + */ + +#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */ +#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) \ + (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \ + || ((MODE) == CAN_Silent_LoopBack_Mode)) +/** + * @} + */ + +/** + * @addtogroup CAN_operating_mode + * @{ + */ +#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */ + +#define IS_CAN_OPERATING_MODE(MODE) \ + (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode)) +/** + * @} + */ + +/** + * @addtogroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */ + +/** + * @} + */ + +/** @addtogroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_RSJW(SJW) \ + (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq)) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq) + +/** + * @} + */ + +/** @addtogroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13) +/** + * @} + */ + +/** @addtogroup CAN_filter_mode + * @{ + */ + +#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode)) +/** + * @} + */ + +/** @addtogroup CAN_filter_scale + * @{ + */ + +#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @addtogroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @addtogroup CAN_identifier_type + * @{ + */ + +#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id)) +/** + * @} + */ + +/** @addtogroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote)) + +/** + * @} + */ + +/** @addtogroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @addtogroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */ + +#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @addtogroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @addtogroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */ + +/** + * @} + */ + +/** @addtogroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */ +#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */ +#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */ +#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */ +#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */ +#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \ + || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \ + || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK)) + +#define IS_CAN_CLEAR_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \ + || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \ + || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + +/** @addtogroup CAN_interrupts + * @{ + */ + +#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/ +#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/ +#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/ +#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/ +#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/ +#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_INT_RQCPM0 CAN_INT_TME +#define CAN_INT_RQCPM1 CAN_INT_TME +#define CAN_INT_RQCPM2 CAN_INT_TME + +#define IS_CAN_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \ + || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \ + || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \ + || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +#define IS_CAN_CLEAR_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \ + || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \ + || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +/** + * @} + */ + +/** @addtogroup CAN_Legacy + * @{ + */ +#define CANINITSTSFAILED CAN_InitSTS_Failed +#define CANINITSTSOK CAN_InitSTS_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Standard_Id +#define CAN_ID_EXT CAN_Extended_Id +#define CAN_RTRQ_DATA CAN_RTRQ_Data +#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote +#define CANTXSTSFAILE CAN_TxSTS_Failed +#define CANTXSTSOK CAN_TxSTS_Ok +#define CANTXSTSPENDING CAN_TxSTS_Pending +#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox +#define CANSLEEPFAILED CAN_SLEEP_Failed +#define CANSLEEPOK CAN_SLEEP_Ok +#define CANWKUFAILED CAN_WKU_Failed +#define CANWKUOK CAN_WKU_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_Module* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam); +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct); +void CAN_InitStruct(CAN_InitType* CAN_InitParam); +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd); +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd); + +/* Transmit functions *********************************************************/ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage); +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage); +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum); +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_EnterSleep(CAN_Module* CANx); +uint8_t CAN_WakeUp(CAN_Module* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrCode(CAN_Module* CANx); +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx); +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd); +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG); +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT); +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_CAN_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_comp.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_comp.h new file mode 100644 index 0000000000000000000000000000000000000000..b8c89fe6327a29cff655b5434f3f7977d690d95c --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_comp.h @@ -0,0 +1,282 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_comp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_COMP_H__ +#define __N32G43X_COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" +#include + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/** @addtogroup COMP_Exported_Constants + * @{ + */ +typedef enum +{ + COMP1 = 0, + COMP2 = 1, +} COMPX; + +// COMPx_CTRL +#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21) +#define COMP1_CTRL_INPDAC_MASK (0x01L << 20) +#define COMP_CTRL_OUT_MASK (0x01L << 19) +#define COMP_CTRL_BLKING_MASK (0x03L << 16) +typedef enum +{ + COMP_CTRL_BLKING_NO = (0x0L << 16), + COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16), + COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16), +} COMP_CTRL_BLKING; +#define COMPx_CTRL_HYST_MASK (0x03L << 14) +typedef enum +{ + COMP_CTRL_HYST_NO = (0x0L << 14), + COMP_CTRL_HYST_LOW = (0x1L << 14), + COMP_CTRL_HYST_MID = (0x2L << 14), + COMP_CTRL_HYST_HIGH = (0x3L << 14), +} COMP_CTRL_HYST; + +#define COMP_POL_MASK (0x01L << 13) +#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9) +typedef enum +{ + // comp1 out trig + COMP1_CTRL_OUTSEL_NC = (0x0L << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9), + COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9), + COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9), + COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9), + COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9), + COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9), + COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9), + COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9), + COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), + // comp2 out trig + COMP2_CTRL_OUTSEL_NC = (0x0L << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9), + COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9), + COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9), + COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9), + COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9), + COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9), + COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9), + COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9), + COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), +} COMP_CTRL_OUTTRIG; + +#define COMP_CTRL_INPSEL_MASK (0x0FL<<5) +typedef enum { + //comp1 inp sel + COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100), + COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140), + COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160), + COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180), + COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0), + COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0), + COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0), + COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120), + //comp2 inp sel + COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100), + COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120), + COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140), + COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160), + COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180), + COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0), + COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0), + COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0), +}COMP_CTRL_INPSEL; + + +#define COMP_CTRL_INMSEL_MASK (0x07L<<1) +typedef enum { + //comp1 inm sel + COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002), + COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004), + COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006), + COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008), + COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A), + COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C), + COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000), + //comp2 inm sel + COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002), + COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004), + COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006), + COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008), + COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A), + COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C), + COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000), +}COMP_CTRL_INMSEL; + +#define COMP_CTRL_EN_MASK (0x01L << 0) + +//COMPx_FILC +#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1. +#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2. +#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable. + +//COMPx_FILP +#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number . + +//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD +#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode. + +//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN +#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTEN_CMP2IEN (0x01L << 1) +#define COMP_INTEN_CMP1IEN (0x01L << 0) + +//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS +#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTSTS_CMP2IS (0x01L << 1) +#define COMP_INTSTS_CMP1IS (0x01L << 0) + +//COMP_VREFSCL @addtogroup COMP_VREFSCL +#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value. +#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7) +#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value. +#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0) + +//COMP_LOCK @addtogroup COMP_LOCK +#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value. +#define COMP_LOCK_CMP1LK (0x1L << 0) + +//COMP_LPCKSEL @addtogroup COMP_LPCKSEL +#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0) + +//COMP_OSEL @addtogroup COMP_OSEL +#define COMP_OSEL_CMP2XO (0x1L << 0) + +/** + * @} + */ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + // ctrl + bool LowPoweMode; // only COMP1 have this bit + bool InpDacConnect; // only COMP1 have this bit + + COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */ + + COMP_CTRL_HYST Hyst; + + bool PolRev; // out polarity reverse + + COMP_CTRL_OUTTRIG OutTrig; + COMP_CTRL_INPSEL InpSel; + COMP_CTRL_INMSEL InmSel; + + bool En; + + // filter + uint8_t SampWindow; // 5bit + uint8_t Thresh; // 5bit ,need > SampWindow/2 + bool FilterEn; + + // filter psc + uint16_t ClkPsc; +} COMP_InitType; + +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +void COMP_DeInit(void); +void COMP_StructInit(COMP_InitType* COMP_InitStruct); +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct); +void COMP_Enable(COMPX COMPx, FunctionalState en); +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel); +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel); +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig); +uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL +FlagStatus COMP_GetOutStatus(COMPX COMPx); +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx); +void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK +void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN +void COMP_CMP2XorOut(bool En); +void COMP_StopOrLowpower32KClkSel(bool En); +void COMP_WindowModeEn(bool En); +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal); +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW); +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST); +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_ADC_H */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_crc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..7980eca3bae540087d64c1949165b5367b030727 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_crc.h @@ -0,0 +1,105 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_crc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_CRC_H__ +#define __N32G43X_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @addtogroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +void CRC32_ResetCrc(void); +uint32_t CRC32_CalcCrc(uint32_t Data); +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC32_GetCrc(void); +void CRC32_SetIDat(uint8_t IDValue); +uint8_t CRC32_GetIDat(void); + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength); +uint16_t CRC16_CalcCRC(uint8_t Data); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_CRC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dac.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..99206fcb82b3fb53cae9d541a4530e22d3e0b2ac --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dac.h @@ -0,0 +1,293 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dac.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_DAC_H__ +#define __N32G43X_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @addtogroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t + LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +} DAC_InitType; + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Constants + * @{ + */ + +/** @addtogroup DAC_trigger_selection + * @{ + */ + +#define DAC_TRG_NONE \ + ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \ + has been loaded, and not by external trigger */ +#define DAC_TRG_T6_TRGO \ + ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T8_TRGO \ + ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \ + only in High-density devices*/ +#define DAC_TRG_T7_TRGO \ + ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T5_TRGO \ + ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T2_TRGO \ + ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T4_TRGO \ + ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_EXT_IT9 \ + ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) \ + (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \ + || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \ + || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE)) + +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040) +#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) \ + (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_UNMASK_LFSRBITS1_0 \ + ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS2_0 \ + ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS3_0 \ + ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS4_0 \ + ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS5_0 \ + ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS6_0 \ + ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS7_0 \ + ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS8_0 \ + ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS9_0 \ + ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS10_0 \ + ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_UNMASK_LFSRBITS11_0 \ + ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \ + (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \ + || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \ + || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \ + || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \ + || ((VALUE) == DAC_TRIAMP_4095)) +/** + * @} + */ + +/** @addtogroup DAC_output_buffer + * @{ + */ + +#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002) +#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE)) +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup DAC_data_alignment + * @{ + */ + +#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000) +#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004) +#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) \ + (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT)) +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVE_NOISE ((uint32_t)0x00000040) +#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(DAC_InitType* DAC_InitStruct); +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct); +void DAC_Enable(FunctionalState Cmd); + +void DAC_DmaEnable(FunctionalState Cmd); +void DAC_SoftTrgEnable(FunctionalState Cmd); +void DAC_SoftwareTrgEnable(FunctionalState Cmd); +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd); +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data); +uint16_t DAC_GetOutputDataVal(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_DAC_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dbg.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dbg.h new file mode 100644 index 0000000000000000000000000000000000000000..c0617ab970f9c550beb346eabebaa785c41de40a --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dbg.h @@ -0,0 +1,124 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dbg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_DBG_H__ +#define __N32G43x_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @{ + */ + +/** @addtogroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBG_SLEEP ((uint32_t)0x00000001) +#define DBG_STOP ((uint32_t)0x00000002) +#define DBG_STDBY ((uint32_t)0x00000004) +#define DBG_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_TIM1_STOP ((uint32_t)0x00000400) +#define DBG_TIM2_STOP ((uint32_t)0x00000800) +#define DBG_TIM3_STOP ((uint32_t)0x00001000) +#define DBG_TIM4_STOP ((uint32_t)0x00002000) +#define DBG_CAN_STOP ((uint32_t)0x00004000) +#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBG_TIM8_STOP ((uint32_t)0x00020000) +#define DBG_TIM5_STOP ((uint32_t)0x00040000) +#define DBG_TIM6_STOP ((uint32_t)0x00080000) +#define DBG_TIM7_STOP ((uint32_t)0x00100000) +#define DBG_TIM9_STOP ((uint32_t)0x00200000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Functions + * @{ + */ + +void GetUCID(uint8_t *UCIDbuf); +void GetUID(uint8_t *UIDbuf); +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf); +uint32_t DBG_GetRevNum(void); +uint32_t DBG_GetDevNum(void); +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); + +uint32_t DBG_GetFlashSize(void); +uint32_t DBG_GetSramSize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43x_DBG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dma.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..98ba0d2af38b3d681e029467454d8c53d17614be --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_dma.h @@ -0,0 +1,469 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dma.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_DMA_H__ +#define __N32G43X_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @addtogroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t Direction; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in PeriphDataSize + or MemDataSize members depending in the transfer direction. */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t MemDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitType; + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) \ + (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \ + || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8)) + +/** @addtogroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010) +#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040) +#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080) +#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000) +#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100) +#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200) +#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \ + || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD)) +/** + * @} + */ + +/** @addtogroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \ + || ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @addtogroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020) +#define DMA_MODE_NORMAL ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup DMA_priority_level + * @{ + */ + +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000) +#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000) +#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000) +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \ + || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW)) +/** + * @} + */ + +/** @addtogroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_ENABLE ((uint32_t)0x00004000) +#define DMA_M2M_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE)) + +/** + * @} + */ + +/** @addtogroup DMA_interrupts_definition + * @{ + */ + +#define DMA_INT_TXC ((uint32_t)0x00000002) +#define DMA_INT_HTX ((uint32_t)0x00000004) +#define DMA_INT_ERR ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA_INT_GLB1 ((uint32_t)0x00000001) +#define DMA_INT_TXC1 ((uint32_t)0x00000002) +#define DMA_INT_HTX1 ((uint32_t)0x00000004) +#define DMA_INT_ERR1 ((uint32_t)0x00000008) +#define DMA_INT_GLB2 ((uint32_t)0x00000010) +#define DMA_INT_TXC2 ((uint32_t)0x00000020) +#define DMA_INT_HTX2 ((uint32_t)0x00000040) +#define DMA_INT_ERR2 ((uint32_t)0x00000080) +#define DMA_INT_GLB3 ((uint32_t)0x00000100) +#define DMA_INT_TXC3 ((uint32_t)0x00000200) +#define DMA_INT_HTX3 ((uint32_t)0x00000400) +#define DMA_INT_ERR3 ((uint32_t)0x00000800) +#define DMA_INT_GLB4 ((uint32_t)0x00001000) +#define DMA_INT_TXC4 ((uint32_t)0x00002000) +#define DMA_INT_HTX4 ((uint32_t)0x00004000) +#define DMA_INT_ERR4 ((uint32_t)0x00008000) +#define DMA_INT_GLB5 ((uint32_t)0x00010000) +#define DMA_INT_TXC5 ((uint32_t)0x00020000) +#define DMA_INT_HTX5 ((uint32_t)0x00040000) +#define DMA_INT_ERR5 ((uint32_t)0x00080000) +#define DMA_INT_GLB6 ((uint32_t)0x00100000) +#define DMA_INT_TXC6 ((uint32_t)0x00200000) +#define DMA_INT_HTX6 ((uint32_t)0x00400000) +#define DMA_INT_ERR6 ((uint32_t)0x00800000) +#define DMA_INT_GLB7 ((uint32_t)0x01000000) +#define DMA_INT_TXC7 ((uint32_t)0x02000000) +#define DMA_INT_HTX7 ((uint32_t)0x04000000) +#define DMA_INT_ERR7 ((uint32_t)0x08000000) +#define DMA_INT_GLB8 ((uint32_t)0x10000000) +#define DMA_INT_TXC8 ((uint32_t)0x20000000) +#define DMA_INT_HTX8 ((uint32_t)0x40000000) +#define DMA_INT_ERR8 ((uint32_t)0x80000000) + + +#define IS_DMA_CLR_INT(IT) ((IT) != 0x00) + +#define IS_DMA_GET_IT(IT) \ + (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \ + || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \ + || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \ + || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \ + || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \ + || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \ + || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \ + || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8)) + +/** + * @} + */ + +/** @addtogroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA_FLAG_TE8 ((uint32_t)0x80000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00) + +#define IS_DMA_GET_FLAG(FLAG) \ + (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \ + || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \ + || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \ + || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \ + || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \ + || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \ + || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \ + || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \ + || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \ + || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \ + || ((FLAG) == DMA_FLAG_TE8)) +/** + * @} + */ + +/** @addtogroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** @addtogroup DMA_remap_request_definition + * @{ + */ +#define DMA_REMAP_ADC1 ((uint32_t)0x00000000) +#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001) +#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002) +#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003) +#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004) +#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005) +#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006) +#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007) +#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008) +#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009) +#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A) +#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B) +#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C) +#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D) +#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E) +#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F) +#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010) +#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011) +#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012) +#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013) +#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014) +#define DMA_REMAP_DAC1 ((uint32_t)0x00000015) +#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016) +#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017) +#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018) +#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019) +#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A) +#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B) +#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C) +#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D) +#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E) +#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F) +#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020) +#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021) +#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022) +#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023) +#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024) +#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025) +#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026) +#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027) +#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028) +#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029) +#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A) +#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B) +#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C) +#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D) +#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E) +#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F) +#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030) +#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031) +#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032) +#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033) +#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034) +#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035) +#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036) +#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037) +#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038) +#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039) +#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A) +#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B) +#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C) +#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D) +#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E) + + +#define IS_DMA_REMAP(FLAG) \ + (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \ + || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \ + || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \ + || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \ + || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \ + || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \ + || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \ + || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \ + || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \ + || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \ + || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \ + || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \ + || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \ + || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \ + || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \ + || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \ + || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_ChannelType* DMAChx); +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam); +void DMA_StructInit(DMA_InitType* DMA_InitParam); +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd); +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd); +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy); +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy); +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_DMA_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_exti.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..b3b0f0b953ef4a1632308d2d17b1f025f18814e3 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_exti.h @@ -0,0 +1,232 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_exti.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_EXTI_H__ +#define __N32G43X_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @addtogroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTI_ModeType; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTI_TriggerType; + +#define IS_EXTI_TRIGGER(TRIGGER) \ + (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \ + || ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitType; + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Constants + * @{ + */ + +/** @addtogroup EXTI_Lines + * @{ + */ + +#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ +#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */ +#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */ +#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */ +#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */ +#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */ +#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */ + + + + + + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) \ + (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \ + || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \ + || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \ + || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \ + || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \ + || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \ + || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25)) + +/** + * @} + */ + +/** @addtogroup EXTI_TSSEL_Line + * @{ + */ +#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000) +#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */ +#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */ +#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */ +#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */ +#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */ +#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */ +#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */ +#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */ +#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */ +#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */ +#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */ +#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */ +#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */ +#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */ +#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */ +#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */ + +#define IS_EXTI_TSSEL_LINE(LINE) \ + (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \ + || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \ + || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \ + || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \ + || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \ + || ((LINE) == EXTI_TSSEL_LINE15)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct); +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct); +void EXTI_TriggerSWInt(uint32_t EXTI_Line); +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line); +void EXTI_ClrStatusFlag(uint32_t EXTI_Line); +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClrITPendBit(uint32_t EXTI_Line); +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_EXTI_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_flash.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..84b22db5ec2514f02d1f9b593906507f0b23ad1a --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_flash.h @@ -0,0 +1,502 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_flash.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_FLASH_H__ +#define __N32G43X_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_RESERVED, + FLASH_ERR_PG, + FLASH_ERR_PV, + FLASH_ERR_WRP, + FLASH_COMPL, + FLASH_ERR_EV, + FLASH_ERR_RDP2, + FLASH_ERR_ADD, + FLASH_TIMEOUT +} FLASH_STS; + +/** + * @brief FLASH_SMPSEL + */ + +typedef enum +{ + FLASH_SMP1 = 0, + FLASH_SMP2 +} FLASH_SMPSEL; + +/** + * @brief FLASH_HSICLOCK + */ + +typedef enum +{ + FLASH_HSICLOCK_ENABLE = 0, + FLASH_HSICLOCK_DISABLE +} FLASH_HSICLOCK; + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Constants + * @{ + */ + +/** @addtogroup Flash_Latency + * @{ + */ + +#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) \ + (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \ + || ((LATENCY) == FLASH_LATENCY_3)) +/** + * @} + */ + +/** @addtogroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS)) +/** + * @} + */ + +/** @addtogroup iCache_Enable_Disable + * @{ + */ + +#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */ +#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */ +#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS)) +/** + * @} + */ + +/** @addtogroup Low Voltage Mode + * @{ + */ + +#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */ +#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */ +#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS)) +/** + * @} + */ + +/** @addtogroup FLASH Sleep Mode + * @{ + */ + +#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */ +#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */ +#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS)) +/** + * @} + */ + +/** @addtogroup SMPSEL_SMP1_SMP2 + * @{ + */ + +#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */ +#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */ +#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2)) +/** + * @} + */ + +/* Values to be used with N32G43x devices */ +#define FLASH_WRP_Pages0to1 \ + ((uint32_t)0x00000001) /*!< N32G43x devices: \ + Write protection of page 0 to 1 */ +#define FLASH_WRP_Pages2to3 \ + ((uint32_t)0x00000002) /*!< N32G43x devices: \ + Write protection of page 2 to 3 */ +#define FLASH_WRP_Pages4to5 \ + ((uint32_t)0x00000004) /*!< N32G43x devices: \ + Write protection of page 4 to 5 */ +#define FLASH_WRP_Pages6to7 \ + ((uint32_t)0x00000008) /*!< N32G43x devices: \ + Write protection of page 6 to 7 */ +#define FLASH_WRP_Pages8to9 \ + ((uint32_t)0x00000010) /*!< N32G43x devices: \ + Write protection of page 8 to 9 */ +#define FLASH_WRP_Pages10to11 \ + ((uint32_t)0x00000020) /*!< N32G43x devices: \ + Write protection of page 10 to 11 */ +#define FLASH_WRP_Pages12to13 \ + ((uint32_t)0x00000040) /*!< N32G43x devices: \ + Write protection of page 12 to 13 */ +#define FLASH_WRP_Pages14to15 \ + ((uint32_t)0x00000080) /*!< N32G43x devices: \ + Write protection of page 14 to 15 */ +#define FLASH_WRP_Pages16to17 \ + ((uint32_t)0x00000100) /*!< N32G43x devices: \ + Write protection of page 16 to 17 */ +#define FLASH_WRP_Pages18to19 \ + ((uint32_t)0x00000200) /*!< N32G43x devices: \ + Write protection of page 18 to 19 */ +#define FLASH_WRP_Pages20to21 \ + ((uint32_t)0x00000400) /*!< N32G43x devices: \ + Write protection of page 20 to 21 */ +#define FLASH_WRP_Pages22to23 \ + ((uint32_t)0x00000800) /*!< N32G43x devices: \ + Write protection of page 22 to 23 */ +#define FLASH_WRP_Pages24to25 \ + ((uint32_t)0x00001000) /*!< N32G43x devices: \ + Write protection of page 24 to 25 */ +#define FLASH_WRP_Pages26to27 \ + ((uint32_t)0x00002000) /*!< N32G43x devices: \ + Write protection of page 26 to 27 */ +#define FLASH_WRP_Pages28to29 \ + ((uint32_t)0x00004000) /*!< N32G43x devices: \ + Write protection of page 28 to 29 */ +#define FLASH_WRP_Pages30to31 \ + ((uint32_t)0x00008000) /*!< N32G43x devices: \ + Write protection of page 30 to 31 */ +#define FLASH_WRP_Pages32to33 \ + ((uint32_t)0x00010000) /*!< N32G43x devices: \ + Write protection of page 32 to 33 */ +#define FLASH_WRP_Pages34to35 \ + ((uint32_t)0x00020000) /*!< N32G43x devices: \ + Write protection of page 34 to 35 */ +#define FLASH_WRP_Pages36to37 \ + ((uint32_t)0x00040000) /*!< N32G43x devices: \ + Write protection of page 36 to 37 */ +#define FLASH_WRP_Pages38to39 \ + ((uint32_t)0x00080000) /*!< N32G43x devices: \ + Write protection of page 38 to 39 */ +#define FLASH_WRP_Pages40to41 \ + ((uint32_t)0x00100000) /*!< N32G43x devices: \ + Write protection of page 40 to 41 */ +#define FLASH_WRP_Pages42to43 \ + ((uint32_t)0x00200000) /*!< N32G43x devices: \ + Write protection of page 42 to 43 */ +#define FLASH_WRP_Pages44to45 \ + ((uint32_t)0x00400000) /*!< N32G43x devices: \ + Write protection of page 44 to 45 */ +#define FLASH_WRP_Pages46to47 \ + ((uint32_t)0x00800000) /*!< N32G43x devices: \ + Write protection of page 46 to 47 */ +#define FLASH_WRP_Pages48to49 \ + ((uint32_t)0x01000000) /*!< N32G43x devices: \ + Write protection of page 48 to 49 */ +#define FLASH_WRP_Pages50to51 \ + ((uint32_t)0x02000000) /*!< N32G43x devices: \ + Write protection of page 50 to 51 */ +#define FLASH_WRP_Pages52to53 \ + ((uint32_t)0x04000000) /*!< N32G43x devices: \ + Write protection of page 52 to 53 */ +#define FLASH_WRP_Pages54to55 \ + ((uint32_t)0x08000000) /*!< N32G43x devices: \ + Write protection of page 54 to 55 */ +#define FLASH_WRP_Pages56to57 \ + ((uint32_t)0x10000000) /*!< N32G43x devices: \ + Write protection of page 56 to 57 */ +#define FLASH_WRP_Pages58to59 \ + ((uint32_t)0x20000000) /*!< N32G43x devices: \ + Write protection of page 58 to 59 */ +#define FLASH_WRP_Pages60to61 \ + ((uint32_t)0x40000000) /*!< N32G43x devices: \ + Write protection of page 60 to 61 */ +#define FLASH_WRP_Pages62to63 \ + ((uint32_t)0x80000000) /*!< N32G43x devices: + Write protection of page 62 to 63 */ + +#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRP_PAGE(PAGE) (1) //(((PAGE) <= FLASH_WRP_AllPages)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP1 + * @{ + */ + +#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */ +#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */ +#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ +#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) + + + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP2 + * @{ + */ + +#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */ +#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */ +#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT0 + * @{ + */ + +#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */ +#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */ +#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT1 + * @{ + */ + +#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */ +#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */ +#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nSWBOOT0 + * @{ + */ + +#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */ +#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */ +#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_BOR_LEV + * @{ + */ + +#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */ +#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */ +#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */ +#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */ +#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */ +#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */ +#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */ +#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */ +#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ + || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \ + || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \ + || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7)) + + +/** + * @} + */ +/** @addtogroup FLASH_Interrupts + * @{ + */ +#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */ +#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */ +#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ + +#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @addtogroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */ +#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) \ + (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \ + || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \ + || ((FLAG) == FLASH_FLAG_OBERR)) + +/** + * @} + */ + +/** @addtogroup FLASH_STS_CLRFLAG + * @{ + */ +#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR) + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for N32G43x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf); +void FLASH_iCacheRST(void); +void FLASH_iCacheCmd(uint32_t FLASH_iCache); +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM); +FlagStatus FLASH_GetLowVoltageModeSTS(void); +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM); +FlagStatus FLASH_GetFLASHSleepModeSTS(void); +FLASH_HSICLOCK FLASH_ClockInit(void); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address); +FLASH_STS FLASH_MassErase(void); +FLASH_STS FLASH_EraseOB(void); +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages); +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd); +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void); +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY); +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +uint32_t FLASH_GetUserOB(void); +uint32_t FLASH_GetWriteProtectionOB(void); +FlagStatus FLASH_GetReadOutProtectionSTS(void); +FlagStatus FLASH_GetReadOutProtectionL2STS(void); +FlagStatus FLASH_GetPrefetchBufSTS(void); +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel); +FLASH_SMPSEL FLASH_GetSMPSELStatus(void); +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd); +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_STS FLASH_GetSTS(void); +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_FLASH_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_gpio.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..06810d41b1be03926375b013570c4721aa7c0210 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_gpio.h @@ -0,0 +1,660 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_gpio.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_GPIO_H__ +#define __N32G43X_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @addtogroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) \ + (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD)) + + +#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\ + ((PERIPH) == (GPIOB))? 1 :\ + ((PERIPH) == (GPIOC))? 2 :3) +#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\ + ((INDEX)==((uint8_t)0x01))? GPIOB :\ + ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD ) + + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Slew_Rate_High = 0, + GPIO_Slew_Rate_Low +} GPIO_SpeedType; +#define IS_GPIO_SLEW_RATE(_RATE_) \ + (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low)) + +/** + * @brief driver strength config + */ + +typedef enum +{ + GPIO_DC_2mA = 0x00, + GPIO_DC_4mA = 0x10, + GPIO_DC_8mA = 0x01, + GPIO_DC_12mA= 0x11 +}GPIO_CurrentType; + +#define IS_GPIO_CURRENT(CURRENT) \ + (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \ + || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA)) +/** + * @brief Configuration Mode enumeration + */ + + +/** @brief GPIO_mode_define Mode definition + * @brief GPIO Configuration Mode + * Values convention: 0xW0yz00YZ + * - W : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ + +typedef enum +{ + GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */ + GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */ + GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */ + GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */ + GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */ + + GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */ + + GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */ + GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */ + GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + + GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */ + GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */ + GPIO_Mode_EVT_Rising_Falling = 0x10320000 +}GPIO_ModeType; + + + +/** + * @} + */ +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\ + ((__MODE__) == GPIO_Mode_Out_PP) ||\ + ((__MODE__) == GPIO_Mode_Out_OD) ||\ + ((__MODE__) == GPIO_Mode_AF_PP) ||\ + ((__MODE__) == GPIO_Mode_AF_OD) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising) ||\ + ((__MODE__) == GPIO_Mode_IT_Falling) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising) ||\ + ((__MODE__) == GPIO_Mode_EVT_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_Analog)) + +/** + * @} + */ + +/** + * @} + */ + +/** @brief GPIO_pull_define Pull definition + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ + +typedef enum +{ + GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */ + GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */ + GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */ +}GPIO_PuPdType; +/** + * @} + */ + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \ + ((__PULL__) == GPIO_Pull_Down)) +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIO_CurrentType GPIO_Current; /*!. + This paramter can be a value of @ref GPIO_CurrentType*/ + + GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_SpeedType */ + + GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_ModeType */ + + uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitType; + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} Bit_OperateType; + +#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET)) + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Exported_Constants + * @{ + */ + +/** @addtogroup GPIO_pins_define + * @{ + */ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF) + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) \ + (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \ + || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \ + || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \ + || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15)) + + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE)))) + + + + + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Port_Sources + * @{ + */ + +#define GPIOA_PORT_SOURCE ((uint8_t)0x00) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01) +#define GPIOC_PORT_SOURCE ((uint8_t)0x02) +#define GPIOD_PORT_SOURCE ((uint8_t)0x03) + +#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + + +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +/** + * @} + */ + +/** @addtogroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00) +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01) +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02) +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03) +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04) +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05) +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06) +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07) +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08) +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09) +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A) +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B) +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C) +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D) +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E) +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) \ + (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE15)) + +/** + * @} + */ + + + +/** @defgroup GPIOx_Alternate_function_selection Alternate function selection + * @{ + */ + +/* + * Alternate function AF0 + */ +#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */ +#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF1 + */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */ +#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF2 + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF3 + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF4 + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF5 + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */ +#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF6 + */ + +#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */ +#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */ +#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF7 + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */ +#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */ +#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */ +#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF8 + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */ +#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF9 + */ +#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */ +#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF15 + */ +#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */ + +#define GPIO_NO_AF (GPIO_AF15) +/** + * @} + */ + + +/** + * IS_GPIO_AF macro definition + */ + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \ + ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \ + ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \ + ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \ + ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \ + ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \ + ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \ + ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \ + ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \ + ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \ + ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \ + ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \ + ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \ + ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \ + ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \ + ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \ + ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF)) + + + + + +/** + * @} + */ +/** @defgroup GPIO Alternate function remaping + * @{ + */ +#define AFIO_SPI1_NSS (11U) +#define AFIO_SPI2_NSS (10U) + +#define IS_AFIO_SPIX(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS)) +typedef enum +{ + AFIO_SPI_NSS_High_IMPEDANCE = 0U, + AFIO_SPI_NSS_High_LEVEL = 1U +}AFIO_SPI_NSSType; + +#define IS_AFIO_SPI_NSS(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL)) + + +typedef enum +{ + AFIO_ADC_ETRI= 9U, + AFIO_ADC_ETRR = 8U +}AFIO_ADC_ETRType; + +typedef enum +{ + AFIO_ADC_TRIG_EXTI_0 = 0x0U, + AFIO_ADC_TRIG_EXTI_1 = 0x01U, + AFIO_ADC_TRIG_EXTI_2, + AFIO_ADC_TRIG_EXTI_3, + AFIO_ADC_TRIG_EXTI_4, + AFIO_ADC_TRIG_EXTI_5, + AFIO_ADC_TRIG_EXTI_6, + AFIO_ADC_TRIG_EXTI_7, + AFIO_ADC_TRIG_EXTI_8, + AFIO_ADC_TRIG_EXTI_9, + AFIO_ADC_TRIG_EXTI_10, + AFIO_ADC_TRIG_EXTI_11, + AFIO_ADC_TRIG_EXTI_12, + AFIO_ADC_TRIG_EXTI_13, + AFIO_ADC_TRIG_EXTI_14, + AFIO_ADC_TRIG_EXTI_15, + AFIO_ADC_TRIG_TIM8_CH3, + AFIO_ADC_TRIG_TIM8_CH4 +}AFIO_ADC_Trig_RemapType; + +#define IS_AFIO_ADC_ETR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR)) +#define IS_AFIO_ADC_ETRI(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4)) + +#define IS_AFIO_ADC_ETRR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3)) + + /** + * @} + */ + +/** @addtogroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_Module* GPIOx); +void GPIO_AFIOInitDefault(void); +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct); +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx); +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd); +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal); +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource); +void GPIO_CtrlEventOutput(FunctionalState Cmd); +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction); +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource); + +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType); +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_GPIO_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_i2c.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..aec2df11c865de57e0f4a7965ee7b17d6f69e9b5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_i2c.h @@ -0,0 +1,672 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_i2c.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_I2C_H__ +#define __N32G43X_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @addtogroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t ClkSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t BusMode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_BusMode */ + + uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t OwnAddr1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t AckEnable; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitType; + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2)) +/** @addtogroup I2C_BusMode + * @{ + */ + +#define I2C_BUSMODE_I2C ((uint16_t)0x0000) +#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002) +#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A) +#define IS_I2C_BUS_MODE(MODE) \ + (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST)) +/** + * @} + */ + +/** @addtogroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledgement + * @{ + */ + +#define I2C_ACKEN ((uint16_t)0x0400) +#define I2C_ACKDIS ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS)) +/** + * @} + */ + +/** @addtogroup I2C_transfer_direction + * @{ + */ + +#define I2C_DIRECTION_SEND ((uint8_t)0x00) +#define I2C_DIRECTION_RECV ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledged_address + * @{ + */ + +#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000) +#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000) +#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT)) +/** + * @} + */ + +/** @addtogroup I2C_registers + * @{ + */ + +#define I2C_REG_CTRL1 ((uint8_t)0x00) +#define I2C_REG_CTRL2 ((uint8_t)0x04) +#define I2C_REG_OADDR1 ((uint8_t)0x08) +#define I2C_REG_OADDR2 ((uint8_t)0x0C) +#define I2C_REG_DAT ((uint8_t)0x10) +#define I2C_REG_STS1 ((uint8_t)0x14) +#define I2C_REG_STS2 ((uint8_t)0x18) +#define I2C_REG_CLKCTRL ((uint8_t)0x1C) +#define I2C_REG_TMRISE ((uint8_t)0x20) +#define IS_I2C_REG(REGISTER) \ + (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \ + || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \ + || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE)) +/** + * @} + */ + +/** @addtogroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBALERT_LOW ((uint16_t)0x2000) +#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF) +#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH)) +/** + * @} + */ + +/** @addtogroup I2C_PEC_position + * @{ + */ + +#define I2C_PEC_POS_NEXT ((uint16_t)0x0800) +#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACK_POS_NEXT ((uint16_t)0x0800) +#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_BUF ((uint16_t)0x0400) +#define I2C_INT_EVENT ((uint16_t)0x0200) +#define I2C_INT_ERR ((uint16_t)0x0100) +#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_SMBALERT ((uint32_t)0x01008000) +#define I2C_INT_TIMOUT ((uint32_t)0x01004000) +#define I2C_INT_PECERR ((uint32_t)0x01001000) +#define I2C_INT_OVERRUN ((uint32_t)0x01000800) +#define I2C_INT_ACKFAIL ((uint32_t)0x01000400) +#define I2C_INT_ARLOST ((uint32_t)0x01000200) +#define I2C_INT_BUSERR ((uint32_t)0x01000100) +#define I2C_INT_TXDATE ((uint32_t)0x06000080) +#define I2C_INT_RXDATNE ((uint32_t)0x06000040) +#define I2C_INT_STOPF ((uint32_t)0x02000010) +#define I2C_INT_ADDR10F ((uint32_t)0x02000008) +#define I2C_INT_BYTEF ((uint32_t)0x02000004) +#define I2C_INT_ADDRF ((uint32_t)0x02000002) +#define I2C_INT_STARTBF ((uint32_t)0x02000001) + +#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_INT(IT) \ + (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \ + || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \ + || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \ + || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_flags_definition + * @{ + */ + +/** + * @brief STS2 register flags + */ + +#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000) +#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000) +#define I2C_FLAG_TRF ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSMODE ((uint32_t)0x00010000) + +/** + * @brief STS1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800) +#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400) +#define I2C_FLAG_ARLOST ((uint32_t)0x10000200) +#define I2C_FLAG_BUSERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXDATE ((uint32_t)0x10000080) +#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008) +#define I2C_FLAG_BYTEF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDRF ((uint32_t)0x10000002) +#define I2C_FLAG_STARTBF ((uint32_t)0x10000001) + +#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) \ + (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \ + || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \ + || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \ + || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \ + || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \ + || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \ + || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateStart() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* Master mode */ +#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */ +/* --EV5 */ +#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSMODE and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_SendAddr7bit() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */ +#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSMODE and ADDRF flags */ +/* --EV9 */ +#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSMODE and ADDR10F flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_RecvData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSMODE and RXDATNE flags */ +/* EV7x shifter register full */ +#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRF, BUSY, MSMODE, TXDATE flags */ +/* --EV8_2 */ +#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRF, BUSY, MSMODE, TXDATE and BSF flags */ + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_ConfigAck()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled + * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) + * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDRF flags */ +#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRF, BUSY, TXDATE and ADDRF flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRF, BUSY and TXDATE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and + * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXDATNE flags */ +/* --EV2x */ +#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */ +/* --EV4 */ +#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRF, BUSY, TXDATE and BSF flags */ +#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRF, BUSY and TXDATE flags */ +/* --EV3_2 */ +#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVT(EVENT) \ + (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS) \ + || ((EVENT) == I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD_NOBUSY)) +/** + * @} + */ + +/** @addtogroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @addtogroup I2C_clock_speed + * @{ + */ + +//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_Module* I2Cx); +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_InitStruct(I2C_InitType* I2C_InitStruct); +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd); +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); +uint8_t I2C_RecvData(I2C_Module* I2Cx); +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register); +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition); +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition); +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd); +uint8_t I2C_GetPec(I2C_Module* I2Cx); +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlag() function (see below). + * The returned value could be compared to events already defined in the + * library (n32g43x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT); +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..d0f045586e53def82f2f4758fdce81fd51f05455 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h @@ -0,0 +1,145 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_iwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_IWDG_H__ +#define __N32G43X_IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @addtogroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Constants + * @{ + */ + +/** @addtogroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WRITE_ENABLE ((uint16_t)0x5555) +#define IWDG_WRITE_DISABLE ((uint16_t)0x0000) +#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE)) +/** + * @} + */ + +/** @addtogroup IWDG_prescaler + * @{ + */ + +#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00) +#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01) +#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02) +#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03) +#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04) +#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05) +#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV256)) +/** + * @} + */ + +/** @addtogroup IWDG_Flag + * @{ + */ + +#define IWDG_PVU_FLAG ((uint16_t)0x0001) +#define IWDG_CRVU_FLAG ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler); +void IWDG_CntReload(uint16_t Reload); +void IWDG_ReloadKey(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_IWDG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lptim.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lptim.h new file mode 100644 index 0000000000000000000000000000000000000000..57b7c5f7fc3f50bb3272def008452bef0bc64367 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lptim.h @@ -0,0 +1,427 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------------- + */ +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32g43x_lptim.h + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ +#ifndef __n32g43x_LPTIM_H +#define __n32g43x_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "n32g43x.h" + +/** @addtogroup n32g43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPTIM + * @{ + */ + +//#if defined (LPTIM) + + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_EC_PRESCALER. + + This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ + + uint32_t Polarity; /*!< Specifies waveform polarity. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ +} LPTIM_InitType; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LPTIM_ReadReg function + * @{ + */ +#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */ +#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_IT IT Defines + * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions + * @{ + */ +#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +void LPTIM_DeInit(LPTIM_Module *LPTIMx); +void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct); +ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct); +void LPTIM_Disable(LPTIM_Module *LPTIMx); + + + +void LPTIM_Enable(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx); +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode); +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode); +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx); +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload); +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx); +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue); +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx); +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode); +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx); +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity); +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform); +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx); +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity); +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler); +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx); +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx); +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx); +void LPTIM_TrigSw(LPTIM_Module *LPTIMx); +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity); +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource); +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx); +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity); +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx); +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode); +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx); +/** + * @} + */ + +/** + * @} + */ + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __n32g43x_LPTIM_H */ + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h new file mode 100644 index 0000000000000000000000000000000000000000..f3faa00d0e3dd1ebe8084b5306c781fddcd14648 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h @@ -0,0 +1,280 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_lpuart.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_LPUART_H__ +#define __N32G43x_LPUART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @{ + */ + +/** @addtogroup LPUART_Exported_Types + * @{ + */ + +/** + * @brief LPUART Init Structure definition + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate))) + - FractionalDivider */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (only support + 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t RtsThreshold; /* Specifies RTS Threshold. + This parameter can be a value of @ref RtsThreshold */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref LPUART_Hardware_Flow_Control */ +} LPUART_InitType; + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Constants + * @{ + */ + +/** @addtogroup Parity + * @{ + */ + +#define LPUART_PE_NO ((uint16_t)0x0008) +#define LPUART_PE_EVEN ((uint16_t)0x0000) +#define LPUART_PE_ODD ((uint16_t)0x0001) +#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define LPUART_MODE_RX ((uint16_t)0x0000) +#define LPUART_MODE_TX ((uint16_t)0x0002) +#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX)) +/** + * @} + */ + +/** @addtogroup RtsThreshold + * @{ + */ + +#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000) +#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100) +#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200) +#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \ + (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU)) +/** + * @} + */ + +/** @addtogroup Hardware_Flow_Control + * @{ + */ +#define LPUART_HFCTRL_NONE ((uint16_t)0x0000) +#define LPUART_HFCTRL_CTS ((uint16_t)0x0400) +#define LPUART_HFCTRL_RTS ((uint16_t)0x0800) +#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00) +#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \ + || ((CONTROL) == LPUART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup LPUART_Interrupt_definition + * @{ + */ + +#define LPUART_INT_PE ((uint16_t)0x0001) +#define LPUART_INT_TXC ((uint16_t)0x0102) +#define LPUART_INT_FIFO_OV ((uint16_t)0x0204) +#define LPUART_INT_FIFO_FU ((uint16_t)0x0308) +#define LPUART_INT_FIFO_HF ((uint16_t)0x0410) +#define LPUART_INT_FIFO_NE ((uint16_t)0x0520) +#define LPUART_INT_WUF ((uint16_t)0x0640) +#define IS_LPUART_CFG_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_GET_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_CLR_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +/** + * @} + */ + +/** @addtogroup LPUART_DMA_Requests + * @{ + */ + +#define LPUART_DMAREQ_TX ((uint16_t)0x0020) +#define LPUART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup LPUART_WakeUp_methods + * @{ + */ + +#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000) +#define LPUART_WUSTP_RXNE ((uint16_t)0x1000) +#define LPUART_WUSTP_BYTE ((uint16_t)0x2000) +#define LPUART_WUSTP_FRAME ((uint16_t)0x3000) +#define IS_LPUART_WAKEUP(WAKEUP) \ + (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME)) +/** + * @} + */ + +/** @addtogroup LPUART_Sampling_methods + * @{ + */ + +#define LPUART_SMPCNT_3B ((uint16_t)0x0000) +#define LPUART_SMPCNT_1B ((uint16_t)0x4000) +#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B)) +/** + * @} + */ + +/** @addtogroup LPUART_Flags + * @{ + */ + +#define LPUART_FLAG_PEF ((uint16_t)0x0001) +#define LPUART_FLAG_TXC ((uint16_t)0x0002) +#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004) +#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008) +#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010) +#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020) +#define LPUART_FLAG_CTS ((uint16_t)0x0040) +#define LPUART_FLAG_WUF ((uint16_t)0x0080) +#define LPUART_FLAG_NF ((uint16_t)0x0100) +#define IS_LPUART_FLAG(FLAG) \ + (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \ + || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \ + || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF)) + +#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000)) + +#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Functions + * @{ + */ + +void LPUART_DeInit(void); +void LPUART_Init(LPUART_InitType* LPUART_InitStruct); +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct); +void LPUART_FlushRxFifo(void); +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd); +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd); +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod); +void LPUART_EnableWakeUpStop(FunctionalState Cmd); +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod); +void LPUART_EnableLoopBack(FunctionalState Cmd); +void LPUART_SendData(uint8_t Data); +uint8_t LPUART_ReceiveData(void); +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData); +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG); +void LPUART_ClrFlag(uint16_t LPUART_FLAG); +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT); +void LPUART_ClrIntPendingBit(uint16_t LPART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43x_LPUART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_opamp.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_opamp.h new file mode 100644 index 0000000000000000000000000000000000000000..3cb413f680746e7811c538eb1381ee8940a8b010 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_opamp.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_opamp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_OPAMPMP_H__ +#define __N32G43X_OPAMPMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" +#include + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @{ + */ + +/** @addtogroup OPAMP_Exported_Constants + * @{ + */ +typedef enum +{ + OPAMP1 = 0, + OPAMP2 = 4, +} OPAMPX; + +// OPAMP_CS +typedef enum +{ + OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24), + OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24), +}OPAMP2_CS_TIMSRCSEL; +typedef enum +{ + OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19), + OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19), + OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19), + OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19), + OPAMP1_CS_VPSSEL_NC = (0x04L << 19), + + OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19), + OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19), + OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19), + OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19), + OPAMP2_CS_VPSSEL_NC = (0x04L << 19), +} OPAMP_CS_VPSSEL; +typedef enum +{ + OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17), + OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17), + OPAMP1_CS_VMSSEL_NC = (0x02L << 17), + OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17), + + OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17), + OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17), + OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17), + OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17), +} OPAMP_CS_VMSSEL; + +typedef enum +{ + OPAMP1_CS_VPSEL_PA1 = (0x00L << 8), + OPAMP1_CS_VPSEL_PA5 = (0x01L << 8), + OPAMP1_CS_VPSEL_PA4 = (0x02L << 8), + OPAMP1_CS_VPSEL_PA7 = (0x03L << 8), + OPAMP1_CS_VPSEL_NC = (0x04L << 8), + + OPAMP2_CS_VPSEL_PA7 = (0x00L << 8), + OPAMP2_CS_VPSEL_PA4 = (0x01L << 8), + OPAMP2_CS_VPSEL_PB14 = (0x02L << 8), + OPAMP2_CS_VPSEL_PD13 = (0x03L << 8), + OPAMP2_CS_VPSEL_NC = (0x04L << 8), +} OPAMP_CS_VPSEL; +typedef enum +{ + OPAMP1_CS_VMSEL_PA3 = (0x00L << 6), + OPAMP1_CS_VMSEL_PC5 = (0x01L << 6), + OPAMPx_CS_VMSEL_NC = (0x02L << 6), + OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6), + + OPAMP2_CS_VMSEL_PC5 = (0x00L << 6), + OPAMP2_CS_VMSEL_PB0 = (0x01L << 6), + OPAMP2_CS_VMSEL_PA5 = (0x02L << 6), + OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6), +} OPAMP_CS_VMSEL; +typedef enum +{ + OPAMP_CS_PGA_GAIN_2 = (0x00 << 3), + OPAMP_CS_PGA_GAIN_4 = (0x01 << 3), + OPAMP_CS_PGA_GAIN_8 = (0x02 << 3), + OPAMP_CS_PGA_GAIN_16 = (0x03 << 3), + OPAMP_CS_PGA_GAIN_32 = (0x04 << 3), +} OPAMP_CS_PGA_GAIN; +typedef enum +{ + OPAMP_CS_EXT_OPAMP = (0x00 << 1), + OPAMP_CS_PGA_EN = (0x02 << 1), + OPAMP_CS_FOLLOW = (0x03 << 1), +} OPAMP_CS_MOD; + +// bit mask +#define OPAMP_CS_EN_MASK (0x01L << 0) +#define OPAMP_CS_MOD_MASK (0x03L << 1) +#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3) +#define OPAMP_CS_VMSEL_MASK (0x03L << 6) +#define OPAMP_CS_VPSEL_MASK (0x07L << 8) +#define OPAMP_CS_CALON_MASK (0x01L << 11) +#define OPAMP_CS_TSTREF_MASK (0x01L << 13) +#define OPAMP_CS_CALOUT_MASK (0x01L << 14) +#define OPAMP_CS_RANGE_MASK (0x01L << 15) +#define OPAMP_CS_TCMEN_MASK (0x01L << 16) +#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17) +#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19) +#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24) +/** @addtogroup OPAMP_LOCK + * @{ + */ +#define OPAMP_LOCK_1 0x01L +#define OPAMP_LOCK_2 0x02L +/** + * @} + */ +/** + * @} + */ + +/** + * @brief OPAMP Init structure definition + */ + +typedef struct +{ + OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/ + + FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */ + + FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/ + + OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */ + + OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/ +} OPAMP_InitType; + +/** @addtogroup OPAMP_Exported_Functions + * @{ + */ + +void OPAMP_DeInit(void); +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain); +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel); +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel); +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel); +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel); +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx); +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_ADC_H */ + /** + * @} + */ + /** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_pwr.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_pwr.h new file mode 100644 index 0000000000000000000000000000000000000000..a040a59701252f67565dbf41d406c5a42dd9e361 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_pwr.h @@ -0,0 +1,224 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_pwr.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_PWR_H__ +#define __N32G43x_PWR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @addtogroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Constants + * @{ + */ + +/** @addtogroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000) +#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002) +#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004) +#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006) +#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008) +#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A) +#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C) +#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E) + + +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \ + || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \ + || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) ) + +/** + * @} + */ + +/** @addtogroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_REGULATOR_ON ((uint32_t)0x00000000) +#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER)) +/** + * @} + */ + +/** @defgroup SLEEP_mode_entry + * @{ + */ +#define SLEEP_ON_EXIT (1) +#define SLEEP_OFF_EXIT (0) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + + +/** + * @} + */ + + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + +/** @addtogroup PWR_Flag + * @{ + */ +//STS1 +#define PWR_WKUP0_FLAG ((uint32_t)0x00000001) +#define PWR_WKUP1_FLAG ((uint32_t)0x00000002) +#define PWR_WKUP2_FLAG ((uint32_t)0x00000004) +#define PWR_STBY_FLAG ((uint32_t)0x00000100) +//STS2 +#define PWR_LPRUN_FLAG ((uint32_t)0x00000001) +#define PWR_MR_FLAG ((uint32_t)0x00000002) +#define PWR_PVDO_FLAG ((uint32_t)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + +#define IS_PWR_CLEAR_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + + + +/** @addtogroup SRAM1oSRAM2 retention set + * @{ + */ +//#define SRAM1DIS_SRAM2DIS 0 +//#define SRAM1EN_SRAM2DIS 1 + +//#define SRAM1DIS_SRAM2EN 2 +//#define SRAM1EN_SRAM2EN 3 +/** @addtogroup MR VOLTAGE + * @{ + */ +#define MR_1V0 2 +#define MR_1V1 3 + + +/** + * @} + */ +typedef enum +{ + WAKEUP_PIN0 = 0x0001, + WAKEUP_PIN1 = 0x0002, + WAKEUP_PIN2 = 0x0004, +} WAKEUP_PINX; +/** @addtogroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ +#define LPRUN_SWITCH_ADDR (__IO unsigned*)(0x40007000) +#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20) +#define CLERR_BIT25 0xfdffffff //bit25 +#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while(0) //0:0.9V 1:1.1V +#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while(0) //0:always on 1:duty on +#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while(0) //0:normal mode 1:standby mode +#define _SetLprunSwitch(vale) do{(*LPRUN_SWITCH_ADDR) &= (~0x0600);(*LPRUN_SWITCH_ADDR) |= (uint32_t)(vale <<9);}while(0) +/** @addtogroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessEnable(FunctionalState Cmd); +void PWR_PvdEnable(FunctionalState Cmd); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd); +void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry); +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret); +void PWR_EnterLowPowerRunMode(void); +void PWR_ExitLowPowerRunMode(void); +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry); + +FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_WakeUpPinConfig(void); +void SetSysClock_MSI(void); +uint8_t GetMrVoltage(void); +void PWR_MRconfig(uint8_t voltage); +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43x_PWR_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rcc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rcc.h new file mode 100644 index 0000000000000000000000000000000000000000..baf80543084db95425c27bdc5ec856a68da66c19 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rcc.h @@ -0,0 +1,911 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_rcc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_RCC_H__ +#define __N32G43X_RCC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */ + uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */ +} RCC_ClocksType; + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ + +/** @addtogroup HSE_configuration + * @{ + */ + +#define RCC_HSE_DISABLE ((uint32_t)0x00000000) +#define RCC_HSE_ENABLE ((uint32_t)0x00010000) +#define RCC_HSE_BYPASS ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS)) + +/** + * @} + */ + +/** @addtogroup HSI_configuration + * @{ + */ + +#define RCC_HSI_DISABLE ((uint32_t)0x00000000) +#define RCC_HSI_ENABLE ((uint32_t)0x00000001) +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE)) + +/** + * @} + */ + +/** @addtogroup MSI_configuration + * @{ + */ + +#define RCC_MSI_DISABLE ((uint32_t)0x00000000) +#define RCC_MSI_ENABLE ((uint32_t)0x00000004) +#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE)) + +#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000) +#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010) +#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020) +#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030) +#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040) +#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050) +#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060) +#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \ + ) + +/** + * @} + */ + +/** @addtogroup PLL_entry_clock_source + * @{ + */ +#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000) +#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001) + +#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000) +#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000) +#define IS_RCC_PLL_SRC(SOURCE) \ + (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \ + || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2)) + +#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000) +#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002) +#define IS_RCC_PLL_DIVCLK(DIVCLK) \ + (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE)) + +/** + * @} + */ + +/** @addtogroup PLL_multiplication_factor + * @{ + */ +#define RCC_PLL_MUL_2 ((uint32_t)0x00000000) +#define RCC_PLL_MUL_3 ((uint32_t)0x00040000) +#define RCC_PLL_MUL_4 ((uint32_t)0x00080000) +#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000) +#define RCC_PLL_MUL_6 ((uint32_t)0x00100000) +#define RCC_PLL_MUL_7 ((uint32_t)0x00140000) +#define RCC_PLL_MUL_8 ((uint32_t)0x00180000) +#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000) +#define RCC_PLL_MUL_10 ((uint32_t)0x00200000) +#define RCC_PLL_MUL_11 ((uint32_t)0x00240000) +#define RCC_PLL_MUL_12 ((uint32_t)0x00280000) +#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000) +#define RCC_PLL_MUL_14 ((uint32_t)0x00300000) +#define RCC_PLL_MUL_15 ((uint32_t)0x00340000) +#define RCC_PLL_MUL_16 ((uint32_t)0x00380000) +#define RCC_PLL_MUL_17 ((uint32_t)0x08000000) +#define RCC_PLL_MUL_18 ((uint32_t)0x08040000) +#define RCC_PLL_MUL_19 ((uint32_t)0x08080000) +#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000) +#define RCC_PLL_MUL_21 ((uint32_t)0x08100000) +#define RCC_PLL_MUL_22 ((uint32_t)0x08140000) +#define RCC_PLL_MUL_23 ((uint32_t)0x08180000) +#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000) +#define RCC_PLL_MUL_25 ((uint32_t)0x08200000) +#define RCC_PLL_MUL_26 ((uint32_t)0x08240000) +#define RCC_PLL_MUL_27 ((uint32_t)0x08280000) +#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000) +#define RCC_PLL_MUL_29 ((uint32_t)0x08300000) +#define RCC_PLL_MUL_30 ((uint32_t)0x08340000) +#define RCC_PLL_MUL_31 ((uint32_t)0x08380000) +#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000) +#define IS_RCC_PLL_MUL(MUL) \ + (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \ + || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \ + || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \ + || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \ + || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \ + || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \ + || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \ + || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \ + || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \ + || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32)) + +/** + * @} + */ + +/** @addtogroup System_clock_source + * @{ + */ + +#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000) +#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001) +#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002) +#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003) +#define IS_RCC_SYSCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \ + || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK)) +/** + * @} + */ + +/** @addtogroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0) +#define IS_RCC_SYSCLK_DIV(HCLK) \ + (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \ + || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \ + || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @addtogroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_HCLK_DIV2 ((uint32_t)0x00000400) +#define RCC_HCLK_DIV4 ((uint32_t)0x00000500) +#define RCC_HCLK_DIV8 ((uint32_t)0x00000600) +#define RCC_HCLK_DIV16 ((uint32_t)0x00000700) +#define IS_RCC_HCLK_DIV(PCLK) \ + (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \ + || ((PCLK) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @addtogroup RCC_Interrupt_source + * @{ + */ + +#define RCC_INT_LSIRDIF ((uint8_t)0x01) +#define RCC_INT_LSERDIF ((uint8_t)0x02) +#define RCC_INT_HSIRDIF ((uint8_t)0x04) +#define RCC_INT_HSERDIF ((uint8_t)0x08) +#define RCC_INT_PLLRDIF ((uint8_t)0x10) +#define RCC_INT_BORIF ((uint8_t)0x20) +#define RCC_INT_MSIRDIF ((uint8_t)0x40) +#define RCC_INT_CLKSSIF ((uint8_t)0x80) + +#define IS_RCC_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF)) + +#define IS_RCC_GET_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF)) + +#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000) +#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000) +#define RCC_CLR_LSERDIF ((uint32_t)0x00020000) +#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000) +#define RCC_CLR_HSERDIF ((uint32_t)0x00080000) +#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000) +#define RCC_CLR_BORIF ((uint32_t)0x00200000) +#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000) + +#define IS_RCC_CLR_INTF(IT) \ + (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \ + || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF)) + +/** + * @} + */ + +/** @addtogroup USB_Device_clock_source + * @{ + */ + +#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00) +#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01) +#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02) +#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03) + +#define IS_RCC_USBCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \ + || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3)) +/** + * @} + */ + +/** @addtogroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000) +#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000) +#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000) +#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000) +#define IS_RCC_PCLK2_DIV(ADCCLK) \ + (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \ + || ((ADCCLK) == RCC_PCLK2_DIV8)) + +/** + * @} + */ + +/** @addtogroup RCC_CFGR2_Config + * @{ + */ +#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000) +#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000) +#define IS_RCC_TIM18CLKSRC(TIM18CLK) \ + (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK)) + +#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000) +#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000) +#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000) +#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000) +#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000) +#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000) +#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000) +#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000) +#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000) +#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000) +#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000) +#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000) +#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000) +#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000) +#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000) +#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000) +#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000) +#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000) +#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000) +#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000) +#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000) +#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000) +#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000) +#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000) +#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000) +#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000) +#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000) +#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000) +#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000) +#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000) +#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000) +#define IS_RCC_RNGCCLKPRE(DIV) \ + (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32)) + +#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE)) + +#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000) +#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000) +#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000) +#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000) +#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000) +#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000) +#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000) +#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000) +#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000) +#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000) +#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000) +#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000) +#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000) +#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000) +#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000) +#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000) +#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000) +#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000) +#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000) +#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000) +#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000) +#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000) +#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000) +#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000) +#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000) +#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000) +#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000) +#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000) +#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000) +#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000) +#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000) +#define IS_RCC_ADC1MCLKPRE(DIV) \ + (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \ + || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \ + || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \ + || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \ + || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \ + || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \ + || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \ + || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \ + || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \ + || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \ + || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32)) + +#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) +#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) +#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) +#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) +#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) +#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) +#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) +#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) +#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) +#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) +#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) +#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) +#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) +#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) +#define IS_RCC_ADCPLLCLKPRE(DIV) \ + (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \ + || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \ + || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \ + || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \ + || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0)) + +#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) +#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) +#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) +#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) +#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) +#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) +#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) +#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) +#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) +#define IS_RCC_ADCHCLKPRE(DIV) \ + (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \ + || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \ + || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \ + || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00)) +/** + * @} + */ + +/** @addtogroup RCC_CFGR3_Config + * @{ + */ + +#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000) +#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF) + +#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \ + (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE)) + +#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000) +#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800) +#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000) +#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800) +#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000) +#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800) +#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000) +#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800) +#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000) +#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800) +#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000) +#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800) +#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000) +#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800) +#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000) +#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800) +#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000) +#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800) +#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000) +#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800) +#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000) +#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800) +#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000) +#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800) +#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000) +#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800) +#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000) +#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800) +#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000) +#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800) +#define IS_RCC_TRNG1MCLKPRE(VAL) \ + (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \ + || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \ + || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \ + || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \ + || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \ + || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \ + || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \ + || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \ + || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \ + || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \ + || ((VAL) == RCC_TRNG1MCLK_DIV62)) + +#define RCC_UCDR_ENABLE ((uint32_t)0x00000080) +#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F) + +#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF) +#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000) +#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200) +#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \ + (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO)) + +#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF) +#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000) +#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100) +#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \ + (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE)) + +/** + * @} + */ + +/** @addtogroup LSE_configuration + * @{ + */ + +#define RCC_LSE_DISABLE ((uint32_t)0x00000000) +#define RCC_LSE_ENABLE ((uint32_t)0x00000001) +#define RCC_LSE_BYPASS ((uint32_t)0x00000004) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @addtogroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000) +#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \ + || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32)) +/** + * @} + */ + +/** @addtogroup LSX_clock_source + * @{ + */ + +#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000) +#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020) +#define IS_RCC_LSXCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE)) +/** + * @} + */ + +/** @addtogroup AHB_peripheral + * @{ + */ + +#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001) +#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004) +#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010) +#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040) +#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200) +#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800) +#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup APB2_peripheral + * @{ + */ + +#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001) +#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000) +#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000) +#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000) +#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup APB1_peripheral + * @{ + */ + +#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040) +#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080) +#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100) +#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200) +#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400) +#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800) +#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000) +#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000) +#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000) +#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000) +#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000) +#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000) +#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup RET_peripheral + * @{ + */ + +#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040) +#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080) + +#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFF3F) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup LPTIM + * @{ + */ +#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8) + +#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001) +#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002) +#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003) +#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004) +#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005) + +#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2)) + +/** + * @} + */ + +/** @addtogroup LPUART + * @{ + */ +#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7) + +#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008) +#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010) +#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018) + +#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00) + +/** + * @} + */ + +/** @addtogroup SRAM_CTRLSTS + * @{ + */ + +#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001) +#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008) +#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \ + || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT)) + +#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002) +#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010) +#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \ + || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET)) + +#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004) +#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020) +#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \ + || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG)) + +/** + * @} + */ + +#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000) +#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000) +#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000) +#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000) +#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000) +#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000) +#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000) +#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000) +#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000) +#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000) +#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000) +#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000) +#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000) +#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000) +#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000) +#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000) +#define IS_RCC_MCOCLKPRE(NUM) \ + (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \ + || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \ + || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \ + || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \ + || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \ + || ((NUM) == RCC_MCO_CLK_NUM15)) + +/** @addtogroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NOCLK ((uint8_t)0x00) +#define RCC_MCO_LSI ((uint8_t)0x01) +#define RCC_MCO_LSE ((uint8_t)0x02) +#define RCC_MCO_MSI ((uint8_t)0x03) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +#define IS_RCC_MCO(MCO) \ + (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \ + || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK)) + +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21) +#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31) +#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39) +#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41) +#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44) +#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C) +#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E) +#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61) +#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63) +#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77) +#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79) +#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A) +#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B) +#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C) +#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D) +#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E) +#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) \ + (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF)) + +#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_ConfigHse(uint32_t RCC_HSE); +ErrorStatus RCC_WaitHseStable(void); +void RCC_ConfigHsi(uint32_t RCC_HSI); +ErrorStatus RCC_WaitHsiStable(void); +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue); +void RCC_EnableHsi(FunctionalState Cmd); +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range); +ErrorStatus RCC_WaitMsiStable(void); +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue); +void RCC_EnableMsi(FunctionalState Cmd); +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK); +void RCC_EnablePll(FunctionalState Cmd); + +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSysclkSrc(void); +void RCC_ConfigHclk(uint32_t RCC_SYSCLK); +void RCC_ConfigPclk1(uint32_t RCC_HCLK); +void RCC_ConfigPclk2(uint32_t RCC_HCLK); +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd); + +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource); + +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource); +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler); + +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler); +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd); +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler); + +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler); +void RCC_EnableTrng1mClk(FunctionalState Cmd); + +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd); + +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode); + +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd); +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd); + +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource); +uint32_t RCC_GetLSXClkSrc(void); + +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource); +uint32_t RCC_GetLPTIMClkSrc(void); +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource); +uint32_t RCC_GetLPUARTClkSrc(void); + +void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd); +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd); +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag); + +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim); +void RCC_EnableLsi(FunctionalState Cmd); +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource); +void RCC_EnableRtcClk(FunctionalState Cmd); +uint32_t RCC_GetRTCClkSrc(void); +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks); +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd); + +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd); +void RCC_EnableLowPowerReset(FunctionalState Cmd); +void RCC_EnableClockSecuritySystem(FunctionalState Cmd); +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd); +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void); +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler); +void RCC_ConfigMco(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClrFlag(void); +INTStatus RCC_GetIntStatus(uint8_t RccInt); +void RCC_ClrIntPendingBit(uint32_t RccClrInt); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_RCC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rtc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..4115158ba14659c933c5c0debe3aebe75512e8a4 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_rtc.h @@ -0,0 +1,789 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_rtc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_RTC_H__ +#define __N32G43X_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x7FFF */ +} RTC_InitType; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_12HOUR_FORMAT is selected or 0-23 range if + the RTC_24HOUR_FORMAT is selected. */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +} RTC_TimeType; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +} RTC_DateType; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +} RTC_AlarmType; + +/** @addtogroup RTC_Exported_Constants + * @{ + */ + +/** @addtogroup RTC_Hour_Formats + * @{ + */ +#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000) +#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT)) +/** + * @} + */ + +/** @addtogroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + +/** @addtogroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @addtogroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_AM_H12 ((uint8_t)0x00) +#define RTC_PM_H12 ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12)) + +/** + * @} + */ + +/** @addtogroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @addtogroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRURY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @addtogroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000) +#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \ + (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000) +#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000) +#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000) +#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_A_ALARM ((uint32_t)0x00000100) +#define RTC_B_ALARM ((uint32_t)0x00000200) +#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM)) +#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions + * @{ + */ +#define RTC_SUBS_MASK_ALL \ + ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \ + There is no comparison on sub seconds \ + for Alarm */ +#define RTC_SUBS_MASK_SS14_1 \ + ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \ + comparison. Only SS[0] is compared. */ +#define RTC_SUBS_MASK_SS14_2 \ + ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \ + comparison. Only SS[1:0] are compared */ +#define RTC_SUBS_MASK_SS14_3 \ + ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \ + comparison. Only SS[2:0] are compared */ +#define RTC_SUBS_MASK_SS14_4 \ + ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \ + comparison. Only SS[3:0] are compared */ +#define RTC_SUBS_MASK_SS14_5 \ + ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \ + comparison. Only SS[4:0] are compared */ +#define RTC_SUBS_MASK_SS14_6 \ + ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \ + comparison. Only SS[5:0] are compared */ +#define RTC_SUBS_MASK_SS14_7 \ + ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \ + comparison. Only SS[6:0] are compared */ +#define RTC_SUBS_MASK_SS14_8 \ + ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \ + comparison. Only SS[7:0] are compared */ +#define RTC_SUBS_MASK_SS14_9 \ + ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \ + comparison. Only SS[8:0] are compared */ +#define RTC_SUBS_MASK_SS14_10 \ + ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \ + comparison. Only SS[9:0] are compared */ +#define RTC_SUBS_MASK_SS14_11 \ + ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \ + comparison. Only SS[10:0] are compared */ +#define RTC_SUBS_MASK_SS14_12 \ + ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \ + comparison.Only SS[11:0] are compared */ +#define RTC_SUBS_MASK_SS14_13 \ + ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \ + comparison. Only SS[12:0] are compared */ +#define RTC_SUBS_MASK_SS14_14 \ + ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \ + comparison.Only SS[13:0] are compared */ +#define RTC_SUBS_MASK_NONE \ + ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \ + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \ + (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \ + || ((INTEN) == RTC_SUBS_MASK_NONE)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004) +#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define IS_RTC_WKUP_CLOCK(CLOCK) \ + (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \ + || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \ + || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS)) +#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @addtogroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \ + (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING)) +/** + * @} + */ + +/** @addtogroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_OUTPUT_DIS ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALA ((uint32_t)0x00200000) +#define RTC_OUTPUT_ALB ((uint32_t)0x00400000) +#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT_MODE(OUTPUT) \ + (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \ + || ((OUTPUT) == RTC_OUTPUT_WKUP)) + +/** + * @} + */ + +/** @addtogroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPOL_LOW ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW)) +/** + * @} + */ + + +/** @addtogroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000) +#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ)) +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define SMOOTH_CALIB_32SEC \ + ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 32s, else 2exp20 RTCCLK seconds */ +#define SMOOTH_CALIB_16SEC \ + ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 16s, else 2exp19 RTCCLK seconds */ +#define SMOOTH_CALIB_8SEC \ + ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \ + (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \ + ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \ + during a X -second window = Y - CALM[8:0]. \ + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \ + ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \ + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \ + (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @addtogroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H)) + +#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) \ + (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET)) +/** + * @} + */ + +/** @addtogroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL)) + +/** + * @} + */ + +/** @addtogroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000) +#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE)) +/** + * @} + */ + +/** @addtogroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + +/** + * @} + */ + +/** @addtogroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TISOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TISF ((uint32_t)0x00000800) +#define RTC_FLAG_WTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSYF ((uint32_t)0x00000020) +#define RTC_FLAG_INITSF ((uint32_t)0x00000010) +#define RTC_FLAG_SHOPF ((uint32_t)0x00000008) +#define RTC_FLAG_WTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \ + ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \ + ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \ + ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \ + ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \ + ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \ + ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_INT_TAMP3 ((uint32_t)0x00080000) +#define RTC_INT_TAMP2 ((uint32_t)0x00040000) +#define RTC_INT_TAMP1 ((uint32_t)0x00020000) +#define RTC_INT_TS ((uint32_t)0x00008000) +#define RTC_INT_WUT ((uint32_t)0x00004000) +#define RTC_INT_ALRB ((uint32_t)0x00002000) +#define RTC_INT_ALRA ((uint32_t)0x00001000) + +#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_INT(IT) \ + (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA)) +#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ + +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for + input tamper 1 */ +#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for + input tamper 2 */ +#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for + input tamper 3 */ +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + + +#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_EnableWriteProtection(FunctionalState Cmd); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd); +void RTC_EnableBypassShadow(FunctionalState Cmd); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd); +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd); + +/* Daylight Saving configuration functions ************************************/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse and Smooth Calibration configuration functions **********************/ +void RTC_EnableCalibOutput(FunctionalState Cmd); +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput); +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Output Type Config configuration functions *********************************/ +void RTC_ConfigOutputType(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClrFlag(uint32_t RTC_FLAG); +INTStatus RTC_GetITStatus(uint32_t RTC_INT); +void RTC_ClrIntPendingBit(uint32_t RTC_INT); + +/* WakeUp TSC function **********************************/ +void RTC_EnableWakeUpTsc(uint32_t count); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState); +void RTC_TamperTAMPTSCmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_RTC_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_spi.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..df4a06a14390ca2326553c255c1286eabcd5288b --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_spi.h @@ -0,0 +1,470 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_spi.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_SPI_H__ +#define __N32G43x_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @addtogroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SpiMode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t DataLen; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t CLKPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitType; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2sMode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2sMode */ + + uint16_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref Standard */ + + uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitType; + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2)) + + +/** @addtogroup SPI_data_direction + * @{ + */ + +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400) +#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000) +#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000) +#define IS_SPI_DIR_MODE(MODE) \ + (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ + || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX)) +/** + * @} + */ + +/** @addtogroup SPI_mode + * @{ + */ + +#define SPI_MODE_MASTER ((uint16_t)0x0104) +#define SPI_MODE_SLAVE ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) +/** + * @} + */ + +/** @addtogroup SPI_data_size + * @{ + */ + +#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CLKPOL_LOW ((uint16_t)0x0000) +#define SPI_CLKPOL_HIGH ((uint16_t)0x0002) +#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) +#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001) +#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) +/** + * @} + */ + +/** @addtogroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_SOFT ((uint16_t)0x0200) +#define SPI_NSS_HARD ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) +/** + * @} + */ + +/** @addtogroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) +#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008) +#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010) +#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018) +#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020) +#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028) +#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030) +#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038) +#define IS_SPI_BR_PRESCALER(PRESCALER) \ + (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \ + || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \ + || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \ + || ((PRESCALER) == SPI_BR_PRESCALER_256)) +/** + * @} + */ + +/** @addtogroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FB_MSB ((uint16_t)0x0000) +#define SPI_FB_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) +/** + * @} + */ + +/** @addtogroup I2sMode + * @{ + */ + +#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000) +#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100) +#define I2S_MODE_MASTER_TX ((uint16_t)0x0200) +#define I2S_MODE_MASTER_RX ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) \ + (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \ + || ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @addtogroup Standard + * @{ + */ + +#define I2S_STD_PHILLIPS ((uint16_t)0x0000) +#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010) +#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020) +#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030) +#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) \ + (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \ + || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME)) +/** + * @} + */ + +/** @addtogroup I2S_Data_Format + * @{ + */ + +#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000) +#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001) +#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003) +#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005) +#define IS_I2S_DATA_FMT(FORMAT) \ + (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \ + || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS)) +/** + * @} + */ + +/** @addtogroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLK_ENABLE ((uint16_t)0x0200) +#define I2S_MCLK_DISABLE ((uint16_t)0x0000) +#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE)) +/** + * @} + */ + +/** @addtogroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AUDIO_FREQ_192K ((uint32_t)192000) +#define I2S_AUDIO_FREQ_96K ((uint32_t)96000) +#define I2S_AUDIO_FREQ_48K ((uint32_t)48000) +#define I2S_AUDIO_FREQ_44K ((uint32_t)44100) +#define I2S_AUDIO_FREQ_32K ((uint32_t)32000) +#define I2S_AUDIO_FREQ_22K ((uint32_t)22050) +#define I2S_AUDIO_FREQ_16K ((uint32_t)16000) +#define I2S_AUDIO_FREQ_11K ((uint32_t)11025) +#define I2S_AUDIO_FREQ_8K ((uint32_t)8000) +#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) \ + ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT)) +/** + * @} + */ + +/** @addtogroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CLKPOL_LOW ((uint16_t)0x0000) +#define I2S_CLKPOL_HIGH ((uint16_t)0x0008) +#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMA_TX ((uint16_t)0x0002) +#define SPI_I2S_DMA_RX ((uint16_t)0x0001) +#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @addtogroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSS_HIGH ((uint16_t)0x0100) +#define SPI_NSS_LOW ((uint16_t)0xFEFF) +#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_TX ((uint8_t)0x00) +#define SPI_CRC_RX ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) +/** + * @} + */ + +/** @addtogroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF) +#define SPI_BIDIRECTION_TX ((uint16_t)0x4000) +#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_INT_TE ((uint8_t)0x71) +#define SPI_I2S_INT_RNE ((uint8_t)0x60) +#define SPI_I2S_INT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR)) +#define SPI_I2S_INT_OVER ((uint8_t)0x56) +#define SPI_INT_MODERR ((uint8_t)0x55) +#define SPI_INT_CRCERR ((uint8_t)0x54) +#define I2S_INT_UNDER ((uint8_t)0x53) +#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR)) +#define IS_SPI_I2S_GET_INT(IT) \ + (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \ + || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001) +#define SPI_I2S_TE_FLAG ((uint16_t)0x0002) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0004) +#define I2S_UNDER_FLAG ((uint16_t)0x0008) +#define SPI_CRCERR_FLAG ((uint16_t)0x0010) +#define SPI_MODERR_FLAG ((uint16_t)0x0020) +#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040) +#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080) +#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) +#define IS_SPI_I2S_GET_FLAG(FLAG) \ + (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \ + || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \ + || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_Module* SPIx); +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct); +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct); +void SPI_InitStruct(SPI_InitType* SPI_InitStruct); +void I2S_InitStruct(I2S_InitType* I2S_InitStruct); +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx); +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); +void SPI_TransmitCrcNext(SPI_Module* SPIx); +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx); +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43x_SPI_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tim.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tim.h new file mode 100644 index 0000000000000000000000000000000000000000..9933153791b1b40aa1537ec9e2cfaa4e67421f18 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tim.h @@ -0,0 +1,1101 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_tim.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_TIM_H__ +#define __N32G43X_TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" +#include "stdbool.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @addtogroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t CntMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t ClkDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter + reaches zero, an update event is generated and counting restarts + from the REPCNT value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0 + Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0 + Tim2,Tim4 valid*/ +} TIM_TimeBaseInitType; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t OcMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t OcPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t OcNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} OCInitType; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + uint16_t Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref Channel */ + + uint16_t IcPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t IcSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t IcFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitType; + +/** + * @brief BKDT structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t OssiState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/ + bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/ + bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/ +} TIM_BDTRInitType; + +/** @addtogroup TIM_Exported_constants + * @{ + */ + +#define IsTimAllModule(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST1: TIM 1 and 8 */ +#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8 */ +#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IsTimList3Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList4Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList5Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList6Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList7Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList8Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList9Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMODE_TIMING ((uint16_t)0x0000) +#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010) +#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020) +#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030) +#define TIM_OCMODE_PWM1 ((uint16_t)0x0060) +#define TIM_OCMODE_PWM2 ((uint16_t)0x0070) +#define IsTimOcMode(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2)) +#define IsTimOc(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \ + || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMODE_SINGLE ((uint16_t)0x0008) +#define TIM_OPMODE_REPET ((uint16_t)0x0000) +#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET)) +/** + * @} + */ + +/** @addtogroup Channel + * @{ + */ + +#define TIM_CH_1 ((uint16_t)0x0000) +#define TIM_CH_2 ((uint16_t)0x0004) +#define TIM_CH_3 ((uint16_t)0x0008) +#define TIM_CH_4 ((uint16_t)0x000C) +#define IsTimCh(CHANNEL) \ + (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4)) +#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2)) +#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3)) +/** + * @} + */ + +/** @addtogroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CLK_DIV1 ((uint16_t)0x0000) +#define TIM_CLK_DIV2 ((uint16_t)0x0100) +#define TIM_CLK_DIV4 ((uint16_t)0x0200) +#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4)) +/** + * @} + */ + +/** @addtogroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CNT_MODE_UP ((uint16_t)0x0000) +#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010) +#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020) +#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040) +#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060) +#define IsTimCntMode(MODE) \ + (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \ + || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002) +#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008) +#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001) +#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004) +#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001) +#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004) +#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Input_enable_disable + * @{ + */ + +#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000) +#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000) +#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Polarity + * @{ + */ + +#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000) +#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000) +#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH)) +/** + * @} + */ + +/** @addtogroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000) +#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000) +#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE)) +/** + * @} + */ + +/** @addtogroup Lock_level + * @{ + */ + +#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000) +#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100) +#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200) +#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300) +#define IsTimLockLevel(LEVEL) \ + (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \ + || ((LEVEL) == TIM_LOCK_LEVEL_3)) +/** + * @} + */ + +/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400) +#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800) +#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100) +#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200) +#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000) +#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002) +#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A) +#define IsTimIcPalaritySingleEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING)) +#define IsTimIcPolarityAnyEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \ + || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_IC_SELECTION_DIRECTTI \ + ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI \ + ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IsTimIcSelection(SELECTION) \ + (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \ + || ((SELECTION) == TIM_IC_SELECTION_TRC)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \ + */ +#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IsTimIcPrescaler(PRESCALER) \ + (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \ + || ((PRESCALER) == TIM_IC_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_interrupt_sources + * @{ + */ + +#define TIM_INT_UPDATE ((uint16_t)0x0001) +#define TIM_INT_CC1 ((uint16_t)0x0002) +#define TIM_INT_CC2 ((uint16_t)0x0004) +#define TIM_INT_CC3 ((uint16_t)0x0008) +#define TIM_INT_CC4 ((uint16_t)0x0010) +#define TIM_INT_COM ((uint16_t)0x0020) +#define TIM_INT_TRIG ((uint16_t)0x0040) +#define TIM_INT_BREAK ((uint16_t)0x0080) +#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IsTimGetInt(IT) \ + (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \ + || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000) +#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001) +#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002) +#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003) +#define TIM_DMABASE_STS ((uint16_t)0x0004) +#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005) +#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006) +#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007) +#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008) +#define TIM_DMABASE_CNT ((uint16_t)0x0009) +#define TIM_DMABASE_PSC ((uint16_t)0x000A) +#define TIM_DMABASE_AR ((uint16_t)0x000B) +#define TIM_DMABASE_REPCNT ((uint16_t)0x000C) +#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D) +#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E) +#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F) +#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010) +#define TIM_DMABASE_BKDT ((uint16_t)0x0011) +#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012) + + +#define IsTimDmaBase(BASE) \ + (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \ + || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \ + || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \ + || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \ + || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \ + || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \ + || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000) +#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100) +#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200) +#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300) +#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400) +#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500) +#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600) +#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700) +#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800) +#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900) +#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00) +#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00) +#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00) +#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00) +#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00) +#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00) +#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000) +#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100) +#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200) +#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300) +#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400) +#define IsTimDmaLength(LENGTH) \ + (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_UPDATE ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_TRIG ((uint16_t)0x4000) +#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000) +#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000) +#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000) +#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000) +#define IsTimExtPreDiv(PRESCALER) \ + (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \ + || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000) +#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010) +#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020) +#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030) +#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040) +#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050) +#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060) +#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070) +#define IsTimTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \ + || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \ + || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF)) +#define IsTimInterTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3)) +/** + * @} + */ + +/** @addtogroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050) +#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060) +#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040) +#define IsTimExtClkSrc(SOURCE) \ + (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED)) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000) +#define IsTimExtTrigPolarity(POLARITY) \ + (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED)) +/** + * @} + */ + +/** @addtogroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001) +#define IsTimPscReloadMode(RELOAD) \ + (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE)) +/** + * @} + */ + +/** @addtogroup TIM_Forced_Action + * @{ + */ + +#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050) +#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040) +#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001) +#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002) +#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003) +#define IsTimEncodeMode(MODE) \ + (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12)) +/** + * @} + */ + +/** @addtogroup TIM_Event_Source + * @{ + */ + +#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001) +#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002) +#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004) +#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008) +#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010) +#define TIM_EVT_SRC_COM ((uint16_t)0x0020) +#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040) +#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080) +#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_Update_Source + * @{ + */ + +#define TIM_UPDATE_SRC_GLOBAL \ + ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008) +#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000) +#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004) +#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000) +#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080) +#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000) +#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000) +#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010) +#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020) +#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030) +#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040) +#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050) +#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060) +#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070) +#define IsTimTrgoSrc(SOURCE) \ + (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \ + || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \ + || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF)) +/** + * @} + */ + +/** @addtogroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004) +#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005) +#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006) +#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007) +#define IsTimSlaveMode(MODE) \ + (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \ + || ((MODE) == TIM_SLAVE_MODE_EXT1)) +/** + * @} + */ + +/** @addtogroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080) +#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000) +#define IsTimMasterSlaveMode(STATE) \ + (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_UPDATE ((uint32_t)0x0001) +#define TIM_FLAG_CC1 ((uint32_t)0x0002) +#define TIM_FLAG_CC2 ((uint32_t)0x0004) +#define TIM_FLAG_CC3 ((uint32_t)0x0008) +#define TIM_FLAG_CC4 ((uint32_t)0x0010) +#define TIM_FLAG_COM ((uint32_t)0x0020) +#define TIM_FLAG_TRIG ((uint32_t)0x0040) +#define TIM_FLAG_BREAK ((uint32_t)0x0080) +#define TIM_FLAG_CC1OF ((uint32_t)0x0200) +#define TIM_FLAG_CC2OF ((uint32_t)0x0400) +#define TIM_FLAG_CC3OF ((uint32_t)0x0800) +#define TIM_FLAG_CC4OF ((uint32_t)0x1000) +#define TIM_FLAG_CC5 ((uint32_t)0x010000) +#define TIM_FLAG_CC6 ((uint32_t)0x020000) + +#define IsTimGetFlag(FLAG) \ + (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \ + || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \ + || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \ + || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \ + || ((FLAG) == TIM_FLAG_CC6)) + +#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Filter + * @{ + */ + +#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +#define TIM_CC1EN ((uint32_t)1<<0) +#define TIM_CC1NEN ((uint32_t)1<<2) +#define TIM_CC2EN ((uint32_t)1<<4) +#define TIM_CC2NEN ((uint32_t)1<<6) +#define TIM_CC3EN ((uint32_t)1<<8) +#define TIM_CC3NEN ((uint32_t)1<<10) +#define TIM_CC4EN ((uint32_t)1<<12) +#define TIM_CC5EN ((uint32_t)1<<16) +#define TIM_CC6EN ((uint32_t)1<<20) + +#define IsAdvancedTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \ + || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \ + || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) ) +#define IsGeneralTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \ + || ((FLAG) == TIM_CC3EN) \ + || ((FLAG) == TIM_CC4EN) ) + +/** @addtogroup TIM_Legacy + * @{ + */ + +#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER +#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS +#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS +#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS +#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS +#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS +#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS +#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS +#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS +#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS +#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS +#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS +#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS +#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS +#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS +#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS +#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS +#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_Module* TIMx); +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct); +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct); +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd); +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource); +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd); +void TIM_ConfigInternalClk(TIM_Module* TIMx); +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, + uint16_t TIM_TIxExternalCLKSource, + uint16_t IcPolarity, + uint16_t ICFilter); +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode); +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity); +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx); +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN); +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode); +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter); +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload); +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1); +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2); +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3); +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4); +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5); +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6); +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCap1(TIM_Module* TIMx); +uint16_t TIM_GetCap2(TIM_Module* TIMx); +uint16_t TIM_GetCap3(TIM_Module* TIMx); +uint16_t TIM_GetCap4(TIM_Module* TIMx); +uint16_t TIM_GetCap5(TIM_Module* TIMx); +uint16_t TIM_GetCap6(TIM_Module* TIMx); +uint16_t TIM_GetCnt(TIM_Module* TIMx); +uint16_t TIM_GetPrescaler(TIM_Module* TIMx); +uint16_t TIM_GetAutoReload(TIM_Module* TIMx); +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN); +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG); +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G43X_TIM_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tsc.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tsc.h new file mode 100644 index 0000000000000000000000000000000000000000..b95669cdbd8ea1660d401dc02796fd23d74d810e --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_tsc.h @@ -0,0 +1,485 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_tsc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_TSC_H__ +#define __N32G43X_TSC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/** + * @brief TSC error code + */ + typedef enum { + TSC_ERROR_OK = 0x00U, /*!< No error */ + TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ + TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ + TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */ + + }TSC_ErrorTypeDef; + /** + * @ + */ + +/** + * @brief TSC clock source + */ +#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/ +#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */ +#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */ +/** + * @ + */ + + +/** + * @defgroup Detect_Period + */ +#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ +#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ +#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ +#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ +#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ +#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ +#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ +#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ +#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ +#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ +#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ +#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ +#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ +/** + * @ + */ + +/** + * @defgroup Detect_Filter + */ +#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ +#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ +#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ +#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ +/** + * @ + */ + +/** + * @defgroup HW_Detect_Mode + */ +#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ +#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */ +/** + * @ + */ + +/** + * @defgroup Detect_Type + */ +#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk) +#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos) + +#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ +#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */ +#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */ +#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */ +/** + * @ + */ + +/** + * @defgroup TSC_Interrupt + */ +#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ +#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ +/** + * @ + */ + +/** + * @defgroup TSC_Out + */ +#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ +#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */ +#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ +/** + * @ + */ + +/** + * @defgroup TSC_Flag + */ +#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */ + +#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */ +#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */ +#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ +/** + * @ + */ + +/** + * @defgroup TSC_SW_Detect + */ +#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ +#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */ +/** + * @ + */ + +/** + * @defgroup TSC_PadOption + */ +#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ +#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */ +/** + * @ + */ + +/** + * @defgroup TSC_PadSpeed + */ +#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ +#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +/** + * @ + */ + +/** + * @defgroup TSC_Constant + */ +#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk) +#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ +#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ +#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ +#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */ +/** + * @ + */ + +/** + * @defgroup TSC_DetectMode + */ +#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ +#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ +/** + * @ + */ + +/* TSC Exported macros -----------------------------------------------------------*/ +/** @defgroup TSC_Exported_Macros + * @{ + */ + +/** @brief Enable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Disable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Config TSC detect period for HW detect mode + * @param __PERIOD__ specifies the TSC detect period during HW detect mode + * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK + * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK + * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK + * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK + * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK + * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK + * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK + * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK + * @retval None + */ +#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__) + +/** @brief Config TSC detect filter for HW detect mode + * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode + * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse + * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse + * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse + * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse + * @retval None + */ +#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__) + +/** @brief Config TSC detect type for HW detect mode,less great or both + * @param __TYPE__ specifies the detect type of a sample during HW detect mode + * @arg TSC_DET_TYPE_NONE: Detect disable + * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time + * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time + * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) + and also be less than (basee+delta) during a sample time + * @retval None + */ +#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ + (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \ + __TYPE__) + +/** @brief Enable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Disable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Config the TSC output + * @param __OUT__ specifies where the TSC output should go + * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin + * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR + * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR + * @retval None + */ +#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ + (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\ + __OUT__) + +/** @brief Config the TSC channel + * @param __CHN__ specifies the pin of channels used for detect + * This parameter:bit[0:23] used,bit[24:31] must be 0 + * bitx: TSC channel x + * @retval None + */ +#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) + +/** @brief Enable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Disable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Config the detect channel number during SW detect mode + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval None + */ +#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__) + +/** @brief Config the pad charge type + * @param __OPT__ specifies which resistor is used for charge + * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used + * @arg TSC_PAD_EXTERNAL_RES: External resistor is used + * @retval None + */ +#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__) + +/** @brief Config TSC speed + * @param __SPEED__ specifies the TSC speed range + * @arg TSC_PAD_SPEED_0: Low speed + * @arg TSC_PAD_SPEED_1: Middle speed + * @arg TSC_PAD_SPEED_2: Middle speed + * @arg TSC_PAD_SPEED_3: High speed + * @retval None + */ +#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__) + + +/** @brief Check if the HW detect mode is enable + * @param None + * @retval Current state of HW detect mode + */ +#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) + +/** @brief Check the detect type during HW detect mode + * @param __FLAG__ specifies the flag of detect type + * @arg TSC_FLAG_LESS_DET: Flag of less detect type + * @arg TSC_FLAG_GREAT_DET: Flag of great detect type + * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type + * @retval Current state of flag + */ +#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) + +/** @brief Get the number of channel which is detected now + * @param None + * @retval Current channel number + */ +#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos ) + +/** @brief Get the count value of pulse + * @param None + * @retval Pulse count of current channel + */ +#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos ) + +/** @brief Get the base value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval base value of the channel + */ +#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos) + +/** @brief Get the delta value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval delta value of the channel + */ +#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos ) + +/** @brief Get the internal resist value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval resist value of the channel + */ +#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TSC_Private_Macros + * @{ + */ +#define IS_TSC_DET_PERIOD(_PERIOD_) \ + (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ + ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ + ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ + ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ + ||((_PERIOD_)==TSC_DET_PERIOD_104) ) + +#define IS_TSC_FILTER(_FILTER_) \ + ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ + ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) + +#define IS_TSC_DET_MODE(_MODE_) \ + ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) + +#define IS_TSC_DET_TYPE(_TYPE_) \ + ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ + ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) + +#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) + +#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) + +#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk))) + +#define IS_TSC_CHN_NUMBER(_NUM_) ( ((_NUM_)==1) \ + ||(((_NUM_)>=4) && ((_NUM_)<=17)) \ + ||(((_NUM_)>=19) && ((_NUM_)<=23)) ) + +#define IS_TSC_PAD_OPTION(_OPT_) (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES)) + +#define IS_TSC_PAD_SPEED(_SPEED_) \ + ( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1) \ + ||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3) ) + +#define IS_TSC_RESISTOR_VALUE(_RES_) \ + ( ((_RES_)==TSC_RESRx_CHN_RESIST_0)||((_RES_)==TSC_RESRx_CHN_RESIST_1) \ + ||((_RES_)==TSC_RESRx_CHN_RESIST_2)||((_RES_)==TSC_RESRx_CHN_RESIST_3) \ + ||((_RES_)==TSC_RESRx_CHN_RESIST_4)||((_RES_)==TSC_RESRx_CHN_RESIST_5) \ + ||((_RES_)==TSC_RESRx_CHN_RESIST_6)||((_RES_)==TSC_RESRx_CHN_RESIST_7) ) + +#define IS_TSC_THRESHOLD_BASE(_BASE_) ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE) + + +#define IS_TSC_THRESHOLD_DELTA(_DELTA_) ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA) + +/** +* @brief TSC Init structure definition +*/ + +typedef struct +{ + uint32_t Mode; /*!< Configures the TSC work mode. + This parameter can be one value of @ref TSC_DetectMode */ + uint32_t Period; /*!< Configures the TSC check period for a sample. + This parameter can be one value of @ref Detect_Period */ + uint32_t Filter; /*!< Configures the TSC filter. + This parameter can be one value of @ref Detect_Filter */ + uint32_t Type; /*!< Configures the TSC check type + This parameter can be one value of @ref Detect_Type */ + uint32_t Chn; /*!< Selects the TSC chnnel used + This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_Msk */ + uint32_t Out; /*!< Configures the TSC_OUT etr + This parameter can be one value of @ref TSC_Out */ + uint32_t Int; /*!< Configures the TSC interrupt + This parameter can be one value of @ref TSC_Interrupt */ + uint32_t PadOpt; /*!< Configures the TSC charge resistor + This parameter can be one value of @ref TSC_PadOption */ + uint32_t Speed; /*!< Configures the TSC detect speed + This parameter can be one value of @ref TSC_PadSpeed */ +}TSC_InitType; + +typedef struct +{ + uint16_t TSC_Base; /*!< base value */ + uint8_t TSC_Delta; /*!< offset value */ + uint8_t TSC_Resistor; /*!< resistance value configuration*/ +} TSC_ChnCfg; + +TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam); +TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource); +TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ); +TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta); +TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X_TSC_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_usart.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..dc37e783cf04ec8beeac2adb6067fddfa0dd60ae --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_usart.h @@ -0,0 +1,397 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_usart.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43x_USART_H__ +#define __N32G43x_USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @addtogroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitType; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref Clock */ + + uint16_t Polarity; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitType; + +/** + * @} + */ + +/** @addtogroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) +/** @addtogroup USART_Word_Length + * @{ + */ + +#define USART_WL_8B ((uint16_t)0x0000) +#define USART_WL_9B ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B)) +/** + * @} + */ + +/** @addtogroup USART_Stop_Bits + * @{ + */ + +#define USART_STPB_1 ((uint16_t)0x0000) +#define USART_STPB_0_5 ((uint16_t)0x1000) +#define USART_STPB_2 ((uint16_t)0x2000) +#define USART_STPB_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) \ + (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \ + || ((STOPBITS) == USART_STPB_1_5)) +/** + * @} + */ + +/** @addtogroup Parity + * @{ + */ + +#define USART_PE_NO ((uint16_t)0x0000) +#define USART_PE_EVEN ((uint16_t)0x0400) +#define USART_PE_ODD ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define USART_MODE_RX ((uint16_t)0x0004) +#define USART_MODE_TX ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @addtogroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HFCTRL_NONE ((uint16_t)0x0000) +#define USART_HFCTRL_RTS ((uint16_t)0x0100) +#define USART_HFCTRL_CTS ((uint16_t)0x0200) +#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \ + || ((CONTROL) == USART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup Clock + * @{ + */ +#define USART_CLK_DISABLE ((uint16_t)0x0000) +#define USART_CLK_ENABLE ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Clock_Polarity + * @{ + */ + +#define USART_CLKPOL_LOW ((uint16_t)0x0000) +#define USART_CLKPOL_HIGH ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH)) + +/** + * @} + */ + +/** @addtogroup USART_Clock_Phase + * @{ + */ + +#define USART_CLKPHA_1EDGE ((uint16_t)0x0000) +#define USART_CLKPHA_2EDGE ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE)) + +/** + * @} + */ + +/** @addtogroup USART_Last_Bit + * @{ + */ + +#define USART_CLKLB_DISABLE ((uint16_t)0x0000) +#define USART_CLKLB_ENABLE ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Interrupt_definition + * @{ + */ + +#define USART_INT_PEF ((uint16_t)0x0028) +#define USART_INT_TXDE ((uint16_t)0x0727) +#define USART_INT_TXC ((uint16_t)0x0626) +#define USART_INT_RXDNE ((uint16_t)0x0525) +#define USART_INT_IDLEF ((uint16_t)0x0424) +#define USART_INT_LINBD ((uint16_t)0x0846) +#define USART_INT_CTSF ((uint16_t)0x096A) +#define USART_INT_ERRF ((uint16_t)0x0060) +#define USART_INT_OREF ((uint16_t)0x0360) +#define USART_INT_NEF ((uint16_t)0x0260) +#define USART_INT_FEF ((uint16_t)0x0160) +#define IS_USART_CFG_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \ + || ((IT) == USART_INT_ERRF)) +#define IS_USART_GET_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \ + || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF)) +#define IS_USART_CLR_INT(IT) \ + (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF)) +/** + * @} + */ + +/** @addtogroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAREQ_TX ((uint16_t)0x0080) +#define USART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup USART_WakeUp_methods + * @{ + */ + +#define USART_WUM_IDLELINE ((uint16_t)0x0000) +#define USART_WUM_ADDRMASK ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK)) +/** + * @} + */ + +/** @addtogroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBDL_10B ((uint16_t)0x0000) +#define USART_LINBDL_11B ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B)) +/** + * @} + */ + +/** @addtogroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004) +#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTSF ((uint16_t)0x0200) +#define USART_FLAG_LINBD ((uint16_t)0x0100) +#define USART_FLAG_TXDE ((uint16_t)0x0080) +#define USART_FLAG_TXC ((uint16_t)0x0040) +#define USART_FLAG_RXDNE ((uint16_t)0x0020) +#define USART_FLAG_IDLEF ((uint16_t)0x0010) +#define USART_FLAG_OREF ((uint16_t)0x0008) +#define USART_FLAG_NEF ((uint16_t)0x0004) +#define USART_FLAG_FEF ((uint16_t)0x0002) +#define USART_FLAG_PEF ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) \ + (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \ + || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \ + || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \ + || ((FLAG) == USART_FLAG_FEF)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \ + ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTSF)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_Module* USARTx); +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct); +void USART_StructInit(USART_InitType* USART_InitStruct); +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct); +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd); +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd); +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr); +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode); +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd); +void USART_SendData(USART_Module* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_Module* USARTx); +void USART_SendBreak(USART_Module* USARTx); +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler); +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd); +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd); +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode); +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd); +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG); +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG); +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT); +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43x_USART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..a9e14b74f9c19dd9c20fb26769483d27c38f9d89 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_wwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G43X_WWDG_H__ +#define __N32G43X_WWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g43x.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @addtogroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Constants + * @{ + */ + +/** @addtogroup WWDG_Prescaler + * @{ + */ + +#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000) +#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080) +#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100) +#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \ + || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8)) +#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler); +void WWDG_SetWValue(uint8_t WindowValue); +void WWDG_EnableInt(void); +void WWDG_SetCnt(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetEWINTF(void); +void WWDG_ClrEWINTF(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G43X__WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/misc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/misc.c new file mode 100644 index 0000000000000000000000000000000000000000..68291cae460d3096a86f24b67caa9ab92f4baf4b --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/misc.c @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "misc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @addtogroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @addtogroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority + * 0 bits for subpriority + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains + * the configuration information for the specified NVIC peripheral. + */ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset Vector Table base offset field. This value must be a multiple + * of 0x200. + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE. + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_adc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..a79a42dbf32bc6fba8564c877b7e9ce4d05d4ed4 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_adc.c @@ -0,0 +1,1417 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_adc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_adc.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @addtogroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Defines + * @{ + */ + +/* ADC DISC_NUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISC_EN mask */ +#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800) +#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC INJ_AUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC INJ_DISC_EN mask */ +#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000) +#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC AWDG_CH mask */ +#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF) + +/* CTRL1 register Mask */ +#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) + +/* ADC AD_ON mask */ +#define CTRL2_AD_ON_SET ((uint32_t)0x00000001) +#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTRL2_DMA_SET ((uint32_t)0x00000100) +#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF) + +/* ADC RST_CALI mask */ +#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTRL2_CAL_SET ((uint32_t)0x00000004) + +/* ADC SOFT_START mask */ +#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000) + +/* ADC EXT_TRIG mask */ +#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000) +#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000) +#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC INJ_EXT_SEL mask */ +#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC INJ_EXT_TRIG mask */ +#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000) +#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC INJ_SWSTART mask */ +#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000) +#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000) +#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* CTRL2 register Mask */ +#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR4_SEQ_SET ((uint32_t)0x0000001F) +#define SQR3_SEQ_SET ((uint32_t)0x0000001F) +#define SQR2_SEQ_SET ((uint32_t)0x0000001F) +#define SQR1_SEQ_SET ((uint32_t)0x0000001F) + +/* RSEQ1 register Mask */ +#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSEQ_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC INJ_LEN mask */ +#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000) +#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SAMPTx mask */ +#define SAMPT1_SMP_SET ((uint32_t)0x00000007) +#define SAMPT2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDATx registers offset */ +#define JDAT_OFFSET ((uint8_t)0x28) + +/* ADC1 DAT register base address */ +#define DAT_ADDR ((uint32_t)0x4001244C) + +/* ADC STS register mask */ +#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F) +/** + * @} + */ + +/** @addtogroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + */ +void ADC_DeInit(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + + if (ADCx == ADC) + { + /* Enable ADC1 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE); + /* Release ADC1 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE); + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param ADC_InitStruct pointer to an ADC_InitType structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn)); + assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect)); + assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign)); + assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber)); + + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tmpreg1 = ADCx->CTRL1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CTRL1_CLR_MASK; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to WorkMode value */ + /* Set SCAN bit according to MultiChEn value */ + tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8)); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tmpreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tmpreg1 = ADCx->CTRL2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CTRL2_CLR_MASK; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL bits according to ExtTrigSelect value */ + /* Set CONT bit according to ContinueConvEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1)); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tmpreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tmpreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tmpreg1 &= RSEQ1_CLR_MASK; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ChsNumber value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized. + */ +void ADC_InitStruct(ADC_InitType* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* initialize the MultiChEn member */ + ADC_InitStruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_InitStruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1; + /* Initialize the DatAlign member */ + ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_InitStruct->ChsNumber = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd) +{ + uint32_t i=0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AD_ON bit to wake up the ADC from power down mode */ + ADCx->CTRL2 |= CTRL2_AD_ON_SET; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CTRL2 &= CTRL2_AD_ON_RESET; + } + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcDmaModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CTRL2 |= CTRL2_DMA_SET; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CTRL2 &= CTRL2_DMA_RESET; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @param Cmd new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (Cmd != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CTRL1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CTRL1 &= (~(uint32_t)itmask); + } +} + + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + */ +void ADC_StartCalibration(ADC_Module* ADCx) +{ + uint32_t i =0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Enable the selected ADC calibration process */ + if(ADCx->CALFACT==0) + ADCx->CTRL2 |= CTRL2_CAL_SET; + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + if(ADCx->CALFACT!=0) + bitstatus = RESET; + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of SOFT_START bit */ + if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET) + { + /* SOFT_START bit is set */ + bitstatus = SET; + } + else + { + /* SOFT_START bit is reset */ + bitstatus = RESET; + } + /* Return the SOFT_START bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Number specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + */ +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcSeqDiscNumberValid(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CTRL1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CTRL1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 |= CTRL1_DISC_EN_SET; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 &= CTRL1_DISC_EN_RESET; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcReqRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The Data conversion value. + */ +uint16_t ADC_GetDat(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DAT; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpregister = ADCx->CTRL2; + /* Clear the old external event selection for injected group */ + tmpregister &= CTRL2_INJ_EXT_SEL_RESET; + /* Set the external event selection for injected group */ + tmpregister |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of INJ_SWSTART bit */ + if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET) + { + /* INJ_SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* INJ_SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the INJ_SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcInjRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Get INJ_LEN value: Number = INJ_LEN+1 */ + tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Length The sequencer length. + * This parameter must be a number between 1 to 4. + */ +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjLenValid(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Clear the old injected sequnence lenght INJ_LEN bits */ + tmpreg1 &= JSEQ_INJ_LEN_RESET; + /* Set the injected sequnence lenght INJ_LEN bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_InjectedChannel the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @param Offset the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + */ +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + assert_param(IsAdcOffsetValid(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t*)tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_InjectedChannel the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @return The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDAT_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_AnalogWatchdog the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel + * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog + */ +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpregister &= CTRL1_AWDG_MODE_RESET; + /* Set the analog watchdog enable mode */ + tmpregister |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param HighThreshold the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcValid(HighThreshold)); + assert_param(IsAdcValid(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->WDGHIGH = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->WDGLOW = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear the Analog watchdog channel select bits */ + tmpregister &= CTRL1_AWDG_CH_RESET; + /* Set the Analog watchdog channel */ + tmpregister |= ADC_Channel; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param Cmd new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableTempSensorVrefint(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 |= CTRL2_TSVREFE_SET; + _EnVref1p2() + _EnVref2p0() + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 &= CTRL2_TSVREFE_RESET; + _DisVref1p2() + _DisVref2p0() + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + * @return The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + */ +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcClrFlag(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @return The new state of ADC_IT (SET or RESET). + */ +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT); + /* Check the status of the specified ADC interrupt */ + if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + */ +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStructEx. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx) +{ + uint32_t tmpregister = 0; + /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/ + if (ADC_InitStructEx->Samp303Style) + ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK; + else + ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK); + + /*intial ADC_CTRL3 once initiall config*/ + tmpregister = ADCx->CTRL3; + if (ADC_InitStructEx->DeepPowerModEn) + tmpregister |= ADC_CTRL3_DPWMOD_MSK; + else + tmpregister &= (~ADC_CTRL3_DPWMOD_MSK); + + if (ADC_InitStructEx->JendcIntEn) + tmpregister |= ADC_CTRL3_JENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK); + + if (ADC_InitStructEx->EndcIntEn) + tmpregister |= ADC_CTRL3_ENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK); + + if (ADC_InitStructEx->CalAtuoLoadEn) + tmpregister |= ADC_CTRL3_CALALD_MSK; + else + tmpregister &= (~ADC_CTRL3_CALALD_MSK); + + if (ADC_InitStructEx->DifModCal) + tmpregister |= ADC_CTRL3_CALDIF_MSK; + else + tmpregister &= (~ADC_CTRL3_CALDIF_MSK); + + tmpregister &= (~ADC_CTRL3_RES_MSK); + tmpregister |= ADC_InitStructEx->ResBit; + + tmpregister &= (~ADC_CTRL3_CKMOD_MSK); + if(ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL) + tmpregister |= ADC_CTRL3_CKMOD_MSK; + + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG_NEW specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_RDY ADC ready flag + * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag + * @return The new state of ADC_FLAG_NEW (SET or RESET). + */ +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG_NEW)); + /* Check the status of the specified ADC flag */ + if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET) + { + /* ADC_FLAG_NEW is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG_NEW is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG_NEW status */ + return bitstatus; +} +/** + * @brief Set Adc calibration bypass or enable. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param en enable bypass calibration. + * This parameter can be one of the following values: + * @arg true bypass calibration + * @arg false not bypass calibration + */ +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + if (en) + tmpregister |= ADC_CTRL3_BPCAL_MSK; + else + tmpregister &= (~ADC_CTRL3_BPCAL_MSK); + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Set Adc trans bits width. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ResultBitNum specifies num with adc trans width. + * This parameter can be one of the following values: + * @arg ADC_RST_BIT_12 12 bit trans + * @arg ADC_RST_BIT_10 10 bit trans + * @arg ADC_RST_BIT_8 8 bit trans + * @arg ADC_RESULT_BIT_6 6 bit trans + */ +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + tmpregister &= 0xFFFFFFFC; + tmpregister |= ResultBitNum; + ADCx->CTRL3 = tmpregister; + return; +} + + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + + * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + */ +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler) +{ + if(ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){ + RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler); + }else{ + RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_can.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_can.c new file mode 100644 index 0000000000000000000000000000000000000000..2aef4545185acb178bcf95a33a969acbbbafc3d5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_can.c @@ -0,0 +1,1372 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_can.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_can.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @addtogroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */ +#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTS register */ +#define CAN_FLAGS_TSTS ((uint32_t)0x08000000) +/* Flags in RFF1 register */ +#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000) +/* Flags in RFF0 register */ +#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000) +/* Flags in MSTS register */ +#define CAN_FLAGS_MSTS ((uint32_t)0x01000000) +/* Flags in ESTS register */ +#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) +/** + * @} + */ + +/** @addtogroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_FunctionPrototypes + * @{ + */ + +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit); + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx. + */ +void CAN_DeInit(CAN_Module* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Enable CAN reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE); +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitParam. + * @param CAN to select the CAN peripheral. + * @param CAN_InitParam pointer to a CAN_InitType structure that + * contains the configuration information for the + * CAN peripheral. + * @return Constant indicates initialization succeed which will be + * CAN_InitSTS_Failed or CAN_InitSTS_Success. + */ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam) +{ + uint8_t InitStatus = CAN_InitSTS_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP)); + assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode)); + assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW)); + assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1)); + assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2)); + assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler)); + + /* Exit from sleep mode */ + CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ); + + /* Request initialisation */ + CANx->MCTRL |= CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitParam->TTCM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TTCM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitParam->ABOM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_ABOM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitParam->AWKUM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_AWKUM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitParam->NART == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_NART; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART; + } + + /* Set the receive DATFIFO locked mode */ + if (CAN_InitParam->RFLM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_RFLM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM; + } + + /* Set the transmit DATFIFO priority */ + if (CAN_InitParam->TXFP == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TXFP; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP; + } + + /* Set the bit timing register */ + CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24) + | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20) + | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1); + + /* Request leave initialisation */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + InitStatus = CAN_InitSTS_Success; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitFilterStruct. + * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType + * structure that contains the configuration + * information. + */ +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num)); + assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num; + + /* Initialisation mode for the filter */ + CAN->FMC |= FMC_FINITM; + + /* Filter Deactivation */ + CAN->FA1 &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale) + { + /* 16-bit scale for the filter */ + CAN->FS1 &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId); + } + + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale) + { + /* 32-bit scale for the filter */ + CAN->FS1 |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId); + } + + /* Filter Mode */ + if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode) + { + /*Id/Mask mode for the filter*/ + CAN->FM1 &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */ + { + /*Identifier list mode for the filter*/ + CAN->FM1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter DATFIFO assignment */ + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0) + { + /* DATFIFO 0 assignation for the filter */ + CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1) + { + /* DATFIFO 1 assignation for the filter */ + CAN->FFA1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_InitFilterStruct->Filter_Act == ENABLE) + { + CAN->FA1 |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMC &= ~FMC_FINITM; +} +/** + * @brief Fills each CAN_InitParam member with its default value. + * @param CAN_InitParam pointer to a CAN_InitType structure which + * will be initialized. + */ +void CAN_InitStruct(CAN_InitType* CAN_InitParam) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitParam->TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitParam->ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitParam->AWKUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitParam->NART = DISABLE; + + /* Initialize the receive DATFIFO locked mode */ + CAN_InitParam->RFLM = DISABLE; + + /* Initialize the transmit DATFIFO priority */ + CAN_InitParam->TXFP = DISABLE; + + /* Initialize the OperatingMode member */ + CAN_InitParam->OperatingMode = CAN_Normal_Mode; + + /* Initialize the RSJW member */ + CAN_InitParam->RSJW = CAN_RSJW_1tq; + + /* Initialize the TBS1 member */ + CAN_InitParam->TBS1 = CAN_TBS1_4tq; + + /* Initialize the TBS2 member */ + CAN_InitParam->TBS2 = CAN_TBS2_3tq; + + /* Initialize the BaudRatePrescaler member */ + CAN_InitParam->BaudRatePrescaler = 1; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CAN to select the CAN peripheral. + * @param Cmd new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + */ +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCTRL |= MCTRL_DBGF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCTRL &= ~MCTRL_DBGF; + } +} + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CAN to select the CAN peripheral. + * @param Cmd Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + */ +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCTRL |= CAN_MCTRL_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CAN to select the CAN peripheral. + * @param TxMessage pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @return The number of the mailbox that is used for transmission + * or CAN_TxSTS_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ID(TxMessage->IDE)); + assert_param(IS_CAN_RTRQ(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxSTS_NoMailBox; + } + + if (transmit_mailbox != CAN_TxSTS_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Standard_Id) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TMDL = + (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) + | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TMDH = + (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) + | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx to select the CAN peripheral. + * @param TransmitMailbox the number of the mailbox that is used for + * transmission. + * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed + * in an other case. + */ +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2); + break; + default: + state = CAN_TxSTS_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): + state = CAN_TxSTS_Pending; + break; + /* transmit failed */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Failed; + break; + /* transmit succeeded */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Ok; + break; + default: + state = CAN_TxSTS_Failed; + break; + } + return (uint8_t)state; +} + +/** + * @brief Cancels a transmit request. + * @param CAN to select the CAN peripheral. + * @param Mailbox Mailbox number. + */ +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTS = CAN_TSTS_ABRQM0; + break; + case (CAN_TXMAILBOX_1): + CANx->TSTS = CAN_TSTS_ABRQM1; + break; + case (CAN_TXMAILBOX_2): + CANx->TSTS = CAN_TSTS_ABRQM2; + break; + default: + break; + } +} + +/** + * @brief Receives a message. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + */ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI; + if (RxMessage->IDE == CAN_Standard_Id) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24); + /* Release the DATFIFO */ + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Releases the specified DATFIFO. + * @param CAN to select the CAN peripheral. + * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1. + */ +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @return NbMessage : which is the number of pending message. + */ +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum) +{ + uint8_t message_pending = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + if (FIFONum == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03); + } + else if (FIFONum == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Select the CAN Operation mode. + * @param CAN to select the CAN peripheral. + * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one + * of @ref CAN_operating_mode enumeration. + * @return status of the requested mode which can be + * - CAN_ModeSTS_Failed CAN failed entering the specific mode + * - CAN_ModeSTS_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeSTS_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INIAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_Operating_InitMode) + { + /* Request initialisation */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_NormalMode) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != 0) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_SleepMode) + { + /* Request Sleep mode */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else + { + status = CAN_ModeSTS_Failed; + } + + return (uint8_t)status; +} + +/** + * @brief Enters the low power mode. + * @param CAN to select the CAN peripheral. + * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an + * other case. + */ +uint8_t CAN_EnterSleep(CAN_Module* CANx) +{ + uint8_t sleepstatus = CAN_SLEEP_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Sleep mode status */ + if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_SLEEP_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CAN to select the CAN peripheral. + * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_Module* CANx) +{ + uint32_t wait_slak = SLPAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WKU_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ; + + /* Sleep mode status */ + while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WKU_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CAN to select the CAN peripheral. + * @return CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrCode(CAN_Module* CANx) +{ + uint8_t errorcode = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx to to select the CAN peripheral. + * @return CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CAN to to select the CAN peripheral. + * @return LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_INT_TME, + * - CAN_INT_FMP0, + * - CAN_INT_FF0, + * - CAN_INT_FOV0, + * - CAN_INT_FMP1, + * - CAN_INT_FF1, + * - CAN_INT_FOV1, + * - CAN_INT_EWG, + * - CAN_INT_EPV, + * - CAN_INT_LEC, + * - CAN_INT_ERR, + * - CAN_INT_WKU or + * - CAN_INT_SLK. + * @param Cmd new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->INTE |= CAN_INT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->INTE &= ~CAN_INT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWGFL + * - CAN_FLAG_EPVFL + * - CAN_FLAG_BOFFL + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFMP1 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFMP0 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @return The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + */ +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */ + { + /* Clear the selected CAN flags */ + CANx->ESTS = (uint32_t)RESET; + } + else /* MSTS or TSTS or RFF0 or RFF1 */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSTS = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSTS = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_INT_TME + * - CAN_INT_FMP0 + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FMP1 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + * @return The current state of CAN_INT (SET or RESET). + */ +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT) +{ + INTStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + + /* check the enable interrupt bit */ + if ((CANx->INTE & CAN_INT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_INT) + { + case CAN_INT_TME: + /* Check CAN_TSTS_RQCPx bits */ + itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2); + break; + case CAN_INT_FMP0: + /* Check CAN_RFF0_FFMP0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0); + break; + case CAN_INT_FF0: + /* Check CAN_RFF0_FFULL0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0); + break; + case CAN_INT_FOV0: + /* Check CAN_RFF0_FFOVR0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0); + break; + case CAN_INT_FMP1: + /* Check CAN_RFF1_FFMP1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1); + break; + case CAN_INT_FF1: + /* Check CAN_RFF1_FFULL1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1); + break; + case CAN_INT_FOV1: + /* Check CAN_RFF1_FFOVR1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1); + break; + case CAN_INT_WKU: + /* Check CAN_MSTS_WKUINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT); + break; + case CAN_INT_SLK: + /* Check CAN_MSTS_SLAKINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT); + break; + case CAN_INT_EWG: + /* Check CAN_ESTS_EWGFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL); + break; + case CAN_INT_EPV: + /* Check CAN_ESTS_EPVFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL); + break; + case CAN_INT_BOF: + /* Check CAN_ESTS_BOFFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL); + break; + case CAN_INT_LEC: + /* Check CAN_ESTS_LEC bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC); + break; + case CAN_INT_ERR: + /* Check CAN_MSTS_ERRINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_INT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the interrupt pending bit to clear. + * - CAN_INT_TME + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + */ +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_INT(CAN_INT)); + + switch (CAN_INT) + { + case CAN_INT_TME: + /* Clear CAN_TSTS_RQCPx (rc_w1)*/ + CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2; + break; + case CAN_INT_FF0: + /* Clear CAN_RFF0_FFULL0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFULL0; + break; + case CAN_INT_FOV0: + /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFOVR0; + break; + case CAN_INT_FF1: + /* Clear CAN_RFF1_FFULL1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFULL1; + break; + case CAN_INT_FOV1: + /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFOVR1; + break; + case CAN_INT_WKU: + /* Clear CAN_MSTS_WKUINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_WKUINT; + break; + case CAN_INT_SLK: + /* Clear CAN_MSTS_SLAKINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_SLAKINT; + break; + case CAN_INT_EWG: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_EPV: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_BOF: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_LEC: + /* Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + break; + case CAN_INT_ERR: + /*Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default: + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg specifies the CAN interrupt register to check. + * @param Int_Bit specifies the interrupt source bit to check. + * @return The new state of the CAN Interrupt (SET or RESET). + */ +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit) +{ + INTStatus pendingbitstatus = RESET; + + if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) + { + /* CAN_INT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_INT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_comp.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_comp.c new file mode 100644 index 0000000000000000000000000000000000000000..f755cbb1790f5e666f0657621eb8beff3fc13428 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_comp.c @@ -0,0 +1,385 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_comp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_comp.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @brief COMP driver modules + * @{ + */ + +/** @addtogroup COMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the COMP peripheral registers to their default reset values. + */ +void COMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE); +} +void COMP_StructInit(COMP_InitType* COMP_InitStruct) +{ + COMP_InitStruct->LowPoweMode =false; // only COMP1 have this bit + COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit + + COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */ + + COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK + + COMP_InitStruct->PolRev = false; // out polarity reverse + + COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC; + COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2 + COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s + COMP_InitStruct->FilterEn=false; + COMP_InitStruct->ClkPsc=0; + COMP_InitStruct->SampWindow=0; + COMP_InitStruct->Thresh=0; + COMP_InitStruct->En = false; +} +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct) +{ + COMP_SingleType* pCS; + __IO uint32_t tmp; + if(COMPx == COMP1) + pCS = &COMP->Cmp1; + else + pCS = &COMP->Cmp2; + + // filter + tmp = pCS->FILC; + SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK); + SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK); + SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK); + pCS->FILC = tmp; + // filter psc + pCS->FILP = COMP_InitStruct->ClkPsc; + + // ctrl + tmp = pCS->CTRL; + if (COMPx == COMP1) + { + if (COMP_InitStruct->InpDacConnect) + SetBit(tmp, COMP1_CTRL_INPDAC_MASK); + else + ClrBit(tmp, COMP1_CTRL_INPDAC_MASK); + if (COMP_InitStruct->LowPoweMode) + SetBit(tmp, COMP1_CTRL_PWRMODE_MASK); + else + ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK); + } + SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK); + SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK); + if (COMP_InitStruct->PolRev) + SetBit(tmp, COMP_POL_MASK); + else + ClrBit(tmp, COMP_POL_MASK); + SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK); + if (COMP_InitStruct->En) + SetBit(tmp, COMP_CTRL_EN_MASK); + else + ClrBit(tmp, COMP_CTRL_EN_MASK); + pCS->CTRL = tmp; +} +void COMP_Enable(COMPX COMPx, FunctionalState en) +{ + if(COMPx == COMP1) + { + if (en) + SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + } + else + { + if (en) + SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + } +} + +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; + +} +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} + +// return see @COMP_INTSTS_CMPIS +uint32_t COMP_GetIntSts(void) +{ + return COMP->INTSTS; +} +// parma range see @COMP_VREFSCL +// Vv2Trim,Vv1Trim max 63 +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En) +{ + __IO uint32_t tmp = 0; + + SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK); + SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK); + SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK); + SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK); + + COMP->VREFSCL = tmp; +} +// SET when comp out 1 +// RESET when comp out 0 +FlagStatus COMP_GetOutStatus(COMPX COMPx) +{ + if(COMPx == COMP1) + return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; + else + return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; +} +// get one comp interrupt flags +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx) +{ + return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET; +} + +// Lock see @COMP_LOCK +void COMP_SetLock(uint32_t Lock) +{ + COMP->LOCK = Lock; +} +// IntEn see @COMP_INTEN_CMPIEN +void COMP_SetIntEn(uint32_t IntEn) +{ + COMP->INTEN = IntEn; +} +// set comp2 xor output with comp1 +void COMP_CMP2XorOut(bool En) +{ + COMP->CMP2OSEL = (En==true)?0x1L:0x0L; +} +// set stop or lowpower mode that sel 32k clk +void COMP_StopOrLowpower32KClkSel(bool En) +{ + COMP->LPCKSEL = (En==true)?0x1L:0x0L; +} +// set comp1 and comp2 component window compare mode +void COMP_WindowModeEn(bool En) +{ + COMP->WINMODE = (En==true)?0x1L:0x0L; +} + + +/** + * @brief Set the COMP filter clock Prescaler value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1. + * @return void + */ +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILP=FilPreVal; + else + COMP->Cmp2.FILP=FilPreVal; +} + +/** + * @brief Set the COMP filter control value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilEn 1 for enable ,0 or disable + * @param TheresNum num under this value is noise + * @param SampPW total sample number in a window + * @return void + */ +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); + else + COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); +} + +/** + * @brief Set the COMP Hyst value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param HYST specifies the HYST level. + * This parameter can be one of the following values: +* @arg COMP_CTRL_HYST_NO Hyst disable +* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV +* @arg COMP_CTRL_HYST_MID Hyst level 15mV +* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV + * @return void + */ +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + + tmp&=~COMP_CTRL_HYST_HIGH; + tmp|=HYST; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @brief Set the COMP Blanking source . + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param BLK specifies the blanking source . + * This parameter can be one of the following values: +* @arg COMP_CTRL_BLKING_NO Blanking disable +* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5 +* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5 + * @return void + */ +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + tmp&=~(7<<16); + tmp|=BLK; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_crc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..41f1e7d88a7b36011615a966e250bebe6f92fe1f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_crc.c @@ -0,0 +1,227 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_crc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_crc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @addtogroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DAT). + */ +void CRC32_ResetCrc(void) +{ + /* Reset CRC generator */ + CRC->CRC32CTRL = CRC32_CTRL_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data data word(32-bit) to compute its CRC + * @return 32-bit CRC + */ +uint32_t CRC32_CalcCrc(uint32_t Data) +{ + CRC->CRC32DAT = Data; + + return (CRC->CRC32DAT); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed + * @return 32-bit CRC + */ +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < BufferLength; index++) + { + CRC->CRC32DAT = pBuffer[index]; + } + return (CRC->CRC32DAT); +} + +/** + * @brief Returns the current CRC value. + * @return 32-bit CRC + */ +uint32_t CRC32_GetCrc(void) +{ + return (CRC->CRC32DAT); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue 8-bit value to be stored in the ID register + */ +void CRC32_SetIDat(uint8_t IDValue) +{ + CRC->CRC32IDAT = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @return 8-bit value of the ID register + */ +uint8_t CRC32_GetIDat(void) +{ + return (CRC->CRC32IDAT); +} + +// CRC16 add +void __CRC16_SetLittleEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL; +} +void __CRC16_SetBigEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL; +} +void __CRC16_SetCleanEnable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL; +} +void __CRC16_SetCleanDisable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL; +} + +uint16_t __CRC16_CalcCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; + return (CRC->CRC16D); +} + +void __CRC16_SetCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; +} + +uint16_t __CRC16_GetCrc(void) +{ + return (CRC->CRC16D); +} + +void __CRC16_SetLRC(uint8_t Data) +{ + CRC->LRC = Data; +} + +uint8_t __CRC16_GetLRC(void) +{ + return (CRC->LRC); +} + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + CRC->CRC16D = 0x00; + for (index = 0; index < BufferLength; index++) + { + CRC->CRC16DAT = pBuffer[index]; + } + return (CRC->CRC16D); +} + +uint16_t CRC16_CalcCRC(uint8_t Data) +{ + CRC->CRC16DAT = Data; + + return (CRC->CRC16D); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dac.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..d47333ecffb9693b70204928a7970d4b03f1145f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dac.c @@ -0,0 +1,357 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dac.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_dac.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @addtogroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Defines + * @{ + */ + +/* CTRL register Mask */ +#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000001) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE) + +/* DCH registers offsets */ +#define DR12CH_OFFSET ((uint32_t)0x00000008) + +/* DATO register offset */ +#define DATO_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @addtogroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_InitStruct pointer to a DAC_InitType structure that + * contains the configuration information for the specified DAC channel. + */ +void DAC_Init(DAC_InitType* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput)); + /*---------------------------- DAC CTRL Configuration --------------------------*/ + /* Get the DAC CTRL value */ + tmpreg1 = DAC->CTRL; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CTRL_CLEAR_MASK ); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to Trigger value */ + /* Set WAVEx bits according to WaveGen value */ + /* Set MAMPx bits according to LfsrUnMaskTriAmp value */ + /* Set BOFFx bit according to BufferOutput value */ + tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp + | DAC_InitStruct->BufferOutput); + /* Calculate CTRL register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 ; + /* Write to DAC CTRL */ + DAC->CTRL = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct pointer to a DAC_InitType structure which will + * be initialized. + */ +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct) +{ + /*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the Trigger member */ + DAC_InitStruct->Trigger = DAC_TRG_NONE; + /* Initialize the WaveGen member */ + DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE; + /* Initialize the LfsrUnMaskTriAmp member */ + DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0; + /* Initialize the BufferOutput member */ + DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_Enable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CTRL |= DAC_CTRL_CHEN ; + } + else + { + /* Disable the selected DAC channel */ + DAC->CTRL &= ~DAC_CTRL_CHEN ; + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_DmaEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CTRL |= DAC_CTRL_DMAEN; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CTRL &= ~DAC_CTRL_DMAEN; + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SOTTR |= DAC_SOTTR_TREN ; + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SOTTR &= ~(DAC_SOTTR_TREN); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param Cmd new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftwareTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SOTTR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SOTTR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_Wave Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_WAVE_NOISE noise wave generation + * @arg DAC_WAVE_TRIANGLE triangle wave generation + * @param Cmd new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmp=DAC->CTRL; + tmp&=~(3<<6); + if (Cmd != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + tmp |= DAC_Wave; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + tmp&=~(3<<6); + } + DAC->CTRL =tmp; +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + */ +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DR12CH_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*)tmp = Data; +} + + + + + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @return The selected DAC channel data output value. + */ +uint16_t DAC_GetOutputDataVal(void) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DATO_OFFSET; + + /* Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dbg.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dbg.c new file mode 100644 index 0000000000000000000000000000000000000000..9dea84a5aa112191222b27756548090aafc9e8c5 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dbg.c @@ -0,0 +1,260 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dbg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_dbg.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @brief DBG driver modules + * @{ + */ + +/** @addtogroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Functions + * @{ + */ + + +void GetUCID(uint8_t *UCIDbuf) +{ + uint8_t num = 0; + uint32_t* ucid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260)) + { + ucid_addr = (uint32_t*)UCID_BASE; + } + else + { + ucid_addr = (uint32_t*)(0x1FFFF260); + } + + for (num = 0; num < UCID_LENGTH;) + { + temp = *(__IO uint32_t*)(ucid_addr++); + UCIDbuf[num++] = (temp & 0xFF); + UCIDbuf[num++] = (temp & 0xFF00) >> 8; + UCIDbuf[num++] = (temp & 0xFF0000) >> 16; + UCIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the UID. + * @return UID + */ + +void GetUID(uint8_t *UIDbuf) +{ + uint8_t num = 0; + uint32_t* uid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270)) + { + uid_addr = (uint32_t*)UID_BASE; + } + else + { + uid_addr = (uint32_t*)(0x1FFFF270); + } + + for (num = 0; num < UID_LENGTH;) + { + temp = *(__IO uint32_t*)(uid_addr++); + UIDbuf[num++] = (temp & 0xFF); + UIDbuf[num++] = (temp & 0xFF00) >> 8; + UIDbuf[num++] = (temp & 0xFF0000) >> 16; + UIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the DBGMCU_ID. + * @return DBGMCU_ID + */ + +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf) +{ + uint8_t num = 0; + uint32_t* dbgid_addr = (void*)0; + uint32_t temp = 0; + + dbgid_addr = (uint32_t*)DBGMCU_ID_BASE; + for (num = 0; num < DBGMCU_ID_LENGTH;) + { + temp = *(__IO uint32_t*)(dbgid_addr++); + DBGMCU_IDbuf[num++] = (temp & 0xFF); + DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8; + DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16; + DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the device revision number. + * @return Device revision identifier + */ +uint32_t DBG_GetRevNum(void) +{ + return (DBG->ID & 0x00FF); +} + +/** + * @brief Returns the device identifier. + * @return Device identifier + */ +uint32_t DBG_GetDevNum(void) +{ + uint32_t id = DBG->ID; + return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBG_Periph specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBG_SLEEP Keep debugger connection during SLEEP mode + * @arg DBG_STOP Keep debugger connection during STOP mode + * @arg DBG_STDBY Keep debugger connection during STANDBY mode + * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted + * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted + * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted + * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted + * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted + * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted + * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted + * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted + * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted + * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted + * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted + * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted + + * @param Cmd new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + */ +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBG_Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + DBG->CTRL |= DBG_Periph; + } + else + { + DBG->CTRL &= ~DBG_Periph; + } +} + +/** + * @brief Get FLASH size of this chip. + * + * @return FLASH size in bytes. + */ +uint32_t DBG_GetFlashSize(void) +{ + return (DBG->ID & 0x000F0000); +} + +/** + * @brief Get SRAM size of this chip. + * + * @return SRAM size in bytes. + */ +uint32_t DBG_GetSramSize(void) +{ + return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dma.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..4db791dd315626aa5aa0ce9fcdae3252c07c405f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_dma.c @@ -0,0 +1,686 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_dma.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_dma.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @addtogroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Defines + * @{ + */ + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1)) +#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2)) +#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3)) +#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4)) +#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5)) +#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6)) +#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7)) +#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8)) + + +/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + */ +void DMA_DeInit(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + + /* Reset DMAy Channelx control register */ + DMAChx->CHCFG = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAChx->TXNUM = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAChx->PADDR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAChx->MADDR = 0; + + if (DMAChx == DMA_CH1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA->INTCLR |= DMA_CH1_INT_MASK; + } + else if (DMAChx == DMA_CH2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA->INTCLR |= DMA_CH2_INT_MASK; + } + else if (DMAChx == DMA_CH3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA->INTCLR |= DMA_CH3_INT_MASK; + } + else if (DMAChx == DMA_CH4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA->INTCLR |= DMA_CH4_INT_MASK; + } + else if (DMAChx == DMA_CH5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA->INTCLR |= DMA_CH5_INT_MASK; + } + else if (DMAChx == DMA_CH6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA->INTCLR |= DMA_CH6_INT_MASK; + } + else if (DMAChx == DMA_CH7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA->INTCLR |= DMA_CH7_INT_MASK; + } + else if (DMAChx == DMA_CH8) + { + /* Reset interrupt pending bits for DMA1 Channel8 */ + DMA->INTCLR |= DMA_CH8_INT_MASK; + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitParam. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMA_InitParam pointer to a DMA_InitType structure that + * contains the configuration information for the specified DMA Channel. + */ +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_DIR(DMA_InitParam->Direction)); + assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize)); + assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc)); + assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize)); + assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode)); + assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem)); + + /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/ + /* Get the DMAyChx CHCFG value */ + tmpregister = DMAChx->CHCFG; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpregister &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to Direction value */ + /* Set CIRC bit according to CircularMode value */ + /* Set PINC bit according to PeriphInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to PeriphDataSize value */ + /* Set MSIZE bits according to MemDataSize value */ + /* Set PL bits according to Priority value */ + /* Set the MEM2MEM bit according to Mem2Mem value */ + tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc + | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize + | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem; + + /* Write to DMAy Channelx CHCFG */ + DMAChx->CHCFG = tmpregister; + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMAy Channelx TXNUM */ + DMAChx->TXNUM = DMA_InitParam->BufSize; + + /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/ + /* Write to DMAy Channelx PADDR */ + DMAChx->PADDR = DMA_InitParam->PeriphAddr; + + /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/ + /* Write to DMAy Channelx MADDR */ + DMAChx->MADDR = DMA_InitParam->MemAddr; +} + +/** + * @brief Fills each DMA_InitParam member with its default value. + * @param DMA_InitParam pointer to a DMA_InitType structure which will + * be initialized. + */ +void DMA_StructInit(DMA_InitType* DMA_InitParam) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the PeriphAddr member */ + DMA_InitParam->PeriphAddr = 0; + /* Initialize the MemAddr member */ + DMA_InitParam->MemAddr = 0; + /* Initialize the Direction member */ + DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC; + /* Initialize the BufSize member */ + DMA_InitParam->BufSize = 0; + /* Initialize the PeriphInc member */ + DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE; + /* Initialize the DMA_MemoryInc member */ + DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE; + /* Initialize the PeriphDataSize member */ + DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + /* Initialize the MemDataSize member */ + DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the CircularMode member */ + DMA_InitParam->CircularMode = DMA_MODE_NORMAL; + /* Initialize the Priority member */ + DMA_InitParam->Priority = DMA_PRIORITY_LOW; + /* Initialize the Mem2Mem member */ + DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAChx->CHCFG |= DMA_CHCFG1_CHEN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMAInt specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_INT_TXC Transfer complete interrupt mask + * @arg DMA_INT_HTX Half transfer interrupt mask + * @arg DMA_INT_ERR Transfer error interrupt mask + * @param Cmd new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_CONFIG_INT(DMAInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAChx->CHCFG |= DMAInt; + } + else + { + /* Disable the selected DMA interrupts */ + DMAChx->CHCFG &= ~DMAInt; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DataNumber The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAyChx is disabled. + */ +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMA Channelx TXNUM */ + DMAChx->TXNUM = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMA Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @return The number of remaining data units in the current DMA Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAChx->TXNUM)); +} + +/** + * @brief Checks whether the specified DMA Channelx flag is set or not. + * @param DMAFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel7 global flag. + * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMAFlag (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy flag */ + if ((tmpregister & DMAFlag) != (uint32_t)RESET) + { + /* DMAyFlag is set */ + bitstatus = SET; + } + else + { + /* DMAyFlag is reset */ + bitstatus = RESET; + } + + /* Return the DMAyFlag status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's pending flags. + * @param DMAFlag specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel8 global flag. + * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Clear the selected DMAy flags */ + DMAy->INTCLR = DMAFlag; +} + +/** + * @brief Checks whether the specified DMA Channelx interrupt has occurred or not. + * @param DMA_IT specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMA_IT (SET or RESET). + */ +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy interrupt */ + if ((tmpregister & DMA_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMAInt status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's interrupt pending bits. + * @param DMA_IT specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLR_INT(DMA_IT)); + + /* Calculate the used DMA */ + /* Clear the selected DMA interrupt pending bits */ + DMAy->INTCLR = DMA_IT; +} + +/** + * @brief Set the DMA Channelx's remap request. + * @param DMA_REMAP specifies the DMA request. + * This parameter can be set by the following values: + * @arg DMA_REMAP_ADC1 DMA Request For ADC1. + * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX. + * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX. + * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX. + * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX. + * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX. + * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX. + * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX. + * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX. + * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX. + * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX. + * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX. + * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX. + * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX. + * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX. + * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX. + * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX. + * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX. + * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX. + * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX. + * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX. + * @arg DMA_REMAP_DAC1 DMA Request For DAC1. + * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1. + * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2. + * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3. + * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4. + * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM. + * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP. + * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG. + * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1. + * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2. + * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3. + * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP. + * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1. + * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3. + * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4. + * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP. + * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1. + * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2. + * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3. + * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP. + * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1. + * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2. + * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3. + * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4. + * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP. + * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG. + * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP. + * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP. + * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1. + * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2. + * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3. + * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4. + * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM. + * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP. + * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG. + * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1. + * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG. + * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3. + * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4. + * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_REMAP(DMA_REMAP)); + + if (Cmd != DISABLE) + { + /* Calculate the used DMAy */ + /* Set the selected DMAy remap request */ + DMAChx->CHSEL = DMA_REMAP; + } + else + { + /* Clear DMAy remap */ + DMAChx->CHSEL = 0; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_exti.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_exti.c new file mode 100644 index 0000000000000000000000000000000000000000..9b75072ef7859e63996a9757c647b93601db149f --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_exti.c @@ -0,0 +1,286 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_exti.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_exti.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @addtogroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + */ +void EXTI_DeInit(void) +{ + EXTI->IMASK = 0x00000000; + EXTI->EMASK = 0x00000000; + EXTI->RT_CFG = 0x00000000; + EXTI->FT_CFG = 0x00000000; + EXTI->PEND = 0x0FFFFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure + * that contains the configuration information for the EXTI peripheral. + */ +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will + * be initialized. + */ +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_TriggerSWInt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIE |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrStatusFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMASK & EXTI_Line; + if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrITPendBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Select one of EXTI inputs to the RTC TimeStamp event. + * @param EXTI_TSSEL_Line specifies the EXTI lines to select. + * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15). + */ +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line)); + + EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK; + EXTI->TS_SEL |= EXTI_TSSEL_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_flash.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..6d14893336963225ff191eb6ae434e916692c292 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_flash.c @@ -0,0 +1,1554 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_flash.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_flash.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @addtogroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define AC_LATENCY_MSK ((uint32_t)0x000000F8) +#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF) +#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F) +#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF) +#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF) + +/* Flash Access Control Register bits */ +#define AC_PRFTBS_MSK ((uint32_t)0x00000020) +#define AC_ICAHRST_MSK ((uint32_t)0x00000040) +#define AC_LVMF_MSK ((uint32_t)0x00000100) +#define AC_SLMF_MSK ((uint32_t)0x00000400) + +/* Flash Control Register bits */ +#define CTRL_Set_PG ((uint32_t)0x00000001) +#define CTRL_Reset_PG ((uint32_t)0x00003FFE) +#define CTRL_Set_PER ((uint32_t)0x00000002) +#define CTRL_Reset_PER ((uint32_t)0x00003FFD) +#define CTRL_Set_MER ((uint32_t)0x00000004) +#define CTRL_Reset_MER ((uint32_t)0x00003FFB) +#define CTRL_Set_OPTPG ((uint32_t)0x00000010) +#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF) +#define CTRL_Set_OPTER ((uint32_t)0x00000020) +#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF) +#define CTRL_Set_START ((uint32_t)0x00000040) +#define CTRL_Set_LOCK ((uint32_t)0x00000080) +#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF) +#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000) +#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100) + +/* FLASH Mask */ +#define RDPRTL1_MSK ((uint32_t)0x00000002) +#define RDPRTL2_MSK ((uint32_t)0x80000000) +#define OBR_USER_MSK ((uint32_t)0x0000001C) +#define WRP0_MSK ((uint32_t)0x000000FF) +#define WRP1_MSK ((uint32_t)0x0000FF00) +#define WRP2_MSK ((uint32_t)0x00FF0000) +#define WRP3_MSK ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define L1_RDP_Key ((uint32_t)0xFFFF00A5) +#define RDP_USER_Key ((uint32_t)0xFFF000A5) +#define L2_RDP_Key ((uint32_t)0xFFFF33CC) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @note This function can be used for N32G43x devices. + * @param FLASH_Latency specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1 FLASH One Latency cycle + * @arg FLASH_LATENCY_2 FLASH Two Latency cycles + * @arg FLASH_LATENCY_3 FLASH Three Latency cycles + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpregister = FLASH->AC; + + /* Sets the Latency value */ + tmpregister &= AC_LATENCY_MSK; + tmpregister |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->AC = tmpregister; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for N32G43x devices. + * @param FLASH_PrefetchBuf specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable + */ +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->AC &= AC_PRFTBE_MSK; + FLASH->AC |= FLASH_PrefetchBuf; +} + +/** + * @brief ICache Reset. + * @note This function can be used for N32G43x devices. + */ +void FLASH_iCacheRST(void) +{ + /* ICache Reset */ + FLASH->AC |= FLASH_AC_ICAHRST; +} + +/** + * @brief Enables or disables the iCache. + * @note This function can be used for N32G43x devices. + * @param FLASH_iCache specifies the iCache status. + * This parameter can be one of the following values: + * @arg FLASH_iCache_EN FLASH iCache Enable + * @arg FLASH_iCache_DIS FLASH iCache Disable + */ +void FLASH_iCacheCmd(uint32_t FLASH_iCache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache)); + + /* Enable or disable the iCache */ + FLASH->AC &= AC_ICAHEN_MSK; + FLASH->AC |= FLASH_iCache; +} + +/** + * @brief Enables or disables the Low Voltage Mode. + * @note This function can be used for N32G43x devices. + * @param FLASH_LVM specifies the Low Voltage Mode status. + * This parameter can be one of the following values: + * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable + * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable + */ +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LVM(FLASH_LVM)); + + /* Enable or disable LVM */ + FLASH->AC &= AC_LVMEN_MSK; + FLASH->AC |= FLASH_LVM; +} + +/** + * @brief Checks whether the Low Voltage Mode status is SET or RESET. + * @note This function can be used for N32G43x devices. + * @return Low Voltage Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetLowVoltageModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the FLASH Sleep Mode. + * @note This function can be used for N32G43x devices. + * @param FLASH_SLM specifies the FLASH Sleep Mode status. + * This parameter can be one of the following values: + * @arg FLASH_SLM_EN FLASH iCache Enable + * @arg FLASH_SLM_DIS FLASH iCache Disable + */ +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SLM(FLASH_SLM)); + + /* Enable or disable SLM */ + FLASH->AC &= AC_SLMEN_MSK; + FLASH->AC |= FLASH_SLM; +} + +/** + * @brief Checks whether the FLASH Sleep Mode status is SET or RESET. + * @note This function can be used for N32G43x devices. + * @return FLASH Sleep Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetFLASHSleepModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32G43x devices. + * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2 + */ +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel)); + + /* SMP1 or SMP2 */ + FLASH->CTRL &= CTRL_Reset_SMPSEL; + FLASH->CTRL |= FLASH_smpsel; +} + +/** + * @brief Configures the Internal High Speed oscillator + * to program/erase FLASH. + * @note This function can be used for N32G43x devices. + * - For N32G43x devices this function enable HSI. + * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE). + */ +FLASH_HSICLOCK FLASH_ClockInit(void) +{ + bool HSIStatus = 0; + __IO uint32_t StartUpCounter = 0; + FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE; + + if((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET) + { + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + hsiclock_status = FLASH_HSICLOCK_DISABLE; + } + } + return hsiclock_status; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for N32G43x devices. + * - For N32G43x devices this function unlocks Bank. + * to FLASH_Unlock function.. + */ +void FLASH_Unlock(void) +{ + /* Unlocks the FLASH Program Erase Controller */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for N32G43x devices. + * - For N32G43x devices this function Locks Bank. + * to FLASH_Lock function. + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FLASH Program Erase Controller */ + FLASH->CTRL |= CTRL_Set_LOCK; +} + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for N32G43x devices. + * @param Page_Address The page address to be erased. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CTRL |= CTRL_Set_PER; + FLASH->ADD = Page_Address; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CTRL &= CTRL_Reset_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all N32G43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_MassErase(void) +{ + FLASH_STS status = FLASH_COMPL; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= CTRL_Set_MER; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CTRL &= CTRL_Reset_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for N32G43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOB(void) +{ + uint32_t rdptmp = L1_RDP_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdptmp = FLASH_USER_USER; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = (uint32_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the erase status */ + return status; +} + + +/** + * @brief Programs the FLASH User Option Byte: + * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / OB_Data0 / OB_Data1 + * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for N32G43x devices. + * @param OB_RDP1 + * This parameter can be one of the following values: + * @arg OB_RDP1_ENABLE + * @arg OB_RDP1_DISABLE + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @param OB_Data0 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param OB_Data1 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param WRP_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages) + * @param OB_RDP2 + * This parameter can be one of the following values: + * @arg OB_RDP2_ENABLE + * @arg OB_RDP2_DISABLE + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_RDP1_SOURCE(OB_RDP1)); + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + assert_param(IS_FLASH_WRP_PAGE(WRP_Pages)); + assert_param(IS_OB_RDP2_SOURCE(OB_RDP2)); + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + WRP_Pages = (uint32_t)(~WRP_Pages); + rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY )) << 16)); + data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data1) << 16)); + wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1)); + wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3)); + rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16)); + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Program USER_RDP Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program Data1_Data0 Option Byte value */ + OBT->Data1_Data0 = (uint32_t)data0data1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP1_WRP0 Option Byte value */ + OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP3_WRP2 Option Byte value */ + OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program USER2_RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + } + } + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for N32G43x devices. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + if((Address & (uint32_t)0x3) != 0) + { + /* The programming address is not a multiple of 4 */ + status = FLASH_ERR_ADD; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to program the new word */ + FLASH->CTRL |= CTRL_Set_PG; + + *(__IO uint32_t*)Address = (uint32_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CTRL &= CTRL_Reset_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for N32G43x devices. + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804. + * @param Data specifies the data to be programmed(Data0 and Data1). + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + *(__IO uint32_t*)Address = (uint32_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for N32G43x devices. + * @param FLASH_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63 + * @arg FLASH_WRP_AllPages + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTPG; + + if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF)) + { + OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL)) + { + OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32G43x devices. + * @param Cmd new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + if (Cmd != DISABLE) + { + OBT->USER_RDP = (FLASH_USER_USER & usertmp); + } + else + { + OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection L2. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32G43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + + /* Get the actual read protection L1 Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() == RESET) + { + usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1); + } + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + OBT->USER_RDP = usertmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Enables the read out protection L2 */ + OBT->USER2_RDP2 = L2_RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for N32G43x devices. + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY) +{ + uint32_t rdpuser_tmp = RDP_USER_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFF00000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = + (uint32_t)rdpuser_tmp + | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY )) << 16); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for N32G43x devices. + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, + uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER); + uint32_t rdp2user2_tmp = 0xFF00FFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFFF0000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Restore the last RDP1 Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Restore the last RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \ + | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for N32G43x devices. + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOB(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OB >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for N32G43x devices. + * @return The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOB(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRP); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for N32G43x devices. + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionSTS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not. + * @note This function can be used for N32G43x devices. + * @return FLASH ReadOut Protection L2 Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionL2STS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for N32G43x devices. + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32G43x devices. + * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2). + */ +FLASH_SMPSEL FLASH_GetSMPSELStatus(void) +{ + FLASH_SMPSEL bitstatus = FLASH_SMP1; + + if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1) + { + bitstatus = FLASH_SMP2; + } + else + { + bitstatus = FLASH_SMP1; + } + /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for N32G43x devices. + * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR FLASH Error Interrupt + * @arg FLASH_INT_FERR EVERR PVERR Interrupt + * @arg FLASH_INT_EOP FLASH end of operation Interrupt + * @param Cmd new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FLASH_INT(FLASH_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CTRL |= FLASH_INT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CTRL &= ~(uint32_t)FLASH_INT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for N32G43x devices. + * @param FLASH_FLAG specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BUSY FLASH Busy flag + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + if (FLASH_FLAG == FLASH_FLAG_OBERR) + { + if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for N32G43x devices. + * @param FLASH_FLAG specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->STS |= FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for N32G43x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_GetSTS(void) +{ + FLASH_STS flashstatus = FLASH_COMPL; + + if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERR_PG; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PVERR) != 0) + { + flashstatus = FLASH_ERR_PV; + } + else + { + if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0) + { + flashstatus = FLASH_ERR_WRP; + } + else + { + if ((FLASH->STS & FLASH_FLAG_EVERR) != 0) + { + flashstatus = FLASH_ERR_EV; + } + else + { + flashstatus = FLASH_COMPL; + } + } + } + } + } + + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for N32G43x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation.. + * @param Timeout FLASH programming Timeout + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check for the Flash Status */ + status = FLASH_GetSTS(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetSTS(); + Timeout--; + } + if (Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_gpio.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..31b69215363e735facb1018f70fd55401a49bb10 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_gpio.c @@ -0,0 +1,768 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_gpio.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_gpio.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @addtogroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- Event control register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +#define GPIO_MODE ((uint32_t)0x00000003) +#define EXTI_MODE ((uint32_t)0x10000000) +#define GPIO_MODE_IT ((uint32_t)0x00010000) +#define GPIO_MODE_EVT ((uint32_t)0x00020000) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300) +#define GPIO_NUMBER ((uint32_t)16) + + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + */ +void GPIO_DeInit(GPIO_Module* GPIOx) +{ + + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + uint32_t GPIO_Pin = GPIO_PIN_ALL; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + /* Check the parameters */ + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + + if (GPIOx == GPIOA) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE); + } + else + { + return; + } + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0) + { + /* Get the IO position */ + iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position); + + if(iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = AFIO->EXTI_CFG[position>>2]; + tmp &= (0x0FuL << (4u*(position & 0x03u))); + if(tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~(iocurrent); + EXTI->EMASK &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~(iocurrent); + EXTI->FT_CFG &= ~(iocurrent); + tmp = 0x0FuL << (4u * (position & 0x03u)); + AFIO->EXTI_CFG[position >> 2u] &= ~tmp; + } + + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + if(position & 0x08) + GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + else + GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + + /* Configure the default value IO Output Type */ + GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U)); + + } + position++; + } +} + + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + */ +void GPIO_AFIOInitDefault(void) +{ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure that + * contains the configuration information for the specified GPIO peripheral. + */ + +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct) +{ + uint32_t pinpos = 0x00U; + uint32_t tmp = 0x00U,tmpregister=0x00U; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull)); + assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + + /*---------------------------- GPIO PL_CFG Configuration ------------------------*/ + + while(((GPIO_InitStruct->Pin)>>position) != 0) + { + iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog)) + { + /* Check if the Alternate function is compliant with the GPIO in use */ + assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate)); + /* Configure Alternate function mapped with the current IO */ + if(position & 0x08) + { + tmp = GPIOx->AFH; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFH = tmp; + } + else + { + tmp = GPIOx->AFL; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFL = tmp; + } + } + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmpregister = GPIOx->PMODE; + tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |=( tmp << pinpos); + GPIOx->PMODE = tmpregister; + + /* Configure pull-down mode */ + tmpregister = GPIOx->PUPD; + tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03); + tmpregister &=~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp <PUPD = tmpregister; + + + /* Configure driver current*/ + if((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog)) + { + assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current)); + tmpregister = GPIOx->DS; + tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03)); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp<DS = tmpregister; + } + /* Configure slew rate*/ + tmp = GPIOx->SR; + tmp &=((uint32_t)(~((uint16_t)0x01 << position))); + tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp; + /*Configure Set/Reset register*/ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down) + { + GPIOx->PBC |= (((uint32_t)0x01) << position); + } + else + { + /* Set the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up) + { + GPIOx->PBSC |= (((uint32_t)0x01) << position); + } + } + + /* In case of Output or Alternate function mode selection */ + if((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) || + (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD)) + { + /* Configure the IO Output Type */ + + tmp= GPIOx->POTYPE; + tmp &= ~(((uint32_t)0x01U) << position) ; + tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->POTYPE = tmp; + } + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if(GPIO_InitStruct->GPIO_Mode & EXTI_MODE) + { + /* Clear EXTI line configuration */ + tmp = EXTI->IMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->IMASK = tmp; + + tmp = EXTI->EMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->EMASK = tmp; + + /* Clear Rising Falling edge configuration */ + + tmp = EXTI->RT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->RT_CFG = tmp; + + tmp = EXTI->FT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->FT_CFG = tmp; + } + } + position++; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will + * be initialized. + */ +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = GPIO_PIN_ALL; + GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input; + GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF; + GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull; + GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->PID); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->POD); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} +void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + // assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBC = Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitCmd specifies the value to be written to the selected bit. + * This parameter can be one of the Bit_OperateType enum values: + * @arg Bit_RESET to clear the port pin + * @arg Bit_SET to set the port pin + */ +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + assert_param(IS_GPIO_BIT_OPERATE(BitCmd)); + + if (BitCmd != Bit_RESET) + { + GPIOx->PBSC = Pin; + } + else + { + GPIOx->PBC = Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param PortVal specifies the value to be written to the port output data register. + */ +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->POD = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + tmp |= Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Reset LCKK bit */ + GPIOx->PLOCK = Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; +} + + + +/** + * @brief Changes the mapping of the specified pin. + * @param PortSource selects the GPIO port to be used. + * @param PinSource specifies the pin for the remaping. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param AlternateFunction specifies the alternate function for the remaping. + */ +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction) +{ + uint32_t tmp = 0x00, tmpregister = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + assert_param(IS_GPIO_AF(AlternateFunction)); + /*Get Peripheral point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + /**/ + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param PortSource selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t tmpregister = 0x00,tmp = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + /*Get Peripheral structure point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Enables or disables the Event Output. + * @param Cmd new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + */ +void GPIO_CtrlEventOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd; +} + + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param PortSource selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t port = (uint32_t)PortSource; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u)); + AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u)); +} + +/** + * @brief Selects the alternate function SPIx NSS mode. + * @param AFIO_SPIx_NSS choose which SPI configuration. + * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS. + * @param SpiNssType specifies the SPI_NSS mode to be configured. + * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL. + */ +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS)); + assert_param(IS_AFIO_SPI_NSS(SpiNssType)); + tmp = AFIO->RMP_CFG; + tmp &=(~(0x01U << AFIO_SPIx_NSS)); + tmp |=(SpiNssType << AFIO_SPIx_NSS); + AFIO->RMP_CFG = tmp; +} + +/** + * @brief Configurate ADC external trigger. + * @param ADCETRType choose whether to configure rule conversion or injection conversion . + * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR. + * @param ADCTrigRemap specifies the external trigger line be configured. + * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4). + */ +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETR(ADCETRType)); + if(ADCETRType == AFIO_ADC_ETRI) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRI bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRI)); + /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4) + { + /* select TIM8_CH4 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRI); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<4U)); + tmp |= (ADCTrigRemap<<4U); + } + AFIO->RMP_CFG = tmp; + } + else + { + if(ADCETRType == AFIO_ADC_ETRR) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRR bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRR)); + /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3) + { + /* select TIM8_CH3 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRR); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<0)); + tmp |= ADCTrigRemap; + } + AFIO->RMP_CFG = tmp; + } + } +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_i2c.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..44a51c5e7d24aeaa17ce5452d6f7461b214df0c8 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_i2c.c @@ -0,0 +1,1301 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_i2c.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_i2c.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @addtogroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CTRL1_SPEN_SET ((uint16_t)0x0001) +#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTRL1_START_SET ((uint16_t)0x0100) +#define CTRL1_START_RESET ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTRL1_STOP_SET ((uint16_t)0x0200) +#define CTRL1_STOP_RESET ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTRL1_ACK_SET ((uint16_t)0x0400) +#define CTRL1_ACK_RESET ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTRL1_GCEN_SET ((uint16_t)0x0040) +#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTRL1_SWRESET_SET ((uint16_t)0x8000) +#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTRL1_PEC_SET ((uint16_t)0x1000) +#define CTRL1_PEC_RESET ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTRL1_PECEN_SET ((uint16_t)0x0020) +#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTRL1_ARPEN_SET ((uint16_t)0x0010) +#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080) +#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTRL2_DMAEN_SET ((uint16_t)0x0800) +#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTRL2_DMALAST_SET ((uint16_t)0x1000) +#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADDR0_SET ((uint16_t)0x0001) +#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_DUALEN_SET ((uint16_t)0x0001) +#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000) + +/* I2C CHCFG mask */ +#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_MASK ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define INTEN_MASK ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @addtogroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + */ +void I2C_DeInit(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct pointer to a I2C_InitType structure that + * contains the configuration information for the specified I2C peripheral. + */ +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint16_t tmpregister = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksType rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed)); + assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode)); + assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle)); + assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable)); + assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode)); + + /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/ + /* Get the I2Cx CTRL2 value */ + tmpregister = I2Cx->CTRL2; + /* Clear frequency FREQ[5:0] bits */ + tmpregister &= CTRL2_CLKFREQ_RESET; + /* Get pclk1 frequency value */ + RCC_GetClocksFreqValue(&rcc_clocks); + pclk1 = rcc_clocks.Pclk1Freq; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpregister |= freqrange; + /* Write to I2Cx CTRL2 */ + I2Cx->CTRL2 = tmpregister; + + /*---------------------------- I2Cx CHCFG Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TMRISE */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + /* Reset tmpregister value */ + /* Clear F/S, DUTY and CHCFG[11:0] bits */ + tmpregister = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->ClkSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1)); + /* Test if CHCFG value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpregister |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TMRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + // else if((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <= + // 400000)*/ + else + { + if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3)); + } + else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_FMDUTYCYCLE_16_9; + } + + /* Test if CHCFG value is under 0x1*/ + if ((result & CLKCTRL_CLKCTRL_SET) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET); + /* Set Maximum Rise Time for fast mode */ + // if (I2C_InitStruct->ClkSpeed <= 400000) + { + I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + // else//add test + //{ + // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1); + //} + } + /* Write to I2Cx CHCFG */ + I2Cx->CLKCTRL = tmpregister; + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + + /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/ + /* Get the I2Cx CTRL1 value */ + tmpregister = I2Cx->CTRL1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to BusMode value */ + /* Set ACK bit according to AckEnable value */ + tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable); + /* Write to I2Cx CTRL1 */ + I2Cx->CTRL1 = tmpregister; + + /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized. + */ +void I2C_InitStruct(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the ClkSpeed member */ + I2C_InitStruct->ClkSpeed = 5000; + /* Initialize the BusMode member */ + I2C_InitStruct->BusMode = I2C_BUSMODE_I2C; + /* Initialize the FmDutyCycle member */ + I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2; + /* Initialize the OwnAddr1 member */ + I2C_InitStruct->OwnAddr1 = 0; + /* Initialize the AckEnable member */ + I2C_InitStruct->AckEnable = I2C_ACKDIS; + /* Initialize the AddrMode member */ + I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CTRL2 |= CTRL2_DMAEN_SET; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CTRL2 &= CTRL2_DMAEN_RESET; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CTRL2 |= CTRL2_DMALAST_SET; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CTRL2 &= CTRL2_DMALAST_RESET; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL1 |= CTRL1_START_SET; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL1 &= CTRL1_START_RESET; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CTRL1 |= CTRL1_STOP_SET; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CTRL1 &= CTRL1_STOP_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CTRL1 |= CTRL1_ACK_SET; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CTRL1 &= CTRL1_ACK_RESET; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the 7bit I2C own address2. + */ +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address) +{ + uint16_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpregister = I2Cx->OADDR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpregister &= OADDR2_ADDR2_RESET; + + /* Set I2Cx Own address2 */ + tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OADDR2 = tmpregister; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OADDR2 |= OADDR2_DUALEN_SET; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OADDR2 &= OADDR2_DUALEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable generall call */ + I2Cx->CTRL1 |= CTRL1_GCEN_SET; + } + else + { + /* Disable generall call */ + I2Cx->CTRL1 &= CTRL1_GCEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_BUF Buffer interrupt mask + * @arg I2C_INT_EVENT Event interrupt mask + * @arg I2C_INT_ERR Error interrupt mask + * @param Cmd new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_I2C_CFG_INT(I2C_IT)); + + if (Cmd != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CTRL2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CTRL2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Data Byte to be transmitted.. + */ +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Write in the DAT register the data to be sent */ + I2Cx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The value of the received data. + */ +uint8_t I2C_RecvData(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->DAT; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the slave address which will be transmitted + * @param I2C_Direction specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_DIRECTION_SEND Transmitter mode + * @arg I2C_DIRECTION_RECV Receiver mode + */ +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_DIRECTION_SEND) + { + /* Set the address bit0 for read */ + Address |= OADDR1_ADDR0_SET; + } + else + { + /* Reset the address bit0 for write */ + Address &= OADDR1_ADDR0_RESET; + } + /* Send the address */ + I2Cx->DAT = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_REG_CTRL1 CTRL1 register. + * @arg I2C_REG_CTRL2 CTRL2 register. + * @arg I2C_REG_OADDR1 OADDR1 register. + * @arg I2C_REG_OADDR2 OADDR2 register. + * @arg I2C_REG_DAT DAT register. + * @arg I2C_REG_STS1 STS1 register. + * @arg I2C_REG_STS2 STS2 register. + * @arg I2C_REG_CLKCTRL CHCFG register. + * @arg I2C_REG_TMRISE TMRISE register. + * @return The value of the read register. + */ +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_REG(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t*)tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CTRL1 |= CTRL1_SWRESET_SET; + } + else + { + /* Peripheral not under reset */ + I2Cx->CTRL1 &= CTRL1_SWRESET_RESET; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACK_POS_NEXT) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last + * received byte. + * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_ConfigPecLocation() + * but is intended to be used in I2C mode while I2C_ConfigPecLocation() + * is intended to used in SMBUS mode. + * + */ +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POS(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACK_POS_NEXT) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CTRL1 |= I2C_NACK_POS_NEXT; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBALERT_LOW SMBAlert pin driven low + * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high + */ +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBALERT_LOW) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CTRL1 |= I2C_SMBALERT_LOW; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CTRL1 &= I2C_SMBALERT_HIGH; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CTRL1 |= CTRL1_PEC_SET; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CTRL1 &= CTRL1_PEC_RESET; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC + * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_ConfigNackLocation() + * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation() + * is intended to used in I2C mode. + * + */ +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POS(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PEC_POS_NEXT) + { + /* Next byte in shift register is PEC */ + I2Cx->CTRL1 |= I2C_PEC_POS_NEXT; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= CTRL1_PECEN_SET; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= CTRL1_PECEN_RESET; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The PEC value. + */ +uint8_t I2C_GetPec(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->STS2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CTRL1 |= CTRL1_ARPEN_SET; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CTRL1 &= CTRL1_ARPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param FmDutyCycle specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2 + * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9 + */ +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle)); + if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9; + } +} + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlag() function. + * The returned value could be compared to events already defined in the + * library (n32g43x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * n32g43x_i2c.h file. + * + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_DATA_RECVD EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2 + * @arg I2C_EVT_SLAVE_DATA_SENDED EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3 + * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2 + * @arg I2C_EVT_SLAVE_STOP_RECVD EV4 + * @arg I2C_EVT_MASTER_MODE_FLAG EV5 + * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7 + * @arg I2C_EVT_MASTER_DATA_SENDING EV8 + * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2 + * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32g43x_i2c.h file. + * + * @return An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_EVT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32g43x_i2c.h file. + * + * @return The last event + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode) + * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode) + * @arg I2C_FLAG_TRF Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY Bus busy flag + * @arg I2C_FLAG_MSMODE Master/Slave flag + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BYTEF Byte transfer finished flag + * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if (i2creg != 0) + { + /* Get the I2Cx STS1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx STS2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx STS2 register address */ + i2cxbase += 0x18; + } + + if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation + * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the + * second byte of the address in DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetFlag()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 + * register (I2C_GetFlag()) followed by a write operation to I2C_DAT + * register (I2C_SendData()). + */ +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert flag + * @arg I2C_INT_TIMOUT Timeout or Tlow error flag + * @arg I2C_INT_PECERR PEC error in reception flag + * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure flag + * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_INT_BUSERR Bus error flag + * @arg I2C_INT_TXDATE Data register empty flag (Transmitter) + * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_INT_STOPF Stop detection flag (Slave mode) + * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_INT_BYTEF Byte transfer finished flag + * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_INT_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_IT (SET or RESET). + */ +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_INT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2)); + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert interrupt + * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt + * @arg I2C_INT_PECERR PEC error in reception interrupt + * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt + * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode) + * @arg I2C_INT_BUSERR Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second + * byte of the address in I2C_DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_DAT register (I2C_SendData()). + */ +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_INT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_iwdg.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_iwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..12cad521e0044b16d5105a2e693583c1a1089cf4 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_iwdg.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_iwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_iwdg.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @addtogroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KEY register bit mask */ +#define KEY_ReloadKey ((uint16_t)0xAAAA) +#define KEY_EnableKey ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers + */ +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE(IWDG_WriteAccess)); + IWDG->KEY = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4 + * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8 + * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16 + * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32 + * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64 + * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128 + * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256 + */ +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler)); + IWDG->PREDIV = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + */ +void IWDG_CntReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RELV = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_ReloadKey(void) +{ + IWDG->KEY = KEY_ReloadKey; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_Enable(void) +{ + IWDG->KEY = KEY_EnableKey; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_PVU_FLAG Prescaler Value Update on going + * @arg IWDG_CRVU_FLAG Reload Value Update on going + * @return The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lptim.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lptim.c new file mode 100644 index 0000000000000000000000000000000000000000..e083197c0affc5f92147fedb0826e52fe9d6e026 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lptim.c @@ -0,0 +1,1258 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* + * ----------------------------------------------------------------------------- + */ + +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32g43x_lptim.c + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "n32g43x_lptim.h" +#include "n32g43x_rcc.h" + +/** @addtogroup n32g43x_StdPeriph_Driver + * @{ + */ + +/** @defgroup LPTIM + * @brief LPTIM driver modules + * @{ + */ + +/** @defgroup LPTIM_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ +//#define LPTIM +//#if defined (LPTIM)//LPTIM + +/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +void LPTIM_DeInit(LPTIM_Module* LPTIMx) +{ + if (LPTIMx == LPTIM) + { + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE); + } +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval None + */ +void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM; + LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + + /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFG, + (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note + * @retval None + */ +void LPTIM_Disable(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_Enable(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LPTIM_StartCounter\n + * CR SNGSTRT LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode); +} + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag be set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CMP register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMPOK flag be set, will + * lead to unpredictable results. + * @rmtoll CMP CMP LPTIM_SetCompare + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CMP CMP LPTIM_GetCompare + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + */ +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN)); +} + +/** + * @brief Configure the LPTIM instance output (LPTIMx_OUT) + * @note This function must be called when the LPTIM instance is disabled. + * @note Regarding the LPTIM output polarity the change takes effect + * immediately, so the output default value will change immediately after + * the polarity is re-configured, even before the timer is enabled. + * @rmtoll CFG WAVE LPTIM_ConfigOutput\n + * CFG WAVPOL LPTIM_ConfigOutput + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity); +} + +/** + * @brief Set waveform shape + * @rmtoll CFG WAVE LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFG WAVE LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE)); +} + +/** + * @brief Set output polarity + * @rmtoll CFG WAVPOL LPTIM_SetPolarity + * @param LPTIMx Low-Power Timer instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity); +} + +/** + * @brief Get actual output polarity + * @rmtoll CFG WAVPOL LPTIM_GetPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + */ +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL)); +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFG PRESC LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + * @retval None + */ +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFG PRESC LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + */ +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFG TIMOUT LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFG TIMOUT LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG TRIGEN LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_TrigSw(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n + * CFG TRGFLT LPTIM_ConfigTrigger\n + * CFG TRIGEN LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + * @param Filter This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + */ +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + */ +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKSEL LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFG CKSEL LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + */ +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFG CKFLT LPTIM_ConfigClock\n + * CFG CKPOL LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFG CKPOL LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFG CKFLT LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + */ +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKPOL LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFG CKPOL LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + */ +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC); +} +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG ENC LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag (CMPMCF) + * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF); +} + +/** + * @brief Inform application whether a compare match interrupt has occurred. + * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occured. + * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMPOKCF). + * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR UP LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Disable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. + * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. + * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx) +{ + return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL); +} + +/** + * @} + */ + + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ + diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lpuart.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lpuart.c new file mode 100644 index 0000000000000000000000000000000000000000..4f491c61d925334dc4e8cdfaa08f66757dac1537 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_lpuart.c @@ -0,0 +1,536 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_lpuart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_lpuart.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @brief LPUART driver modules + * @{ + */ + +/** @addtogroup LPUART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Defines + * @{ + */ + +#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */ + +#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */ +#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */ + +#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */ +#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */ +#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */ +#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */ +#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */ +#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */ +#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */ +#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */ +#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the LPUART peripheral registers to their default reset values. + */ +void LPUART_DeInit(void) +{ + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE); +} + +/** + * @brief Initializes the LPUART peripheral according to the specified + * parameters in the LPUART_InitStruct. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * that contains the configuration information for the specified LPUART + * peripheral. + */ +void LPUART_Init(LPUART_InitType* LPUART_InitStruct) +{ + uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00; + RCC_ClocksType RCC_ClocksStatus; + + /* Check the parameters */ + // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode)); + assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold)); + assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl)); + + // 时钟源判断，波特率范围 + + /*---------------------------- LPUART CTRL Configuration -----------------------*/ + tmpregister = LPUART->CTRL; + /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */ + tmpregister &= CTRL_CLR_MASK; + /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */ + /* Set PCDIS and PSEL bits according to Parity value */ + /* Set the TRS bit according to Mode */ + /* Set RTS_THSEL[1:0] bits according to RtsThrehold */ + /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */ + tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl; + /* Write to LPUART CTRL */ + LPUART->CTRL = (uint16_t)tmpregister; + + /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/ + /* Configure the LPUART Baud Rate -------------------------------------------*/ + clocksrc = RCC_GetLPUARTClkSrc(); + if (clocksrc == RCC_LPUARTCLK_SRC_LSE) + { + apbclock = 0x8000; // 32.768kHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_HSI) + { + apbclock = 0xF42400; // 16MHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.SysclkFreq; + } + else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = apbclock / (LPUART_InitStruct->BaudRate); + + /* Configure sampling method */ + if(integerdivider <= 10) + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B); + } + else + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B); + } + + /* Check baudrate */ + assert_param(IS_LPUART_BAUDRATE(integerdivider)); + /* Write to LPUART BRCFG1 */ + LPUART->BRCFG1 = (uint16_t)integerdivider; + + /* Determine the fractional part */ + fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate); + + tmpregister = 0x00; + tmpdivider = fractionaldivider; + /* Implement the fractional part in the register */ + for( i = 0; i < 8; i++) + { + lastdivider = tmpdivider; + tmpdivider = lastdivider + fractionaldivider; + if((tmpdivider / 10000) ^ (lastdivider / 10000)) + { + tmpregister |= (0x01 << i); + } + } + /* Write to LPUART BRCFG2 */ + LPUART->BRCFG2 = (uint8_t)tmpregister; +} + +/** + * @brief Fills each LPUART_InitStruct member with its default value. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * which will be initialized. + */ +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct) +{ + /* LPUART_InitStruct members default value */ + LPUART_InitStruct->BaudRate = 9600; + LPUART_InitStruct->Parity = LPUART_PE_NO; + LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX; + LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU; + LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE; +} + +/** + * @brief Flushes Receiver FIFO. + */ +void LPUART_FlushRxFifo(void) +{ + /* Clear LPUART Flush Receiver FIFO */ + LPUART->CTRL |= CTRL_FLUSH_SET; + while(LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET) + { + } + LPUART->CTRL &= CTRL_FLUSH_RESET; +} + +/** + * @brief Enables or disables the specified LPUART interrupts. + * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @param Cmd new state of the specified LPUART interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CFG_INT(LPUART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + LPUART->INTEN |= (uint8_t)LPUART_INT; + } + else + { + LPUART->INTEN &= (uint8_t)(~LPUART_INT); + } +} + +/** + * @brief Enables or disables the LPUART's DMA interface. + * @param LPUART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg LPUART_DMAREQ_TX LPUART DMA transmit request + * @arg LPUART_DMAREQ_RX LPUART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL |= LPUART_DMAReq; + } + else + { + /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq); + } +} + +/** + * @brief Selects the LPUART WakeUp method. + * @param LPUART_WakeUpMethod specifies the LPUART wakeup method. + * This parameter can be one of the following values: + * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection + * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection + * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte + * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame + */ +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod)); + + LPUART->CTRL &= CTRL_WUSTP_MASK; + LPUART->CTRL |= LPUART_WakeUpMethod; +} + +/** + * @brief Enables or disables LPUART Wakeup in STOP2 mode. + * @param Cmd new state of the LPUART Wakeup in STOP2 mode. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableWakeUpStop(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */ + LPUART->CTRL |= CTRL_WUSTP_SET; + } + else + { + /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */ + LPUART->CTRL &= CTRL_WUSTP_RESET; + } +} + +/** + * @brief Selects the LPUART Sampling method. + * @param LPUART_SamplingMethod specifies the LPAURT sampling method. + * This parameter can be one of the following values: + * @arg LPUART_SMPCNT_3B 3 Sample bit + * @arg LPUART_SMPCNT_1B 1 Sample bit + */ +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod)); + + LPUART->CTRL &= CTRL_SMPCNT_MASK; + LPUART->CTRL |= LPUART_SamplingMethod; +} + +/** + * @brief Enables or disables LPUART Loop Back Self-Test. + * @param Cmd new state of the LPUART Loop Back Self-Test. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableLoopBack(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */ + LPUART->CTRL |= CTRL_LOOPBACK_SET; + } + else + { + /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */ + LPUART->CTRL &= CTRL_LOOPBACK_RESET; + } +} + +/** + * @brief Transmits single data through the LPUART peripheral. + * @param Data the data to transmit. + */ +void LPUART_SendData(uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DATA(Data)); + + /* Transmit Data */ + LPUART->DAT = (Data & (uint8_t)0xFF); +} + +/** + * @brief Returns the most recent received data by the LPUART peripheral. + * @return The received data. + */ +uint8_t LPUART_ReceiveData(void) +{ + /* Receive Data */ + return (uint8_t)(LPUART->DAT & (uint8_t)0xFF); +} + +/** + * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode. + * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode. + */ +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData) +{ + LPUART->WUDAT = LPUART_WakeUpData; +} + +/** + * @brief Checks whether the specified LPUART flag is set or not. + * @param LPUART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + * @return The new state of LPUART_FLAG (SET or RESET). + */ +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_FLAG(LPUART_FLAG)); + + if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the LPUART's pending flags. + * @param LPUART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + */ +void LPUART_ClrFlag(uint16_t LPUART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG)); + + LPUART->STS = (uint16_t)LPUART_FLAG; +} + +/** + * @brief Checks whether the specified LPUART interrupt has occurred or not. + * @param LPUART_INT specifies the LPUART interrupt source to check. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @return The new state of LPUART_INT (SET or RESET). + */ +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_GET_INT(LPUART_INT)); + + /* Get the interrupt position */ + itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + itmask &= LPUART->INTEN; + + bitpos = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT){ + bitpos = (bitpos << 0x01); + } + bitpos &= LPUART->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the LPUART's interrupt pending bits. + * @param LPUART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + */ +void LPUART_ClrIntPendingBit(uint16_t LPUART_INT) +{ + uint16_t itmask = 0x00; + /* Check the parameters */ + assert_param(IS_LPUART_CLR_INT(LPUART_INT)); + + itmask = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT) + { + itmask = (itmask << 0x01); + } + LPUART->STS = (uint16_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_opamp.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_opamp.c new file mode 100644 index 0000000000000000000000000000000000000000..3a27c1b4e1167fddb6ce02549990258b3b9ddaba --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_opamp.c @@ -0,0 +1,198 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_opamp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_opamp.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @brief OPAMP driver modules + * @{ + */ + +/** @addtogroup OPAMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the OPAMP peripheral registers to their default reset values. + */ +void OPAMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE); +} +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct) +{ + OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6; + OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2; + OPAMP_InitStruct->HighVolRangeEn = ENABLE; + OPAMP_InitStruct->TimeAutoMuxEn = DISABLE; + OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN; +} +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + if(OPAMPx == OPAMP2) + SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL); + SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK); + if(OPAMP_InitStruct->HighVolRangeEn==ENABLE) + SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK); + else + ClrBit(tmp,OPAMP_CS_RANGE_MASK); + if(OPAMP_InitStruct->TimeAutoMuxEn==ENABLE) + SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK); + else + ClrBit(tmp,OPAMP_CS_TCMEN_MASK); + SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK); + *pCs = tmp; +} +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_EN_MASK); + else + ClrBit(*pCs, OPAMP_CS_EN_MASK); +} + +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK); + *pCs = tmp; +} +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false; +} +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_CALON_MASK); + else + ClrBit(*pCs, OPAMP_CS_CALON_MASK); +} +// Lock see @OPAMP_LOCK +void OPAMP_SetLock(uint32_t Lock) +{ + OPAMP->LOCK = Lock; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_pwr.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_pwr.c new file mode 100644 index 0000000000000000000000000000000000000000..bd89e4d15d6302b6daeb90db65ace297b1525449 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_pwr.c @@ -0,0 +1,584 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_pwr.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_pwr.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @addtogroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of DBKP bit */ +#define CTRL_OFFSET (PWR_OFFSET + 0x00) +#define DBKP_BITN 0x08 +#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4)) + +/* Alias word address of PVDEN bit */ +#define PVDEN_BITN 0x04 +#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of WKUPEN bit */ +#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04) +#define WKUPEN_BITN 0x08 +#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + + +void SetSysClock_MSI(void); +/** + * @} + */ + +/** @addtogroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + */ +void PWR_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param Cmd new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_BackupAccessEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd; +} +/** + * @brief MR voltage selection. + * @param voltage value: 1.0V and 1.1V. + * This parameter can be: MR_1V0 or MR_1V1. + */ +void PWR_MRconfig(uint8_t voltage) +{ + uint32_t tmpreg = 0; + + tmpreg = PWR->CTRL1; + /* Clear MRSEL bits */ + tmpreg &= (~PWR_CTRL1_MRSELMASK); + /* Set voltage*/ + tmpreg |= (uint32_t)(voltage << 9); + PWR->CTRL1 = tmpreg; +} +/** + * @brief Get MR voltage value. + * @param voltage value: 1.0V and 1.1V. + * @return The value of voltage. + */ +uint8_t GetMrVoltage(void) +{ + uint8_t tmp = 0; + + tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);//2bits + return tmp ; +} +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param Cmd new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_PvdEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; //Can not enable the PVD bit + PWR->CTRL2 |= Cmd; + +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V + * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V + * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V + * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V + * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V + * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V + * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V + * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT) + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpregister = PWR->CTRL2; + /* Clear PLS[7:5] bits */ + tmpregister &= (~PWR_CTRL2_PLSMASK); + /* Set PRS[7:5] bits according to PWR_PVDLevel value */ + tmpregister |= PWR_PVDLevel; + /* Store the new value */ + PWR->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param Pin: which PIN select to wakeup. + * This parameter can be one of the following values: + * @arg WAKEUP_PIN0 + * @arg WAKEUP_PIN1 + * @arg WAKEUP_PIN2 + * @param Cmd new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd) +{ + uint32_t Temp = 0; + Temp = PWR->CTRL3; + if(ENABLE==Cmd) + { + Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN)); + Temp |= (WKUP_Pin); + PWR->CTRL3 = Temp; + } + else + { + Temp &= (~(WKUP_Pin)); + PWR->CTRL3 = Temp; + } +} + + + + +/** + * @brief Enters SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + + /* CLEAR SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); + + /* Select SLEEPONEXIT mode entry --------------------------------------------------*/ + if(SLEEPONEXIT == 1) + { + /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } + else if(SLEEPONEXIT == 0) + { + /* Sleep-now */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT); + } + + /* Select SLEEP mode entry --------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + + +/** + * @brief Enters STOP2 mode. + * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction + * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET + */ +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + /* Wait MR Voltage Adjust Complete */ + while((PWR->STS2 &0X2) != 2); + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= RetentionMode; + PWR->CTRL3 = tmpreg; + /* Select the regulator state in STOP2 mode ---------------------------------*/ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set stop2 mode select */ + tmpreg |= PWR_CTRL1_STOP2; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + /*Clear PWR_CTRL3_PBDTSTP2 for BOR always on*/ + tmpreg = PWR->CTRL3; + tmpreg &= (~PWR_CTRL3_PBDTSTP2); + PWR->CTRL3 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + + +/** + * @brief Enters Low power run mode. + * @param + * @arg + * @arg + * @retval None + */ +void PWR_EnterLowPowerRunMode(void) +{ + uint32_t tmpreg = 0; + + SetSysClock_MSI(); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + //config FLASH enter the low power voltage mode + FLASH->AC |= FLASH_AC_LVMEN; + while((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + + _SetLprunSramVoltage(0); + _SetBandGapMode(0); + _SetPvdBorMode(0); + /* Select the regulator state in LPRUN mode ---------------------------------*/ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set lpr to run the main power domain*/ + tmpreg |= PWR_CTRL1_LPREN; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + /*Clear PWR_CTRL3_PBDTLPR for BOR always on*/ + tmpreg = PWR->CTRL3; + tmpreg &= (~PWR_CTRL3_PBDTLPR); + PWR->CTRL3 = tmpreg; + while((PWR->STS2 &PWR_STS2_LPRUNF) != 0);//LPRCNT flag ready +} + +/** + * @brief Enters Low power run mode. + * @retval None + */ +void PWR_ExitLowPowerRunMode(void) +{ + PWR->CTRL1 &= ~PWR_CTRL1_LPREN; + _SetLprunSwitch(3); + while((PWR->STS2 &PWR_STS2_MRF) != PWR_STS2_MRF); + while((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + FLASH->AC &= ~FLASH_AC_LVMEN; //clear LVMREQ + while((FLASH->AC &FLASH_AC_LVMF) != 0); //wait LVE is deasserted by polling the LVMVLD bit + _SetPvdBorMode(1); + _SetBandGapMode(1); + _SetLprunSramVoltage(1); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + _SetLprunSwitch(2); + while((PWR->STS2 &0X2) != 0) // wait MF to be 0 first + { + } + while((PWR->STS2 &0X2) != 2) // wait MF to be 1 then + { + } +} + +/** + * @brief Enters LP_SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + PWR_EnterLowPowerRunMode(); + PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry); +} + + /** + * @brief Enters STANDBY mode. + * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction + * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention + * @retval None + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret) +{ + uint32_t tmpreg; + /* Clear Wake-up flag */ + PWR->STSCLR |= PWR_STSCLR_CLRWKUP0; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP1; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP2; + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= Sam2Ret; + PWR->CTRL3 = tmpreg; + + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Select STANDBY mode */ + tmpreg |= PWR_CTRL1_STANDBY; + PWR->CTRL1 = tmpreg; + /*Clear PWR_CTRL3_PBDTSTBY for BOR always on*/ + tmpreg = PWR->CTRL3; + tmpreg &= (~PWR_CTRL3_PBDTSTBY); + PWR->CTRL3 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Select STANDBY mode entry --------------------------------------------------*/ + if(PWR_STANDBYEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_WKUP0_FLAG/PWR_WKUP1_FLAG/PWR_WKUP2_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + * @arg PWR_LPRUN_FLAG: low power work flag + * @arg PWR_MR_FLAG: MR work statue flag + * @arg PWR_PVDO_FLAG: PVD output flag + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + if(STS == 1) + { + if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + } + else + { + if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->STSCLR |= PWR_FLAG ; +} + + +/** + * @brief set system clock with MSI. + * @param void. + */ +void SetSysClock_MSI(void) +{ + RCC_DeInit(); + + if(RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD)) + { + /* Enable MSI and Config Clock */ + RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M); + /* Waits for MSI start-up */ + while(SUCCESS != RCC_WaitMsiStable()); + } + + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN); + + /* Select MSI as system clock source */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI); + + /* Wait till MSI is used as system clock source */ + while (RCC_GetSysclkSrc() != 0x00) + { + } + + /* Flash 0 wait state */ + //FLASH_SetLatency(FLASH_LATENCY_0); + + /* HCLK = SYSCLK */ + RCC_ConfigHclk(RCC_SYSCLK_DIV1); + + /* PCLK2 = HCLK */ + RCC_ConfigPclk2(RCC_HCLK_DIV1); + + /* PCLK1 = HCLK */ + RCC_ConfigPclk1(RCC_HCLK_DIV1); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rcc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rcc.c new file mode 100644 index 0000000000000000000000000000000000000000..934cd9bed64c3fea34b60e0c67db6d19b91ab5a9 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rcc.c @@ -0,0 +1,1952 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_rcc.c + * @author Nations + * @version v1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @addtogroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of HSIEN bit */ +#define CTRL_OFFSET (RCC_OFFSET + 0x00) +#define HSIEN_BITN 0x00 +#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4)) + +/* Alias word address of PLLEN bit */ +#define PLLEN_BITN 0x18 +#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4)) + +/* Alias word address of CLKSSEN bit */ +#define CLKSSEN_BITN 0x13 +#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4)) + +/* --- CFG Register ---*/ + +/* Alias word address of USBPRES bit */ +#define CFG_OFFSET (RCC_OFFSET + 0x04) + +#define USBPRES_BITN 0x16 +#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4)) + +#define USBPRE_Bit1Number 0x17 +#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4)) + +/* --- CLKINT Register ---*/ + +#define CLKINT_OFFSET (RCC_OFFSET + 0x08) + +/* Alias word address of LSIRDIF bit */ +#define LSIRDIF_BITN 0x00 +#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4)) + +/* --- LDCTRL Register ---*/ + +/* Alias word address of LSECLKSSEN bit */ +#define LSECLKSSEN_BITN 0x03 +#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4)) + +/* Alias word address of RTCEN bit */ +#define LDCTRL_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BITN 0x0F +#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4)) + +/* Alias word address of LDSFTRST bit */ +#define LDSFTRST_BITN 0x10 +#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of LSIEN bit */ +#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24) +#define LSIEN_BITNUMBER 0x00 +#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4)) + +/* Alias word address of MSIEN bit */ +#define MSIEN_BITNUMBER 0x02 +#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF) +#define CTRL_HSEBP_SET ((uint32_t)0x00040000) +#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF) +#define CTRL_HSEEN_SET ((uint32_t)0x00010000) +#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83) +#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE) +#define CTRL_HSIEN_SET ((uint32_t)0x00000001) + +/* CTRLSTS register bit mask */ +#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF) +#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB) +#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004) + +#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F) +#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */ + +/* CFG register bit mask */ +#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF) + +#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000) +#define CFG_PLLSRC_MASK ((uint32_t)0x00010000) +#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000) +#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C) +#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC) +#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F) +#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0) +#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF) +#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700) +#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF) +#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800) + +/* CFG2 register bit mask */ +#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000) +#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF) +#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000) +#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF) +#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000) +#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF) +#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000) +#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF) +#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0) +#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F) +#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F) +#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0) + +/* CFG3 register bit mask */ +#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) + +/* CTRLSTS register bit mask */ +#define CSR_RMRSTF_SET ((uint32_t)0x01000000) +#define CSR_RMVF_Reset ((uint32_t)0xfeffffff) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CLKINT register(Bits[31:0]) base address */ +#define CLKINT_ADDR ((uint32_t)0x40021008) + +/* LDCTRL register base address */ +#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET) + +/* RDCTRL register bit mask */ +#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007) +#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018) + +/* PLLHSIPRE register bit mask */ +#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001) +#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002) + +#define LSE_TRIMR_ADDR ((uint32_t)0x40001808) + +#define LSE_GM_MASK_VALUE (0x1FF) +#define LSE_GM_MAX_VALUE (0x1FF) +#define LSE_GM_DEFAULT_VALUE (0x1FF) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Variables + * @{ + */ + +static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32}; +static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256}; +static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +/** + * @} + */ + +/** @addtogroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + */ +void RCC_DeInit(void) +{ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFE; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */ + RCC->CFG &= (uint32_t)0xF700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_DISABLE HSE oscillator OFF + * @arg RCC_HSE_ENABLE HSE oscillator ON + * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +void RCC_ConfigHse(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CTRL &= CTRL_HSEEN_RESET; + /* Reset HSEBYP bit */ + RCC->CTRL &= CTRL_HSEBP_RESET; + /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */ + switch (RCC_HSE) + { + case RCC_HSE_ENABLE: + /* Set HSEEN bit */ + RCC->CTRL |= CTRL_HSEEN_SET; + break; + + case RCC_HSE_BYPASS: + /* Set HSEBYP and HSEEN bits */ + RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitHseStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF); + StartUpCounter++; + } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Configures the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSI specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_DISABLE HSI oscillator OFF + * @arg RCC_HSI_ENABLE HSI oscillator ON + */ +void RCC_ConfigHsi(uint32_t RCC_HSI) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_HSI)); + /* Reset HSIEN bit */ + RCC->CTRL &= CTRL_HSIEN_RESET; + /* Configure HSI */ + switch (RCC_HSI) + { + case RCC_HSI_ENABLE: + /* Set HSIEN bit */ + RCC->CTRL |= CTRL_HSIEN_SET; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSI oscillator is stable and ready to use + * - ERROR: HSI oscillator not yet ready + */ +ErrorStatus RCC_WaitHsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSIStatus = RESET; + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF); + StartUpCounter++; + } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue)); + tmpregister = RCC->CTRL; + /* Clear HSITRIM[4:0] bits */ + tmpregister &= CTRL_HSITRIM_MASK; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpregister |= (uint32_t)HSICalibrationValue << 2; + /* Store the new value */ + RCC->CTRL = tmpregister; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableHsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the Multi Speed oscillator (MSI). + * @param RCC_MSI specifies the new state of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_DISABLE MSI oscillator OFF + * @arg RCC_MSI_ENABLE MSI oscillator ON + * @param RCC_MSI_Range specifies the clock of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_RANGE_100K 100KHz + * @arg RCC_MSI_RANGE_200K 200KHz + * @arg RCC_MSI_RANGE_400K 400KHz + * @arg RCC_MSI_RANGE_800K 800KHz + * @arg RCC_MSI_RANGE_1M 1MHz + * @arg RCC_MSI_RANGE_2M 2MHz + * @arg RCC_MSI_RANGE_4M 4MHz + */ +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range) +{ + /* Check the parameters */ + assert_param(IS_RCC_MSI(RCC_MSI)); + assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range)); + /* Set MSIRANGE[2:0] bit */ + RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK; + RCC->CTRLSTS |= RCC_MSI_Range; + /* Configure MSI */ + switch (RCC_MSI) + { + case RCC_MSI_ENABLE: + /* Set MSIEN bit */ + RCC->CTRLSTS |= CTRLSTS_MSIEN_SET; + break; + case RCC_MSI_DISABLE: + /* Reset MSIEN bit */ + RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET; + break; + default: + break; + } +} + +/** + * @brief Waits for MSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: MSI oscillator is stable and ready to use + * - ERROR: MSI oscillator not yet ready + */ +ErrorStatus RCC_WaitMsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus MSIStatus = RESET; + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD); + StartUpCounter++; + } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Multi Speed oscillator (MSI) calibration value. + * @param MSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0xFF. + */ +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue)); + tmpregister = RCC->CTRLSTS; + /* Clear MSITRIM[7:0] bits */ + tmpregister &= CTRLSTS_MSITRIM_MASK; + /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */ + tmpregister |= (uint32_t)MSICalibrationValue << 15; + /* Store the new value */ + RCC->CTRLSTS = tmpregister; +} + +/** + * @brief Enables or disables the Multi Speed oscillator (MSI). + * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableMsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource specifies the PLL entry clock source. + * this parameter can be one of the following values: + * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul specifies the PLL multiplication factor. + * this parameter can be RCC_PLLMul_x where x:[2,32] + * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source. + * this parameter can be one of the following values: + * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry + * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry + */ +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK) +{ + uint32_t tmpregister = 0; + uint32_t pllhsipreregister = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SRC(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK)); + + tmpregister = RCC->CFG; + pllhsipreregister = RCC->PLLHSIPRE; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */ + tmpregister &= CFG_PLL_MASK; + /* Clear PLLHSIPRE, PLLSRCDIV bits */ + pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK)); + /* Set the PLL configuration bits */ + if((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2)) + { + tmpregister |= RCC_PLLMul; + pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK; + } + /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */ + else + { + tmpregister |= RCC_PLLSource | RCC_PLLMul; + pllhsipreregister |= RCC_PLLDIVCLK; + } + /* Store the new value */ + RCC->CFG = tmpregister; + RCC->PLLHSIPRE = pllhsipreregister; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnablePll(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock + * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock + */ +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource)); + tmpregister = RCC->CFG; + /* Clear SW[1:0] bits */ + tmpregister &= CFG_SCLKSW_MASK; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpregister |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Returns the clock source used as system clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: MSI used as system clock + * - 0x04: HSI used as system clock + * - 0x08: HSE used as system clock + * - 0x0C: PLL used as system clock + */ +uint8_t RCC_GetSysclkSrc(void) +{ + return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK + * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512 + */ +void RCC_ConfigHclk(uint32_t RCC_SYSCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK)); + tmpregister = RCC->CFG; + /* Clear HPRE[3:0] bits */ + tmpregister &= CFG_AHBPRES_RESET_MASK; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpregister |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB1 clock = HCLK + * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16 + */ +void RCC_ConfigPclk1(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE1[2:0] bits */ + tmpregister &= CFG_APB1PRES_RESET_MASK; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB2 clock = HCLK + * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16 + */ +void RCC_ConfigPclk2(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE2[2:0] bits */ + tmpregister &= CFG_APB2PRES_RESET_MASK; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RccInt specifies the RCC interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF BOR interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * + * @param Cmd new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_INT(RccInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8); + } + else + { + /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8)); + } +} + +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source + */ +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource)); + + *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource; + *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1; +} + +/** + * @brief Configures the TIM1/8 clock (TIM1/8CLK). + * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM18CLK_SRC_TIM18CLK + * @arg RCC_TIM18CLK_SRC_SYSCLK + */ +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource)); + + tmpregister = RCC->CFG2; + /* Clear TIMCLK_SEL bits */ + tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK; + /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */ + tmpregister |= RCC_TIM18CLKSource; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the RNGCCLK prescaler. + * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler. + * This parameter can be one of the following values: + * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1 + * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2 + * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3 + * ... + * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31 + * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32 + */ +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear RNGCPRE[3:0] bits */ + tmpregister &= CFG2_RNGCPRES_RESET_MASK; + /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */ + tmpregister |= RCC_RNGCCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCx 1M clock (ADC1MCLK). + * @param RCC_ADC1MCLKSource specifies the ADC1M clock source. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_SRC_HSI + * @arg RCC_ADC1MCLK_SRC_HSE + * + * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1 + * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2 + * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3 + * ... + * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31 + * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32 + */ +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource)); + assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */ + tmpregister &= CFG2_ADC1MSEL_RESET_MASK; + tmpregister &= CFG2_ADC1MPRES_RESET_MASK; + /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */ + tmpregister |= RCC_ADC1MCLKSource; + /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */ + tmpregister |= RCC_ADC1MPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK. + * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + * + * @param Cmd specifies the ADCPLLCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable ADCPLLCLK + * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + */ +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + tmpregister = RCC->CFG2; + /* Clear ADCPLLPRES[4:0] bits */ + tmpregister &= CFG2_ADCPLLPRES_RESET_MASK; + + if (Cmd != DISABLE) + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + } + else + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + tmpregister &= RCC_ADCPLLCLK_DISABLE; + } + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + */ +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADCHPRE[3:0] bits */ + tmpregister &= CFG2_ADCHPRES_RESET_MASK; + /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_ADCHCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the TRNG 1M clock (TRNG1MCLK). + * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_SRC_HSI + * @arg RCC_TRNG1MCLK_SRC_HSE + * + * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2 + * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4 + * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6 + * ... + * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60 + * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62 + */ +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource)); + assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler)); + + tmpregister = RCC->CFG3; + /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */ + tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK; + tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK; + /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */ + tmpregister |= RCC_TRNG1MCLKSource; + /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */ + tmpregister |= RCC_TRNG1MPrescaler; + + /* Store the new value */ + RCC->CFG3 = tmpregister; +} + +/** + * @brief Enable/disable TRNG clock (TRNGCLK). + * @param Cmd specifies the TRNGCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable TRNGCLK + * @arg DISABLE disable TRNGCLK + */ +void RCC_EnableTrng1mClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE; + } + else + { + RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE; + } +} + +/** + * @brief Configures the UCDR clock. + * @param RCC_UCDR300MSource specifies the UCDR clock source. + * This parameter can be on of the following values: + * @arg RCC_UCDR300M_SRC_OSC300M + * @arg RCC_UCDR300M_SRC_PLLVCO + * + * @param Cmd enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable UCDR + * @arg DISABLE disable UCDR + */ +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + tmpregister = RCC->CFG3; + /* Clear UCDR300MSEL bits */ + tmpregister &= RCC_UCDR300MSource_MASK; + /* Set UCDR300MSEL bits */ + tmpregister |= RCC_UCDR300MSource; + + /* Store the new value */ + RCC->CFG3 = tmpregister; + + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_UCDR_ENABLE; + } + else + { + RCC->CFG3 &= RCC_UCDR_DISABLE; + } +} + +/** + * @brief Configures the USB Crystal Mode. + * @param RCC_USBXTALESSMode specifies the USB Crystal Mode. + * This parameter can be one of the following values: + * @arg RCC_USBXTALESS_MODE USB work in crystal mode + * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode + */ +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode)); + + /* Clear the USB Crystal Mode bit */ + RCC->CFG3 &= RCC_USBXTALESSMode_MASK; + + /* Select the USB Crystal Mode */ + RCC->CFG3 |= RCC_USBXTALESSMode; +} + +/** + * @brief Enables or disables the RET peripheral clock. + * @param RCC_RETPeriph specifies the RET peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM + * @arg RCC_RET_PERIPH_LPUART + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->RDCTRL |= RCC_RETPeriph; + } + else + { + RCC->RDCTRL &= ~RCC_RETPeriph; + } +} + +/** + * @brief Forces or releases RET peripheral reset. + * @param RCC_RETPeriph specifies the RET peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM. + * RCC_RET_PERIPH_LPUART. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->RDCTRL |= (RCC_RETPeriph << 4); + } + else + { + RCC->RDCTRL &= ~(RCC_RETPeriph << 4); + } +} + +/** + * @brief Configures the LPTIM clock (LPTIMCLK). + * @param RCC_LPTIMCLKSource specifies the LPTIM clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + * @note When switching from comparator1/2 to other clock sources, + * it is suggested to disable comparators first. + */ +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource)); + //PWR DBP set 1 + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Clear the LPTIM clock source */ + RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK; + + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPTIMCLKSource; +} + +/** + * @brief Returns the clock source used as LPTIM clock (LPTIMCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + */ +uint32_t RCC_GetLPTIMClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK)); +} + +/** + * @brief Configures the LPUART clock (LPUARTCLK). + * @param RCC_LPUARTCLKSource specifies the LPUART clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock + */ +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource)); + + /* Clear the LPUART clock source */ + RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK; + + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPUARTCLKSource; +} + +/** + * @brief Returns the clock source used as LPUART clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock + */ +uint32_t RCC_GetLPUARTClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK)); +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error interrupts. + * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt + * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt + * + * @param Cmd new state of the specified SRAM1/2 parity error interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORINT(SramErrorInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS |= SramErrorInt; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS &= (~SramErrorInt); + } +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error reset. + * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset + * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset + * + * @param Cmd new state of the specified SRAM1/2 parity error reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS |= SramErrorReset; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS &= (~SramErrorReset); + } +} + +/** + * @brief Clears the specified SRAM1/2 parity error flag. + * @param SramErrorReset specifies the SRAM1/2 parity error flag. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag + * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag + */ +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag)); + RCC->SRAM_CTRLSTS |= SramErrorflag; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) Xtal bias. + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x0~0x1FF + */ +void LSE_XtalConfig(uint16_t LSE_Trim) +{ + uint32_t tmpregister = 0; + tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR; + //clear lse trim[8:0] + tmpregister &= (~(LSE_GM_MASK_VALUE)); + (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE); + tmpregister |= LSE_Trim; + *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_DISABLE LSE oscillator OFF + * @arg RCC_LSE_ENABLE LSE oscillator ON + * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x00~0x1FF + */ +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim) +{ + uint32_t LDCTRL_Value; + uint32_t i=0; + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* PWR DBP set 1 Enable PWR Clock */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE*/ + LDCTRL_Value = *(__IO uint32_t*)LDCTRL_ADDR; + LDCTRL_Value &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN)); + /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ENABLE: + /* Set LSEON bit */ + LDCTRL_Value |= RCC_LSE_ENABLE; + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + LSE_XtalConfig(LSE_Trim); + break; + case RCC_LSE_DISABLE: + /* Reset LSEON bit */ + LDCTRL_Value &= (~RCC_LSE_DISABLE); + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + /*Delay for 3 LSE Clock Wait for LSERD bit Reset*/ + for(i=0;i<0x7FF;i++); + break; + case RCC_LSE_BYPASS: + /* Set LSEBYP and LSEON bits */ + LDCTRL_Value |= RCC_LSE_BYPASS; + *(__IO uint32_t*)LDCTRL_ADDR = LDCTRL_Value; + break; + default: + break; + } +} + + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock + */ +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource)); + + /* Clear the RTC clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL); + + /* Select the RTC clock source */ + RCC->LDCTRL |= RCC_RTCCLKSource; +} + +/** + * @brief Returns the clock source used as RTC clock (RTCCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK) + */ +uint32_t RCC_GetRTCClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL)); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function. + * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRtcClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the LSX clock (for TSC). + * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock + * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock + */ +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource)); + + /* Clear the LSX clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL); + + /* Select the LSX clock source */ + RCC->LDCTRL |= RCC_LSXCLKSource; +} + +/** + * @brief Returns the clock source used as LSX clock (for TSC). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC) + * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC) + */ +uint32_t RCC_GetLSXClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL)); +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks) +{ + uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0; + uint8_t msi_clk = 0; + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFG & CFG_PLLMULFCT_MASK; + pllsource = RCC->CFG & CFG_PLLSRC_MASK; + /* Get MSI clock --------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + pllclk = (HSI_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSI_VALUE * pllmull; + } + + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + pllclk = (HSE_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSE_VALUE * pllmull; + } + } + + /* PLL Div clock */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET) + { /* PLL clock divided by 2 */ + pllclk = (pllclk >> 1); + } + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFG & CFG_SCLKSTS_MASK; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + RCC_Clocks->SysclkFreq = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + RCC_Clocks->SysclkFreq = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + RCC_Clocks->SysclkFreq = pllclk; + break; + + default: + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFG & CFG_AHBPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_ApbAhbPresTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFG & CFG_APB1PRES_SET_MASK; + tmp = tmp >> 8; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFG & CFG_APB2PRES_SET_MASK; + tmp = tmp >> 11; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc; + + /* Get ADCHCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK; + presc = s_AdcHclkPresTable[tmp]; + /* ADCHCLK clock frequency */ + RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc; + /* Get ADCPLLCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5 + /* ADCPLLCLK clock frequency */ + RCC_Clocks->AdcPllClkFreq = pllclk / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_DMA + * @arg RCC_AHB_PERIPH_SRAM + * @arg RCC_AHB_PERIPH_FLITF + * @arg RCC_AHB_PERIPH_CRC + * @arg RCC_AHB_PERIPH_RNGC + * @arg RCC_AHB_PERIPH_SAC + * @arg RCC_AHB_PERIPH_ADC + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->AHBPCLKEN |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCLKEN &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PCLKEN |= RCC_APB2Periph; + } + else + { + RCC->APB2PCLKEN &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PCLKEN |= RCC_APB1Periph; + } + else + { + RCC->APB1PCLKEN &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_ADC. + * RCC_AHB_PERIPH_SAC. + * RCC_AHB_PERIPH_RNGC. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->AHBPRST |= RCC_AHBPeriph; + } + else + { + RCC->AHBPRST &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PRST |= RCC_APB2Periph; + } + else + { + RCC->APB2PRST &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PRST |= RCC_APB1Periph; + } + else + { + RCC->APB1PRST &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the LowPower domain reset. + * @param Cmd new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLowPowerReset(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param Cmd new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the LSE Clock Security System. + * @param Cmd new state of the LSE Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Get LSE Clock Security System failure status. + * @return LSE Clock Security System failure status (SET or RESET). + */ +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void) +{ + FlagStatus bitstatus = RESET; + /* Check the status of LSE Clock Security System */ + if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return LSE Clock Security System status */ + return bitstatus; +} + +/** + * @brief Configures the MCO PLL clock prescaler. + * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source + * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50% + */ +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler)); + + tmpregister = RCC->CFG; + /* Clear MCOPRE[3:0] bits */ + tmpregister &= ((uint32_t)0x0FFFFFFF); + /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_MCOCLKPrescaler; + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO specifies the clock source to output. + * + * this parameter can be one of the following values: + * @arg RCC_MCO_NOCLK No clock selected + * @arg RCC_MCO_LSI LSI oscillator clock selected + * @arg RCC_MCO_LSE LSE oscillator clock selected + * @arg RCC_MCO_MSI MSI oscillator clock selected + * @arg RCC_MCO_SYSCLK System clock selected + * @arg RCC_MCO_HSI HSI oscillator clock selected + * @arg RCC_MCO_HSE HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK PLL clock selected + * + */ +void RCC_ConfigMco(uint8_t RCC_MCO) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + tmpregister = RCC->CFG; + /* Clear MCO[2:0] bits */ + tmpregister &= ((uint32_t)0xF8FFFFFF); + /* Set MCO[2:0] bits according to RCC_MCO value */ + tmpregister |= ((uint32_t)(RCC_MCO << 24)); + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG specifies the flag to check. + * + * this parameter can be one of the following values: + * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready + * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready + * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready + * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready + * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status + * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag + * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag + * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag + * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag + * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset + * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset + * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset + * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset + * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset + * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset + * + * @return The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = RCC->CTRL; + } + else if (tmp == 2) /* The flag to check is in BDCTRL register */ + { + statusreg = RCC->LDCTRL; + } + else /* The flag to check is in CTRLSTS register */ + { + statusreg = RCC->CTRLSTS; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST, + * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, + * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +void RCC_ClrFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CTRLSTS |= CSR_RMRSTF_SET; + /* RMVF bit should be reset */ + RCC->CTRLSTS &= CSR_RMVF_Reset; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RccInt specifies the RCC interrupt source to check. + * + * this parameter can be one of the following values: + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * @arg RCC_INT_CLKSSIF Clock Security System interrupt + * + * @return The new state of RccInt (SET or RESET). + */ +INTStatus RCC_GetIntStatus(uint8_t RccInt) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_INT(RccInt)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT & RccInt) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RccInt status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RccInt specifies the interrupt pending bit to clear. + * + * this parameter can be any combination of the + * following values: + * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag + * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag + * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag + * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag + * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag + * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag + * @arg RCC_CLR_BORIF Clear BOR interrupt flag + * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag + */ +void RCC_ClrIntPendingBit(uint32_t RccClrInt) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLR_INTF(RccClrInt)); + /* Software set this bit to clear INT flag. */ + RCC->CLKINT |= RccClrInt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rtc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..62856f8e84baaf007aa3216909157431aba1242c --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_rtc.c @@ -0,0 +1,2332 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_rtc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_rtc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF) +#define RTC_FLAGS_MASK \ + ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \ + | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \ + | RTC_FLAG_SHOPF)) + +#define INITMODE_TIMEOUT ((uint32_t)0x00002000) +#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000) +#define RECALPF_TIMEOUT ((uint32_t)0x00001000) +#define SHPF_TIMEOUT ((uint32_t)0x00002000) + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** @addtogroup RTC_Private_Functions + * @{ + */ + +/** @addtogroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WRP. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSYF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSYF clear and RSYF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TSH, DAT and CTRL registers */ + RTC->TSH = (uint32_t)0x00000000; + RTC->DATE = (uint32_t)0x00002101; + + /* Reset All CTRL bits except CTRL[2:0] */ + RTC->CTRL &= (uint32_t)0x00000007; + + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CTRL register bits */ + RTC->CTRL &= (uint32_t)0x00000000; + RTC->WKUPT = (uint32_t)0x0000FFFF; + RTC->PRE = (uint32_t)0x007F00FF; + RTC->ALARMA = (uint32_t)0x00000000; + RTC->ALARMB = (uint32_t)0x00000000; + RTC->SCTRL = (uint32_t)0x00000000; + RTC->CALIB = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + RTC->ALRMBSS = (uint32_t)0x00000000; + + /* Reset INTSTS register and exit initialization mode */ + RTC->INITSTS = (uint32_t)0x00000000; + + RTC->OPT = (uint32_t)0x00000000; + RTC->TSCWKUPCTRL = (uint32_t)0x00000008; + RTC->TSCWKUPCNT = (uint32_t)0x000002FE; + + /* Wait till the RTC RSYF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct pointer to a RTC_InitType structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t i =0; + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CTRL HFMT Bit */ + RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT)); + /* Set RTC_CTRL register */ + RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + /* Configure the RTC PRE */ + RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Delay for the RTC prescale effect */ + for(i=0;i<0x2FF;i++); + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct pointer to a RTC_InitType structure which will be + * initialized. + */ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_INITSTS[13:8]. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param Cmd new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableWriteProtection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->INITSTS & RTC_INITSTS_INITF; + initcounter++; + } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSYF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TSH and RTC_DATE shadow registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear RSYF flag */ + RTC->INITSTS &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF; + synchrocounter++; + } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param Cmd new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (Cmd != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CTRL |= RTC_CTRL_REFCLKEN; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CTRL &= ~RTC_CTRL_REFCLKEN; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param Cmd new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableBypassShadow(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Set the BYPS bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS; + } + else + { + /* Reset the BYPS bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains + * the time configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds))); + } + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16)); + } + else + { + tmpregister = + (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16)); + } + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TSH register */ + RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(status!=ERROR) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be + * initialized. + */ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->H12 = RTC_AM_H12; + RTC_TimeStruct->Hours = 0; + RTC_TimeStruct->Minutes = 0; + RTC_TimeStruct->Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will + * contain the returned current time configuration. + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes); + RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @return RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpregister = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpregister = (uint32_t)(RTC->SUBS); + + return (tmpregister); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that contains + * the date configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year))); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month); + assert_param(IS_RTC_MONTH(tmpregister)); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date); + assert_param(IS_RTC_DATE(tmpregister)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DATE register */ + RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(ERROR!=status) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct pointer to a RTC_DateType structure which will be + * initialized. + */ +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Date = 1; + RTC_DateStruct->Month = RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that will + * contain the returned current date configuration. + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year); + RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month); + RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date); + } +} + +/** + * @} + */ + +/** @addtogroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_EnableAlarm(DISABLE)). + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that + * contains the alarm configuration parameters. + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode)); + + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue)); + } + else + { + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue)); + } + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + assert_param(IS_RTC_12HOUR(tmpregister)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister)); + } + else + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = + (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds)) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_A_ALARM) + { + RTC->ALARMA = (uint32_t)tmpregister; + } + else + { + RTC->ALARMB = (uint32_t)tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which + * will be initialized. + */ +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12; + RTC_AlarmStruct->AlarmTime.Hours = 0; + RTC_AlarmStruct->AlarmTime.Minutes = 0; + RTC_AlarmStruct->AlarmTime.Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + RTC_AlarmStruct->DateWeekValue = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will + * contains the output alarm configuration values. + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)(RTC->ALARMA); + } + else + { + tmpregister = (uint32_t)(RTC->ALARMB); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16); + RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8); + RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU)); + RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16); + RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24); + RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL); + RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL); + + if (RTC_Format == RTC_FORMAT_BIN) + { + RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes); + RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds); + RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param Cmd new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm state */ + if (Cmd != DISABLE) + { + RTC->CTRL |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8); + alarmcounter++; + } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask.* + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmSubSecondValue specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared. + * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared. + * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared. + * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared. + * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared. + * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared. + * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared. + * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared. + * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared. + * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared. + * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match + * to activate alarm. + */ +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + + if (RTC_Alarm == RTC_A_ALARM) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASS = tmpregister; + } + else + { + /* Configure the Alarm B SubSecond register */ + RTC->ALRMBSS = tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @return RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpregister = 0; + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV); + } + else + { + tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV); + } + + return (tmpregister); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpClock Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16. + * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8. + * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4. + * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2. + * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE. + * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE. + */ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the Wakeup Timer clock source bits in CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL; + + /* Configure the clock source */ + RTC->CTRL |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp. + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpCounter specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WKUPT = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @return The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param Cmd new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + */ +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN; + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### Daylight Saving configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaving the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time). + * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time). + * @param RTC_StoreOperation Specifies the value to be written in the BCK bit + * in CTRL register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset. + * @arg RTC_STORE_OPERATION_SET BCK Bit Set. + */ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP); + /* Clear the SU1H and AD1H bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @return RTC Day Light Saving stored operation. + * - RTC_STORE_OPERATION_RESET + * - RTC_STORE_OPERATION_SET + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CTRL & RTC_CTRL_BAKP); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + + + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_DIS No output selected + * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output. + * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output. + * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output. + * @param RTC_OutputPolarity Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OUTPOL_HIGH The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + * @arg RTC_OUTPOL_LOW The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + */ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_MODE(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL); + + /* Configure the output selection and polarity */ + RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions + * @brief Coarse and Smooth Calibrations configuration functions + * +@verbatim + =============================================================================== + ##### Coarse and Smooth Calibrations configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative + * pin. + * @param Cmd new state of the coarse calibration Output. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableCalibOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_COEN; + } + else + { + /* Disable the RTC clock output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz. + * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz. + */ +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /*clear flags before config*/ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL); + + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s. + * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s. + * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured + */ +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses + | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the + * falling edge of the related pin. + * @param Cmd new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN)); + + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN); + } + else + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format + * @arg RTC_FORMAT_BCD BCD data format + * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will + * contains the TimeStamp date values. + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours); + RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes); + RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month); + RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date); + RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @return RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSS); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group11 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in + * Push Pull mode. + */ +void RTC_ConfigOutputType(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE); + RTC->OPT |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar. + * @arg RTC_SHIFT_ADD1S_DISABLE No effect. + * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured + */ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET) + { + /* Configure the Shift settings */ + RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) + using the RTC_SetAlarm() and RTC_EnableAlarm() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 20 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (+) Configure the RTC to generate the RTC wakeup timer event using the + RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is + required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC time-stamp event using the + RTC_EnableTimeStamp() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt mask. + * @arg RTC_INT_WUT WakeUp Timer interrupt mask. + * @arg RTC_INT_ALRB Alarm B interrupt mask. + * @arg RTC_INT_ALRA Alarm A interrupt mask. + * @param Cmd new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_INT(RTC_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN); + } + else + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN); + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECPF RECALPF event flag. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_INITF Initialization mode flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + * @arg RTC_FLAG_INITSF Registers Configured flag. + * @arg RTC_FLAG_SHOPF Shift operation pending flag. + * @arg RTC_FLAG_WTWF WakeUp Timer Write flag. + * @arg RTC_FLAG_ALBWF Alarm B Write flag. + * @arg RTC_FLAG_ALAWF Alarm A write flag. + * @return The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpregister & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG specifies the RTC flag to clear. + * This parameter can be any combination of the following values:. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + */ +void RTC_ClrFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_INT specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_INT_TS Time Stamp interrupt. + * @arg RTC_INT_WUT WakeUp Timer interrupt. + * @arg RTC_INT_ALRB Alarm B interrupt. + * @arg RTC_INT_ALRA Alarm A interrupt. + * @return The new state of RTC_INT (SET or RESET). + */ +INTStatus RTC_GetITStatus(uint32_t RTC_INT) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0, enablestatus = 0; + uint8_t tamperEnable = 0; + /* Check the parameters */ + assert_param(IS_RTC_GET_INT(RTC_INT)); + + /* Get the Interrupt enable Status */ + if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3)) + { + tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16); + if (tamperEnable > 0) + { + enablestatus = SET; + } + + } + else + { + enablestatus = (uint32_t)((RTC->CTRL & RTC_INT)); + + } + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_INT specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt + * @arg RTC_INT_WUT WakeUp Timer interrupt + * @arg RTC_INT_ALRB Alarm B interrupt + * @arg RTC_INT_ALRA Alarm A interrupt + */ +void RTC_ClrIntPendingBit(uint32_t RTC_INT) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_INT(RTC_INT)); + + /* Get the RTC_INITSTS Interrupt pending bits mask */ + tmpregister = (uint32_t)(RTC_INT >> 4); + + /* Clear the interrupt pending bits in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted. + * @return Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted. + * @return Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} +/** + * @brief Enable wakeup tsc functionand wakeup by the set time + * @param count wakeup time. + */ +void RTC_EnableWakeUpTsc(uint32_t count) +{ + // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1 + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // enter config wakeup cnt mode + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF; + // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI + RTC->TSCWKUPCNT = count; + // exit config wakeup cnt mode + RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF); + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // TSC wakeup enable + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN; +} + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @arg RTC_Tamper_3: Select Tamper 3. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + if (RTC_Tamper == RTC_TAMPER_3) + { + RTC_TamperTrigger <<= 5; + } + else if (RTC_Tamper == RTC_TAMPER_2) + { + RTC_TamperTrigger <<= 3; + } + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger); + +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level. + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle. + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSEN bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS; + } +} + +/** + * @brief Enables or Disables the TAMPTS. + * @param NewState: new state of TAMPTS. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperTAMPTSCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER1_INT: Select Tamper 1. + * @arg RTC_TAMPER2_INT: Select Tamper 2. + * @arg RTC_TAMPER3_INT: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(TAMPxIE)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)TAMPxIE; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~TAMPxIE; + } +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_spi.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9c8c400023f0b3c01a964d20862387e9f9f46f58 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_spi.c @@ -0,0 +1,853 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_spi.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_spi.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @addtogroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Defines + * @{ + */ + +/* SPI SPIEN mask */ +#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040) +#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF) + +/* I2S I2SEN mask */ +#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400) +#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF) + +/* SPI CRCNEXT mask */ +#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000) +#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004) +#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0x3040) +#define I2SCFG_CLR_MASK ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xF7FF) +#define I2S_MODE_ENABLE ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S1_CLKSRC ((uint32_t)(0x00020000)) +#define I2S2_CLKSRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @addtogroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx where x can be 1, 2 to select the SPI peripheral. + */ +void SPI_I2S_DeInit(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE); + } + +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_InitStruct pointer to a SPI_InitType structure that + * contains the configuration information for the specified SPI peripheral. + */ +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct) +{ + uint16_t tmpregister = 0; + + /* check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen)); + assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL)); + assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + + /*---------------------------- SPIx CTRL1 Configuration ------------------------*/ + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */ + /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */ + /* Set LSBFirst bit according to FirstBit value */ + /* Set BR bits according to BaudRatePres value */ + /* Set CPOL bit according to CLKPOL value */ + /* Set CPHA bit according to CLKPHA value */ + tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode + | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA + | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit); + /* Write to SPIx CTRL1 */ + SPIx->CTRL1 = tmpregister; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */ + SPIx->I2SCFG &= SPI_MODE_ENABLE; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SPI_InitStruct->CRCPoly; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct pointer to an I2S_InitType structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + */ +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct) +{ + uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksType RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat)); + assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency)); + assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL)); + + /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/ + /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */ + SPIx->I2SCFG &= I2SCFG_CLR_MASK; + SPIx->I2SPREDIV = 0x0002; + + /* Get the I2SCFG register value */ + tmpregister = SPIx->I2SCFG; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if (((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S1 */ + tmp = I2S1_CLKSRC; + } + else + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLKSRC; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SysclkFreq; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPREDIV register the computed value */ + SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpregister |= (uint16_t)( + I2S_MODE_ENABLE + | (uint16_t)(I2S_InitStruct->I2sMode + | (uint16_t)(I2S_InitStruct->Standard + | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL)))); + + /* Write to SPIx I2SCFG */ + SPIx->I2SCFG = tmpregister; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized. + */ +void SPI_InitStruct(SPI_InitType* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; + /* Initialize the CRCPoly member */ + SPI_InitStruct->CRCPoly = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized. + */ +void I2S_InitStruct(I2S_InitType* I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the MCLKEnable member */ + I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE; + + /* Initialize the AudioFrequency member */ + I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT; + + /* Initialize the CLKPOL member */ + I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask + * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask + * @arg SPI_I2S_INT_ERR Error interrupt mask + * @param Cmd new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CTRL2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CTRL2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request + * @param Cmd new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param Data Data to be transmitted. + */ +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Write in the DAT register the data to be sent */ + SPIx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @return The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the data in the DAT register */ + return SPIx->DAT; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_NSSInternalSoft specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSS_HIGH Set NSS pin internally + * @arg SPI_NSS_LOW Reset NSS pin internally + */ +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSS_LOW) + { + /* Set NSS pin internally by software */ + SPIx->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CTRL1 &= SPI_NSS_LOW; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataLen specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit + * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit + */ +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(DataLen)); + /* Clear DFF bit */ + SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS; + /* Set new DFF bit value */ + SPIx->CTRL1 |= DataLen; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + */ +void SPI_TransmitCrcNext(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_CRC specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_TX Selects Tx CRC register + * @arg SPI_CRC_RX Selects Rx CRC register + * @return The selected CRC register value.. + */ +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_RX) + { + /* Get the Tx CRC register */ + crcreg = SPIx->CRCTDAT; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->CRCRDAT; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @return The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPOLY; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataDirection specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction + * @arg SPI_BIDIRECTION_RX Selects Rx receive direction + */ +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_BIDIRECTION(DataDirection)); + if (DataDirection == SPI_BIDIRECTION_TX) + { + /* Set the Tx only mode */ + SPIx->CTRL1 |= SPI_BIDIRECTION_TX; + } + else + { + /* Set the Rx only mode */ + SPIx->CTRL1 &= SPI_BIDIRECTION_RX; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag. + * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag. + * @arg SPI_I2S_BUSY_FLAG Busy flag. + * @arg SPI_I2S_OVER_FLAG Overrun flag. + * @arg SPI_MODERR_FLAG Mode Fault flag. + * @arg SPI_CRCERR_FLAG CRC Error flag. + * @arg I2S_UNDER_FLAG Underrun Error flag. + * @arg I2S_CHSIDE_FLAG Channel Side flag. + * @return The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_FLAG specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STS register (SPI_I2S_GetStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STS register (SPI_I2S_GetStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a + * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI). + */ +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->STS = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt. + * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt. + * @arg SPI_I2S_INT_OVER Overrun interrupt. + * @arg SPI_INT_MODERR Mode Fault interrupt. + * @arg SPI_INT_CRCERR CRC Error interrupt. + * @arg I2S_INT_UNDER Underrun Error interrupt. + * @return The new state of SPI_I2S_IT (SET or RESET). + */ +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable + * the SPI). + */ +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->STS = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tim.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tim.c new file mode 100644 index 0000000000000000000000000000000000000000..6d792168be01b39f94a318047ecdb943215553e1 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tim.c @@ -0,0 +1,3290 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_tim.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_tim.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @addtogroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCTRL_ETR_MASK ((uint16_t)0x00FF) +#define CAPCMPMOD_OFFSET ((uint16_t)0x0018) +#define CAPCMPEN_CCE_SET ((uint16_t)0x0001) +#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004) + +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + */ +void TIM_DeInit(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + + if (TIMx == TIM1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE); + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure that contains the configuration information for the + * specified TIM peripheral. + */ +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode)); + assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv)); + + tmpcr1 = TIMx->CTRL1; + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode; + } + + if ((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv; + } + + TIMx->CTRL1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->AR = TIM_TimeBaseInitStruct->Period; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE; + + /*channel input from comp or iom*/ + tmpcr1 = TIMx->CTRL1; + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapCh1FromCompEn) + tmpcr1 |= (0x01L << 11); + else + tmpcr1 &= ~(0x01L << 11); + } + if(TIMx==TIM9) + { + if (TIM_TimeBaseInitStruct->CapCh2FromCompEn) + tmpcr1 |= (0x01L << 12); + else + tmpcr1 &= ~(0x01L << 12); + if (TIM_TimeBaseInitStruct->CapCh3FromCompEn) + tmpcr1 |= (0x01L << 13); + else + tmpcr1 &= ~(0x01L << 13); + if (TIM_TimeBaseInitStruct->CapCh4FromCompEn) + tmpcr1 |= (0x01L << 14); + else + tmpcr1 &= ~(0x01L << 14); + } + /*etr input from comp or iom*/ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn) + tmpcr1 |= (0x01L << 15); + else + tmpcr1 &= ~(0x01L << 15); + } + TIMx->CTRL1 = tmpcr1; + /*sel etr from iom or tsc*/ + tmpcr1 = TIMx->CTRL2; + if ((TIMx == TIM2) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn) + tmpcr1 |= (0x01L << 8); + else + tmpcr1 &= ~(0x01L << 8); + } + TIMx->CTRL2 = tmpcr1; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN); + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->OcPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->OutputState; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->OcNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcNIdleState; + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN)); + + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel5 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 5: Reset the CC5E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel6 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 6: Reset the CC6E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT6 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IsTimCh(TIM_ICInitStruct->Channel)); + assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection)); + assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler)); + assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity)); + } + else + { + assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity)); + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + assert_param(IsTimList8Module(TIMx)); + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + assert_param(IsTimList6Module(TIMx)); + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + assert_param(IsTimList3Module(TIMx)); + /* TI3 Configuration */ + ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + assert_param(IsTimList3Module(TIMx)); + /* TI4 Configuration */ + ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING; + uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING) + { + icoppositepolarity = TIM_IC_POLARITY_FALLING; + } + else + { + icoppositepolarity = TIM_IC_POLARITY_RISING; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI) + { + icoppositeselection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI2 Configuration */ + ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI1 Configuration */ + ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that + * contains the BKDT Register configuration information for the TIM peripheral. + */ +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + uint32_t tmp; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState)); + assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState)); + assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel)); + assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break)); + assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel + | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity + | TIM_BDTRInitStruct->AutomaticOutput; + + /*cofigure other break in*/ + tmp = TIMx->CTRL1; + /*IOMBKPEN 0 meaning iom as break enable*/ + if (TIM_BDTRInitStruct->IomBreakEn) + tmp &= ~(0x01L << 10); + else + tmp |= (0x01L << 10); + if (TIM_BDTRInitStruct->LockUpBreakEn) + tmp |= (0x01L << 16); + else + tmp &= ~(0x01L << 16); + if (TIM_BDTRInitStruct->PvdBreakEn) + tmp |= (0x01L << 17); + else + tmp &= ~(0x01L << 17); + TIMx->CTRL1 = tmp; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure which will be initialized. + */ +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Period = 0xFFFF; + TIM_TimeBaseInitStruct->Prescaler = 0x0000; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->RepetCnt = 0x0000; + + TIM_TimeBaseInitStruct->CapCh1FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh2FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh3FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh4FromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct pointer to a OCInitType structure which will + * be initialized. + */ +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x0000; + TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will + * be initialized. + */ +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->Channel = TIM_CH_1; + TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->IcFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which + * will be initialized. + */ +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param Cmd new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CTRL1 |= TIM_CTRL1_CNTEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral. + * @param Cmd new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BKDT |= TIM_BKDT_MOEN; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @param Cmd new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DINTEN |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DINTEN &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_EventSource specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EVT_SRC_UPDATE Timer update Event source + * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source + * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source + * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source + * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source + * @arg TIM_EVT_SRC_COM Timer COM event source + * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source + * @arg TIM_EVT_SRC_BREAK Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8. + */ +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimEvtSrc(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EVTGEN = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_DMABase DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL, + * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN, + * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN, + * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR, + * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2, + * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT, + * TIM_DMABASE_DMACTRL. + * @param TIM_DMABurstLength DMA Burst length. + * This parameter can be one value between: + * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS. + */ +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IsTimDmaBase(TIM_DMABase)); + assert_param(IsTimDmaLength(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 + * to select the TIM peripheral. + * @param TIM_DMASource specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_UPDATE TIM update Interrupt source + * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM TIM Commutation DMA source + * @arg TIM_DMA_TRIG TIM Trigger DMA source + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList9Module(TIMx)); + assert_param(IsTimDmaSrc(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DINTEN |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DINTEN &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIM peripheral. + */ +void TIM_ConfigInternalClk(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_InputTriggerSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + */ +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimInterTrigSel(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector + * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1 + * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2 + * @param IcPolarity specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param ICFilter specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + */ +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource)); + assert_param(IsTimIcPalaritySingleEdge(IcPolarity)); + assert_param(IsTimInCapFilter(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2) + { + ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + else + { + ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + tmpsmcr |= TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCTRL |= TIM_SMCTRL_EXCEN; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + tmpsmcr = TIMx->SMCTRL; + /* Reset the ETR Bits */ + tmpsmcr &= SMCTRL_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= + (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Prescaler specifies the Prescaler Register value + * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event. + * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately. + */ +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimPscReloadMode(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EVTGEN = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param CntMode specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CNT_MODE_UP TIM Up Counting Mode + * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode + * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1 + * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2 + * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3 + */ +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode) +{ + uint32_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimCntMode(CntMode)); + tmpcr1 = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + tmpcr1 |= CntMode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector + * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1 + * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2 + * @arg TIM_TRIG_SEL_ETRF External Trigger input + */ +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimTrigSel(TIM_InputTriggerSource)); + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + * @param TIM_IC2Polarity specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + */ +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IsTimEncodeMode(TIM_EncoderMode)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity)); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL))); + tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P))); + tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF. + */ +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF. + */ +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF. + */ +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF. + */ +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 5 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF. + */ +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Forces the TIMx output 6 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF. + */ +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on AR. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AR Preload Bit */ + TIMx->CTRL1 |= TIM_CTRL1_ARPEN; + } + else + { + /* Reset the AR Preload Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral + * @param Cmd new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the COM Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCUSEL; + } + else + { + /* Reset the COM Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param Cmd new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCDSEL; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIMx peripheral + * @param Cmd new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCPCTL; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC5PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC6PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 5 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 6 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF5 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF6 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param OcPolarity specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P); + tmpccer |= OcPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP); + tmpccer |= OcNPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P); + tmpccer |= (uint32_t)(OcPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP); + tmpccer |= (uint32_t)(OcNPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P); + tmpccer |= (uint32_t)(OcPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP); + tmpccer |= (uint32_t)(OcNPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P); + tmpccer |= (uint32_t)(OcPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 5 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC5 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC5P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P); + tmpccer |= (uint32_t)(OcPolarity << 16); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 6 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC6 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC6P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P); + tmpccer |= (uint32_t)(OcPolarity << 20); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param TIM_CCx specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE. + */ +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimCapCmpState(TIM_CCx)); + + tmp = CAPCMPEN_CCE_SET << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE. + */ +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimComplementaryCh(Channel)); + assert_param(IsTimCapCmpNState(TIM_CCxN)); + + tmp = CAPCMPEN_CCNE_SET << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param OcMode specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMODE_TIMING + * @arg TIM_OCMODE_ACTIVE + * @arg TIM_OCMODE_TOGGLE + * @arg TIM_OCMODE_PWM1 + * @arg TIM_OCMODE_PWM2 + * @arg TIM_FORCED_ACTION_ACTIVE + * @arg TIM_FORCED_ACTION_INACTIVE + */ +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimOc(OcMode)); + + tmp = (uint32_t)TIMx; + tmp += CAPCMPMOD_OFFSET; + + tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint16_t)~tmp1; + + if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3)) + { + tmp += (Channel >> 1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= OcMode; + } + else + { + tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_UpdateSource specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow. + */ +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimUpdateSrc(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the URS Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPRS; + } + else + { + /* Reset the URS Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CTRL2 |= TIM_CTRL2_TI1SEL; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_OPMode specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE + * @arg TIM_OPMODE_REPET + */ +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimOpMOde(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM); + /* Configure the OPM Mode */ + TIMx->CTRL1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral. + * @param TIM_TRGOSource specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO). + * + */ +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IsTimList7Module(TIMx)); + assert_param(IsTimTrgoSrc(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_SlaveMode specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter. + */ +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimSlaveMode(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL); + /* Select the Slave Mode */ + TIMx->SMCTRL |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action + */ +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD); + + /* Set or Reset the MSM Bit */ + TIMx->SMCTRL |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Counter specifies the Counter register new value. + */ +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Autoreload specifies the Autoreload register new value. + */ +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Autoreload Register value */ + TIMx->AR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Compare1 specifies the Capture Compare1 register new value. + */ +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCDAT1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param Compare2 specifies the Capture Compare2 register new value. + */ +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCDAT2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3 specifies the Capture Compare3 register new value. + */ +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCDAT3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4 specifies the Capture Compare4 register new value. + */ +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT4 = Compare4; +} + +/** + * @brief Sets the TIMx Capture Compare5 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare5 specifies the Capture Compare5 register new value. + */ +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT5 = Compare5; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare6 specifies the Capture Compare6 register new value. + */ +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT6 = Compare6; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMOD2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLK_DIV1 TDTS = Tck_tim + * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim + * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim + */ +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimClkDiv(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD); + /* Set the CKD value */ + TIMx->CTRL1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @return Capture Compare 1 Register value. + */ +uint16_t TIM_GetCap1(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCDAT1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @return Capture Compare 2 Register value. + */ +uint16_t TIM_GetCap2(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCDAT2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 3 Register value. + */ +uint16_t TIM_GetCap3(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCDAT3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 4 Register value. + */ +uint16_t TIM_GetCap4(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCDAT4; +} + +/** + * @brief Gets the TIMx Input Capture 5 value. + * @param TIMx where x can be 1 8 to select the TIM peripheral. + * @return Capture Compare 5 Register value. + */ +uint16_t TIM_GetCap5(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 5 Register value */ + return TIMx->CCDAT5; +} + +/** + * @brief Gets the TIMx Input Capture 6 value. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @return Capture Compare 6 Register value. + */ +uint16_t TIM_GetCap6(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 6 Register value */ + return TIMx->CCDAT6; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Counter Register value. + */ +uint16_t TIM_GetCnt(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetAutoReload(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->AR; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral. + * @param TIM_CCEN specifies the Bit to check. + * This parameter can be one of the following values: + * @arg TIM_CC1EN CC1EN Bit + * @arg TIM_CC1NEN CC1NEN Bit + * @arg TIM_CC2EN CC2EN Bit + * @arg TIM_CC2NEN CC2NEN Bit + * @arg TIM_CC3EN CC3EN Bit + * @arg TIM_CC3NEN CC3NEN Bit + * @arg TIM_CC4EN CC4EN Bit + * @arg TIM_CC5EN CC5EN Bit + * @arg TIM_CC6EN CC6EN Bit + * @note + * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + + if(TIMx==TIM1 || TIMx==TIM8){ + assert_param(IsAdvancedTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + }else if(TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){ + assert_param(IsGeneralTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetFlag(TIM_FLAG)); + + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + */ +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimClrFlag(TIM_FLAG)); + + /* Clear the flags */ + TIMx->STS = (uint32_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @return The new state of the TIM_IT(SET or RESET). + */ +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetInt(TIM_IT)); + + itstatus = TIMx->STS & TIM_IT; + + itenable = TIMx->DINTEN & TIM_IT; + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM1 update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + */ +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->STS = (uint32_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F))); + tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F))); + tmpccmr1 |= (uint16_t)(IcFilter << 12); + tmpccmr1 |= (uint16_t)(IcSelection << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F))); + tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F))); + tmpccmr2 |= (uint16_t)(IcSelection << 8); + tmpccmr2 |= (uint16_t)(IcFilter << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN); + } + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tsc.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tsc.c new file mode 100644 index 0000000000000000000000000000000000000000..d924396d0fb2ccec479059f9847d977cf559865c --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_tsc.c @@ -0,0 +1,279 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_tsc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x.h" +#include "n32g43x_tsc.h" + +/** +* @brief Init TSC config +* @param InitParam: TSC initialize structure +* @return : TSC_ErrorTypeDef +*/ +TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam) +{ + uint32_t tempreg,timeout; + + assert_param(IS_TSC_DET_MODE(InitParam->Mode)); + assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt)); + assert_param(IS_TSC_PAD_SPEED(InitParam->Speed)); + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*TSC_CTRL config*/ + tempreg = 0; + if(InitParam->Mode == TSC_HW_DETECT_MODE) + { + assert_param(IS_TSC_DET_PERIOD(InitParam->Period)); + assert_param(IS_TSC_FILTER(InitParam->Filter)); + assert_param(IS_TSC_DET_TYPE(InitParam->Type)); + assert_param(IS_TSC_INT(InitParam->Int)); + + tempreg |= InitParam->Period; + tempreg |= InitParam->Filter; + tempreg |= InitParam->Type; + tempreg |= InitParam->Int; + } + else + { + assert_param(IS_TSC_OUT(InitParam->Out)); + tempreg |= InitParam->Out; + } + + TSC->CTRL = tempreg; + + /*TSC_ANA_SEL config*/ + TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed; + + return TSC_ERROR_OK; +} + +/** + * @brief Config the clock source of TSC + * @param TSC_ClkSource specifies the clock source of TSC + * This parameter can be one of the following values: + * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default) + * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator + * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock + * @retval TSC error code + */ +TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(TSC_CLK_SRC_LSI == TSC_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + else if((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET) + { + RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28); + timeout = 0; + while(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + } + else + return TSC_ERROR_PARAMETER; + + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100; + + /*set LSI as TSC clock source*/ + RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL); + + /*Enable TSC clk*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE); + + return TSC_ERROR_OK; +} + +/** +* @brief Configure internal charge resistor for some channels +* @param res: internal resistor selecte +* This parameter can be one of the following values: +* @arg TSC_RESR_CHN_RESIST_0: 1M OHM +* @arg TSC_RESR_CHN_RESIST_1: 882K OHM +* @arg TSC_RESR_CHN_RESIST_2: 756K OHM +* @arg TSC_RESR_CHN_RESIST_3: 630K OHM +* @arg TSC_RESR_CHN_RESIST_4: 504K OHM +* @arg TSC_RESR_CHN_RESIST_5: 378K OHM +* @arg TSC_RESR_CHN_RESIST_6: 252K OHM +* @arg TSC_RESR_CHN_RESIST_7: 126K OHM +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @return: none +*/ +TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ) +{ + uint32_t i,chn,timeout,nReg,nPos; + + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_RESISTOR_VALUE(res)); + + /*Check charge resistor value */ + if(res > TSC_RESRx_CHN_RESIST_7) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /* Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set resistance for each channel one by one*/ + for (i = 0; i> 3; + nPos = (i & 0x7UL)*4; + MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1; + } + + return TSC_ERROR_OK; +} + +/** +* @brief Configure threshold value for some channels +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE +* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA +* @return: None +*/ +TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta) +{ + uint32_t i, chn,timeout; + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_THRESHOLD_BASE(base)); + assert_param(IS_TSC_THRESHOLD_DELTA(delta)); + + /*Check the base and delta value*/ + if( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA)) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set the base and delta for each channnel one by one*/ + for (i = 0; iTHRHD[i] = (base<>= 1; + } + + return TSC_ERROR_OK; +} + + +/** +* @brief Get parameters of one channel. +* @param ChnCfg: Pointer of TSC_ChnCfg structure. +* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN +* @return: None +*/ +TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum) +{ + uint32_t nReg,nPos; + + assert_param(IS_TSC_CHN_NUMBER(ChannelNum)); + + /*Check channel number*/ + if(!(IS_TSC_CHN_NUMBER(ChannelNum))) + return TSC_ERROR_PARAMETER; + + /* Get the base and delta value for a channel*/ + ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos; + ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos; + + /* Get the charge resistor type for a channel*/ + nReg = ChannelNum>>3; + nPos = (ChannelNum & 0x7UL)*4; + ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk; + + return TSC_ERROR_OK; +} + + diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_usart.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..0ea48506b8b721683f2fdcf292137f988da51524 --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_usart.c @@ -0,0 +1,956 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_usart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_usart.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @brief USART driver modules + * @{ + */ + +/** @addtogroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Defines + * @{ + */ + +#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ +#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */ +#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */ + +#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */ + +#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_DeInit(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE); + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct pointer to a USART_InitType structure + * that contains the configuration information for the specified USART + * peripheral. + */ +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct) +{ + uint32_t tmpregister = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksType RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear STOP[13:12] bits */ + tmpregister &= CTRL2_STPB_CLR_MASK; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to StopBits value */ + tmpregister |= (uint32_t)USART_InitStruct->StopBits; + + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL1 Configuration -----------------------*/ + tmpregister = USARTx->CTRL1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to WordLength value */ + /* Set PCE and PS bits according to Parity value */ + /* Set TE and RE bits according to Mode value */ + tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode; + /* Write to USART CTRL1 */ + USARTx->CTRL1 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL3 Configuration -----------------------*/ + tmpregister = USARTx->CTRL3; + /* Clear CTSE and RTSE bits */ + tmpregister &= CTRL3_CLR_MASK; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to HardwareFlowControl value */ + tmpregister |= USART_InitStruct->HardwareFlowControl; + /* Write to USART CTRL3 */ + USARTx->CTRL3 = (uint16_t)tmpregister; + + /*---------------------------- USART PBC Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE)) + { + apbclock = RCC_ClocksStatus.Pclk2Freq; + } + else + { + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate))); + tmpregister = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpregister >> 4)); + + /* Implement the fractional part in the register */ + tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + /* Write to USART PBC */ + USARTx->BRCF = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct pointer to a USART_InitType structure + * which will be initialized. + */ +void USART_StructInit(USART_InitType* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->BaudRate = 9600; + USART_InitStruct->WordLength = USART_WL_8B; + USART_InitStruct->StopBits = USART_STPB_1; + USART_InitStruct->Parity = USART_PE_NO; + USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4/UART5. + */ +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct) +{ + uint32_t tmpregister = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit)); + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpregister &= CTRL2_CLOCK_CLR_MASK; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to Clock value */ + /* Set CPOL bit according to Polarity value */ + /* Set CPHA bit according to Phase value */ + /* Set LBCL bit according to LastBit value */ + tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity + | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure which will be initialized. + */ +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->Clock = USART_CLK_DISABLE; + USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW; + USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; + USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_UEN_SET; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_UEN_RESET; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Transmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) + * @param Cmd new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CFG_INT(USART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_INT & INT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CTRL3 register */ + { + usartxbase += 0x14; + } + if (Cmd != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAREQ_TX USART DMA transmit request + * @arg USART_DMAREQ_RX USART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Addr Indicates the address of the USART node. + */ +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Addr)); + + /* Clear the USART address */ + USARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the USART address node */ + USARTx->CTRL2 |= USART_Addr; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUpMode specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WUM_IDLELINE WakeUp by an idle line detection + * @arg USART_WUM_ADDRMASK WakeUp by an address mark + */ +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUpMode)); + + USARTx->CTRL1 &= CTRL1_WUM_MASK; + USARTx->CTRL1 |= USART_WakeUpMode; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_RCVWU_SET; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_RCVWU_RESET; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBDL_10B 10-bit break detection + * @arg USART_LINBDL_11B 11-bit break detection + */ +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CTRL2 &= CTRL2_LINBDL_MASK; + USARTx->CTRL2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 |= CTRL2_LINMEN_SET; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 &= CTRL2_LINMEN_RESET; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data the data to transmit. + */ +void USART_SendData(USART_Module* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DAT = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_SendBreak(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime specifies the guard time. + * @note The guard time bits are not available for UART4/UART5. + */ +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTP &= GTP_LSB_MASK; + /* Set the USART guard time */ + USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + */ +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTP &= GTP_MSB_MASK; + /* Set the USART prescaler */ + USARTx->GTP |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCMEN_SET; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCMEN_RESET; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCNACK_SET; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCNACK_RESET; + } +} + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_HDMEN_SET; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_HDMEN_RESET; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDAMODE_LOWPPWER + * @arg USART_IRDAMODE_NORMAL + */ +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CTRL3 &= CTRL3_IRDALP_MASK; + USARTx->CTRL3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_IRDAMEN_SET; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LINBD LIN Break detection flag + * @arg USART_FLAG_TXDE Transmit data register empty flag + * @arg USART_FLAG_TXC Transmission Complete flag + * @arg USART_FLAG_RXDNE Receive data register not empty flag + * @arg USART_FLAG_IDLEF Idle Line detection flag + * @arg USART_FLAG_OREF OverRun Error flag + * @arg USART_FLAG_NEF Noise Error flag + * @arg USART_FLAG_FEF Framing Error flag + * @arg USART_FLAG_PEF Parity Error flag + * @return The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if (USART_FLAG == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LINBD LIN Break detection flag. + * @arg USART_FLAG_TXC Transmission Complete flag. + * @arg USART_FLAG_RXDNE Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->STS = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Tansmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_OREF OverRun Error interrupt + * @arg USART_INT_NEF Noise Error interrupt + * @arg USART_INT_FEF Framing Error interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @return The new state of USART_INT (SET or RESET). + */ +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_INT & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + itmask &= USARTx->CTRL1; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + itmask &= USARTx->CTRL2; + } + else /* The IT is in CTRL3 register */ + { + itmask &= USARTx->CTRL3; + } + + bitpos = USART_INT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXC Transmission complete interrupt. + * @arg USART_INT_RXDNE Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetIntStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetIntStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLR_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_INT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STS = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_wwdg.c b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..8990125739dd926437770f3a2078836fa516f76e --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/n32g43x_std_periph_driver/src/n32g43x_wwdg.c @@ -0,0 +1,223 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g43x_wwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g43x_wwdg.h" +#include "n32g43x_rcc.h" + +/** @addtogroup N32G43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @addtogroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFG_OFFADDR (WWDG_OFFADDR + 0x04) +#define EWINT_BIT 0x09 +#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_ACTB_SET ((uint32_t)0x00000080) + +/* CFG register bit mask */ +#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F) +#define CFG_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + */ +void WWDG_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8 + */ +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpregister = WWDG->CFG & CFG_TIMERB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpregister |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + */ +void WWDG_SetWValue(uint8_t WindowValue) +{ + __IO uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WVALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpregister = WWDG->CFG & CFG_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpregister |= WindowValue & (uint32_t)BIT_MASK; + + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + */ +void WWDG_EnableInt(void) +{ + *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_SetCnt(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CTRL = Counter & BIT_MASK; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + WWDG->CTRL = CTRL_ACTB_SET | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetEWINTF(void) +{ + return (FlagStatus)(WWDG->STS); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + */ +void WWDG_ClrEWINTF(void) +{ + WWDG->STS = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32G43x/weave.yaml b/drivers/hal/nationstech/N32G43x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e9346393ad04431335cfae27c94f6b1e41c16d1b --- /dev/null +++ b/drivers/hal/nationstech/N32G43x/weave.yaml @@ -0,0 +1,33 @@ +# 组名 +group_name: hal/lowlevel + +# 依赖宏控 +depend_macro: + - SERIES_N32G43X + +# 编译连接信息 +build_option: + cpppath: + - n32g43x_std_periph_driver/inc + - CMSIS/core + - CMSIS/device + +# 源码 +source_file: + - CMSIS/device/system_n32g43x.c + - n32g43x_std_periph_driver/src/n32g43x_rcc.c + - n32g43x_std_periph_driver/src/misc.c + - n32g43x_std_periph_driver/src/n32g43x_gpio.c + - n32g43x_std_periph_driver/src/n32g43x_exti.c ? {is_define("OS_USING_PIN")} + - n32g43x_std_periph_driver/src/n32g43x_iwdg.c ? {is_define("OS_USING_WDG")} + - n32g43x_std_periph_driver/src/n32g43x_usart.c ? {is_define("OS_USING_SERIAL")} + - n32g43x_std_periph_driver/src/n32g43x_adc.c ? {is_define("OS_USING_ADC")} + - n32g43x_std_periph_driver/src/n32g43x_dac.c ? {is_define("OS_USING_DAC")} + - n32g43x_std_periph_driver/src/n32g43x_i2c.c ? {is_define("OS_USING_I2C")} + - n32g43x_std_periph_driver/src/n32g43x_spi.c ? {is_define("OS_USING_SPI")} + - n32g43x_std_periph_driver/src/n32g43x_flash.c ? {is_define("OS_USING_FAL")} + - n32g43x_std_periph_driver/src/n32g43x_dma.c ? {is_define("OS_USING_DMA")} + - n32g43x_std_periph_driver/src/n32g43x_rtc.c ? {is_define("BSP_USING_RTC")} + - n32g43x_std_periph_driver/src/n32g43x_pwr.c ? {is_define("BSP_USING_RTC")} + - n32g43x_std_periph_driver/src/n32g43x_tim.c ? {is_define("BSP_USING_TIMER")} + - n32g43x_std_periph_driver/src/n32g43x_eth.c ? {is_define("BSP_USING_ETH")} diff --git a/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x.h b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x.h index 8db521e956ac7dfe831df5dcbbbb60c0711a960e..53008423ed776b8cd40c932cb625ccc8cf18c19b 100644 --- a/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x.h +++ b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x.h @@ -1044,8 +1044,8 @@ typedef struct __IO uint32_t DMA_CTRL; __IO uint32_t DMATDL_CTRL; __IO uint32_t DMARDL_CTRL; - __IO uint32_t IDCODE; - __IO uint32_t RESERVED; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; __IO uint32_t DAT0; __IO uint32_t DAT1; __IO uint32_t DAT2; @@ -7910,58 +7910,58 @@ typedef struct #define QSPI_CTRL0_DFS_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define QSPI_CTRL0_DFS_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define QSPI_CTRL0_DFS_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define QSPI_CTRL0_DFS_4_BIT ((uint32_t)0x00000003) -#define QSPI_CTRL0_DFS_5_BIT ((uint32_t)0x00000004) -#define QSPI_CTRL0_DFS_6_BIT ((uint32_t)0x00000005) -#define QSPI_CTRL0_DFS_7_BIT ((uint32_t)0x00000006) -#define QSPI_CTRL0_DFS_8_BIT ((uint32_t)0x00000007) -#define QSPI_CTRL0_DFS_9_BIT ((uint32_t)0x00000008) -#define QSPI_CTRL0_DFS_10_BIT ((uint32_t)0x00000009) -#define QSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0000000A) -#define QSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0000000B) -#define QSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0000000C) -#define QSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0000000D) -#define QSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0000000E) -#define QSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0000000F) -#define QSPI_CTRL0_DFS_17_BIT ((uint32_t)0x00000010) -#define QSPI_CTRL0_DFS_18_BIT ((uint32_t)0x00000011) -#define QSPI_CTRL0_DFS_19_BIT ((uint32_t)0x00000012) -#define QSPI_CTRL0_DFS_20_BIT ((uint32_t)0x00000013) -#define QSPI_CTRL0_DFS_21_BIT ((uint32_t)0x00000014) -#define QSPI_CTRL0_DFS_22_BIT ((uint32_t)0x00000015) -#define QSPI_CTRL0_DFS_23_BIT ((uint32_t)0x00000016) -#define QSPI_CTRL0_DFS_24_BIT ((uint32_t)0x00000017) -#define QSPI_CTRL0_DFS_25_BIT ((uint32_t)0x00000018) -#define QSPI_CTRL0_DFS_26_BIT ((uint32_t)0x00000019) -#define QSPI_CTRL0_DFS_27_BIT ((uint32_t)0x0000001A) -#define QSPI_CTRL0_DFS_28_BIT ((uint32_t)0x0000001B) -#define QSPI_CTRL0_DFS_29_BIT ((uint32_t)0x0000001C) -#define QSPI_CTRL0_DFS_30_BIT ((uint32_t)0x0000001D) -#define QSPI_CTRL0_DFS_31_BIT ((uint32_t)0x0000001E) -#define QSPI_CTRL0_DFS_32_BIT ((uint32_t)0x0000001F) +#define QSPI_CTRL0_DFS_4_BIT ((uint32_t)0x00000003) +#define QSPI_CTRL0_DFS_5_BIT ((uint32_t)0x00000004) +#define QSPI_CTRL0_DFS_6_BIT ((uint32_t)0x00000005) +#define QSPI_CTRL0_DFS_7_BIT ((uint32_t)0x00000006) +#define QSPI_CTRL0_DFS_8_BIT ((uint32_t)0x00000007) +#define QSPI_CTRL0_DFS_9_BIT ((uint32_t)0x00000008) +#define QSPI_CTRL0_DFS_10_BIT ((uint32_t)0x00000009) +#define QSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0000000A) +#define QSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0000000B) +#define QSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0000000C) +#define QSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0000000D) +#define QSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0000000E) +#define QSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0000000F) +#define QSPI_CTRL0_DFS_17_BIT ((uint32_t)0x00000010) +#define QSPI_CTRL0_DFS_18_BIT ((uint32_t)0x00000011) +#define QSPI_CTRL0_DFS_19_BIT ((uint32_t)0x00000012) +#define QSPI_CTRL0_DFS_20_BIT ((uint32_t)0x00000013) +#define QSPI_CTRL0_DFS_21_BIT ((uint32_t)0x00000014) +#define QSPI_CTRL0_DFS_22_BIT ((uint32_t)0x00000015) +#define QSPI_CTRL0_DFS_23_BIT ((uint32_t)0x00000016) +#define QSPI_CTRL0_DFS_24_BIT ((uint32_t)0x00000017) +#define QSPI_CTRL0_DFS_25_BIT ((uint32_t)0x00000018) +#define QSPI_CTRL0_DFS_26_BIT ((uint32_t)0x00000019) +#define QSPI_CTRL0_DFS_27_BIT ((uint32_t)0x0000001A) +#define QSPI_CTRL0_DFS_28_BIT ((uint32_t)0x0000001B) +#define QSPI_CTRL0_DFS_29_BIT ((uint32_t)0x0000001C) +#define QSPI_CTRL0_DFS_30_BIT ((uint32_t)0x0000001D) +#define QSPI_CTRL0_DFS_31_BIT ((uint32_t)0x0000001E) +#define QSPI_CTRL0_DFS_32_BIT ((uint32_t)0x0000001F) #define QSPI_CTRL0_FRF ((uint32_t)0x000000C0) /*!< FRF[1:0] bits (Frame Format) */ #define QSPI_CTRL0_FRF_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define QSPI_CTRL0_FRF_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define QSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000) -#define QSPI_CTRL0_FRF_TI ((uint32_t)0x00000040) -#define QSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080) +#define QSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000) +#define QSPI_CTRL0_FRF_TI ((uint32_t)0x00000040) +#define QSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080) #define QSPI_CTRL0_SCPH ((uint32_t)0x00000100) /*!< SCPH (Serial Clock Phase) */ -#define QSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000) -#define QSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100) +#define QSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000) +#define QSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100) #define QSPI_CTRL0_SCPOL ((uint32_t)0x00000200) /*!< SCPOL(Serial Clock Polarity) */ -#define QSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000) -#define QSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200) +#define QSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000) +#define QSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200) #define QSPI_CTRL0_TMOD ((uint32_t)0x00000C00) /*!< TMOD[1:0] bits (Transfer Mode) */ #define QSPI_CTRL0_TMOD_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define QSPI_CTRL0_TMOD_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define QSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000) -#define QSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400) -#define QSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800) -#define QSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00) +#define QSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000) +#define QSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400) +#define QSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800) +#define QSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00) #define QSPI_CTRL0_SRL_EN ((uint32_t)0x00002000) /*!< SRL (Shift Register Loop) */ #define QSPI_CTRL0_SSTE_EN ((uint32_t)0x00004000) /*!< SSTE(Slave Select Toggle Enable) */ @@ -7971,29 +7971,29 @@ typedef struct #define QSPI_CTRL0_CFS_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define QSPI_CTRL0_CFS_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define QSPI_CTRL0_CFS_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define QSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000) -#define QSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000) -#define QSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000) -#define QSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000) -#define QSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000) -#define QSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000) -#define QSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000) -#define QSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000) -#define QSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000) -#define QSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000) -#define QSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000) -#define QSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000) -#define QSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000) -#define QSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000) -#define QSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000) -#define QSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000) +#define QSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000) +#define QSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000) +#define QSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000) +#define QSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000) +#define QSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000) +#define QSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000) +#define QSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000) +#define QSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000) +#define QSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000) +#define QSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000) +#define QSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000) +#define QSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000) +#define QSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000) +#define QSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000) +#define QSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000) +#define QSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000) #define QSPI_CTRL0_SPI_FRF ((uint32_t)0x00C00000) /*!< SPI_FRF[1:0] bits (SPI Frame Format) */ #define QSPI_CTRL0_SPI_FRF_0 ((uint32_t)0x00400000) /*!< Bit 0 */ #define QSPI_CTRL0_SPI_FRF_1 ((uint32_t)0x00800000) /*!< Bit 1 */ -#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT ((uint32_t)0x00000000) -#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT ((uint32_t)0x00400000) -#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT ((uint32_t)0x00800000) +#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT ((uint32_t)0x00000000) +#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT ((uint32_t)0x00400000) +#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT ((uint32_t)0x00800000) /******************* Bit definition for QSPI_CTRL1 register *******************/ #define QSPI_CTRL1_NDF ((uint32_t)0x0000FFFF) /*!< NDF[15:0] bits (Numver of Data Frames) */ @@ -8019,12 +8019,12 @@ typedef struct /******************* Bit definition for QSPI_MW_CTRL register *******************/ #define QSPI_MW_CTRL_MWMOD ((uint32_t)0x00000001) /*!< MWMO (Microwire Transfer Mode) */ -#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL ((uint32_t)0x00000000) -#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x00000001) +#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL ((uint32_t)0x00000000) +#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x00000001) #define QSPI_MW_CTRL_MC_DIR ((uint32_t)0x00000002) /*!< MC_DIR (Direction of Data when Microwire Control) */ -#define QSPI_MW_CTRL_MC_DIR_RX ((uint32_t)0x00000000) -#define QSPI_MW_CTRL_MC_DIR_TX ((uint32_t)0x00000002) +#define QSPI_MW_CTRL_MC_DIR_RX ((uint32_t)0x00000000) +#define QSPI_MW_CTRL_MC_DIR_TX ((uint32_t)0x00000002) #define QSPI_MW_CTRL_MHS_EN ((uint32_t)0x00000004) /*!< MHS_EN (Microwire Handshaking Enable) */ @@ -8098,8 +8098,7 @@ typedef struct #define QSPI_STS_TXFE ((uint32_t)0x00000004) /*!< TXFE (Transmit FIFO not Empty) */ #define QSPI_STS_RXFNE ((uint32_t)0x00000008) /*!< RXFNE (Receive FIFO not Empty) */ #define QSPI_STS_RXFF ((uint32_t)0x00000010) /*!< RXFF (Receive FIFO not Full) */ -#define QSPI_STS_TX_ERR ((uint32_t)0x00000020) /*!< TX_ERR (Transmit Error) */ -#define QSPI_STS_DC_ERR ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */ +#define QSPI_STS_DC_ERR ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */ /******************* Bit definition for QSPI_IMASK register *******************/ #define QSPI_IMASK ((uint32_t)0x0000007F) /*!< IMASK[6:0] (Interrupt of Mask) */ @@ -8168,41 +8167,6 @@ typedef struct #define QSPI_DMARDL_CTRL_DMARDL_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define QSPI_DMARDL_CTRL_DMARDL_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -/******************* Bit definition for QSPI_IDCODE register *******************/ -#define QSPI_IDCODE ((uint32_t)0x0000FFFF) /*!< IDCODE[31:0] (Identification Code) */ -#define QSPI_IDCODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define QSPI_IDCODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define QSPI_IDCODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define QSPI_IDCODE_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define QSPI_IDCODE_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define QSPI_IDCODE_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define QSPI_IDCODE_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define QSPI_IDCODE_7 ((uint32_t)0x00000080) /*!< Bit 7 */ -#define QSPI_IDCODE_8 ((uint32_t)0x00000100) /*!< Bit 8 */ -#define QSPI_IDCODE_9 ((uint32_t)0x00000200) /*!< Bit 9 */ -#define QSPI_IDCODE_10 ((uint32_t)0x00000400) /*!< Bit 10 */ -#define QSPI_IDCODE_11 ((uint32_t)0x00000800) /*!< Bit 11 */ -#define QSPI_IDCODE_12 ((uint32_t)0x00001000) /*!< Bit 12 */ -#define QSPI_IDCODE_13 ((uint32_t)0x00002000) /*!< Bit 13 */ -#define QSPI_IDCODE_14 ((uint32_t)0x00004000) /*!< Bit 14 */ -#define QSPI_IDCODE_15 ((uint32_t)0x00008000) /*!< Bit 15 */ -#define QSPI_IDCODE_16 ((uint32_t)0x00010000) /*!< Bit 16 */ -#define QSPI_IDCODE_17 ((uint32_t)0x00020000) /*!< Bit 17 */ -#define QSPI_IDCODE_18 ((uint32_t)0x00040000) /*!< Bit 18 */ -#define QSPI_IDCODE_19 ((uint32_t)0x00080000) /*!< Bit 19 */ -#define QSPI_IDCODE_20 ((uint32_t)0x00100000) /*!< Bit 20 */ -#define QSPI_IDCODE_21 ((uint32_t)0x00200000) /*!< Bit 21 */ -#define QSPI_IDCODE_22 ((uint32_t)0x00400000) /*!< Bit 22 */ -#define QSPI_IDCODE_23 ((uint32_t)0x00800000) /*!< Bit 23 */ -#define QSPI_IDCODE_24 ((uint32_t)0x01000000) /*!< Bit 24 */ -#define QSPI_IDCODE_25 ((uint32_t)0x02000000) /*!< Bit 25 */ -#define QSPI_IDCODE_26 ((uint32_t)0x04000000) /*!< Bit 26 */ -#define QSPI_IDCODE_27 ((uint32_t)0x08000000) /*!< Bit 27 */ -#define QSPI_IDCODE_28 ((uint32_t)0x10000000) /*!< Bit 28 */ -#define QSPI_IDCODE_29 ((uint32_t)0x20000000) /*!< Bit 29 */ -#define QSPI_IDCODE_30 ((uint32_t)0x40000000) /*!< Bit 30 */ -#define QSPI_IDCODE_31 ((uint32_t)0x80000000) /*!< Bit 31 */ - /******************* Bit definition for QSPI_DAT0~QSPI_DAT31 register *******************/ #define QSPI_DATA_ALL ((uint32_t)0x0000FFFF) /*!< QSPI_DAT[31:0] (DATA Register) */ #define QSPI_DATA_0 ((uint32_t)0x00000001) /*!< Bit 0 */ @@ -8248,24 +8212,24 @@ typedef struct #define QSPI_RS_DELAY_SDCN_5 ((uint32_t)0x00000020) /*!< Bit 5 */ #define QSPI_RS_DELAY_SDCN_6 ((uint32_t)0x00000040) /*!< Bit 6 */ #define QSPI_RS_DELAY_SDCN_7 ((uint32_t)0x00000080) /*!< Bit 7 */ -#define QSPI_RS_DELAY_SDCN_0_CYCLES ((uint32_t)0x00000000) -#define QSPI_RS_DELAY_SDCN_1_CYCLES ((uint32_t)0x00000001) -#define QSPI_RS_DELAY_SDCN_2_CYCLES ((uint32_t)0x00000002) -#define QSPI_RS_DELAY_SDCN_3_CYCLES ((uint32_t)0x00000003) -#define QSPI_RS_DELAY_SDCN_4_CYCLES ((uint32_t)0x00000004) -#define QSPI_RS_DELAY_SDCN_5_CYCLES ((uint32_t)0x00000005) -#define QSPI_RS_DELAY_SDCN_6_CYCLES ((uint32_t)0x00000006) - -#define QSPI_RS_DELAY_SES ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */ -#define QSPI_RS_DELAY_SES_RISING_EDGE ((uint32_t)0x00000000) -#define QSPI_RS_DELAY_SES_FALLING_EDGE ((uint32_t)0x00010000) +#define QSPI_RS_DELAY_SDCN_0_CYCLES ((uint32_t)0x00000000) +#define QSPI_RS_DELAY_SDCN_1_CYCLES ((uint32_t)0x00000001) +#define QSPI_RS_DELAY_SDCN_2_CYCLES ((uint32_t)0x00000002) +#define QSPI_RS_DELAY_SDCN_3_CYCLES ((uint32_t)0x00000003) +#define QSPI_RS_DELAY_SDCN_4_CYCLES ((uint32_t)0x00000004) +#define QSPI_RS_DELAY_SDCN_5_CYCLES ((uint32_t)0x00000005) +#define QSPI_RS_DELAY_SDCN_6_CYCLES ((uint32_t)0x00000006) + +#define QSPI_RS_DELAY_SES ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */ +#define QSPI_RS_DELAY_SES_RISING_EDGE ((uint32_t)0x00000000) +#define QSPI_RS_DELAY_SES_FALLING_EDGE ((uint32_t)0x00010000) /******************* Bit definition for QSPI_ENH_CTRL0 register *******************/ #define QSPI_ENH_CTRL0_TRANS_TYPE ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */ #define QSPI_ENH_CTRL0_TRANS_TYPE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define QSPI_ENH_CTRL0_TRANS_TYPE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD ((uint32_t)0x00000000) -#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001) -#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF ((uint32_t)0x00000002) +#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD ((uint32_t)0x00000000) +#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001) +#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF ((uint32_t)0x00000002) #define QSPI_ENH_CTRL0_ADDR_LEN ((uint32_t)0x0000003C) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */ #define QSPI_ENH_CTRL0_ADDR_LEN_0 ((uint32_t)0x00000004) /*!< Bit 0 */ @@ -8288,15 +8252,13 @@ typedef struct #define QSPI_ENH_CTRL0_ADDR_LEN_56_BIT ((uint32_t)0x00000038) #define QSPI_ENH_CTRL0_ADDR_LEN_60_BIT ((uint32_t)0x0000003C) -#define QSPI_ENH_CTRL0_MD_BIT_EN ((uint32_t)0x00000080) /*!< MD_BIT_EN (Mode bits enable in XIP mode) */ - #define QSPI_ENH_CTRL0_INST_L ((uint32_t)0x00000300) /*!< INST_L[1:0] (Dual/Quad mode instruction length in bits) */ #define QSPI_ENH_CTRL0_INST_L_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define QSPI_ENH_CTRL0_INST_L_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define QSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000) -#define QSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100) -#define QSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200) -#define QSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300) +#define QSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000) +#define QSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100) +#define QSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200) +#define QSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300) #define QSPI_ENH_CTRL0_WAIT_CYCLES ((uint32_t)0x0000F800) /*!< WAIT_CYCLES[4:0] (Wait Cycles in Dual/Quad mode between control frames transmit and data reception) */ #define QSPI_ENH_CTRL0_WAIT_CYCLES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ @@ -8336,23 +8298,10 @@ typedef struct #define QSPI_ENH_CTRL0_WAIT_30CYCLES ((uint32_t)0x0000F000) #define QSPI_ENH_CTRL0_WAIT_31CYCLES ((uint32_t)0x0000F800) - #define QSPI_ENH_CTRL0_SPI_DDR_EN ((uint32_t)0x00010000) /*!< SPI_DDR_EN (SPI DDR Enable) */ #define QSPI_ENH_CTRL0_INST_DDR_EN ((uint32_t)0x00020000) /*!< INST_DDR_EN (XIP instruction enable) */ -#define QSPI_ENH_CTRL0_XIP_DFS_HC ((uint32_t)0x00080000) /*!< XIP_DFS_HC (Fix DFS for XIP transfers) */ -#define QSPI_ENH_CTRL0_XIP_INST_EN ((uint32_t)0x00100000) /*!< XIP_INST_EN (XIP instruction enable) */ -#define QSPI_ENH_CTRL0_XIP_CT_EN ((uint32_t)0x00200000) /*!< XIP_CT_EN (Enable Continuous Transfer in XIP mode) */ - -#define QSPI_ENH_CTRL0_XIP_MBL ((uint32_t)0x0C000000) /*!< XIP_MBL[1:0] (XIP Mode bits length) */ -#define QSPI_ENH_CTRL0_XIP_MBL_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define QSPI_ENH_CTRL0_XIP_MBL_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT ((uint32_t)0x00000000) -#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT ((uint32_t)0x04000000) -#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT ((uint32_t)0x08000000) -#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT ((uint32_t)0x0C000000) - -#define QSPI_ENH_CTRL0_CLK_STRETCH_EN ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable Continuous Transfer in XIP mode) */ +#define QSPI_ENH_CTRL0_CLK_STRETCH_EN ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable clock stretch capablity in SPI tramsfers) */ /******************* Bit definition for QSPI_DDR_TXDE register *******************/ #define QSPI_DDR_TXDE ((uint32_t)0x000000FF) /*!< TXDE[7:0] (Transmit Drive Edge) */ @@ -9039,7 +8988,7 @@ typedef struct */ #ifdef USE_STDPERIPH_DRIVER -#include "n32g45x_hal.h" +#include "n32g45x_conf.h" #endif #ifdef __cplusplus diff --git a/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_hal.h b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_conf.h similarity index 99% rename from drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_hal.h rename to drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_conf.h index cebe2d970662b26f80cb8a97dd67d31baa0a8b04..29f19692baea091bea9b8262ec1a8bdfdc63839f 100644 --- a/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_hal.h +++ b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_conf.h @@ -35,8 +35,6 @@ #ifndef __N32G45X_CONF_H__ #define __N32G45X_CONF_H__ -#include "n32g45x.h" - /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ #include "n32g45x_adc.h" diff --git a/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_flash.ld b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..0bfa52a21bf3833b726c65e3042f6420cc9adb91 --- /dev/null +++ b/drivers/hal/nationstech/N32G45x/CMSIS/device/n32g45x_flash.ld @@ -0,0 +1,182 @@ +/** + **************************************************************************** + Copyright (c) 2019, Nations Technologies Inc. + + All rights reserved. + **************************************************************************** + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the disclaimer below. + + Nations' name may not be used to endorse or promote products derived from + this software without specific prior written permission. + + DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + **/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/drivers/hal/nationstech/N32G45x/CMSIS/device/startup/startup_n32g45x_gcc.s b/drivers/hal/nationstech/N32G45x/CMSIS/device/startup/startup_n32g45x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..4d9e42ff12dcb5efcc3d8993693c0fd8293d9256 --- /dev/null +++ b/drivers/hal/nationstech/N32G45x/CMSIS/device/startup/startup_n32g45x_gcc.s @@ -0,0 +1,506 @@ +/** + **************************************************************************** + Copyright (c) 2019, Nations Technologies Inc. + + All rights reserved. + **************************************************************************** + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the disclaimer below. + + Nations' name may not be used to endorse or promote products derived from + this software without specific prior written permission. + + DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + **/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1, ADC2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word ADC3_4_IRQHandler /* ADC3 & ADC4 */ + .word XFMC_IRQHandler /* XFMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel5 */ + .word ETH_IRQHandler /* Ethernet global interrupt */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word QSPI_IRQHandler /* QSPI */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel7 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word I2C4_EV_IRQHandler /* I2C4 event */ + .word I2C4_ER_IRQHandler /* I2C4 error */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel8 */ + .word DVP_IRQHandler /* DVP */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_4_IRQHandler + .thumb_set ADC3_4_IRQHandler,Default_Handler + + .weak XFMC_IRQHandler + .thumb_set XFMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak QSPI_IRQHandler + .thumb_set QSPI_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak UART6_IRQHandler + .thumb_set UART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler diff --git a/drivers/hal/nationstech/N32G45x/CMSIS/device/system_n32g45x.c b/drivers/hal/nationstech/N32G45x/CMSIS/device/system_n32g45x.c index 10fdf895754b545ac9926fb7126f4cb6eda4cccc..3699bb882bb7cc2b50727a5acfba24bf0dc34221 100644 --- a/drivers/hal/nationstech/N32G45x/CMSIS/device/system_n32g45x.c +++ b/drivers/hal/nationstech/N32G45x/CMSIS/device/system_n32g45x.c @@ -28,7 +28,7 @@ /** * @file system_n32g45x.c * @author Nations - * @version v1.0.2 + * @version v1.0.3 * * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. */ @@ -64,11 +64,11 @@ #define SYSCLK_USE_HSE_PLL 3 #ifndef SYSCLK_FREQ -#define SYSCLK_FREQ (100*1000*1000) +#define SYSCLK_FREQ 144000000 #endif #ifndef SYSCLK_SRC -#define SYSCLK_SRC SYSCLK_USE_HSI_PLL +#define SYSCLK_SRC SYSCLK_USE_HSE_PLL #endif #if SYSCLK_SRC == SYSCLK_USE_HSI @@ -171,10 +171,10 @@ void SystemInit(void) RCC->CFG &= (uint32_t)0xF700FFFF; /* Reset CFG2 register */ - RCC->CFG2 = 0x00000000; + RCC->CFG2 = 0x00003800; /* Reset CFG3 register */ - RCC->CFG3 = 0x00000000; + RCC->CFG3 = 0x00003840; /* Disable all interrupts and clear pending bits */ RCC->CLKINT = 0x009F0000; diff --git a/drivers/hal/nationstech/N32G45x/Kconfig b/drivers/hal/nationstech/N32G45x/Kconfig index 224355da5755b1a90d3e45944b2388644d369eaa..ad30736d3ad6d971b18f8100ed32c98239aa2cfe 100644 --- a/drivers/hal/nationstech/N32G45x/Kconfig +++ b/drivers/hal/nationstech/N32G45x/Kconfig @@ -1,4 +1,4 @@ -config SERIES_N32G4XX +config SERIES_N32G45X bool select ARCH_ARM_CORTEX_M4 default n @@ -6,5 +6,5 @@ config SERIES_N32G4XX config SOC_N32G452CCL7 bool select MANUFACTOR_NATIONSTECH - select SERIES_N32G4XX + select SERIES_N32G45X default n diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/misc.h b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/misc.h index 543e4d1533b045d9bb2c4b50feb740e81e66f250..944a6120a33581fec8f62e9887da716ceb548e07 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/misc.h +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/misc.h @@ -180,10 +180,9 @@ priority | | | 0 * @{ */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +//#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) \ - (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE) == SysTick_CLKSource_HCLK) /** * @} */ diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_adc.h b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_adc.h index 37d99ca583f6d5e2998b813363fba1b27110963d..35b1167070aec8f9e601139e3277b0ce66808274 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_adc.h +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_adc.h @@ -528,6 +528,9 @@ typedef struct /** * @} */ + +#define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK) +#define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK)) /**@addtogroup ADC_sampt3_definition * @{ diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_comp.h b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_comp.h index ae6079af330700ffa01d8d06c84da47e4ee98642..dfbb58438184c2daaced4357f53d528f5296c036 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_comp.h +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_comp.h @@ -214,49 +214,49 @@ typedef enum { COMP1_CTRL_INMSEL_PA0 = (0x0L << 1), COMP1_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1), COMP1_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1), - COMP1_CTRL_INMSEL_VERF1 = (0x3L << 1), - COMP1_CTRL_INMSEL_VERF2 = (0x4L << 1), + COMP1_CTRL_INMSEL_VREF1 = (0x3L << 1), + COMP1_CTRL_INMSEL_VREF2 = (0x4L << 1), //comp2 inm sel COMP2_CTRL_INMSEL_PB1 = (0x0L << 1), COMP2_CTRL_INMSEL_PE8 = (0x1L << 1), COMP2_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), COMP2_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), - COMP2_CTRL_INMSEL_VERF1 = (0x4L << 1), - COMP2_CTRL_INMSEL_VERF2 = (0x5L << 1), + COMP2_CTRL_INMSEL_VREF1 = (0x4L << 1), + COMP2_CTRL_INMSEL_VREF2 = (0x5L << 1), //comp3 inm sel COMP3_CTRL_INMSEL_PB12 = (0x0L << 1), COMP3_CTRL_INMSEL_PE7 = (0x1L << 1), COMP3_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), COMP3_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), - COMP3_CTRL_INMSEL_VERF1 = (0x4L << 1), - COMP3_CTRL_INMSEL_VERF2 = (0x5L << 1), + COMP3_CTRL_INMSEL_VREF1 = (0x4L << 1), + COMP3_CTRL_INMSEL_VREF2 = (0x5L << 1), //comp4 inm sel COMP4_CTRL_INMSEL_PC4 = (0x0L << 1), COMP4_CTRL_INMSEL_PB13 = (0x1L << 1), COMP4_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), COMP4_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), - COMP4_CTRL_INMSEL_VERF1 = (0x4L << 1), - COMP4_CTRL_INMSEL_VERF2 = (0x5L << 1), + COMP4_CTRL_INMSEL_VREF1 = (0x4L << 1), + COMP4_CTRL_INMSEL_VREF2 = (0x5L << 1), //comp5 inm sel COMP5_CTRL_INMSEL_PB10 = (0x0L << 1), COMP5_CTRL_INMSEL_PD10 = (0x1L << 1), COMP5_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), COMP5_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), - COMP5_CTRL_INMSEL_VERF1 = (0x4L << 1), - COMP5_CTRL_INMSEL_VERF2 = (0x5L << 1), + COMP5_CTRL_INMSEL_VREF1 = (0x4L << 1), + COMP5_CTRL_INMSEL_VREF2 = (0x5L << 1), //comp6 inm sel COMP6_CTRL_INMSEL_PA7 = (0x0L << 1), COMP6_CTRL_INMSEL_PD8 = (0x1L << 1), COMP6_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), COMP6_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), - COMP6_CTRL_INMSEL_VERF1 = (0x4L << 1), - COMP6_CTRL_INMSEL_VERF2 = (0x5L << 1), + COMP6_CTRL_INMSEL_VREF1 = (0x4L << 1), + COMP6_CTRL_INMSEL_VREF2 = (0x5L << 1), //comp7 inm sel COMP7_CTRL_INMSEL_PC0 = (0x0L << 1), COMP7_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1), COMP7_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1), - COMP7_CTRL_INMSEL_VERF1 = (0x3L << 1), - COMP7_CTRL_INMSEL_VERF2 = (0x4L << 1), + COMP7_CTRL_INMSEL_VREF1 = (0x3L << 1), + COMP7_CTRL_INMSEL_VREF2 = (0x4L << 1), }COMP_CTRL_INMSEL; #define COMP_CTRL_EN_MASK (0x01L << 0) diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_qspi.h b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_qspi.h index 914e426d7d127618a790f81f683dd2f5f218a61c..f8a74b132995625fcd4df8d3398e04ed82ed9e8e 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_qspi.h +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_qspi.h @@ -120,15 +120,10 @@ typedef struct /*QSPI_ENH_CTRL0*/ uint32_t ENHANCED_TRANS_TYPE; uint32_t ENHANCED_ADDR_LEN; - uint32_t ENHANCED_MD_BIT_EN; uint32_t ENHANCED_INST_L; uint32_t ENHANCED_WAIT_CYCLES; uint32_t ENHANCED_SPI_DDR_EN; uint32_t ENHANCED_INST_DDR_EN; - uint32_t ENHANCED_XIP_DFS_HC; - uint32_t ENHANCED_XIP_INST_EN; - uint32_t ENHANCED_XIP_CT_EN; - uint32_t ENHANCED_XIP_MBL; uint32_t ENHANCED_CLK_STRETCH_EN; /*QSPI_DDR_TXDE*/ @@ -213,16 +208,6 @@ typedef struct #define IS_QSPI_ENH_CLK_STRETCH_EN(ENH_CLK_STRETCH_EN) (((ENH_CLK_STRETCH_EN) == QSPI_ENH_CTRL0_CLK_STRETCH_EN) || ((ENH_CLK_STRETCH_EN) == 0)) -#define IS_QSPI_ENH_XIP_MBL(ENH_XIP_MBL) \ - (((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_2_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_4_BIT) || \ - ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_8_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_16_BIT)) - -#define IS_QSPI_ENH_XIP_CT_EN(ENH_XIP_CT_EN) (((ENH_XIP_CT_EN) == QSPI_ENH_CTRL0_XIP_CT_EN) || ((ENH_XIP_CT_EN) == 0)) - -#define IS_QSPI_ENH_XIP_INST_EN(ENH_XIP_INST_EN) (((ENH_XIP_INST_EN) == QSPI_ENH_CTRL0_XIP_INST_EN) || ((ENH_XIP_INST_EN) == 0)) - -#define IS_QSPI_ENH_XIP_DFS_HC(ENH_XIP_DFS_HC) (((ENH_XIP_DFS_HC) == QSPI_ENH_CTRL0_XIP_DFS_HC) || ((ENH_XIP_DFS_HC) == 0)) - #define IS_QSPI_ENH_INST_DDR_EN(ENH_INST_DDR_EN) (((ENH_INST_DDR_EN) == QSPI_ENH_CTRL0_INST_DDR_EN) || ((ENH_INST_DDR_EN) == 0)) #define IS_QSPI_ENH_SPI_DDR_EN(ENH_SPI_DDR_EN) (((ENH_SPI_DDR_EN) == QSPI_ENH_CTRL0_SPI_DDR_EN) || ((ENH_SPI_DDR_EN) == 0)) @@ -234,8 +219,6 @@ typedef struct (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || \ ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE)) -#define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0)) - #define IS_QSPI_ENH_ADDR_LEN(ENH_ADDR_LEN) ((((ENH_ADDR_LEN) >= QSPI_ENH_CTRL0_ADDR_LEN_4_BIT) && ((ENH_ADDR_LEN) <= QSPI_ENH_CTRL0_ADDR_LEN_60_BIT)) || \ ((ENH_ADDR_LEN) == 0)) @@ -297,7 +280,8 @@ void QSPI_XIP_Cmd(bool cmd); void QSPI_DeInit(void); void QspiInitConfig(QSPI_InitType* QSPI_InitStruct); void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output); -void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel); +void QSPI_Tx_DMA_CTRL_Config(uint8_t Cmd,uint8_t TxDataLevel); +void QSPI_Rx_DMA_CTRL_Config(uint8_t Cmd, uint8_t RxDataLevel); uint16_t QSPI_GetITStatus(uint16_t FLAG); void QSPI_ClearITFLAG(uint16_t FLAG); void QSPI_XIP_ClearITFLAG(uint16_t FLAG); @@ -306,7 +290,6 @@ bool GetQspiTxDataBusyStatus(void); bool GetQspiTxDataEmptyStatus(void); bool GetQspiRxHaveDataStatus(void); bool GetQspiRxDataFullStatus(void); -bool GetQspiTransmitErrorStatus(void); bool GetQspiDataConflictErrorStatus(void); void QspiSendWord(uint32_t SendData); uint32_t QspiReadWord(void); diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_tim.h b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_tim.h index 5da1c9c5641cbcfa1e71bcc288964195493b88ba..6a6d2ac47a727340c440bf9fa64117c4654e1f92 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_tim.h +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/inc/n32g45x_tim.h @@ -568,19 +568,17 @@ typedef struct #define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010) #define TIM_DMABASE_BKDT ((uint16_t)0x0011) #define TIM_DMABASE_DMACTRL ((uint16_t)0x0012) -#define TIM_DMABASE_CAPCMPMOD3 ((uint16_t)0x0013) -#define TIM_DMABASE_CAPCMPDAT5 ((uint16_t)0x0014) -#define TIM_DMABASE_CAPCMPDAT6 ((uint16_t)0x0015) + + #define IsTimDmaBase(BASE) \ (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \ || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \ - || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMABASE_CAPCMPMOD3) \ + || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \ || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \ || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \ || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \ - || ((BASE) == TIM_DMABASE_CAPCMPDAT5) || ((BASE) == TIM_DMABASE_CAPCMPDAT6) || ((BASE) == TIM_DMABASE_BKDT) \ - || ((BASE) == TIM_DMABASE_DMACTRL)) + || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL)) /** * @} */ diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/misc.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/misc.c index 274a8058cb8aee365e661e0f8afa2668f38b79ff..f00bc465078a2ffab9fdd823b1153771b7b4a249 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/misc.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/misc.c @@ -199,7 +199,6 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) * @brief Configures the SysTick clock source. * @param SysTick_CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source. * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. */ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) @@ -210,10 +209,10 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) { SysTick->CTRL |= SysTick_CLKSource_HCLK; } - else - { - //SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } +// else +// { +// SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; +// } } /** diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_adc.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_adc.c index 0989c93c9f327327ced51f22b92efb8917107873..4ad6806cf81bcaa91e2a544403c7aaffa27e00e7 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_adc.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_adc.c @@ -703,7 +703,7 @@ uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx) /* Check the parameters */ assert_param(IsAdcModule(ADCx)); /* Return the dual mode conversion value */ - if(ADCx==ADC1 | ADCx==ADC2) + if((ADCx==ADC1) | (ADCx==ADC2)) return (uint32_t)ADC1->DAT; else return (uint32_t)ADC3->DAT; @@ -1414,7 +1414,23 @@ void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) ADCx->CTRL3 = tmpregister; return; } +/** + * @brief Set Adc Clock bits for AHB . + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + */ +void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx) +{ + ADCx->CTRL3 &= ADC_CLOCK_AHB; +} +/** + * @brief Set Adc Clock bits for PLL . + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + */ +void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx) +{ + ADCx->CTRL3 |= ADC_CLOCK_PLL; +} /** * @brief Configures the ADCHCLK prescaler. * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. @@ -1451,11 +1467,19 @@ void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler) { RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE); RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler); + ADC_AHB_Clock_Mode_Config(ADC1); + ADC_AHB_Clock_Mode_Config(ADC2); + ADC_AHB_Clock_Mode_Config(ADC3); + ADC_AHB_Clock_Mode_Config(ADC4); } else { RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE); RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1); + ADC_PLL_Clock_Mode_Config(ADC1); + ADC_PLL_Clock_Mode_Config(ADC2); + ADC_PLL_Clock_Mode_Config(ADC3); + ADC_PLL_Clock_Mode_Config(ADC4); } } /** diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_comp.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_comp.c index f8e0c53b1223fbcfddb69a395d1e56ffd28415f2..1f43a7a7471ecc413e8e3deacd8f661c9fda7525 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_comp.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_comp.c @@ -87,7 +87,7 @@ /** @addtogroup COMP_Private_Functions * @{ */ -#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit))) +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) #define ClrBit(reg, bit) ((reg) &= ~(bit)) #define SetBit(reg, bit) ((reg) |= (bit)) #define GetBit(reg, bit) ((reg) & (bit)) diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_exti.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_exti.c index 94e3598f0a224713efaf7eff1d9df2011d47beee..fb77e696236f457552b78017a9eb9e618ab2d49e 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_exti.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_exti.c @@ -28,7 +28,7 @@ /** * @file n32g45x_exti.c * @author Nations - * @version v1.0.0 + * @version v1.0.1 * * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. */ @@ -98,7 +98,7 @@ void EXTI_DeInit(void) EXTI->EMASK = 0x00000000; EXTI->RT_CFG = 0x00000000; EXTI->FT_CFG = 0x00000000; - EXTI->PEND = 0x000FFFFF; + EXTI->PEND = 0x003FFFFF; } /** diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_flash.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_flash.c index 236301e37715a0f4ff58dd279c3003a485c8af5a..fc8b38ba38bd3f59108d924d920ff7da2f88cbe6 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_flash.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_flash.c @@ -28,7 +28,7 @@ /** * @file n32g45x_flash.c * @author Nations - * @version v1.0.2 + * @version v1.0.3 * * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. */ @@ -408,7 +408,6 @@ FLASH_STS FLASH_EraseOB(void) FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data) { FLASH_STS status = FLASH_COMPL; - __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_i2c.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_i2c.c index 9b908b50442471d193f5f433d9b4b3de01675b53..f71765739e819a7fa73b05de67a974e467d132cf 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_i2c.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_i2c.c @@ -181,13 +181,31 @@ void I2C_DeInit(I2C_Module* I2Cx) /* Release I2C1 from reset state */ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE); } - else + else if (I2Cx == I2C2) { /* Enable I2C2 reset state */ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE); /* Release I2C2 from reset state */ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE); } + else if (I2Cx == I2C3) + { + /* Enable I2C2 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, ENABLE); + /* Release I2C2 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, DISABLE); + } + else if (I2Cx == I2C4) + { + /* Enable I2C4 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, ENABLE); + /* Release I2C4 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, DISABLE); + } + else + { + + } } /** @@ -231,11 +249,11 @@ void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) /* Set frequency bits depending on pclk1 value */ freqrange = (uint16_t)(pclk / 1000000); - if (freqrange > 36) + if (freqrange > 36) { freqrange = 36; } - /* Write to I2Cx CTRL2 */ + /* Write to I2Cx CTRL2 */ tmpregister |= freqrange; I2Cx->CTRL2 = tmpregister; diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_opamp.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_opamp.c index d8dd50db71629444cda18295933cc98f945c7c7e..9c39562eec2a3f5f4ce3f19b3481d907b6b59e36 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_opamp.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_opamp.c @@ -87,7 +87,7 @@ /** @addtogroup OPAMP_Private_Functions * @{ */ -#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit))) +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) #define ClrBit(reg, bit) ((reg) &= ~(bit)) #define SetBit(reg, bit) ((reg) |= (bit)) #define GetBit(reg, bit) ((reg) & (bit)) diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_qspi.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_qspi.c index e51b063b7139d1d1079c70a17a24465ed25ce5aa..692228defb601cf9ccee8d0128a536e15231fc8c 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_qspi.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_qspi.c @@ -98,15 +98,10 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct) assert_param(IS_QSPI_SDCN(QSPI_InitStruct->SDCN)); assert_param(IS_QSPI_ENH_CLK_STRETCH_EN(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN)); - assert_param(IS_QSPI_ENH_XIP_MBL(QSPI_InitStruct->ENHANCED_XIP_MBL)); - assert_param(IS_QSPI_ENH_XIP_CT_EN(QSPI_InitStruct->ENHANCED_XIP_CT_EN)); - assert_param(IS_QSPI_ENH_XIP_INST_EN(QSPI_InitStruct->ENHANCED_XIP_INST_EN)); - assert_param(IS_QSPI_ENH_XIP_DFS_HC(QSPI_InitStruct->ENHANCED_XIP_DFS_HC)); assert_param(IS_QSPI_ENH_INST_DDR_EN(QSPI_InitStruct->ENHANCED_INST_DDR_EN)); assert_param(IS_QSPI_ENH_SPI_DDR_EN(QSPI_InitStruct->ENHANCED_SPI_DDR_EN)); assert_param(IS_QSPI_ENH_WAIT_CYCLES(QSPI_InitStruct->ENHANCED_WAIT_CYCLES)); assert_param(IS_QSPI_ENH_INST_L(QSPI_InitStruct->ENHANCED_INST_L)); - assert_param(IS_QSPI_ENH_MD_BIT_EN(QSPI_InitStruct->ENHANCED_MD_BIT_EN)); assert_param(IS_QSPI_ENH_ADDR_LEN(QSPI_InitStruct->ENHANCED_ADDR_LEN)); assert_param(IS_QSPI_ENH_TRANS_TYPE(QSPI_InitStruct->ENHANCED_TRANS_TYPE)); @@ -165,10 +160,9 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct) QSPI->RS_DELAY = tmpregister; tmpregister = 0; - tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_XIP_MBL | QSPI_InitStruct->ENHANCED_XIP_CT_EN - | QSPI_InitStruct->ENHANCED_XIP_INST_EN | QSPI_InitStruct->ENHANCED_XIP_DFS_HC | QSPI_InitStruct->ENHANCED_INST_DDR_EN + tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_INST_DDR_EN | QSPI_InitStruct->ENHANCED_SPI_DDR_EN | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->ENHANCED_INST_L - | QSPI_InitStruct->ENHANCED_MD_BIT_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE); + | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE); QSPI->ENH_CTRL0 = tmpregister; tmpregister = 0; @@ -330,32 +324,48 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out break; } } + /** * @brief Configuration of QSPI DMA. - * @param TxRx transmit or receive data. + * @param Tx transmit or receive data. QSPI_DMA_CTRL_TX_DMA_EN:transmit data - QSPI_DMA_CTRL_RX_DMA_EN:receive data * @param TxDataLevel dma transmit data level. - * @param RxDataLevel dma receive data level. */ -void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel) +void QSPI_Tx_DMA_CTRL_Config(uint8_t Cmd,uint8_t TxDataLevel) { - assert_param(IS_QSPI_DMA_CTRL(TxRx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); assert_param(IS_QSPI_DMATDL_CTRL(TxDataLevel)); - assert_param(IS_QSPI_DMARDL_CTRL(RxDataLevel)); - - QSPI->DMA_CTRL = 0x00; - - if (TxRx & QSPI_DMA_CTRL_TX_DMA_EN) + if (Cmd) { QSPI->DMATDL_CTRL = TxDataLevel; QSPI->DMA_CTRL |= QSPI_DMA_CTRL_TX_DMA_EN; } - if (TxRx & QSPI_DMA_CTRL_RX_DMA_EN) + else + { + QSPI->DMA_CTRL &= ~QSPI_DMA_CTRL_TX_DMA_EN; + } +} + +/** + * @brief Configuration of QSPI DMA. + * @param Rx transmit or receive data. + QSPI_DMA_CTRL_RX_DMA_EN:receive data + * @param RxDataLevel dma receive data level. + */ +void QSPI_Rx_DMA_CTRL_Config(uint8_t Cmd, uint8_t RxDataLevel) +{ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_QSPI_DMARDL_CTRL(RxDataLevel)); + + if (Cmd) { QSPI->DMARDL_CTRL = RxDataLevel; QSPI->DMA_CTRL |= QSPI_DMA_CTRL_RX_DMA_EN; } + else + { + QSPI->DMA_CTRL &= ~QSPI_DMA_CTRL_RX_DMA_EN; + } } /** * @brief Get the flag of interrupt status register. @@ -376,18 +386,19 @@ uint16_t QSPI_GetITStatus(uint16_t FLAG) */ void QSPI_ClearITFLAG(uint16_t FLAG) { - volatile uint16_t tmp = 0; - if (FLAG == QSPI_ISTS_TXFOIS) - tmp = QSPI->TXFOI_CLR; - if (FLAG == QSPI_ISTS_RXFOIS) - tmp = QSPI->RXFOI_CLR; - if (FLAG == QSPI_ISTS_RXFUIS) - tmp = QSPI->RXFUI_CLR; - if (FLAG == QSPI_ISTS_MMCIS) - tmp = QSPI->MMC_CLR; - if (FLAG == QSPI_ISTS) - tmp = QSPI->ICLR; + (void)QSPI->TXFOI_CLR; + else if (FLAG == QSPI_ISTS_RXFOIS) + (void)QSPI->RXFOI_CLR; + else if (FLAG == QSPI_ISTS_RXFUIS) + (void)QSPI->RXFUI_CLR; + else if (FLAG == QSPI_ISTS_MMCIS) + (void)QSPI->MMC_CLR; + else if (FLAG == QSPI_ISTS) + (void)QSPI->ICLR; + else + { + } } /** * @brief Clear the flag of related interrupt register. @@ -395,10 +406,11 @@ void QSPI_ClearITFLAG(uint16_t FLAG) */ void QSPI_XIP_ClearITFLAG(uint16_t FLAG) { - volatile uint16_t tmp = 0; - if (FLAG == QSPI_XIP_RXFOI_CLR_XRXFOIC) - tmp = QSPI->XIP_RXFOI_CLR; + (void)QSPI->XIP_RXFOI_CLR; + else + { + } } /** * @brief Get QSPI status,busy or not. @@ -450,16 +462,7 @@ bool GetQspiRxDataFullStatus(void) return 1; return 0; } -/** - * @brief Check transmit error or not. - * @return 1: Transmit error;0: No transmit error. - */ -bool GetQspiTransmitErrorStatus(void) -{ - if ((QSPI->STS & 0x20) == 0x20) - return 1; - return 0; -} + /** * @brief Check data conflict error or not. * @return 1: Data conflict error;0: No data conflict error. diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rcc.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rcc.c index 914a7f2d81206b31b42cf34c80da4783a9615e0b..8c1f892057ce96df5ffc9d5e2c2408016564b122 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rcc.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rcc.c @@ -28,7 +28,7 @@ /** * @file n32g45x_rcc.c * @author Nations - * @version v1.0.1 + * @version v1.0.2 * * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. */ @@ -225,7 +225,7 @@ void RCC_DeInit(void) RCC->CFG2 = 0x00003800; /* Reset CFG3 register */ - RCC->CFG3 = 0x00003800; + RCC->CFG3 = 0x00003840; /* Disable all interrupts and clear pending bits */ RCC->CLKINT = 0x009F0000; diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rtc.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rtc.c index 8a65046ab8d88272818510c035806b23ed544476..9fbdd434fc4f7d6a027e9f0a8cdb20bd03f5e21b 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rtc.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_rtc.c @@ -1345,7 +1345,6 @@ uint32_t RTC_GetStoreOperation(void) */ void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) { - __IO uint32_t temp = 0; /* Check the parameters */ assert_param(IS_RTC_OUTPUT_MODE(RTC_Output)); assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); diff --git a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_tim.c b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_tim.c index 41e441db654072d245698158a85c06e56398acab..c8a774e816e91d67d3018bfdf12c3ef24a182394 100644 --- a/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_tim.c +++ b/drivers/hal/nationstech/N32G45x/n32g45x_std_periph_driver/src/n32g45x_tim.c @@ -1056,8 +1056,7 @@ void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource) * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR, * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2, * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT, - * TIM_DMABASE_CAPCMPMOD3, TIM_DMABASE_CAPCMPDAT5, TIM_DMABASE_CAPCMPDAT6, - * TIM_DMABASE_DMACTRL. + * TIM_DMABASE_DMACTRL. * @param TIM_DMABurstLength DMA Burst length. * This parameter can be one value between: * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS. diff --git a/drivers/hal/nationstech/N32G45x/weave.yaml b/drivers/hal/nationstech/N32G45x/weave.yaml index 6df83df1f516c07a0ef913a41c56ad5217758b98..72ec336db608591b6c79255578615267aea1d843 100644 --- a/drivers/hal/nationstech/N32G45x/weave.yaml +++ b/drivers/hal/nationstech/N32G45x/weave.yaml @@ -3,33 +3,31 @@ group_name: hal/lowlevel # 依赖宏控 depend_macro: - - SERIES_N32G4XX + - SERIES_N32G45X # 编译连接信息 build_option: cpppath: - n32g45x_std_periph_driver/inc - - CMSIS/device - CMSIS/core - cppdefines: - - USE_STDPERIPH_DRIVER + - CMSIS/device # 源码 source_file: - - CMSIS/device/system_n32g45x.c - - n32g45x_std_periph_driver/src/n32g45x_rcc.c - - n32g45x_std_periph_driver/src/misc.c - - n32g45x_std_periph_driver/src/n32g45x_gpio.c - - n32g45x_std_periph_driver/src/n32g45x_exti.c ? {is_define("OS_USING_PIN")} - - n32g45x_std_periph_driver/src/n32g45x_iwdg.c ? {is_define("OS_USING_WDG")} - - n32g45x_std_periph_driver/src/n32g45x_usart.c ? {is_define("OS_USING_SERIAL")} - - n32g45x_std_periph_driver/src/n32g45x_adc.c ? {is_define("OS_USING_ADC")} - - n32g45x_std_periph_driver/src/n32g45x_dac.c ? {is_define("OS_USING_DAC")} - - n32g45x_std_periph_driver/src/n32g45x_i2c.c ? {is_define("OS_USING_I2C")} - - n32g45x_std_periph_driver/src/n32g45x_spi.c ? {is_define("OS_USING_SPI")} - - n32g45x_std_periph_driver/src/n32g45x_flash.c ? {is_define("OS_USING_FAL")} - - n32g45x_std_periph_driver/src/n32g45x_dma.c ? {is_define("OS_USING_DMA")} - - n32g45x_std_periph_driver/src/n32g45x_rtc.c ? {is_define("BSP_USING_RTC")} - - n32g45x_std_periph_driver/src/n32g45x_pwr.c ? {is_define("BSP_USING_RTC")} - - n32g45x_std_periph_driver/src/n32g45x_tim.c ? {is_define("BSP_USING_TIMER")} - - n32g45x_std_periph_driver/src/n32g45x_eth.c ? {is_define("BSP_USING_ETH")} + - CMSIS/device/system_n32g45x.c + - n32g45x_std_periph_driver/src/n32g45x_rcc.c + - n32g45x_std_periph_driver/src/misc.c + - n32g45x_std_periph_driver/src/n32g45x_gpio.c + - n32g45x_std_periph_driver/src/n32g45x_exti.c ? {is_define("OS_USING_PIN")} + - n32g45x_std_periph_driver/src/n32g45x_iwdg.c ? {is_define("OS_USING_WDG")} + - n32g45x_std_periph_driver/src/n32g45x_usart.c ? {is_define("OS_USING_SERIAL")} + - n32g45x_std_periph_driver/src/n32g45x_adc.c ? {is_define("OS_USING_ADC")} + - n32g45x_std_periph_driver/src/n32g45x_dac.c ? {is_define("OS_USING_DAC")} + - n32g45x_std_periph_driver/src/n32g45x_i2c.c ? {is_define("OS_USING_I2C")} + - n32g45x_std_periph_driver/src/n32g45x_spi.c ? {is_define("OS_USING_SPI")} + - n32g45x_std_periph_driver/src/n32g45x_flash.c ? {is_define("OS_USING_FAL")} + - n32g45x_std_periph_driver/src/n32g45x_dma.c ? {is_define("OS_USING_DMA")} + - n32g45x_std_periph_driver/src/n32g45x_rtc.c ? {is_define("BSP_USING_RTC")} + - n32g45x_std_periph_driver/src/n32g45x_pwr.c ? {is_define("BSP_USING_RTC")} + - n32g45x_std_periph_driver/src/n32g45x_tim.c ? {is_define("BSP_USING_TIMER")} + - n32g45x_std_periph_driver/src/n32g45x_eth.c ? {is_define("BSP_USING_ETH")} diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_common_tables.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfea7460e9a79e5b20670d947e6a52a894b29801 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_const_structs.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..80a3e8bbe72b8c54f34a0f40aa1e01f2bfb3308f --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_math.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9dd26aa8110a0a90babc7b297c5bc6d5eb4216 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armcc.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..4d9d0645d3f747970c52d076595c6fcd9187e6e5 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armclang.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..162a400ea1b01605d779037e697abb2b678fc802 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_compiler.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..adfd3c2504294bbc9f70a3b3db978b3095961d65 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_gcc.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..2d9db15a5def3461f91ec54855611284379cde32 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_iccarm.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..931db1d5141e0361e621bb5796f12804ffdfbc5f --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_version.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/core_cm4.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..7d56873532c3144c832911d9aba3f1944d32d290 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/core/mpu_armv7.h b/drivers/hal/nationstech/N32L40x/CMSIS/core/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..01422033d087616db42542f90a0ce27e42fd0ad4 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/core/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x.h b/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x.h new file mode 100644 index 0000000000000000000000000000000000000000..02164ab6f50402d7dad5406a5865ca78e53459aa --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x.h @@ -0,0 +1,7921 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_H__ +#define __N32L40X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup n32l40x_Library_Basic + * @{ + */ + +#if !defined USE_STDPERIPH_DRIVER +/* + * Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_STDPERIPH_DRIVER +#endif + +/* + * In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE +#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/* + * In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */ + +#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/ + +#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/ + +#define __N32L40X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ +#define __N32L40X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __N32L40X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __N32L40X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ + +/** + * @brief n32l40x Standard Peripheral Library version number + */ +#define __N32L40X_STDPERIPH_VERSION \ + ((__N32L40X_STDPERIPH_VERSION_MAIN << 24) | (__N32L40X_STDPERIPH_VERSION_SUB1 << 16) \ + | (__N32L40X_STDPERIPH_VERSION_SUB2 << 8) | (__N32L40X_STDPERIPH_VERSION_RC)) + +/* + * Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#ifdef N32L40X +#define __MPU_PRESENT 1 /*!< n32l40x devices does not provide an MPU */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#endif /* n32l40x */ +#define __NVIC_PRIO_BITS 4 /*!< n32l40x uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief n32l40x Interrupt Number Definition + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** n32l40x specific Interrupt Numbers ********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */ + RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */ + DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */ + DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */ + DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */ + DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */ + DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */ + DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */ + DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */ + ADC_IRQn = 19, /*!< ADC global Interrupt */ + USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */ + USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */ + COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + UART4_IRQn = 47, /*!< UART4 global Interrupt */ + UART5_IRQn = 48, /*!< UART5 global Interrupt */ + LPUART_IRQn = 49, /*!< LPUART global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + TIM6_IRQn = 51, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 52, /*!< TIM7 global Interrupt */ + CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */ + CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */ + LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */ + LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */ + LCD_IRQn = 59, /*!< LCD global interrupt through EXTI line 26 */ + SAC_IRQn = 60, /*!< SAC global Interrupt */ + MMU_IRQn = 61, /*!< MMU global Interrupt */ + TSC_IRQn = 62, /*!< TSC global Interrupt */ + RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */ + TIM9_IRQn = 64, /*!< TIM9 global interrupt */ + UCDR_IRQn = 65, /*!< UCDR error interrupt */ + +} IRQn_Type; + +#include "core_cm4.h" +#include "system_n32l40x.h" +#include +#include + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, + INTStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/* n32l40x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t SAMPT1; + __IO uint32_t SAMPT2; + __IO uint32_t JOFFSET1; + __IO uint32_t JOFFSET2; + __IO uint32_t JOFFSET3; + __IO uint32_t JOFFSET4; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t RSEQ1; + __IO uint32_t RSEQ2; + __IO uint32_t RSEQ3; + __IO uint32_t JSEQ; + __IO uint32_t JDAT1; + __IO uint32_t JDAT2; + __IO uint32_t JDAT3; + __IO uint32_t JDAT4; + __IO uint32_t DAT; + __IO uint32_t DIFSEL; + __IO uint32_t CALFACT; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT3; +} ADC_Module; + +/** + * @brief OPAMP + */ +typedef struct +{ + __IO uint32_t CS1; + __IO uint32_t RES1[3]; + __IO uint32_t CS2; + __IO uint32_t RES2[3]; + __IO uint32_t LOCK; +} OPAMP_Module; + +/** + * @brief COMP_Single + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; +} COMP_SingleType; + +/** + * @brief COMP + */ +typedef struct +{ + __IO uint32_t INTEN; + __IO uint32_t LPCKSEL; + __IO uint32_t WINMODE; + __IO uint32_t LOCK; + COMP_SingleType Cmp1; + __IO uint32_t RES; + COMP_SingleType Cmp2; + __IO uint32_t CMP2OSEL; + __IO uint32_t VREFSCL; + __IO uint32_t TEST; + __IO uint32_t INTSTS; +} COMP_Module; + +/** + * @brief AFEC + */ + +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + //uint32_t RESERVED0; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; +} AFEC_Module; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMDT; + __IO uint32_t TMDL; + __IO uint32_t TMDH; +} CAN_TxMailBox_Param; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RMI; + __IO uint32_t RMDT; + __IO uint32_t RMDL; + __IO uint32_t RMDH; +} CAN_FIFOMailBox_Param; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_Param; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; + __IO uint32_t MSTS; + __IO uint32_t TSTS; + __IO uint32_t RFF0; + __IO uint32_t RFF1; + __IO uint32_t INTE; + __IO uint32_t ESTS; + __IO uint32_t BTIM; + uint32_t RESERVED0[88]; + CAN_TxMailBox_Param sTxMailBox[3]; + CAN_FIFOMailBox_Param sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMC; + __IO uint32_t FM1; + uint32_t RESERVED2; + __IO uint32_t FS1; + uint32_t RESERVED3; + __IO uint32_t FFA1; + uint32_t RESERVED4; + __IO uint32_t FA1; + uint32_t RESERVED5[8]; + CAN_FilterRegister_Param sFilterRegister[14]; +} CAN_Module; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t CRC32DAT; /*!< CRC data register */ + __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/ + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CRC32CTRL; /*!< CRC control register */ + __IO uint32_t CRC16CTRL; + __IO uint8_t CRC16DAT; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint16_t CRC16D; + uint16_t RESERVED4; + __IO uint8_t LRC; + uint8_t RESERVED5; + uint16_t RESERVED6; +} CRC_Module; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SOTTR; + __IO uint32_t DR12CH; + __IO uint32_t DL12CH; + __IO uint32_t DR8CH; + __IO uint32_t DATO; + +} DAC_Module; +/** + * @brief USB + */ + +typedef struct +{ + __IO uint32_t EP0; + __IO uint32_t EP1; + __IO uint32_t EP2; + __IO uint32_t EP3; + __IO uint32_t EP4; + __IO uint32_t EP5; + __IO uint32_t EP6; + __IO uint32_t EP7; + __IO uint32_t Reserve20h; + __IO uint32_t Reserve24h; + __IO uint32_t Reserve28h; + __IO uint32_t Reserve2Ch; + __IO uint32_t Reserve30h; + __IO uint32_t Reserve34h; + __IO uint32_t Reserve38h; + __IO uint32_t Reserve3Ch; + __IO uint32_t CTRL; + __IO uint32_t STS; + __IO uint32_t FN; + __IO uint32_t ADDR; + __IO uint32_t BUFTAB; +} USB_Module; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t CTRL; +} DBG_Module; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CHCFG; + __IO uint32_t TXNUM; + __IO uint32_t PADDR; + __IO uint32_t MADDR; + __IO uint32_t CHSEL; + +} DMA_ChannelType; + +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO DMA_ChannelType DMA_Channel[8]; +} DMA_Module; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMASK; /*offset 0x00*/ + __IO uint32_t EMASK; /*offset 0x04*/ + __IO uint32_t RT_CFG; /*offset 0x08*/ + __IO uint32_t FT_CFG; /*offset 0x0C*/ + __IO uint32_t SWIE; /*offset 0x10*/ + __IO uint32_t PEND; /*offset 0x14*/ + __IO uint32_t TS_SEL; /*offset 0x18*/ +} EXTI_Module; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t AC; + __IO uint32_t KEYR; + __IO uint32_t OPTKEY; + __IO uint32_t STS; + __IO uint32_t CTRL; + __IO uint32_t ADD; + __IO uint32_t OB2; + __IO uint32_t OB; + __IO uint32_t WRP; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t RESERVED2; + __IO uint32_t CAHR; +} FLASH_Module; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t WRP1_WRP0; + __IO uint32_t WRP3_WRP2; + __IO uint32_t USER2_RDP2; +} OB_Module; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t PMODE; /*offset 0x00*/ + __IO uint32_t POTYPE; /*offset 0x04*/ + __IO uint32_t SR; /*offset 0x08*/ + __IO uint32_t PUPD; /*offset 0x0C*/ + __IO uint32_t PID; /*offset 0x10*/ + __IO uint32_t POD; /*offset 0x14*/ + __IO uint32_t PBSC; /*offset 0x18*/ + __IO uint32_t PLOCK; /*offset 0x1C*/ + __IO uint32_t AFL; /*offset 0x20*/ + __IO uint32_t AFH; /*offset 0x24*/ + __IO uint32_t PBC; /*offset 0x28*/ + __IO uint32_t DS; /*offset 0x2C*/ + +} GPIO_Module; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t RMP_CFG; + __IO uint32_t EXTI_CFG[4]; +} AFIO_Module; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DAT; + uint16_t RESERVED4; + __IO uint16_t STS1; + uint16_t RESERVED5; + __IO uint16_t STS2; + uint16_t RESERVED6; + __IO uint16_t CLKCTRL; + uint16_t RESERVED7; + __IO uint16_t TMRISE; + uint16_t RESERVED8; +} I2C_Module; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t PREDIV; /*!< IWDG PREDIV */ + __IO uint32_t RELV; + __IO uint32_t STS; +} IWDG_Module; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; + __IO uint32_t STS1; + __IO uint32_t STS2; + __IO uint32_t STSCLR; +} PWR_Module; +/** + * @brief Low-Power Timer + */ +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO uint32_t INTEN; + __IO uint32_t CFG; + __IO uint32_t CTRL; + __IO uint32_t COMPx; + __IO uint32_t ARR; + __IO uint32_t CNT; + +} LPTIM_Module; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t CLKINT; + __IO uint32_t APB2PRST; + __IO uint32_t APB1PRST; + __IO uint32_t AHBPCLKEN; + __IO uint32_t APB2PCLKEN; + __IO uint32_t APB1PCLKEN; + __IO uint32_t LDCTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t AHBPRST; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t RDCTRL; + __IO uint32_t Reserve0; + __IO uint32_t Reserve1; + __IO uint32_t PLLHSIPRE; + __IO uint32_t SRAM_CTRLSTS; +} RCC_Module; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved0; /*!< Reserved */ + __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */ + __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */ +} RTC_Module; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t STS; + uint16_t RESERVED2; + __IO uint16_t DAT; + uint16_t RESERVED3; + __IO uint16_t CRCPOLY; + uint16_t RESERVED4; + __IO uint16_t CRCRDAT; + uint16_t RESERVED5; + __IO uint16_t CRCTDAT; + uint16_t RESERVED6; + __IO uint16_t I2SCFG; + uint16_t RESERVED7; + __IO uint16_t I2SPREDIV; + uint16_t RESERVED8; +} SPI_Module; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint16_t SMCTRL; + uint16_t RESERVED1; + __IO uint16_t DINTEN; + uint16_t RESERVED2; + __IO uint32_t STS; + __IO uint16_t EVTGEN; + uint16_t RESERVED3; + __IO uint16_t CCMOD1; + uint16_t RESERVED4; + __IO uint16_t CCMOD2; + uint16_t RESERVED5; + __IO uint32_t CCEN; + __IO uint16_t CNT; + uint16_t RESERVED6; + __IO uint16_t PSC; + uint16_t RESERVED7; + __IO uint16_t AR; + uint16_t RESERVED8; + __IO uint16_t REPCNT; + uint16_t RESERVED9; + __IO uint16_t CCDAT1; + uint16_t RESERVED10; + __IO uint16_t CCDAT2; + uint16_t RESERVED11; + __IO uint16_t CCDAT3; + uint16_t RESERVED12; + __IO uint16_t CCDAT4; + uint16_t RESERVED13; + __IO uint16_t BKDT; + uint16_t RESERVED14; + __IO uint16_t DCTRL; + uint16_t RESERVED15; + __IO uint16_t DADDR; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t CCMOD3; + uint16_t RESERVED18; + __IO uint16_t CCDAT5; + uint16_t RESERVED19; + __IO uint16_t CCDAT6; + uint16_t RESERVED20; +} TIM_Module; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint16_t DAT; + uint16_t RESERVED1; + __IO uint16_t BRCF; + uint16_t RESERVED2; + __IO uint16_t CTRL1; + uint16_t RESERVED3; + __IO uint16_t CTRL2; + uint16_t RESERVED4; + __IO uint16_t CTRL3; + uint16_t RESERVED5; + __IO uint16_t GTP; + uint16_t RESERVED6; +} USART_Module; + +/** + * @brief Low-power Universal Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint8_t INTEN; + uint8_t RESERVED1; + uint16_t RESERVED2; + __IO uint16_t CTRL; + uint16_t RESERVED3; + __IO uint16_t BRCFG1; + uint16_t RESERVED4; + __IO uint8_t DAT; + uint8_t RESERVED5; + uint16_t RESERVED6; + __IO uint8_t BRCFG2; + uint8_t RESERVED7; + uint16_t RESERVED8; + __IO uint32_t WUDAT; +} LPUART_Module; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t STS; +} WWDG_Module; + +/** + * @brief LCD Controller + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FCTRL; + __IO uint32_t STS; + __IO uint32_t CLR; + uint32_t RESERVED; + __IO uint32_t RAM_COM[16]; +} LCD_Module; + +/** + * @brief Touch Sensor Controller + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CHNEN; + __IO uint32_t STS; + __IO uint32_t RESERVED; + __IO uint32_t ANA_CTRL; + __IO uint32_t ANA_SEL; + __IO uint32_t RESR[3]; +// __IO uint32_t RESR0; +// __IO uint32_t RESR1; +// __IO uint32_t RESR2; + __IO uint32_t THRHD[24]; +// __IO uint32_t THRHD0; +// __IO uint32_t THRHD1; +// __IO uint32_t THRHD2; +// __IO uint32_t THRHD3; +// __IO uint32_t THRHD4; +// __IO uint32_t THRHD5; +// __IO uint32_t THRHD6; +// __IO uint32_t THRHD7; +// __IO uint32_t THRHD8; +// __IO uint32_t THRHD9; +// __IO uint32_t THRHD10; +// __IO uint32_t THRHD11; +// __IO uint32_t THRHD12; +// __IO uint32_t THRHD13; +// __IO uint32_t THRHD14; +// __IO uint32_t THRHD15; +// __IO uint32_t THRHD16; +// __IO uint32_t THRHD17; +// __IO uint32_t THRHD18; +// __IO uint32_t THRHD19; +// __IO uint32_t THRHD20; +// __IO uint32_t THRHD21; +// __IO uint32_t THRHD22; +// __IO uint32_t THRHD23; + +} TSC_Module; + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */ +#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */ +#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */ +#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */ +#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000) + +/* APB1 */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000) +#define COMP_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define TSC_BASE (APB1PERIPH_BASE + 0x3400) + +#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00) +#define LCD_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00) +#define LPUART_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00) +#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/* APB2 */ +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00) +#define UART4_BASE (APB2PERIPH_BASE + 0x5000) +#define UART5_BASE (APB2PERIPH_BASE + 0x5400) + +/* AHB */ +#define DMA_BASE (AHBPERIPH_BASE + 0x8000) +#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008) +#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C) +#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030) +#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044) +#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058) +#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C) +#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080) +#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094) +#define ADC_BASE (AHBPERIPH_BASE + 0x8800) +#define RCC_BASE (AHBPERIPH_BASE + 0x9000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0xB000) +#define SAC_BASE (AHBPERIPH_BASE + 0xC000) +#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400) +#define MMU_BASE (AHBPERIPH_BASE + 0xCC00) + +#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +#define TIM2 ((TIM_Module*)TIM2_BASE) +#define TIM3 ((TIM_Module*)TIM3_BASE) +#define TIM4 ((TIM_Module*)TIM4_BASE) +#define TIM5 ((TIM_Module*)TIM5_BASE) +#define TIM6 ((TIM_Module*)TIM6_BASE) +#define TIM7 ((TIM_Module*)TIM7_BASE) +#define AFEC ((AFEC_Module*)AFEC_BASE) +#define OPAMP ((OPAMP_Module*)OPAMP_BASE) +#define COMP ((COMP_Module*)COMP_BASE) +#define RTC ((RTC_Module*)RTC_BASE) +#define WWDG ((WWDG_Module*)WWDG_BASE) +#define IWDG ((IWDG_Module*)IWDG_BASE) +#define TSC ((TSC_Module*)TSC_BASE) + +#define TIM9 ((TIM_Module*)TIM9_BASE) +#define LCD ((LCD_Module*)LCD_BASE) +#define USART2 ((USART_Module*)USART2_BASE) +#define USART3 ((USART_Module*)USART3_BASE) +#define LPTIM ((LPTIM_Module*)LPTIM_BASE) +#define LPUART ((LPUART_Module*)LPUART_BASE) +#define I2C1 ((I2C_Module*)I2C1_BASE) +#define I2C2 ((I2C_Module*)I2C2_BASE) +#define USB ((USB_Module*)USB_BASE) +#define CAN ((CAN_Module*)CAN_BASE) +#define PWR ((PWR_Module*)PWR_BASE) +#define DAC ((DAC_Module*)DAC_BASE) +#define AFIO ((AFIO_Module*)AFIO_BASE) +#define EXTI ((EXTI_Module*)EXTI_BASE) +#define GPIOA ((GPIO_Module*)GPIOA_BASE) +#define GPIOB ((GPIO_Module*)GPIOB_BASE) +#define GPIOC ((GPIO_Module*)GPIOC_BASE) +#define GPIOD ((GPIO_Module*)GPIOD_BASE) +#define TIM1 ((TIM_Module*)TIM1_BASE) +#define SPI1 ((SPI_Module*)SPI1_BASE) +#define TIM8 ((TIM_Module*)TIM8_BASE) +#define USART1 ((USART_Module*)USART1_BASE) +#define SPI2 ((SPI_Module*)SPI2_BASE) +#define UART4 ((USART_Module*)UART4_BASE) +#define UART5 ((USART_Module*)UART5_BASE) +#define DMA ((DMA_Module*)DMA_BASE) +#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE) +#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE) +#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE) +#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE) +#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE) +#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE) +#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE) +#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE) +#define ADC ((ADC_Module*)ADC_BASE) +#define RCC ((RCC_Module*)RCC_BASE) +#define FLASH ((FLASH_Module*)FLASH_R_BASE) +#define OBT ((OB_Module*)OB_BASE) +#define CRC ((CRC_Module*)CRC_BASE) + +#define DBG ((DBG_Module*)DBG_BASE) + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_CRC32DAT register *********************/ +#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_CRC32IDAT register ********************/ +#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CRC32CTRL register ********************/ +#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************** Bit definition for CRC16_CR register ********************/ +#define CRC16_CTRL_LITTLE ((uint8_t)0x02) +#define CRC16_CTRL_BIG ((uint8_t)0xFD) + +#define CRC16_CTRL_RESET ((uint8_t)0x04) +#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CTRL1 register ********************/ +#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */ +#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */ +#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */ + + +#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */ + +#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */ +#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */ +#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */ +#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */ + +#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */ +#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */ +/******************** Bit definition for PWR_CTRL2 register ********************/ +#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */ +#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */ +#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */ +#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */ +#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */ +#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */ +#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */ +#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */ +#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */ + +#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */ + + +/******************** Bit definition for PWR_CTRL3 register ********************/ +#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby . */ +#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby . */ +#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby. */ +#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */ +#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */ +#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */ +#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */ +#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */ +#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */ +#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */ + +#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */ +#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */ +#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */ +#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */ +#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */ + +#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */ +#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */ +#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */ +/******************** Bit definition for PWR_STS1 register ********************/ +#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP0. */ +#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */ +#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */ +#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */ +#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */ + +/******************** Bit definition for PWR_STS2 register ********************/ +#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */ +#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */ +#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */ + +/******************** Bit definition for PWR_STSCLR register ********************/ +#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF3 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */ + + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTRL register ********************/ +#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */ +#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */ +#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +/******************* Bit definition for RCC_CFG register *******************/ +/*!< SW configuration */ +#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */ +#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */ + +/*!< AHBPRES configuration */ +#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */ +#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< APB1PRES configuration */ +#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */ +#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< APB2PRES configuration */ +#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */ +#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< PLLSRC configuration */ +#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */ +#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + +/*!< PLLXTPRE configuration */ +#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ +#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */ +#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */ +#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */ + +#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ +#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ +#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ +#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ +#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ +#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ +#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ +#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */ +#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ +#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ +#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ +#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ +#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ +#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ +#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ +#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ +#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ +#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ +#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ +#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ +#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ +#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ +#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ +#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ +#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ +#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ +#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ +#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ +#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ + +/*!< USBPRES configuration */ +#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */ +#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ +#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */ +#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */ + +/*!< MCO configuration */ +#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */ +#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */ +#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */ +#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ +#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ +#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ +#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */ + +/*!< MCOPRE configuration */ +#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by + software to generate MCOPRE clock.) */ +#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */ +#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */ + +#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */ +#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */ +#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */ +#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */ +#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */ +#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */ +#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */ +#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */ +#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */ +#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */ +#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */ +#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */ +#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */ +#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */ +#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */ + +/*!<****************** Bit definition for RCC_CLKINT register ********************/ +#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */ +#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */ +#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */ +#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */ +#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */ +#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ +#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */ +#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */ +#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRST register *****************/ +#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ +#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ +#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */ +#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */ +#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */ + +/***************** Bit definition for RCC_APB1PRST register *****************/ +#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ +#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */ +#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */ +#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */ +#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */ +#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */ + +/****************** Bit definition for RCC_AHBPCLKEN register ******************/ +#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */ +#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ +#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */ +#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */ +#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */ + +/****************** Bit definition for RCC_APB2PCLKEN register *****************/ +#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ +#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ +#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ +#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */ +#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */ +#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */ + +/***************** Bit definition for RCC_APB1PCLKEN register ******************/ +#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ +#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */ +#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */ +#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */ +#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */ +#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */ +#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */ + +/******************* Bit definition for RCC_LDCTRL register *******************/ +#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */ +#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */ +#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC clock source selection) */ + +#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */ +#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */ +#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */ + +/******************* Bit definition for RCC_CTRLSTS register ********************/ +#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */ +#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */ + +#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */ +#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */ + +#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */ +#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */ +#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */ +#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */ +#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */ +#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */ +#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */ + +#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */ +#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */ +#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */ +#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBPRST register ****************/ +#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */ +#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */ +#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */ + +/******************* Bit definition for RCC_CFG2 register ******************/ +/*!< ADCHPRE configuration */ +#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */ +#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */ +#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */ +#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */ +#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */ +#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */ +#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */ +#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */ +#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */ +#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ +#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ + +/*!< ADCPLLPRES configuration */ +#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */ +#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ +#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */ + +#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */ +#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */ +#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */ +#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */ +#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */ +#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */ +#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */ +#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */ +#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */ +#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */ +#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */ +#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */ +#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */ +#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */ + +/*!< ADC1MPRE configuration */ +#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */ +#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */ +#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */ +#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */ + +#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */ +#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */ +#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */ +#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */ +#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */ +#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */ +#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */ +#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */ +#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */ +#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */ +#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */ +#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */ +#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */ +#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */ +#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */ +#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */ +#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */ +#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */ +#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */ +#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */ +#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */ +#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */ +#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */ +#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */ +#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */ +#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */ +#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */ +#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */ +#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */ +#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */ +#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */ +#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */ + +/*!< ADC1MSEL configuration */ +#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */ + +#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */ +#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */ + +/*!< RNGCPRE configuration */ +#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */ +#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */ + +#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */ +#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */ +#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */ +#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */ +#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */ +#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */ +#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */ +#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */ +#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */ +#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */ +#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */ +#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */ +#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */ +#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */ +#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */ +#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */ +#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */ +#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */ +#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */ +#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */ +#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */ +#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */ +#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */ +#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */ +#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */ +#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */ +#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */ +#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */ +#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */ +#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */ +#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */ +#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */ + +/*!< TIMCLK_SEL configuration */ +#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */ + +#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */ +#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */ + +/******************* Bit definition for RCC_CFG3 register ******************/ +/*!< UCDREN configuration */ +#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */ + +#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */ +#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */ + +/*!< USBXTALESS configuration */ +#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */ + +#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */ +#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */ + +/*!< UCDR300MSEL configuration */ +#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */ + +#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */ +#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */ + +/*!< TRNG1MPRE configuration */ +#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */ +#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ +#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ +#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ + +#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */ +#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */ +#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */ +#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */ +#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */ +#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */ +#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */ +#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */ +#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */ +#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */ +#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */ +#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */ +#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */ +#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */ +#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */ +#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */ +#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */ +#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */ +#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */ +#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */ +#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */ +#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */ +#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */ +#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */ +#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */ +#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */ +#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */ +#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */ +#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */ +#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */ +#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */ + +/*!< TRNG1MSEL configuration */ +#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */ + +#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */ +#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */ + +/*!< TRNG1MEN configuration */ +#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */ +#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +/******************* Bit definition for RCC_RDCTRL register ******************/ +/*!< LPTIMSEL congiguration */ +#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */ +#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */ + +/*!< LPUARTSEL congiguration */ +#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */ +#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */ + +#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */ +#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */ +#define RCC_RDCTRL_LCDEN ((uint32_t)0x00000100) /*!< LCD clock enable */ + +#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */ +#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */ +#define RCC_RDCTRL_LCDRST ((uint32_t)0x00001000) /*!< LCD reset */ + + +/******************* Bit definition for RCC_PLLHSIPRE register ******************/ +/*!< PLLHSIPRE configuration */ +#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */ + +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */ + +/*!< PLLSRCDIV configuration */ +#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */ + +#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */ + +/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/ +#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */ +#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */ + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD \ + ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */ +#define SCB_ICSR_RETTOBASE \ + ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT \ + ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 \ + ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 \ + ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 \ + ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 \ + ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 \ + ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 \ + ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 \ + ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 \ + ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA \ + ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND \ + ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \ + Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN \ + ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N \ + ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 \ + ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 \ + ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 \ + ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED \ + ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO \ + ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL \ + ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED \ + ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTSTS register ********************/ +#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ +#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTCLR register *******************/ +#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ +#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CHCFG1 register *******************/ +#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG2 register *******************/ +#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG3 register *******************/ +#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CHCFG4 register *******************/ +#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CHCFG5 register *******************/ +#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG6 register *******************/ +#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG7 register *******************/ +#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG8 register *******************/ +#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_TXNUM1 register ******************/ +#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM2 register ******************/ +#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM3 register ******************/ +#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM4 register ******************/ +#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM5 register ******************/ +#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM6 register ******************/ +#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM7 register ******************/ +#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM8 register ******************/ +#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STS register ********************/ +#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */ +#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */ +#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */ + + +/******************* Bit definition for ADC_CTRL1 register ********************/ +#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTRL2 register ********************/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CTRL2_EXTJSEL \ + ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */ +#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPT1 register *******************/ +#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SAMPT2 register *******************/ +#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFFSET1 register *******************/ +#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFFSET2 register *******************/ +#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFFSET3 register *******************/ +#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFFSET4 register *******************/ +#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDGHIGH register ********************/ +#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDGLOW register ********************/ +#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSEQ1 register *******************/ +#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_RSEQ2 register *******************/ +#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_RSEQ3 register *******************/ +#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSEQ register *******************/ +#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */ +#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDAT1 register *******************/ +#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT2 register *******************/ +#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT3 register *******************/ +#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT4 register *******************/ +#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DAT register ********************/ +#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */ + +///******************** Bit definition for ADC_DIFSEL register ********************/ +//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */ +//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */ +//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */ +//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */ +//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */ +//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */ +//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */ +//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */ +//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */ +//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */ +//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */ +//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */ +//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */ +//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */ +//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */ +//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */ +//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */ +//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */ +//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */ +//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */ + +///******************** Bit definition for ADC_CALFACT register ********************/ +//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */ +//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */ +//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */ +//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */ +//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */ +//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */ +//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */ +//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */ + +//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */ +//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */ +//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */ +//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */ +//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */ +//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */ +//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */ +//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */ + +///******************** Bit definition for ADC_CTRL3 register ********************/ +//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */ +//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */ +//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */ + +//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */ +//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */ +//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */ +//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */ +//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */ +//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */ +//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */ +//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */ +//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */ +//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */ + +///******************** Bit definition for ADC_SAMPT3 register ********************/ +//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTRL register ********************/ +#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */ +#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */ +#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */ + +#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */ +#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */ +#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */ +#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */ + + + +/***************** Bit definition for DAC_SOTTR register ******************/ +#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */ + + +/***************** Bit definition for DAC_DR12CH register ******************/ +#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DL12CH register ******************/ +#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DR8CH register ******************/ +#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */ + + + + +/******************* Bit definition for DAC_DATO register *******************/ +#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */ + + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTRL1 register ********************/ +#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */ +#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */ +#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */ +#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */ +#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */ + +#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */ + +#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */ +#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */ +#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */ +#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */ +#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */ +#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */ + +#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/ +#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */ + +/******************* Bit definition for TIM_CTRL2 register ********************/ +#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */ +#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */ + +#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */ +#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */ + +/******************* Bit definition for TIM_SMCTRL register *******************/ +#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DINTEN register *******************/ +#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_STS register ********************/ +#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */ +#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */ +#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */ +#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */ +#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */ + +#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */ +#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */ + +/******************* Bit definition for TIM_EVTGEN register ********************/ +#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMOD1 register *******************/ +#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD2 register *******************/ +#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD3 register *******************/ +#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */ +#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */ + +#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */ + +#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */ +#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */ + +#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */ +#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +/******************* Bit definition for TIM_CCEN register *******************/ +#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */ + +#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */ +#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */ +#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */ +#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_AR register ********************/ +#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_REPCNT register ********************/ +#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCDAT1 register *******************/ +#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCDAT2 register *******************/ +#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCDAT3 register *******************/ +#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCDAT4 register *******************/ +#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_CCDAT5 register *******************/ +#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */ + +/******************* Bit definition for TIM_CCDAT6 register *******************/ +#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */ + +/******************* Bit definition for TIM_BKDT register *******************/ +#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCTRL register ********************/ +#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DADDR register *******************/ +#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ +/******************************************************************************/ +/* */ +/* Low Power Timer (LPTTIM) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for LPTIM_INTSTS register *******************/ +#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */ +#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */ + +/****************** Bit definition for LPTIM_INTCLR register *******************/ +#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */ +#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */ +#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */ +#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */ +#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */ + +/****************** Bit definition for LPTIM_INTEN register ********************/ +#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */ + +/****************** Bit definition for LPTIM_CFG register *******************/ +#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */ + +#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */ +#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */ +#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */ + +#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */ +#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */ + +#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */ +#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */ + +#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */ +#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */ +#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */ +#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */ + +#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */ +#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */ +#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */ +#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */ + +#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */ +#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */ + +#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */ +#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */ +#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */ +#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */ +#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */ +#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ +#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */ +/****************** Bit definition for LPTIM_CTRL register ********************/ +#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */ +#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */ +#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */ + +/****************** Bit definition for LPTIM_CMPT register *******************/ +#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */ + +/****************** Bit definition for LPTIM_AUTRLD register *******************/ +#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */ + +/****************** Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TSH register *******************/ +#define RTC_TSH_APM ((uint32_t)0x00400000) +#define RTC_TSH_HOT ((uint32_t)0x00300000) +#define RTC_TSH_HOT_0 ((uint32_t)0x00100000) +#define RTC_TSH_HOT_1 ((uint32_t)0x00200000) +#define RTC_TSH_HOU ((uint32_t)0x000F0000) +#define RTC_TSH_HOU_0 ((uint32_t)0x00010000) +#define RTC_TSH_HOU_1 ((uint32_t)0x00020000) +#define RTC_TSH_HOU_2 ((uint32_t)0x00040000) +#define RTC_TSH_HOU_3 ((uint32_t)0x00080000) +#define RTC_TSH_MIT ((uint32_t)0x00007000) +#define RTC_TSH_MIT_0 ((uint32_t)0x00001000) +#define RTC_TSH_MIT_1 ((uint32_t)0x00002000) +#define RTC_TSH_MIT_2 ((uint32_t)0x00004000) +#define RTC_TSH_MIU ((uint32_t)0x00000F00) +#define RTC_TSH_MIU_0 ((uint32_t)0x00000100) +#define RTC_TSH_MIU_1 ((uint32_t)0x00000200) +#define RTC_TSH_MIU_2 ((uint32_t)0x00000400) +#define RTC_TSH_MIU_3 ((uint32_t)0x00000800) +#define RTC_TSH_SCT ((uint32_t)0x00000070) +#define RTC_TSH_SCT_0 ((uint32_t)0x00000010) +#define RTC_TSH_SCT_1 ((uint32_t)0x00000020) +#define RTC_TSH_SCT_2 ((uint32_t)0x00000040) +#define RTC_TSH_SCU ((uint32_t)0x0000000F) +#define RTC_TSH_SCU_0 ((uint32_t)0x00000001) +#define RTC_TSH_SCU_1 ((uint32_t)0x00000002) +#define RTC_TSH_SCU_2 ((uint32_t)0x00000004) +#define RTC_TSH_SCU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_DATE register *******************/ +#define RTC_DATE_YRT ((uint32_t)0x00F00000) +#define RTC_DATE_YRT_0 ((uint32_t)0x00100000) +#define RTC_DATE_YRT_1 ((uint32_t)0x00200000) +#define RTC_DATE_YRT_2 ((uint32_t)0x00400000) +#define RTC_DATE_YRT_3 ((uint32_t)0x00800000) +#define RTC_DATE_YRU ((uint32_t)0x000F0000) +#define RTC_DATE_YRU_0 ((uint32_t)0x00010000) +#define RTC_DATE_YRU_1 ((uint32_t)0x00020000) +#define RTC_DATE_YRU_2 ((uint32_t)0x00040000) +#define RTC_DATE_YRU_3 ((uint32_t)0x00080000) +#define RTC_DATE_WDU ((uint32_t)0x0000E000) +#define RTC_DATE_WDU_0 ((uint32_t)0x00002000) +#define RTC_DATE_WDU_1 ((uint32_t)0x00004000) +#define RTC_DATE_WDU_2 ((uint32_t)0x00008000) +#define RTC_DATE_MOT ((uint32_t)0x00001000) +#define RTC_DATE_MOU ((uint32_t)0x00000F00) +#define RTC_DATE_MOU_0 ((uint32_t)0x00000100) +#define RTC_DATE_MOU_1 ((uint32_t)0x00000200) +#define RTC_DATE_MOU_2 ((uint32_t)0x00000400) +#define RTC_DATE_MOU_3 ((uint32_t)0x00000800) +#define RTC_DATE_DAT ((uint32_t)0x00000030) +#define RTC_DATE_DAT_0 ((uint32_t)0x00000010) +#define RTC_DATE_DAT_1 ((uint32_t)0x00000020) +#define RTC_DATE_DAU ((uint32_t)0x0000000F) +#define RTC_DATE_DAU_0 ((uint32_t)0x00000001) +#define RTC_DATE_DAU_1 ((uint32_t)0x00000002) +#define RTC_DATE_DAU_2 ((uint32_t)0x00000004) +#define RTC_DATE_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_CTRL register *******************/ +#define RTC_CTRL_COEN ((uint32_t)0x00800000) +#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000) +#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000) +#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000) +#define RTC_CTRL_OPOL ((uint32_t)0x00100000) +#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000) +#define RTC_CTRL_BAKP ((uint32_t)0x00040000) +#define RTC_CTRL_SU1H ((uint32_t)0x00020000) +#define RTC_CTRL_AD1H ((uint32_t)0x00010000) +#define RTC_CTRL_TSIEN ((uint32_t)0x00008000) +#define RTC_CTRL_WTIEN ((uint32_t)0x00004000) +#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000) +#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000) +#define RTC_CTRL_TSEN ((uint32_t)0x00000800) +#define RTC_CTRL_WTEN ((uint32_t)0x00000400) +#define RTC_CTRL_ALBEN ((uint32_t)0x00000200) +#define RTC_CTRL_ALAEN ((uint32_t)0x00000100) + +#define RTC_CTRL_HFMT ((uint32_t)0x00000040) +#define RTC_CTRL_BYPS ((uint32_t)0x00000020) +#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010) +#define RTC_CTRL_TEDGE ((uint32_t)0x00000008) +#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007) +#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001) +#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002) +#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004) + +/******************** Bits definition for RTC_INITSTS register ******************/ +#define RTC_INITSTS_RECPF ((uint32_t)0x00010000) +#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000) +#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000) +#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000) +#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000) +#define RTC_INITSTS_TISF ((uint32_t)0x00000800) +#define RTC_INITSTS_WTF ((uint32_t)0x00000400) +#define RTC_INITSTS_ALBF ((uint32_t)0x00000200) +#define RTC_INITSTS_ALAF ((uint32_t)0x00000100) +#define RTC_INITSTS_INITM ((uint32_t)0x00000080) +#define RTC_INITSTS_INITF ((uint32_t)0x00000040) +#define RTC_INITSTS_RSYF ((uint32_t)0x00000020) +#define RTC_INITSTS_INITSF ((uint32_t)0x00000010) +#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008) +#define RTC_INITSTS_WTWF ((uint32_t)0x00000004) +#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002) +#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_PRE register *****************/ +#define RTC_PRE_DIVA ((uint32_t)0x007F0000) +#define RTC_PRE_DIVS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_WKUPT register *****************/ +#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF) + + +/******************** Bits definition for RTC_ALARMA register ***************/ +#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMA_DTT ((uint32_t)0x30000000) +#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMA_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMA_APM ((uint32_t)0x00400000) +#define RTC_ALARMA_HOT ((uint32_t)0x00300000) +#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMA_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMA_MIT ((uint32_t)0x00007000) +#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMA_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMA_SET ((uint32_t)0x00000070) +#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMA_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_ALARMB register ***************/ +#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMB_DTT ((uint32_t)0x30000000) +#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMB_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMB_APM ((uint32_t)0x00400000) +#define RTC_ALARMB_HOT ((uint32_t)0x00300000) +#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMB_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMB_MIT ((uint32_t)0x00007000) +#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMB_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMB_SET ((uint32_t)0x00000070) +#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMB_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_WRP register ******************/ +#define RTC_WRP_PKEY ((uint32_t)0x000000FF) + +/******************** Bits definition for RTC_SUBS register ******************/ +#define RTC_SUBS_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_SCTRL register ***************/ +#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF) +#define RTC_SCTRL_AD1S ((uint32_t)0x80000000) + +/******************** Bits definition for RTC_TST register *****************/ +#define RTC_TST_APM ((uint32_t)0x00400000) +#define RTC_TST_HOT ((uint32_t)0x00300000) +#define RTC_TST_HOT_0 ((uint32_t)0x00100000) +#define RTC_TST_HOT_1 ((uint32_t)0x00200000) +#define RTC_TST_HOU ((uint32_t)0x000F0000) +#define RTC_TST_HOU_0 ((uint32_t)0x00010000) +#define RTC_TST_HOU_1 ((uint32_t)0x00020000) +#define RTC_TST_HOU_2 ((uint32_t)0x00040000) +#define RTC_TST_HOU_3 ((uint32_t)0x00080000) +#define RTC_TST_MIT ((uint32_t)0x00007000) +#define RTC_TST_MIT_0 ((uint32_t)0x00001000) +#define RTC_TST_MIT_1 ((uint32_t)0x00002000) +#define RTC_TST_MIT_2 ((uint32_t)0x00004000) +#define RTC_TST_MIU ((uint32_t)0x00000F00) +#define RTC_TST_MIU_0 ((uint32_t)0x00000100) +#define RTC_TST_MIU_1 ((uint32_t)0x00000200) +#define RTC_TST_MIU_2 ((uint32_t)0x00000400) +#define RTC_TST_MIU_3 ((uint32_t)0x00000800) +#define RTC_TST_SET ((uint32_t)0x00000070) +#define RTC_TST_SET_0 ((uint32_t)0x00000010) +#define RTC_TST_SET_1 ((uint32_t)0x00000020) +#define RTC_TST_SET_2 ((uint32_t)0x00000040) +#define RTC_TST_SEU ((uint32_t)0x0000000F) +#define RTC_TST_SEU_0 ((uint32_t)0x00000001) +#define RTC_TST_SEU_1 ((uint32_t)0x00000002) +#define RTC_TST_SEU_2 ((uint32_t)0x00000004) +#define RTC_TST_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSD register *****************/ +#define RTC_TSD_YRT ((uint32_t)0x00F00000) +#define RTC_TSD_YRT_0 ((uint32_t)0x00100000) +#define RTC_TSD_YRT_1 ((uint32_t)0x00200000) +#define RTC_TSD_YRT_2 ((uint32_t)0x00400000) +#define RTC_TSD_YRT_3 ((uint32_t)0x00800000) +#define RTC_TSD_YRU ((uint32_t)0x000F0000) +#define RTC_TSD_YRU_0 ((uint32_t)0x00010000) +#define RTC_TSD_YRU_1 ((uint32_t)0x00020000) +#define RTC_TSD_YRU_2 ((uint32_t)0x00040000) +#define RTC_TSD_YRU_3 ((uint32_t)0x00080000) + +#define RTC_TSD_WDU ((uint32_t)0x0000E000) +#define RTC_TSD_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSD_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSD_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSD_MOT ((uint32_t)0x00001000) +#define RTC_TSD_MOU ((uint32_t)0x00000F00) +#define RTC_TSD_MOU_0 ((uint32_t)0x00000100) +#define RTC_TSD_MOU_1 ((uint32_t)0x00000200) +#define RTC_TSD_MOU_2 ((uint32_t)0x00000400) +#define RTC_TSD_MOU_3 ((uint32_t)0x00000800) +#define RTC_TSD_DAT ((uint32_t)0x00000030) +#define RTC_TSD_DAT_0 ((uint32_t)0x00000010) +#define RTC_TSD_DAT_1 ((uint32_t)0x00000020) +#define RTC_TSD_DAU ((uint32_t)0x0000000F) +#define RTC_TSD_DAU_0 ((uint32_t)0x00000001) +#define RTC_TSD_DAU_1 ((uint32_t)0x00000002) +#define RTC_TSD_DAU_2 ((uint32_t)0x00000004) +#define RTC_TSD_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSSS register ****************/ +#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CALIB register *****************/ +#define RTC_CALIB_CP ((uint32_t)0x00008000) +#define RTC_CALIB_CW8 ((uint32_t)0x00004000) +#define RTC_CALIB_CW16 ((uint32_t)0x00002000) +#define RTC_CALIB_CM ((uint32_t)0x000001FF) +#define RTC_CALIB_CM_0 ((uint32_t)0x00000001) +#define RTC_CALIB_CM_1 ((uint32_t)0x00000002) +#define RTC_CALIB_CM_2 ((uint32_t)0x00000004) +#define RTC_CALIB_CM_3 ((uint32_t)0x00000008) +#define RTC_CALIB_CM_4 ((uint32_t)0x00000010) +#define RTC_CALIB_CM_5 ((uint32_t)0x00000020) +#define RTC_CALIB_CM_6 ((uint32_t)0x00000040) +#define RTC_CALIB_CM_7 ((uint32_t)0x00000080) +#define RTC_CALIB_CM_8 ((uint32_t)0x00000100) + +/******************** Bits definition for RTC_TMPCFG register ****************/ + +#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000) +#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000) +#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000) +#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000) +#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000) +#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000) +#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000) +#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000) +#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000) +#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000) +#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000) +#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800) +#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800) +#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000) +#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700) +#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080) +#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040) +#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020) +#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010) +#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008) +#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004) +#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002) +#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_ALRMASS register *************/ +#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_ALRMBSS register *************/ +#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_OPT register *******************/ +#define RTC_OPT_TYPE ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/ +#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008) +#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004) +#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCNT register *******************/ +#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF) +/******************** Bits definition for RTC_BKP1 register ****************/ +#define RTC_BKP1 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP2 register ****************/ +#define RTC_BKP2 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP3 register ****************/ +#define RTC_BKP3 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP4 register ****************/ +#define RTC_BKP4 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP5 register ****************/ +#define RTC_BKP5 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP6 register ****************/ +#define RTC_BKP6 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP7 register ****************/ +#define RTC_BKP7 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP8 register ****************/ +#define RTC_BKP8 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP9 register ****************/ +#define RTC_BKP9 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP10 register ****************/ +#define RTC_BKP10 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP11 register ***************/ +#define RTC_BKP11 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP12register ***************/ +#define RTC_BKP12 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP13 register ***************/ +#define RTC_BKP13 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP14 register ***************/ +#define RTC_BKP14 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP15 register ***************/ +#define RTC_BKP15 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP16 register ***************/ +#define RTC_BKP16 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP17register ***************/ +#define RTC_BKP17 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP18 register ***************/ +#define RTC_BKP18 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP19 register ***************/ +#define RTC_BKP19 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP20 register ***************/ +#define RTC_BKP20 ((uint32_t)0xFFFFFFFF) + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KEY register ********************/ +#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PREDIV register ********************/ +#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RELV register *******************/ +#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STS register ********************/ +#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTRL register ********************/ +#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFG register *******************/ +#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */ +#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STS register ********************/ +#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for XFMC_BCR1 register *******************/ +#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BCR2 register *******************/ +#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BTR1 register ******************/ +#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BTR2 register *******************/ +#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR1 register ******************/ +#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR2 register ******************/ +#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_PCR2 register *******************/ +#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for XFMC_PCR3 register *******************/ +#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for XFMC_SR2 register *******************/ +//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/******************* Bit definition for XFMC_SR3 register *******************/ +//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/****************** Bit definition for XFMC_PMEM2 register ******************/ +#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PMEM3 register ******************/ +#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT2 register ******************/ +#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT3 register ******************/ +#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_ECCR2 register ******************/ +#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for XFMC_ECCR3 register ******************/ +#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */ +#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCTRL register ********************/ +#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */ +#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */ +#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */ +#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */ + +/******************* Bit definition for CAN_MSTS register ********************/ +#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTS register ********************/ +#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFF0 register *******************/ +#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */ +#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */ +#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */ +#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFF1 register *******************/ +#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */ +#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */ +#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */ +#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTE register *******************/ +#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTIM register ********************/ +#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMC register ********************/ +#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1 register *******************/ +#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1 register *******************/ +#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1 register *******************/ +#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */ +#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */ +#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */ +#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */ +#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */ +#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */ +#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */ +#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */ +#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */ +#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */ +#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */ +#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */ +#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */ +#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */ +#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1 register *******************/ +#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTRL1 register ********************/ +#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTRL2 register ********************/ +#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STS register ********************/ +#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DAT register ********************/ +#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPOLY register ******************/ +#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_CRCRDAT register ******************/ +#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_CRCTDAT register ******************/ +#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFG register *****************/ +#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPREDIV register *******************/ +#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTRL1 register ********************/ +#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CTRL2 register ********************/ +#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DAT register ********************/ +#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_STS1 register ********************/ +#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_STS2 register ********************/ +#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CLKCTRL register ********************/ +#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_STS register *******************/ +#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DAT register *******************/ +#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRCF register *******************/ +#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTRL1 register *******************/ +#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */ +#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */ + +/****************** Bit definition for USART_CTRL2 register *******************/ +#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CTRL3 register *******************/ +#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ + +/****************** Bit definition for USART_GTP register ******************/ +#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Low-power Universal Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for LPUART_STS register ******************/ +#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */ +#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */ +#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */ +#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */ +#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */ +#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */ +#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */ +#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */ +#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */ + +/****************** Bit definition for LPUART_INTEN register ******************/ +#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */ +#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */ +#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */ +#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/ +#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */ +#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */ +#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */ + +/****************** Bit definition for LPUART_CTRL register ******************/ +#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */ +#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */ +#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */ +#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */ +#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */ +#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */ +#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */ +#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */ +#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */ +#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */ +#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */ +#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */ +#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */ + +/****************** Bit definition for LPUART_BRCFG1 register ******************/ +#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */ + +/****************** Bit definition for LPUART_DAT register ******************/ +#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */ + +/****************** Bit definition for LPUART_BRCFG2 register ******************/ +#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */ + +/****************** Bit definition for LPUART_WUDAT register ******************/ +#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBG_ID register *****************/ +#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBG_CTRL register *******************/ +#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ + +#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */ +#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */ +#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */ +#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/ +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_AC register ******************/ +#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */ +#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */ +#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */ +#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */ + +#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ +#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ +#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */ +#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */ +#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */ +#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */ +#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */ +#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */ + +/****************** Bit definition for FLASH_KEY register ******************/ +#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */ + +/***************** Bit definition for FLASH_OPTKEY register ****************/ +#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */ +#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */ +#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */ + +/******************* Bit definition for FLASH_CTRL register *******************/ +#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */ +#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */ +#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */ + +/******************* Bit definition for FLASH_ADD register *******************/ +#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OB2 register *******************/ +#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */ +#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */ +#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */ +#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */ + +/****************** Bit definition for FLASH_OB register *******************/ +#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */ + +#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */ +#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */ + +#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */ +#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */ +#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */ + +/****************** Bit definition for FLASH_WRP register ******************/ +#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/****************** Bit definition for FLASH_CAHR register ******************/ +#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */ +#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */ +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for OptionByte Data0 *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte Data1 *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte WRP0 ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP1 ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP2 ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP3 ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte RDP2 *******************/ +#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */ +#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */ + +/****************** Bit definition for OptionByte USER2 ******************/ +#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_PMODE register *******************/ + + +#define GPIO_PMODE0_Pos (0) +#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE0 GPIO_PMODE0_Msk +#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE1_Pos (2) +#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE1 GPIO_PMODE1_Msk +#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE2_Pos (4) +#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE2 GPIO_PMODE2_Msk +#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE3_Pos (6) +#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE3 GPIO_PMODE3_Msk +#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE4_Pos (8) +#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE4 GPIO_PMODE4_Msk +#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE5_Pos (10) +#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE5 GPIO_PMODE5_Msk +#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE6_Pos (12) +#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE6 GPIO_PMODE6_Msk +#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE7_Pos (14) +#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE7 GPIO_PMODE7_Msk +#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE8_Pos (16) +#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE8 GPIO_PMODE8_Msk +#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE9_Pos (18) +#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE9 GPIO_PMODE9_Msk +#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE10_Pos (20) +#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE10 GPIO_PMODE10_Msk +#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE11_Pos (22) +#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE11 GPIO_PMODE11_Msk +#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE12_Pos (24) +#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE12 GPIO_PMODE12_Msk +#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE13_Pos (26) +#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE13 GPIO_PMODE13_Msk +#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE14_Pos (28) +#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE14 GPIO_PMODE14_Msk +#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE15_Pos (30) +#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE15 GPIO_PMODE15_Msk +#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ + + + + +/****************** Bit definition for GPIO_POTYPER register *****************/ +#define GPIO_POTYPE_POT_0 (0x00000001) +#define GPIO_POTYPE_POT_1 (0x00000002) +#define GPIO_POTYPE_POT_2 (0x00000004) +#define GPIO_POTYPE_POT_3 (0x00000008) +#define GPIO_POTYPE_POT_4 (0x00000010) +#define GPIO_POTYPE_POT_5 (0x00000020) +#define GPIO_POTYPE_POT_6 (0x00000040) +#define GPIO_POTYPE_POT_7 (0x00000080) +#define GPIO_POTYPE_POT_8 (0x00000100) +#define GPIO_POTYPE_POT_9 (0x00000200) +#define GPIO_POTYPE_POT_10 (0x00000400) +#define GPIO_POTYPE_POT_11 (0x00000800) +#define GPIO_POTYPE_POT_12 (0x00001000) +#define GPIO_POTYPE_POT_13 (0x00002000) +#define GPIO_POTYPE_POT_14 (0x00004000) +#define GPIO_POTYPE_POT_15 (0x00008000) + + +/******************* Bit definition for GPIO_PUPDR register ******************/ +#define GPIO_PUPD0_Pos (0) +#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD0 GPIO_PUPD0_Msk +#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD1_Pos (2) +#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD1 GPIO_PUPD1_Msk +#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD2_Pos (4) +#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD2 GPIO_PUPD2_Msk +#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD3_Pos (6) +#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD3 GPIO_PUPD3_Msk +#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD4_Pos (8) +#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD4 GPIO_PUPD4_Msk +#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD5_Pos (10) +#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD5 GPIO_PUPD5_Msk +#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD6_Pos (12) +#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD6 GPIO_PUPD6_Msk +#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD7_Pos (14) +#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD7 GPIO_PUPD7_Msk +#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD8_Pos (16) +#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD8 GPIO_PUPD8_Msk +#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD9_Pos (18) +#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD9 GPIO_PUPD9_Msk +#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD10_Pos (20) +#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD10 GPIO_PUPD10_Msk +#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD11_Pos (22) +#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD11 GPIO_PUPD11_Msk +#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD12_Pos (24) +#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD12 GPIO_PUPD12_Msk +#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD13_Pos (26) +#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD13 GPIO_PUPD13_Msk +#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD14_Pos (28) +#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD14 GPIO_PUPD14_Msk +#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD15_Pos (30) +#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD15 GPIO_PUPD15_Msk +#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */ + + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_POD register *******************/ +#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/****************** Bit definition for GPIO_AFL register *******************/ +#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */ +#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */ +#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */ +#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */ +#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */ +#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */ +#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */ +#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */ + +/****************** Bit definition for GPIO_AFH register *******************/ +#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */ +#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */ +#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */ +#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */ +#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */ +#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */ +#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */ +#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */ + + +/******************* Bit definition for GPIO_DS register ******************/ +#define GPIO_DS0_Pos (0) +#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ +#define GPIO_DS0 GPIO_DS0_Msk +#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */ +#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */ +#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */ +#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ + +#define GPIO_DS1_Pos (2) +#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ +#define GPIO_DS1 GPIO_DS1_Msk +#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */ +#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */ +#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */ +#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ + +#define GPIO_DS2_Pos (4) +#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ +#define GPIO_DS2 GPIO_DS2_Msk +#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */ +#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */ +#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */ +#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ + +#define GPIO_DS3_Pos (6) +#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ +#define GPIO_DS3 GPIO_DS3_Msk +#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */ +#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */ +#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */ +#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ + +#define GPIO_DS4_Pos (8) +#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ +#define GPIO_DS4 GPIO_DS4_Msk +#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */ +#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */ +#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */ +#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ + +#define GPIO_DS5_Pos (10) +#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ +#define GPIO_DS5 GPIO_DS5_Msk +#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */ +#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */ +#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */ +#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ + +#define GPIO_DS6_Pos (12) +#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ +#define GPIO_DS6 GPIO_DS6_Msk +#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */ +#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */ +#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */ +#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ + +#define GPIO_DS7_Pos (14) +#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ +#define GPIO_DS7 GPIO_DS7_Msk +#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */ +#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */ +#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */ +#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ + + +#define GPIO_DS8_Pos (16) +#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ +#define GPIO_DS8 GPIO_DS8_Msk +#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */ +#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */ +#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */ +#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ + +#define GPIO_DS9_Pos (18) +#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ +#define GPIO_DS9 GPIO_DS9_Msk +#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */ +#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */ +#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */ +#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ + +#define GPIO_DS10_Pos (20) +#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ +#define GPIO_DS10 GPIO_DS10_Msk +#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */ +#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */ +#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */ +#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ + +#define GPIO_DS11_Pos (22) +#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ +#define GPIO_DS11 GPIO_DS11_Msk +#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */ +#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */ +#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */ +#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ + +#define GPIO_DS12_Pos (24) +#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ +#define GPIO_DS12 GPIO_DS12_Msk +#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */ +#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */ +#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */ +#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ + +#define GPIO_DS13_Pos (26) +#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ +#define GPIO_DS13 GPIO_DS13_Msk +#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */ +#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */ +#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */ +#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ + +#define GPIO_DS14_Pos (28) +#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ +#define GPIO_DS14 GPIO_DS14_Msk +#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */ +#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */ +#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */ +#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ + +#define GPIO_DS15_Pos (30) +#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ +#define GPIO_DS15 GPIO_DS15_Msk +#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */ +#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */ +#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */ +#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ + +/******************* Bit definition for GPIO_SR register *******************/ +#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */ +#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */ +#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */ +#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */ +#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */ +#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */ +#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */ +#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */ +#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */ +#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */ +#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */ +#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */ +#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */ +#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */ +#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */ +#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for AFIO_RMP_CFG register *****************/ +#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */ +#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */ +#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */ +#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */ +#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */ +#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */ +#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */ +#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */ +#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */ +#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */ +#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */ +#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ + +/*!< EXTI5 configuration */ +#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */ +#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */ +#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */ +#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */ +#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */ +#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */ +#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */ + +/*!< EXTI12 configuration */ +#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ + +/*!< EXTI13 configuration */ +#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ +#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ +#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ +#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ +#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ +#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ +#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ +#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ +#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ +#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ +#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ +#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ +#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ +#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ +#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ + + +/****************** Bit definition for EXTI_RT_CFG register *******************/ +#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ +#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ +#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ +#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ +#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ + + + +/****************** Bit definition for EXTI_FT_CFG register *******************/ +#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ +#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ +#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ +#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ +#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ + +/****************** Bit definition for EXTI_SWIE register ******************/ +#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ +#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ +#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ +#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ +#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ +#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ + +/******************* Bit definition for EXTI_PEND register ********************/ +#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ +#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ +#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ +#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ +#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ +#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ +#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ +#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ +#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ + + +/******************************************************************************/ +/* */ +/* LCD Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for LCD_CTRL register *******************/ +#define LCD_CTRL_BUFEN_Msk ((uint32_t)0x00000100) +#define LCD_CTRL_BUFEN_Pos (8U) +#define LCD_CTRL_BUFEN (LCD_CTRL_BUFEN_Msk) /*!< High driving capacity buffer enable bit*/ + +#define LCD_CTRL_MUXSEG_Msk ((uint32_t)0x00000080) +#define LCD_CTRL_MUXSEG_Pos (7U) +#define LCD_CTRL_MUXSEG (LCD_CTRL_MUXSEG_Msk) /*!< Mux segment enable bit*/ + +#define LCD_CTRL_BIAS_Msk ((uint32_t)0x00000060) +#define LCD_CTRL_BIAS_Pos (5U) +#define LCD_CTRL_BIAS (LCD_CTRL_BIAS_Msk) +#define LCD_CTRL_BIAS_0 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< Bias selector bit*/ +#define LCD_CTRL_BIAS_1 (0x2UL << LCD_CTRL_BIAS_Pos) + +#define LCD_CTRL_DUTY_Msk ((uint32_t)0x0000001C) +#define LCD_CTRL_DUTY_Pos (2U) +#define LCD_CTRL_DUTY (LCD_CTRL_DUTY_Msk) /*!< Duty selection bit*/ +#define LCD_CTRL_DUTY_0 (0x1UL << LCD_CTRL_DUTY_Pos) +#define LCD_CTRL_DUTY_1 (0x2UL << LCD_CTRL_DUTY_Pos) +#define LCD_CTRL_DUTY_2 (0x4UL << LCD_CTRL_DUTY_Pos) + +#define LCD_CTRL_VSEL_Msk ((uint32_t)0x00000002) +#define LCD_CTRL_VSEL_Pos (1U) +#define LCD_CTRL_VSEL (LCD_CTRL_VSEL_Msk) /*!< Voltage source selection bit*/ + +#define LCD_CTRL_LCDEN_Msk ((uint32_t)0x00000001) +#define LCD_CTRL_LCDEN_Pos (0U) +#define LCD_CTRL_LCDEN (LCD_CTRL_LCDEN_Msk) /*!< LCD controller enable bit*/ + +/******************* Bit definition for LCD_FCTRL register *******************/ +#define LCD_FCTRL_PRES_Msk ((uint32_t)0x03C00000) +#define LCD_FCTRL_PRES_Pos (22U) +#define LCD_FCTRL_PRES (LCD_FCTRL_PRES_Msk) /*!< 16-bit prescaler bit*/ +#define LCD_FCTRL_PRES_0 (0x1UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_1 (0x2UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_2 (0x4UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_3 (0x8UL << LCD_FCTRL_PRES_Pos) + +#define LCD_FCTRL_DIV_Msk ((uint32_t)0x003C0000) +#define LCD_FCTRL_DIV_Pos (18U) +#define LCD_FCTRL_DIV (LCD_FCTRL_DIV_Msk) /*!< DIV clock divider bit*/ +#define LCD_FCTRL_DIV_0 (0x1UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_1 (0x2UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_2 (0x4UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_3 (0x8UL << LCD_FCTRL_DIV_Pos) + +#define LCD_FCTRL_BLINK_Msk ((uint32_t)0x00030000) +#define LCD_FCTRL_BLINK_Pos (16U) +#define LCD_FCTRL_BLINK (LCD_FCTRL_BLINK_Msk) /*!< Blink mode selection bit*/ +#define LCD_FCTRL_BLINK_0 (0x1UL << LCD_FCTRL_BLINK_Pos) +#define LCD_FCTRL_BLINK_1 (0x2UL << LCD_FCTRL_BLINK_Pos) + +#define LCD_FCTRL_BLINKF_Msk ((uint32_t)0x0000E000) +#define LCD_FCTRL_BLINKF_Pos (13U) +#define LCD_FCTRL_BLINKF (LCD_FCTRL_BLINKF_Msk) /*!< Blink frequency selection bit*/ +#define LCD_FCTRL_BLINKF_0 (0x1UL << LCD_FCTRL_BLINKF_Pos) +#define LCD_FCTRL_BLINKF_1 (0x2UL << LCD_FCTRL_BLINKF_Pos) +#define LCD_FCTRL_BLINKF_2 (0x4UL << LCD_FCTRL_BLINKF_Pos) + +#define LCD_FCTRL_CONTRAST_Msk ((uint32_t)0x00001C00) +#define LCD_FCTRL_CONTRAST_Pos (10U) +#define LCD_FCTRL_CONTRAST (LCD_FCTRL_CONTRAST_Msk) /*!< Contrast Control bit*/ +#define LCD_FCTRL_CONTRAST_0 (0x1UL << LCD_FCTRL_CONTRAST_Pos) +#define LCD_FCTRL_CONTRAST_1 (0x2UL << LCD_FCTRL_CONTRAST_Pos) +#define LCD_FCTRL_CONTRAST_2 (0x4UL << LCD_FCTRL_CONTRAST_Pos) + +#define LCD_FCTRL_DEAD_Msk ((uint32_t)0x00000380) +#define LCD_FCTRL_DEAD_Pos (7U) +#define LCD_FCTRL_DEAD (LCD_FCTRL_DEAD_Msk) /*!< Dead time duration bit*/ +#define LCD_FCTRL_DEAD_0 (0x1UL << LCD_FCTRL_DEAD_Pos) +#define LCD_FCTRL_DEAD_1 (0x2UL << LCD_FCTRL_DEAD_Pos) +#define LCD_FCTRL_DEAD_2 (0x4UL << LCD_FCTRL_DEAD_Pos) + +#define LCD_FCTRL_PULSEON_Msk ((uint32_t)0x00000070) +#define LCD_FCTRL_PULSEON_Pos (4U) +#define LCD_FCTRL_PULSEON (LCD_FCTRL_PULSEON_Msk) /*!< Pulse on duration bit*/ +#define LCD_FCTRL_PULSEON_0 (0x1UL << LCD_FCTRL_PULSEON_Pos) +#define LCD_FCTRL_PULSEON_1 (0x2UL << LCD_FCTRL_PULSEON_Pos) +#define LCD_FCTRL_PULSEON_2 (0x4UL << LCD_FCTRL_PULSEON_Pos) + +#define LCD_FCTRL_UDDIE_Msk ((uint32_t)0x00000008) +#define LCD_FCTRL_UDDIE_Pos (3U) +#define LCD_FCTRL_UDDIE (LCD_FCTRL_UDDIE_Msk) /*!< Update display done interrupt enable bit*/ + +#define LCD_FCTRL_SOFIE_Msk ((uint32_t)0x00000002) +#define LCD_FCTRL_SOFIE_Pos (1U) +#define LCD_FCTRL_SOFIE (LCD_FCTRL_SOFIE_Msk) /*!< Start of frame interrupt enable bit*/ + +#define LCD_FCTRL_HDEN_Msk ((uint32_t)0x00000001) +#define LCD_FCTRL_HDEN_Pos (0U) +#define LCD_FCTRL_HDEN (LCD_FCTRL_HDEN_Msk) /*!< High drive enable bit*/ + +/******************* Bit definition for LCD_STS register *******************/ +#define LCD_STS_FCRSF_Msk ((uint32_t)0x00000020) +#define LCD_STS_FCRSF_Pos (5U) +#define LCD_STS_FCRSF (LCD_STS_FCRSF_Msk) /*!< LCD Frame Control Register Synchronization flag bit*/ + +#define LCD_STS_RDY_Msk ((uint32_t)0x00000010) +#define LCD_STS_RDY_Pos (4U) +#define LCD_STS_RDY (LCD_STS_RDY_Msk) /*!< VLCD Ready Flag bit*/ + +#define LCD_STS_UDD_Msk ((uint32_t)0x00000008) +#define LCD_STS_UDD_Pos (3U) +#define LCD_STS_UDD (LCD_STS_UDD_Msk) /*!< Update Display Done bit*/ + +#define LCD_STS_UDR_Msk ((uint32_t)0x00000004) +#define LCD_STS_UDR_Pos (2U) +#define LCD_STS_UDR (LCD_STS_UDR_Msk) /*!< Update Display Request bit*/ + +#define LCD_STS_SOF_Msk ((uint32_t)0x00000002) +#define LCD_STS_SOF_Pos (1U) +#define LCD_STS_SOF (LCD_STS_SOF_Msk) /*!< Start of Frame flag*/ + +#define LCD_STS_ENSTS_Msk ((uint32_t)0x00000001) +#define LCD_STS_ENSTS_Pos (0U) +#define LCD_STS_ENSTS (LCD_STS_ENSTS_Msk) /*!< LCD state bit*/ + +/******************* Bit definition for LCD_CLR register *******************/ +#define LCD_CLR_UDDCLR_Msk ((uint32_t)0x00000008) /*!< Update display done clear bit*/ +#define LCD_CLR_UDDCLR_Pos (3U) +#define LCD_CLR_UDDCLR (LCD_CLR_UDDCLR_Msk) + +#define LCD_CLR_SOFCLR_Msk ((uint32_t)0x00000002) /*!FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x_hal.h b/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x_hal.h new file mode 100644 index 0000000000000000000000000000000000000000..3207fc9cc09df005a9b6aa7515f87a5795dcc645 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/n32l40x_hal.h @@ -0,0 +1,85 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_conf.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_CONF_H__ +#define __N32L40X_CONF_H__ + +/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ + +#include "n32l40x_adc.h" +#include "n32l40x_can.h" +#include "n32l40x_comp.h" +#include "n32l40x_crc.h" +#include "n32l40x_dac.h" +#include "n32l40x_dbg.h" +#include "n32l40x_dma.h" +#include "n32l40x_exti.h" +#include "n32l40x_flash.h" +#include "n32l40x_gpio.h" +#include "n32l40x_i2c.h" +#include "n32l40x_iwdg.h" +#include "n32l40x_opamp.h" +#include "n32l40x_pwr.h" +#include "n32l40x_rcc.h" +#include "n32l40x_rtc.h" +#include "n32l40x_spi.h" +#include "n32l40x_tim.h" +#include "n32l40x_usart.h" +#include "n32l40x_lpuart.h" +#include "n32l40x_wwdg.h" +#include "n32l40x_tsc.h" +#include "n32l40x_lcd.h" + +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + */ +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((const uint8_t*)#expr, (const uint8_t*)__FILE__, __LINE__)) + +void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line); +#else +#define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __N32L40X_CONF_H__ */ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x.s b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x.s new file mode 100644 index 0000000000000000000000000000000000000000..cee6fb09b258367eaddd5fe4bcff8a7b0c31c6d5 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x.s @@ -0,0 +1,373 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +LCD_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_EWARM.s b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_EWARM.s new file mode 100644 index 0000000000000000000000000000000000000000..e9a39bed20bf9ade38a8f772a03554f78f8b5ea8 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_EWARM.s @@ -0,0 +1,523 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel1_IRQHandler + B DMA_Channel1_IRQHandler + + PUBWEAK DMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel2_IRQHandler + B DMA_Channel2_IRQHandler + + PUBWEAK DMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel3_IRQHandler + B DMA_Channel3_IRQHandler + + PUBWEAK DMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel4_IRQHandler + B DMA_Channel4_IRQHandler + + PUBWEAK DMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel5_IRQHandler + B DMA_Channel5_IRQHandler + + PUBWEAK DMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel6_IRQHandler + B DMA_Channel6_IRQHandler + + PUBWEAK DMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel7_IRQHandler + B DMA_Channel7_IRQHandler + + PUBWEAK DMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel8_IRQHandler + B DMA_Channel8_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK COMP_1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_1_2_IRQHandler + B COMP_1_2_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK LPUART_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_IRQHandler + B LPUART_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK CAN_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_TX_IRQHandler + B CAN_TX_IRQHandler + + PUBWEAK CAN_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX0_IRQHandler + B CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK LPUART_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_WKUP_IRQHandler + B LPUART_WKUP_IRQHandler + + PUBWEAK LPTIM_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM_WKUP_IRQHandler + B LPTIM_WKUP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK SAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAC_IRQHandler + B SAC_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RAMC_PERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAMC_PERR_IRQHandler + B RAMC_PERR_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK UCDR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UCDR_IRQHandler + B UCDR_IRQHandler + + + END + diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_gcc.s b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..3fdb7a1c3ff2385dea5238e189ec92776484ddd0 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/startup/startup_n32l40x_gcc.s @@ -0,0 +1,457 @@ +/** + **************************************************************************** + Copyright (c) 2019, Nations Technologies Inc. + + All rights reserved. + **************************************************************************** + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the disclaimer below. + + Nations' name may not be used to endorse or promote products derived from + this software without specific prior written permission. + + DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + **/ + +* Amount of memory (in bytes) allocated for Stack +* Tailor this value to your application needs +* Stack Configuration +* Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +* +*/ + +/** +****************************************************************************** +* @file startup_n32l40x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT Nations Technologies Inc *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.c b/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.c new file mode 100644 index 0000000000000000000000000000000000000000..def86f1b96ec344befa78b9c8bab3ccab6470c6b --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.c @@ -0,0 +1,659 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32l40x.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x.h" + +/* Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your + device's maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume + that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to + drive the System clock. If you are using different crystal you have to adapt + those functions accordingly. + */ + +#define SYSCLK_USE_MSI 0 +#define SYSCLK_USE_HSI 1 +#define SYSCLK_USE_HSE 2 +#define SYSCLK_USE_HSI_PLL 3 +#define SYSCLK_USE_HSE_PLL 4 + +#ifndef SYSCLK_FREQ +#define SYSCLK_FREQ 64000000 +#endif + +/* +* SYSCLK_SRC * +** SYSCLK_USE_MSI ** +** SYSCLK_USE_HSI ** +** SYSCLK_USE_HSE ** +** SYSCLK_USE_HSI_PLL ** +** SYSCLK_USE_HSE_PLL ** +*/ +#ifndef SYSCLK_SRC +#define SYSCLK_SRC SYSCLK_USE_HSE_PLL +#endif + +#define PLL_DIV2_DISABLE 0x00000000 +#define PLL_DIV2_ENABLE 0x00000002 +#define SRAM_VOL (__IO unsigned*)(0x40001800 + 0x20) +#define ConfigSRAMVoltage(vale) do{(*SRAM_VOL ) &= (~(uint32_t)(1 <<25));(*SRAM_VOL ) |= (uint32_t)(vale <<25);}while(0) //vale only equal to 0,1 +#if SYSCLK_SRC == SYSCLK_USE_MSI + + #if (SYSCLK_FREQ == MSI_VALUE_L0) + #define MSI_CLK 0 + #elif (SYSCLK_FREQ == MSI_VALUE_L1) + #define MSI_CLK 1 + #elif (SYSCLK_FREQ == MSI_VALUE_L2) + #define MSI_CLK 2 + #elif (SYSCLK_FREQ == MSI_VALUE_L3) + #define MSI_CLK 3 + #elif (SYSCLK_FREQ == MSI_VALUE_L4) + #define MSI_CLK 4 + #elif (SYSCLK_FREQ == MSI_VALUE_L5) + #define MSI_CLK 5 + #elif (SYSCLK_FREQ == MSI_VALUE_L6) + #define MSI_CLK 6 + #else + #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6) + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI + + #if SYSCLK_FREQ != HSI_VALUE + #error SYSCL_FREQ must be set to HSI_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if SYSCLK_FREQ != HSE_VALUE + #error SYSCL_FREQ must be set to HSE_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL + + #ifndef HSI_VALUE + #error HSI_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE) + + #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE) + + #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#else +#error wrong value for SYSCLK_SRC +#endif + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ + +/******************************************************************************* + * Clock Definitions + *******************************************************************************/ +uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +static void SetSysClock(void); + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + */ +void SystemInit(void) +{ + /* FPU settings + * ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +// /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSEON, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */ + RCC->CFG &= (uint32_t)0x0700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; + + /* Enable ex mode */ + RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN; + + if((PWR->CTRL1 & PWR_CTRL1_MRSEL2) == PWR_CTRL1_MRSEL2) + { + ConfigSRAMVoltage(1); + } + /* Enable ICACHE and Prefetch Buffer */ + FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN); + + /* Checks whether the Low Voltage Mode status is SET or RESET */ + if((FLASH->AC & FLASH_AC_LVMF) != RESET) + { + /* FLASH Low Voltage Mode Disable */ + FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN); + } + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or + * configure other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any + * configuration based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the + * MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the + * HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the + * HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the + * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in n32l40x.h file (default value + * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real + * value may vary depending on the variations in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in n32l40x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in n32l40x.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to + * ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0; + uint8_t msi_clk = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + tmp = RCC->CFG & RCC_CFG_SCLKSTS; + + /* Get MSI clock + * -------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + SystemCoreClock = MSIClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor + * ----------------------*/ + pllmull = RCC->CFG & RCC_CFG_PLLMULFCT; + pllsource = RCC->CFG & RCC_CFG_PLLSRC; + plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV; + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSI_VALUE * pllmull; + } + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + if (plldiv2 == 0x02) + { + /* PLL source clock divided by 2 selected as PLL clock entry */ + SystemCoreClock >>= 1; + } + + break; + + default: + SystemCoreClock = MSIClockTable[msi_clk]; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System PWR level to 1.0V + * . + */ +void ConfigMRVoltage1V(void) +{ + uint32_t ctrl_temp=0; + /*delay about 25us pll in 64M */ + uint32_t T25us=65*25; + __disable_irq(); + while(((PWR->STS2 & PWR_STS2_MRF) != PWR_STS2_MRF) && (T25us--)); + /*SRAM read margin setting switch in 0.9/lprun mode: use low voltage mode settings and 1.0v use normal mode*/ + ConfigSRAMVoltage(1); + ctrl_temp = PWR->CTRL1; + ctrl_temp &= (uint32_t)(~PWR_CTRL1_MRSEL); + ctrl_temp |= PWR_CTRL1_MRSEL2; + PWR->CTRL1 = ctrl_temp; + T25us=65*25; + /*wait VOSF to be 0 first*/ + while(((PWR->STS2 & PWR_STS2_MRF) != 0) && (T25us--)); + T25us=65*25; + /* wait VOSF to be 1 then */ + while(((PWR->STS2 & PWR_STS2_MRF) != PWR_STS2_MRF) && (T25us--)); + __enable_irq(); +} + + +/** + * @brief Configures the System PWR level to 1.1V + * . + */ +void ConfigMRVoltage1_1V(void) +{ + uint32_t ctrl_temp=0; + /*delay about 25us pll in 64M */ + uint32_t T25us=65*25; + __disable_irq(); + while(((PWR->STS2 & PWR_STS2_MRF) != PWR_STS2_MRF) && (T25us--)); + /*SRAM read margin setting switch in 0.9/lprun mode: use low voltage mode settings and 1.0v use normal mode*/ + ConfigSRAMVoltage(0); + /*MR=1.1V*/ + ctrl_temp = PWR->CTRL1; + ctrl_temp &= (uint32_t)(~PWR_CTRL1_MRSEL); + ctrl_temp |= PWR_CTRL1_MRSEL; + PWR->CTRL1 = ctrl_temp; + T25us=65*25; + /* wait VOSF to be 0 first */ + while(((PWR->STS2 &PWR_STS2_MRF) != 0) && (T25us--)); + T25us=65*25; + /* wait VOSF to be 1 then */ + while(((PWR->STS2 & PWR_STS2_MRF) != PWR_STS2_MRF) && (T25us--)); + __enable_irq(); +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 + * prescalers. + */ +static void SetSysClock(void) +{ + uint32_t rcc_cfg = 0; + uint32_t rcc_pllhsipre = 0; + uint32_t StartUpCounter = 0; + +#if (SYSCLK_SRC == SYSCLK_USE_MSI) + uint8_t i=0; + bool MSIStatus = 0; + /* Config MSI */ + RCC->CTRLSTS &= 0xFFFFFF8F; + /*Delay for while*/ + for(i=0;i<0x30;i++); + RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4); + /*Delay for while*/ + for(i=0;i<0x30;i++); + /* Enable MSI */ + RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN); + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD; + StartUpCounter++; + } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT)); + + MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET); + if (!MSIStatus) + { + /* If MSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL)) + + bool HSIStatus = 0; + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + /* If HSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL)) + + bool HSEStatus = 0; + /* Enable HSE */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET); + if (!HSEStatus) + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } +#endif + + ConfigMRVoltage1V(); + + /* Flash wait state + 0: HCLK <= 32M + 1: HCLK <= 64M + */ + FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY); + FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000); + + /* HCLK = SYSCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1; + + /* PCLK2 max 32M */ + if (SYSCLK_FREQ > 32000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1; + } + + /* PCLK1 max 16M */ + if (SYSCLK_FREQ > 32000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4; + } + else if (SYSCLK_FREQ > 16000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1; + } + +#if SYSCLK_SRC == SYSCLK_USE_MSI + /* Select MSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI; + + /* Wait till MSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI + /* Select HSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSE + /* Select HSE as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + /* clear bits */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT)); + RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV)); + + /* set PLL source */ + rcc_cfg = RCC->CFG; + rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE); + /* PLL DIV */ + rcc_pllhsipre = RCC->PLLHSIPRE; + + #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL + rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2); + #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); + #endif + + /* set PLL DIV */ + rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE); + + /* set PLL multiply factor */ + #if PLL_MUL <= 16 + rcc_cfg |= (PLL_MUL - 2) << 18; + #else + rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27); + #endif + + RCC->CFG = rcc_cfg; + RCC->PLLHSIPRE = rcc_pllhsipre; + + /* Enable PLL */ + RCC->CTRL |= RCC_CTRL_PLLEN; + + /* Wait till PLL is ready */ + while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C) + { + } +#endif +} diff --git a/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.h b/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.h new file mode 100644 index 0000000000000000000000000000000000000000..a01696cb15dcf83902cb3ccf054e0b111266e97e --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/CMSIS/device/system_n32l40x.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32l40x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SYSTEM_n32l40x_H__ +#define __SYSTEM_n32l40x_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup n32l40x_System + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_n32l40x_H__ */ diff --git a/drivers/hal/nationstech/N32L40x/Kconfig b/drivers/hal/nationstech/N32L40x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..ac7dbb4a9828f373f157dc6a21cb40dd392dfddb --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/Kconfig @@ -0,0 +1,10 @@ +config SERIES_N32L40X + bool + select ARCH_ARM_CORTEX_M4 + default n + +config SOC_N32L406RBL7 + bool + select MANUFACTOR_NATIONSTECH + select SERIES_N32L40X + default n diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/misc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/misc.h new file mode 100644 index 0000000000000000000000000000000000000000..2515705e38b741e3f2bbcc2cd225fc6b73c7a7d1 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/misc.h @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @addtogroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete n32l40x Devices IRQ Channels list, please + refer to n32l40x.h file) */ + + uint8_t + NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + +/** + * @} + */ + +/** @addtogroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption +priority | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption +priority | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption +priority | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption +priority | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption +priority | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Constants + * @{ + */ + +/** @addtogroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @addtogroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @addtogroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 \ + ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \ + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 \ + ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \ + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 \ + ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \ + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 \ + ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \ + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 \ + ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \ + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) \ + (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \ + || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @addtogroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) \ + (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_adc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..086433eef1136a110d2a6941ddc09da2b56105c9 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_adc.h @@ -0,0 +1,577 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_adc.h + * @author Nations Solution Team + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_ADC_H__ +#define __N32L40X_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" +#include + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ +#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while(0); +#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while(0); + +#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while(0); +#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while(0); + +/** @addtogroup ADC + * @{ + */ + +/** @addtogroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + + FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref + ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitType; +/** + * @} + */ + +/** @addtogroup ADC_Exported_Constants + * @{ + */ + +#define IsAdcModule(PERIPH) (((PERIPH) == ADC)) + +#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC)) + + + +/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) +#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) +#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) +#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) +#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) +#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) +#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) + + +#define IsAdcExtTrig(REGTRIG) \ + (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_data_align + * @{ + */ + +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) +#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) +/** + * @} + */ + +/** @addtogroup ADC_channels + * @{ + */ + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) + +#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0) +#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17) +#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18) + +#define IsAdcChannel(CHANNEL) \ + (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ + || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ + || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ + || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ + || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) +/** + * @} + */ + +/** @addtogroup ADC_sampling_time + * @{ + */ + +#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) +#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) +#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) +#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) +#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) +#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) +#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) +#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) +#define IsAdcSampleTime(TIME) \ + (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_239CYCLES5)) +/** + * @} + */ + +/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) +#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) +#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) +#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) +#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) +#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) +#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) + + +#define IsAdcExtInjTrig(INJTRIG) \ + (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_INJ_CH_1 ((uint8_t)0x14) +#define ADC_INJ_CH_2 ((uint8_t)0x18) +#define ADC_INJ_CH_3 ((uint8_t)0x1C) +#define ADC_INJ_CH_4 ((uint8_t)0x20) +#define IsAdcInjCh(CHANNEL) \ + (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ + || ((CHANNEL) == ADC_INJ_CH_4)) +/** + * @} + */ + +/** @addtogroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) +#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) +#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) +#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) +#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) +#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) +#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) + +#define IsAdcAnalogWatchdog(WATCHDOG) \ + (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_interrupts_definition + * @{ + */ + +#define ADC_INT_ENDC ((uint16_t)0x0220) +#define ADC_INT_AWD ((uint16_t)0x0140) +#define ADC_INT_JENDC ((uint16_t)0x0480) + +#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) +/** + * @} + */ + +/** @addtogroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_JENDC ((uint8_t)0x04) +#define ADC_FLAG_JSTR ((uint8_t)0x08) +#define ADC_FLAG_STR ((uint8_t)0x10) +#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) +#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) +#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) +#define IsAdcGetFlag(FLAG) \ + (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ + || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) +/** + * @} + */ + +/** @addtogroup ADC_thresholds + * @{ + */ +#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @addtogroup ADC_injected_offset + * @{ + */ + +#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @addtogroup ADC_injected_length + * @{ + */ + +#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_injected_rank + * @{ + */ + +#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_length + * @{ + */ + +#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @addtogroup ADC_regular_rank + * @{ + */ + +#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/************************** fllowing bit seg in ex register **********************/ +/**@addtogroup ADC_channels_ex_style + * @{ + */ + + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1_PA0 ((uint8_t)0x01) +#define ADC_CH_2_PA1 ((uint8_t)0x02) +#define ADC_CH_3_PA2 ((uint8_t)0x03) +#define ADC_CH_4_PA3 ((uint8_t)0x04) +#define ADC_CH_5_PA4 ((uint8_t)0x05) +#define ADC_CH_6_PA5 ((uint8_t)0x06) +#define ADC_CH_7_PA6 ((uint8_t)0x07) +#define ADC_CH_8_PA7 ((uint8_t)0x08) +#define ADC_CH_9_PB0 ((uint8_t)0x09) +#define ADC_CH_10_PB1 ((uint8_t)0x0A) +#define ADC_CH_11_PC0 ((uint8_t)0x0B) +#define ADC_CH_12_PC1 ((uint8_t)0x0C) +#define ADC_CH_13_PC2 ((uint8_t)0x0D) +#define ADC_CH_14_PC3 ((uint8_t)0x0E) +#define ADC_CH_15_PC4 ((uint8_t)0x0F) +#define ADC_CH_16_PC5 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) +/** + * @} + */ + +/**@addtogroup ADC_dif_sel_ch_definition + * @{ + */ +#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF) +#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001) +#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) +#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) +#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) +#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) +#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) +#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) +#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) +#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) +#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) +#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) +#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) +#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) +#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) +#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) +#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) +#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) +#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) +#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) +/** + * @} + */ + +/**@addtogroup ADC_calfact_definition + * @{ + */ +#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) +#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) +/** + * @} + */ + +/**@addtogroup ADC_ctrl3_definition + * @{ + */ +#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) +#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) +#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) +#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) +#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) +#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) +#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) +#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) +#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) +typedef enum +{ + ADC_CTRL3_CKMOD_AHB = 0, + ADC_CTRL3_CKMOD_PLL = 1, +} ADC_CTRL3_CKMOD; +typedef enum +{ + ADC_CTRL3_RES_12BIT = 3, + ADC_CTRL3_RES_10BIT = 2, + ADC_CTRL3_RES_8BIT = 1, + ADC_CTRL3_RES_6BIT = 0, +} ADC_CTRL3_RES; +typedef struct +{ + FunctionalState DeepPowerModEn; + FunctionalState JendcIntEn; + FunctionalState EndcIntEn; + ADC_CTRL3_CKMOD ClkMode; + FunctionalState CalAtuoLoadEn; + bool DifModCal; + ADC_CTRL3_RES ResBit; + bool Samp303Style; +} ADC_InitTypeEx; + +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; + __IO uint32_t EMC_CTRL; + __IO uint32_t EMC_ST; +} AFEC_TypeDef; + +typedef enum +{ + ADC_REFENCE_Volt_VREF = 0, + ADC_REFENCE_Volt_VREFBUFF = 1, +} ADC_REFERENCE_Volt; +/** + * @} + */ + +/**@addtogroup ADC_bit_num_definition + * @{ + */ +#define ADC_RST_BIT_12 ((uint32_t)0x03) +#define ADC_RST_BIT_10 ((uint32_t)0x02) +#define ADC_RST_BIT_8 ((uint32_t)0x01) +#define ADC_RESULT_BIT_6 ((uint32_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC_flags_ex_definition + * @{ + */ +#define ADC_FLAG_RDY ((uint8_t)0x20) +#define ADC_FLAG_PD_RDY ((uint8_t)0x40) +#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)) +/** + * @} + */ +/** @addtogroup ADC_AFEC definition + * @{ + */ +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) + +#define AFEC_CTL ((AFEC_TypeDef *) AFEC_BASE) + +#define RCC_APB1Periph_AFEC ((uint32_t)0x00000100) +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_Module* ADCx); +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_InitStruct(ADC_InitType* ADC_InitStruct); +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); +void ADC_StartCalibration(ADC_Module* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); +uint16_t ADC_GetDat(ADC_Module* ADCx); +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); +void ADC_EnableTempSensorVrefint(FunctionalState Cmd); +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); + +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); + +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); + +void Reference_Voltage_Switch(ADC_REFERENCE_Volt Ref_Type); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_ADC_H__ */ + +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_can.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_can.h new file mode 100644 index 0000000000000000000000000000000000000000..e4dcad93dcce6c67cba3ed582c87aee38424cb89 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_can.h @@ -0,0 +1,670 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_can.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_CAN_H__ +#define __N32L40X_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @addtogroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t OperatingMode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t RSJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t TBS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t TBS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitType; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t Filter_Scale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState Filter_Act; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitType; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMessage; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMessage; + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Constants + * @{ + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @addtogroup OperatingMode + * @{ + */ + +#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */ +#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) \ + (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \ + || ((MODE) == CAN_Silent_LoopBack_Mode)) +/** + * @} + */ + +/** + * @addtogroup CAN_operating_mode + * @{ + */ +#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */ + +#define IS_CAN_OPERATING_MODE(MODE) \ + (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode)) +/** + * @} + */ + +/** + * @addtogroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */ + +/** + * @} + */ + +/** @addtogroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_RSJW(SJW) \ + (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq)) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq) + +/** + * @} + */ + +/** @addtogroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13) +/** + * @} + */ + +/** @addtogroup CAN_filter_mode + * @{ + */ + +#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode)) +/** + * @} + */ + +/** @addtogroup CAN_filter_scale + * @{ + */ + +#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @addtogroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @addtogroup CAN_identifier_type + * @{ + */ + +#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id)) +/** + * @} + */ + +/** @addtogroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote)) + +/** + * @} + */ + +/** @addtogroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @addtogroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */ + +#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @addtogroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @addtogroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */ + +/** + * @} + */ + +/** @addtogroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */ +#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */ +#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */ +#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */ +#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */ +#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \ + || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \ + || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK)) + +#define IS_CAN_CLEAR_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \ + || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \ + || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + +/** @addtogroup CAN_interrupts + * @{ + */ + +#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/ +#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/ +#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/ +#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/ +#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/ +#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_INT_RQCPM0 CAN_INT_TME +#define CAN_INT_RQCPM1 CAN_INT_TME +#define CAN_INT_RQCPM2 CAN_INT_TME + +#define IS_CAN_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \ + || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \ + || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \ + || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +#define IS_CAN_CLEAR_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \ + || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \ + || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +/** + * @} + */ + +/** @addtogroup CAN_Legacy + * @{ + */ +#define CANINITSTSFAILED CAN_InitSTS_Failed +#define CANINITSTSOK CAN_InitSTS_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Standard_Id +#define CAN_ID_EXT CAN_Extended_Id +#define CAN_RTRQ_DATA CAN_RTRQ_Data +#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote +#define CANTXSTSFAILE CAN_TxSTS_Failed +#define CANTXSTSOK CAN_TxSTS_Ok +#define CANTXSTSPENDING CAN_TxSTS_Pending +#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox +#define CANSLEEPFAILED CAN_SLEEP_Failed +#define CANSLEEPOK CAN_SLEEP_Ok +#define CANWKUFAILED CAN_WKU_Failed +#define CANWKUOK CAN_WKU_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_Module* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam); +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct); +void CAN_InitStruct(CAN_InitType* CAN_InitParam); +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd); +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd); + +/* Transmit functions *********************************************************/ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage); +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage); +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum); +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_EnterSleep(CAN_Module* CANx); +uint8_t CAN_WakeUp(CAN_Module* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrCode(CAN_Module* CANx); +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx); +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd); +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG); +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT); +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_CAN_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_comp.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_comp.h new file mode 100644 index 0000000000000000000000000000000000000000..3a7d5b39dee4c2b42cbf03760d0da3b6136903e6 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_comp.h @@ -0,0 +1,282 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_comp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_COMP_H__ +#define __N32L40X_COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" +#include + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/** @addtogroup COMP_Exported_Constants + * @{ + */ +typedef enum +{ + COMP1 = 0, + COMP2 = 1, +} COMPX; + +// COMPx_CTRL +#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21) +#define COMP1_CTRL_INPDAC_MASK (0x01L << 20) +#define COMP_CTRL_OUT_MASK (0x01L << 19) +#define COMP_CTRL_BLKING_MASK (0x03L << 16) +typedef enum +{ + COMP_CTRL_BLKING_NO = (0x0L << 16), + COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16), + COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16), +} COMP_CTRL_BLKING; +#define COMPx_CTRL_HYST_MASK (0x03L << 14) +typedef enum +{ + COMP_CTRL_HYST_NO = (0x0L << 14), + COMP_CTRL_HYST_LOW = (0x1L << 14), + COMP_CTRL_HYST_MID = (0x2L << 14), + COMP_CTRL_HYST_HIGH = (0x3L << 14), +} COMP_CTRL_HYST; + +#define COMP_POL_MASK (0x01L << 13) +#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9) +typedef enum +{ + // comp1 out trig + COMP1_CTRL_OUTSEL_NC = (0x0L << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9), + COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9), + COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9), + COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9), + COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9), + COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9), + COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9), + COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9), + COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), + // comp2 out trig + COMP2_CTRL_OUTSEL_NC = (0x0L << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9), + COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9), + COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9), + COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9), + COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9), + COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9), + COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9), + COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9), + COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), +} COMP_CTRL_OUTTRIG; + +#define COMP_CTRL_INPSEL_MASK (0x0FL<<5) +typedef enum { + //comp1 inp sel + COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100), + COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140), + COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160), + COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180), + COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0), + COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0), + COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0), + COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120), + //comp2 inp sel + COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100), + COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120), + COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140), + COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160), + COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180), + COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0), + COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0), + COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0), +}COMP_CTRL_INPSEL; + + +#define COMP_CTRL_INMSEL_MASK (0x07L<<1) +typedef enum { + //comp1 inm sel + COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002), + COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004), + COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006), + COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008), + COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A), + COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C), + COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000), + //comp2 inm sel + COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002), + COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004), + COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006), + COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008), + COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A), + COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C), + COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000), +}COMP_CTRL_INMSEL; + +#define COMP_CTRL_EN_MASK (0x01L << 0) + +//COMPx_FILC +#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1. +#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2. +#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable. + +//COMPx_FILP +#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number . + +//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD +#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode. + +//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN +#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTEN_CMP2IEN (0x01L << 1) +#define COMP_INTEN_CMP1IEN (0x01L << 0) + +//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS +#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTSTS_CMP2IS (0x01L << 1) +#define COMP_INTSTS_CMP1IS (0x01L << 0) + +//COMP_VREFSCL @addtogroup COMP_VREFSCL +#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value. +#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7) +#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value. +#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0) + +//COMP_LOCK @addtogroup COMP_LOCK +#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value. +#define COMP_LOCK_CMP1LK (0x1L << 0) + +//COMP_LPCKSEL @addtogroup COMP_LPCKSEL +#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0) + +//COMP_OSEL @addtogroup COMP_OSEL +#define COMP_OSEL_CMP2XO (0x1L << 0) + +/** + * @} + */ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + // ctrl + bool LowPoweMode; // only COMP1 have this bit + bool InpDacConnect; // only COMP1 have this bit + + COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */ + + COMP_CTRL_HYST Hyst; + + bool PolRev; // out polarity reverse + + COMP_CTRL_OUTTRIG OutTrig; + COMP_CTRL_INPSEL InpSel; + COMP_CTRL_INMSEL InmSel; + + bool En; + + // filter + uint8_t SampWindow; // 5bit + uint8_t Thresh; // 5bit ,need > SampWindow/2 + bool FilterEn; + + // filter psc + uint16_t ClkPsc; +} COMP_InitType; + +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +void COMP_DeInit(void); +void COMP_StructInit(COMP_InitType* COMP_InitStruct); +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct); +void COMP_Enable(COMPX COMPx, FunctionalState en); +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel); +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel); +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig); +uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL +FlagStatus COMP_GetOutStatus(COMPX COMPx); +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx); +void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK +void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN +void COMP_CMP2XorOut(bool En); +void COMP_StopOrLowpower32KClkSel(bool En); +void COMP_WindowModeEn(bool En); +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal); +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW); +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST); +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_ADC_H */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_crc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..f5ff10ac11d434b069cad64e7399d111c915655c --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_crc.h @@ -0,0 +1,105 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_crc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_CRC_H__ +#define __N32L40X_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @addtogroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +void CRC32_ResetCrc(void); +uint32_t CRC32_CalcCrc(uint32_t Data); +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC32_GetCrc(void); +void CRC32_SetIDat(uint8_t IDValue); +uint8_t CRC32_GetIDat(void); + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength); +uint16_t CRC16_CalcCRC(uint8_t Data); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_CRC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dac.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..d902d503f45664fc9db560c8ba4677e79e507998 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dac.h @@ -0,0 +1,293 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dac.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_DAC_H__ +#define __N32L40X_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @addtogroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t + LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +} DAC_InitType; + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Constants + * @{ + */ + +/** @addtogroup DAC_trigger_selection + * @{ + */ + +#define DAC_TRG_NONE \ + ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \ + has been loaded, and not by external trigger */ +#define DAC_TRG_T6_TRGO \ + ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T8_TRGO \ + ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \ + only in High-density devices*/ +#define DAC_TRG_T7_TRGO \ + ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T5_TRGO \ + ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T2_TRGO \ + ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T4_TRGO \ + ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_EXT_IT9 \ + ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) \ + (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \ + || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \ + || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE)) + +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040) +#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) \ + (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_UNMASK_LFSRBITS1_0 \ + ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS2_0 \ + ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS3_0 \ + ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS4_0 \ + ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS5_0 \ + ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS6_0 \ + ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS7_0 \ + ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS8_0 \ + ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS9_0 \ + ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS10_0 \ + ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_UNMASK_LFSRBITS11_0 \ + ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \ + (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \ + || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \ + || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \ + || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \ + || ((VALUE) == DAC_TRIAMP_4095)) +/** + * @} + */ + +/** @addtogroup DAC_output_buffer + * @{ + */ + +#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002) +#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE)) +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup DAC_data_alignment + * @{ + */ + +#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000) +#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004) +#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) \ + (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT)) +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVE_NOISE ((uint32_t)0x00000040) +#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(DAC_InitType* DAC_InitStruct); +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct); +void DAC_Enable(FunctionalState Cmd); + +void DAC_DmaEnable(FunctionalState Cmd); +void DAC_SoftTrgEnable(FunctionalState Cmd); +void DAC_SoftwareTrgEnable(FunctionalState Cmd); +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd); +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data); +uint16_t DAC_GetOutputDataVal(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_DAC_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dbg.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dbg.h new file mode 100644 index 0000000000000000000000000000000000000000..7e6cf938c5a61a4bd7513496466948440f3ea67e --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dbg.h @@ -0,0 +1,124 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dbg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_DBG_H__ +#define __N32L40X_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @{ + */ + +/** @addtogroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBG_SLEEP ((uint32_t)0x00000001) +#define DBG_STOP ((uint32_t)0x00000002) +#define DBG_STDBY ((uint32_t)0x00000004) +#define DBG_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_TIM1_STOP ((uint32_t)0x00000400) +#define DBG_TIM2_STOP ((uint32_t)0x00000800) +#define DBG_TIM3_STOP ((uint32_t)0x00001000) +#define DBG_TIM4_STOP ((uint32_t)0x00002000) +#define DBG_CAN_STOP ((uint32_t)0x00004000) +#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBG_TIM8_STOP ((uint32_t)0x00020000) +#define DBG_TIM5_STOP ((uint32_t)0x00040000) +#define DBG_TIM6_STOP ((uint32_t)0x00080000) +#define DBG_TIM7_STOP ((uint32_t)0x00100000) +#define DBG_TIM9_STOP ((uint32_t)0x00200000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Functions + * @{ + */ + +void GetUCID(uint8_t *UCIDbuf); +void GetUID(uint8_t *UIDbuf); +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf); +uint32_t DBG_GetRevNum(void); +uint32_t DBG_GetDevNum(void); +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); + +uint32_t DBG_GetFlashSize(void); +uint32_t DBG_GetSramSize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_DBG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dma.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..7409fdb697695045e12759a8e365f45ba35a5348 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_dma.h @@ -0,0 +1,469 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dma.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_DMA_H__ +#define __N32L40X_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @addtogroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t Direction; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in PeriphDataSize + or MemDataSize members depending in the transfer direction. */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t MemDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitType; + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) \ + (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \ + || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8)) + +/** @addtogroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010) +#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040) +#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080) +#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000) +#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100) +#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200) +#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \ + || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD)) +/** + * @} + */ + +/** @addtogroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \ + || ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @addtogroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020) +#define DMA_MODE_NORMAL ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup DMA_priority_level + * @{ + */ + +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000) +#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000) +#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000) +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \ + || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW)) +/** + * @} + */ + +/** @addtogroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_ENABLE ((uint32_t)0x00004000) +#define DMA_M2M_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE)) + +/** + * @} + */ + +/** @addtogroup DMA_interrupts_definition + * @{ + */ + +#define DMA_INT_TXC ((uint32_t)0x00000002) +#define DMA_INT_HTX ((uint32_t)0x00000004) +#define DMA_INT_ERR ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA_INT_GLB1 ((uint32_t)0x00000001) +#define DMA_INT_TXC1 ((uint32_t)0x00000002) +#define DMA_INT_HTX1 ((uint32_t)0x00000004) +#define DMA_INT_ERR1 ((uint32_t)0x00000008) +#define DMA_INT_GLB2 ((uint32_t)0x00000010) +#define DMA_INT_TXC2 ((uint32_t)0x00000020) +#define DMA_INT_HTX2 ((uint32_t)0x00000040) +#define DMA_INT_ERR2 ((uint32_t)0x00000080) +#define DMA_INT_GLB3 ((uint32_t)0x00000100) +#define DMA_INT_TXC3 ((uint32_t)0x00000200) +#define DMA_INT_HTX3 ((uint32_t)0x00000400) +#define DMA_INT_ERR3 ((uint32_t)0x00000800) +#define DMA_INT_GLB4 ((uint32_t)0x00001000) +#define DMA_INT_TXC4 ((uint32_t)0x00002000) +#define DMA_INT_HTX4 ((uint32_t)0x00004000) +#define DMA_INT_ERR4 ((uint32_t)0x00008000) +#define DMA_INT_GLB5 ((uint32_t)0x00010000) +#define DMA_INT_TXC5 ((uint32_t)0x00020000) +#define DMA_INT_HTX5 ((uint32_t)0x00040000) +#define DMA_INT_ERR5 ((uint32_t)0x00080000) +#define DMA_INT_GLB6 ((uint32_t)0x00100000) +#define DMA_INT_TXC6 ((uint32_t)0x00200000) +#define DMA_INT_HTX6 ((uint32_t)0x00400000) +#define DMA_INT_ERR6 ((uint32_t)0x00800000) +#define DMA_INT_GLB7 ((uint32_t)0x01000000) +#define DMA_INT_TXC7 ((uint32_t)0x02000000) +#define DMA_INT_HTX7 ((uint32_t)0x04000000) +#define DMA_INT_ERR7 ((uint32_t)0x08000000) +#define DMA_INT_GLB8 ((uint32_t)0x10000000) +#define DMA_INT_TXC8 ((uint32_t)0x20000000) +#define DMA_INT_HTX8 ((uint32_t)0x40000000) +#define DMA_INT_ERR8 ((uint32_t)0x80000000) + + +#define IS_DMA_CLR_INT(IT) ((IT) != 0x00) + +#define IS_DMA_GET_IT(IT) \ + (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \ + || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \ + || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \ + || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \ + || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \ + || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \ + || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \ + || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8)) + +/** + * @} + */ + +/** @addtogroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA_FLAG_TE8 ((uint32_t)0x80000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00) + +#define IS_DMA_GET_FLAG(FLAG) \ + (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \ + || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \ + || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \ + || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \ + || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \ + || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \ + || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \ + || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \ + || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \ + || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \ + || ((FLAG) == DMA_FLAG_TE8)) +/** + * @} + */ + +/** @addtogroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** @addtogroup DMA_remap_request_definition + * @{ + */ +#define DMA_REMAP_ADC1 ((uint32_t)0x00000000) +#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001) +#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002) +#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003) +#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004) +#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005) +#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006) +#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007) +#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008) +#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009) +#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A) +#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B) +#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C) +#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D) +#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E) +#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F) +#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010) +#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011) +#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012) +#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013) +#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014) +#define DMA_REMAP_DAC1 ((uint32_t)0x00000015) +#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016) +#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017) +#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018) +#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019) +#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A) +#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B) +#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C) +#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D) +#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E) +#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F) +#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020) +#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021) +#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022) +#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023) +#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024) +#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025) +#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026) +#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027) +#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028) +#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029) +#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A) +#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B) +#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C) +#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D) +#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E) +#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F) +#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030) +#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031) +#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032) +#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033) +#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034) +#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035) +#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036) +#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037) +#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038) +#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039) +#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A) +#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B) +#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C) +#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D) +#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E) + + +#define IS_DMA_REMAP(FLAG) \ + (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \ + || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \ + || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \ + || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \ + || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \ + || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \ + || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \ + || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \ + || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \ + || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \ + || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \ + || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \ + || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \ + || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \ + || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \ + || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \ + || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_ChannelType* DMAChx); +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam); +void DMA_StructInit(DMA_InitType* DMA_InitParam); +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd); +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd); +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy); +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy); +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_DMA_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_exti.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..168ab543269395baed5e5fc5875738f0c8861e9b --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_exti.h @@ -0,0 +1,234 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_exti.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_EXTI_H__ +#define __N32L40X_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @addtogroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTI_ModeType; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTI_TriggerType; + +#define IS_EXTI_TRIGGER(TRIGGER) \ + (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \ + || ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitType; + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Constants + * @{ + */ + +/** @addtogroup EXTI_Lines + * @{ + */ + +#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ +#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */ +#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */ +#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */ +#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */ +#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */ +#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */ +#define EXTI_LINE26 ((uint32_t)0x4000000) /*!< External interrupt line 26 Connected to the LCD Global interrupt */ + + + + + + + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) \ + (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \ + || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \ + || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \ + || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \ + || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \ + || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \ + || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26)) + +/** + * @} + */ + +/** @addtogroup EXTI_TSSEL_Line + * @{ + */ +#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000) +#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */ +#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */ +#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */ +#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */ +#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */ +#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */ +#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */ +#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */ +#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */ +#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */ +#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */ +#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */ +#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */ +#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */ +#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */ +#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */ + +#define IS_EXTI_TSSEL_LINE(LINE) \ + (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \ + || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \ + || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \ + || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \ + || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \ + || ((LINE) == EXTI_TSSEL_LINE15)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct); +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct); +void EXTI_TriggerSWInt(uint32_t EXTI_Line); +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line); +void EXTI_ClrStatusFlag(uint32_t EXTI_Line); +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClrITPendBit(uint32_t EXTI_Line); +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_EXTI_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_flash.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..0c30cf910a4d7a215d7d4d59518ffd5ee9f8f09b --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_flash.h @@ -0,0 +1,501 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_flash.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_FLASH_H__ +#define __N32L40X_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_RESERVED, + FLASH_ERR_PG, + FLASH_ERR_PV, + FLASH_ERR_WRP, + FLASH_COMPL, + FLASH_ERR_EV, + FLASH_ERR_RDP2, + FLASH_ERR_ADD, + FLASH_TIMEOUT +} FLASH_STS; + +/** + * @brief FLASH_SMPSEL + */ + +typedef enum +{ + FLASH_SMP1 = 0, + FLASH_SMP2 +} FLASH_SMPSEL; + +/** + * @brief FLASH_HSICLOCK + */ + +typedef enum +{ + FLASH_HSICLOCK_ENABLE = 0, + FLASH_HSICLOCK_DISABLE +} FLASH_HSICLOCK; + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Constants + * @{ + */ + +/** @addtogroup Flash_Latency + * @{ + */ + +#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) \ + (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \ + || ((LATENCY) == FLASH_LATENCY_3)) +/** + * @} + */ + +/** @addtogroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS)) +/** + * @} + */ + +/** @addtogroup iCache_Enable_Disable + * @{ + */ + +#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */ +#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */ +#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS)) +/** + * @} + */ + +/** @addtogroup Low Voltage Mode + * @{ + */ + +#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */ +#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */ +#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS)) +/** + * @} + */ + +/** @addtogroup FLASH Sleep Mode + * @{ + */ + +#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */ +#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */ +#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS)) +/** + * @} + */ + +/** @addtogroup SMPSEL_SMP1_SMP2 + * @{ + */ + +#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */ +#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */ +#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2)) +/** + * @} + */ + +/* Values to be used with n32l40x devices */ +#define FLASH_WRP_Pages0to1 \ + ((uint32_t)0x00000001) /*!< n32l40x devices: \ + Write protection of page 0 to 1 */ +#define FLASH_WRP_Pages2to3 \ + ((uint32_t)0x00000002) /*!< n32l40x devices: \ + Write protection of page 2 to 3 */ +#define FLASH_WRP_Pages4to5 \ + ((uint32_t)0x00000004) /*!< n32l40x devices: \ + Write protection of page 4 to 5 */ +#define FLASH_WRP_Pages6to7 \ + ((uint32_t)0x00000008) /*!< n32l40x devices: \ + Write protection of page 6 to 7 */ +#define FLASH_WRP_Pages8to9 \ + ((uint32_t)0x00000010) /*!< n32l40x devices: \ + Write protection of page 8 to 9 */ +#define FLASH_WRP_Pages10to11 \ + ((uint32_t)0x00000020) /*!< n32l40x devices: \ + Write protection of page 10 to 11 */ +#define FLASH_WRP_Pages12to13 \ + ((uint32_t)0x00000040) /*!< n32l40x devices: \ + Write protection of page 12 to 13 */ +#define FLASH_WRP_Pages14to15 \ + ((uint32_t)0x00000080) /*!< n32l40x devices: \ + Write protection of page 14 to 15 */ +#define FLASH_WRP_Pages16to17 \ + ((uint32_t)0x00000100) /*!< n32l40x devices: \ + Write protection of page 16 to 17 */ +#define FLASH_WRP_Pages18to19 \ + ((uint32_t)0x00000200) /*!< n32l40x devices: \ + Write protection of page 18 to 19 */ +#define FLASH_WRP_Pages20to21 \ + ((uint32_t)0x00000400) /*!< n32l40x devices: \ + Write protection of page 20 to 21 */ +#define FLASH_WRP_Pages22to23 \ + ((uint32_t)0x00000800) /*!< n32l40x devices: \ + Write protection of page 22 to 23 */ +#define FLASH_WRP_Pages24to25 \ + ((uint32_t)0x00001000) /*!< n32l40x devices: \ + Write protection of page 24 to 25 */ +#define FLASH_WRP_Pages26to27 \ + ((uint32_t)0x00002000) /*!< n32l40x devices: \ + Write protection of page 26 to 27 */ +#define FLASH_WRP_Pages28to29 \ + ((uint32_t)0x00004000) /*!< n32l40x devices: \ + Write protection of page 28 to 29 */ +#define FLASH_WRP_Pages30to31 \ + ((uint32_t)0x00008000) /*!< n32l40x devices: \ + Write protection of page 30 to 31 */ +#define FLASH_WRP_Pages32to33 \ + ((uint32_t)0x00010000) /*!< n32l40x devices: \ + Write protection of page 32 to 33 */ +#define FLASH_WRP_Pages34to35 \ + ((uint32_t)0x00020000) /*!< n32l40x devices: \ + Write protection of page 34 to 35 */ +#define FLASH_WRP_Pages36to37 \ + ((uint32_t)0x00040000) /*!< n32l40x devices: \ + Write protection of page 36 to 37 */ +#define FLASH_WRP_Pages38to39 \ + ((uint32_t)0x00080000) /*!< n32l40x devices: \ + Write protection of page 38 to 39 */ +#define FLASH_WRP_Pages40to41 \ + ((uint32_t)0x00100000) /*!< n32l40x devices: \ + Write protection of page 40 to 41 */ +#define FLASH_WRP_Pages42to43 \ + ((uint32_t)0x00200000) /*!< n32l40x devices: \ + Write protection of page 42 to 43 */ +#define FLASH_WRP_Pages44to45 \ + ((uint32_t)0x00400000) /*!< n32l40x devices: \ + Write protection of page 44 to 45 */ +#define FLASH_WRP_Pages46to47 \ + ((uint32_t)0x00800000) /*!< n32l40x devices: \ + Write protection of page 46 to 47 */ +#define FLASH_WRP_Pages48to49 \ + ((uint32_t)0x01000000) /*!< n32l40x devices: \ + Write protection of page 48 to 49 */ +#define FLASH_WRP_Pages50to51 \ + ((uint32_t)0x02000000) /*!< n32l40x devices: \ + Write protection of page 50 to 51 */ +#define FLASH_WRP_Pages52to53 \ + ((uint32_t)0x04000000) /*!< n32l40x devices: \ + Write protection of page 52 to 53 */ +#define FLASH_WRP_Pages54to55 \ + ((uint32_t)0x08000000) /*!< n32l40x devices: \ + Write protection of page 54 to 55 */ +#define FLASH_WRP_Pages56to57 \ + ((uint32_t)0x10000000) /*!< n32l40x devices: \ + Write protection of page 56 to 57 */ +#define FLASH_WRP_Pages58to59 \ + ((uint32_t)0x20000000) /*!< n32l40x devices: \ + Write protection of page 58 to 59 */ +#define FLASH_WRP_Pages60to61 \ + ((uint32_t)0x40000000) /*!< n32l40x devices: \ + Write protection of page 60 to 61 */ +#define FLASH_WRP_Pages62to63 \ + ((uint32_t)0x80000000) /*!< n32l40x devices: + Write protection of page 62 to 63 */ + +#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRP_PAGE(PAGE) (1)//(((PAGE) <= FLASH_WRP_AllPages)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP1 + * @{ + */ + +#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */ +#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */ +#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ +#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) + + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP2 + * @{ + */ + +#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */ +#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */ +#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT0 + * @{ + */ + +#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */ +#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */ +#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT1 + * @{ + */ + +#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */ +#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */ +#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nSWBOOT0 + * @{ + */ + +#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */ +#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */ +#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_BOR_LEV + * @{ + */ + +#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */ +#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */ +#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */ +#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */ +#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */ +#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */ +#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */ +#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */ +#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ + || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \ + || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \ + || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7)) + + +/** + * @} + */ +/** @addtogroup FLASH_Interrupts + * @{ + */ +#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */ +#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */ +#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ + +#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @addtogroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */ +#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) \ + (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \ + || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \ + || ((FLAG) == FLASH_FLAG_OBERR)) + +/** + * @} + */ + +/** @addtogroup FLASH_STS_CLRFLAG + * @{ + */ +#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR) + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for n32l40x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf); +void FLASH_iCacheRST(void); +void FLASH_iCacheCmd(uint32_t FLASH_iCache); +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM); +FlagStatus FLASH_GetLowVoltageModeSTS(void); +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM); +FlagStatus FLASH_GetFLASHSleepModeSTS(void); +FLASH_HSICLOCK FLASH_ClockInit(void); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address); +FLASH_STS FLASH_MassErase(void); +FLASH_STS FLASH_EraseOB(void); +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages); +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd); +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void); +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY); +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +uint32_t FLASH_GetUserOB(void); +uint32_t FLASH_GetWriteProtectionOB(void); +FlagStatus FLASH_GetReadOutProtectionSTS(void); +FlagStatus FLASH_GetReadOutProtectionL2STS(void); +FlagStatus FLASH_GetPrefetchBufSTS(void); +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel); +FLASH_SMPSEL FLASH_GetSMPSELStatus(void); +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd); +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_STS FLASH_GetSTS(void); +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_FLASH_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_gpio.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..608a50f172c73fd83c98bc84311c7f93dfb3767f --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_gpio.h @@ -0,0 +1,676 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_gpio.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_GPIO_H__ +#define __N32L40X_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @addtogroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) \ + (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD)) + + +#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\ + ((PERIPH) == (GPIOB))? 1 :\ + ((PERIPH) == (GPIOC))? 2 :3) +#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\ + ((INDEX)==((uint8_t)0x01))? GPIOB :\ + ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD ) + + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Slew_Rate_High = 0, + GPIO_Slew_Rate_Low +} GPIO_SpeedType; +#define IS_GPIO_SLEW_RATE(_RATE_) \ + (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low)) + +/** + * @brief driver strength config + */ + +typedef enum +{ + GPIO_DC_2mA = 0x00, + GPIO_DC_4mA = 0x10, + GPIO_DC_8mA = 0x01, + GPIO_DC_12mA= 0x11 +}GPIO_CurrentType; + +#define IS_GPIO_CURRENT(CURRENT) \ + (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \ + || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA)) +/** + * @brief Configuration Mode enumeration + */ + + +/** @brief GPIO_mode_define Mode definition + * @brief GPIO Configuration Mode + * Values convention: 0xW0yz00YZ + * - W : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ + +typedef enum +{ + GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */ + GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */ + GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */ + GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */ + GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */ + + GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */ + + GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */ + GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */ + GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + + GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */ + GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */ + GPIO_Mode_EVT_Rising_Falling = 0x10320000 +}GPIO_ModeType; + + + +/** + * @} + */ +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\ + ((__MODE__) == GPIO_Mode_Out_PP) ||\ + ((__MODE__) == GPIO_Mode_Out_OD) ||\ + ((__MODE__) == GPIO_Mode_AF_PP) ||\ + ((__MODE__) == GPIO_Mode_AF_OD) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising) ||\ + ((__MODE__) == GPIO_Mode_IT_Falling) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising) ||\ + ((__MODE__) == GPIO_Mode_EVT_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_Analog)) + +/** + * @} + */ + +/** + * @} + */ + +/** @brief GPIO_pull_define Pull definition + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ + +typedef enum +{ + GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */ + GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */ + GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */ +}GPIO_PuPdType; +/** + * @} + */ + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \ + ((__PULL__) == GPIO_Pull_Down)) +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIO_CurrentType GPIO_Current; /*!. + This paramter can be a value of @ref GPIO_CurrentType*/ + + GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_SpeedType */ + + GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_ModeType */ + + uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitType; + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} Bit_OperateType; + +#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET)) + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Exported_Constants + * @{ + */ + +/** @addtogroup GPIO_pins_define + * @{ + */ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF) + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) \ + (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \ + || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \ + || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \ + || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15)) + + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE)))) + + + + + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Port_Sources + * @{ + */ + +#define GPIOA_PORT_SOURCE ((uint8_t)0x00) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01) +#define GPIOC_PORT_SOURCE ((uint8_t)0x02) +#define GPIOD_PORT_SOURCE ((uint8_t)0x03) + +#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + + +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +/** + * @} + */ + +/** @addtogroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00) +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01) +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02) +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03) +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04) +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05) +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06) +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07) +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08) +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09) +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A) +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B) +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C) +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D) +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E) +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) \ + (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE15)) + +/** + * @} + */ + + + +/** @defgroup GPIOx_Alternate_function_selection Alternate function selection + * @{ + */ + +/* + * Alternate function AF0 + */ +#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */ +#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF1 + */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */ +#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF2 + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF3 + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF4 + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF5 + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */ +#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF6 + */ + +#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */ +#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */ +#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF7 + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */ +#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */ +#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */ +#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF8 + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */ +#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF9 + */ +#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */ +#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF10 + */ +#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF11 + */ +#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ + + + /* + * Alternate function AF15 + */ +#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */ + +#define GPIO_NO_AF (GPIO_AF15) +/** + * @} + */ + + +/** + * IS_GPIO_AF macro definition + */ + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \ + ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \ + ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \ + ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \ + ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \ + ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \ + ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \ + ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \ + ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \ + ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \ + ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \ + ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \ + ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \ + ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \ + ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \ + ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \ + ((__AF__) == GPIO_AF10_LCD) || ((__AF__) == GPIO_AF11_LCD) || \ + ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF)) + + + + + +/** + * @} + */ +/** @defgroup GPIO Alternate function remaping + * @{ + */ +#define AFIO_SPI1_NSS (11U) +#define AFIO_SPI2_NSS (10U) + +#define IS_AFIO_SPIX(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS)) +typedef enum +{ + AFIO_SPI_NSS_High_IMPEDANCE = 0U, + AFIO_SPI_NSS_High_LEVEL = 1U +}AFIO_SPI_NSSType; + +#define IS_AFIO_SPI_NSS(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL)) + + +typedef enum +{ + AFIO_ADC_ETRI= 9U, + AFIO_ADC_ETRR = 8U +}AFIO_ADC_ETRType; + +typedef enum +{ + AFIO_ADC_TRIG_EXTI_0 = 0x0U, + AFIO_ADC_TRIG_EXTI_1 = 0x01U, + AFIO_ADC_TRIG_EXTI_2, + AFIO_ADC_TRIG_EXTI_3, + AFIO_ADC_TRIG_EXTI_4, + AFIO_ADC_TRIG_EXTI_5, + AFIO_ADC_TRIG_EXTI_6, + AFIO_ADC_TRIG_EXTI_7, + AFIO_ADC_TRIG_EXTI_8, + AFIO_ADC_TRIG_EXTI_9, + AFIO_ADC_TRIG_EXTI_10, + AFIO_ADC_TRIG_EXTI_11, + AFIO_ADC_TRIG_EXTI_12, + AFIO_ADC_TRIG_EXTI_13, + AFIO_ADC_TRIG_EXTI_14, + AFIO_ADC_TRIG_EXTI_15, + AFIO_ADC_TRIG_TIM8_CH3, + AFIO_ADC_TRIG_TIM8_CH4 +}AFIO_ADC_Trig_RemapType; + +#define IS_AFIO_ADC_ETR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR)) +#define IS_AFIO_ADC_ETRI(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4)) + +#define IS_AFIO_ADC_ETRR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3)) + + /** + * @} + */ + +/** @addtogroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_Module* GPIOx); +void GPIO_AFIOInitDefault(void); +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct); +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx); +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd); +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal); +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource); +void GPIO_CtrlEventOutput(FunctionalState Cmd); +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction); +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource); + +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType); +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_GPIO_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_i2c.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..60a81b419795f09c00816feda5c18081d8594a75 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_i2c.h @@ -0,0 +1,671 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_i2c.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_I2C_H__ +#define __N32L40X_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @addtogroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t ClkSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t BusMode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_BusMode */ + + uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t OwnAddr1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t AckEnable; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitType; + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2)) +/** @addtogroup I2C_BusMode + * @{ + */ + +#define I2C_BUSMODE_I2C ((uint16_t)0x0000) +#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002) +#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A) +#define IS_I2C_BUS_MODE(MODE) \ + (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST)) +/** + * @} + */ + +/** @addtogroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledgement + * @{ + */ + +#define I2C_ACKEN ((uint16_t)0x0400) +#define I2C_ACKDIS ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS)) +/** + * @} + */ + +/** @addtogroup I2C_transfer_direction + * @{ + */ + +#define I2C_DIRECTION_SEND ((uint8_t)0x00) +#define I2C_DIRECTION_RECV ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledged_address + * @{ + */ + +#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000) +#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000) +#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT)) +/** + * @} + */ + +/** @addtogroup I2C_registers + * @{ + */ + +#define I2C_REG_CTRL1 ((uint8_t)0x00) +#define I2C_REG_CTRL2 ((uint8_t)0x04) +#define I2C_REG_OADDR1 ((uint8_t)0x08) +#define I2C_REG_OADDR2 ((uint8_t)0x0C) +#define I2C_REG_DAT ((uint8_t)0x10) +#define I2C_REG_STS1 ((uint8_t)0x14) +#define I2C_REG_STS2 ((uint8_t)0x18) +#define I2C_REG_CLKCTRL ((uint8_t)0x1C) +#define I2C_REG_TMRISE ((uint8_t)0x20) +#define IS_I2C_REG(REGISTER) \ + (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \ + || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \ + || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE)) +/** + * @} + */ + +/** @addtogroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBALERT_LOW ((uint16_t)0x2000) +#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF) +#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH)) +/** + * @} + */ + +/** @addtogroup I2C_PEC_position + * @{ + */ + +#define I2C_PEC_POS_NEXT ((uint16_t)0x0800) +#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACK_POS_NEXT ((uint16_t)0x0800) +#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_BUF ((uint16_t)0x0400) +#define I2C_INT_EVENT ((uint16_t)0x0200) +#define I2C_INT_ERR ((uint16_t)0x0100) +#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_SMBALERT ((uint32_t)0x01008000) +#define I2C_INT_TIMOUT ((uint32_t)0x01004000) +#define I2C_INT_PECERR ((uint32_t)0x01001000) +#define I2C_INT_OVERRUN ((uint32_t)0x01000800) +#define I2C_INT_ACKFAIL ((uint32_t)0x01000400) +#define I2C_INT_ARLOST ((uint32_t)0x01000200) +#define I2C_INT_BUSERR ((uint32_t)0x01000100) +#define I2C_INT_TXDATE ((uint32_t)0x06000080) +#define I2C_INT_RXDATNE ((uint32_t)0x06000040) +#define I2C_INT_STOPF ((uint32_t)0x02000010) +#define I2C_INT_ADDR10F ((uint32_t)0x02000008) +#define I2C_INT_BYTEF ((uint32_t)0x02000004) +#define I2C_INT_ADDRF ((uint32_t)0x02000002) +#define I2C_INT_STARTBF ((uint32_t)0x02000001) + +#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_INT(IT) \ + (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \ + || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \ + || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \ + || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_flags_definition + * @{ + */ + +/** + * @brief STS2 register flags + */ + +#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000) +#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000) +#define I2C_FLAG_TRF ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSMODE ((uint32_t)0x00010000) + +/** + * @brief STS1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800) +#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400) +#define I2C_FLAG_ARLOST ((uint32_t)0x10000200) +#define I2C_FLAG_BUSERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXDATE ((uint32_t)0x10000080) +#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008) +#define I2C_FLAG_BYTEF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDRF ((uint32_t)0x10000002) +#define I2C_FLAG_STARTBF ((uint32_t)0x10000001) + +#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) \ + (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \ + || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \ + || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \ + || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \ + || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \ + || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \ + || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateStart() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* Master mode */ +#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */ +/* --EV5 */ +#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_SendAddr7bit() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_RecvData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +/* EV7x shifter register full */ +#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_ConfigAck()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled + * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) + * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and + * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV2x */ +#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */ +/* --EV4 */ +#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVT(EVENT) \ + (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS)) +/** + * @} + */ + +/** @addtogroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @addtogroup I2C_clock_speed + * @{ + */ + +//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_Module* I2Cx); +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_InitStruct(I2C_InitType* I2C_InitStruct); +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd); +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); +uint8_t I2C_RecvData(I2C_Module* I2Cx); +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register); +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition); +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition); +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd); +uint8_t I2C_GetPec(I2C_Module* I2Cx); +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlag() function (see below). + * The returned value could be compared to events already defined in the + * library (n32l40x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT); +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..b5915a83e723bd338f707b8eaf160947d7f6485e --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h @@ -0,0 +1,145 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_iwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_IWDG_H__ +#define __N32L40X_IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @addtogroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Constants + * @{ + */ + +/** @addtogroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WRITE_ENABLE ((uint16_t)0x5555) +#define IWDG_WRITE_DISABLE ((uint16_t)0x0000) +#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE)) +/** + * @} + */ + +/** @addtogroup IWDG_prescaler + * @{ + */ + +#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00) +#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01) +#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02) +#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03) +#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04) +#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05) +#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV256)) +/** + * @} + */ + +/** @addtogroup IWDG_Flag + * @{ + */ + +#define IWDG_PVU_FLAG ((uint16_t)0x0001) +#define IWDG_CRVU_FLAG ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler); +void IWDG_CntReload(uint16_t Reload); +void IWDG_ReloadKey(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_IWDG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lcd.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..18ba2cd50c40e1ce3b7d36be0188510964a9134f --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lcd.h @@ -0,0 +1,735 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_lcd.hd + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#ifndef __N32L40X_LCD_H__ +#define __N32L40X_LCD_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32l40x.h" +/** @addtogroup N32L40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LCD + * @{ + */ + +/* LCD Exported constants --------------------------------------------------------*/ +/** @addtogroup LCD_Exported_Constants LCD Exported Constants + * @{ + */ + +/** + * @brief LCD error code + */ +typedef enum { + LCD_ERROR_OK = 0x00, /*!< No error */ + LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag error */ + LCD_ERROR_UDR = 0x02, /*!< Update display request flag error */ + LCD_ERROR_UDD = 0x03, /*!< Update display done flag error */ + LCD_ERROR_ENSTS = 0x04, /*!< LCD enabled status flag error */ + LCD_ERROR_RDY = 0x05, /*!< LCD VLCD ready flag error */ + LCD_ERROR_PARAM = 0x06, /*!< LCD function parameter error */ + LCD_ERROR_CLK = 0x07, /*!< LCD clock source fail error */ +}LCD_ErrorTypeDef; + +/** +* @brief LCD normal timeout +*/ +#define LCD_TIME_OUT (0x01000000) + +/** + * @defgroup LCD_Clock_Source + */ +#define LCD_CLK_SRC_LSI (RCC_RTCCLK_SRC_LSI) /*!< LSI*/ +#define LCD_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_RTCCLK_SRC_LSE) /*!< LSE */ +#define LCD_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_RTCCLK_SRC_LSE) /*!< LSE bypass */ +#define LCD_CLK_SRC_HSE_DIV32 (RCC_HSE_ENABLE|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE */ +#define LCD_CLK_SRC_HSE_BYPASS_DIV32 (RCC_HSE_BYPASS|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE bypass */ + +/** + * @} + */ + +/** + * @defgroup LCD_RAMRegister + */ +#define LCD_RAM1_COM0 (0x00000000U) +#define LCD_RAM2_COM0 (0x00000001U) +#define LCD_RAM1_COM1 (0x00000002U) +#define LCD_RAM2_COM1 (0x00000003U) +#define LCD_RAM1_COM2 (0x00000004U) +#define LCD_RAM2_COM2 (0x00000005U) +#define LCD_RAM1_COM3 (0x00000006U) +#define LCD_RAM2_COM3 (0x00000007U) +#define LCD_RAM1_COM4 (0x00000008U) +#define LCD_RAM2_COM4 (0x00000009U) +#define LCD_RAM1_COM5 (0x0000000AU) +#define LCD_RAM2_COM5 (0x0000000BU) +#define LCD_RAM1_COM6 (0x0000000CU) +#define LCD_RAM2_COM6 (0x0000000DU) +#define LCD_RAM1_COM7 (0x0000000EU) +#define LCD_RAM2_COM7 (0x0000000FU) +/** + * @} + */ + +/** + * @defgroup LCD_Prescaler + */ +#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */ +#define LCD_PRESCALER_2 (0x1UL << LCD_FCTRL_PRES_Pos) /*!< 0x00400000U CLKPS = LCDCLK/2 */ +#define LCD_PRESCALER_4 (0x2UL << LCD_FCTRL_PRES_Pos) /*!< 0x00800000U CLKPS = LCDCLK/4 */ +#define LCD_PRESCALER_8 (0x3UL << LCD_FCTRL_PRES_Pos) /*!< 0x00C00000U CLKPS = LCDCLK/8 */ +#define LCD_PRESCALER_16 (0x4UL << LCD_FCTRL_PRES_Pos) /*!< 0x01000000U CLKPS = LCDCLK/16 */ +#define LCD_PRESCALER_32 (0x5UL << LCD_FCTRL_PRES_Pos) /*!< 0x01400000U CLKPS = LCDCLK/32 */ +#define LCD_PRESCALER_64 (0x6UL << LCD_FCTRL_PRES_Pos) /*!< 0x01800000U CLKPS = LCDCLK/64 */ +#define LCD_PRESCALER_128 (0x7UL << LCD_FCTRL_PRES_Pos) /*!< 0x01C00000U CLKPS = LCDCLK/128 */ +#define LCD_PRESCALER_256 (0x8UL << LCD_FCTRL_PRES_Pos) /*!< 0x02000000U CLKPS = LCDCLK/256 */ +#define LCD_PRESCALER_512 (0x9UL << LCD_FCTRL_PRES_Pos) /*!< 0x02400000U CLKPS = LCDCLK/512 */ +#define LCD_PRESCALER_1024 (0xAUL << LCD_FCTRL_PRES_Pos) /*!< 0x02800000U CLKPS = LCDCLK/1024 */ +#define LCD_PRESCALER_2048 (0xBUL << LCD_FCTRL_PRES_Pos) /*!< 0x02C00000U CLKPS = LCDCLK/2048 */ +#define LCD_PRESCALER_4096 (0xCUL << LCD_FCTRL_PRES_Pos) /*!< 0x03000000U CLKPS = LCDCLK/4096 */ +#define LCD_PRESCALER_8192 (0xDUL << LCD_FCTRL_PRES_Pos) /*!< 0x03400000U CLKPS = LCDCLK/8192 */ +#define LCD_PRESCALER_16384 (0xEUL << LCD_FCTRL_PRES_Pos) /*!< 0x03800000U CLKPS = LCDCLK/16384 */ +#define LCD_PRESCALER_32768 (0xFUL << LCD_FCTRL_PRES_Pos) /*!< 0x03C00000U CLKPS = LCDCLK/32768 */ +/** + * @} + */ + +/** + * @defgroup LCD_Divider + */ +#define LCD_DIV_16 (0x00000000U) /*!< CLKDIV = CLKPS/(16) */ +#define LCD_DIV_17 (0x1UL << LCD_FCTRL_DIV_Pos) /*!< 0x00040000U CLKDIV = CLKPS/(17) */ +#define LCD_DIV_18 (0x2UL << LCD_FCTRL_DIV_Pos) /*!< 0x00080000U CLKDIV = CLKPS/(18) */ +#define LCD_DIV_19 (0x3UL << LCD_FCTRL_DIV_Pos) /*!< 0x000C0000U CLKDIV = CLKPS/(19) */ +#define LCD_DIV_20 (0x4UL << LCD_FCTRL_DIV_Pos) /*!< 0x00100000U CLKDIV = CLKPS/(20) */ +#define LCD_DIV_21 (0x5UL << LCD_FCTRL_DIV_Pos) /*!< 0x00140000U CLKDIV = CLKPS/(21) */ +#define LCD_DIV_22 (0x6UL << LCD_FCTRL_DIV_Pos) /*!< 0x00180000U CLKDIV = CLKPS/(22) */ +#define LCD_DIV_23 (0x7UL << LCD_FCTRL_DIV_Pos) /*!< 0x001C0000U CLKDIV = CLKPS/(23) */ +#define LCD_DIV_24 (0x8UL << LCD_FCTRL_DIV_Pos) /*!< 0x00200000U CLKDIV = CLKPS/(24) */ +#define LCD_DIV_25 (0x9UL << LCD_FCTRL_DIV_Pos) /*!< 0x00240000U CLKDIV = CLKPS/(25) */ +#define LCD_DIV_26 (0xAUL << LCD_FCTRL_DIV_Pos) /*!< 0x00280000U CLKDIV = CLKPS/(26) */ +#define LCD_DIV_27 (0xBUL << LCD_FCTRL_DIV_Pos) /*!< 0x002C0000U CLKDIV = CLKPS/(27) */ +#define LCD_DIV_28 (0xCUL << LCD_FCTRL_DIV_Pos) /*!< 0x00300000U CLKDIV = CLKPS/(28) */ +#define LCD_DIV_29 (0xDUL << LCD_FCTRL_DIV_Pos) /*!< 0x00340000U CLKDIV = CLKPS/(29) */ +#define LCD_DIV_30 (0xEUL << LCD_FCTRL_DIV_Pos) /*!< 0x00380000U CLKDIV = CLKPS/(30) */ +#define LCD_DIV_31 (0xFUL << LCD_FCTRL_DIV_Pos) /*!< 0x003C0000U CLKDIV = CLKPS/(31) */ +/** + * @} + */ + +/** + * @defgroup LCD_Duty + */ +#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */ +#define LCD_DUTY_1_2 (0x1UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/2 duty */ +#define LCD_DUTY_1_3 (0x2UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/3 duty */ +#define LCD_DUTY_1_4 (0x3UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/4 duty */ +#define LCD_DUTY_1_8 (0x4UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/8 duty */ +/** + * @} + */ + +/** + * @defgroup LCD_Bias + */ +#define LCD_BIAS_1_2 (0x00000000U) /*!< 1/2 Bias */ +#define LCD_BIAS_1_3 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000020U 1/3 Bias */ +#define LCD_BIAS_1_4 (0x2UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000040U 1/4 Bias */ +/** + * @} + */ + +/** + * @defgroup LCD_Voltage_source + */ +#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_EXTERNAL (LCD_CTRL_VSEL) /*!< External voltage source for the LCD */ +/** + * @} + */ + +/** + * @defgroup LCD_Contrast + */ +#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_1 (0x1UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000400U Maximum Voltage = 2.73V */ +#define LCD_CONTRASTLEVEL_2 (0x2UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000800U Maximum Voltage = 2.86V */ +#define LCD_CONTRASTLEVEL_3 (0x3UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000C00U Maximum Voltage = 2.99V */ +#define LCD_CONTRASTLEVEL_4 (0x4UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001000U Maximum Voltage = 3.12V */ +#define LCD_CONTRASTLEVEL_5 (0x5UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001400U Maximum Voltage = 3.26V */ +#define LCD_CONTRASTLEVEL_6 (0x6UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001800U Maximum Voltage = 3.40V */ +#define LCD_CONTRASTLEVEL_7 (0x7UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001C00U Maximum Voltage = 3.55V */ +/** + * @} + */ + +/** + * @defgroup LCD_DeadTime + */ +#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */ +#define LCD_DEADTIME_1 (0x1UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000080U One Phase between different couple of Frame */ +#define LCD_DEADTIME_2 (0x2UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000100U Two Phase between different couple of Frame */ +#define LCD_DEADTIME_3 (0x3UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000180UThree Phase between different couple of Frame */ +#define LCD_DEADTIME_4 (0x4UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000200UFour Phase between different couple of Frame */ +#define LCD_DEADTIME_5 (0x5UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000280UFive Phase between different couple of Frame */ +#define LCD_DEADTIME_6 (0x6UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000300USix Phase between different couple of Frame */ +#define LCD_DEADTIME_7 (0x7UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000380USeven Phase between different couple of Frame */ +/** + * @} + */ + +/** + * @defgroup LCD_PulseOnDuration + */ +#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_1 (0x1U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000010U Pulse ON duration = 1/CK_PS */ +#define LCD_PULSEONDURATION_2 (0x2U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000020U Pulse ON duration = 2/CK_PS */ +#define LCD_PULSEONDURATION_3 (0x3U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000030U Pulse ON duration = 3/CK_PS */ +#define LCD_PULSEONDURATION_4 (0x4U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000040U Pulse ON duration = 4/CK_PS */ +#define LCD_PULSEONDURATION_5 (0x5U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000050U Pulse ON duration = 5/CK_PS */ +#define LCD_PULSEONDURATION_6 (0x6U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000060U Pulse ON duration = 6/CK_PS */ +#define LCD_PULSEONDURATION_7 (0x7U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000070U Pulse ON duration = 7/CK_PS */ +/** + * @} + */ + +/** + * @defgroup LCD_HighDrive + */ +#define LCD_HIGHDRIVE_DISABLE (0x00000000U) /*!< High drive disabled */ +#define LCD_HIGHDRIVE_ENABLE (LCD_FCTRL_HDEN) /*!< High drive enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_HighDrive_Buffer + */ +#define LCD_HIGHDRIVEBUFFER_DISABLE (0x00000000U) /*!< High drive buffer disabled */ +#define LCD_HIGHDRIVEBUFFER_ENABLE (LCD_CTRL_BUFEN) /*!< High drive buffer enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_Blink_Mode + */ +#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disable */ +#define LCD_BLINKMODE_SEG0_COM0 (0x1UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00010000U Blink enabled on SEG[0], COM[0] (1 pixel) */ +#define LCD_BLINKMODE_SEG0_ALLCOM (0x2UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00020000U Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */ +#define LCD_BLINKMODE_ALLSEG_ALLCOM (0x3UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00030000U Blink enabled on all SEG and all COM (all pixels) */ +/** + * @} + */ + +/** + * @defgroup LCD_Blink_Frequency + */ +#define LCD_BLINKFREQ_DIV_8 (0x00000000U) /*!< The Blink frequency = fck_div/8 */ +#define LCD_BLINKFREQ_DIV_16 (0x1UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00002000U The Blink frequency = fck_div/16 */ +#define LCD_BLINKFREQ_DIV_32 (0x2UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00004000U The Blink frequency = fck_div/32 */ +#define LCD_BLINKFREQ_DIV_64 (0x3UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00006000U The Blink frequency = fck_div/64 */ +#define LCD_BLINKFREQ_DIV_128 (0x4UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00008000U The Blink frequency = fck_div/128 */ +#define LCD_BLINKFREQ_DIV_256 (0x5UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000A000U The Blink frequency = fck_div/256 */ +#define LCD_BLINKFREQ_DIV_512 (0x6UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000C000U The Blink frequency = fck_div/512 */ +#define LCD_BLINKFREQ_DIV_1024 (0x7UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000E000U The Blink frequency = fck_div/1024 */ +/** + * @} + */ + +/** + * @defgroup LCD_MuxSegment + */ +#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< Mux segment disabled */ +#define LCD_MUXSEGMENT_ENABLE (LCD_CTRL_MUXSEG) /*!< Mux segment enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_Interrupt + */ +#define LCD_IT_UDD (LCD_FCTRL_UDDIE) /*!< Update display done interrupt */ +#define LCD_IT_SOF (LCD_FCTRL_SOFIE) /*!< Start of frame interrupt */ +/** + * @} + */ + +/** + * @defgroup LCD_Flag + */ +#define LCD_FLAG_ENSTS (LCD_STS_ENSTS) /*!< LCD enable flag*/ +#define LCD_FLAG_SOF (LCD_STS_SOF) /*!< LCD start of frame event flag*/ +#define LCD_FLAG_UDR (LCD_STS_UDR) /*!< Update display request Flag*/ +#define LCD_FLAG_UDD (LCD_STS_UDD) /*!< Update display done event flag */ +#define LCD_FLAG_RDY (LCD_STS_RDY) /*!< Ready flag */ +#define LCD_FLAG_FCRSF (LCD_STS_FCRSF) /*!< LCD frame control register synchronization flag */ +/** + * @} + */ + +/** + * @defgroup LCD_Flag_Clear + */ +#define LCD_FLAG_SOF_CLEAR (LCD_CLR_SOFCLR) /*!< Clear LCD start of frame event flag*/ +#define LCD_FLAG_UDD_CLEAR (LCD_CLR_UDDCLR) /*!< Clear Update display done event flag */ +/** + * @} + */ + + +/* LCD Exported macros -----------------------------------------------------------*/ +/** @defgroup LCD_Exported_Macros LCD Exported Macros + * @{ + */ + +/** @brief Enable the LCD peripheral. + * @param None + * @retval None + */ +#define __LCD_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_LCDEN) + +/** @brief Disable the LCD peripheral. + * @param None + * @retval None + */ +#define __LCD_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_LCDEN) + +/** @brief Enable the LCD voltage output buffer. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_BUF_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_BUFEN) + +/** @brief Disable the LCD voltage output buffer. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_BUF_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_BUFEN) + +/** @brief Enable the LCD mux segment. + * @param None + * @retval None + */ +#define __LCD_MUXSEG_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_MUXSEG) + +/** @brief Disable the LCD mux segment. + * @param None + * @retval None + */ +#define __LCD_MUXSEG_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_MUXSEG) + +/** @brief Select internal VLCD as LCD voltage source + * @param None + * @retval None + */ +#define __LCD_SELECT_INTERNAL_VLCD() CLEAR_BIT(LCD->CTRL, LCD_CTRL_VSEL) + +/** @brief Select external VLCD as LCD voltage source + * @param None + * @retval None + */ +#define __LCD_SELECT_EXTERNAL_VLCD() SET_BIT(LCD->CTRL, LCD_CTRL_VSEL) + +/** @brief Enable the LCD high driver mode. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_ENABLE() SET_BIT(LCD->FCTRL, LCD_FCTRL_HDEN) + +/** @brief Disable the LCD high driver mode. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_DISABLE() CLEAR_BIT(LCD->FCTRL, LCD_FCTRL_HDEN) + +/** @brief Config the prescaler factor + * @param __PRES__ specifies the LCD prescaler + * This parameter can be one of the following values: + * @arg LCD_PRESCALER_1: CLKPS = LCDCLK + * @arg LCD_PRESCALER_2: CLKPS = LCDCLK/2 + * @arg LCD_PRESCALER_4: CLKPS = LCDCLK/4 + * @arg LCD_PRESCALER_8: CLKPS = LCDCLK/8 + * @arg LCD_PRESCALER_16: CLKPS = LCDCLK/16 + * @arg LCD_PRESCALER_32: CLKPS = LCDCLK/32 + * @arg LCD_PRESCALER_64: CLKPS = LCDCLK/64 + * @arg LCD_PRESCALER_128: CLKPS = LCDCLK/128 + * @arg LCD_PRESCALER_256: CLKPS = LCDCLK/256 + * @arg LCD_PRESCALER_512: CLKPS = LCDCLK/512 + * @arg LCD_PRESCALER_1024: CLKPS = LCDCLK/1024 + * @arg LCD_PRESCALER_2048: CLKPS = LCDCLK/2048 + * @arg LCD_PRESCALER_4096: CLKPS = LCDCLK/4096 + * @arg LCD_PRESCALER_8192: CLKPS = LCDCLK/8192 + * @arg LCD_PRESCALER_16384: CLKPS = LCDCLK/16384 + * @arg LCD_PRESCALER_32768: CLKPS = LCDCLK/32768 + * @retval None + */ +#define __LCD_PRESCALER_CONFIG(__PRES__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PRES,__PRES__) + +/** @brief Config the divider factor + * @param __DIV__ specifies the LCD divider + * This parameter can be one of the following values: + * @arg LCD_DIV_16: CLKDIV = CLKPS/(16) + * @arg LCD_DIV_17: CLKDIV = CLKPS/(17) + * @arg LCD_DIV_18: CLKDIV = CLKPS/(18) + * @arg LCD_DIV_19: CLKDIV = CLKPS/(19) + * @arg LCD_DIV_20: CLKDIV = CLKPS/(20) + * @arg LCD_DIV_21: CLKDIV = CLKPS/(21) + * @arg LCD_DIV_22: CLKDIV = CLKPS/(22) + * @arg LCD_DIV_23: CLKDIV = CLKPS/(23) + * @arg LCD_DIV_24: CLKDIV = CLKPS/(24) + * @arg LCD_DIV_25: CLKDIV = CLKPS/(25) + * @arg LCD_DIV_26: CLKDIV = CLKPS/(26) + * @arg LCD_DIV_27: CLKDIV = CLKPS/(27) + * @arg LCD_DIV_28: CLKDIV = CLKPS/(28) + * @arg LCD_DIV_29: CLKDIV = CLKPS/(29) + * @arg LCD_DIV_30: CLKDIV = CLKPS/(30) + * @arg LCD_DIV_31: CLKDIV = CLKPS/(31) + * @retval None + */ +#define __LCD_DIVIDER_CONFIG(__DIV__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DIV,__DIV__) + +/** @brief Config the blink mode and frequency + * @param __BLINKMODE__ specifies the LCD blink mode + * This parameter can be one of the following values: + * @arg LCD_DIV_16: CLKDIV = CLKPS/(16) + * @arg LCD_BLINKMODE_OFF: Blink disable + * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) + * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) + * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels) + * @param __BLINKFREQUENCY__ specifies the LCD blink frequency + * This parameter can be one of the following values: + * @arg LCD_BLINKFREQ_DIV_8: The Blink frequency = fck_div/8 + * @arg LCD_BLINKFREQ_DIV_16: The Blink frequency = fck_div/16 + * @arg LCD_BLINKFREQ_DIV_32: The Blink frequency = fck_div/32 + * @arg LCD_BLINKFREQ_DIV_64: The Blink frequency = fck_div/64 + * @arg LCD_BLINKFREQ_DIV_128: The Blink frequency = fck_div/128 + * @arg LCD_BLINKFREQ_DIV_256: The Blink frequency = fck_div/256 + * @arg LCD_BLINKFREQ_DIV_512: The Blink frequency = fck_div/512 + * @arg LCD_BLINKFREQ_DIV_1024: The Blink frequency = fck_div/1024 + * @retval None + */ +#define __LCD_BLINK_CONFIG(__BLINKMODE__,__BLINKFREQUENCY__) MODIFY_REG(LCD->FCTRL, (LCD_FCTRL_BLINK|LCD_FCTRL_BLINKF),(__BLINKMODE__|__BLINKFREQUENCY__)) + + +/** @brief Config the contrast + * @param __CONTRAST__ specifies the LCD contrast + * This parameter can be one of the following values: + * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V + * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V + * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V + * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V + * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V + * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.26V + * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.40V + * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.55V + * @retval None + */ +#define __LCD_CONTRAST_CONFIG(__CONTRAST__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_CONTRAST,__CONTRAST__) + +/** @brief Config the dead time + * @param __CONTRAST__ specifies the LCD dead time + * This parameter can be one of the following values: + * @arg LCD_DEADTIME_0: No dead Time + * @arg LCD_DEADTIME_1: One Phase between different couple of Frame + * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame + * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame + * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame + * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame + * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame + * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame + * @retval None + */ +#define __LCD_DEADTIME_CONFIG(__DEADTIME__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DEAD,__DEADTIME__) + +/** @brief Config the pulse on duration + * @param __PULSEON__ specifies the LCD pulse on duration in terms of + * CK_PS (prescaled LCD clock period) pulses. + * This parameter can be one of the following values: + * @arg LCD_PULSEONDURATION_0: 0 pulse + * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS + * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS + * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS + * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS + * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS + * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS + * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS + * @retval None + */ +#define __LCD_PULSEONDURATION_CONFIG(__PULSEON__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PULSEON,__PULSEON__) + +/** @brief Enable the specified LCD interrupt. + * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt + * @retval None + */ +#define __LCD_ENABLE_IT(__INTERRUPT__) SET_BIT(LCD->FCTRL, __INTERRUPT__) + +/** @brief Disable the specified LCD interrupt. + * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt + * @retval None + */ +#define __LCD_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(LCD->FCTRL, __INTERRUPT__) + +/** @brief Check whether the specified LCD interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the LCD interrupt source to check. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt. + * @retval The state of __INTERRUPT__ + */ +#define __LCD_GET_IT_SOURCE(__INTERRUPT__) ((LCD->FCTRL) & (__INTERRUPT__)) + +/** @brief Set LCD UDR flag for update dispaly request + * @param None + * @retval None + */ +#define __LCD_UPDATE_REQUEST() SET_BIT(LCD->STS, LCD_FLAG_UDR) + +/** @brief Check whether the specified LCD flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. + * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR + * goes from 0 to 1. On deactivation it reflects the real status of + * LCD so it becomes 0 at the end of the last displayed frame. + * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at + * the beginning of a new frame, at the same time as the display data is + * updated. + * @arg LCD_FLAG_UDR: Update Display Request flag. + * @arg LCD_FLAG_UDD: Update Display Done flag. + * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status + * of the step-up converter. + * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. + * This flag is set by hardware each time the LCD_FCR register is updated + * in the LCDCLK domain. + * @retval The new state of __FLAG__ + */ +#define __LCD_GET_FLAG(__FLAG__) (((LCD->STS) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified LCD pending flag. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LCD_FLAG_SOF_CLEAR: Start of Frame Interrupt + * @arg LCD_FLAG_UDD_CLEAR: Update Display Done Interrupt + * @retval None + */ +#define __LCD_CLEAR_FLAG(__FLAG__) \ + do { \ + SET_BIT((LCD->CLR), (__FLAG__)); \ + CLEAR_BIT((LCD->CLR), (__FLAG__)); \ + }while(0) + +/** @brief Config LCD to keep display in STOP2 mode. + * @param None + * @retval None + */ +#define __LCD_DISPLAY_IN_STOP2() \ + do { \ + SET_BIT(*(__IO uint32_t *)(PWR_BASE+0x08), (0x1UL << 21)); \ + CLEAR_BIT(*(__IO uint32_t *)(PWR_BASE+0x1c), (0x1UL << 7)); \ + }while(0) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LCD_Private_Macros LCD Private Macros + * @{ + */ +#define IS_LCD_RAM_REGISTER_INDEX(__RAMRegIndex__) ((__RAMRegIndex__)<=LCD_RAM2_COM7) + +#define IS_LCD_PRESCALER(_PRESCALER_) \ + (((_PRESCALER_)==LCD_PRESCALER_1) ||((_PRESCALER_)==LCD_PRESCALER_2) \ + ||((_PRESCALER_)==LCD_PRESCALER_4) ||((_PRESCALER_)==LCD_PRESCALER_8) \ + ||((_PRESCALER_)==LCD_PRESCALER_16) ||((_PRESCALER_)==LCD_PRESCALER_32) \ + ||((_PRESCALER_)==LCD_PRESCALER_64) ||((_PRESCALER_)==LCD_PRESCALER_128) \ + ||((_PRESCALER_)==LCD_PRESCALER_256) ||((_PRESCALER_)==LCD_PRESCALER_512) \ + ||((_PRESCALER_)==LCD_PRESCALER_1024)||((_PRESCALER_)==LCD_PRESCALER_2048) \ + ||((_PRESCALER_)==LCD_PRESCALER_4096)||((_PRESCALER_)==LCD_PRESCALER_8192) \ + ||((_PRESCALER_)==LCD_PRESCALER_16384)||((_PRESCALER_)==LCD_PRESCALER_32768)) + +#define IS_LCD_DIVIDER(__DIVIDER__) \ + (((__DIVIDER__)==LCD_DIV_16)||((__DIVIDER__)==LCD_DIV_17)||((__DIVIDER__)==LCD_DIV_18) \ + ||((__DIVIDER__)==LCD_DIV_19)||((__DIVIDER__)==LCD_DIV_20)||((__DIVIDER__)==LCD_DIV_21) \ + ||((__DIVIDER__)==LCD_DIV_22)||((__DIVIDER__)==LCD_DIV_23)||((__DIVIDER__)==LCD_DIV_24) \ + ||((__DIVIDER__)==LCD_DIV_25)||((__DIVIDER__)==LCD_DIV_26)||((__DIVIDER__)==LCD_DIV_27) \ + ||((__DIVIDER__)==LCD_DIV_28)||((__DIVIDER__)==LCD_DIV_29)||((__DIVIDER__)==LCD_DIV_30) \ + ||((__DIVIDER__)==LCD_DIV_31)) + +#define IS_LCD_DUTY(__DUTY__) \ + (((__DUTY__)==LCD_DUTY_STATIC)||((__DUTY__)==LCD_DUTY_1_2) \ + ||((__DUTY__)==LCD_DUTY_1_3) ||((__DUTY__)==LCD_DUTY_1_4) \ + ||((__DUTY__)==LCD_DUTY_1_8) ) + +#define IS_LCD_BIAS(__BIAS__) \ + (((__BIAS__)==LCD_BIAS_1_2)||((__BIAS__)==LCD_BIAS_1_3)||((__BIAS__)==LCD_BIAS_1_4)) + +#define IS_LCD_VOLTAGESOURCE(__SOURCE__) \ + (((__SOURCE__)==LCD_VOLTAGESOURCE_INTERNAL)||((__SOURCE__)==LCD_VOLTAGESOURCE_EXTERNAL)) + +#define IS_LCD_CONTRASTLEVEL(__CONTRAST__) \ + (((__CONTRAST__)==LCD_CONTRASTLEVEL_0) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_1) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_2) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_3) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_4) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_5) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_6) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_7)) + +#define IS_LCD_DEADTIME(__DEADTIME__) \ + (((__DEADTIME__)==LCD_DEADTIME_0) ||((__DEADTIME__)==LCD_DEADTIME_1) \ + ||((__DEADTIME__)==LCD_DEADTIME_2) ||((__DEADTIME__)==LCD_DEADTIME_3) \ + ||((__DEADTIME__)==LCD_DEADTIME_4) ||((__DEADTIME__)==LCD_DEADTIME_5) \ + ||((__DEADTIME__)==LCD_DEADTIME_6) ||((__DEADTIME__)==LCD_DEADTIME_7)) + +#define IS_LCD_PULSEONDURATION(__PULSE__) \ + (((__PULSE__)==LCD_PULSEONDURATION_0) ||((__PULSE__)==LCD_PULSEONDURATION_1) \ + ||((__PULSE__)==LCD_PULSEONDURATION_2) ||((__PULSE__)==LCD_PULSEONDURATION_3) \ + ||((__PULSE__)==LCD_PULSEONDURATION_4) ||((__PULSE__)==LCD_PULSEONDURATION_5) \ + ||((__PULSE__)==LCD_PULSEONDURATION_6) ||((__PULSE__)==LCD_PULSEONDURATION_7)) + +#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) \ + ((((__HIGHDRIVE__))==LCD_HIGHDRIVE_DISABLE)||(((__HIGHDRIVE__))==LCD_HIGHDRIVE_ENABLE)) + +#define IS_LCD_HIGHDRIVEBUFFER(__HIGHDRIVEBUF__) \ + (((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_DISABLE)||((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_ENABLE)) + +#define IS_LCD_BLINKMODE(__BLINKMODE__) \ + (((__BLINKMODE__)==LCD_BLINKMODE_OFF) ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_COM0) \ + ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_ALLCOM) ||((__BLINKMODE__)==LCD_BLINKMODE_ALLSEG_ALLCOM)) + +#define IS_LCD_BLINKFREQ(__BLINKFREQ__) \ + (((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_8) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_16) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_32) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_64) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_128) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_256) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_512) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_1024)) + +#define IS_LCD_MUXSEGMENT(__MUXSEG__) \ + (((__MUXSEG__)==LCD_MUXSEGMENT_DISABLE)||((__MUXSEG__)==LCD_MUXSEGMENT_ENABLE)) + +#define IS_LCD_FLAG(__FLAG__) \ + (((__FLAG__)==LCD_FLAG_ENSTS)||((__FLAG__)==LCD_FLAG_SOF) \ + ||((__FLAG__)==LCD_FLAG_UDR)||((__FLAG__)==LCD_FLAG_UDD) \ + ||((__FLAG__)==LCD_FLAG_RDY)||((__FLAG__)==LCD_FLAG_FCRSF)) + +#define IS_LCD_CLR_FLAG(__CLEARFLAG__) (((__CLEARFLAG__)==LCD_FLAG_SOF_CLEAR)||((__CLEARFLAG__)==LCD_FLAG_UDD_CLEAR) + + +/** + * @brief LCD Init structure definition + */ + +typedef struct +{ + uint32_t Prescaler; /*!< Configures the LCD Prescaler. + This parameter can be one value of @ref LCD_Prescaler */ + uint32_t Divider; /*!< Configures the LCD Divider. + This parameter can be one value of @ref LCD_Divider */ + uint32_t Duty; /*!< Configures the LCD Duty. + This parameter can be one value of @ref LCD_Duty */ + uint32_t Bias; /*!< Configures the LCD Bias. + This parameter can be one value of @ref LCD_Bias */ + uint32_t VoltageSource; /*!< Selects the LCD Voltage source. + This parameter can be one value of @ref LCD_Voltage_source */ + uint32_t Contrast; /*!< Configures the LCD Contrast. + This parameter can be one value of @ref LCD_Contrast */ + uint32_t DeadTime; /*!< Configures the LCD Dead Time. + This parameter can be one value of @ref LCD_DeadTime */ + uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. + This parameter can be one value of @ref LCD_PulseOnDuration */ + uint32_t HighDrive; /*!< Enable or disable the permanent high driver. + This parameter can be one value of @ref LCD_HighDrive */ + uint32_t HighDriveBuffer; /*!< Enable or disable the high driver buffer. + This parameter can be one value of @ref LCD_HighDrive_Buffer */ + uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. + This parameter can be one value of @ref LCD_Blink_Mode */ + uint32_t BlinkFreq; /*!< Configures the LCD Blink frequency. + This parameter can be one value of @ref LCD_Blink_Frequency */ + uint32_t MuxSegment; /*!< Enable or disable mux segment. + This parameter can be one value of @ref LCD_MuxSegment */ +}LCD_InitType; + + +/** @addtogroup LCD_Exported_Functions + * @{ + */ +LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure ); +void LCD_DeInit(void); + +LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource); + +void LCD_RamClear(void); + +LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void); + +LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData); + + +LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData); + +LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData); + +LCD_ErrorTypeDef LCD_WaitForSynchro(void); + +/** + * @} + */ + + + +#ifdef __cplusplus + } +#endif + +#endif /* __N32L40X_LCD_H__ */ + /** + * @} + */ + + /** + * @} + */ + + /** + * @} + */ + + diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lptim.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lptim.h new file mode 100644 index 0000000000000000000000000000000000000000..6130253603b582ea38df0625fd469d79885fa0c6 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lptim.h @@ -0,0 +1,427 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------------- + */ +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32l40x_lptim.h + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ +#ifndef __N32L40X_LPTIM_H +#define __N32L40X_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPTIM + * @{ + */ + +//#if defined (LPTIM) + + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_EC_PRESCALER. + + This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ + + uint32_t Polarity; /*!< Specifies waveform polarity. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ +} LPTIM_InitType; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LPTIM_ReadReg function + * @{ + */ +#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */ +#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_IT IT Defines + * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions + * @{ + */ +#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +void LPTIM_DeInit(LPTIM_Module *LPTIMx); +void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct); +ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct); +void LPTIM_Disable(LPTIM_Module *LPTIMx); + + + +void LPTIM_Enable(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx); +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode); +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode); +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx); +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload); +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx); +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue); +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx); +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode); +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx); +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity); +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform); +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx); +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity); +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler); +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx); +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx); +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx); +void LPTIM_TrigSw(LPTIM_Module *LPTIMx); +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity); +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource); +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx); +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity); +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx); +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode); +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx); +/** + * @} + */ + +/** + * @} + */ + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_LPTIM_H */ + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h new file mode 100644 index 0000000000000000000000000000000000000000..847c2c9903fde842306fa57e5bb03b355e61a85f --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h @@ -0,0 +1,280 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_lpuart.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_LPUART_H__ +#define __N32L40X_LPUART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @{ + */ + +/** @addtogroup LPUART_Exported_Types + * @{ + */ + +/** + * @brief LPUART Init Structure definition + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate))) + - FractionalDivider */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (only support + 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t RtsThreshold; /* Specifies RTS Threshold. + This parameter can be a value of @ref RtsThreshold */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref LPUART_Hardware_Flow_Control */ +} LPUART_InitType; + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Constants + * @{ + */ + +/** @addtogroup Parity + * @{ + */ + +#define LPUART_PE_NO ((uint16_t)0x0008) +#define LPUART_PE_EVEN ((uint16_t)0x0000) +#define LPUART_PE_ODD ((uint16_t)0x0001) +#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define LPUART_MODE_RX ((uint16_t)0x0000) +#define LPUART_MODE_TX ((uint16_t)0x0002) +#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX)) +/** + * @} + */ + +/** @addtogroup RtsThreshold + * @{ + */ + +#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000) +#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100) +#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200) +#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \ + (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU)) +/** + * @} + */ + +/** @addtogroup Hardware_Flow_Control + * @{ + */ +#define LPUART_HFCTRL_NONE ((uint16_t)0x0000) +#define LPUART_HFCTRL_CTS ((uint16_t)0x0400) +#define LPUART_HFCTRL_RTS ((uint16_t)0x0800) +#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00) +#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \ + || ((CONTROL) == LPUART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup LPUART_Interrupt_definition + * @{ + */ + +#define LPUART_INT_PE ((uint16_t)0x0001) +#define LPUART_INT_TXC ((uint16_t)0x0102) +#define LPUART_INT_FIFO_OV ((uint16_t)0x0204) +#define LPUART_INT_FIFO_FU ((uint16_t)0x0308) +#define LPUART_INT_FIFO_HF ((uint16_t)0x0410) +#define LPUART_INT_FIFO_NE ((uint16_t)0x0520) +#define LPUART_INT_WUF ((uint16_t)0x0640) +#define IS_LPUART_CFG_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_GET_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_CLR_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +/** + * @} + */ + +/** @addtogroup LPUART_DMA_Requests + * @{ + */ + +#define LPUART_DMAREQ_TX ((uint16_t)0x0020) +#define LPUART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup LPUART_WakeUp_methods + * @{ + */ + +#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000) +#define LPUART_WUSTP_RXNE ((uint16_t)0x1000) +#define LPUART_WUSTP_BYTE ((uint16_t)0x2000) +#define LPUART_WUSTP_FRAME ((uint16_t)0x3000) +#define IS_LPUART_WAKEUP(WAKEUP) \ + (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME)) +/** + * @} + */ + +/** @addtogroup LPUART_Sampling_methods + * @{ + */ + +#define LPUART_SMPCNT_3B ((uint16_t)0x0000) +#define LPUART_SMPCNT_1B ((uint16_t)0x4000) +#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B)) +/** + * @} + */ + +/** @addtogroup LPUART_Flags + * @{ + */ + +#define LPUART_FLAG_PEF ((uint16_t)0x0001) +#define LPUART_FLAG_TXC ((uint16_t)0x0002) +#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004) +#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008) +#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010) +#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020) +#define LPUART_FLAG_CTS ((uint16_t)0x0040) +#define LPUART_FLAG_WUF ((uint16_t)0x0080) +#define LPUART_FLAG_NF ((uint16_t)0x0100) +#define IS_LPUART_FLAG(FLAG) \ + (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \ + || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \ + || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF)) + +#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000)) + +#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Functions + * @{ + */ + +void LPUART_DeInit(void); +void LPUART_Init(LPUART_InitType* LPUART_InitStruct); +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct); +void LPUART_FlushRxFifo(void); +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd); +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd); +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod); +void LPUART_EnableWakeUpStop(FunctionalState Cmd); +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod); +void LPUART_EnableLoopBack(FunctionalState Cmd); +void LPUART_SendData(uint8_t Data); +uint8_t LPUART_ReceiveData(void); +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData); +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG); +void LPUART_ClrFlag(uint16_t LPUART_FLAG); +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT); +void LPUART_ClrIntPendingBit(uint16_t LPART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_LPUART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_opamp.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_opamp.h new file mode 100644 index 0000000000000000000000000000000000000000..8af375f48a28d6230a6aeb3a4c4397a42331cec0 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_opamp.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_opamp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_OPAMPMP_H__ +#define __N32L40X_OPAMPMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" +#include + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @{ + */ + +/** @addtogroup OPAMP_Exported_Constants + * @{ + */ +typedef enum +{ + OPAMP1 = 0, + OPAMP2 = 4, +} OPAMPX; + +// OPAMP_CS +typedef enum +{ + OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24), + OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24), +}OPAMP2_CS_TIMSRCSEL; +typedef enum +{ + OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19), + OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19), + OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19), + OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19), + OPAMP1_CS_VPSSEL_NC = (0x04L << 19), + + OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19), + OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19), + OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19), + OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19), + OPAMP2_CS_VPSSEL_NC = (0x04L << 19), +} OPAMP_CS_VPSSEL; +typedef enum +{ + OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17), + OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17), + OPAMP1_CS_VMSSEL_NC = (0x02L << 17), + OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17), + + OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17), + OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17), + OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17), + OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17), +} OPAMP_CS_VMSSEL; + +typedef enum +{ + OPAMP1_CS_VPSEL_PA1 = (0x00L << 8), + OPAMP1_CS_VPSEL_PA5 = (0x01L << 8), + OPAMP1_CS_VPSEL_PA4 = (0x02L << 8), + OPAMP1_CS_VPSEL_PA7 = (0x03L << 8), + OPAMP1_CS_VPSEL_NC = (0x04L << 8), + + OPAMP2_CS_VPSEL_PA7 = (0x00L << 8), + OPAMP2_CS_VPSEL_PA4 = (0x01L << 8), + OPAMP2_CS_VPSEL_PB14 = (0x02L << 8), + OPAMP2_CS_VPSEL_PD13 = (0x03L << 8), + OPAMP2_CS_VPSEL_NC = (0x04L << 8), +} OPAMP_CS_VPSEL; +typedef enum +{ + OPAMP1_CS_VMSEL_PA3 = (0x00L << 6), + OPAMP1_CS_VMSEL_PC5 = (0x01L << 6), + OPAMPx_CS_VMSEL_NC = (0x02L << 6), + OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6), + + OPAMP2_CS_VMSEL_PC5 = (0x00L << 6), + OPAMP2_CS_VMSEL_PB0 = (0x01L << 6), + OPAMP2_CS_VMSEL_PA5 = (0x02L << 6), + OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6), +} OPAMP_CS_VMSEL; +typedef enum +{ + OPAMP_CS_PGA_GAIN_2 = (0x00 << 3), + OPAMP_CS_PGA_GAIN_4 = (0x01 << 3), + OPAMP_CS_PGA_GAIN_8 = (0x02 << 3), + OPAMP_CS_PGA_GAIN_16 = (0x03 << 3), + OPAMP_CS_PGA_GAIN_32 = (0x04 << 3), +} OPAMP_CS_PGA_GAIN; +typedef enum +{ + OPAMP_CS_EXT_OPAMP = (0x00 << 1), + OPAMP_CS_PGA_EN = (0x02 << 1), + OPAMP_CS_FOLLOW = (0x03 << 1), +} OPAMP_CS_MOD; + +// bit mask +#define OPAMP_CS_EN_MASK (0x01L << 0) +#define OPAMP_CS_MOD_MASK (0x03L << 1) +#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3) +#define OPAMP_CS_VMSEL_MASK (0x03L << 6) +#define OPAMP_CS_VPSEL_MASK (0x07L << 8) +#define OPAMP_CS_CALON_MASK (0x01L << 11) +#define OPAMP_CS_TSTREF_MASK (0x01L << 13) +#define OPAMP_CS_CALOUT_MASK (0x01L << 14) +#define OPAMP_CS_RANGE_MASK (0x01L << 15) +#define OPAMP_CS_TCMEN_MASK (0x01L << 16) +#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17) +#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19) +#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24) +/** @addtogroup OPAMP_LOCK + * @{ + */ +#define OPAMP_LOCK_1 0x01L +#define OPAMP_LOCK_2 0x02L +/** + * @} + */ +/** + * @} + */ + +/** + * @brief OPAMP Init structure definition + */ + +typedef struct +{ + OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/ + + FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */ + + FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/ + + OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */ + + OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/ +} OPAMP_InitType; + +/** @addtogroup OPAMP_Exported_Functions + * @{ + */ + +void OPAMP_DeInit(void); +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain); +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel); +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel); +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel); +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel); +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx); +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_ADC_H */ + /** + * @} + */ + /** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_pwr.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_pwr.h new file mode 100644 index 0000000000000000000000000000000000000000..774cd20f13cd9f55b220769b161fcf36cf01534a --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_pwr.h @@ -0,0 +1,224 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_pwr.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_PWR_H__ +#define __N32L40X_PWR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @addtogroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Constants + * @{ + */ + +/** @addtogroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000) +#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002) +#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004) +#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006) +#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008) +#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A) +#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C) +#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E) + + +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \ + || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \ + || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) ) + +/** + * @} + */ + +/** @addtogroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_REGULATOR_ON ((uint32_t)0x00000000) +#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER)) +/** + * @} + */ + +/** @defgroup SLEEP_mode_entry + * @{ + */ +#define SLEEP_ON_EXIT (1) +#define SLEEP_OFF_EXIT (0) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + + +/** + * @} + */ + + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + +/** @addtogroup PWR_Flag + * @{ + */ +//STS1 +#define PWR_WKUP0_FLAG ((uint32_t)0x00000001) +#define PWR_WKUP1_FLAG ((uint32_t)0x00000002) +#define PWR_WKUP2_FLAG ((uint32_t)0x00000004) +#define PWR_STBY_FLAG ((uint32_t)0x00000100) +//STS2 +#define PWR_LPRUN_FLAG ((uint32_t)0x00000001) +#define PWR_MR_FLAG ((uint32_t)0x00000002) +#define PWR_PVDO_FLAG ((uint32_t)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + +#define IS_PWR_CLEAR_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + + + +/** @addtogroup SRAM1oSRAM2 retention set + * @{ + */ +//#define SRAM1DIS_SRAM2DIS 0 +//#define SRAM1EN_SRAM2DIS 1 + +//#define SRAM1DIS_SRAM2EN 2 +//#define SRAM1EN_SRAM2EN 3 +/** @addtogroup MR VOLTAGE + * @{ + */ +#define MR_1V0 2 +#define MR_1V1 3 + + +/** + * @} + */ +typedef enum +{ + WAKEUP_PIN0 = 0x0001, + WAKEUP_PIN1 = 0x0002, + WAKEUP_PIN2 = 0x0004, +} WAKEUP_PINX; +/** @addtogroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ +#define LPRUN_SWITCH_ADDR (__IO unsigned*)(0x40007000) +#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20) +#define CLERR_BIT25 0xfdffffff //bit25 +#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while(0) //0:0.9V 1:1.1V +#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while(0) //0:always on 1:duty on +#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while(0) //0:normal mode 1:standby mode +#define _SetLprunSwitch(vale) do{(*LPRUN_SWITCH_ADDR) &= (~0x0600);(*LPRUN_SWITCH_ADDR) |= (uint32_t)(vale <<9);}while(0) +/** @addtogroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessEnable(FunctionalState Cmd); +void PWR_PvdEnable(FunctionalState Cmd); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd); +void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry); +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret); +void PWR_EnterLowPowerRunMode(void); +void PWR_ExitLowPowerRunMode(void); +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry); + +FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_WakeUpPinConfig(void); +void SetSysClock_MSI(void); +uint8_t GetMrVoltage(void); +void PWR_MRconfig(uint8_t voltage); +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_PWR_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rcc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rcc.h new file mode 100644 index 0000000000000000000000000000000000000000..c5a0336f1d6c40cbdb54cdb9c7077906c9d3508a --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rcc.h @@ -0,0 +1,913 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_rcc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_RCC_H__ +#define __N32L40X_RCC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup N32L40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */ + uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */ +} RCC_ClocksType; + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ + +/** @addtogroup HSE_configuration + * @{ + */ + +#define RCC_HSE_DISABLE ((uint32_t)0x00000000) +#define RCC_HSE_ENABLE ((uint32_t)0x00010000) +#define RCC_HSE_BYPASS ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS)) + +/** + * @} + */ + +/** @addtogroup HSI_configuration + * @{ + */ + +#define RCC_HSI_DISABLE ((uint32_t)0x00000000) +#define RCC_HSI_ENABLE ((uint32_t)0x00000001) +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE)) + +/** + * @} + */ + +/** @addtogroup MSI_configuration + * @{ + */ + +#define RCC_MSI_DISABLE ((uint32_t)0x00000000) +#define RCC_MSI_ENABLE ((uint32_t)0x00000004) +#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE)) + +#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000) +#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010) +#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020) +#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030) +#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040) +#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050) +#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060) +#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \ + ) + +/** + * @} + */ + +/** @addtogroup PLL_entry_clock_source + * @{ + */ +#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000) +#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001) + +#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000) +#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000) +#define IS_RCC_PLL_SRC(SOURCE) \ + (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \ + || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2)) + +#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000) +#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002) +#define IS_RCC_PLL_DIVCLK(DIVCLK) \ + (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE)) + +/** + * @} + */ + +/** @addtogroup PLL_multiplication_factor + * @{ + */ +#define RCC_PLL_MUL_2 ((uint32_t)0x00000000) +#define RCC_PLL_MUL_3 ((uint32_t)0x00040000) +#define RCC_PLL_MUL_4 ((uint32_t)0x00080000) +#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000) +#define RCC_PLL_MUL_6 ((uint32_t)0x00100000) +#define RCC_PLL_MUL_7 ((uint32_t)0x00140000) +#define RCC_PLL_MUL_8 ((uint32_t)0x00180000) +#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000) +#define RCC_PLL_MUL_10 ((uint32_t)0x00200000) +#define RCC_PLL_MUL_11 ((uint32_t)0x00240000) +#define RCC_PLL_MUL_12 ((uint32_t)0x00280000) +#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000) +#define RCC_PLL_MUL_14 ((uint32_t)0x00300000) +#define RCC_PLL_MUL_15 ((uint32_t)0x00340000) +#define RCC_PLL_MUL_16 ((uint32_t)0x00380000) +#define RCC_PLL_MUL_17 ((uint32_t)0x08000000) +#define RCC_PLL_MUL_18 ((uint32_t)0x08040000) +#define RCC_PLL_MUL_19 ((uint32_t)0x08080000) +#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000) +#define RCC_PLL_MUL_21 ((uint32_t)0x08100000) +#define RCC_PLL_MUL_22 ((uint32_t)0x08140000) +#define RCC_PLL_MUL_23 ((uint32_t)0x08180000) +#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000) +#define RCC_PLL_MUL_25 ((uint32_t)0x08200000) +#define RCC_PLL_MUL_26 ((uint32_t)0x08240000) +#define RCC_PLL_MUL_27 ((uint32_t)0x08280000) +#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000) +#define RCC_PLL_MUL_29 ((uint32_t)0x08300000) +#define RCC_PLL_MUL_30 ((uint32_t)0x08340000) +#define RCC_PLL_MUL_31 ((uint32_t)0x08380000) +#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000) +#define IS_RCC_PLL_MUL(MUL) \ + (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \ + || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \ + || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \ + || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \ + || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \ + || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \ + || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \ + || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \ + || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \ + || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32)) + +/** + * @} + */ + +/** @addtogroup System_clock_source + * @{ + */ + +#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000) +#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001) +#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002) +#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003) +#define IS_RCC_SYSCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \ + || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK)) +/** + * @} + */ + +/** @addtogroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0) +#define IS_RCC_SYSCLK_DIV(HCLK) \ + (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \ + || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \ + || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @addtogroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_HCLK_DIV2 ((uint32_t)0x00000400) +#define RCC_HCLK_DIV4 ((uint32_t)0x00000500) +#define RCC_HCLK_DIV8 ((uint32_t)0x00000600) +#define RCC_HCLK_DIV16 ((uint32_t)0x00000700) +#define IS_RCC_HCLK_DIV(PCLK) \ + (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \ + || ((PCLK) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @addtogroup RCC_Interrupt_source + * @{ + */ + +#define RCC_INT_LSIRDIF ((uint8_t)0x01) +#define RCC_INT_LSERDIF ((uint8_t)0x02) +#define RCC_INT_HSIRDIF ((uint8_t)0x04) +#define RCC_INT_HSERDIF ((uint8_t)0x08) +#define RCC_INT_PLLRDIF ((uint8_t)0x10) +#define RCC_INT_BORIF ((uint8_t)0x20) +#define RCC_INT_MSIRDIF ((uint8_t)0x40) +#define RCC_INT_CLKSSIF ((uint8_t)0x80) + +#define IS_RCC_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF)) + +#define IS_RCC_GET_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF)) + +#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000) +#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000) +#define RCC_CLR_LSERDIF ((uint32_t)0x00020000) +#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000) +#define RCC_CLR_HSERDIF ((uint32_t)0x00080000) +#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000) +#define RCC_CLR_BORIF ((uint32_t)0x00200000) +#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000) + +#define IS_RCC_CLR_INTF(IT) \ + (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \ + || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF)) + +/** + * @} + */ + +/** @addtogroup USB_Device_clock_source + * @{ + */ + +#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00) +#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01) +#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02) +#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03) + +#define IS_RCC_USBCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \ + || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3)) +/** + * @} + */ + +/** @addtogroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000) +#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000) +#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000) +#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000) +#define IS_RCC_PCLK2_DIV(ADCCLK) \ + (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \ + || ((ADCCLK) == RCC_PCLK2_DIV8)) + +/** + * @} + */ + +/** @addtogroup RCC_CFGR2_Config + * @{ + */ +#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000) +#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000) +#define IS_RCC_TIM18CLKSRC(TIM18CLK) \ + (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK)) + +#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000) +#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000) +#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000) +#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000) +#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000) +#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000) +#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000) +#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000) +#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000) +#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000) +#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000) +#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000) +#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000) +#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000) +#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000) +#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000) +#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000) +#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000) +#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000) +#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000) +#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000) +#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000) +#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000) +#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000) +#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000) +#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000) +#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000) +#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000) +#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000) +#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000) +#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000) +#define IS_RCC_RNGCCLKPRE(DIV) \ + (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32)) + +#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE)) + +#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000) +#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000) +#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000) +#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000) +#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000) +#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000) +#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000) +#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000) +#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000) +#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000) +#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000) +#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000) +#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000) +#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000) +#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000) +#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000) +#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000) +#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000) +#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000) +#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000) +#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000) +#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000) +#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000) +#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000) +#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000) +#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000) +#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000) +#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000) +#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000) +#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000) +#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000) +#define IS_RCC_ADC1MCLKPRE(DIV) \ + (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \ + || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \ + || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \ + || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \ + || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \ + || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \ + || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \ + || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \ + || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \ + || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \ + || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32)) + +#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) +#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) +#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) +#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) +#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) +#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) +#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) +#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) +#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) +#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) +#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) +#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) +#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) +#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) +#define IS_RCC_ADCPLLCLKPRE(DIV) \ + (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \ + || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \ + || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \ + || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \ + || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0)) + +#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) +#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) +#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) +#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) +#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) +#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) +#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) +#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) +#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) +#define IS_RCC_ADCHCLKPRE(DIV) \ + (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \ + || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \ + || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \ + || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00)) +/** + * @} + */ + +/** @addtogroup RCC_CFGR3_Config + * @{ + */ + +#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000) +#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF) + +#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \ + (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE)) + +#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000) +#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800) +#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000) +#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800) +#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000) +#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800) +#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000) +#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800) +#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000) +#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800) +#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000) +#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800) +#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000) +#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800) +#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000) +#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800) +#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000) +#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800) +#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000) +#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800) +#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000) +#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800) +#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000) +#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800) +#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000) +#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800) +#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000) +#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800) +#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000) +#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800) +#define IS_RCC_TRNG1MCLKPRE(VAL) \ + (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \ + || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \ + || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \ + || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \ + || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \ + || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \ + || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \ + || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \ + || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \ + || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \ + || ((VAL) == RCC_TRNG1MCLK_DIV62)) + +#define RCC_UCDR_ENABLE ((uint32_t)0x00000080) +#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F) + +#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF) +#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000) +#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200) +#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \ + (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO)) + +#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF) +#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000) +#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100) +#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \ + (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE)) + +/** + * @} + */ + +/** @addtogroup LSE_configuration + * @{ + */ + +#define RCC_LSE_DISABLE ((uint32_t)0x00000000) +#define RCC_LSE_ENABLE ((uint32_t)0x00000001) +#define RCC_LSE_BYPASS ((uint32_t)0x00000004) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @addtogroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000) +#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \ + || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32)) +/** + * @} + */ + +/** @addtogroup LSX_clock_source + * @{ + */ + +#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000) +#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020) +#define IS_RCC_LSXCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE)) +/** + * @} + */ + +/** @addtogroup AHB_peripheral + * @{ + */ + +#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001) +#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004) +#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010) +#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040) +#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200) +#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800) +#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup APB2_peripheral + * @{ + */ + +#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001) +#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000) +#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000) +#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000) +#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup APB1_peripheral + * @{ + */ + +#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040) +#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080) +#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100) +#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200) +#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400) +#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800) +#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000) +#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000) +#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000) +#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000) +#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000) +#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000) +#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup RET_peripheral + * @{ + */ + +#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040) +#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080) +#define RCC_RET_PERIPH_LCD ((uint32_t)0x00000100) + + +#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFC3F) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup LPTIM + * @{ + */ +#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8) + +#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001) +#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002) +#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003) +#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004) +#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005) + +#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2)) + +/** + * @} + */ + +/** @addtogroup LPUART + * @{ + */ +#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7) + +#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008) +#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010) +#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018) + +#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00) + +/** + * @} + */ + +/** @addtogroup SRAM_CTRLSTS + * @{ + */ + +#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001) +#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008) +#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \ + || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT)) + +#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002) +#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010) +#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \ + || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET)) + +#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004) +#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020) +#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \ + || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG)) + +/** + * @} + */ + +#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000) +#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000) +#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000) +#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000) +#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000) +#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000) +#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000) +#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000) +#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000) +#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000) +#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000) +#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000) +#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000) +#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000) +#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000) +#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000) +#define IS_RCC_MCOCLKPRE(NUM) \ + (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \ + || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \ + || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \ + || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \ + || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \ + || ((NUM) == RCC_MCO_CLK_NUM15)) + +/** @addtogroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NOCLK ((uint8_t)0x00) +#define RCC_MCO_LSI ((uint8_t)0x01) +#define RCC_MCO_LSE ((uint8_t)0x02) +#define RCC_MCO_MSI ((uint8_t)0x03) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +#define IS_RCC_MCO(MCO) \ + (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \ + || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK)) + +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21) +#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31) +#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39) +#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41) +#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44) +#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C) +#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E) +#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61) +#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63) +#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77) +#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79) +#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A) +#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B) +#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C) +#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D) +#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E) +#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) \ + (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF)) + +#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_ConfigHse(uint32_t RCC_HSE); +ErrorStatus RCC_WaitHseStable(void); +void RCC_ConfigHsi(uint32_t RCC_HSI); +ErrorStatus RCC_WaitHsiStable(void); +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue); +void RCC_EnableHsi(FunctionalState Cmd); +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range); +ErrorStatus RCC_WaitMsiStable(void); +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue); +void RCC_EnableMsi(FunctionalState Cmd); +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK); +void RCC_EnablePll(FunctionalState Cmd); + +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSysclkSrc(void); +void RCC_ConfigHclk(uint32_t RCC_SYSCLK); +void RCC_ConfigPclk1(uint32_t RCC_HCLK); +void RCC_ConfigPclk2(uint32_t RCC_HCLK); +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd); + +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource); + +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource); +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler); + +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler); +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd); +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler); + +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler); +void RCC_EnableTrng1mClk(FunctionalState Cmd); + +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd); + +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode); + +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd); +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd); + +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource); +uint32_t RCC_GetLSXClkSrc(void); + +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource); +uint32_t RCC_GetLPTIMClkSrc(void); +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource); +uint32_t RCC_GetLPUARTClkSrc(void); + +void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd); +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd); +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag); + +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim); +void RCC_EnableLsi(FunctionalState Cmd); +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource); +void RCC_EnableRtcClk(FunctionalState Cmd); +uint32_t RCC_GetRTCClkSrc(void); +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks); +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd); + +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd); +void RCC_EnableLowPowerReset(FunctionalState Cmd); +void RCC_EnableClockSecuritySystem(FunctionalState Cmd); +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd); +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void); +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler); +void RCC_ConfigMco(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClrFlag(void); +INTStatus RCC_GetIntStatus(uint8_t RccInt); +void RCC_ClrIntPendingBit(uint32_t RccClrInt); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_RCC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rtc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..ebc4cff74357cae3424420e0c47ac4d86290a877 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_rtc.h @@ -0,0 +1,789 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_rtc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_RTC_H__ +#define __N32L40X_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x7FFF */ +} RTC_InitType; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_12HOUR_FORMAT is selected or 0-23 range if + the RTC_24HOUR_FORMAT is selected. */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +} RTC_TimeType; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +} RTC_DateType; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +} RTC_AlarmType; + +/** @addtogroup RTC_Exported_Constants + * @{ + */ + +/** @addtogroup RTC_Hour_Formats + * @{ + */ +#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000) +#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT)) +/** + * @} + */ + +/** @addtogroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + +/** @addtogroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @addtogroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_AM_H12 ((uint8_t)0x00) +#define RTC_PM_H12 ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12)) + +/** + * @} + */ + +/** @addtogroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @addtogroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRURY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @addtogroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000) +#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \ + (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000) +#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000) +#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000) +#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_A_ALARM ((uint32_t)0x00000100) +#define RTC_B_ALARM ((uint32_t)0x00000200) +#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM)) +#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions + * @{ + */ +#define RTC_SUBS_MASK_ALL \ + ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \ + There is no comparison on sub seconds \ + for Alarm */ +#define RTC_SUBS_MASK_SS14_1 \ + ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \ + comparison. Only SS[0] is compared. */ +#define RTC_SUBS_MASK_SS14_2 \ + ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \ + comparison. Only SS[1:0] are compared */ +#define RTC_SUBS_MASK_SS14_3 \ + ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \ + comparison. Only SS[2:0] are compared */ +#define RTC_SUBS_MASK_SS14_4 \ + ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \ + comparison. Only SS[3:0] are compared */ +#define RTC_SUBS_MASK_SS14_5 \ + ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \ + comparison. Only SS[4:0] are compared */ +#define RTC_SUBS_MASK_SS14_6 \ + ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \ + comparison. Only SS[5:0] are compared */ +#define RTC_SUBS_MASK_SS14_7 \ + ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \ + comparison. Only SS[6:0] are compared */ +#define RTC_SUBS_MASK_SS14_8 \ + ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \ + comparison. Only SS[7:0] are compared */ +#define RTC_SUBS_MASK_SS14_9 \ + ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \ + comparison. Only SS[8:0] are compared */ +#define RTC_SUBS_MASK_SS14_10 \ + ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \ + comparison. Only SS[9:0] are compared */ +#define RTC_SUBS_MASK_SS14_11 \ + ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \ + comparison. Only SS[10:0] are compared */ +#define RTC_SUBS_MASK_SS14_12 \ + ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \ + comparison.Only SS[11:0] are compared */ +#define RTC_SUBS_MASK_SS14_13 \ + ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \ + comparison. Only SS[12:0] are compared */ +#define RTC_SUBS_MASK_SS14_14 \ + ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \ + comparison.Only SS[13:0] are compared */ +#define RTC_SUBS_MASK_NONE \ + ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \ + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \ + (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \ + || ((INTEN) == RTC_SUBS_MASK_NONE)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004) +#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define IS_RTC_WKUP_CLOCK(CLOCK) \ + (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \ + || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \ + || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS)) +#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @addtogroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \ + (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING)) +/** + * @} + */ + +/** @addtogroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_OUTPUT_DIS ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALA ((uint32_t)0x00200000) +#define RTC_OUTPUT_ALB ((uint32_t)0x00400000) +#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT_MODE(OUTPUT) \ + (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \ + || ((OUTPUT) == RTC_OUTPUT_WKUP)) + +/** + * @} + */ + +/** @addtogroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPOL_LOW ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW)) +/** + * @} + */ + + +/** @addtogroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000) +#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ)) +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define SMOOTH_CALIB_32SEC \ + ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 32s, else 2exp20 RTCCLK seconds */ +#define SMOOTH_CALIB_16SEC \ + ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 16s, else 2exp19 RTCCLK seconds */ +#define SMOOTH_CALIB_8SEC \ + ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \ + (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \ + ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \ + during a X -second window = Y - CALM[8:0]. \ + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \ + ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \ + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \ + (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @addtogroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H)) + +#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) \ + (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET)) +/** + * @} + */ + +/** @addtogroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL)) + +/** + * @} + */ + +/** @addtogroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000) +#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE)) +/** + * @} + */ + +/** @addtogroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + +/** + * @} + */ + +/** @addtogroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TISOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TISF ((uint32_t)0x00000800) +#define RTC_FLAG_WTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSYF ((uint32_t)0x00000020) +#define RTC_FLAG_INITSF ((uint32_t)0x00000010) +#define RTC_FLAG_SHOPF ((uint32_t)0x00000008) +#define RTC_FLAG_WTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \ + ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \ + ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \ + ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \ + ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \ + ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \ + ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_INT_TAMP3 ((uint32_t)0x00080000) +#define RTC_INT_TAMP2 ((uint32_t)0x00040000) +#define RTC_INT_TAMP1 ((uint32_t)0x00020000) +#define RTC_INT_TS ((uint32_t)0x00008000) +#define RTC_INT_WUT ((uint32_t)0x00004000) +#define RTC_INT_ALRB ((uint32_t)0x00002000) +#define RTC_INT_ALRA ((uint32_t)0x00001000) + +#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_INT(IT) \ + (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA)) +#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ + +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for + input tamper 1 */ +#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for + input tamper 2 */ +#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for + input tamper 3 */ +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + + +#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_EnableWriteProtection(FunctionalState Cmd); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd); +void RTC_EnableBypassShadow(FunctionalState Cmd); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd); +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd); + +/* Daylight Saving configuration functions ************************************/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse and Smooth Calibration configuration functions **********************/ +void RTC_EnableCalibOutput(FunctionalState Cmd); +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput); +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Output Type Config configuration functions *********************************/ +void RTC_ConfigOutputType(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClrFlag(uint32_t RTC_FLAG); +INTStatus RTC_GetITStatus(uint32_t RTC_INT); +void RTC_ClrIntPendingBit(uint32_t RTC_INT); + +/* WakeUp TSC function **********************************/ +void RTC_EnableWakeUpTsc(uint32_t count); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState); +void RTC_TamperTAMPTSCmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_RTC_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_spi.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..845bcb8bcf7a85232690c39155c7b91c445ce1f9 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_spi.h @@ -0,0 +1,470 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_spi.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_SPI_H__ +#define __N32L40X_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @addtogroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SpiMode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t DataLen; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t CLKPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitType; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2sMode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2sMode */ + + uint16_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref Standard */ + + uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitType; + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2)) + + +/** @addtogroup SPI_data_direction + * @{ + */ + +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400) +#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000) +#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000) +#define IS_SPI_DIR_MODE(MODE) \ + (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ + || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX)) +/** + * @} + */ + +/** @addtogroup SPI_mode + * @{ + */ + +#define SPI_MODE_MASTER ((uint16_t)0x0104) +#define SPI_MODE_SLAVE ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) +/** + * @} + */ + +/** @addtogroup SPI_data_size + * @{ + */ + +#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CLKPOL_LOW ((uint16_t)0x0000) +#define SPI_CLKPOL_HIGH ((uint16_t)0x0002) +#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) +#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001) +#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) +/** + * @} + */ + +/** @addtogroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_SOFT ((uint16_t)0x0200) +#define SPI_NSS_HARD ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) +/** + * @} + */ + +/** @addtogroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) +#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008) +#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010) +#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018) +#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020) +#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028) +#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030) +#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038) +#define IS_SPI_BR_PRESCALER(PRESCALER) \ + (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \ + || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \ + || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \ + || ((PRESCALER) == SPI_BR_PRESCALER_256)) +/** + * @} + */ + +/** @addtogroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FB_MSB ((uint16_t)0x0000) +#define SPI_FB_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) +/** + * @} + */ + +/** @addtogroup I2sMode + * @{ + */ + +#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000) +#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100) +#define I2S_MODE_MASTER_TX ((uint16_t)0x0200) +#define I2S_MODE_MASTER_RX ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) \ + (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \ + || ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @addtogroup Standard + * @{ + */ + +#define I2S_STD_PHILLIPS ((uint16_t)0x0000) +#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010) +#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020) +#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030) +#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) \ + (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \ + || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME)) +/** + * @} + */ + +/** @addtogroup I2S_Data_Format + * @{ + */ + +#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000) +#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001) +#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003) +#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005) +#define IS_I2S_DATA_FMT(FORMAT) \ + (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \ + || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS)) +/** + * @} + */ + +/** @addtogroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLK_ENABLE ((uint16_t)0x0200) +#define I2S_MCLK_DISABLE ((uint16_t)0x0000) +#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE)) +/** + * @} + */ + +/** @addtogroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AUDIO_FREQ_192K ((uint32_t)192000) +#define I2S_AUDIO_FREQ_96K ((uint32_t)96000) +#define I2S_AUDIO_FREQ_48K ((uint32_t)48000) +#define I2S_AUDIO_FREQ_44K ((uint32_t)44100) +#define I2S_AUDIO_FREQ_32K ((uint32_t)32000) +#define I2S_AUDIO_FREQ_22K ((uint32_t)22050) +#define I2S_AUDIO_FREQ_16K ((uint32_t)16000) +#define I2S_AUDIO_FREQ_11K ((uint32_t)11025) +#define I2S_AUDIO_FREQ_8K ((uint32_t)8000) +#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) \ + ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT)) +/** + * @} + */ + +/** @addtogroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CLKPOL_LOW ((uint16_t)0x0000) +#define I2S_CLKPOL_HIGH ((uint16_t)0x0008) +#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMA_TX ((uint16_t)0x0002) +#define SPI_I2S_DMA_RX ((uint16_t)0x0001) +#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @addtogroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSS_HIGH ((uint16_t)0x0100) +#define SPI_NSS_LOW ((uint16_t)0xFEFF) +#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_TX ((uint8_t)0x00) +#define SPI_CRC_RX ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) +/** + * @} + */ + +/** @addtogroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF) +#define SPI_BIDIRECTION_TX ((uint16_t)0x4000) +#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_INT_TE ((uint8_t)0x71) +#define SPI_I2S_INT_RNE ((uint8_t)0x60) +#define SPI_I2S_INT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR)) +#define SPI_I2S_INT_OVER ((uint8_t)0x56) +#define SPI_INT_MODERR ((uint8_t)0x55) +#define SPI_INT_CRCERR ((uint8_t)0x54) +#define I2S_INT_UNDER ((uint8_t)0x53) +#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR)) +#define IS_SPI_I2S_GET_INT(IT) \ + (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \ + || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001) +#define SPI_I2S_TE_FLAG ((uint16_t)0x0002) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0004) +#define I2S_UNDER_FLAG ((uint16_t)0x0008) +#define SPI_CRCERR_FLAG ((uint16_t)0x0010) +#define SPI_MODERR_FLAG ((uint16_t)0x0020) +#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040) +#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080) +#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) +#define IS_SPI_I2S_GET_FLAG(FLAG) \ + (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \ + || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \ + || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_Module* SPIx); +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct); +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct); +void SPI_InitStruct(SPI_InitType* SPI_InitStruct); +void I2S_InitStruct(I2S_InitType* I2S_InitStruct); +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx); +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); +void SPI_TransmitCrcNext(SPI_Module* SPIx); +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx); +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_SPI_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tim.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tim.h new file mode 100644 index 0000000000000000000000000000000000000000..d0db578e3f8490dabf434182e257022a54045eaa --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tim.h @@ -0,0 +1,1101 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_tim.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_TIM_H__ +#define __N32L40X_TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" +#include "stdbool.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @addtogroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t CntMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t ClkDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter + reaches zero, an update event is generated and counting restarts + from the REPCNT value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0 + Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0 + Tim2,Tim4 valid*/ +} TIM_TimeBaseInitType; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t OcMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t OcPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t OcNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} OCInitType; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + uint16_t Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref Channel */ + + uint16_t IcPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t IcSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t IcFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitType; + +/** + * @brief BKDT structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t OssiState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/ + bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/ + bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/ +} TIM_BDTRInitType; + +/** @addtogroup TIM_Exported_constants + * @{ + */ + +#define IsTimAllModule(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST1: TIM 1 and 8 */ +#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8 */ +#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IsTimList3Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList4Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList5Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList6Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList7Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList8Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList9Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMODE_TIMING ((uint16_t)0x0000) +#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010) +#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020) +#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030) +#define TIM_OCMODE_PWM1 ((uint16_t)0x0060) +#define TIM_OCMODE_PWM2 ((uint16_t)0x0070) +#define IsTimOcMode(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2)) +#define IsTimOc(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \ + || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMODE_SINGLE ((uint16_t)0x0008) +#define TIM_OPMODE_REPET ((uint16_t)0x0000) +#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET)) +/** + * @} + */ + +/** @addtogroup Channel + * @{ + */ + +#define TIM_CH_1 ((uint16_t)0x0000) +#define TIM_CH_2 ((uint16_t)0x0004) +#define TIM_CH_3 ((uint16_t)0x0008) +#define TIM_CH_4 ((uint16_t)0x000C) +#define IsTimCh(CHANNEL) \ + (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4)) +#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2)) +#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3)) +/** + * @} + */ + +/** @addtogroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CLK_DIV1 ((uint16_t)0x0000) +#define TIM_CLK_DIV2 ((uint16_t)0x0100) +#define TIM_CLK_DIV4 ((uint16_t)0x0200) +#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4)) +/** + * @} + */ + +/** @addtogroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CNT_MODE_UP ((uint16_t)0x0000) +#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010) +#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020) +#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040) +#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060) +#define IsTimCntMode(MODE) \ + (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \ + || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002) +#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008) +#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001) +#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004) +#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001) +#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004) +#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Input_enable_disable + * @{ + */ + +#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000) +#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000) +#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Polarity + * @{ + */ + +#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000) +#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000) +#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH)) +/** + * @} + */ + +/** @addtogroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000) +#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000) +#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE)) +/** + * @} + */ + +/** @addtogroup Lock_level + * @{ + */ + +#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000) +#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100) +#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200) +#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300) +#define IsTimLockLevel(LEVEL) \ + (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \ + || ((LEVEL) == TIM_LOCK_LEVEL_3)) +/** + * @} + */ + +/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400) +#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800) +#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100) +#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200) +#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000) +#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002) +#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A) +#define IsTimIcPalaritySingleEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING)) +#define IsTimIcPolarityAnyEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \ + || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_IC_SELECTION_DIRECTTI \ + ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI \ + ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IsTimIcSelection(SELECTION) \ + (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \ + || ((SELECTION) == TIM_IC_SELECTION_TRC)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \ + */ +#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IsTimIcPrescaler(PRESCALER) \ + (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \ + || ((PRESCALER) == TIM_IC_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_interrupt_sources + * @{ + */ + +#define TIM_INT_UPDATE ((uint16_t)0x0001) +#define TIM_INT_CC1 ((uint16_t)0x0002) +#define TIM_INT_CC2 ((uint16_t)0x0004) +#define TIM_INT_CC3 ((uint16_t)0x0008) +#define TIM_INT_CC4 ((uint16_t)0x0010) +#define TIM_INT_COM ((uint16_t)0x0020) +#define TIM_INT_TRIG ((uint16_t)0x0040) +#define TIM_INT_BREAK ((uint16_t)0x0080) +#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IsTimGetInt(IT) \ + (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \ + || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000) +#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001) +#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002) +#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003) +#define TIM_DMABASE_STS ((uint16_t)0x0004) +#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005) +#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006) +#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007) +#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008) +#define TIM_DMABASE_CNT ((uint16_t)0x0009) +#define TIM_DMABASE_PSC ((uint16_t)0x000A) +#define TIM_DMABASE_AR ((uint16_t)0x000B) +#define TIM_DMABASE_REPCNT ((uint16_t)0x000C) +#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D) +#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E) +#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F) +#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010) +#define TIM_DMABASE_BKDT ((uint16_t)0x0011) +#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012) + + +#define IsTimDmaBase(BASE) \ + (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \ + || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \ + || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \ + || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \ + || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \ + || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \ + || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000) +#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100) +#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200) +#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300) +#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400) +#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500) +#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600) +#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700) +#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800) +#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900) +#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00) +#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00) +#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00) +#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00) +#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00) +#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00) +#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000) +#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100) +#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200) +#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300) +#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400) +#define IsTimDmaLength(LENGTH) \ + (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_UPDATE ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_TRIG ((uint16_t)0x4000) +#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000) +#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000) +#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000) +#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000) +#define IsTimExtPreDiv(PRESCALER) \ + (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \ + || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000) +#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010) +#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020) +#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030) +#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040) +#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050) +#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060) +#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070) +#define IsTimTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \ + || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \ + || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF)) +#define IsTimInterTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3)) +/** + * @} + */ + +/** @addtogroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050) +#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060) +#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040) +#define IsTimExtClkSrc(SOURCE) \ + (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED)) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000) +#define IsTimExtTrigPolarity(POLARITY) \ + (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED)) +/** + * @} + */ + +/** @addtogroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001) +#define IsTimPscReloadMode(RELOAD) \ + (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE)) +/** + * @} + */ + +/** @addtogroup TIM_Forced_Action + * @{ + */ + +#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050) +#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040) +#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001) +#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002) +#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003) +#define IsTimEncodeMode(MODE) \ + (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12)) +/** + * @} + */ + +/** @addtogroup TIM_Event_Source + * @{ + */ + +#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001) +#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002) +#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004) +#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008) +#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010) +#define TIM_EVT_SRC_COM ((uint16_t)0x0020) +#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040) +#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080) +#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_Update_Source + * @{ + */ + +#define TIM_UPDATE_SRC_GLOBAL \ + ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008) +#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000) +#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004) +#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000) +#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080) +#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000) +#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000) +#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010) +#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020) +#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030) +#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040) +#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050) +#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060) +#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070) +#define IsTimTrgoSrc(SOURCE) \ + (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \ + || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \ + || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF)) +/** + * @} + */ + +/** @addtogroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004) +#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005) +#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006) +#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007) +#define IsTimSlaveMode(MODE) \ + (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \ + || ((MODE) == TIM_SLAVE_MODE_EXT1)) +/** + * @} + */ + +/** @addtogroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080) +#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000) +#define IsTimMasterSlaveMode(STATE) \ + (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_UPDATE ((uint32_t)0x0001) +#define TIM_FLAG_CC1 ((uint32_t)0x0002) +#define TIM_FLAG_CC2 ((uint32_t)0x0004) +#define TIM_FLAG_CC3 ((uint32_t)0x0008) +#define TIM_FLAG_CC4 ((uint32_t)0x0010) +#define TIM_FLAG_COM ((uint32_t)0x0020) +#define TIM_FLAG_TRIG ((uint32_t)0x0040) +#define TIM_FLAG_BREAK ((uint32_t)0x0080) +#define TIM_FLAG_CC1OF ((uint32_t)0x0200) +#define TIM_FLAG_CC2OF ((uint32_t)0x0400) +#define TIM_FLAG_CC3OF ((uint32_t)0x0800) +#define TIM_FLAG_CC4OF ((uint32_t)0x1000) +#define TIM_FLAG_CC5 ((uint32_t)0x010000) +#define TIM_FLAG_CC6 ((uint32_t)0x020000) + +#define IsTimGetFlag(FLAG) \ + (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \ + || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \ + || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \ + || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \ + || ((FLAG) == TIM_FLAG_CC6)) + +#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Filter + * @{ + */ + +#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +#define TIM_CC1EN ((uint32_t)1<<0) +#define TIM_CC1NEN ((uint32_t)1<<2) +#define TIM_CC2EN ((uint32_t)1<<4) +#define TIM_CC2NEN ((uint32_t)1<<6) +#define TIM_CC3EN ((uint32_t)1<<8) +#define TIM_CC3NEN ((uint32_t)1<<10) +#define TIM_CC4EN ((uint32_t)1<<12) +#define TIM_CC5EN ((uint32_t)1<<16) +#define TIM_CC6EN ((uint32_t)1<<20) + +#define IsAdvancedTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \ + || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \ + || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) ) +#define IsGeneralTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \ + || ((FLAG) == TIM_CC3EN) \ + || ((FLAG) == TIM_CC4EN) ) + +/** @addtogroup TIM_Legacy + * @{ + */ + +#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER +#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS +#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS +#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS +#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS +#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS +#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS +#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS +#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS +#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS +#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS +#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS +#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS +#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS +#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS +#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS +#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS +#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_Module* TIMx); +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct); +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct); +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd); +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource); +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd); +void TIM_ConfigInternalClk(TIM_Module* TIMx); +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, + uint16_t TIM_TIxExternalCLKSource, + uint16_t IcPolarity, + uint16_t ICFilter); +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode); +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity); +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx); +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN); +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode); +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter); +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload); +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1); +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2); +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3); +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4); +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5); +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6); +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCap1(TIM_Module* TIMx); +uint16_t TIM_GetCap2(TIM_Module* TIMx); +uint16_t TIM_GetCap3(TIM_Module* TIMx); +uint16_t TIM_GetCap4(TIM_Module* TIMx); +uint16_t TIM_GetCap5(TIM_Module* TIMx); +uint16_t TIM_GetCap6(TIM_Module* TIMx); +uint16_t TIM_GetCnt(TIM_Module* TIMx); +uint16_t TIM_GetPrescaler(TIM_Module* TIMx); +uint16_t TIM_GetAutoReload(TIM_Module* TIMx); +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN); +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG); +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L40X_TIM_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tsc.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tsc.h new file mode 100644 index 0000000000000000000000000000000000000000..30c72b8207fdf2eb717e6c5a1912a568d60fec80 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_tsc.h @@ -0,0 +1,483 @@ +/***************************************************************************** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* **************************************************************************** +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* Nations' name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ + +/** + * @file n32l40x_tsc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_TSC_H__ +#define __N32L40X_TSC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/** + * @brief TSC error code + */ + typedef enum { + TSC_ERROR_OK = 0x00U, /*!< No error */ + TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ + TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ + TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */ + + }TSC_ErrorTypeDef; + /** + * @ + */ + +/** + * @brief TSC clock source + */ +#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/ +#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */ +#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */ +/** + * @ + */ + + +/** + * @defgroup Detect_Period + */ +#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ +#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ +#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ +#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ +#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ +#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ +#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ +#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ +#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ +#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ +#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ +#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ +#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ +/** + * @ + */ + +/** + * @defgroup Detect_Filter + */ +#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ +#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ +#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ +#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ +/** + * @ + */ + +/** + * @defgroup HW_Detect_Mode + */ +#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ +#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */ +/** + * @ + */ + +/** + * @defgroup Detect_Type + */ +#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk) +#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos) + +#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ +#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */ +#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */ +#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */ +/** + * @ + */ + +/** + * @defgroup TSC_Interrupt + */ +#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ +#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ +/** + * @ + */ + +/** + * @defgroup TSC_Out + */ +#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ +#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */ +#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ +/** + * @ + */ + +/** + * @defgroup TSC_Flag + */ +#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */ + +#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */ +#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */ +#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ +/** + * @ + */ + +/** + * @defgroup TSC_SW_Detect + */ +#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ +#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */ +/** + * @ + */ + +/** + * @defgroup TSC_PadOption + */ +#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ +#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */ +/** + * @ + */ + +/** + * @defgroup TSC_PadSpeed + */ +#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ +#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +/** + * @ + */ + +/** + * @defgroup TSC_Constant + */ +#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk) +#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ +#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ +#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ +#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */ +/** + * @ + */ + +/** + * @defgroup TSC_DetectMode + */ +#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ +#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ +/** + * @ + */ + +/* TSC Exported macros -----------------------------------------------------------*/ +/** @defgroup TSC_Exported_Macros + * @{ + */ + +/** @brief Enable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Disable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Config TSC detect period for HW detect mode + * @param __PERIOD__ specifies the TSC detect period during HW detect mode + * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK + * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK + * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK + * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK + * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK + * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK + * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK + * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK + * @retval None + */ +#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__) + +/** @brief Config TSC detect filter for HW detect mode + * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode + * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse + * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse + * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse + * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse + * @retval None + */ +#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__) + +/** @brief Config TSC detect type for HW detect mode,less great or both + * @param __TYPE__ specifies the detect type of a sample during HW detect mode + * @arg TSC_DET_TYPE_NONE: Detect disable + * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time + * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time + * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) + and also be less than (basee+delta) during a sample time + * @retval None + */ +#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ + (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \ + __TYPE__) + +/** @brief Enable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Disable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Config the TSC output + * @param __OUT__ specifies where the TSC output should go + * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin + * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR + * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR + * @retval None + */ +#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ + (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\ + __OUT__) + +/** @brief Config the TSC channel + * @param __CHN__ specifies the pin of channels used for detect + * This parameter:bit[0:23] used,bit[24:31] must be 0 + * bitx: TSC channel x + * @retval None + */ +#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) + +/** @brief Enable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Disable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Config the detect channel number during SW detect mode + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval None + */ +#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__) + +/** @brief Config the pad charge type + * @param __OPT__ specifies which resistor is used for charge + * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used + * @arg TSC_PAD_EXTERNAL_RES: External resistor is used + * @retval None + */ +#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__) + +/** @brief Config TSC speed + * @param __SPEED__ specifies the TSC speed range + * @arg TSC_PAD_SPEED_0: Low speed + * @arg TSC_PAD_SPEED_1: Middle speed + * @arg TSC_PAD_SPEED_2: Middle speed + * @arg TSC_PAD_SPEED_3: High speed + * @retval None + */ +#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__) + + +/** @brief Check if the HW detect mode is enable + * @param None + * @retval Current state of HW detect mode + */ +#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) + +/** @brief Check the detect type during HW detect mode + * @param __FLAG__ specifies the flag of detect type + * @arg TSC_FLAG_LESS_DET: Flag of less detect type + * @arg TSC_FLAG_GREAT_DET: Flag of great detect type + * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type + * @retval Current state of flag + */ +#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) + +/** @brief Get the number of channel which is detected now + * @param None + * @retval Current channel number + */ +#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos ) + +/** @brief Get the count value of pulse + * @param None + * @retval Pulse count of current channel + */ +#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos ) + +/** @brief Get the base value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval base value of the channel + */ +#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos) + +/** @brief Get the delta value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval delta value of the channel + */ +#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos ) + +/** @brief Get the internal resist value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval resist value of the channel + */ +#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TSC_Private_Macros + * @{ + */ +#define IS_TSC_DET_PERIOD(_PERIOD_) \ + (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ + ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ + ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ + ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ + ||((_PERIOD_)==TSC_DET_PERIOD_104) ) + +#define IS_TSC_FILTER(_FILTER_) \ + ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ + ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) + +#define IS_TSC_DET_MODE(_MODE_) \ + ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) + +#define IS_TSC_DET_TYPE(_TYPE_) \ + ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ + ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) + +#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) + +#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) + +#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk))) + +#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitType; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref Clock */ + + uint16_t Polarity; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitType; + +/** + * @} + */ + +/** @addtogroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) +/** @addtogroup USART_Word_Length + * @{ + */ + +#define USART_WL_8B ((uint16_t)0x0000) +#define USART_WL_9B ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B)) +/** + * @} + */ + +/** @addtogroup USART_Stop_Bits + * @{ + */ + +#define USART_STPB_1 ((uint16_t)0x0000) +#define USART_STPB_0_5 ((uint16_t)0x1000) +#define USART_STPB_2 ((uint16_t)0x2000) +#define USART_STPB_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) \ + (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \ + || ((STOPBITS) == USART_STPB_1_5)) +/** + * @} + */ + +/** @addtogroup Parity + * @{ + */ + +#define USART_PE_NO ((uint16_t)0x0000) +#define USART_PE_EVEN ((uint16_t)0x0400) +#define USART_PE_ODD ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define USART_MODE_RX ((uint16_t)0x0004) +#define USART_MODE_TX ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @addtogroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HFCTRL_NONE ((uint16_t)0x0000) +#define USART_HFCTRL_RTS ((uint16_t)0x0100) +#define USART_HFCTRL_CTS ((uint16_t)0x0200) +#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \ + || ((CONTROL) == USART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup Clock + * @{ + */ +#define USART_CLK_DISABLE ((uint16_t)0x0000) +#define USART_CLK_ENABLE ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Clock_Polarity + * @{ + */ + +#define USART_CLKPOL_LOW ((uint16_t)0x0000) +#define USART_CLKPOL_HIGH ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH)) + +/** + * @} + */ + +/** @addtogroup USART_Clock_Phase + * @{ + */ + +#define USART_CLKPHA_1EDGE ((uint16_t)0x0000) +#define USART_CLKPHA_2EDGE ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE)) + +/** + * @} + */ + +/** @addtogroup USART_Last_Bit + * @{ + */ + +#define USART_CLKLB_DISABLE ((uint16_t)0x0000) +#define USART_CLKLB_ENABLE ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Interrupt_definition + * @{ + */ + +#define USART_INT_PEF ((uint16_t)0x0028) +#define USART_INT_TXDE ((uint16_t)0x0727) +#define USART_INT_TXC ((uint16_t)0x0626) +#define USART_INT_RXDNE ((uint16_t)0x0525) +#define USART_INT_IDLEF ((uint16_t)0x0424) +#define USART_INT_LINBD ((uint16_t)0x0846) +#define USART_INT_CTSF ((uint16_t)0x096A) +#define USART_INT_ERRF ((uint16_t)0x0060) +#define USART_INT_OREF ((uint16_t)0x0360) +#define USART_INT_NEF ((uint16_t)0x0260) +#define USART_INT_FEF ((uint16_t)0x0160) +#define IS_USART_CFG_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \ + || ((IT) == USART_INT_ERRF)) +#define IS_USART_GET_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \ + || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF)) +#define IS_USART_CLR_INT(IT) \ + (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF)) +/** + * @} + */ + +/** @addtogroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAREQ_TX ((uint16_t)0x0080) +#define USART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup USART_WakeUp_methods + * @{ + */ + +#define USART_WUM_IDLELINE ((uint16_t)0x0000) +#define USART_WUM_ADDRMASK ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK)) +/** + * @} + */ + +/** @addtogroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBDL_10B ((uint16_t)0x0000) +#define USART_LINBDL_11B ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B)) +/** + * @} + */ + +/** @addtogroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004) +#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTSF ((uint16_t)0x0200) +#define USART_FLAG_LINBD ((uint16_t)0x0100) +#define USART_FLAG_TXDE ((uint16_t)0x0080) +#define USART_FLAG_TXC ((uint16_t)0x0040) +#define USART_FLAG_RXDNE ((uint16_t)0x0020) +#define USART_FLAG_IDLEF ((uint16_t)0x0010) +#define USART_FLAG_OREF ((uint16_t)0x0008) +#define USART_FLAG_NEF ((uint16_t)0x0004) +#define USART_FLAG_FEF ((uint16_t)0x0002) +#define USART_FLAG_PEF ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) \ + (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \ + || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \ + || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \ + || ((FLAG) == USART_FLAG_FEF)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \ + ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTSF)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_Module* USARTx); +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct); +void USART_StructInit(USART_InitType* USART_InitStruct); +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct); +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd); +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd); +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr); +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode); +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd); +void USART_SendData(USART_Module* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_Module* USARTx); +void USART_SendBreak(USART_Module* USARTx); +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler); +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd); +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd); +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode); +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd); +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG); +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG); +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT); +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X_USART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..8d2e989a5e149d84082d5b839375ddb5aa8eed97 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_wwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L40X_WWDG_H__ +#define __N32L40X_WWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l40x.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @addtogroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Constants + * @{ + */ + +/** @addtogroup WWDG_Prescaler + * @{ + */ + +#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000) +#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080) +#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100) +#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \ + || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8)) +#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler); +void WWDG_SetWValue(uint8_t WindowValue); +void WWDG_EnableInt(void); +void WWDG_SetCnt(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetEWINTF(void); +void WWDG_ClrEWINTF(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L40X__WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/misc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/misc.c new file mode 100644 index 0000000000000000000000000000000000000000..0339acbfc9c3f3355a5a0551606786bc59ba3cea --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/misc.c @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "misc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @addtogroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @addtogroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority + * 0 bits for subpriority + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains + * the configuration information for the specified NVIC peripheral. + */ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset Vector Table base offset field. This value must be a multiple + * of 0x200. + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE. + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_adc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..cad3af98c335783fa33a4b3a23d1eaa031cfd488 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_adc.c @@ -0,0 +1,1438 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_adc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_adc.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @addtogroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Defines + * @{ + */ + +/* ADC DISC_NUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISC_EN mask */ +#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800) +#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC INJ_AUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC INJ_DISC_EN mask */ +#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000) +#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC AWDG_CH mask */ +#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF) + +/* CTRL1 register Mask */ +#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) + +/* ADC AD_ON mask */ +#define CTRL2_AD_ON_SET ((uint32_t)0x00000001) +#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTRL2_DMA_SET ((uint32_t)0x00000100) +#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF) + +/* ADC RST_CALI mask */ +#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTRL2_CAL_SET ((uint32_t)0x00000004) + +/* ADC SOFT_START mask */ +#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000) + +/* ADC EXT_TRIG mask */ +#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000) +#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000) +#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC INJ_EXT_SEL mask */ +#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC INJ_EXT_TRIG mask */ +#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000) +#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC INJ_SWSTART mask */ +#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000) +#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000) +#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* CTRL2 register Mask */ +#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR4_SEQ_SET ((uint32_t)0x0000001F) +#define SQR3_SEQ_SET ((uint32_t)0x0000001F) +#define SQR2_SEQ_SET ((uint32_t)0x0000001F) +#define SQR1_SEQ_SET ((uint32_t)0x0000001F) + +/* RSEQ1 register Mask */ +#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSEQ_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC INJ_LEN mask */ +#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000) +#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SAMPTx mask */ +#define SAMPT1_SMP_SET ((uint32_t)0x00000007) +#define SAMPT2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDATx registers offset */ +#define JDAT_OFFSET ((uint8_t)0x28) + +/* ADC1 DAT register base address */ +#define DAT_ADDR ((uint32_t)0x4001244C) + +/* ADC STS register mask */ +#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F) +/** + * @} + */ + +/** @addtogroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_DeInit(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + + if (ADCx == ADC) + { + /* Enable ADC1 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE); + /* Release ADC1 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE); + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InitStruct pointer to an ADC_InitType structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn)); + assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect)); + assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign)); + assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber)); + + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tmpreg1 = ADCx->CTRL1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CTRL1_CLR_MASK; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to WorkMode value */ + /* Set SCAN bit according to MultiChEn value */ + tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8)); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tmpreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tmpreg1 = ADCx->CTRL2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CTRL2_CLR_MASK; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL bits according to ExtTrigSelect value */ + /* Set CONT bit according to ContinueConvEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1)); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tmpreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tmpreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tmpreg1 &= RSEQ1_CLR_MASK; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ChsNumber value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized. + */ +void ADC_InitStruct(ADC_InitType* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* initialize the MultiChEn member */ + ADC_InitStruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_InitStruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1; + /* Initialize the DatAlign member */ + ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_InitStruct->ChsNumber = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd) +{ + uint32_t i=0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AD_ON bit to wake up the ADC from power down mode */ + ADCx->CTRL2 |= CTRL2_AD_ON_SET; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CTRL2 &= CTRL2_AD_ON_RESET; + } + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcDmaModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CTRL2 |= CTRL2_DMA_SET; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CTRL2 &= CTRL2_DMA_RESET; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @param Cmd new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (Cmd != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CTRL1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CTRL1 &= (~(uint32_t)itmask); + } +} + + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_StartCalibration(ADC_Module* ADCx) +{ + uint32_t i =0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Enable the selected ADC calibration process */ + if(ADCx->CALFACT==0) + ADCx->CTRL2 |= CTRL2_CAL_SET; + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + if(ADCx->CALFACT!=0) + bitstatus = RESET; + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of SOFT_START bit */ + if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET) + { + /* SOFT_START bit is set */ + bitstatus = SET; + } + else + { + /* SOFT_START bit is reset */ + bitstatus = RESET; + } + /* Return the SOFT_START bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Number specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + */ +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcSeqDiscNumberValid(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CTRL1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CTRL1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 |= CTRL1_DISC_EN_SET; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 &= CTRL1_DISC_EN_RESET; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcReqRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The Data conversion value. + */ +uint16_t ADC_GetDat(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DAT; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpregister = ADCx->CTRL2; + /* Clear the old external event selection for injected group */ + tmpregister &= CTRL2_INJ_EXT_SEL_RESET; + /* Set the external event selection for injected group */ + tmpregister |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of INJ_SWSTART bit */ + if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET) + { + /* INJ_SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* INJ_SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the INJ_SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcInjRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Get INJ_LEN value: Number = INJ_LEN+1 */ + tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Length The sequencer length. + * This parameter must be a number between 1 to 4. + */ +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjLenValid(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Clear the old injected sequnence lenght INJ_LEN bits */ + tmpreg1 &= JSEQ_INJ_LEN_RESET; + /* Set the injected sequnence lenght INJ_LEN bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InjectedChannel the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @param Offset the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + */ +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + assert_param(IsAdcOffsetValid(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t*)tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InjectedChannel the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @return The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDAT_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_AnalogWatchdog the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel + * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog + */ +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpregister &= CTRL1_AWDG_MODE_RESET; + /* Set the analog watchdog enable mode */ + tmpregister |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param HighThreshold the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcValid(HighThreshold)); + assert_param(IsAdcValid(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->WDGHIGH = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->WDGLOW = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear the Analog watchdog channel select bits */ + tmpregister &= CTRL1_AWDG_CH_RESET; + /* Set the Analog watchdog channel */ + tmpregister |= ADC_Channel; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param Cmd new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableTempSensorVrefint(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 |= CTRL2_TSVREFE_SET; + _EnVref1p2() + _EnVref2p0() + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 &= CTRL2_TSVREFE_RESET; + _DisVref1p2() + _DisVref2p0() + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + * @return The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + */ +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcClrFlag(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @return The new state of ADC_IT (SET or RESET). + */ +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT); + /* Check the status of the specified ADC interrupt */ + if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + */ +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStructEx. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx) +{ + uint32_t tmpregister = 0; + /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/ + if (ADC_InitStructEx->Samp303Style) + ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK; + else + ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK); + + /*intial ADC_CTRL3 once initiall config*/ + tmpregister = ADCx->CTRL3; + if (ADC_InitStructEx->DeepPowerModEn) + tmpregister |= ADC_CTRL3_DPWMOD_MSK; + else + tmpregister &= (~ADC_CTRL3_DPWMOD_MSK); + + if (ADC_InitStructEx->JendcIntEn) + tmpregister |= ADC_CTRL3_JENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK); + + if (ADC_InitStructEx->EndcIntEn) + tmpregister |= ADC_CTRL3_ENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK); + + if (ADC_InitStructEx->CalAtuoLoadEn) + tmpregister |= ADC_CTRL3_CALALD_MSK; + else + tmpregister &= (~ADC_CTRL3_CALALD_MSK); + + if (ADC_InitStructEx->DifModCal) + tmpregister |= ADC_CTRL3_CALDIF_MSK; + else + tmpregister &= (~ADC_CTRL3_CALDIF_MSK); + + tmpregister &= (~ADC_CTRL3_RES_MSK); + tmpregister |= ADC_InitStructEx->ResBit; + + tmpregister &= (~ADC_CTRL3_CKMOD_MSK); + if(ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL) + tmpregister |= ADC_CTRL3_CKMOD_MSK; + + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG_NEW specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_RDY ADC ready flag + * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag + * @return The new state of ADC_FLAG_NEW (SET or RESET). + */ +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG_NEW)); + /* Check the status of the specified ADC flag */ + if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET) + { + /* ADC_FLAG_NEW is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG_NEW is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG_NEW status */ + return bitstatus; +} +/** + * @brief Set Adc calibration bypass or enable. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param en enable bypass calibration. + * This parameter can be one of the following values: + * @arg true bypass calibration + * @arg false not bypass calibration + */ +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + if (en) + tmpregister |= ADC_CTRL3_BPCAL_MSK; + else + tmpregister &= (~ADC_CTRL3_BPCAL_MSK); + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Set Adc trans bits width. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ResultBitNum specifies num with adc trans width. + * This parameter can be one of the following values: + * @arg ADC_RST_BIT_12 12 bit trans + * @arg ADC_RST_BIT_10 10 bit trans + * @arg ADC_RST_BIT_8 8 bit trans + * @arg ADC_RESULT_BIT_6 6 bit trans + */ +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + tmpregister &= 0xFFFFFFFC; + tmpregister |= ResultBitNum; + ADCx->CTRL3 = tmpregister; + return; +} + + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + + * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + */ +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler) +{ + if(ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){ + RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler); + }else{ + RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1); + } +} + +/** + * @brief ADC reference voltage switch. + * @param Select reference voltage of ADC. + * @arg ADC_REFENCE_Volt_VREF Select VREF+ as reference voltage + * @arg ADC_REFENCE_Volt_VREFBUFF Select VREFBUFF as reference voltage + * @return None. + */ +void Reference_Voltage_Switch(ADC_REFERENCE_Volt Ref_Type) +{ + uint32_t afectemp = 0; + RCC_EnableAPB1PeriphClk(RCC_APB1Periph_AFEC, ENABLE); + + afectemp = AFEC->TESTR0; + afectemp &= 0xFFE5FFC1; + if(Ref_Type == ADC_REFENCE_Volt_VREFBUFF) + { + afectemp |= 0x1A0034; + } + AFEC->TESTR0 = afectemp; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_can.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_can.c new file mode 100644 index 0000000000000000000000000000000000000000..57f2c3ffef3bdfd57a024cf75ab3f9bd36a6ddca --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_can.c @@ -0,0 +1,1372 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_can.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_can.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @addtogroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */ +#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTS register */ +#define CAN_FLAGS_TSTS ((uint32_t)0x08000000) +/* Flags in RFF1 register */ +#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000) +/* Flags in RFF0 register */ +#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000) +/* Flags in MSTS register */ +#define CAN_FLAGS_MSTS ((uint32_t)0x01000000) +/* Flags in ESTS register */ +#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) +/** + * @} + */ + +/** @addtogroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_FunctionPrototypes + * @{ + */ + +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit); + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx. + */ +void CAN_DeInit(CAN_Module* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Enable CAN reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE); +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitParam. + * @param CAN to select the CAN peripheral. + * @param CAN_InitParam pointer to a CAN_InitType structure that + * contains the configuration information for the + * CAN peripheral. + * @return Constant indicates initialization succeed which will be + * CAN_InitSTS_Failed or CAN_InitSTS_Success. + */ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam) +{ + uint8_t InitStatus = CAN_InitSTS_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP)); + assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode)); + assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW)); + assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1)); + assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2)); + assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler)); + + /* Exit from sleep mode */ + CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ); + + /* Request initialisation */ + CANx->MCTRL |= CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitParam->TTCM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TTCM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitParam->ABOM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_ABOM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitParam->AWKUM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_AWKUM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitParam->NART == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_NART; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART; + } + + /* Set the receive DATFIFO locked mode */ + if (CAN_InitParam->RFLM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_RFLM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM; + } + + /* Set the transmit DATFIFO priority */ + if (CAN_InitParam->TXFP == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TXFP; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP; + } + + /* Set the bit timing register */ + CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24) + | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20) + | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1); + + /* Request leave initialisation */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + InitStatus = CAN_InitSTS_Success; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitFilterStruct. + * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType + * structure that contains the configuration + * information. + */ +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num)); + assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num; + + /* Initialisation mode for the filter */ + CAN->FMC |= FMC_FINITM; + + /* Filter Deactivation */ + CAN->FA1 &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale) + { + /* 16-bit scale for the filter */ + CAN->FS1 &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId); + } + + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale) + { + /* 32-bit scale for the filter */ + CAN->FS1 |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId); + } + + /* Filter Mode */ + if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode) + { + /*Id/Mask mode for the filter*/ + CAN->FM1 &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */ + { + /*Identifier list mode for the filter*/ + CAN->FM1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter DATFIFO assignment */ + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0) + { + /* DATFIFO 0 assignation for the filter */ + CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1) + { + /* DATFIFO 1 assignation for the filter */ + CAN->FFA1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_InitFilterStruct->Filter_Act == ENABLE) + { + CAN->FA1 |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMC &= ~FMC_FINITM; +} +/** + * @brief Fills each CAN_InitParam member with its default value. + * @param CAN_InitParam pointer to a CAN_InitType structure which + * will be initialized. + */ +void CAN_InitStruct(CAN_InitType* CAN_InitParam) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitParam->TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitParam->ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitParam->AWKUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitParam->NART = DISABLE; + + /* Initialize the receive DATFIFO locked mode */ + CAN_InitParam->RFLM = DISABLE; + + /* Initialize the transmit DATFIFO priority */ + CAN_InitParam->TXFP = DISABLE; + + /* Initialize the OperatingMode member */ + CAN_InitParam->OperatingMode = CAN_Normal_Mode; + + /* Initialize the RSJW member */ + CAN_InitParam->RSJW = CAN_RSJW_1tq; + + /* Initialize the TBS1 member */ + CAN_InitParam->TBS1 = CAN_TBS1_4tq; + + /* Initialize the TBS2 member */ + CAN_InitParam->TBS2 = CAN_TBS2_3tq; + + /* Initialize the BaudRatePrescaler member */ + CAN_InitParam->BaudRatePrescaler = 1; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CAN to select the CAN peripheral. + * @param Cmd new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + */ +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCTRL |= MCTRL_DBGF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCTRL &= ~MCTRL_DBGF; + } +} + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CAN to select the CAN peripheral. + * @param Cmd Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + */ +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCTRL |= CAN_MCTRL_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CAN to select the CAN peripheral. + * @param TxMessage pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @return The number of the mailbox that is used for transmission + * or CAN_TxSTS_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ID(TxMessage->IDE)); + assert_param(IS_CAN_RTRQ(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxSTS_NoMailBox; + } + + if (transmit_mailbox != CAN_TxSTS_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Standard_Id) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TMDL = + (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) + | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TMDH = + (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) + | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx to select the CAN peripheral. + * @param TransmitMailbox the number of the mailbox that is used for + * transmission. + * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed + * in an other case. + */ +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2); + break; + default: + state = CAN_TxSTS_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): + state = CAN_TxSTS_Pending; + break; + /* transmit failed */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Failed; + break; + /* transmit succeeded */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Ok; + break; + default: + state = CAN_TxSTS_Failed; + break; + } + return (uint8_t)state; +} + +/** + * @brief Cancels a transmit request. + * @param CAN to select the CAN peripheral. + * @param Mailbox Mailbox number. + */ +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTS = CAN_TSTS_ABRQM0; + break; + case (CAN_TXMAILBOX_1): + CANx->TSTS = CAN_TSTS_ABRQM1; + break; + case (CAN_TXMAILBOX_2): + CANx->TSTS = CAN_TSTS_ABRQM2; + break; + default: + break; + } +} + +/** + * @brief Receives a message. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + */ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI; + if (RxMessage->IDE == CAN_Standard_Id) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24); + /* Release the DATFIFO */ + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Releases the specified DATFIFO. + * @param CAN to select the CAN peripheral. + * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1. + */ +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @return NbMessage : which is the number of pending message. + */ +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum) +{ + uint8_t message_pending = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + if (FIFONum == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03); + } + else if (FIFONum == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Select the CAN Operation mode. + * @param CAN to select the CAN peripheral. + * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one + * of @ref CAN_operating_mode enumeration. + * @return status of the requested mode which can be + * - CAN_ModeSTS_Failed CAN failed entering the specific mode + * - CAN_ModeSTS_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeSTS_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INIAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_Operating_InitMode) + { + /* Request initialisation */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_NormalMode) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != 0) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_SleepMode) + { + /* Request Sleep mode */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else + { + status = CAN_ModeSTS_Failed; + } + + return (uint8_t)status; +} + +/** + * @brief Enters the low power mode. + * @param CAN to select the CAN peripheral. + * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an + * other case. + */ +uint8_t CAN_EnterSleep(CAN_Module* CANx) +{ + uint8_t sleepstatus = CAN_SLEEP_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Sleep mode status */ + if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_SLEEP_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CAN to select the CAN peripheral. + * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_Module* CANx) +{ + uint32_t wait_slak = SLPAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WKU_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ; + + /* Sleep mode status */ + while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WKU_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CAN to select the CAN peripheral. + * @return CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrCode(CAN_Module* CANx) +{ + uint8_t errorcode = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx to to select the CAN peripheral. + * @return CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CAN to to select the CAN peripheral. + * @return LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_INT_TME, + * - CAN_INT_FMP0, + * - CAN_INT_FF0, + * - CAN_INT_FOV0, + * - CAN_INT_FMP1, + * - CAN_INT_FF1, + * - CAN_INT_FOV1, + * - CAN_INT_EWG, + * - CAN_INT_EPV, + * - CAN_INT_LEC, + * - CAN_INT_ERR, + * - CAN_INT_WKU or + * - CAN_INT_SLK. + * @param Cmd new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->INTE |= CAN_INT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->INTE &= ~CAN_INT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWGFL + * - CAN_FLAG_EPVFL + * - CAN_FLAG_BOFFL + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFMP1 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFMP0 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @return The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + */ +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */ + { + /* Clear the selected CAN flags */ + CANx->ESTS = (uint32_t)RESET; + } + else /* MSTS or TSTS or RFF0 or RFF1 */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSTS = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSTS = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_INT_TME + * - CAN_INT_FMP0 + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FMP1 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + * @return The current state of CAN_INT (SET or RESET). + */ +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT) +{ + INTStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + + /* check the enable interrupt bit */ + if ((CANx->INTE & CAN_INT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_INT) + { + case CAN_INT_TME: + /* Check CAN_TSTS_RQCPx bits */ + itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2); + break; + case CAN_INT_FMP0: + /* Check CAN_RFF0_FFMP0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0); + break; + case CAN_INT_FF0: + /* Check CAN_RFF0_FFULL0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0); + break; + case CAN_INT_FOV0: + /* Check CAN_RFF0_FFOVR0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0); + break; + case CAN_INT_FMP1: + /* Check CAN_RFF1_FFMP1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1); + break; + case CAN_INT_FF1: + /* Check CAN_RFF1_FFULL1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1); + break; + case CAN_INT_FOV1: + /* Check CAN_RFF1_FFOVR1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1); + break; + case CAN_INT_WKU: + /* Check CAN_MSTS_WKUINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT); + break; + case CAN_INT_SLK: + /* Check CAN_MSTS_SLAKINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT); + break; + case CAN_INT_EWG: + /* Check CAN_ESTS_EWGFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL); + break; + case CAN_INT_EPV: + /* Check CAN_ESTS_EPVFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL); + break; + case CAN_INT_BOF: + /* Check CAN_ESTS_BOFFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL); + break; + case CAN_INT_LEC: + /* Check CAN_ESTS_LEC bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC); + break; + case CAN_INT_ERR: + /* Check CAN_MSTS_ERRINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_INT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the interrupt pending bit to clear. + * - CAN_INT_TME + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + */ +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_INT(CAN_INT)); + + switch (CAN_INT) + { + case CAN_INT_TME: + /* Clear CAN_TSTS_RQCPx (rc_w1)*/ + CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2; + break; + case CAN_INT_FF0: + /* Clear CAN_RFF0_FFULL0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFULL0; + break; + case CAN_INT_FOV0: + /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFOVR0; + break; + case CAN_INT_FF1: + /* Clear CAN_RFF1_FFULL1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFULL1; + break; + case CAN_INT_FOV1: + /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFOVR1; + break; + case CAN_INT_WKU: + /* Clear CAN_MSTS_WKUINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_WKUINT; + break; + case CAN_INT_SLK: + /* Clear CAN_MSTS_SLAKINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_SLAKINT; + break; + case CAN_INT_EWG: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_EPV: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_BOF: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_LEC: + /* Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + break; + case CAN_INT_ERR: + /*Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default: + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg specifies the CAN interrupt register to check. + * @param Int_Bit specifies the interrupt source bit to check. + * @return The new state of the CAN Interrupt (SET or RESET). + */ +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit) +{ + INTStatus pendingbitstatus = RESET; + + if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) + { + /* CAN_INT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_INT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_comp.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_comp.c new file mode 100644 index 0000000000000000000000000000000000000000..4ce6efef321e0388f9be8847781957eaf816e630 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_comp.c @@ -0,0 +1,385 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_comp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_comp.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @brief COMP driver modules + * @{ + */ + +/** @addtogroup COMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the COMP peripheral registers to their default reset values. + */ +void COMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE); +} +void COMP_StructInit(COMP_InitType* COMP_InitStruct) +{ + COMP_InitStruct->LowPoweMode =false; // only COMP1 have this bit + COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit + + COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */ + + COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK + + COMP_InitStruct->PolRev = false; // out polarity reverse + + COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC; + COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2 + COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s + COMP_InitStruct->FilterEn=false; + COMP_InitStruct->ClkPsc=0; + COMP_InitStruct->SampWindow=0; + COMP_InitStruct->Thresh=0; + COMP_InitStruct->En = false; +} +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct) +{ + COMP_SingleType* pCS; + __IO uint32_t tmp; + if(COMPx == COMP1) + pCS = &COMP->Cmp1; + else + pCS = &COMP->Cmp2; + + // filter + tmp = pCS->FILC; + SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK); + SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK); + SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK); + pCS->FILC = tmp; + // filter psc + pCS->FILP = COMP_InitStruct->ClkPsc; + + // ctrl + tmp = pCS->CTRL; + if (COMPx == COMP1) + { + if (COMP_InitStruct->InpDacConnect) + SetBit(tmp, COMP1_CTRL_INPDAC_MASK); + else + ClrBit(tmp, COMP1_CTRL_INPDAC_MASK); + if (COMP_InitStruct->LowPoweMode) + SetBit(tmp, COMP1_CTRL_PWRMODE_MASK); + else + ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK); + } + SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK); + SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK); + if (COMP_InitStruct->PolRev) + SetBit(tmp, COMP_POL_MASK); + else + ClrBit(tmp, COMP_POL_MASK); + SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK); + if (COMP_InitStruct->En) + SetBit(tmp, COMP_CTRL_EN_MASK); + else + ClrBit(tmp, COMP_CTRL_EN_MASK); + pCS->CTRL = tmp; +} +void COMP_Enable(COMPX COMPx, FunctionalState en) +{ + if(COMPx == COMP1) + { + if (en) + SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + } + else + { + if (en) + SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + } +} + +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; + +} +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} + +// return see @COMP_INTSTS_CMPIS +uint32_t COMP_GetIntSts(void) +{ + return COMP->INTSTS; +} +// parma range see @COMP_VREFSCL +// Vv2Trim,Vv1Trim max 63 +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En) +{ + __IO uint32_t tmp = 0; + + SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK); + SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK); + SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK); + SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK); + + COMP->VREFSCL = tmp; +} +// SET when comp out 1 +// RESET when comp out 0 +FlagStatus COMP_GetOutStatus(COMPX COMPx) +{ + if(COMPx == COMP1) + return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; + else + return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; +} +// get one comp interrupt flags +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx) +{ + return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET; +} + +// Lock see @COMP_LOCK +void COMP_SetLock(uint32_t Lock) +{ + COMP->LOCK = Lock; +} +// IntEn see @COMP_INTEN_CMPIEN +void COMP_SetIntEn(uint32_t IntEn) +{ + COMP->INTEN = IntEn; +} +// set comp2 xor output with comp1 +void COMP_CMP2XorOut(bool En) +{ + COMP->CMP2OSEL = (En==true)?0x1L:0x0L; +} +// set stop or lowpower mode that sel 32k clk +void COMP_StopOrLowpower32KClkSel(bool En) +{ + COMP->LPCKSEL = (En==true)?0x1L:0x0L; +} +// set comp1 and comp2 component window compare mode +void COMP_WindowModeEn(bool En) +{ + COMP->WINMODE = (En==true)?0x1L:0x0L; +} + + +/** + * @brief Set the COMP filter clock Prescaler value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1. + * @return void + */ +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILP=FilPreVal; + else + COMP->Cmp2.FILP=FilPreVal; +} + +/** + * @brief Set the COMP filter control value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilEn 1 for enable ,0 or disable + * @param TheresNum num under this value is noise + * @param SampPW total sample number in a window + * @return void + */ +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); + else + COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); +} + +/** + * @brief Set the COMP Hyst value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param HYST specifies the HYST level. + * This parameter can be one of the following values: +* @arg COMP_CTRL_HYST_NO Hyst disable +* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV +* @arg COMP_CTRL_HYST_MID Hyst level 15mV +* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV + * @return void + */ +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + + tmp&=~COMP_CTRL_HYST_HIGH; + tmp|=HYST; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @brief Set the COMP Blanking source . + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param BLK specifies the blanking source . + * This parameter can be one of the following values: +* @arg COMP_CTRL_BLKING_NO Blanking disable +* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5 +* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5 + * @return void + */ +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + tmp&=~(7<<16); + tmp|=BLK; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_crc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..afc00fd032e1956635b352b8dc6438fd1214bece --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_crc.c @@ -0,0 +1,227 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_crc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_crc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @addtogroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DAT). + */ +void CRC32_ResetCrc(void) +{ + /* Reset CRC generator */ + CRC->CRC32CTRL = CRC32_CTRL_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data data word(32-bit) to compute its CRC + * @return 32-bit CRC + */ +uint32_t CRC32_CalcCrc(uint32_t Data) +{ + CRC->CRC32DAT = Data; + + return (CRC->CRC32DAT); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed + * @return 32-bit CRC + */ +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < BufferLength; index++) + { + CRC->CRC32DAT = pBuffer[index]; + } + return (CRC->CRC32DAT); +} + +/** + * @brief Returns the current CRC value. + * @return 32-bit CRC + */ +uint32_t CRC32_GetCrc(void) +{ + return (CRC->CRC32DAT); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue 8-bit value to be stored in the ID register + */ +void CRC32_SetIDat(uint8_t IDValue) +{ + CRC->CRC32IDAT = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @return 8-bit value of the ID register + */ +uint8_t CRC32_GetIDat(void) +{ + return (CRC->CRC32IDAT); +} + +// CRC16 add +void __CRC16_SetLittleEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL; +} +void __CRC16_SetBigEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL; +} +void __CRC16_SetCleanEnable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL; +} +void __CRC16_SetCleanDisable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL; +} + +uint16_t __CRC16_CalcCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; + return (CRC->CRC16D); +} + +void __CRC16_SetCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; +} + +uint16_t __CRC16_GetCrc(void) +{ + return (CRC->CRC16D); +} + +void __CRC16_SetLRC(uint8_t Data) +{ + CRC->LRC = Data; +} + +uint8_t __CRC16_GetLRC(void) +{ + return (CRC->LRC); +} + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + CRC->CRC16D = 0x00; + for (index = 0; index < BufferLength; index++) + { + CRC->CRC16DAT = pBuffer[index]; + } + return (CRC->CRC16D); +} + +uint16_t CRC16_CalcCRC(uint8_t Data) +{ + CRC->CRC16DAT = Data; + + return (CRC->CRC16D); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dac.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..fff549f4404707248e298a3b32718cfb77b0fa3e --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dac.c @@ -0,0 +1,357 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dac.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_dac.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @addtogroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Defines + * @{ + */ + +/* CTRL register Mask */ +#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000001) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE) + +/* DCH registers offsets */ +#define DR12CH_OFFSET ((uint32_t)0x00000008) + +/* DATO register offset */ +#define DATO_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @addtogroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_InitStruct pointer to a DAC_InitType structure that + * contains the configuration information for the specified DAC channel. + */ +void DAC_Init(DAC_InitType* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput)); + /*---------------------------- DAC CTRL Configuration --------------------------*/ + /* Get the DAC CTRL value */ + tmpreg1 = DAC->CTRL; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CTRL_CLEAR_MASK ); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to Trigger value */ + /* Set WAVEx bits according to WaveGen value */ + /* Set MAMPx bits according to LfsrUnMaskTriAmp value */ + /* Set BOFFx bit according to BufferOutput value */ + tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp + | DAC_InitStruct->BufferOutput); + /* Calculate CTRL register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 ; + /* Write to DAC CTRL */ + DAC->CTRL = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct pointer to a DAC_InitType structure which will + * be initialized. + */ +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct) +{ + /*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the Trigger member */ + DAC_InitStruct->Trigger = DAC_TRG_NONE; + /* Initialize the WaveGen member */ + DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE; + /* Initialize the LfsrUnMaskTriAmp member */ + DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0; + /* Initialize the BufferOutput member */ + DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_Enable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CTRL |= DAC_CTRL_CHEN ; + } + else + { + /* Disable the selected DAC channel */ + DAC->CTRL &= ~DAC_CTRL_CHEN ; + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_DmaEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CTRL |= DAC_CTRL_DMAEN; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CTRL &= ~DAC_CTRL_DMAEN; + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SOTTR |= DAC_SOTTR_TREN ; + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SOTTR &= ~(DAC_SOTTR_TREN); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param Cmd new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftwareTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SOTTR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SOTTR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_Wave Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_WAVE_NOISE noise wave generation + * @arg DAC_WAVE_TRIANGLE triangle wave generation + * @param Cmd new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmp=DAC->CTRL; + tmp&=~(3<<6); + if (Cmd != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + tmp |= DAC_Wave; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + tmp&=~(3<<6); + } + DAC->CTRL =tmp; +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + */ +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DR12CH_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*)tmp = Data; +} + + + + + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @return The selected DAC channel data output value. + */ +uint16_t DAC_GetOutputDataVal(void) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DATO_OFFSET; + + /* Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dbg.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dbg.c new file mode 100644 index 0000000000000000000000000000000000000000..a8f3896e95e57aac5e861e4272fb325949ec7e04 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dbg.c @@ -0,0 +1,260 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dbg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_dbg.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @brief DBG driver modules + * @{ + */ + +/** @addtogroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Functions + * @{ + */ + + +void GetUCID(uint8_t *UCIDbuf) +{ + uint8_t num = 0; + uint32_t* ucid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260)) + { + ucid_addr = (uint32_t*)UCID_BASE; + } + else + { + ucid_addr = (uint32_t*)(0x1FFFF260); + } + + for (num = 0; num < UCID_LENGTH;) + { + temp = *(__IO uint32_t*)(ucid_addr++); + UCIDbuf[num++] = (temp & 0xFF); + UCIDbuf[num++] = (temp & 0xFF00) >> 8; + UCIDbuf[num++] = (temp & 0xFF0000) >> 16; + UCIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the UID. + * @return UID + */ + +void GetUID(uint8_t *UIDbuf) +{ + uint8_t num = 0; + uint32_t* uid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270)) + { + uid_addr = (uint32_t*)UID_BASE; + } + else + { + uid_addr = (uint32_t*)(0x1FFFF270); + } + + for (num = 0; num < UID_LENGTH;) + { + temp = *(__IO uint32_t*)(uid_addr++); + UIDbuf[num++] = (temp & 0xFF); + UIDbuf[num++] = (temp & 0xFF00) >> 8; + UIDbuf[num++] = (temp & 0xFF0000) >> 16; + UIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the DBGMCU_ID. + * @return DBGMCU_ID + */ + +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf) +{ + uint8_t num = 0; + uint32_t* dbgid_addr = (void*)0; + uint32_t temp = 0; + + dbgid_addr = (uint32_t*)DBGMCU_ID_BASE; + for (num = 0; num < DBGMCU_ID_LENGTH;) + { + temp = *(__IO uint32_t*)(dbgid_addr++); + DBGMCU_IDbuf[num++] = (temp & 0xFF); + DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8; + DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16; + DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the device revision number. + * @return Device revision identifier + */ +uint32_t DBG_GetRevNum(void) +{ + return (DBG->ID & 0x00FF); +} + +/** + * @brief Returns the device identifier. + * @return Device identifier + */ +uint32_t DBG_GetDevNum(void) +{ + uint32_t id = DBG->ID; + return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBG_Periph specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBG_SLEEP Keep debugger connection during SLEEP mode + * @arg DBG_STOP Keep debugger connection during STOP mode + * @arg DBG_STDBY Keep debugger connection during STANDBY mode + * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted + * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted + * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted + * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted + * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted + * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted + * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted + * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted + * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted + * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted + * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted + * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted + + * @param Cmd new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + */ +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBG_Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + DBG->CTRL |= DBG_Periph; + } + else + { + DBG->CTRL &= ~DBG_Periph; + } +} + +/** + * @brief Get FLASH size of this chip. + * + * @return FLASH size in bytes. + */ +uint32_t DBG_GetFlashSize(void) +{ + return (DBG->ID & 0x000F0000); +} + +/** + * @brief Get SRAM size of this chip. + * + * @return SRAM size in bytes. + */ +uint32_t DBG_GetSramSize(void) +{ + return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dma.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..4504ff7a7aca31e6b70444c8c6ce62afd7eb4ecf --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_dma.c @@ -0,0 +1,686 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_dma.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_dma.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @addtogroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Defines + * @{ + */ + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1)) +#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2)) +#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3)) +#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4)) +#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5)) +#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6)) +#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7)) +#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8)) + + +/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + */ +void DMA_DeInit(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + + /* Reset DMAy Channelx control register */ + DMAChx->CHCFG = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAChx->TXNUM = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAChx->PADDR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAChx->MADDR = 0; + + if (DMAChx == DMA_CH1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA->INTCLR |= DMA_CH1_INT_MASK; + } + else if (DMAChx == DMA_CH2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA->INTCLR |= DMA_CH2_INT_MASK; + } + else if (DMAChx == DMA_CH3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA->INTCLR |= DMA_CH3_INT_MASK; + } + else if (DMAChx == DMA_CH4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA->INTCLR |= DMA_CH4_INT_MASK; + } + else if (DMAChx == DMA_CH5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA->INTCLR |= DMA_CH5_INT_MASK; + } + else if (DMAChx == DMA_CH6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA->INTCLR |= DMA_CH6_INT_MASK; + } + else if (DMAChx == DMA_CH7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA->INTCLR |= DMA_CH7_INT_MASK; + } + else if (DMAChx == DMA_CH8) + { + /* Reset interrupt pending bits for DMA1 Channel8 */ + DMA->INTCLR |= DMA_CH8_INT_MASK; + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitParam. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMA_InitParam pointer to a DMA_InitType structure that + * contains the configuration information for the specified DMA Channel. + */ +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_DIR(DMA_InitParam->Direction)); + assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize)); + assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc)); + assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize)); + assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode)); + assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem)); + + /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/ + /* Get the DMAyChx CHCFG value */ + tmpregister = DMAChx->CHCFG; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpregister &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to Direction value */ + /* Set CIRC bit according to CircularMode value */ + /* Set PINC bit according to PeriphInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to PeriphDataSize value */ + /* Set MSIZE bits according to MemDataSize value */ + /* Set PL bits according to Priority value */ + /* Set the MEM2MEM bit according to Mem2Mem value */ + tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc + | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize + | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem; + + /* Write to DMAy Channelx CHCFG */ + DMAChx->CHCFG = tmpregister; + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMAy Channelx TXNUM */ + DMAChx->TXNUM = DMA_InitParam->BufSize; + + /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/ + /* Write to DMAy Channelx PADDR */ + DMAChx->PADDR = DMA_InitParam->PeriphAddr; + + /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/ + /* Write to DMAy Channelx MADDR */ + DMAChx->MADDR = DMA_InitParam->MemAddr; +} + +/** + * @brief Fills each DMA_InitParam member with its default value. + * @param DMA_InitParam pointer to a DMA_InitType structure which will + * be initialized. + */ +void DMA_StructInit(DMA_InitType* DMA_InitParam) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the PeriphAddr member */ + DMA_InitParam->PeriphAddr = 0; + /* Initialize the MemAddr member */ + DMA_InitParam->MemAddr = 0; + /* Initialize the Direction member */ + DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC; + /* Initialize the BufSize member */ + DMA_InitParam->BufSize = 0; + /* Initialize the PeriphInc member */ + DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE; + /* Initialize the DMA_MemoryInc member */ + DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE; + /* Initialize the PeriphDataSize member */ + DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + /* Initialize the MemDataSize member */ + DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the CircularMode member */ + DMA_InitParam->CircularMode = DMA_MODE_NORMAL; + /* Initialize the Priority member */ + DMA_InitParam->Priority = DMA_PRIORITY_LOW; + /* Initialize the Mem2Mem member */ + DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAChx->CHCFG |= DMA_CHCFG1_CHEN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMAInt specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_INT_TXC Transfer complete interrupt mask + * @arg DMA_INT_HTX Half transfer interrupt mask + * @arg DMA_INT_ERR Transfer error interrupt mask + * @param Cmd new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_CONFIG_INT(DMAInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAChx->CHCFG |= DMAInt; + } + else + { + /* Disable the selected DMA interrupts */ + DMAChx->CHCFG &= ~DMAInt; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DataNumber The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAyChx is disabled. + */ +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMA Channelx TXNUM */ + DMAChx->TXNUM = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMA Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @return The number of remaining data units in the current DMA Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAChx->TXNUM)); +} + +/** + * @brief Checks whether the specified DMA Channelx flag is set or not. + * @param DMAFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel7 global flag. + * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMAFlag (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy flag */ + if ((tmpregister & DMAFlag) != (uint32_t)RESET) + { + /* DMAyFlag is set */ + bitstatus = SET; + } + else + { + /* DMAyFlag is reset */ + bitstatus = RESET; + } + + /* Return the DMAyFlag status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's pending flags. + * @param DMAFlag specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel8 global flag. + * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Clear the selected DMAy flags */ + DMAy->INTCLR = DMAFlag; +} + +/** + * @brief Checks whether the specified DMA Channelx interrupt has occurred or not. + * @param DMA_IT specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMA_IT (SET or RESET). + */ +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy interrupt */ + if ((tmpregister & DMA_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMAInt status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's interrupt pending bits. + * @param DMA_IT specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLR_INT(DMA_IT)); + + /* Calculate the used DMA */ + /* Clear the selected DMA interrupt pending bits */ + DMAy->INTCLR = DMA_IT; +} + +/** + * @brief Set the DMA Channelx's remap request. + * @param DMA_REMAP specifies the DMA request. + * This parameter can be set by the following values: + * @arg DMA_REMAP_ADC1 DMA Request For ADC1. + * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX. + * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX. + * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX. + * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX. + * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX. + * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX. + * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX. + * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX. + * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX. + * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX. + * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX. + * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX. + * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX. + * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX. + * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX. + * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX. + * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX. + * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX. + * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX. + * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX. + * @arg DMA_REMAP_DAC1 DMA Request For DAC1. + * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1. + * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2. + * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3. + * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4. + * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM. + * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP. + * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG. + * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1. + * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2. + * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3. + * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP. + * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1. + * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3. + * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4. + * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP. + * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1. + * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2. + * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3. + * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP. + * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1. + * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2. + * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3. + * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4. + * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP. + * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG. + * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP. + * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP. + * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1. + * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2. + * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3. + * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4. + * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM. + * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP. + * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG. + * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1. + * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG. + * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3. + * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4. + * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_REMAP(DMA_REMAP)); + + if (Cmd != DISABLE) + { + /* Calculate the used DMAy */ + /* Set the selected DMAy remap request */ + DMAChx->CHSEL = DMA_REMAP; + } + else + { + /* Clear DMAy remap */ + DMAChx->CHSEL = 0; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_exti.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_exti.c new file mode 100644 index 0000000000000000000000000000000000000000..02743e2a514453afe5c3594a87e5652365932ac5 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_exti.c @@ -0,0 +1,286 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_exti.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_exti.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @addtogroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + */ +void EXTI_DeInit(void) +{ + EXTI->IMASK = 0x00000000; + EXTI->EMASK = 0x00000000; + EXTI->RT_CFG = 0x00000000; + EXTI->FT_CFG = 0x00000000; + EXTI->PEND = 0x0FFFFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure + * that contains the configuration information for the EXTI peripheral. + */ +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will + * be initialized. + */ +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_TriggerSWInt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIE |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrStatusFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMASK & EXTI_Line; + if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrITPendBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Select one of EXTI inputs to the RTC TimeStamp event. + * @param EXTI_TSSEL_Line specifies the EXTI lines to select. + * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15). + */ +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line)); + + EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK; + EXTI->TS_SEL |= EXTI_TSSEL_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_flash.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..08864e1a438e9914d42eb9fcd76bba427a8fd7e0 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_flash.c @@ -0,0 +1,1554 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_flash.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_flash.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @addtogroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define AC_LATENCY_MSK ((uint32_t)0x000000F8) +#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF) +#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F) +#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF) +#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF) + +/* Flash Access Control Register bits */ +#define AC_PRFTBS_MSK ((uint32_t)0x00000020) +#define AC_ICAHRST_MSK ((uint32_t)0x00000040) +#define AC_LVMF_MSK ((uint32_t)0x00000100) +#define AC_SLMF_MSK ((uint32_t)0x00000400) + +/* Flash Control Register bits */ +#define CTRL_Set_PG ((uint32_t)0x00000001) +#define CTRL_Reset_PG ((uint32_t)0x00003FFE) +#define CTRL_Set_PER ((uint32_t)0x00000002) +#define CTRL_Reset_PER ((uint32_t)0x00003FFD) +#define CTRL_Set_MER ((uint32_t)0x00000004) +#define CTRL_Reset_MER ((uint32_t)0x00003FFB) +#define CTRL_Set_OPTPG ((uint32_t)0x00000010) +#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF) +#define CTRL_Set_OPTER ((uint32_t)0x00000020) +#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF) +#define CTRL_Set_START ((uint32_t)0x00000040) +#define CTRL_Set_LOCK ((uint32_t)0x00000080) +#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF) +#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000) +#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100) + +/* FLASH Mask */ +#define RDPRTL1_MSK ((uint32_t)0x00000002) +#define RDPRTL2_MSK ((uint32_t)0x80000000) +#define OBR_USER_MSK ((uint32_t)0x0000001C) +#define WRP0_MSK ((uint32_t)0x000000FF) +#define WRP1_MSK ((uint32_t)0x0000FF00) +#define WRP2_MSK ((uint32_t)0x00FF0000) +#define WRP3_MSK ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define L1_RDP_Key ((uint32_t)0xFFFF00A5) +#define RDP_USER_Key ((uint32_t)0xFFF000A5) +#define L2_RDP_Key ((uint32_t)0xFFFF33CC) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @note This function can be used for n32l40x devices. + * @param FLASH_Latency specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1 FLASH One Latency cycle + * @arg FLASH_LATENCY_2 FLASH Two Latency cycles + * @arg FLASH_LATENCY_3 FLASH Three Latency cycles + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpregister = FLASH->AC; + + /* Sets the Latency value */ + tmpregister &= AC_LATENCY_MSK; + tmpregister |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->AC = tmpregister; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for n32l40x devices. + * @param FLASH_PrefetchBuf specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable + */ +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->AC &= AC_PRFTBE_MSK; + FLASH->AC |= FLASH_PrefetchBuf; +} + +/** + * @brief ICache Reset. + * @note This function can be used for n32l40x devices. + */ +void FLASH_iCacheRST(void) +{ + /* ICache Reset */ + FLASH->AC |= FLASH_AC_ICAHRST; +} + +/** + * @brief Enables or disables the iCache. + * @note This function can be used for n32l40x devices. + * @param FLASH_iCache specifies the iCache status. + * This parameter can be one of the following values: + * @arg FLASH_iCache_EN FLASH iCache Enable + * @arg FLASH_iCache_DIS FLASH iCache Disable + */ +void FLASH_iCacheCmd(uint32_t FLASH_iCache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache)); + + /* Enable or disable the iCache */ + FLASH->AC &= AC_ICAHEN_MSK; + FLASH->AC |= FLASH_iCache; +} + +/** + * @brief Enables or disables the Low Voltage Mode. + * @note This function can be used for n32l40x devices. + * @param FLASH_LVM specifies the Low Voltage Mode status. + * This parameter can be one of the following values: + * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable + * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable + */ +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LVM(FLASH_LVM)); + + /* Enable or disable LVM */ + FLASH->AC &= AC_LVMEN_MSK; + FLASH->AC |= FLASH_LVM; +} + +/** + * @brief Checks whether the Low Voltage Mode status is SET or RESET. + * @note This function can be used for n32l40x devices. + * @return Low Voltage Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetLowVoltageModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the FLASH Sleep Mode. + * @note This function can be used for n32l40x devices. + * @param FLASH_SLM specifies the FLASH Sleep Mode status. + * This parameter can be one of the following values: + * @arg FLASH_SLM_EN FLASH iCache Enable + * @arg FLASH_SLM_DIS FLASH iCache Disable + */ +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SLM(FLASH_SLM)); + + /* Enable or disable SLM */ + FLASH->AC &= AC_SLMEN_MSK; + FLASH->AC |= FLASH_SLM; +} + +/** + * @brief Checks whether the FLASH Sleep Mode status is SET or RESET. + * @note This function can be used for n32l40x devices. + * @return FLASH Sleep Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetFLASHSleepModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for n32l40x devices. + * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2 + */ +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel)); + + /* SMP1 or SMP2 */ + FLASH->CTRL &= CTRL_Reset_SMPSEL; + FLASH->CTRL |= FLASH_smpsel; +} + +/** + * @brief Configures the Internal High Speed oscillator + * to program/erase FLASH. + * @note This function can be used for n32l40x devices. + * - For n32l40x devices this function enable HSI. + * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE). + */ +FLASH_HSICLOCK FLASH_ClockInit(void) +{ + bool HSIStatus = 0; + __IO uint32_t StartUpCounter = 0; + FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE; + + if((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET) + { + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + hsiclock_status = FLASH_HSICLOCK_DISABLE; + } + } + return hsiclock_status; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for n32l40x devices. + * - For n32l40x devices this function unlocks Bank. + * to FLASH_Unlock function.. + */ +void FLASH_Unlock(void) +{ + /* Unlocks the FLASH Program Erase Controller */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for n32l40x devices. + * - For n32l40x devices this function Locks Bank. + * to FLASH_Lock function. + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FLASH Program Erase Controller */ + FLASH->CTRL |= CTRL_Set_LOCK; +} + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for n32l40x devices. + * @param Page_Address The page address to be erased. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CTRL |= CTRL_Set_PER; + FLASH->ADD = Page_Address; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CTRL &= CTRL_Reset_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all n32l40x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_MassErase(void) +{ + FLASH_STS status = FLASH_COMPL; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= CTRL_Set_MER; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CTRL &= CTRL_Reset_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for n32l40x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOB(void) +{ + uint32_t rdptmp = L1_RDP_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdptmp = FLASH_USER_USER; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = (uint32_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the erase status */ + return status; +} + + +/** + * @brief Programs the FLASH User Option Byte: + * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / OB_Data0 / OB_Data1 + * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for n32l40x devices. + * @param OB_RDP1 + * This parameter can be one of the following values: + * @arg OB_RDP1_ENABLE + * @arg OB_RDP1_DISABLE + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @param OB_Data0 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param OB_Data1 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param WRP_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b n32l40x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages) + * @param OB_RDP2 + * This parameter can be one of the following values: + * @arg OB_RDP2_ENABLE + * @arg OB_RDP2_DISABLE + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_RDP1_SOURCE(OB_RDP1)); + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + assert_param(IS_FLASH_WRP_PAGE(WRP_Pages)); + assert_param(IS_OB_RDP2_SOURCE(OB_RDP2)); + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + WRP_Pages = (uint32_t)(~WRP_Pages); + rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY)) << 16)); + data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data1) << 16)); + wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1)); + wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3)); + rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16)); + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Program USER_RDP Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program Data1_Data0 Option Byte value */ + OBT->Data1_Data0 = (uint32_t)data0data1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP1_WRP0 Option Byte value */ + OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP3_WRP2 Option Byte value */ + OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program USER2_RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + } + } + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for n32l40x devices. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + if((Address & (uint32_t)0x3) != 0) + { + /* The programming address is not a multiple of 4 */ + status = FLASH_ERR_ADD; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to program the new word */ + FLASH->CTRL |= CTRL_Set_PG; + + *(__IO uint32_t*)Address = (uint32_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CTRL &= CTRL_Reset_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for n32l40x devices. + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804. + * @param Data specifies the data to be programmed(Data0 and Data1). + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + *(__IO uint32_t*)Address = (uint32_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for n32l40x devices. + * @param FLASH_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b n32l40x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63 + * @arg FLASH_WRP_AllPages + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTPG; + + if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF)) + { + OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL)) + { + OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for n32l40x devices. + * @param Cmd new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + if (Cmd != DISABLE) + { + OBT->USER_RDP = (FLASH_USER_USER & usertmp); + } + else + { + OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection L2. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for n32l40x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + + /* Get the actual read protection L1 Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() == RESET) + { + usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1); + } + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + OBT->USER_RDP = usertmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Enables the read out protection L2 */ + OBT->USER2_RDP2 = L2_RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for n32l40x devices. + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY) +{ + uint32_t rdpuser_tmp = RDP_USER_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFF00000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = + (uint32_t)rdpuser_tmp + | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY )) << 16); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for n32l40x devices. + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, + uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER); + uint32_t rdp2user2_tmp = 0xFF00FFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFFF0000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Restore the last RDP1 Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Restore the last RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \ + | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for n32l40x devices. + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOB(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OB >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for n32l40x devices. + * @return The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOB(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRP); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for n32l40x devices. + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionSTS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not. + * @note This function can be used for n32l40x devices. + * @return FLASH ReadOut Protection L2 Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionL2STS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for n32l40x devices. + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for n32l40x devices. + * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2). + */ +FLASH_SMPSEL FLASH_GetSMPSELStatus(void) +{ + FLASH_SMPSEL bitstatus = FLASH_SMP1; + + if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1) + { + bitstatus = FLASH_SMP2; + } + else + { + bitstatus = FLASH_SMP1; + } + /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for n32l40x devices. + * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR FLASH Error Interrupt + * @arg FLASH_INT_FERR EVERR PVERR Interrupt + * @arg FLASH_INT_EOP FLASH end of operation Interrupt + * @param Cmd new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FLASH_INT(FLASH_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CTRL |= FLASH_INT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CTRL &= ~(uint32_t)FLASH_INT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for n32l40x devices. + * @param FLASH_FLAG specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BUSY FLASH Busy flag + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + if (FLASH_FLAG == FLASH_FLAG_OBERR) + { + if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for n32l40x devices. + * @param FLASH_FLAG specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->STS |= FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for n32l40x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_GetSTS(void) +{ + FLASH_STS flashstatus = FLASH_COMPL; + + if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERR_PG; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PVERR) != 0) + { + flashstatus = FLASH_ERR_PV; + } + else + { + if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0) + { + flashstatus = FLASH_ERR_WRP; + } + else + { + if ((FLASH->STS & FLASH_FLAG_EVERR) != 0) + { + flashstatus = FLASH_ERR_EV; + } + else + { + flashstatus = FLASH_COMPL; + } + } + } + } + } + + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for n32l40x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation.. + * @param Timeout FLASH programming Timeout + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check for the Flash Status */ + status = FLASH_GetSTS(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetSTS(); + Timeout--; + } + if (Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_gpio.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..e4f855b75ec9e1a219c36495988ba8d15b197820 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_gpio.c @@ -0,0 +1,768 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_gpio.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_gpio.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @addtogroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- Event control register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +#define GPIO_MODE ((uint32_t)0x00000003) +#define EXTI_MODE ((uint32_t)0x10000000) +#define GPIO_MODE_IT ((uint32_t)0x00010000) +#define GPIO_MODE_EVT ((uint32_t)0x00020000) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300) +#define GPIO_NUMBER ((uint32_t)16) + + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + */ +void GPIO_DeInit(GPIO_Module* GPIOx) +{ + + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + uint32_t GPIO_Pin = GPIO_PIN_ALL; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + /* Check the parameters */ + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + + if (GPIOx == GPIOA) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE); + } + else + { + return; + } + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0) + { + /* Get the IO position */ + iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position); + + if(iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = AFIO->EXTI_CFG[position>>2]; + tmp &= (0x0FuL << (4u*(position & 0x03u))); + if(tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~(iocurrent); + EXTI->EMASK &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~(iocurrent); + EXTI->FT_CFG &= ~(iocurrent); + tmp = 0x0FuL << (4u * (position & 0x03u)); + AFIO->EXTI_CFG[position >> 2u] &= ~tmp; + } + + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + if(position & 0x08) + GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + else + GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + + /* Configure the default value IO Output Type */ + GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U)); + + } + position++; + } +} + + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + */ +void GPIO_AFIOInitDefault(void) +{ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure that + * contains the configuration information for the specified GPIO peripheral. + */ + +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct) +{ + uint32_t pinpos = 0x00U; + uint32_t tmp = 0x00U,tmpregister=0x00U; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull)); + assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + + /*---------------------------- GPIO PL_CFG Configuration ------------------------*/ + + while(((GPIO_InitStruct->Pin)>>position) != 0) + { + iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog)) + { + /* Check if the Alternate function is compliant with the GPIO in use */ + assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate)); + /* Configure Alternate function mapped with the current IO */ + if(position & 0x08) + { + tmp = GPIOx->AFH; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFH = tmp; + } + else + { + tmp = GPIOx->AFL; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFL = tmp; + } + } + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmpregister = GPIOx->PMODE; + tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |=( tmp << pinpos); + GPIOx->PMODE = tmpregister; + + /* Configure pull-down mode */ + tmpregister = GPIOx->PUPD; + tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03); + tmpregister &=~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp <PUPD = tmpregister; + + + /* Configure driver current*/ + if((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog)) + { + assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current)); + tmpregister = GPIOx->DS; + tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03)); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp<DS = tmpregister; + } + /* Configure slew rate*/ + tmp = GPIOx->SR; + tmp &=((uint32_t)(~((uint16_t)0x01 << position))); + tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp; + /*Configure Set/Reset register*/ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down) + { + GPIOx->PBC |= (((uint32_t)0x01) << position); + } + else + { + /* Set the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up) + { + GPIOx->PBSC |= (((uint32_t)0x01) << position); + } + } + + /* In case of Output or Alternate function mode selection */ + if((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) || + (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD)) + { + /* Configure the IO Output Type */ + + tmp= GPIOx->POTYPE; + tmp &= ~(((uint32_t)0x01U) << position) ; + tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->POTYPE = tmp; + } + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if(GPIO_InitStruct->GPIO_Mode & EXTI_MODE) + { + /* Clear EXTI line configuration */ + tmp = EXTI->IMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->IMASK = tmp; + + tmp = EXTI->EMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->EMASK = tmp; + + /* Clear Rising Falling edge configuration */ + + tmp = EXTI->RT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->RT_CFG = tmp; + + tmp = EXTI->FT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->FT_CFG = tmp; + } + } + position++; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will + * be initialized. + */ +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = GPIO_PIN_ALL; + GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input; + GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF; + GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull; + GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->PID); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->POD); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} +void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + // assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBC = Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitCmd specifies the value to be written to the selected bit. + * This parameter can be one of the Bit_OperateType enum values: + * @arg Bit_RESET to clear the port pin + * @arg Bit_SET to set the port pin + */ +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + assert_param(IS_GPIO_BIT_OPERATE(BitCmd)); + + if (BitCmd != Bit_RESET) + { + GPIOx->PBSC = Pin; + } + else + { + GPIOx->PBC = Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param PortVal specifies the value to be written to the port output data register. + */ +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->POD = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + tmp |= Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Reset LCKK bit */ + GPIOx->PLOCK = Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; +} + + + +/** + * @brief Changes the mapping of the specified pin. + * @param PortSource selects the GPIO port to be used. + * @param PinSource specifies the pin for the remaping. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param AlternateFunction specifies the alternate function for the remaping. + */ +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction) +{ + uint32_t tmp = 0x00, tmpregister = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + assert_param(IS_GPIO_AF(AlternateFunction)); + /*Get Peripheral point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + /**/ + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param PortSource selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t tmpregister = 0x00,tmp = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + /*Get Peripheral structure point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Enables or disables the Event Output. + * @param Cmd new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + */ +void GPIO_CtrlEventOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd; +} + + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param PortSource selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t port = (uint32_t)PortSource; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u)); + AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u)); +} + +/** + * @brief Selects the alternate function SPIx NSS mode. + * @param AFIO_SPIx_NSS choose which SPI configuration. + * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS. + * @param SpiNssType specifies the SPI_NSS mode to be configured. + * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL. + */ +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS)); + assert_param(IS_AFIO_SPI_NSS(SpiNssType)); + tmp = AFIO->RMP_CFG; + tmp &=(~(0x01U << AFIO_SPIx_NSS)); + tmp |=(SpiNssType << AFIO_SPIx_NSS); + AFIO->RMP_CFG = tmp; +} + +/** + * @brief Configur ADC external trigger. + * @param ADCETRType choose whether to configure rule conversion or injection conversion . + * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR. + * @param ADCTrigRemap specifies the external trigger line be configured. + * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4). + */ +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETR(ADCETRType)); + if(ADCETRType == AFIO_ADC_ETRI) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRI bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRI)); + /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4) + { + /* select TIM8_CH4 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRI); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<4U)); + tmp |= (ADCTrigRemap<<4U); + } + AFIO->RMP_CFG = tmp; + } + else + { + if(ADCETRType == AFIO_ADC_ETRR) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRR bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRR)); + /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3) + { + /* select TIM8_CH3 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRR); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<0)); + tmp |= ADCTrigRemap; + } + AFIO->RMP_CFG = tmp; + } + } +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_i2c.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..0bb4ae468aae9c1bcb66d89e692a2a22436ffd64 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_i2c.c @@ -0,0 +1,1301 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_i2c.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_i2c.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @addtogroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CTRL1_SPEN_SET ((uint16_t)0x0001) +#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTRL1_START_SET ((uint16_t)0x0100) +#define CTRL1_START_RESET ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTRL1_STOP_SET ((uint16_t)0x0200) +#define CTRL1_STOP_RESET ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTRL1_ACK_SET ((uint16_t)0x0400) +#define CTRL1_ACK_RESET ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTRL1_GCEN_SET ((uint16_t)0x0040) +#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTRL1_SWRESET_SET ((uint16_t)0x8000) +#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTRL1_PEC_SET ((uint16_t)0x1000) +#define CTRL1_PEC_RESET ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTRL1_PECEN_SET ((uint16_t)0x0020) +#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTRL1_ARPEN_SET ((uint16_t)0x0010) +#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080) +#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTRL2_DMAEN_SET ((uint16_t)0x0800) +#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTRL2_DMALAST_SET ((uint16_t)0x1000) +#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADDR0_SET ((uint16_t)0x0001) +#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_DUALEN_SET ((uint16_t)0x0001) +#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000) + +/* I2C CHCFG mask */ +#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_MASK ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define INTEN_MASK ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @addtogroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + */ +void I2C_DeInit(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct pointer to a I2C_InitType structure that + * contains the configuration information for the specified I2C peripheral. + */ +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint16_t tmpregister = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksType rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed)); + assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode)); + assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle)); + assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable)); + assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode)); + + /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/ + /* Get the I2Cx CTRL2 value */ + tmpregister = I2Cx->CTRL2; + /* Clear frequency FREQ[5:0] bits */ + tmpregister &= CTRL2_CLKFREQ_RESET; + /* Get pclk1 frequency value */ + RCC_GetClocksFreqValue(&rcc_clocks); + pclk1 = rcc_clocks.Pclk1Freq; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpregister |= freqrange; + /* Write to I2Cx CTRL2 */ + I2Cx->CTRL2 = tmpregister; + + /*---------------------------- I2Cx CHCFG Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TMRISE */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + /* Reset tmpregister value */ + /* Clear F/S, DUTY and CHCFG[11:0] bits */ + tmpregister = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->ClkSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1)); + /* Test if CHCFG value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpregister |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TMRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + // else if((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <= + // 400000)*/ + else + { + if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3)); + } + else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_FMDUTYCYCLE_16_9; + } + + /* Test if CHCFG value is under 0x1*/ + if ((result & CLKCTRL_CLKCTRL_SET) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET); + /* Set Maximum Rise Time for fast mode */ + // if (I2C_InitStruct->ClkSpeed <= 400000) + { + I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + // else//add test + //{ + // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1); + //} + } + /* Write to I2Cx CHCFG */ + I2Cx->CLKCTRL = tmpregister; + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + + /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/ + /* Get the I2Cx CTRL1 value */ + tmpregister = I2Cx->CTRL1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to BusMode value */ + /* Set ACK bit according to AckEnable value */ + tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable); + /* Write to I2Cx CTRL1 */ + I2Cx->CTRL1 = tmpregister; + + /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized. + */ +void I2C_InitStruct(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the ClkSpeed member */ + I2C_InitStruct->ClkSpeed = 5000; + /* Initialize the BusMode member */ + I2C_InitStruct->BusMode = I2C_BUSMODE_I2C; + /* Initialize the FmDutyCycle member */ + I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2; + /* Initialize the OwnAddr1 member */ + I2C_InitStruct->OwnAddr1 = 0; + /* Initialize the AckEnable member */ + I2C_InitStruct->AckEnable = I2C_ACKDIS; + /* Initialize the AddrMode member */ + I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CTRL2 |= CTRL2_DMAEN_SET; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CTRL2 &= CTRL2_DMAEN_RESET; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CTRL2 |= CTRL2_DMALAST_SET; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CTRL2 &= CTRL2_DMALAST_RESET; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL1 |= CTRL1_START_SET; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL1 &= CTRL1_START_RESET; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CTRL1 |= CTRL1_STOP_SET; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CTRL1 &= CTRL1_STOP_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CTRL1 |= CTRL1_ACK_SET; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CTRL1 &= CTRL1_ACK_RESET; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the 7bit I2C own address2. + */ +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address) +{ + uint16_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpregister = I2Cx->OADDR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpregister &= OADDR2_ADDR2_RESET; + + /* Set I2Cx Own address2 */ + tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OADDR2 = tmpregister; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OADDR2 |= OADDR2_DUALEN_SET; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OADDR2 &= OADDR2_DUALEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable generall call */ + I2Cx->CTRL1 |= CTRL1_GCEN_SET; + } + else + { + /* Disable generall call */ + I2Cx->CTRL1 &= CTRL1_GCEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_BUF Buffer interrupt mask + * @arg I2C_INT_EVENT Event interrupt mask + * @arg I2C_INT_ERR Error interrupt mask + * @param Cmd new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_I2C_CFG_INT(I2C_IT)); + + if (Cmd != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CTRL2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CTRL2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Data Byte to be transmitted.. + */ +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Write in the DAT register the data to be sent */ + I2Cx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The value of the received data. + */ +uint8_t I2C_RecvData(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->DAT; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the slave address which will be transmitted + * @param I2C_Direction specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_DIRECTION_SEND Transmitter mode + * @arg I2C_DIRECTION_RECV Receiver mode + */ +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_DIRECTION_SEND) + { + /* Set the address bit0 for read */ + Address |= OADDR1_ADDR0_SET; + } + else + { + /* Reset the address bit0 for write */ + Address &= OADDR1_ADDR0_RESET; + } + /* Send the address */ + I2Cx->DAT = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_REG_CTRL1 CTRL1 register. + * @arg I2C_REG_CTRL2 CTRL2 register. + * @arg I2C_REG_OADDR1 OADDR1 register. + * @arg I2C_REG_OADDR2 OADDR2 register. + * @arg I2C_REG_DAT DAT register. + * @arg I2C_REG_STS1 STS1 register. + * @arg I2C_REG_STS2 STS2 register. + * @arg I2C_REG_CLKCTRL CHCFG register. + * @arg I2C_REG_TMRISE TMRISE register. + * @return The value of the read register. + */ +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_REG(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t*)tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CTRL1 |= CTRL1_SWRESET_SET; + } + else + { + /* Peripheral not under reset */ + I2Cx->CTRL1 &= CTRL1_SWRESET_RESET; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACK_POS_NEXT) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last + * received byte. + * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_ConfigPecLocation() + * but is intended to be used in I2C mode while I2C_ConfigPecLocation() + * is intended to used in SMBUS mode. + * + */ +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POS(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACK_POS_NEXT) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CTRL1 |= I2C_NACK_POS_NEXT; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBALERT_LOW SMBAlert pin driven low + * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high + */ +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBALERT_LOW) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CTRL1 |= I2C_SMBALERT_LOW; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CTRL1 &= I2C_SMBALERT_HIGH; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CTRL1 |= CTRL1_PEC_SET; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CTRL1 &= CTRL1_PEC_RESET; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC + * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_ConfigNackLocation() + * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation() + * is intended to used in I2C mode. + * + */ +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POS(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PEC_POS_NEXT) + { + /* Next byte in shift register is PEC */ + I2Cx->CTRL1 |= I2C_PEC_POS_NEXT; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= CTRL1_PECEN_SET; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= CTRL1_PECEN_RESET; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The PEC value. + */ +uint8_t I2C_GetPec(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->STS2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CTRL1 |= CTRL1_ARPEN_SET; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CTRL1 &= CTRL1_ARPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param FmDutyCycle specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2 + * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9 + */ +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle)); + if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9; + } +} + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlag() function. + * The returned value could be compared to events already defined in the + * library (n32l40x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * n32l40x_i2c.h file. + * + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_DATA_RECVD EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2 + * @arg I2C_EVT_SLAVE_DATA_SENDED EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3 + * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2 + * @arg I2C_EVT_SLAVE_STOP_RECVD EV4 + * @arg I2C_EVT_MASTER_MODE_FLAG EV5 + * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7 + * @arg I2C_EVT_MASTER_DATA_SENDING EV8 + * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2 + * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32l40x_i2c.h file. + * + * @return An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_EVT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32l40x_i2c.h file. + * + * @return The last event + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode) + * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode) + * @arg I2C_FLAG_TRF Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY Bus busy flag + * @arg I2C_FLAG_MSMODE Master/Slave flag + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BYTEF Byte transfer finished flag + * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if (i2creg != 0) + { + /* Get the I2Cx STS1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx STS2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx STS2 register address */ + i2cxbase += 0x18; + } + + if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation + * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the + * second byte of the address in DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetFlag()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 + * register (I2C_GetFlag()) followed by a write operation to I2C_DAT + * register (I2C_SendData()). + */ +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert flag + * @arg I2C_INT_TIMOUT Timeout or Tlow error flag + * @arg I2C_INT_PECERR PEC error in reception flag + * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure flag + * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_INT_BUSERR Bus error flag + * @arg I2C_INT_TXDATE Data register empty flag (Transmitter) + * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_INT_STOPF Stop detection flag (Slave mode) + * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_INT_BYTEF Byte transfer finished flag + * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_INT_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_IT (SET or RESET). + */ +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_INT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2)); + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert interrupt + * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt + * @arg I2C_INT_PECERR PEC error in reception interrupt + * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt + * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode) + * @arg I2C_INT_BUSERR Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second + * byte of the address in I2C_DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_DAT register (I2C_SendData()). + */ +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_INT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_iwdg.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_iwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..3553f3647346cd04a415367d901e3581775fe1ce --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_iwdg.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_iwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_iwdg.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @addtogroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KEY register bit mask */ +#define KEY_ReloadKey ((uint16_t)0xAAAA) +#define KEY_EnableKey ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers + */ +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE(IWDG_WriteAccess)); + IWDG->KEY = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4 + * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8 + * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16 + * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32 + * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64 + * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128 + * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256 + */ +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler)); + IWDG->PREDIV = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + */ +void IWDG_CntReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RELV = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_ReloadKey(void) +{ + IWDG->KEY = KEY_ReloadKey; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_Enable(void) +{ + IWDG->KEY = KEY_EnableKey; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_PVU_FLAG Prescaler Value Update on going + * @arg IWDG_CRVU_FLAG Reload Value Update on going + * @return The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lcd.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..c5a7f8eb1c0f929140f8a0c1c6b1a5f73da24af0 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lcd.c @@ -0,0 +1,406 @@ +/***************************************************************************** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* **************************************************************************** +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* Nations' name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ + +/** + * @file n32l40x_lcd.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#include "n32l40x_lcd.h" + +/** @addtogroup N32L40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LCD + * @brief LCD driver modules + * @{ + */ + +/** @addtogroup LCD_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LCD_Private_Defines + * @{ + */ + + +/** + * @} + */ + +/** + * @brief Initialize the LCD peripheral according to the specified parameters + * in the LCD_InitStruct. + * @param LCD_InitStructure LCD initialize structure parameters + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure ) +{ + uint32_t tmp, timeout; + + /* Check function parameters */ + assert_param(IS_LCD_BIAS(LCD_InitStructure->Bias)); + assert_param(IS_LCD_BLINKFREQ(LCD_InitStructure->BlinkFreq)); + assert_param(IS_LCD_BLINKMODE(LCD_InitStructure->BlinkMode)); + assert_param(IS_LCD_CONTRASTLEVEL(LCD_InitStructure->Contrast)); + assert_param(IS_LCD_DEADTIME(LCD_InitStructure->DeadTime)); + assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider)); + assert_param(IS_LCD_DUTY(LCD_InitStructure->Duty)); + assert_param(IS_LCD_HIGHDRIVE(LCD_InitStructure->HighDrive)); + assert_param(IS_LCD_HIGHDRIVEBUFFER(LCD_InitStructure->HighDriveBuffer)); + assert_param(IS_LCD_MUXSEGMENT(LCD_InitStructure->MuxSegment)); + assert_param(IS_LCD_PRESCALER(LCD_InitStructure->Prescaler)); + assert_param(IS_LCD_PULSEONDURATION(LCD_InitStructure->PulseOnDuration)); + assert_param(IS_LCD_VOLTAGESOURCE(LCD_InitStructure->VoltageSource)); + + /*Disable LCD controller*/ + __LCD_DISABLE(); + + /*During 1/8 duty mode, 1/4 bias is not supported,use 1/3 bias instead*/ + if(LCD_DUTY_1_8 == LCD_InitStructure->Duty) + { + if(LCD_BIAS_1_4 == LCD_InitStructure->Bias) + LCD_InitStructure->Bias = LCD_BIAS_1_3; + } + + /* set the bits of LCD_CTRL register with corresonding parameters */ + tmp = 0; + tmp |= LCD_InitStructure->HighDriveBuffer; + tmp |= LCD_InitStructure->MuxSegment; + tmp |= LCD_InitStructure->Bias; + tmp |= LCD_InitStructure->Duty; + tmp |= LCD_InitStructure->VoltageSource; + LCD->CTRL = tmp; + + /*If High driver enable, PulseOnDuration must be LCD_PulseOnDuration_1*/ + if(LCD_InitStructure->HighDrive == LCD_HIGHDRIVE_ENABLE) + { + LCD_InitStructure->PulseOnDuration = LCD_PULSEONDURATION_1; + } + + /* set the bits of LCD_FCTRL register with corresonding parameters */ + tmp = 0; + tmp |= LCD_InitStructure->Prescaler; + tmp |= LCD_InitStructure->Divider; + tmp |= LCD_InitStructure->BlinkMode; + tmp |= LCD_InitStructure->BlinkFreq; + tmp |= LCD_InitStructure->Contrast; + tmp |= LCD_InitStructure->DeadTime; + tmp |= LCD_InitStructure->HighDrive; + tmp |= LCD_InitStructure->PulseOnDuration; + LCD->FCTRL = tmp; + + /*Clear LCD display ram, and set the update request flag*/ + LCD_RamClear(); + __LCD_UPDATE_REQUEST(); + + /*Enable LCD controller*/ + __LCD_ENABLE(); + + /*Check the LCD ENSTS status*/ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_ENSTS))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_ENSTS; + } + + /*Wait VLCD stable*/ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_RDY))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_RDY; + } + + return (LCD_WaitForSynchro()); +} + +/** + * @brief DeInitialize the LCD peripheral + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,DISABLE); +} + +/** + * @brief Config the clock source of LCD + * @param LCD_ClkSource specifies the clock source of LCD + * This parameter can be one of the following values: + * @arg LCD_CLK_SRC_LSI: LCD clock source is LSI + * @arg LCD_CLK_SRC_LSE: LCD clock source is LSE,and LSE is oscillator + * @arg LCD_CLK_SRC_LSE_BYPASS: LCD clock source is LSE,and LSE is extennal clock + * @arg LCD_CLK_SRC_HSE_DIV32: LCD clock source is HSE/32,and HSE is oscillator + * @arg LCD_CLK_SRC_HSE_BYPASS_DIV32: LCD clock source is HSE/32,and HSE is extennal clock + * @retval LCD error code + * note: LCD clock is the same with RTC + */ +LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(LCD_CLK_SRC_LSI == LCD_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + if(++timeout >LCD_TIME_OUT) + return LCD_ERROR_CLK; + } + } + else if((LCD_CLK_SRC_LSE==LCD_ClkSource)||(LCD_CLK_SRC_LSE_BYPASS==LCD_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET) + { + RCC_ConfigLse((LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)),0x28); + timeout = 0; + while(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + if(++timeout >LCD_TIME_OUT) + return LCD_ERROR_CLK; + } + } + } + else if((LCD_CLK_SRC_HSE_DIV32==LCD_ClkSource)||(LCD_CLK_SRC_HSE_BYPASS_DIV32==LCD_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF)==RESET) + { + RCC_ConfigHse(LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)); + if(RCC_WaitHseStable()!=SUCCESS) + return LCD_ERROR_CLK; + } + } + else + return LCD_ERROR_PARAM; + + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100; + + /*set LSI as RTC clock source*/ + RCC_ConfigRtcClk(LCD_ClkSource & RCC_LDCTRL_RTCSEL); + + /*Enable RTC clk*/ + RCC_EnableRtcClk(ENABLE); + + /*Enable LCD clk*/ + RCC_EnableRETPeriphClk(RCC_RET_PERIPH_LCD,ENABLE); + + return LCD_ERROR_OK; +} + +/** + * @brief Clear LCD ram register. + * @param None + * @retval None + */ +void LCD_RamClear(void) +{ + uint32_t counter; + + /*Clear lcd ram*/ + for(counter = LCD_RAM1_COM0; counter <= LCD_RAM2_COM7; counter++) + { + LCD->RAM_COM[counter] = 0x0U; + } +} + +/** + * @brief Update Display request. + * @param None + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void) +{ + uint32_t timeout; + + /*Clear UDD flag*/ + __LCD_CLEAR_FLAG(LCD_FLAG_UDD_CLEAR); + + /* set update display request bit*/ + __LCD_UPDATE_REQUEST(); + + /* Wait update complete */ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_UDD))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_UDD; + } + + return LCD_ERROR_OK; +} + +/** + * @brief write to the lcd ram register. + * @param RAMRegisterIndex RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMRegisterMask specifies the LCD RAM Register Data Mask. + * @param RAMData value written to RAM. + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData) +{ + uint32_t timeout; + + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + MODIFY_REG(LCD->RAM_COM[RAMRegisterIndex], ~(RAMRegisterMask), RAMData &(~(RAMRegisterMask))); + + return LCD_ERROR_OK; + +} + +/** + * @brief set some bits of lcd ram register. + * @param RAMRegisterIndex: RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMData: value to be set + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData) +{ + uint32_t timeout; + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + SET_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData); + return LCD_ERROR_OK; +} + +/** + * @brief clear some bits of lcd ram register. + * @param RAMRegisterIndex: RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMData: value to be clear + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData) +{ + uint32_t timeout; + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + CLEAR_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData); + return LCD_ERROR_OK; +} + + +/** + * @brief Wait until the LCD FCTRL register is synchronized in the LCDCLK domain. + * This function must be called after any write operation to LCD_FCTRL register. + * @param RAMData: None + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_WaitForSynchro(void) +{ + uint32_t timeout; + + /* Loop until FCRSF flag is set */ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_FCRSF))) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_FCRSF; + } + } + + return LCD_ERROR_OK; +} + +/** +* @} +*/ +/** +* @} +*/ + + + diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lptim.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lptim.c new file mode 100644 index 0000000000000000000000000000000000000000..d632271a97c93f33222ab5b1135d132593cd5c38 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lptim.c @@ -0,0 +1,1258 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* + * ----------------------------------------------------------------------------- + */ + +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32l40x_lptim.c + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "n32l40x_lptim.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @defgroup LPTIM + * @brief LPTIM driver modules + * @{ + */ + +/** @defgroup LPTIM_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ +//#define LPTIM +//#if defined (LPTIM)//LPTIM + +/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +void LPTIM_DeInit(LPTIM_Module* LPTIMx) +{ + if (LPTIMx == LPTIM) + { + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE); + } +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval None + */ +void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM; + LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + + /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFG, + (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note + * @retval None + */ +void LPTIM_Disable(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_Enable(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LPTIM_StartCounter\n + * CR SNGSTRT LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode); +} + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag be set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CMP register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMPOK flag be set, will + * lead to unpredictable results. + * @rmtoll CMP CMP LPTIM_SetCompare + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CMP CMP LPTIM_GetCompare + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + */ +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN)); +} + +/** + * @brief Configure the LPTIM instance output (LPTIMx_OUT) + * @note This function must be called when the LPTIM instance is disabled. + * @note Regarding the LPTIM output polarity the change takes effect + * immediately, so the output default value will change immediately after + * the polarity is re-configured, even before the timer is enabled. + * @rmtoll CFG WAVE LPTIM_ConfigOutput\n + * CFG WAVPOL LPTIM_ConfigOutput + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity); +} + +/** + * @brief Set waveform shape + * @rmtoll CFG WAVE LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFG WAVE LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE)); +} + +/** + * @brief Set output polarity + * @rmtoll CFG WAVPOL LPTIM_SetPolarity + * @param LPTIMx Low-Power Timer instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity); +} + +/** + * @brief Get actual output polarity + * @rmtoll CFG WAVPOL LPTIM_GetPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + */ +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL)); +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFG PRESC LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + * @retval None + */ +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFG PRESC LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + */ +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFG TIMOUT LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFG TIMOUT LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG TRIGEN LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_TrigSw(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n + * CFG TRGFLT LPTIM_ConfigTrigger\n + * CFG TRIGEN LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + * @param Filter This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + */ +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + */ +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKSEL LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFG CKSEL LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + */ +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFG CKFLT LPTIM_ConfigClock\n + * CFG CKPOL LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFG CKPOL LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFG CKFLT LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + */ +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKPOL LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFG CKPOL LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + */ +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC); +} +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG ENC LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag (CMPMCF) + * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF); +} + +/** + * @brief Inform application whether a compare match interrupt has occurred. + * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occured. + * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMPOKCF). + * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR UP LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Disable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. + * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. + * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx) +{ + return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL); +} + +/** + * @} + */ + + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ + diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lpuart.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lpuart.c new file mode 100644 index 0000000000000000000000000000000000000000..6e157a0f108750a3d0537752afe528159b0d5cc1 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_lpuart.c @@ -0,0 +1,536 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_lpuart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_lpuart.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @brief LPUART driver modules + * @{ + */ + +/** @addtogroup LPUART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Defines + * @{ + */ + +#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */ + +#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */ +#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */ + +#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */ +#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */ +#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */ +#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */ +#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */ +#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */ +#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */ +#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */ +#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the LPUART peripheral registers to their default reset values. + */ +void LPUART_DeInit(void) +{ + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE); +} + +/** + * @brief Initializes the LPUART peripheral according to the specified + * parameters in the LPUART_InitStruct. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * that contains the configuration information for the specified LPUART + * peripheral. + */ +void LPUART_Init(LPUART_InitType* LPUART_InitStruct) +{ + uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00; + RCC_ClocksType RCC_ClocksStatus; + + /* Check the parameters */ + // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode)); + assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold)); + assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl)); + + // 时钟源判断，波特率范围 + + /*---------------------------- LPUART CTRL Configuration -----------------------*/ + tmpregister = LPUART->CTRL; + /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */ + tmpregister &= CTRL_CLR_MASK; + /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */ + /* Set PCDIS and PSEL bits according to Parity value */ + /* Set the TRS bit according to Mode */ + /* Set RTS_THSEL[1:0] bits according to RtsThrehold */ + /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */ + tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl; + /* Write to LPUART CTRL */ + LPUART->CTRL = (uint16_t)tmpregister; + + /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/ + /* Configure the LPUART Baud Rate -------------------------------------------*/ + clocksrc = RCC_GetLPUARTClkSrc(); + if (clocksrc == RCC_LPUARTCLK_SRC_LSE) + { + apbclock = 0x8000; // 32.768kHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_HSI) + { + apbclock = 0xF42400; // 16MHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.SysclkFreq; + } + else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = apbclock / (LPUART_InitStruct->BaudRate); + + /* Configure sampling method */ + if(integerdivider <= 10) + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B); + } + else + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B); + } + + /* Check baudrate */ + assert_param(IS_LPUART_BAUDRATE(integerdivider)); + /* Write to LPUART BRCFG1 */ + LPUART->BRCFG1 = (uint16_t)integerdivider; + + /* Determine the fractional part */ + fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate); + + tmpregister = 0x00; + tmpdivider = fractionaldivider; + /* Implement the fractional part in the register */ + for( i = 0; i < 8; i++) + { + lastdivider = tmpdivider; + tmpdivider = lastdivider + fractionaldivider; + if((tmpdivider / 10000) ^ (lastdivider / 10000)) + { + tmpregister |= (0x01 << i); + } + } + /* Write to LPUART BRCFG2 */ + LPUART->BRCFG2 = (uint8_t)tmpregister; +} + +/** + * @brief Fills each LPUART_InitStruct member with its default value. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * which will be initialized. + */ +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct) +{ + /* LPUART_InitStruct members default value */ + LPUART_InitStruct->BaudRate = 9600; + LPUART_InitStruct->Parity = LPUART_PE_NO; + LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX; + LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU; + LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE; +} + +/** + * @brief Flushes Receiver FIFO. + */ +void LPUART_FlushRxFifo(void) +{ + /* Clear LPUART Flush Receiver FIFO */ + LPUART->CTRL |= CTRL_FLUSH_SET; + while(LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET) + { + } + LPUART->CTRL &= CTRL_FLUSH_RESET; +} + +/** + * @brief Enables or disables the specified LPUART interrupts. + * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @param Cmd new state of the specified LPUART interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CFG_INT(LPUART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + LPUART->INTEN |= (uint8_t)LPUART_INT; + } + else + { + LPUART->INTEN &= (uint8_t)(~LPUART_INT); + } +} + +/** + * @brief Enables or disables the LPUART's DMA interface. + * @param LPUART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg LPUART_DMAREQ_TX LPUART DMA transmit request + * @arg LPUART_DMAREQ_RX LPUART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL |= LPUART_DMAReq; + } + else + { + /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq); + } +} + +/** + * @brief Selects the LPUART WakeUp method. + * @param LPUART_WakeUpMethod specifies the LPUART wakeup method. + * This parameter can be one of the following values: + * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection + * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection + * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte + * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame + */ +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod)); + + LPUART->CTRL &= CTRL_WUSTP_MASK; + LPUART->CTRL |= LPUART_WakeUpMethod; +} + +/** + * @brief Enables or disables LPUART Wakeup in STOP2 mode. + * @param Cmd new state of the LPUART Wakeup in STOP2 mode. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableWakeUpStop(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */ + LPUART->CTRL |= CTRL_WUSTP_SET; + } + else + { + /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */ + LPUART->CTRL &= CTRL_WUSTP_RESET; + } +} + +/** + * @brief Selects the LPUART Sampling method. + * @param LPUART_SamplingMethod specifies the LPAURT sampling method. + * This parameter can be one of the following values: + * @arg LPUART_SMPCNT_3B 3 Sample bit + * @arg LPUART_SMPCNT_1B 1 Sample bit + */ +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod)); + + LPUART->CTRL &= CTRL_SMPCNT_MASK; + LPUART->CTRL |= LPUART_SamplingMethod; +} + +/** + * @brief Enables or disables LPUART Loop Back Self-Test. + * @param Cmd new state of the LPUART Loop Back Self-Test. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableLoopBack(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */ + LPUART->CTRL |= CTRL_LOOPBACK_SET; + } + else + { + /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */ + LPUART->CTRL &= CTRL_LOOPBACK_RESET; + } +} + +/** + * @brief Transmits single data through the LPUART peripheral. + * @param Data the data to transmit. + */ +void LPUART_SendData(uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DATA(Data)); + + /* Transmit Data */ + LPUART->DAT = (Data & (uint8_t)0xFF); +} + +/** + * @brief Returns the most recent received data by the LPUART peripheral. + * @return The received data. + */ +uint8_t LPUART_ReceiveData(void) +{ + /* Receive Data */ + return (uint8_t)(LPUART->DAT & (uint8_t)0xFF); +} + +/** + * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode. + * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode. + */ +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData) +{ + LPUART->WUDAT = LPUART_WakeUpData; +} + +/** + * @brief Checks whether the specified LPUART flag is set or not. + * @param LPUART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + * @return The new state of LPUART_FLAG (SET or RESET). + */ +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_FLAG(LPUART_FLAG)); + + if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the LPUART's pending flags. + * @param LPUART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + */ +void LPUART_ClrFlag(uint16_t LPUART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG)); + + LPUART->STS = (uint16_t)LPUART_FLAG; +} + +/** + * @brief Checks whether the specified LPUART interrupt has occurred or not. + * @param LPUART_INT specifies the LPUART interrupt source to check. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @return The new state of LPUART_INT (SET or RESET). + */ +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_GET_INT(LPUART_INT)); + + /* Get the interrupt position */ + itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + itmask &= LPUART->INTEN; + + bitpos = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT){ + bitpos = (bitpos << 0x01); + } + bitpos &= LPUART->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the LPUART's interrupt pending bits. + * @param LPUART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + */ +void LPUART_ClrIntPendingBit(uint16_t LPUART_INT) +{ + uint16_t itmask = 0x00; + /* Check the parameters */ + assert_param(IS_LPUART_CLR_INT(LPUART_INT)); + + itmask = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT) + { + itmask = (itmask << 0x01); + } + LPUART->STS = (uint16_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_opamp.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_opamp.c new file mode 100644 index 0000000000000000000000000000000000000000..33aa6bb63dbe1236704f2f486e6ec3bd83db5f28 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_opamp.c @@ -0,0 +1,198 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_opamp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_opamp.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @brief OPAMP driver modules + * @{ + */ + +/** @addtogroup OPAMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the OPAMP peripheral registers to their default reset values. + */ +void OPAMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE); +} +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct) +{ + OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6; + OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2; + OPAMP_InitStruct->HighVolRangeEn = ENABLE; + OPAMP_InitStruct->TimeAutoMuxEn = DISABLE; + OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN; +} +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + if(OPAMPx == OPAMP2) + SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL); + SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK); + if(OPAMP_InitStruct->HighVolRangeEn==ENABLE) + SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK); + else + ClrBit(tmp,OPAMP_CS_RANGE_MASK); + if(OPAMP_InitStruct->TimeAutoMuxEn==ENABLE) + SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK); + else + ClrBit(tmp,OPAMP_CS_TCMEN_MASK); + SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK); + *pCs = tmp; +} +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_EN_MASK); + else + ClrBit(*pCs, OPAMP_CS_EN_MASK); +} + +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK); + *pCs = tmp; +} +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false; +} +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_CALON_MASK); + else + ClrBit(*pCs, OPAMP_CS_CALON_MASK); +} +// Lock see @OPAMP_LOCK +void OPAMP_SetLock(uint32_t Lock) +{ + OPAMP->LOCK = Lock; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_pwr.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_pwr.c new file mode 100644 index 0000000000000000000000000000000000000000..628661a4d4197d7aeedf0f9cb6b1852dbc55d3de --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_pwr.c @@ -0,0 +1,569 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_pwr.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_pwr.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @addtogroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of DBKP bit */ +#define CTRL_OFFSET (PWR_OFFSET + 0x00) +#define DBKP_BITN 0x08 +#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4)) + +/* Alias word address of PVDEN bit */ +#define PVDEN_BITN 0x04 +#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of WKUPEN bit */ +#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04) +#define WKUPEN_BITN 0x08 +#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + + +void SetSysClock_MSI(void); +/** + * @} + */ + +/** @addtogroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + */ +void PWR_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param Cmd new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_BackupAccessEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd; +} +/** + * @brief MR voltage selection. + * @param voltage value: 1.0V and 1.1V. + * This parameter can be: MR_1V0 or MR_1V1. + */ +void PWR_MRconfig(uint8_t voltage) +{ + uint32_t tmpreg = 0; + + tmpreg = PWR->CTRL1; + /* Clear MRSEL bits */ + tmpreg &= (~PWR_CTRL1_MRSELMASK); + /* Set voltage*/ + tmpreg |= (uint32_t)(voltage << 9); + PWR->CTRL1 = tmpreg; +} +/** + * @brief Get MR voltage value. + * @param voltage value: 1.0V and 1.1V. + * @return The value of voltage. + */ +uint8_t GetMrVoltage(void) +{ + uint8_t tmp = 0; + + tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);//2bits + return tmp ; +} +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param Cmd new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_PvdEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; //Can not enable the PVD bit + PWR->CTRL2 |= Cmd; + +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V + * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V + * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V + * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V + * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V + * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V + * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V + * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT) + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpregister = PWR->CTRL2; + /* Clear PLS[7:5] bits */ + tmpregister &= (~PWR_CTRL2_PLSMASK); + /* Set PRS[7:5] bits according to PWR_PVDLevel value */ + tmpregister |= PWR_PVDLevel; + /* Store the new value */ + PWR->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param Pin: which PIN select to wakeup. + * This parameter can be one of the following values: + * @arg WAKEUP_PIN0 + * @arg WAKEUP_PIN1 + * @arg WAKEUP_PIN2 + * @param Cmd new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd) +{ + uint32_t Temp = 0; + Temp = PWR->CTRL3; + if(ENABLE==Cmd) + { + Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN)); + Temp |= (WKUP_Pin); + PWR->CTRL3 = Temp; + } + else + { + Temp &= (~(WKUP_Pin)); + PWR->CTRL3 = Temp; + } +} + +/** + * @brief Enters SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + + /* CLEAR SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); + + /* Select SLEEPONEXIT mode entry --------------------------------------------------*/ + if(SLEEPONEXIT == 1) + { + /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } + else if(SLEEPONEXIT == 0) + { + /* Sleep-now */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT); + } + + /* Select SLEEP mode entry --------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + + +/** + * @brief Enters STOP2 mode. + * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction + * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET + */ +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + /* Wait MR Voltage Adjust Complete */ + while((PWR->STS2 &0X2) != 2); + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= RetentionMode; + PWR->CTRL3 = tmpreg; + /* Select the regulator state in STOP2 mode ---------------------------------*/ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set stop2 mode select */ + tmpreg |= PWR_CTRL1_STOP2; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + + +/** + * @brief Enters Low power run mode. + * @param + * @arg + * @arg + * @retval None + */ +void PWR_EnterLowPowerRunMode(void) +{ + uint32_t tmpreg = 0; + SetSysClock_MSI(); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + //config FLASH enter the low power voltage mode + FLASH->AC |= FLASH_AC_LVMEN; + while((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + _SetLprunSramVoltage(0); + _SetBandGapMode(0); + _SetPvdBorMode(0); + /* Select the regulator state in LPRUN mode ---------------------------------*/ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set lpr to run the main power domain*/ + tmpreg |= PWR_CTRL1_LPREN; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + while((PWR->STS2 &PWR_STS2_LPRUNF) != 0);//LPRCNT flag ready +} + +/** + * @brief Enters Low power run mode. + * @retval None + */ +void PWR_ExitLowPowerRunMode(void) +{ + PWR->CTRL1 &= ~PWR_CTRL1_LPREN; + _SetLprunSwitch(3); + while((PWR->STS2 &PWR_STS2_MRF) != PWR_STS2_MRF); + while((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + FLASH->AC &= ~FLASH_AC_LVMEN; //clear LVMREQ + while((FLASH->AC &FLASH_AC_LVMF) != 0); //wait LVE is deasserted by polling the LVMVLD bit + _SetPvdBorMode(1); + _SetBandGapMode(1); + _SetLprunSramVoltage(1); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + _SetLprunSwitch(2); + while((PWR->STS2 &0X2) != 0) // wait MF to be 0 first + { + } + while((PWR->STS2 &0X2) != 2) // wait MF to be 1 then + { + } +} + +/** + * @brief Enters LP_SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + PWR_EnterLowPowerRunMode(); + PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry); +} + + /** + * @brief Enters STANDBY mode. + * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction + * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention + * @retval None + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret) +{ + uint32_t tmpreg; + /* Clear Wake-up flag */ + PWR->STSCLR |= PWR_STSCLR_CLRWKUP0; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP1; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP2; + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= Sam2Ret; + PWR->CTRL3 = tmpreg; + + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Select STANDBY mode */ + tmpreg |= PWR_CTRL1_STANDBY; + PWR->CTRL1 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Select STANDBY mode entry --------------------------------------------------*/ + if(PWR_STANDBYEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_WKUP0_FLAG/PWR_WKUP1_FLAG/PWR_WKUP2_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + * @arg PWR_LPRUN_FLAG: low power work flag + * @arg PWR_MR_FLAG: MR work statue flag + * @arg PWR_PVDO_FLAG: PVD output flag + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + if(STS == 1) + { + if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + } + else + { + if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->STSCLR |= PWR_FLAG ; +} + + +/** + * @brief set system clock with MSI. + * @param void. + */ + +void SetSysClock_MSI(void) +{ + RCC_DeInit(); + + if(RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD)) + { + /* Enable MSI and Config Clock */ + RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M); + /* Waits for MSI start-up */ + while(SUCCESS != RCC_WaitMsiStable()); + } + + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN); + + /* Select MSI as system clock source */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI); + + /* Wait till MSI is used as system clock source */ + while (RCC_GetSysclkSrc() != 0x00) + { + } + + /* Flash 0 wait state */ + //FLASH_SetLatency(FLASH_LATENCY_0); + + /* HCLK = SYSCLK */ + RCC_ConfigHclk(RCC_SYSCLK_DIV1); + + /* PCLK2 = HCLK */ + RCC_ConfigPclk2(RCC_HCLK_DIV1); + + /* PCLK1 = HCLK */ + RCC_ConfigPclk1(RCC_HCLK_DIV1); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rcc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rcc.c new file mode 100644 index 0000000000000000000000000000000000000000..f017ec4e6e4523a2a1763d5991917d9dd30f3216 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rcc.c @@ -0,0 +1,1953 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_rcc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @addtogroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of HSIEN bit */ +#define CTRL_OFFSET (RCC_OFFSET + 0x00) +#define HSIEN_BITN 0x00 +#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4)) + +/* Alias word address of PLLEN bit */ +#define PLLEN_BITN 0x18 +#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4)) + +/* Alias word address of CLKSSEN bit */ +#define CLKSSEN_BITN 0x13 +#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4)) + +/* --- CFG Register ---*/ + +/* Alias word address of USBPRES bit */ +#define CFG_OFFSET (RCC_OFFSET + 0x04) + +#define USBPRES_BITN 0x16 +#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4)) + +#define USBPRE_Bit1Number 0x17 +#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4)) + +/* --- CLKINT Register ---*/ + +#define CLKINT_OFFSET (RCC_OFFSET + 0x08) + +/* Alias word address of LSIRDIF bit */ +#define LSIRDIF_BITN 0x00 +#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4)) + +/* --- LDCTRL Register ---*/ + +/* Alias word address of LSECLKSSEN bit */ +#define LSECLKSSEN_BITN 0x03 +#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4)) + +/* Alias word address of RTCEN bit */ +#define LDCTRL_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BITN 0x0F +#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4)) + +/* Alias word address of LDSFTRST bit */ +#define LDSFTRST_BITN 0x10 +#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of LSIEN bit */ +#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24) +#define LSIEN_BITNUMBER 0x00 +#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4)) + +/* Alias word address of MSIEN bit */ +#define MSIEN_BITNUMBER 0x02 +#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF) +#define CTRL_HSEBP_SET ((uint32_t)0x00040000) +#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF) +#define CTRL_HSEEN_SET ((uint32_t)0x00010000) +#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83) +#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE) +#define CTRL_HSIEN_SET ((uint32_t)0x00000001) + +/* CTRLSTS register bit mask */ +#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF) +#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB) +#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004) + +#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F) +#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */ + +/* CFG register bit mask */ +#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF) + +#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000) +#define CFG_PLLSRC_MASK ((uint32_t)0x00010000) +#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000) +#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C) +#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC) +#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F) +#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0) +#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF) +#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700) +#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF) +#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800) + +/* CFG2 register bit mask */ +#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000) +#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF) +#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000) +#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF) +#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000) +#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF) +#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000) +#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF) +#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0) +#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F) +#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F) +#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0) + +/* CFG3 register bit mask */ +#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) + +/* CTRLSTS register bit mask */ +#define CSR_RMRSTF_SET ((uint32_t)0x01000000) +#define CSR_RMVF_Reset ((uint32_t)0xfeffffff) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CLKINT register(Bits[31:0]) base address */ +#define CLKINT_ADDR ((uint32_t)0x40021008) + +/* LDCTRL register base address */ +#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET) + +/* RDCTRL register bit mask */ +#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007) +#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018) + +/* PLLHSIPRE register bit mask */ +#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001) +#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002) + +#define LSE_TRIMR_ADDR ((uint32_t)0x40001808) + +#define LSE_GM_MASK_VALUE (0x1FF) +#define LSE_GM_MAX_VALUE (0x1FF) +#define LSE_GM_DEFAULT_VALUE (0x1FF) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Variables + * @{ + */ + +static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32}; +static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256}; +static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +/** + * @} + */ + +/** @addtogroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + */ +void RCC_DeInit(void) +{ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFE; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */ + RCC->CFG &= (uint32_t)0xF700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_DISABLE HSE oscillator OFF + * @arg RCC_HSE_ENABLE HSE oscillator ON + * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +void RCC_ConfigHse(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CTRL &= CTRL_HSEEN_RESET; + /* Reset HSEBYP bit */ + RCC->CTRL &= CTRL_HSEBP_RESET; + /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */ + switch (RCC_HSE) + { + case RCC_HSE_ENABLE: + /* Set HSEEN bit */ + RCC->CTRL |= CTRL_HSEEN_SET; + break; + + case RCC_HSE_BYPASS: + /* Set HSEBYP and HSEEN bits */ + RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitHseStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF); + StartUpCounter++; + } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Configures the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSI specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_DISABLE HSI oscillator OFF + * @arg RCC_HSI_ENABLE HSI oscillator ON + */ +void RCC_ConfigHsi(uint32_t RCC_HSI) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_HSI)); + /* Reset HSIEN bit */ + RCC->CTRL &= CTRL_HSIEN_RESET; + /* Configure HSI */ + switch (RCC_HSI) + { + case RCC_HSI_ENABLE: + /* Set HSIEN bit */ + RCC->CTRL |= CTRL_HSIEN_SET; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSI oscillator is stable and ready to use + * - ERROR: HSI oscillator not yet ready + */ +ErrorStatus RCC_WaitHsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSIStatus = RESET; + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF); + StartUpCounter++; + } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue)); + tmpregister = RCC->CTRL; + /* Clear HSITRIM[4:0] bits */ + tmpregister &= CTRL_HSITRIM_MASK; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpregister |= (uint32_t)HSICalibrationValue << 2; + /* Store the new value */ + RCC->CTRL = tmpregister; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableHsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the Multi Speed oscillator (MSI). + * @param RCC_MSI specifies the new state of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_DISABLE MSI oscillator OFF + * @arg RCC_MSI_ENABLE MSI oscillator ON + * @param RCC_MSI_Range specifies the clock of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_RANGE_100K 100KHz + * @arg RCC_MSI_RANGE_200K 200KHz + * @arg RCC_MSI_RANGE_400K 400KHz + * @arg RCC_MSI_RANGE_800K 800KHz + * @arg RCC_MSI_RANGE_1M 1MHz + * @arg RCC_MSI_RANGE_2M 2MHz + * @arg RCC_MSI_RANGE_4M 4MHz + */ +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range) +{ + /* Check the parameters */ + assert_param(IS_RCC_MSI(RCC_MSI)); + assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range)); + /* Set MSIRANGE[2:0] bit */ + RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK; + RCC->CTRLSTS |= RCC_MSI_Range; + /* Configure MSI */ + switch (RCC_MSI) + { + case RCC_MSI_ENABLE: + /* Set MSIEN bit */ + RCC->CTRLSTS |= CTRLSTS_MSIEN_SET; + break; + case RCC_MSI_DISABLE: + /* Reset MSIEN bit */ + RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET; + break; + default: + break; + } +} + +/** + * @brief Waits for MSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: MSI oscillator is stable and ready to use + * - ERROR: MSI oscillator not yet ready + */ +ErrorStatus RCC_WaitMsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus MSIStatus = RESET; + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD); + StartUpCounter++; + } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Multi Speed oscillator (MSI) calibration value. + * @param MSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0xFF. + */ +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue)); + tmpregister = RCC->CTRLSTS; + /* Clear MSITRIM[7:0] bits */ + tmpregister &= CTRLSTS_MSITRIM_MASK; + /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */ + tmpregister |= (uint32_t)MSICalibrationValue << 15; + /* Store the new value */ + RCC->CTRLSTS = tmpregister; +} + +/** + * @brief Enables or disables the Multi Speed oscillator (MSI). + * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableMsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource specifies the PLL entry clock source. + * this parameter can be one of the following values: + * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul specifies the PLL multiplication factor. + * this parameter can be RCC_PLLMul_x where x:[2,32] + * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source. + * this parameter can be one of the following values: + * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry + * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry + */ +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK) +{ + uint32_t tmpregister = 0; + uint32_t pllhsipreregister = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SRC(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK)); + + tmpregister = RCC->CFG; + pllhsipreregister = RCC->PLLHSIPRE; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */ + tmpregister &= CFG_PLL_MASK; + /* Clear PLLHSIPRE, PLLSRCDIV bits */ + pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK)); + /* Set the PLL configuration bits */ + if((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2)) + { + tmpregister |= RCC_PLLMul; + pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK; + } + /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */ + else + { + tmpregister |= RCC_PLLSource | RCC_PLLMul; + pllhsipreregister |= RCC_PLLDIVCLK; + } + /* Store the new value */ + RCC->CFG = tmpregister; + RCC->PLLHSIPRE = pllhsipreregister; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnablePll(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock + * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock + */ +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource)); + tmpregister = RCC->CFG; + /* Clear SW[1:0] bits */ + tmpregister &= CFG_SCLKSW_MASK; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpregister |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Returns the clock source used as system clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: MSI used as system clock + * - 0x04: HSI used as system clock + * - 0x08: HSE used as system clock + * - 0x0C: PLL used as system clock + */ +uint8_t RCC_GetSysclkSrc(void) +{ + return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK + * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512 + */ +void RCC_ConfigHclk(uint32_t RCC_SYSCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK)); + tmpregister = RCC->CFG; + /* Clear HPRE[3:0] bits */ + tmpregister &= CFG_AHBPRES_RESET_MASK; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpregister |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB1 clock = HCLK + * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16 + */ +void RCC_ConfigPclk1(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE1[2:0] bits */ + tmpregister &= CFG_APB1PRES_RESET_MASK; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB2 clock = HCLK + * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16 + */ +void RCC_ConfigPclk2(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE2[2:0] bits */ + tmpregister &= CFG_APB2PRES_RESET_MASK; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RccInt specifies the RCC interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF BOR interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * + * @param Cmd new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_INT(RccInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8); + } + else + { + /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8)); + } +} + +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source + */ +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource)); + + *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource; + *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1; +} + +/** + * @brief Configures the TIM1/8 clock (TIM1/8CLK). + * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM18CLK_SRC_TIM18CLK + * @arg RCC_TIM18CLK_SRC_SYSCLK + */ +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource)); + + tmpregister = RCC->CFG2; + /* Clear TIMCLK_SEL bits */ + tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK; + /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */ + tmpregister |= RCC_TIM18CLKSource; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the RNGCCLK prescaler. + * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler. + * This parameter can be one of the following values: + * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1 + * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2 + * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3 + * ... + * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31 + * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32 + */ +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear RNGCPRE[3:0] bits */ + tmpregister &= CFG2_RNGCPRES_RESET_MASK; + /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */ + tmpregister |= RCC_RNGCCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCx 1M clock (ADC1MCLK). + * @param RCC_ADC1MCLKSource specifies the ADC1M clock source. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_SRC_HSI + * @arg RCC_ADC1MCLK_SRC_HSE + * + * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1 + * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2 + * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3 + * ... + * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31 + * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32 + */ +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource)); + assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */ + tmpregister &= CFG2_ADC1MSEL_RESET_MASK; + tmpregister &= CFG2_ADC1MPRES_RESET_MASK; + /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */ + tmpregister |= RCC_ADC1MCLKSource; + /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */ + tmpregister |= RCC_ADC1MPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK. + * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + * + * @param Cmd specifies the ADCPLLCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable ADCPLLCLK + * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + */ +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + tmpregister = RCC->CFG2; + /* Clear ADCPLLPRES[4:0] bits */ + tmpregister &= CFG2_ADCPLLPRES_RESET_MASK; + + if (Cmd != DISABLE) + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + } + else + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + tmpregister &= RCC_ADCPLLCLK_DISABLE; + } + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + */ +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADCHPRE[3:0] bits */ + tmpregister &= CFG2_ADCHPRES_RESET_MASK; + /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_ADCHCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the TRNG 1M clock (TRNG1MCLK). + * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_SRC_HSI + * @arg RCC_TRNG1MCLK_SRC_HSE + * + * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2 + * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4 + * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6 + * ... + * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60 + * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62 + */ +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource)); + assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler)); + + tmpregister = RCC->CFG3; + /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */ + tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK; + tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK; + /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */ + tmpregister |= RCC_TRNG1MCLKSource; + /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */ + tmpregister |= RCC_TRNG1MPrescaler; + + /* Store the new value */ + RCC->CFG3 = tmpregister; +} + +/** + * @brief Enable/disable TRNG clock (TRNGCLK). + * @param Cmd specifies the TRNGCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable TRNGCLK + * @arg DISABLE disable TRNGCLK + */ +void RCC_EnableTrng1mClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE; + } + else + { + RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE; + } +} + +/** + * @brief Configures the UCDR clock. + * @param RCC_UCDR300MSource specifies the UCDR clock source. + * This parameter can be on of the following values: + * @arg RCC_UCDR300M_SRC_OSC300M + * @arg RCC_UCDR300M_SRC_PLLVCO + * + * @param Cmd enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable UCDR + * @arg DISABLE disable UCDR + */ +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + tmpregister = RCC->CFG3; + /* Clear UCDR300MSEL bits */ + tmpregister &= RCC_UCDR300MSource_MASK; + /* Set UCDR300MSEL bits */ + tmpregister |= RCC_UCDR300MSource; + + /* Store the new value */ + RCC->CFG3 = tmpregister; + + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_UCDR_ENABLE; + } + else + { + RCC->CFG3 &= RCC_UCDR_DISABLE; + } +} + +/** + * @brief Configures the USB Crystal Mode. + * @param RCC_USBXTALESSMode specifies the USB Crystal Mode. + * This parameter can be one of the following values: + * @arg RCC_USBXTALESS_MODE USB work in crystal mode + * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode + */ +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode)); + + /* Clear the USB Crystal Mode bit */ + RCC->CFG3 &= RCC_USBXTALESSMode_MASK; + + /* Select the USB Crystal Mode */ + RCC->CFG3 |= RCC_USBXTALESSMode; +} + +/** + * @brief Enables or disables the RET peripheral clock. + * @param RCC_RETPeriph specifies the RET peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM + * @arg RCC_RET_PERIPH_LPUART + * @arg RCC_RET_PERIPH_LCD + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->RDCTRL |= RCC_RETPeriph; + } + else + { + RCC->RDCTRL &= ~RCC_RETPeriph; + } +} + +/** + * @brief Forces or releases RET peripheral reset. + * @param RCC_RETPeriph specifies the RET peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM. + * RCC_RET_PERIPH_LPUART. + * RCC_RET_PERIPH_LCD. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->RDCTRL |= (RCC_RETPeriph << 4); + } + else + { + RCC->RDCTRL &= ~(RCC_RETPeriph << 4); + } +} + +/** + * @brief Configures the LPTIM clock (LPTIMCLK). + * @param RCC_LPTIMCLKSource specifies the LPTIM clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + * @note When switching from comparator1/2 to other clock sources, + * it is suggested to disable comparators first. + */ +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource)); + //PWR DBP set 1 + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Clear the LPTIM clock source */ + RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK; + + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPTIMCLKSource; +} + +/** + * @brief Returns the clock source used as LPTIM clock (LPTIMCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + */ +uint32_t RCC_GetLPTIMClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK)); +} + +/** + * @brief Configures the LPUART clock (LPUARTCLK). + * @param RCC_LPUARTCLKSource specifies the LPUART clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock + */ +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource)); + + /* Clear the LPUART clock source */ + RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK; + + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPUARTCLKSource; +} + +/** + * @brief Returns the clock source used as LPUART clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock + */ +uint32_t RCC_GetLPUARTClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK)); +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error interrupts. + * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt + * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt + * + * @param Cmd new state of the specified SRAM1/2 parity error interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORINT(SramErrorInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS |= SramErrorInt; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS &= (~SramErrorInt); + } +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error reset. + * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset + * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset + * + * @param Cmd new state of the specified SRAM1/2 parity error reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS |= SramErrorReset; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS &= (~SramErrorReset); + } +} + +/** + * @brief Clears the specified SRAM1/2 parity error flag. + * @param SramErrorReset specifies the SRAM1/2 parity error flag. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag + * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag + */ +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag)); + RCC->SRAM_CTRLSTS |= SramErrorflag; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) Xtal bias. + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x0~0x1FF + */ +void LSE_XtalConfig(uint16_t LSE_Trim) +{ + uint32_t tmpregister = 0; + tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR; + //clear lse trim[8:0] + tmpregister &= (~(LSE_GM_MASK_VALUE)); + (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE); + tmpregister |= LSE_Trim; + *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_DISABLE LSE oscillator OFF + * @arg RCC_LSE_ENABLE LSE oscillator ON + * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x00~0x1FF + */ +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim) +{ + uint32_t LDCTRL_Value; + uint32_t i=0; + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* PWR DBP set 1 Enable PWR Clock */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE*/ + LDCTRL_Value = *(__IO uint32_t*)LDCTRL_ADDR; + LDCTRL_Value &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN)); + /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ENABLE: + /* Set LSEON bit */ + LDCTRL_Value |= RCC_LSE_ENABLE; + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + LSE_XtalConfig(LSE_Trim); + break; + case RCC_LSE_DISABLE: + /* Reset LSEON bit */ + LDCTRL_Value &= (~RCC_LSE_DISABLE); + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + /*Delay for 3 LSE Clock Wait for LSERD bit Reset*/ + for(i=0;i<0x7FF;i++); + break; + case RCC_LSE_BYPASS: + /* Set LSEBYP and LSEON bits */ + LDCTRL_Value |= RCC_LSE_BYPASS; + *(__IO uint32_t*)LDCTRL_ADDR = LDCTRL_Value; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock + */ +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource)); + + /* Clear the RTC clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL); + + /* Select the RTC clock source */ + RCC->LDCTRL |= RCC_RTCCLKSource; +} + +/** + * @brief Returns the clock source used as RTC clock (RTCCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK) + */ +uint32_t RCC_GetRTCClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL)); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function. + * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRtcClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the LSX clock (for TSC). + * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock + * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock + */ +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource)); + + /* Clear the LSX clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL); + + /* Select the LSX clock source */ + RCC->LDCTRL |= RCC_LSXCLKSource; +} + +/** + * @brief Returns the clock source used as LSX clock (for TSC). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC) + * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC) + */ +uint32_t RCC_GetLSXClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL)); +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks) +{ + uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0; + uint8_t msi_clk = 0; + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFG & CFG_PLLMULFCT_MASK; + pllsource = RCC->CFG & CFG_PLLSRC_MASK; + /* Get MSI clock --------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + pllclk = (HSI_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSI_VALUE * pllmull; + } + + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + pllclk = (HSE_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSE_VALUE * pllmull; + } + } + + /* PLL Div clock */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET) + { /* PLL clock divided by 2 */ + pllclk = (pllclk >> 1); + } + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFG & CFG_SCLKSTS_MASK; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + RCC_Clocks->SysclkFreq = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + RCC_Clocks->SysclkFreq = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + RCC_Clocks->SysclkFreq = pllclk; + break; + + default: + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFG & CFG_AHBPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_ApbAhbPresTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFG & CFG_APB1PRES_SET_MASK; + tmp = tmp >> 8; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFG & CFG_APB2PRES_SET_MASK; + tmp = tmp >> 11; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc; + + /* Get ADCHCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK; + presc = s_AdcHclkPresTable[tmp]; + /* ADCHCLK clock frequency */ + RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc; + /* Get ADCPLLCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5 + /* ADCPLLCLK clock frequency */ + RCC_Clocks->AdcPllClkFreq = pllclk / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_DMA + * @arg RCC_AHB_PERIPH_SRAM + * @arg RCC_AHB_PERIPH_FLITF + * @arg RCC_AHB_PERIPH_CRC + * @arg RCC_AHB_PERIPH_RNGC + * @arg RCC_AHB_PERIPH_SAC + * @arg RCC_AHB_PERIPH_ADC + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->AHBPCLKEN |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCLKEN &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PCLKEN |= RCC_APB2Periph; + } + else + { + RCC->APB2PCLKEN &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PCLKEN |= RCC_APB1Periph; + } + else + { + RCC->APB1PCLKEN &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_ADC. + * RCC_AHB_PERIPH_SAC. + * RCC_AHB_PERIPH_RNGC. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->AHBPRST |= RCC_AHBPeriph; + } + else + { + RCC->AHBPRST &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PRST |= RCC_APB2Periph; + } + else + { + RCC->APB2PRST &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PRST |= RCC_APB1Periph; + } + else + { + RCC->APB1PRST &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the LowPower domain reset. + * @param Cmd new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLowPowerReset(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param Cmd new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the LSE Clock Security System. + * @param Cmd new state of the LSE Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Get LSE Clock Security System failure status. + * @return LSE Clock Security System failure status (SET or RESET). + */ +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void) +{ + FlagStatus bitstatus = RESET; + /* Check the status of LSE Clock Security System */ + if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return LSE Clock Security System status */ + return bitstatus; +} + +/** + * @brief Configures the MCO PLL clock prescaler. + * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source + * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50% + */ +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler)); + + tmpregister = RCC->CFG; + /* Clear MCOPRE[3:0] bits */ + tmpregister &= ((uint32_t)0x0FFFFFFF); + /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_MCOCLKPrescaler; + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO specifies the clock source to output. + * + * this parameter can be one of the following values: + * @arg RCC_MCO_NOCLK No clock selected + * @arg RCC_MCO_LSI LSI oscillator clock selected + * @arg RCC_MCO_LSE LSE oscillator clock selected + * @arg RCC_MCO_MSI MSI oscillator clock selected + * @arg RCC_MCO_SYSCLK System clock selected + * @arg RCC_MCO_HSI HSI oscillator clock selected + * @arg RCC_MCO_HSE HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK PLL clock selected + * + */ +void RCC_ConfigMco(uint8_t RCC_MCO) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + tmpregister = RCC->CFG; + /* Clear MCO[2:0] bits */ + tmpregister &= ((uint32_t)0xF8FFFFFF); + /* Set MCO[2:0] bits according to RCC_MCO value */ + tmpregister |= ((uint32_t)(RCC_MCO << 24)); + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG specifies the flag to check. + * + * this parameter can be one of the following values: + * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready + * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready + * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready + * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready + * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status + * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag + * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag + * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag + * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag + * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset + * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset + * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset + * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset + * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset + * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset + * + * @return The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = RCC->CTRL; + } + else if (tmp == 2) /* The flag to check is in BDCTRL register */ + { + statusreg = RCC->LDCTRL; + } + else /* The flag to check is in CTRLSTS register */ + { + statusreg = RCC->CTRLSTS; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST, + * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, + * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +void RCC_ClrFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CTRLSTS |= CSR_RMRSTF_SET; + /* RMVF bit should be reset */ + RCC->CTRLSTS &= CSR_RMVF_Reset; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RccInt specifies the RCC interrupt source to check. + * + * this parameter can be one of the following values: + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * @arg RCC_INT_CLKSSIF Clock Security System interrupt + * + * @return The new state of RccInt (SET or RESET). + */ +INTStatus RCC_GetIntStatus(uint8_t RccInt) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_INT(RccInt)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT & RccInt) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RccInt status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RccInt specifies the interrupt pending bit to clear. + * + * this parameter can be any combination of the + * following values: + * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag + * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag + * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag + * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag + * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag + * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag + * @arg RCC_CLR_BORIF Clear BOR interrupt flag + * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag + */ +void RCC_ClrIntPendingBit(uint32_t RccClrInt) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLR_INTF(RccClrInt)); + /* Software set this bit to clear INT flag. */ + RCC->CLKINT |= RccClrInt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rtc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..9fed21757c08218a422b276adfa63691db072a0a --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_rtc.c @@ -0,0 +1,2344 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_rtc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_rtc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF) +#define RTC_FLAGS_MASK \ + ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \ + | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \ + | RTC_FLAG_SHOPF)) + +#define INITMODE_TIMEOUT ((uint32_t)0x00002000) +#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000) +#define RECALPF_TIMEOUT ((uint32_t)0x00001000) +#define SHPF_TIMEOUT ((uint32_t)0x00002000) + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** @addtogroup RTC_Private_Functions + * @{ + */ + +/** @addtogroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WRP. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSYF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSYF clear and RSYF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TSH, DAT and CTRL registers */ + RTC->TSH = (uint32_t)0x00000000; + RTC->DATE = (uint32_t)0x00002101; + + /* Reset All CTRL bits except CTRL[2:0] */ + RTC->CTRL &= (uint32_t)0x00000007; + + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CTRL register bits */ + RTC->CTRL &= (uint32_t)0x00000000; + RTC->WKUPT = (uint32_t)0x0000FFFF; + RTC->PRE = (uint32_t)0x007F00FF; + RTC->ALARMA = (uint32_t)0x00000000; + RTC->ALARMB = (uint32_t)0x00000000; + RTC->SCTRL = (uint32_t)0x00000000; + RTC->CALIB = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + RTC->ALRMBSS = (uint32_t)0x00000000; + + /* Reset INTSTS register and exit initialization mode */ + RTC->INITSTS = (uint32_t)0x00000000; + + RTC->OPT = (uint32_t)0x00000000; + RTC->TSCWKUPCTRL = (uint32_t)0x00000008; + RTC->TSCWKUPCNT = (uint32_t)0x000002FE; + + /* Wait till the RTC RSYF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct pointer to a RTC_InitType structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t i =0; + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CTRL HFMT Bit */ + RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT)); + /* Set RTC_CTRL register */ + RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRE */ + RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Delay for the RTC prescale effect */ + for(i=0;i<0x2FF;i++); + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct pointer to a RTC_InitType structure which will be + * initialized. + */ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_INITSTS[13:8]. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param Cmd new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableWriteProtection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->INITSTS & RTC_INITSTS_INITF; + initcounter++; + } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSYF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TSH and RTC_DATE shadow registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear RSYF flag */ + RTC->INITSTS &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF; + synchrocounter++; + } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param Cmd new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (Cmd != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CTRL |= RTC_CTRL_REFCLKEN; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CTRL &= ~RTC_CTRL_REFCLKEN; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param Cmd new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableBypassShadow(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Set the BYPS bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS; + } + else + { + /* Reset the BYPS bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains + * the time configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16)); + } + else + { + tmpregister = + (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TSH register */ + RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(status!=ERROR) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be + * initialized. + */ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->H12 = RTC_AM_H12; + RTC_TimeStruct->Hours = 0; + RTC_TimeStruct->Minutes = 0; + RTC_TimeStruct->Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will + * contain the returned current time configuration. + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes); + RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @return RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpregister = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpregister = (uint32_t)(RTC->SUBS); + + return (tmpregister); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that contains + * the date configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year))); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month); + assert_param(IS_RTC_MONTH(tmpregister)); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date); + assert_param(IS_RTC_DATE(tmpregister)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DATE register */ + RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(ERROR!=status) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct pointer to a RTC_DateType structure which will be + * initialized. + */ +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Date = 1; + RTC_DateStruct->Month = RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that will + * contain the returned current date configuration. + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year); + RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month); + RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date); + } +} + +/** + * @} + */ + +/** @addtogroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_EnableAlarm(DISABLE)). + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that + * contains the alarm configuration parameters. + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode)); + + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue)); + } + else + { + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue)); + } + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + assert_param(IS_RTC_12HOUR(tmpregister)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister)); + } + else + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = + (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds)) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_A_ALARM) + { + RTC->ALARMA = (uint32_t)tmpregister; + } + else + { + RTC->ALARMB = (uint32_t)tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which + * will be initialized. + */ +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12; + RTC_AlarmStruct->AlarmTime.Hours = 0; + RTC_AlarmStruct->AlarmTime.Minutes = 0; + RTC_AlarmStruct->AlarmTime.Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + RTC_AlarmStruct->DateWeekValue = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will + * contains the output alarm configuration values. + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)(RTC->ALARMA); + } + else + { + tmpregister = (uint32_t)(RTC->ALARMB); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16); + RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8); + RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU)); + RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16); + RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24); + RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL); + RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL); + + if (RTC_Format == RTC_FORMAT_BIN) + { + RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes); + RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds); + RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param Cmd new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm state */ + if (Cmd != DISABLE) + { + RTC->CTRL |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8); + alarmcounter++; + } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask.* + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmSubSecondValue specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared. + * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared. + * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared. + * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared. + * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared. + * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared. + * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared. + * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared. + * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared. + * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared. + * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match + * to activate alarm. + */ +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + + if (RTC_Alarm == RTC_A_ALARM) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASS = tmpregister; + } + else + { + /* Configure the Alarm B SubSecond register */ + RTC->ALRMBSS = tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @return RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpregister = 0; + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV); + } + else + { + tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV); + } + + return (tmpregister); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpClock Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16. + * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8. + * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4. + * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2. + * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE. + * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE. + */ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the Wakeup Timer clock source bits in CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL; + + /* Configure the clock source */ + RTC->CTRL |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp. + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpCounter specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WKUPT = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @return The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param Cmd new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + */ +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN; + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### Daylight Saving configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaving the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time). + * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time). + * @param RTC_StoreOperation Specifies the value to be written in the BCK bit + * in CTRL register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset. + * @arg RTC_STORE_OPERATION_SET BCK Bit Set. + */ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP); + /* Clear the SU1H and AD1H bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @return RTC Day Light Saving stored operation. + * - RTC_STORE_OPERATION_RESET + * - RTC_STORE_OPERATION_SET + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CTRL & RTC_CTRL_BAKP); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + + + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_DIS No output selected + * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output. + * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output. + * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output. + * @param RTC_OutputPolarity Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OUTPOL_HIGH The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + * @arg RTC_OUTPOL_LOW The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + */ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_MODE(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL); + + /* Configure the output selection and polarity */ + RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions + * @brief Coarse and Smooth Calibrations configuration functions + * +@verbatim + =============================================================================== + ##### Coarse and Smooth Calibrations configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative + * pin. + * @param Cmd new state of the coarse calibration Output. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableCalibOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_COEN; + } + else + { + /* Disable the RTC clock output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz. + * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz. + */ +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /*clear flags before config*/ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL); + + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s. + * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s. + * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured + */ +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses + | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the + * falling edge of the related pin. + * @param Cmd new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN)); + + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN); + } + else + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format + * @arg RTC_FORMAT_BCD BCD data format + * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will + * contains the TimeStamp date values. + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours); + RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes); + RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month); + RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date); + RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @return RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSS); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group11 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in + * Push Pull mode. + */ +void RTC_ConfigOutputType(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE); + RTC->OPT |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar. + * @arg RTC_SHIFT_ADD1S_DISABLE No effect. + * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured + */ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET) + { + /* Configure the Shift settings */ + RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) + using the RTC_SetAlarm() and RTC_EnableAlarm() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 20 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (+) Configure the RTC to generate the RTC wakeup timer event using the + RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is + required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC time-stamp event using the + RTC_EnableTimeStamp() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt mask. + * @arg RTC_INT_WUT WakeUp Timer interrupt mask. + * @arg RTC_INT_ALRB Alarm B interrupt mask. + * @arg RTC_INT_ALRA Alarm A interrupt mask. + * @param Cmd new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_INT(RTC_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN); + } + else + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN); + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECPF RECALPF event flag. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_INITF Initialization mode flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + * @arg RTC_FLAG_INITSF Registers Configured flag. + * @arg RTC_FLAG_SHOPF Shift operation pending flag. + * @arg RTC_FLAG_WTWF WakeUp Timer Write flag. + * @arg RTC_FLAG_ALBWF Alarm B Write flag. + * @arg RTC_FLAG_ALAWF Alarm A write flag. + * @return The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpregister & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG specifies the RTC flag to clear. + * This parameter can be any combination of the following values:. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + */ +void RTC_ClrFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_INT specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_INT_TS Time Stamp interrupt. + * @arg RTC_INT_WUT WakeUp Timer interrupt. + * @arg RTC_INT_ALRB Alarm B interrupt. + * @arg RTC_INT_ALRA Alarm A interrupt. + * @return The new state of RTC_INT (SET or RESET). + */ +INTStatus RTC_GetITStatus(uint32_t RTC_INT) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0, enablestatus = 0; + uint8_t tamperEnable = 0; + /* Check the parameters */ + assert_param(IS_RTC_GET_INT(RTC_INT)); + + /* Get the Interrupt enable Status */ + if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3)) + { + tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16); + if (tamperEnable > 0) + { + enablestatus = SET; + } + + } + else + { + enablestatus = (uint32_t)((RTC->CTRL & RTC_INT)); + + } + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_INT specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt + * @arg RTC_INT_WUT WakeUp Timer interrupt + * @arg RTC_INT_ALRB Alarm B interrupt + * @arg RTC_INT_ALRA Alarm A interrupt + */ +void RTC_ClrIntPendingBit(uint32_t RTC_INT) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_INT(RTC_INT)); + + /* Get the RTC_INITSTS Interrupt pending bits mask */ + tmpregister = (uint32_t)(RTC_INT >> 4); + + /* Clear the interrupt pending bits in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted. + * @return Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted. + * @return Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} +/** + * @brief Enable wakeup tsc functionand wakeup by the set time + * @param count wakeup time. + */ +void RTC_EnableWakeUpTsc(uint32_t count) +{ + // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1 + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // enter config wakeup cnt mode + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF; + // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI + RTC->TSCWKUPCNT = count; + // exit config wakeup cnt mode + RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF); + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // TSC wakeup enable + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN; +} + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @arg RTC_Tamper_3: Select Tamper 3. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + if (RTC_Tamper == RTC_TAMPER_3) + { + RTC_TamperTrigger <<= 5; + } + else if (RTC_Tamper == RTC_TAMPER_2) + { + RTC_TamperTrigger <<= 3; + } + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger); + +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level. + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle. + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSEN bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS; + } +} + +/** + * @brief Enables or Disables the TAMPTS. + * @param NewState: new state of TAMPTS. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperTAMPTSCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER1_INT: Select Tamper 1. + * @arg RTC_TAMPER2_INT: Select Tamper 2. + * @arg RTC_TAMPER3_INT: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(TAMPxIE)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)TAMPxIE; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~TAMPxIE; + } +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_spi.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..f9cb4f316d88634e35af9c2ec73a3275bdc4bdfd --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_spi.c @@ -0,0 +1,853 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_spi.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_spi.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @addtogroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Defines + * @{ + */ + +/* SPI SPIEN mask */ +#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040) +#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF) + +/* I2S I2SEN mask */ +#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400) +#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF) + +/* SPI CRCNEXT mask */ +#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000) +#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004) +#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0x3040) +#define I2SCFG_CLR_MASK ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xF7FF) +#define I2S_MODE_ENABLE ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S1_CLKSRC ((uint32_t)(0x00020000)) +#define I2S2_CLKSRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @addtogroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx where x can be 1, 2 to select the SPI peripheral. + */ +void SPI_I2S_DeInit(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE); + } + +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_InitStruct pointer to a SPI_InitType structure that + * contains the configuration information for the specified SPI peripheral. + */ +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct) +{ + uint16_t tmpregister = 0; + + /* check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen)); + assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL)); + assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + + /*---------------------------- SPIx CTRL1 Configuration ------------------------*/ + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */ + /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */ + /* Set LSBFirst bit according to FirstBit value */ + /* Set BR bits according to BaudRatePres value */ + /* Set CPOL bit according to CLKPOL value */ + /* Set CPHA bit according to CLKPHA value */ + tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode + | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA + | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit); + /* Write to SPIx CTRL1 */ + SPIx->CTRL1 = tmpregister; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */ + SPIx->I2SCFG &= SPI_MODE_ENABLE; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SPI_InitStruct->CRCPoly; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct pointer to an I2S_InitType structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + */ +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct) +{ + uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksType RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat)); + assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency)); + assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL)); + + /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/ + /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */ + SPIx->I2SCFG &= I2SCFG_CLR_MASK; + SPIx->I2SPREDIV = 0x0002; + + /* Get the I2SCFG register value */ + tmpregister = SPIx->I2SCFG; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if (((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S1 */ + tmp = I2S1_CLKSRC; + } + else + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLKSRC; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SysclkFreq; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPREDIV register the computed value */ + SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpregister |= (uint16_t)( + I2S_MODE_ENABLE + | (uint16_t)(I2S_InitStruct->I2sMode + | (uint16_t)(I2S_InitStruct->Standard + | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL)))); + + /* Write to SPIx I2SCFG */ + SPIx->I2SCFG = tmpregister; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized. + */ +void SPI_InitStruct(SPI_InitType* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; + /* Initialize the CRCPoly member */ + SPI_InitStruct->CRCPoly = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized. + */ +void I2S_InitStruct(I2S_InitType* I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the MCLKEnable member */ + I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE; + + /* Initialize the AudioFrequency member */ + I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT; + + /* Initialize the CLKPOL member */ + I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask + * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask + * @arg SPI_I2S_INT_ERR Error interrupt mask + * @param Cmd new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CTRL2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CTRL2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request + * @param Cmd new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param Data Data to be transmitted. + */ +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Write in the DAT register the data to be sent */ + SPIx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @return The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the data in the DAT register */ + return SPIx->DAT; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_NSSInternalSoft specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSS_HIGH Set NSS pin internally + * @arg SPI_NSS_LOW Reset NSS pin internally + */ +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSS_LOW) + { + /* Set NSS pin internally by software */ + SPIx->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CTRL1 &= SPI_NSS_LOW; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataLen specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit + * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit + */ +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(DataLen)); + /* Clear DFF bit */ + SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS; + /* Set new DFF bit value */ + SPIx->CTRL1 |= DataLen; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + */ +void SPI_TransmitCrcNext(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_CRC specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_TX Selects Tx CRC register + * @arg SPI_CRC_RX Selects Rx CRC register + * @return The selected CRC register value.. + */ +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_RX) + { + /* Get the Tx CRC register */ + crcreg = SPIx->CRCTDAT; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->CRCRDAT; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @return The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPOLY; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataDirection specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction + * @arg SPI_BIDIRECTION_RX Selects Rx receive direction + */ +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_BIDIRECTION(DataDirection)); + if (DataDirection == SPI_BIDIRECTION_TX) + { + /* Set the Tx only mode */ + SPIx->CTRL1 |= SPI_BIDIRECTION_TX; + } + else + { + /* Set the Rx only mode */ + SPIx->CTRL1 &= SPI_BIDIRECTION_RX; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag. + * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag. + * @arg SPI_I2S_BUSY_FLAG Busy flag. + * @arg SPI_I2S_OVER_FLAG Overrun flag. + * @arg SPI_MODERR_FLAG Mode Fault flag. + * @arg SPI_CRCERR_FLAG CRC Error flag. + * @arg I2S_UNDER_FLAG Underrun Error flag. + * @arg I2S_CHSIDE_FLAG Channel Side flag. + * @return The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_FLAG specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STS register (SPI_I2S_GetStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STS register (SPI_I2S_GetStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a + * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI). + */ +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->STS = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt. + * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt. + * @arg SPI_I2S_INT_OVER Overrun interrupt. + * @arg SPI_INT_MODERR Mode Fault interrupt. + * @arg SPI_INT_CRCERR CRC Error interrupt. + * @arg I2S_INT_UNDER Underrun Error interrupt. + * @return The new state of SPI_I2S_IT (SET or RESET). + */ +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable + * the SPI). + */ +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->STS = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tim.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tim.c new file mode 100644 index 0000000000000000000000000000000000000000..01f012dd9a17248b98a1a31727136692f50ebf8a --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tim.c @@ -0,0 +1,3290 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_tim.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_tim.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @addtogroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCTRL_ETR_MASK ((uint16_t)0x00FF) +#define CAPCMPMOD_OFFSET ((uint16_t)0x0018) +#define CAPCMPEN_CCE_SET ((uint16_t)0x0001) +#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004) + +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + */ +void TIM_DeInit(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + + if (TIMx == TIM1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE); + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure that contains the configuration information for the + * specified TIM peripheral. + */ +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode)); + assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv)); + + tmpcr1 = TIMx->CTRL1; + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode; + } + + if ((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv; + } + + TIMx->CTRL1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->AR = TIM_TimeBaseInitStruct->Period; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE; + + /*channel input from comp or iom*/ + tmpcr1 = TIMx->CTRL1; + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapCh1FromCompEn) + tmpcr1 |= (0x01L << 11); + else + tmpcr1 &= ~(0x01L << 11); + } + if(TIMx==TIM9) + { + if (TIM_TimeBaseInitStruct->CapCh2FromCompEn) + tmpcr1 |= (0x01L << 12); + else + tmpcr1 &= ~(0x01L << 12); + if (TIM_TimeBaseInitStruct->CapCh3FromCompEn) + tmpcr1 |= (0x01L << 13); + else + tmpcr1 &= ~(0x01L << 13); + if (TIM_TimeBaseInitStruct->CapCh4FromCompEn) + tmpcr1 |= (0x01L << 14); + else + tmpcr1 &= ~(0x01L << 14); + } + /*etr input from comp or iom*/ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn) + tmpcr1 |= (0x01L << 15); + else + tmpcr1 &= ~(0x01L << 15); + } + TIMx->CTRL1 = tmpcr1; + /*sel etr from iom or tsc*/ + tmpcr1 = TIMx->CTRL2; + if ((TIMx == TIM2) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn) + tmpcr1 |= (0x01L << 8); + else + tmpcr1 &= ~(0x01L << 8); + } + TIMx->CTRL2 = tmpcr1; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN); + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->OcPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->OutputState; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->OcNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcNIdleState; + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN)); + + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel5 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 5: Reset the CC5E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel6 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 6: Reset the CC6E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT6 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IsTimCh(TIM_ICInitStruct->Channel)); + assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection)); + assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler)); + assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity)); + } + else + { + assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity)); + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + assert_param(IsTimList8Module(TIMx)); + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + assert_param(IsTimList6Module(TIMx)); + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + assert_param(IsTimList3Module(TIMx)); + /* TI3 Configuration */ + ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + assert_param(IsTimList3Module(TIMx)); + /* TI4 Configuration */ + ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING; + uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING) + { + icoppositepolarity = TIM_IC_POLARITY_FALLING; + } + else + { + icoppositepolarity = TIM_IC_POLARITY_RISING; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI) + { + icoppositeselection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI2 Configuration */ + ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI1 Configuration */ + ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that + * contains the BKDT Register configuration information for the TIM peripheral. + */ +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + uint32_t tmp; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState)); + assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState)); + assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel)); + assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break)); + assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel + | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity + | TIM_BDTRInitStruct->AutomaticOutput; + + /*cofigure other break in*/ + tmp = TIMx->CTRL1; + /*IOMBKPEN 0 meaning iom as break enable*/ + if (TIM_BDTRInitStruct->IomBreakEn) + tmp &= ~(0x01L << 10); + else + tmp |= (0x01L << 10); + if (TIM_BDTRInitStruct->LockUpBreakEn) + tmp |= (0x01L << 16); + else + tmp &= ~(0x01L << 16); + if (TIM_BDTRInitStruct->PvdBreakEn) + tmp |= (0x01L << 17); + else + tmp &= ~(0x01L << 17); + TIMx->CTRL1 = tmp; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure which will be initialized. + */ +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Period = 0xFFFF; + TIM_TimeBaseInitStruct->Prescaler = 0x0000; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->RepetCnt = 0x0000; + + TIM_TimeBaseInitStruct->CapCh1FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh2FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh3FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh4FromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct pointer to a OCInitType structure which will + * be initialized. + */ +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x0000; + TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will + * be initialized. + */ +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->Channel = TIM_CH_1; + TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->IcFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which + * will be initialized. + */ +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param Cmd new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CTRL1 |= TIM_CTRL1_CNTEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral. + * @param Cmd new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BKDT |= TIM_BKDT_MOEN; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @param Cmd new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DINTEN |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DINTEN &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_EventSource specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EVT_SRC_UPDATE Timer update Event source + * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source + * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source + * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source + * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source + * @arg TIM_EVT_SRC_COM Timer COM event source + * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source + * @arg TIM_EVT_SRC_BREAK Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8. + */ +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimEvtSrc(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EVTGEN = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_DMABase DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL, + * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN, + * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN, + * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR, + * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2, + * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT, + * TIM_DMABASE_DMACTRL. + * @param TIM_DMABurstLength DMA Burst length. + * This parameter can be one value between: + * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS. + */ +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IsTimDmaBase(TIM_DMABase)); + assert_param(IsTimDmaLength(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 + * to select the TIM peripheral. + * @param TIM_DMASource specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_UPDATE TIM update Interrupt source + * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM TIM Commutation DMA source + * @arg TIM_DMA_TRIG TIM Trigger DMA source + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList9Module(TIMx)); + assert_param(IsTimDmaSrc(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DINTEN |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DINTEN &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIM peripheral. + */ +void TIM_ConfigInternalClk(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_InputTriggerSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + */ +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimInterTrigSel(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector + * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1 + * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2 + * @param IcPolarity specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param ICFilter specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + */ +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource)); + assert_param(IsTimIcPalaritySingleEdge(IcPolarity)); + assert_param(IsTimInCapFilter(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2) + { + ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + else + { + ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + tmpsmcr |= TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCTRL |= TIM_SMCTRL_EXCEN; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + tmpsmcr = TIMx->SMCTRL; + /* Reset the ETR Bits */ + tmpsmcr &= SMCTRL_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= + (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Prescaler specifies the Prescaler Register value + * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event. + * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately. + */ +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimPscReloadMode(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EVTGEN = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param CntMode specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CNT_MODE_UP TIM Up Counting Mode + * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode + * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1 + * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2 + * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3 + */ +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode) +{ + uint32_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimCntMode(CntMode)); + tmpcr1 = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + tmpcr1 |= CntMode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector + * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1 + * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2 + * @arg TIM_TRIG_SEL_ETRF External Trigger input + */ +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimTrigSel(TIM_InputTriggerSource)); + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + * @param TIM_IC2Polarity specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + */ +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IsTimEncodeMode(TIM_EncoderMode)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity)); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL))); + tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P))); + tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF. + */ +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF. + */ +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF. + */ +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF. + */ +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 5 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF. + */ +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Forces the TIMx output 6 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF. + */ +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on AR. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AR Preload Bit */ + TIMx->CTRL1 |= TIM_CTRL1_ARPEN; + } + else + { + /* Reset the AR Preload Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral + * @param Cmd new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the COM Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCUSEL; + } + else + { + /* Reset the COM Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param Cmd new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCDSEL; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIMx peripheral + * @param Cmd new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCPCTL; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC5PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC6PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 5 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 6 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF5 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF6 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param OcPolarity specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P); + tmpccer |= OcPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP); + tmpccer |= OcNPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P); + tmpccer |= (uint32_t)(OcPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP); + tmpccer |= (uint32_t)(OcNPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P); + tmpccer |= (uint32_t)(OcPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP); + tmpccer |= (uint32_t)(OcNPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P); + tmpccer |= (uint32_t)(OcPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 5 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC5 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC5P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P); + tmpccer |= (uint32_t)(OcPolarity << 16); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 6 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC6 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC6P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P); + tmpccer |= (uint32_t)(OcPolarity << 20); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param TIM_CCx specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE. + */ +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimCapCmpState(TIM_CCx)); + + tmp = CAPCMPEN_CCE_SET << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE. + */ +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimComplementaryCh(Channel)); + assert_param(IsTimCapCmpNState(TIM_CCxN)); + + tmp = CAPCMPEN_CCNE_SET << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param OcMode specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMODE_TIMING + * @arg TIM_OCMODE_ACTIVE + * @arg TIM_OCMODE_TOGGLE + * @arg TIM_OCMODE_PWM1 + * @arg TIM_OCMODE_PWM2 + * @arg TIM_FORCED_ACTION_ACTIVE + * @arg TIM_FORCED_ACTION_INACTIVE + */ +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimOc(OcMode)); + + tmp = (uint32_t)TIMx; + tmp += CAPCMPMOD_OFFSET; + + tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint16_t)~tmp1; + + if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3)) + { + tmp += (Channel >> 1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= OcMode; + } + else + { + tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_UpdateSource specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow. + */ +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimUpdateSrc(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the URS Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPRS; + } + else + { + /* Reset the URS Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CTRL2 |= TIM_CTRL2_TI1SEL; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_OPMode specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE + * @arg TIM_OPMODE_REPET + */ +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimOpMOde(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM); + /* Configure the OPM Mode */ + TIMx->CTRL1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral. + * @param TIM_TRGOSource specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO). + * + */ +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IsTimList7Module(TIMx)); + assert_param(IsTimTrgoSrc(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_SlaveMode specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter. + */ +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimSlaveMode(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL); + /* Select the Slave Mode */ + TIMx->SMCTRL |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action + */ +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD); + + /* Set or Reset the MSM Bit */ + TIMx->SMCTRL |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Counter specifies the Counter register new value. + */ +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Autoreload specifies the Autoreload register new value. + */ +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Autoreload Register value */ + TIMx->AR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Compare1 specifies the Capture Compare1 register new value. + */ +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCDAT1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param Compare2 specifies the Capture Compare2 register new value. + */ +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCDAT2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3 specifies the Capture Compare3 register new value. + */ +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCDAT3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4 specifies the Capture Compare4 register new value. + */ +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT4 = Compare4; +} + +/** + * @brief Sets the TIMx Capture Compare5 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare5 specifies the Capture Compare5 register new value. + */ +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT5 = Compare5; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare6 specifies the Capture Compare6 register new value. + */ +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT6 = Compare6; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMOD2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLK_DIV1 TDTS = Tck_tim + * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim + * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim + */ +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimClkDiv(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD); + /* Set the CKD value */ + TIMx->CTRL1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @return Capture Compare 1 Register value. + */ +uint16_t TIM_GetCap1(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCDAT1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @return Capture Compare 2 Register value. + */ +uint16_t TIM_GetCap2(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCDAT2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 3 Register value. + */ +uint16_t TIM_GetCap3(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCDAT3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 4 Register value. + */ +uint16_t TIM_GetCap4(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCDAT4; +} + +/** + * @brief Gets the TIMx Input Capture 5 value. + * @param TIMx where x can be 1 8 to select the TIM peripheral. + * @return Capture Compare 5 Register value. + */ +uint16_t TIM_GetCap5(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 5 Register value */ + return TIMx->CCDAT5; +} + +/** + * @brief Gets the TIMx Input Capture 6 value. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @return Capture Compare 6 Register value. + */ +uint16_t TIM_GetCap6(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 6 Register value */ + return TIMx->CCDAT6; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Counter Register value. + */ +uint16_t TIM_GetCnt(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetAutoReload(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->AR; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral. + * @param TIM_CCEN specifies the Bit to check. + * This parameter can be one of the following values: + * @arg TIM_CC1EN CC1EN Bit + * @arg TIM_CC1NEN CC1NEN Bit + * @arg TIM_CC2EN CC2EN Bit + * @arg TIM_CC2NEN CC2NEN Bit + * @arg TIM_CC3EN CC3EN Bit + * @arg TIM_CC3NEN CC3NEN Bit + * @arg TIM_CC4EN CC4EN Bit + * @arg TIM_CC5EN CC5EN Bit + * @arg TIM_CC6EN CC6EN Bit + * @note + * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + + if(TIMx==TIM1 || TIMx==TIM8){ + assert_param(IsAdvancedTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + }else if(TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){ + assert_param(IsGeneralTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetFlag(TIM_FLAG)); + + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + */ +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimClrFlag(TIM_FLAG)); + + /* Clear the flags */ + TIMx->STS = (uint32_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @return The new state of the TIM_IT(SET or RESET). + */ +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetInt(TIM_IT)); + + itstatus = TIMx->STS & TIM_IT; + + itenable = TIMx->DINTEN & TIM_IT; + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM1 update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + */ +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->STS = (uint32_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F))); + tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F))); + tmpccmr1 |= (uint16_t)(IcFilter << 12); + tmpccmr1 |= (uint16_t)(IcSelection << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F))); + tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F))); + tmpccmr2 |= (uint16_t)(IcSelection << 8); + tmpccmr2 |= (uint16_t)(IcFilter << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN); + } + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tsc.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tsc.c new file mode 100644 index 0000000000000000000000000000000000000000..9338f80deb56cb96f7716f4189719cc0459d713c --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_tsc.c @@ -0,0 +1,279 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_tsc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x.h" +#include "n32l40x_tsc.h" + +/** +* @brief Init TSC config +* @param InitParam: TSC initialize structure +* @return : TSC_ErrorTypeDef +*/ +TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam) +{ + uint32_t tempreg,timeout; + + assert_param(IS_TSC_DET_MODE(InitParam->Mode)); + assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt)); + assert_param(IS_TSC_PAD_SPEED(InitParam->Speed)); + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*TSC_CTRL config*/ + tempreg = 0; + if(InitParam->Mode == TSC_HW_DETECT_MODE) + { + assert_param(IS_TSC_DET_PERIOD(InitParam->Period)); + assert_param(IS_TSC_FILTER(InitParam->Filter)); + assert_param(IS_TSC_DET_TYPE(InitParam->Type)); + assert_param(IS_TSC_INT(InitParam->Int)); + + tempreg |= InitParam->Period; + tempreg |= InitParam->Filter; + tempreg |= InitParam->Type; + tempreg |= InitParam->Int; + } + else + { + assert_param(IS_TSC_OUT(InitParam->Out)); + tempreg |= InitParam->Out; + } + + TSC->CTRL = tempreg; + + /*TSC_ANA_SEL config*/ + TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed; + + return TSC_ERROR_OK; +} + +/** + * @brief Config the clock source of TSC + * @param TSC_ClkSource specifies the clock source of TSC + * This parameter can be one of the following values: + * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default) + * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator + * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock + * @retval TSC error code + */ +TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(TSC_CLK_SRC_LSI == TSC_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + else if((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET) + { + RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28); + timeout = 0; + while(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + } + else + return TSC_ERROR_PARAMETER; + + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100; + + /*set LSI as TSC clock source*/ + RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL); + + /*Enable TSC clk*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE); + + return TSC_ERROR_OK; +} + +/** +* @brief Configure internal charge resistor for some channels +* @param res: internal resistor selecte +* This parameter can be one of the following values: +* @arg TSC_RESR_CHN_RESIST_0: 1M OHM +* @arg TSC_RESR_CHN_RESIST_1: 882K OHM +* @arg TSC_RESR_CHN_RESIST_2: 756K OHM +* @arg TSC_RESR_CHN_RESIST_3: 630K OHM +* @arg TSC_RESR_CHN_RESIST_4: 504K OHM +* @arg TSC_RESR_CHN_RESIST_5: 378K OHM +* @arg TSC_RESR_CHN_RESIST_6: 252K OHM +* @arg TSC_RESR_CHN_RESIST_7: 126K OHM +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @return: none +*/ +TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ) +{ + uint32_t i,chn,timeout,nReg,nPos; + + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_RESISTOR_VALUE(res)); + + /*Check charge resistor value */ + if(res > TSC_RESRx_CHN_RESIST_7) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /* Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set resistance for each channel one by one*/ + for (i = 0; i> 3; + nPos = (i & 0x7UL)*4; + MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1; + } + + return TSC_ERROR_OK; +} + +/** +* @brief Configure threshold value for some channels +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE +* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA +* @return: None +*/ +TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta) +{ + uint32_t i, chn,timeout; + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_THRESHOLD_BASE(base)); + assert_param(IS_TSC_THRESHOLD_DELTA(delta)); + + /*Check the base and delta value*/ + if( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA)) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set the base and delta for each channnel one by one*/ + for (i = 0; iTHRHD[i] = (base<>= 1; + } + + return TSC_ERROR_OK; +} + + +/** +* @brief Get parameters of one channel. +* @param ChnCfg: Pointer of TSC_ChnCfg structure. +* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN +* @return: None +*/ +TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum) +{ + uint32_t nReg,nPos; + + assert_param(IS_TSC_CHN_NUMBER(ChannelNum)); + + /*Check channel number*/ + if(!(IS_TSC_CHN_NUMBER(ChannelNum))) + return TSC_ERROR_PARAMETER; + + /* Get the base and delta value for a channel*/ + ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos; + ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos; + + /* Get the charge resistor type for a channel*/ + nReg = ChannelNum>>3; + nPos = (ChannelNum & 0x7UL)*4; + ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk; + + return TSC_ERROR_OK; +} + + diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_usart.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..82cfbe6f0a4351206714fdaf196870070a4eb909 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_usart.c @@ -0,0 +1,956 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_usart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_usart.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @brief USART driver modules + * @{ + */ + +/** @addtogroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Defines + * @{ + */ + +#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ +#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */ +#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */ + +#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */ + +#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_DeInit(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE); + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct pointer to a USART_InitType structure + * that contains the configuration information for the specified USART + * peripheral. + */ +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct) +{ + uint32_t tmpregister = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksType RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear STOP[13:12] bits */ + tmpregister &= CTRL2_STPB_CLR_MASK; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to StopBits value */ + tmpregister |= (uint32_t)USART_InitStruct->StopBits; + + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL1 Configuration -----------------------*/ + tmpregister = USARTx->CTRL1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to WordLength value */ + /* Set PCE and PS bits according to Parity value */ + /* Set TE and RE bits according to Mode value */ + tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode; + /* Write to USART CTRL1 */ + USARTx->CTRL1 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL3 Configuration -----------------------*/ + tmpregister = USARTx->CTRL3; + /* Clear CTSE and RTSE bits */ + tmpregister &= CTRL3_CLR_MASK; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to HardwareFlowControl value */ + tmpregister |= USART_InitStruct->HardwareFlowControl; + /* Write to USART CTRL3 */ + USARTx->CTRL3 = (uint16_t)tmpregister; + + /*---------------------------- USART PBC Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE)) + { + apbclock = RCC_ClocksStatus.Pclk2Freq; + } + else + { + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate))); + tmpregister = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpregister >> 4)); + + /* Implement the fractional part in the register */ + tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + /* Write to USART PBC */ + USARTx->BRCF = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct pointer to a USART_InitType structure + * which will be initialized. + */ +void USART_StructInit(USART_InitType* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->BaudRate = 9600; + USART_InitStruct->WordLength = USART_WL_8B; + USART_InitStruct->StopBits = USART_STPB_1; + USART_InitStruct->Parity = USART_PE_NO; + USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4/UART5. + */ +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct) +{ + uint32_t tmpregister = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit)); + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpregister &= CTRL2_CLOCK_CLR_MASK; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to Clock value */ + /* Set CPOL bit according to Polarity value */ + /* Set CPHA bit according to Phase value */ + /* Set LBCL bit according to LastBit value */ + tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity + | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure which will be initialized. + */ +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->Clock = USART_CLK_DISABLE; + USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW; + USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; + USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_UEN_SET; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_UEN_RESET; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Transmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) + * @param Cmd new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CFG_INT(USART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_INT & INT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CTRL3 register */ + { + usartxbase += 0x14; + } + if (Cmd != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAREQ_TX USART DMA transmit request + * @arg USART_DMAREQ_RX USART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Addr Indicates the address of the USART node. + */ +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Addr)); + + /* Clear the USART address */ + USARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the USART address node */ + USARTx->CTRL2 |= USART_Addr; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUpMode specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WUM_IDLELINE WakeUp by an idle line detection + * @arg USART_WUM_ADDRMASK WakeUp by an address mark + */ +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUpMode)); + + USARTx->CTRL1 &= CTRL1_WUM_MASK; + USARTx->CTRL1 |= USART_WakeUpMode; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_RCVWU_SET; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_RCVWU_RESET; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBDL_10B 10-bit break detection + * @arg USART_LINBDL_11B 11-bit break detection + */ +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CTRL2 &= CTRL2_LINBDL_MASK; + USARTx->CTRL2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 |= CTRL2_LINMEN_SET; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 &= CTRL2_LINMEN_RESET; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data the data to transmit. + */ +void USART_SendData(USART_Module* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DAT = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_SendBreak(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime specifies the guard time. + * @note The guard time bits are not available for UART4/UART5. + */ +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTP &= GTP_LSB_MASK; + /* Set the USART guard time */ + USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + */ +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTP &= GTP_MSB_MASK; + /* Set the USART prescaler */ + USARTx->GTP |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCMEN_SET; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCMEN_RESET; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCNACK_SET; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCNACK_RESET; + } +} + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_HDMEN_SET; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_HDMEN_RESET; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDAMODE_LOWPPWER + * @arg USART_IRDAMODE_NORMAL + */ +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CTRL3 &= CTRL3_IRDALP_MASK; + USARTx->CTRL3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_IRDAMEN_SET; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LINBD LIN Break detection flag + * @arg USART_FLAG_TXDE Transmit data register empty flag + * @arg USART_FLAG_TXC Transmission Complete flag + * @arg USART_FLAG_RXDNE Receive data register not empty flag + * @arg USART_FLAG_IDLEF Idle Line detection flag + * @arg USART_FLAG_OREF OverRun Error flag + * @arg USART_FLAG_NEF Noise Error flag + * @arg USART_FLAG_FEF Framing Error flag + * @arg USART_FLAG_PEF Parity Error flag + * @return The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if (USART_FLAG == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LINBD LIN Break detection flag. + * @arg USART_FLAG_TXC Transmission Complete flag. + * @arg USART_FLAG_RXDNE Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->STS = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Tansmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_OREF OverRun Error interrupt + * @arg USART_INT_NEF Noise Error interrupt + * @arg USART_INT_FEF Framing Error interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @return The new state of USART_INT (SET or RESET). + */ +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_INT & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + itmask &= USARTx->CTRL1; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + itmask &= USARTx->CTRL2; + } + else /* The IT is in CTRL3 register */ + { + itmask &= USARTx->CTRL3; + } + + bitpos = USART_INT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXC Transmission complete interrupt. + * @arg USART_INT_RXDNE Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetIntStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetIntStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLR_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_INT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STS = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_wwdg.c b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..a31b9592ec50c448b9021297e3c72900139dc6b8 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/n32l40x_std_periph_driver/src/n32l40x_wwdg.c @@ -0,0 +1,223 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l40x_wwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l40x_wwdg.h" +#include "n32l40x_rcc.h" + +/** @addtogroup n32l40x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @addtogroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFG_OFFADDR (WWDG_OFFADDR + 0x04) +#define EWINT_BIT 0x09 +#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_ACTB_SET ((uint32_t)0x00000080) + +/* CFG register bit mask */ +#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F) +#define CFG_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + */ +void WWDG_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8 + */ +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpregister = WWDG->CFG & CFG_TIMERB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpregister |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + */ +void WWDG_SetWValue(uint8_t WindowValue) +{ + __IO uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WVALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpregister = WWDG->CFG & CFG_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpregister |= WindowValue & (uint32_t)BIT_MASK; + + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + */ +void WWDG_EnableInt(void) +{ + *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_SetCnt(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CTRL = Counter & BIT_MASK; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + WWDG->CTRL = CTRL_ACTB_SET | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetEWINTF(void) +{ + return (FlagStatus)(WWDG->STS); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + */ +void WWDG_ClrEWINTF(void) +{ + WWDG->STS = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L40x/weave.yaml b/drivers/hal/nationstech/N32L40x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..05c7267a4d120ffb616341a5670cf2d0587fb4f1 --- /dev/null +++ b/drivers/hal/nationstech/N32L40x/weave.yaml @@ -0,0 +1,33 @@ +# 组名 +group_name: hal/lowlevel + +# 依赖宏控 +depend_macro: + - SERIES_N32L40X + +# 编译连接信息 +build_option: + cpppath: + - n32l40x_std_periph_driver/inc + - CMSIS/core + - CMSIS/device + +# 源码 +source_file: + - CMSIS/device/system_n32l40x.c + - n32l40x_std_periph_driver/src/n32l40x_rcc.c + - n32l40x_std_periph_driver/src/misc.c + - n32l40x_std_periph_driver/src/n32l40x_gpio.c + - n32l40x_std_periph_driver/src/n32l40x_exti.c ? {is_define("OS_USING_PIN")} + - n32l40x_std_periph_driver/src/n32l40x_iwdg.c ? {is_define("OS_USING_WDG")} + - n32l40x_std_periph_driver/src/n32l40x_usart.c ? {is_define("OS_USING_SERIAL")} + - n32l40x_std_periph_driver/src/n32l40x_adc.c ? {is_define("OS_USING_ADC")} + - n32l40x_std_periph_driver/src/n32l40x_dac.c ? {is_define("OS_USING_DAC")} + - n32l40x_std_periph_driver/src/n32l40x_i2c.c ? {is_define("OS_USING_I2C")} + - n32l40x_std_periph_driver/src/n32l40x_spi.c ? {is_define("OS_USING_SPI")} + - n32l40x_std_periph_driver/src/n32l40x_flash.c ? {is_define("OS_USING_FAL")} + - n32l40x_std_periph_driver/src/n32l40x_dma.c ? {is_define("OS_USING_DMA")} + - n32l40x_std_periph_driver/src/n32l40x_rtc.c ? {is_define("BSP_USING_RTC")} + - n32l40x_std_periph_driver/src/n32l40x_pwr.c ? {is_define("BSP_USING_RTC")} + - n32l40x_std_periph_driver/src/n32l40x_tim.c ? {is_define("BSP_USING_TIMER")} + - n32l40x_std_periph_driver/src/n32l40x_eth.c ? {is_define("BSP_USING_ETH")} diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_common_tables.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..68884992bdfb7723a872afb7b6893b25cb89e4ed --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 09. August 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_const_structs.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..51accc69646afaf0463cba20d999c1512f5c0912 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 09. August 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_math.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..7bf0c7dbf560b873426ab4498192ec7c028682d0 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armcc.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..0fb81877143241e2195410179977ace21c8b22ea --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armclang.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..ddc2a81e71f91669c8c1ece7a0d763be04cd9d54 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_compiler.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..156da2bcd50e3ba24d27e442a802b35c1c8d4ee0 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_gcc.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..90a4b8f5cb243cf3e4debcc335838c0f1e85b94b --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_iccarm.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..49e22185b76e186cb30c808f10c315018da17ff0 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_version.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..bbfe74b8847f7ddf3a14320ea0ef9f3b17a6f577 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/core_cm4.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..f54efdff0b41ee92f5fb90c3f409944de3138aba --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/core/mpu_armv7.h b/drivers/hal/nationstech/N32L43x/CMSIS/core/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..423d73abe54a5931b99bf3b4359cf63c524a0c71 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/core/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V1.2.1 + * @date 09. August 2022 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/n32l43x.h b/drivers/hal/nationstech/N32L43x/CMSIS/device/n32l43x.h new file mode 100644 index 0000000000000000000000000000000000000000..e6433a7664458b039087c4f18761adfe268bab23 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/n32l43x.h @@ -0,0 +1,8067 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_H__ +#define __N32L43X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32L43x_Library_Basic + * @{ + */ + +#if !defined USE_STDPERIPH_DRIVER +/* + * Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_STDPERIPH_DRIVER +#endif + +/* + * In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE +#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/* + * In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */ + +#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/ +#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/ + +#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/ + +#define __N32L43X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ +#define __N32L43X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __N32L43X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __N32L43X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ + +/** + * @brief N32L43x Standard Peripheral Library version number + */ +#define __N32L43X_STDPERIPH_VERSION \ + ((__N32L43X_STDPERIPH_VERSION_MAIN << 24) | (__N32L43X_STDPERIPH_VERSION_SUB1 << 16) \ + | (__N32L43X_STDPERIPH_VERSION_SUB2 << 8) | (__N32L43X_STDPERIPH_VERSION_RC)) + +/* + * Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#ifdef N32L43X +#define __MPU_PRESENT 1 /*!< N32L43x devices does not provide an MPU */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#endif /* N32L43x */ +#define __NVIC_PRIO_BITS 4 /*!< N32L43x uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief N32L43x Interrupt Number Definition + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** N32L43x specific Interrupt Numbers ********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */ + RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */ + DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */ + DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */ + DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */ + DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */ + DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */ + DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */ + DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */ + ADC_IRQn = 19, /*!< ADC global Interrupt */ + USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */ + USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */ + COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + UART4_IRQn = 47, /*!< UART4 global Interrupt */ + UART5_IRQn = 48, /*!< UART5 global Interrupt */ + LPUART_IRQn = 49, /*!< LPUART global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + TIM6_IRQn = 51, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 52, /*!< TIM7 global Interrupt */ + CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */ + CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */ + LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */ + LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */ + LCD_IRQn = 59, /*!< LCD global interrupt through EXTI line 26 */ + SAC_IRQn = 60, /*!< SAC global Interrupt */ + MMU_IRQn = 61, /*!< MMU global Interrupt */ + TSC_IRQn = 62, /*!< TSC global Interrupt */ + RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */ + TIM9_IRQn = 64, /*!< TIM9 global interrupt */ + UCDR_IRQn = 65, /*!< UCDR error interrupt */ + LPRCNT_IRQn = 152 /*!< LPRCNT turns overflow interrupt */ +} IRQn_Type; + +#include "core_cm4.h" +#include "system_n32l43x.h" +#include +#include + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, + INTStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/* N32L43x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t SAMPT1; + __IO uint32_t SAMPT2; + __IO uint32_t JOFFSET1; + __IO uint32_t JOFFSET2; + __IO uint32_t JOFFSET3; + __IO uint32_t JOFFSET4; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t RSEQ1; + __IO uint32_t RSEQ2; + __IO uint32_t RSEQ3; + __IO uint32_t JSEQ; + __IO uint32_t JDAT1; + __IO uint32_t JDAT2; + __IO uint32_t JDAT3; + __IO uint32_t JDAT4; + __IO uint32_t DAT; + __IO uint32_t DIFSEL; + __IO uint32_t CALFACT; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT3; +} ADC_Module; + +/** + * @brief OPAMP + */ +typedef struct +{ + __IO uint32_t CS1; + __IO uint32_t RES1[3]; + __IO uint32_t CS2; + __IO uint32_t RES2[3]; + __IO uint32_t LOCK; +} OPAMP_Module; + +/** + * @brief COMP_Single + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; +} COMP_SingleType; + +/** + * @brief COMP + */ +typedef struct +{ + __IO uint32_t INTEN; + __IO uint32_t LPCKSEL; + __IO uint32_t WINMODE; + __IO uint32_t LOCK; + COMP_SingleType Cmp1; + __IO uint32_t RES; + COMP_SingleType Cmp2; + __IO uint32_t CMP2OSEL; + __IO uint32_t VREFSCL; + __IO uint32_t TEST; + __IO uint32_t INTSTS; +} COMP_Module; + +/** + * @brief AFEC + */ + +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + //uint32_t RESERVED0; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; +} AFEC_Module; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMDT; + __IO uint32_t TMDL; + __IO uint32_t TMDH; +} CAN_TxMailBox_Param; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RMI; + __IO uint32_t RMDT; + __IO uint32_t RMDL; + __IO uint32_t RMDH; +} CAN_FIFOMailBox_Param; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_Param; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; + __IO uint32_t MSTS; + __IO uint32_t TSTS; + __IO uint32_t RFF0; + __IO uint32_t RFF1; + __IO uint32_t INTE; + __IO uint32_t ESTS; + __IO uint32_t BTIM; + uint32_t RESERVED0[88]; + CAN_TxMailBox_Param sTxMailBox[3]; + CAN_FIFOMailBox_Param sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMC; + __IO uint32_t FM1; + uint32_t RESERVED2; + __IO uint32_t FS1; + uint32_t RESERVED3; + __IO uint32_t FFA1; + uint32_t RESERVED4; + __IO uint32_t FA1; + uint32_t RESERVED5[8]; + CAN_FilterRegister_Param sFilterRegister[14]; +} CAN_Module; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t CRC32DAT; /*!< CRC data register */ + __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/ + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CRC32CTRL; /*!< CRC control register */ + __IO uint32_t CRC16CTRL; + __IO uint8_t CRC16DAT; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint16_t CRC16D; + uint16_t RESERVED4; + __IO uint8_t LRC; + uint8_t RESERVED5; + uint16_t RESERVED6; +} CRC_Module; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SOTTR; + __IO uint32_t DR12CH; + __IO uint32_t DL12CH; + __IO uint32_t DR8CH; + __IO uint32_t DATO; + +} DAC_Module; +/** + * @brief USB + */ + +typedef struct +{ + __IO uint32_t EP0; + __IO uint32_t EP1; + __IO uint32_t EP2; + __IO uint32_t EP3; + __IO uint32_t EP4; + __IO uint32_t EP5; + __IO uint32_t EP6; + __IO uint32_t EP7; + __IO uint32_t Reserve20h; + __IO uint32_t Reserve24h; + __IO uint32_t Reserve28h; + __IO uint32_t Reserve2Ch; + __IO uint32_t Reserve30h; + __IO uint32_t Reserve34h; + __IO uint32_t Reserve38h; + __IO uint32_t Reserve3Ch; + __IO uint32_t CTRL; + __IO uint32_t STS; + __IO uint32_t FN; + __IO uint32_t ADDR; + __IO uint32_t BUFTAB; +} USB_Module; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t CTRL; +} DBG_Module; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CHCFG; + __IO uint32_t TXNUM; + __IO uint32_t PADDR; + __IO uint32_t MADDR; + __IO uint32_t CHSEL; + +} DMA_ChannelType; + +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO DMA_ChannelType DMA_Channel[8]; +} DMA_Module; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMASK; /*offset 0x00*/ + __IO uint32_t EMASK; /*offset 0x04*/ + __IO uint32_t RT_CFG; /*offset 0x08*/ + __IO uint32_t FT_CFG; /*offset 0x0C*/ + __IO uint32_t SWIE; /*offset 0x10*/ + __IO uint32_t PEND; /*offset 0x14*/ + __IO uint32_t TS_SEL; /*offset 0x18*/ +} EXTI_Module; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t AC; + __IO uint32_t KEYR; + __IO uint32_t OPTKEY; + __IO uint32_t STS; + __IO uint32_t CTRL; + __IO uint32_t ADD; + __IO uint32_t OB2; + __IO uint32_t OB; + __IO uint32_t WRP; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t RESERVED2; + __IO uint32_t CAHR; +} FLASH_Module; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t WRP1_WRP0; + __IO uint32_t WRP3_WRP2; + __IO uint32_t USER2_RDP2; +} OB_Module; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t PMODE; /*offset 0x00*/ + __IO uint32_t POTYPE; /*offset 0x04*/ + __IO uint32_t SR; /*offset 0x08*/ + __IO uint32_t PUPD; /*offset 0x0C*/ + __IO uint32_t PID; /*offset 0x10*/ + __IO uint32_t POD; /*offset 0x14*/ + __IO uint32_t PBSC; /*offset 0x18*/ + __IO uint32_t PLOCK; /*offset 0x1C*/ + __IO uint32_t AFL; /*offset 0x20*/ + __IO uint32_t AFH; /*offset 0x24*/ + __IO uint32_t PBC; /*offset 0x28*/ + __IO uint32_t DS; /*offset 0x2C*/ + +} GPIO_Module; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t RMP_CFG; + __IO uint32_t EXTI_CFG[4]; +} AFIO_Module; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DAT; + uint16_t RESERVED4; + __IO uint16_t STS1; + uint16_t RESERVED5; + __IO uint16_t STS2; + uint16_t RESERVED6; + __IO uint16_t CLKCTRL; + uint16_t RESERVED7; + __IO uint16_t TMRISE; + uint16_t RESERVED8; +} I2C_Module; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t PREDIV; /*!< IWDG PREDIV */ + __IO uint32_t RELV; + __IO uint32_t STS; +} IWDG_Module; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; + __IO uint32_t STS1; + __IO uint32_t STS2; + __IO uint32_t STSCLR; +} PWR_Module; +/** + * @brief Low-Power Timer + */ +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO uint32_t INTEN; + __IO uint32_t CFG; + __IO uint32_t CTRL; + __IO uint32_t COMPx; + __IO uint32_t ARR; + __IO uint32_t CNT; + +} LPTIM_Module; +/** + * @brief Low-Power RCNT + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t INTSTS; + __IO uint32_t SCTRL; + __IO uint32_t CH0CFG0; + __IO uint32_t CH0CFG1; + __IO uint32_t CH1CFG0; + __IO uint32_t CH1CFG1; + __IO uint32_t CH2CFG0; + __IO uint32_t CH2CFG1; + __IO uint32_t CMD; + __IO uint32_t Reserve; + __IO uint32_t Reserve1; + __IO uint32_t CAL0; + __IO uint32_t CAL1; + __IO uint32_t CAL2; + __IO uint32_t CAL3; +} LPRCNT_Module; + + + + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t CLKINT; + __IO uint32_t APB2PRST; + __IO uint32_t APB1PRST; + __IO uint32_t AHBPCLKEN; + __IO uint32_t APB2PCLKEN; + __IO uint32_t APB1PCLKEN; + __IO uint32_t LDCTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t AHBPRST; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t RDCTRL; + __IO uint32_t Reserve0; + __IO uint32_t Reserve1; + __IO uint32_t PLLHSIPRE; + __IO uint32_t SRAM_CTRLSTS; +} RCC_Module; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved0; /*!< Reserved */ + __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */ + __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */ +} RTC_Module; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t STS; + uint16_t RESERVED2; + __IO uint16_t DAT; + uint16_t RESERVED3; + __IO uint16_t CRCPOLY; + uint16_t RESERVED4; + __IO uint16_t CRCRDAT; + uint16_t RESERVED5; + __IO uint16_t CRCTDAT; + uint16_t RESERVED6; + __IO uint16_t I2SCFG; + uint16_t RESERVED7; + __IO uint16_t I2SPREDIV; + uint16_t RESERVED8; +} SPI_Module; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint16_t SMCTRL; + uint16_t RESERVED1; + __IO uint16_t DINTEN; + uint16_t RESERVED2; + __IO uint32_t STS; + __IO uint16_t EVTGEN; + uint16_t RESERVED3; + __IO uint16_t CCMOD1; + uint16_t RESERVED4; + __IO uint16_t CCMOD2; + uint16_t RESERVED5; + __IO uint32_t CCEN; + __IO uint16_t CNT; + uint16_t RESERVED6; + __IO uint16_t PSC; + uint16_t RESERVED7; + __IO uint16_t AR; + uint16_t RESERVED8; + __IO uint16_t REPCNT; + uint16_t RESERVED9; + __IO uint16_t CCDAT1; + uint16_t RESERVED10; + __IO uint16_t CCDAT2; + uint16_t RESERVED11; + __IO uint16_t CCDAT3; + uint16_t RESERVED12; + __IO uint16_t CCDAT4; + uint16_t RESERVED13; + __IO uint16_t BKDT; + uint16_t RESERVED14; + __IO uint16_t DCTRL; + uint16_t RESERVED15; + __IO uint16_t DADDR; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t CCMOD3; + uint16_t RESERVED18; + __IO uint16_t CCDAT5; + uint16_t RESERVED19; + __IO uint16_t CCDAT6; + uint16_t RESERVED20; +} TIM_Module; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint16_t DAT; + uint16_t RESERVED1; + __IO uint16_t BRCF; + uint16_t RESERVED2; + __IO uint16_t CTRL1; + uint16_t RESERVED3; + __IO uint16_t CTRL2; + uint16_t RESERVED4; + __IO uint16_t CTRL3; + uint16_t RESERVED5; + __IO uint16_t GTP; + uint16_t RESERVED6; +} USART_Module; + +/** + * @brief Low-power Universal Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint8_t INTEN; + uint8_t RESERVED1; + uint16_t RESERVED2; + __IO uint16_t CTRL; + uint16_t RESERVED3; + __IO uint16_t BRCFG1; + uint16_t RESERVED4; + __IO uint8_t DAT; + uint8_t RESERVED5; + uint16_t RESERVED6; + __IO uint8_t BRCFG2; + uint8_t RESERVED7; + uint16_t RESERVED8; + __IO uint32_t WUDAT; +} LPUART_Module; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t STS; +} WWDG_Module; + +/** + * @brief LCD Controller + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FCTRL; + __IO uint32_t STS; + __IO uint32_t CLR; + uint32_t RESERVED; + __IO uint32_t RAM_COM[16]; +} LCD_Module; + +/** + * @brief Touch Sensor Controller + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CHNEN; + __IO uint32_t STS; + __IO uint32_t RESERVED; + __IO uint32_t ANA_CTRL; + __IO uint32_t ANA_SEL; + __IO uint32_t RESR[3]; +// __IO uint32_t RESR0; +// __IO uint32_t RESR1; +// __IO uint32_t RESR2; + __IO uint32_t THRHD[24]; +// __IO uint32_t THRHD0; +// __IO uint32_t THRHD1; +// __IO uint32_t THRHD2; +// __IO uint32_t THRHD3; +// __IO uint32_t THRHD4; +// __IO uint32_t THRHD5; +// __IO uint32_t THRHD6; +// __IO uint32_t THRHD7; +// __IO uint32_t THRHD8; +// __IO uint32_t THRHD9; +// __IO uint32_t THRHD10; +// __IO uint32_t THRHD11; +// __IO uint32_t THRHD12; +// __IO uint32_t THRHD13; +// __IO uint32_t THRHD14; +// __IO uint32_t THRHD15; +// __IO uint32_t THRHD16; +// __IO uint32_t THRHD17; +// __IO uint32_t THRHD18; +// __IO uint32_t THRHD19; +// __IO uint32_t THRHD20; +// __IO uint32_t THRHD21; +// __IO uint32_t THRHD22; +// __IO uint32_t THRHD23; + +} TSC_Module; + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */ +#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */ +#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */ +#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */ +#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000) + +/* APB1 */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000) +#define COMP_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define TSC_BASE (APB1PERIPH_BASE + 0x3400) +#define LPRCNT_BASE (APB1PERIPH_BASE + 0x3800) +#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00) +#define LCD_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00) +#define LPUART_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00) +#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/* APB2 */ +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00) +#define UART4_BASE (APB2PERIPH_BASE + 0x5000) +#define UART5_BASE (APB2PERIPH_BASE + 0x5400) + +/* AHB */ +#define DMA_BASE (AHBPERIPH_BASE + 0x8000) +#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008) +#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C) +#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030) +#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044) +#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058) +#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C) +#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080) +#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094) +#define ADC_BASE (AHBPERIPH_BASE + 0x8800) +#define RCC_BASE (AHBPERIPH_BASE + 0x9000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0xB000) +#define SAC_BASE (AHBPERIPH_BASE + 0xC000) +#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400) +#define MMU_BASE (AHBPERIPH_BASE + 0xCC00) + +#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +#define TIM2 ((TIM_Module*)TIM2_BASE) +#define TIM3 ((TIM_Module*)TIM3_BASE) +#define TIM4 ((TIM_Module*)TIM4_BASE) +#define TIM5 ((TIM_Module*)TIM5_BASE) +#define TIM6 ((TIM_Module*)TIM6_BASE) +#define TIM7 ((TIM_Module*)TIM7_BASE) +#define AFEC ((AFEC_Module*)AFEC_BASE) +#define OPAMP ((OPAMP_Module*)OPAMP_BASE) +#define COMP ((COMP_Module*)COMP_BASE) +#define RTC ((RTC_Module*)RTC_BASE) +#define WWDG ((WWDG_Module*)WWDG_BASE) +#define IWDG ((IWDG_Module*)IWDG_BASE) +#define TSC ((TSC_Module*)TSC_BASE) +#define LPRCNT ((LPRCNT_Module*)LPRCNT_BASE) +#define TIM9 ((TIM_Module*)TIM9_BASE) +#define LCD ((LCD_Module*)LCD_BASE) +#define USART2 ((USART_Module*)USART2_BASE) +#define USART3 ((USART_Module*)USART3_BASE) +#define LPTIM ((LPTIM_Module*)LPTIM_BASE) +#define LPUART ((LPUART_Module*)LPUART_BASE) +#define I2C1 ((I2C_Module*)I2C1_BASE) +#define I2C2 ((I2C_Module*)I2C2_BASE) +#define USB ((USB_Module*)USB_BASE) +#define CAN ((CAN_Module*)CAN_BASE) +#define PWR ((PWR_Module*)PWR_BASE) +#define DAC ((DAC_Module*)DAC_BASE) +#define AFIO ((AFIO_Module*)AFIO_BASE) +#define EXTI ((EXTI_Module*)EXTI_BASE) +#define GPIOA ((GPIO_Module*)GPIOA_BASE) +#define GPIOB ((GPIO_Module*)GPIOB_BASE) +#define GPIOC ((GPIO_Module*)GPIOC_BASE) +#define GPIOD ((GPIO_Module*)GPIOD_BASE) +#define TIM1 ((TIM_Module*)TIM1_BASE) +#define SPI1 ((SPI_Module*)SPI1_BASE) +#define TIM8 ((TIM_Module*)TIM8_BASE) +#define USART1 ((USART_Module*)USART1_BASE) +#define SPI2 ((SPI_Module*)SPI2_BASE) +#define UART4 ((USART_Module*)UART4_BASE) +#define UART5 ((USART_Module*)UART5_BASE) +#define DMA ((DMA_Module*)DMA_BASE) +#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE) +#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE) +#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE) +#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE) +#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE) +#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE) +#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE) +#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE) +#define ADC ((ADC_Module*)ADC_BASE) +#define RCC ((RCC_Module*)RCC_BASE) +#define FLASH ((FLASH_Module*)FLASH_R_BASE) +#define OBT ((OB_Module*)OB_BASE) +#define CRC ((CRC_Module*)CRC_BASE) + +#define DBG ((DBG_Module*)DBG_BASE) + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_CRC32DAT register *********************/ +#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_CRC32IDAT register ********************/ +#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CRC32CTRL register ********************/ +#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************** Bit definition for CRC16_CR register ********************/ +#define CRC16_CTRL_LITTLE ((uint8_t)0x02) +#define CRC16_CTRL_BIG ((uint8_t)0xFD) + +#define CRC16_CTRL_RESET ((uint8_t)0x04) +#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CTRL1 register ********************/ +#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */ +#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */ +#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */ + + +#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */ + +#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */ +#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */ +#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */ +#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */ +#define PWR_CTRL1_MRSEL1 ((uint16_t)0x0600) /*!< vddd Range1=1.1 V */ +#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */ +#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */ +/******************** Bit definition for PWR_CTRL2 register ********************/ +#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */ +#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */ +#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */ +#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */ +#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */ +#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */ +#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */ +#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */ +#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */ + +#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */ + + +/******************** Bit definition for PWR_CTRL3 register ********************/ +#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby mode. */ +#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */ +#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */ +#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */ +#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */ +#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */ +#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */ +#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */ +#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */ + +#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */ +#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */ +#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */ +#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */ +#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */ + +#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */ +#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */ +#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */ +/******************** Bit definition for PWR_STS1 register ********************/ +#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP0. */ +#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */ +#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */ +#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */ +#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */ + +/******************** Bit definition for PWR_STS2 register ********************/ +#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */ +#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */ +#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */ + +/******************** Bit definition for PWR_STSCLR register ********************/ +#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF0 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */ +#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */ + + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTRL register ********************/ +#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */ +#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */ +#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +/******************* Bit definition for RCC_CFG register *******************/ +/*!< SW configuration */ +#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */ +#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */ + +/*!< AHBPRES configuration */ +#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */ +#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< APB1PRES configuration */ +#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */ +#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< APB2PRES configuration */ +#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */ +#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< PLLSRC configuration */ +#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */ +#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + +/*!< PLLXTPRE configuration */ +#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ +#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */ +#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */ +#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */ + +#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ +#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ +#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ +#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ +#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ +#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ +#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ +#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */ +#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ +#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ +#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ +#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ +#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ +#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ +#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ +#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ +#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ +#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ +#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ +#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ +#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ +#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ +#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ +#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ +#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ +#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ +#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ +#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ +#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ + +/*!< USBPRES configuration */ +#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */ +#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ +#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */ +#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */ + +/*!< MCO configuration */ +#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */ +#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */ +#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */ +#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ +#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ +#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ +#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */ + +/*!< MCOPRE configuration */ +#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by + software to generate MCOPRE clock.) */ +#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */ +#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */ + +#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */ +#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */ +#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */ +#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */ +#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */ +#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */ +#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */ +#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */ +#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */ +#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */ +#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */ +#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */ +#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */ +#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */ +#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */ + +/*!<****************** Bit definition for RCC_CLKINT register ********************/ +#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */ +#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */ +#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */ +#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */ +#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */ +#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ +#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */ +#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */ +#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRST register *****************/ +#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ +#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ +#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */ +#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */ +#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */ + +/***************** Bit definition for RCC_APB1PRST register *****************/ +#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ +#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */ +#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */ +#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */ +#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */ +#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */ + +/****************** Bit definition for RCC_AHBPCLKEN register ******************/ +#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */ +#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ +#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */ +#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */ +#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */ + +/****************** Bit definition for RCC_APB2PCLKEN register *****************/ +#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ +#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ +#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ +#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */ +#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */ +#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */ + +/***************** Bit definition for RCC_APB1PCLKEN register ******************/ +#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ +#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */ +#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */ +#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */ +#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */ +#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */ +#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */ + +/******************* Bit definition for RCC_LDCTRL register *******************/ +#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */ +#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */ +#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC/LPRCNT clock source selection) */ + +#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */ +#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */ +#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */ + +/******************* Bit definition for RCC_CTRLSTS register ********************/ +#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */ +#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */ + +#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */ +#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */ + +#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */ +#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */ +#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */ +#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */ +#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */ +#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */ +#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */ + +#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */ +#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */ +#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */ +#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBPRST register ****************/ +#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */ +#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */ +#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */ + +/******************* Bit definition for RCC_CFG2 register ******************/ +/*!< ADCHPRE configuration */ +#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */ +#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */ +#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */ +#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */ +#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */ +#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */ +#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */ +#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */ +#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */ +#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ +#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ + +/*!< ADCPLLPRES configuration */ +#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */ +#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ +#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */ + +#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */ +#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */ +#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */ +#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */ +#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */ +#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */ +#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */ +#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */ +#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */ +#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */ +#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */ +#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */ +#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */ +#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */ + +/*!< ADC1MPRE configuration */ +#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */ +#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */ +#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */ +#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */ + +#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */ +#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */ +#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */ +#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */ +#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */ +#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */ +#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */ +#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */ +#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */ +#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */ +#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */ +#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */ +#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */ +#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */ +#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */ +#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */ +#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */ +#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */ +#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */ +#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */ +#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */ +#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */ +#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */ +#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */ +#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */ +#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */ +#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */ +#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */ +#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */ +#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */ +#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */ +#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */ + +/*!< ADC1MSEL configuration */ +#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */ + +#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */ +#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */ + +/*!< RNGCPRE configuration */ +#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */ +#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */ + +#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */ +#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */ +#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */ +#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */ +#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */ +#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */ +#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */ +#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */ +#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */ +#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */ +#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */ +#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */ +#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */ +#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */ +#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */ +#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */ +#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */ +#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */ +#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */ +#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */ +#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */ +#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */ +#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */ +#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */ +#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */ +#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */ +#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */ +#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */ +#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */ +#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */ +#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */ +#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */ + +/*!< TIMCLK_SEL configuration */ +#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */ + +#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */ +#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */ + +/******************* Bit definition for RCC_CFG3 register ******************/ +/*!< UCDREN configuration */ +#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */ + +#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */ +#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */ + +/*!< USBXTALESS configuration */ +#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */ + +#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */ +#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */ + +/*!< UCDR300MSEL configuration */ +#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */ + +#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */ +#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */ + +/*!< TRNG1MPRE configuration */ +#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */ +#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ +#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ +#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ + +#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */ +#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */ +#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */ +#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */ +#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */ +#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */ +#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */ +#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */ +#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */ +#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */ +#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */ +#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */ +#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */ +#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */ +#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */ +#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */ +#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */ +#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */ +#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */ +#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */ +#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */ +#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */ +#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */ +#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */ +#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */ +#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */ +#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */ +#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */ +#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */ +#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */ +#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */ + +/*!< TRNG1MSEL configuration */ +#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */ + +#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */ +#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */ + +/*!< TRNG1MEN configuration */ +#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */ +#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +/******************* Bit definition for RCC_RDCTRL register ******************/ +/*!< LPTIMSEL congiguration */ +#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */ +#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */ +#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */ + +/*!< LPUARTSEL congiguration */ +#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */ +#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */ +#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */ + +#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */ +#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */ +#define RCC_RDCTRL_LCDEN ((uint32_t)0x00000100) /*!< LCD clock enable */ +#define RCC_RDCTRL_LPRCNTEN ((uint32_t)0x00000200) /*!< LPRCNT clock enable */ +#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */ +#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */ +#define RCC_RDCTRL_LCDRST ((uint32_t)0x00001000) /*!< LCD reset */ +#define RCC_RDCTRL_LPRCNTRST ((uint32_t)0x00002000) /*!< LPRCNT reset */ + +/******************* Bit definition for RCC_PLLHSIPRE register ******************/ +/*!< PLLHSIPRE configuration */ +#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */ + +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */ + +/*!< PLLSRCDIV configuration */ +#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */ + +#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */ +#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */ + +/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/ +#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */ +#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */ +#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */ +#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */ + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD \ + ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */ +#define SCB_ICSR_RETTOBASE \ + ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT \ + ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 \ + ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 \ + ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 \ + ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 \ + ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 \ + ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 \ + ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 \ + ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 \ + ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA \ + ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND \ + ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \ + Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN \ + ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N \ + ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 \ + ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 \ + ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 \ + ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED \ + ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO \ + ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL \ + ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED \ + ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTSTS register ********************/ +#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ +#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTCLR register *******************/ +#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ +#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CHCFG1 register *******************/ +#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG2 register *******************/ +#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG3 register *******************/ +#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CHCFG4 register *******************/ +#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CHCFG5 register *******************/ +#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG6 register *******************/ +#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CHCFG7 register *******************/ +#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CHCFG8 register *******************/ +#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_TXNUM1 register ******************/ +#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM2 register ******************/ +#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM3 register ******************/ +#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM4 register ******************/ +#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM5 register ******************/ +#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM6 register ******************/ +#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM7 register ******************/ +#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_TXNUM8 register ******************/ +#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STS register ********************/ +#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */ +#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */ +#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */ + + +/******************* Bit definition for ADC_CTRL1 register ********************/ +#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTRL2 register ********************/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CTRL2_EXTJSEL \ + ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */ +#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPT1 register *******************/ +#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SAMPT2 register *******************/ +#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFFSET1 register *******************/ +#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFFSET2 register *******************/ +#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFFSET3 register *******************/ +#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFFSET4 register *******************/ +#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDGHIGH register ********************/ +#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDGLOW register ********************/ +#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSEQ1 register *******************/ +#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_RSEQ2 register *******************/ +#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_RSEQ3 register *******************/ +#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSEQ register *******************/ +#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */ +#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDAT1 register *******************/ +#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT2 register *******************/ +#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT3 register *******************/ +#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDAT4 register *******************/ +#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DAT register ********************/ +#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */ + +///******************** Bit definition for ADC_DIFSEL register ********************/ +//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */ +//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */ +//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */ +//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */ +//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */ +//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */ +//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */ +//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */ +//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */ +//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */ +//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */ +//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */ +//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */ +//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */ +//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */ +//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */ +//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */ +//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */ +//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */ +//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */ + +///******************** Bit definition for ADC_CALFACT register ********************/ +//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */ +//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */ +//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */ +//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */ +//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */ +//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */ +//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */ +//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */ + +//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */ +//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */ +//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */ +//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */ +//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */ +//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */ +//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */ +//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */ + +///******************** Bit definition for ADC_CTRL3 register ********************/ +//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */ +//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */ +//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */ + +//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */ +//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */ +//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */ +//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */ +//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */ +//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */ +//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */ +//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */ +//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */ +//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */ + +///******************** Bit definition for ADC_SAMPT3 register ********************/ +//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTRL register ********************/ +#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */ +#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */ +#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */ + +#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */ +#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */ +#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */ +#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */ + + + +/***************** Bit definition for DAC_SOTTR register ******************/ +#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */ + + +/***************** Bit definition for DAC_DR12CH register ******************/ +#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DL12CH register ******************/ +#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DR8CH register ******************/ +#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */ + + + + +/******************* Bit definition for DAC_DATO register *******************/ +#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */ + + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTRL1 register ********************/ +#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */ +#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */ +#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */ +#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */ +#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */ + +#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */ + +#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */ +#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */ +#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */ +#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */ +#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */ +#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */ + +#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/ +#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */ + +/******************* Bit definition for TIM_CTRL2 register ********************/ +#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */ +#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */ + +#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */ +#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */ + +/******************* Bit definition for TIM_SMCTRL register *******************/ +#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DINTEN register *******************/ +#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_STS register ********************/ +#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */ +#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */ +#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */ +#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */ +#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */ + +#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */ +#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */ + +/******************* Bit definition for TIM_EVTGEN register ********************/ +#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMOD1 register *******************/ +#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD2 register *******************/ +#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMOD3 register *******************/ +#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */ +#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */ + +#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */ + +#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */ +#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */ + +#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */ +#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +/******************* Bit definition for TIM_CCEN register *******************/ +#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */ + +#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */ +#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */ +#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */ +#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_AR register ********************/ +#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_REPCNT register ********************/ +#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCDAT1 register *******************/ +#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCDAT2 register *******************/ +#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCDAT3 register *******************/ +#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCDAT4 register *******************/ +#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_CCDAT5 register *******************/ +#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */ + +/******************* Bit definition for TIM_CCDAT6 register *******************/ +#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */ + +/******************* Bit definition for TIM_BKDT register *******************/ +#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCTRL register ********************/ +#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DADDR register *******************/ +#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ +/******************************************************************************/ +/* */ +/* Low Power Timer (LPTTIM) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for LPTIM_INTSTS register *******************/ +#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */ +#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */ + +/****************** Bit definition for LPTIM_INTCLR register *******************/ +#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */ +#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */ +#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */ +#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */ +#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */ + +/****************** Bit definition for LPTIM_INTEN register ********************/ +#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */ + +/****************** Bit definition for LPTIM_CFG register *******************/ +#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */ + +#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */ +#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */ +#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */ + +#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */ +#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */ + +#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */ +#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */ + +#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */ +#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */ +#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */ +#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */ + +#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */ +#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */ +#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */ +#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */ + +#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */ +#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */ + +#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */ +#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */ +#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */ +#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */ +#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */ +#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ +#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */ +/****************** Bit definition for LPTIM_CTRL register ********************/ +#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */ +#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */ +#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */ + +/****************** Bit definition for LPTIM_CMPT register *******************/ +#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */ + +/****************** Bit definition for LPTIM_AUTRLD register *******************/ +#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */ + +/****************** Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */ +/******************************************************************************/ +/* */ +/* Low-Power RCNT (LPRCNT) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for LPRCNT_CTRL register *******************/ +#define LPRCNT_CTRL_RPTTH ((uint32_t)0x0000FFFF) /*!< threshold of RCNT value, interrupt to wake up CPU when the value reach it */ +#define LPRCNT_CTRL_CLKDIV ((uint32_t)0x00030000) /*!< MSI clock to decide processing precision of sensors */ +#define LPRCNT_CTRL_AVGSEL ((uint32_t)0x000C0000) /*!< auto calculate average data for multi time */ +#define LPRCNT_CTRL_CNTDIR ((uint32_t)0x00100000) /*!< direction mode, turn lprcnt counting to the opposite direction */ + +#define LPRCNT_CTRL_PWRLVL ((uint32_t)0x00600000) /*!< power level select */ +#define LPRCNT_CTRL_PWRLVL1V5 ((uint32_t)0x00000000) /*!< power level select 1.5V */ +#define LPRCNT_CTRL_PWRLVL1V6 ((uint32_t)0x00200000) /*!< power level select 1.6V */ +#define LPRCNT_CTRL_PWRLVL1V8 ((uint32_t)0x00400000) /*!< power level select 1.8V */ +#define LPRCNT_CTRL_PWRLVL2V ((uint32_t)0x00600000) /*!< power level select 2.0V */ +#define LPRCNT_CTRL_CMPAUT ((uint32_t)0x00800000) /*!< enable to auto detect comparator stop */ +#define LPRCNT_CTRL_RCNTM ((uint32_t)0x01000000) /*!< RCNT RUN mode enable */ +#define LPRCNT_CTRL_CALM ((uint32_t)0x02000000) /*!< sensor data processing mode in RCNT debug mode */ +#define LPRCNT_CTRL_ALMPRD ((uint32_t)0x0C000000) /*!< the alarm sensor prescale */ +#define LPRCNT_CTRL_ALMPRD4 ((uint32_t)0x00000000) /*!< the alarm sensor prescale /4 */ +#define LPRCNT_CTRL_ALMPRD8 ((uint32_t)0x04000000) /*!< the alarm sensor prescale /8 */ +#define LPRCNT_CTRL_ALMPRD16 ((uint32_t)0x08000000) /*!< the alarm sensor prescale /16 */ +#define LPRCNT_CTRL_ALMPRD32 ((uint32_t)0x0C000000) /*!< the alarm sensor prescale /32 */ + +#define LPRCNT_CTRL_ALMIE ((uint32_t)0x10000000) /*!< the alarm sensor interruput enable */ +#define LPRCNT_CTRL_RPTIE ((uint32_t)0x20000000) /*!< reading interruput enable */ +#define LPRCNT_CTRL_CALIE ((uint32_t)0x40000000) /*!< the sensor debug mode interruput enable */ + +/******************** Bits definition for LPRCNT_INTSTS register *******************/ +#define LPRCNT_INTSTS_RPTVAL ((uint32_t)0x0000FFFF) /*!< lprcnt counter value report */ +#define LPRCNT_INTSTS_ALMIF ((uint32_t)0x00010000) /*!< RCNT alarm interrupt status*/ +#define LPRCNT_INTSTS_RPTIF ((uint32_t)0x00020000) /*!< RCNT read interrupt status*/ +#define LPRCNT_INTSTS_CALIF ((uint32_t)0x00040000) /*!< RCNT debug interrupt status*/ + +/******************** Bits definition for LPRCNT_SCTRL register *******************/ +#define LPRCNT_SCTRL_HSPRD ((uint32_t)0x000000FF) /*!< lprcnt high mode scan period */ +#define LPRCNT_SCTRL_SWT ((uint32_t)0x0000FF00) /*!< lprcnt high mode VS low mode switch time */ +#define LPRCNT_SCTRL_LSPRD ((uint32_t)0x03FF0000) /*!< lprcnt low mode scan period */ + +/******************** Bits definition for LPRCNT_CH0CFG0 register *******************/ +#define LPRCNT_CH0CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 0 damped threshold,less than to be detect damped */ +#define LPRCNT_CH0CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 0 undamped threshold,less than to be detect undamped */ +#define LPRCNT_CH0CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 0 damped threshold,less than to be detect damped */ + +/******************** Bits definition for LPRCNT_CH0CFG1 register *******************/ +#define LPRCNT_CH0CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */ +#define LPRCNT_CH0CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */ +#define LPRCNT_CH0CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */ +/******************** Bits definition for LPRCNT_CH1CFG0 register *******************/ +#define LPRCNT_CH1CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 1 damped threshold,less than to be detect damped */ +#define LPRCNT_CH1CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 1 undamped threshold,less than to be detect undamped */ +#define LPRCNT_CH1CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 1 damped threshold,less than to be detect damped */ + +/******************** Bits definition for LPRCNT_CH1CFG1 register *******************/ +#define LPRCNT_CH1CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */ +#define LPRCNT_CH1CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */ +#define LPRCNT_CH1CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */ +/******************** Bits definition for LPRCNT_CH2CFG0 register *******************/ +#define LPRCNT_CH2CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 2 damped threshold,less than to be detect damped */ +#define LPRCNT_CH2CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 2 undamped threshold,less than to be detect undamped */ +#define LPRCNT_CH2CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 2 damped threshold,less than to be detect damped */ + +/******************** Bits definition for LPRCNT_CH2CFG1 register *******************/ +#define LPRCNT_CH2CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */ +#define LPRCNT_CH2CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */ +#define LPRCNT_CH2CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */ + +/******************** Bits definition for LPRCNT_CMD register *******************/ +#define LPRCNT_CMD_START ((uint32_t)0x00000001) /*!< start LPRCNT processing */ +#define LPRCNT_CMD_STOP ((uint32_t)0x00000002) /*!< stop LPRCNT processing */ +#define LPRCNT_CMD_CLRCNT ((uint32_t)0x00000004) /*!< clear LPRCNT count */ + +/******************** Bits definition for LPRCNT_CAL0 register *******************/ +#define LPRCNT_CAL0_CH0CNT ((uint32_t)0x000000FF) /*!< sensor channel 0,comparator output valid count */ + +#define LPRCNT_CAL0_CH0STS_UND ((uint32_t)0x00000000) /*!< sensor channel 0 undamped state */ +#define LPRCNT_CAL0_CH0STS_MID ((uint32_t)0x00000100) /*!< sensor channel 0 middle state */ +#define LPRCNT_CAL0_CH0STS_DAM ((uint32_t)0x00000200) /*!< sensor channel 0 damped state */ + +#define LPRCNT_CAL0_CH1CNT ((uint32_t)0x00FF0000) /*!< sensor channel 1,comparator output valid count */ + +#define LPRCNT_CAL0_CH1STS_UND ((uint32_t)0x00000000) /*!< sensor channel 1 undamped state */ +#define LPRCNT_CAL0_CH1STS_MID ((uint32_t)0x01000000) /*!< sensor channel 1 middle state */ +#define LPRCNT_CAL0_CH1STS_DAM ((uint32_t)0x02000000) /*!< sensor channel 1 damped state */ +/******************** Bits definition for LPRCNT_CAL1 register *******************/ +#define LPRCNT_CAL1_CH2CNT ((uint32_t)0x000000FF) /*!< sensor channel 0,comparator output valid count */ + +#define LPRCNT_CAL1_CH2STS_UND ((uint32_t)0x00000000) /*!< sensor channel 2 undamped state */ +#define LPRCNT_CAL1_CH2STS_MID ((uint32_t)0x00000100) /*!< sensor channel 2 middle state */ +#define LPRCNT_CAL1_CH2STS_DAM ((uint32_t)0x00000200) /*!< sensor channel 2 damped state */ + +/******************** Bits definition for LPRCNT_CAL2 register *******************/ +#define LPRCNT_CAL2_DACSET ((uint32_t)0x0000003F) /*!< sensor channel DAC setup time */ +#define LPRCNT_CAL2_CMPSET ((uint32_t)0x00003F00) /*!< sensor channel comparator setup time */ +#define LPRCNT_CAL2_GAP ((uint32_t)0x000F0000) /*!< charge to discharge gap time length */ +#define LPRCNT_CAL2_RCNTADJ ((uint32_t)0x00F00000) /*!< adjust number for slow switch fast lost */ +#define LPRCNT_CAL2_SAMPMODE ((uint32_t)0x02000000) /*!< LPRCNT module sample mode */ + +/******************** Bits definition for LPRCNT_CAL3 register *******************/ +#define LPRCNT_CAL3_CMP_AUTO_MODE ((uint32_t)0x00000040) /*!< when enter the mode of auto detect comparator stop, the period of duty wait clock */ +#define LPRCNT_CAL3_PWR_DUR_EN ((uint32_t)0x00000080) /*!< LDO powering sensors by time duration */ +#define LPRCNT_CAL3_STAT_CLR_CTRL ((uint32_t)0x00000100) /*!< Whether clear state on fast mode to slow mode */ +#define LPRCNT_CAL3_DAC_CMP_ALWSON ((uint32_t)0x00000200) /*!< DAC & CMP always on enable while 1 round sampling */ +#define LPRCNT_CAL3_CMP_HYSEL ((uint32_t)0x00000C00) /*!< Comparator hysteresis selection */ +#define LPRCNT_CAL3_CMP_HYSEL_NULL ((uint32_t)0x00000000) /*!< Comparator hysteresis disable */ +#define LPRCNT_CAL3_CMP_HYSEL_LOW ((uint32_t)0x00000400) /*!< select low Comparator hysteresis */ +#define LPRCNT_CAL3_CMP_HYSEL_MID ((uint32_t)0x00000800) /*!< select middle Comparator hysteresis */ +#define LPRCNT_CAL3_CMP_HYSEL_HIGH ((uint32_t)0x00000C00) /*!< select high Comparator hysteresis */ +#define LPRCNT_CAL3_CMP_INMSEL ((uint32_t)0x00007000) /*!< COMP input minus selection bits */ +#define LPRCNT_CAL3_CMP_LPEN ((uint32_t)0x00008000) /*!< COMP low power enable */ + +#define LPRCNT_CAL3_ANGFILEN ((uint32_t)0x00200000) /*!< Analog filtering anable bit */ +#define LPRCNT_CAL3_DIGFILPH ((uint32_t)0x00400000) /*!< Digital filter phase control */ +#define LPRCNT_CAL3_DIGFILPH_P ((uint32_t)0x00000000) /*!< Digital filter phase selection positive */ +#define LPRCNT_CAL3_DIGFILPH_N ((uint32_t)0x00400000) /*!< Digital filter phase selection negative */ +#define LPRCNT_CAL3_FILTH ((uint32_t)0x01800000) /*!< Filter threshold control*/ +#define LPRCNT_CAL3_DIGFILEN ((uint32_t)0x02000000) /*!< Digital filtering anable bit */ +#define LPRCNT_CAL3_CH0MAP ((uint32_t)0x0C000000) /*!< CH0 map to which sensor select */ +#define LPRCNT_CAL3_CH1MAP ((uint32_t)0x30000000) /*!< CH1 map to which sensor select */ +#define LPRCNT_CAL3_CH2MAP ((uint32_t)0xC0000000) /*!< CH2 map to which sensor select */ +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TSH register *******************/ +#define RTC_TSH_APM ((uint32_t)0x00400000) +#define RTC_TSH_HOT ((uint32_t)0x00300000) +#define RTC_TSH_HOT_0 ((uint32_t)0x00100000) +#define RTC_TSH_HOT_1 ((uint32_t)0x00200000) +#define RTC_TSH_HOU ((uint32_t)0x000F0000) +#define RTC_TSH_HOU_0 ((uint32_t)0x00010000) +#define RTC_TSH_HOU_1 ((uint32_t)0x00020000) +#define RTC_TSH_HOU_2 ((uint32_t)0x00040000) +#define RTC_TSH_HOU_3 ((uint32_t)0x00080000) +#define RTC_TSH_MIT ((uint32_t)0x00007000) +#define RTC_TSH_MIT_0 ((uint32_t)0x00001000) +#define RTC_TSH_MIT_1 ((uint32_t)0x00002000) +#define RTC_TSH_MIT_2 ((uint32_t)0x00004000) +#define RTC_TSH_MIU ((uint32_t)0x00000F00) +#define RTC_TSH_MIU_0 ((uint32_t)0x00000100) +#define RTC_TSH_MIU_1 ((uint32_t)0x00000200) +#define RTC_TSH_MIU_2 ((uint32_t)0x00000400) +#define RTC_TSH_MIU_3 ((uint32_t)0x00000800) +#define RTC_TSH_SCT ((uint32_t)0x00000070) +#define RTC_TSH_SCT_0 ((uint32_t)0x00000010) +#define RTC_TSH_SCT_1 ((uint32_t)0x00000020) +#define RTC_TSH_SCT_2 ((uint32_t)0x00000040) +#define RTC_TSH_SCU ((uint32_t)0x0000000F) +#define RTC_TSH_SCU_0 ((uint32_t)0x00000001) +#define RTC_TSH_SCU_1 ((uint32_t)0x00000002) +#define RTC_TSH_SCU_2 ((uint32_t)0x00000004) +#define RTC_TSH_SCU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_DATE register *******************/ +#define RTC_DATE_YRT ((uint32_t)0x00F00000) +#define RTC_DATE_YRT_0 ((uint32_t)0x00100000) +#define RTC_DATE_YRT_1 ((uint32_t)0x00200000) +#define RTC_DATE_YRT_2 ((uint32_t)0x00400000) +#define RTC_DATE_YRT_3 ((uint32_t)0x00800000) +#define RTC_DATE_YRU ((uint32_t)0x000F0000) +#define RTC_DATE_YRU_0 ((uint32_t)0x00010000) +#define RTC_DATE_YRU_1 ((uint32_t)0x00020000) +#define RTC_DATE_YRU_2 ((uint32_t)0x00040000) +#define RTC_DATE_YRU_3 ((uint32_t)0x00080000) +#define RTC_DATE_WDU ((uint32_t)0x0000E000) +#define RTC_DATE_WDU_0 ((uint32_t)0x00002000) +#define RTC_DATE_WDU_1 ((uint32_t)0x00004000) +#define RTC_DATE_WDU_2 ((uint32_t)0x00008000) +#define RTC_DATE_MOT ((uint32_t)0x00001000) +#define RTC_DATE_MOU ((uint32_t)0x00000F00) +#define RTC_DATE_MOU_0 ((uint32_t)0x00000100) +#define RTC_DATE_MOU_1 ((uint32_t)0x00000200) +#define RTC_DATE_MOU_2 ((uint32_t)0x00000400) +#define RTC_DATE_MOU_3 ((uint32_t)0x00000800) +#define RTC_DATE_DAT ((uint32_t)0x00000030) +#define RTC_DATE_DAT_0 ((uint32_t)0x00000010) +#define RTC_DATE_DAT_1 ((uint32_t)0x00000020) +#define RTC_DATE_DAU ((uint32_t)0x0000000F) +#define RTC_DATE_DAU_0 ((uint32_t)0x00000001) +#define RTC_DATE_DAU_1 ((uint32_t)0x00000002) +#define RTC_DATE_DAU_2 ((uint32_t)0x00000004) +#define RTC_DATE_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_CTRL register *******************/ +#define RTC_CTRL_COEN ((uint32_t)0x00800000) +#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000) +#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000) +#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000) +#define RTC_CTRL_OPOL ((uint32_t)0x00100000) +#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000) +#define RTC_CTRL_BAKP ((uint32_t)0x00040000) +#define RTC_CTRL_SU1H ((uint32_t)0x00020000) +#define RTC_CTRL_AD1H ((uint32_t)0x00010000) +#define RTC_CTRL_TSIEN ((uint32_t)0x00008000) +#define RTC_CTRL_WTIEN ((uint32_t)0x00004000) +#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000) +#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000) +#define RTC_CTRL_TSEN ((uint32_t)0x00000800) +#define RTC_CTRL_WTEN ((uint32_t)0x00000400) +#define RTC_CTRL_ALBEN ((uint32_t)0x00000200) +#define RTC_CTRL_ALAEN ((uint32_t)0x00000100) + +#define RTC_CTRL_HFMT ((uint32_t)0x00000040) +#define RTC_CTRL_BYPS ((uint32_t)0x00000020) +#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010) +#define RTC_CTRL_TEDGE ((uint32_t)0x00000008) +#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007) +#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001) +#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002) +#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004) + +/******************** Bits definition for RTC_INITSTS register ******************/ +#define RTC_INITSTS_RECPF ((uint32_t)0x00010000) +#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000) +#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000) +#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000) +#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000) +#define RTC_INITSTS_TISF ((uint32_t)0x00000800) +#define RTC_INITSTS_WTF ((uint32_t)0x00000400) +#define RTC_INITSTS_ALBF ((uint32_t)0x00000200) +#define RTC_INITSTS_ALAF ((uint32_t)0x00000100) +#define RTC_INITSTS_INITM ((uint32_t)0x00000080) +#define RTC_INITSTS_INITF ((uint32_t)0x00000040) +#define RTC_INITSTS_RSYF ((uint32_t)0x00000020) +#define RTC_INITSTS_INITSF ((uint32_t)0x00000010) +#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008) +#define RTC_INITSTS_WTWF ((uint32_t)0x00000004) +#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002) +#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_PRE register *****************/ +#define RTC_PRE_DIVA ((uint32_t)0x007F0000) +#define RTC_PRE_DIVS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_WKUPT register *****************/ +#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF) + + +/******************** Bits definition for RTC_ALARMA register ***************/ +#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMA_DTT ((uint32_t)0x30000000) +#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMA_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMA_APM ((uint32_t)0x00400000) +#define RTC_ALARMA_HOT ((uint32_t)0x00300000) +#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMA_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMA_MIT ((uint32_t)0x00007000) +#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMA_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMA_SET ((uint32_t)0x00000070) +#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMA_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_ALARMB register ***************/ +#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMB_DTT ((uint32_t)0x30000000) +#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMB_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMB_APM ((uint32_t)0x00400000) +#define RTC_ALARMB_HOT ((uint32_t)0x00300000) +#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMB_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMB_MIT ((uint32_t)0x00007000) +#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMB_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMB_SET ((uint32_t)0x00000070) +#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMB_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_WRP register ******************/ +#define RTC_WRP_PKEY ((uint32_t)0x000000FF) + +/******************** Bits definition for RTC_SUBS register ******************/ +#define RTC_SUBS_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_SCTRL register ***************/ +#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF) +#define RTC_SCTRL_AD1S ((uint32_t)0x80000000) + +/******************** Bits definition for RTC_TST register *****************/ +#define RTC_TST_APM ((uint32_t)0x00400000) +#define RTC_TST_HOT ((uint32_t)0x00300000) +#define RTC_TST_HOT_0 ((uint32_t)0x00100000) +#define RTC_TST_HOT_1 ((uint32_t)0x00200000) +#define RTC_TST_HOU ((uint32_t)0x000F0000) +#define RTC_TST_HOU_0 ((uint32_t)0x00010000) +#define RTC_TST_HOU_1 ((uint32_t)0x00020000) +#define RTC_TST_HOU_2 ((uint32_t)0x00040000) +#define RTC_TST_HOU_3 ((uint32_t)0x00080000) +#define RTC_TST_MIT ((uint32_t)0x00007000) +#define RTC_TST_MIT_0 ((uint32_t)0x00001000) +#define RTC_TST_MIT_1 ((uint32_t)0x00002000) +#define RTC_TST_MIT_2 ((uint32_t)0x00004000) +#define RTC_TST_MIU ((uint32_t)0x00000F00) +#define RTC_TST_MIU_0 ((uint32_t)0x00000100) +#define RTC_TST_MIU_1 ((uint32_t)0x00000200) +#define RTC_TST_MIU_2 ((uint32_t)0x00000400) +#define RTC_TST_MIU_3 ((uint32_t)0x00000800) +#define RTC_TST_SET ((uint32_t)0x00000070) +#define RTC_TST_SET_0 ((uint32_t)0x00000010) +#define RTC_TST_SET_1 ((uint32_t)0x00000020) +#define RTC_TST_SET_2 ((uint32_t)0x00000040) +#define RTC_TST_SEU ((uint32_t)0x0000000F) +#define RTC_TST_SEU_0 ((uint32_t)0x00000001) +#define RTC_TST_SEU_1 ((uint32_t)0x00000002) +#define RTC_TST_SEU_2 ((uint32_t)0x00000004) +#define RTC_TST_SEU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSD register *****************/ +#define RTC_TSD_YRT ((uint32_t)0x00F00000) +#define RTC_TSD_YRT_0 ((uint32_t)0x00100000) +#define RTC_TSD_YRT_1 ((uint32_t)0x00200000) +#define RTC_TSD_YRT_2 ((uint32_t)0x00400000) +#define RTC_TSD_YRT_3 ((uint32_t)0x00800000) +#define RTC_TSD_YRU ((uint32_t)0x000F0000) +#define RTC_TSD_YRU_0 ((uint32_t)0x00010000) +#define RTC_TSD_YRU_1 ((uint32_t)0x00020000) +#define RTC_TSD_YRU_2 ((uint32_t)0x00040000) +#define RTC_TSD_YRU_3 ((uint32_t)0x00080000) + +#define RTC_TSD_WDU ((uint32_t)0x0000E000) +#define RTC_TSD_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSD_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSD_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSD_MOT ((uint32_t)0x00001000) +#define RTC_TSD_MOU ((uint32_t)0x00000F00) +#define RTC_TSD_MOU_0 ((uint32_t)0x00000100) +#define RTC_TSD_MOU_1 ((uint32_t)0x00000200) +#define RTC_TSD_MOU_2 ((uint32_t)0x00000400) +#define RTC_TSD_MOU_3 ((uint32_t)0x00000800) +#define RTC_TSD_DAT ((uint32_t)0x00000030) +#define RTC_TSD_DAT_0 ((uint32_t)0x00000010) +#define RTC_TSD_DAT_1 ((uint32_t)0x00000020) +#define RTC_TSD_DAU ((uint32_t)0x0000000F) +#define RTC_TSD_DAU_0 ((uint32_t)0x00000001) +#define RTC_TSD_DAU_1 ((uint32_t)0x00000002) +#define RTC_TSD_DAU_2 ((uint32_t)0x00000004) +#define RTC_TSD_DAU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSSS register ****************/ +#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CALIB register *****************/ +#define RTC_CALIB_CP ((uint32_t)0x00008000) +#define RTC_CALIB_CW8 ((uint32_t)0x00004000) +#define RTC_CALIB_CW16 ((uint32_t)0x00002000) +#define RTC_CALIB_CM ((uint32_t)0x000001FF) +#define RTC_CALIB_CM_0 ((uint32_t)0x00000001) +#define RTC_CALIB_CM_1 ((uint32_t)0x00000002) +#define RTC_CALIB_CM_2 ((uint32_t)0x00000004) +#define RTC_CALIB_CM_3 ((uint32_t)0x00000008) +#define RTC_CALIB_CM_4 ((uint32_t)0x00000010) +#define RTC_CALIB_CM_5 ((uint32_t)0x00000020) +#define RTC_CALIB_CM_6 ((uint32_t)0x00000040) +#define RTC_CALIB_CM_7 ((uint32_t)0x00000080) +#define RTC_CALIB_CM_8 ((uint32_t)0x00000100) + +/******************** Bits definition for RTC_TMPCFG register ****************/ + +#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000) +#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000) +#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000) +#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000) +#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000) +#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000) +#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000) +#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000) +#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000) +#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000) +#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000) +#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800) +#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800) +#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000) +#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700) +#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080) +#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040) +#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020) +#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010) +#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008) +#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004) +#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002) +#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_ALRMASS register *************/ +#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_ALRMBSS register *************/ +#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_OPT register *******************/ +#define RTC_OPT_TYPE ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/ +#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008) +#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004) +#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001) +/******************** Bits definition for RTC_TSCWKUPCNT register *******************/ +#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF) +/******************** Bits definition for RTC_BKP1 register ****************/ +#define RTC_BKP1 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP2 register ****************/ +#define RTC_BKP2 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP3 register ****************/ +#define RTC_BKP3 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP4 register ****************/ +#define RTC_BKP4 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP5 register ****************/ +#define RTC_BKP5 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP6 register ****************/ +#define RTC_BKP6 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP7 register ****************/ +#define RTC_BKP7 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP8 register ****************/ +#define RTC_BKP8 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP9 register ****************/ +#define RTC_BKP9 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP10 register ****************/ +#define RTC_BKP10 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP11 register ***************/ +#define RTC_BKP11 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP12register ***************/ +#define RTC_BKP12 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP13 register ***************/ +#define RTC_BKP13 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP14 register ***************/ +#define RTC_BKP14 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP15 register ***************/ +#define RTC_BKP15 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP16 register ***************/ +#define RTC_BKP16 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP17register ***************/ +#define RTC_BKP17 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP18 register ***************/ +#define RTC_BKP18 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP19 register ***************/ +#define RTC_BKP19 ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP20 register ***************/ +#define RTC_BKP20 ((uint32_t)0xFFFFFFFF) + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KEY register ********************/ +#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PREDIV register ********************/ +#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RELV register *******************/ +#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STS register ********************/ +#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTRL register ********************/ +#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFG register *******************/ +#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */ +#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STS register ********************/ +#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for XFMC_BCR1 register *******************/ +#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BCR2 register *******************/ +#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for XFMC_BTR1 register ******************/ +#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BTR2 register *******************/ +#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR1 register ******************/ +#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_BWTR2 register ******************/ +#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for XFMC_PCR2 register *******************/ +#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for XFMC_PCR3 register *******************/ +#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */ + +#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for XFMC_SR2 register *******************/ +//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/******************* Bit definition for XFMC_SR3 register *******************/ +//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable +// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection +// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge +// detection Enable bit */ +#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */ + +/****************** Bit definition for XFMC_PMEM2 register ******************/ +#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PMEM3 register ******************/ +#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT2 register ******************/ +#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_PATT3 register ******************/ +#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for XFMC_ECCR2 register ******************/ +#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for XFMC_ECCR3 register ******************/ +#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */ +#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCTRL register ********************/ +#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */ +#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */ +#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */ +#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */ + +/******************* Bit definition for CAN_MSTS register ********************/ +#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTS register ********************/ +#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFF0 register *******************/ +#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */ +#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */ +#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */ +#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFF1 register *******************/ +#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */ +#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */ +#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */ +#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTE register *******************/ +#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */ +#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */ +#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */ +#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTIM register ********************/ +#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMC register ********************/ +#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1 register *******************/ +#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1 register *******************/ +#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1 register *******************/ +#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */ +#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */ +#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */ +#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */ +#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */ +#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */ +#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */ +#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */ +#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */ +#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */ +#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */ +#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */ +#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */ +#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */ +#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1 register *******************/ +#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTRL1 register ********************/ +#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTRL2 register ********************/ +#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STS register ********************/ +#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DAT register ********************/ +#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPOLY register ******************/ +#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_CRCRDAT register ******************/ +#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_CRCTDAT register ******************/ +#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFG register *****************/ +#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPREDIV register *******************/ +#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTRL1 register ********************/ +#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CTRL2 register ********************/ +#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DAT register ********************/ +#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_STS1 register ********************/ +#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_STS2 register ********************/ +#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CLKCTRL register ********************/ +#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_STS register *******************/ +#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DAT register *******************/ +#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRCF register *******************/ +#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTRL1 register *******************/ +#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */ +#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */ + +/****************** Bit definition for USART_CTRL2 register *******************/ +#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CTRL3 register *******************/ +#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ + +/****************** Bit definition for USART_GTP register ******************/ +#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Low-power Universal Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for LPUART_STS register ******************/ +#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */ +#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */ +#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */ +#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */ +#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */ +#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */ +#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */ +#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */ +#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */ + +/****************** Bit definition for LPUART_INTEN register ******************/ +#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */ +#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */ +#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */ +#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/ +#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */ +#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */ +#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */ + +/****************** Bit definition for LPUART_CTRL register ******************/ +#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */ +#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */ +#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */ +#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */ +#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */ +#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */ +#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */ +#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */ +#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */ +#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */ +#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */ +#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */ +#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */ + +/****************** Bit definition for LPUART_BRCFG1 register ******************/ +#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */ + +/****************** Bit definition for LPUART_DAT register ******************/ +#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */ + +/****************** Bit definition for LPUART_BRCFG2 register ******************/ +#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */ + +/****************** Bit definition for LPUART_WUDAT register ******************/ +#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBG_ID register *****************/ +#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBG_CTRL register *******************/ +#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ + +#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */ +#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */ +#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */ +#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/ +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_AC register ******************/ +#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */ +#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */ +#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */ +#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */ + +#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ +#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ +#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */ +#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */ +#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */ +#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */ +#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */ +#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */ + +/****************** Bit definition for FLASH_KEY register ******************/ +#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */ + +/***************** Bit definition for FLASH_OPTKEY register ****************/ +#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */ +#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */ +#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */ + +/******************* Bit definition for FLASH_CTRL register *******************/ +#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */ +#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */ +#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */ + +/******************* Bit definition for FLASH_ADD register *******************/ +#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OB2 register *******************/ +#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */ +#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */ +#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */ +#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */ + +/****************** Bit definition for FLASH_OB register *******************/ +#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */ + +#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */ +#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */ + +#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */ +#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */ +#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */ + +/****************** Bit definition for FLASH_WRP register ******************/ +#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/****************** Bit definition for FLASH_CAHR register ******************/ +#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */ +#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */ +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for OptionByte USER ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for OptionByte Data0 *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte Data1 *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for OptionByte WRP0 ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP1 ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP2 ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte WRP3 ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for OptionByte RDP2 *******************/ +#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */ +#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */ + +/****************** Bit definition for OptionByte USER2 ******************/ +#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_PMODE register *******************/ + + +#define GPIO_PMODE0_Pos (0) +#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE0 GPIO_PMODE0_Msk +#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE1_Pos (2) +#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE1 GPIO_PMODE1_Msk +#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE2_Pos (4) +#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE2 GPIO_PMODE2_Msk +#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE3_Pos (6) +#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE3 GPIO_PMODE3_Msk +#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE4_Pos (8) +#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE4 GPIO_PMODE4_Msk +#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE5_Pos (10) +#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE5 GPIO_PMODE5_Msk +#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE6_Pos (12) +#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE6 GPIO_PMODE6_Msk +#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE7_Pos (14) +#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE7 GPIO_PMODE7_Msk +#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE8_Pos (16) +#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE8 GPIO_PMODE8_Msk +#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE9_Pos (18) +#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE9 GPIO_PMODE9_Msk +#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE10_Pos (20) +#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE10 GPIO_PMODE10_Msk +#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE11_Pos (22) +#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE11 GPIO_PMODE11_Msk +#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE12_Pos (24) +#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE12 GPIO_PMODE12_Msk +#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE13_Pos (26) +#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE13 GPIO_PMODE13_Msk +#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE14_Pos (28) +#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE14 GPIO_PMODE14_Msk +#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */ + +#define GPIO_PMODE15_Pos (30) +#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ +#define GPIO_PMODE15 GPIO_PMODE15_Msk +#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */ +#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */ +#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */ +#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */ + + + + +/****************** Bit definition for GPIO_POTYPER register *****************/ +#define GPIO_POTYPE_POT_0 (0x00000001) +#define GPIO_POTYPE_POT_1 (0x00000002) +#define GPIO_POTYPE_POT_2 (0x00000004) +#define GPIO_POTYPE_POT_3 (0x00000008) +#define GPIO_POTYPE_POT_4 (0x00000010) +#define GPIO_POTYPE_POT_5 (0x00000020) +#define GPIO_POTYPE_POT_6 (0x00000040) +#define GPIO_POTYPE_POT_7 (0x00000080) +#define GPIO_POTYPE_POT_8 (0x00000100) +#define GPIO_POTYPE_POT_9 (0x00000200) +#define GPIO_POTYPE_POT_10 (0x00000400) +#define GPIO_POTYPE_POT_11 (0x00000800) +#define GPIO_POTYPE_POT_12 (0x00001000) +#define GPIO_POTYPE_POT_13 (0x00002000) +#define GPIO_POTYPE_POT_14 (0x00004000) +#define GPIO_POTYPE_POT_15 (0x00008000) + + +/******************* Bit definition for GPIO_PUPDR register ******************/ +#define GPIO_PUPD0_Pos (0) +#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD0 GPIO_PUPD0_Msk +#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD1_Pos (2) +#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD1 GPIO_PUPD1_Msk +#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD2_Pos (4) +#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD2 GPIO_PUPD2_Msk +#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD3_Pos (6) +#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD3 GPIO_PUPD3_Msk +#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD4_Pos (8) +#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD4 GPIO_PUPD4_Msk +#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD5_Pos (10) +#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD5 GPIO_PUPD5_Msk +#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD6_Pos (12) +#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD6 GPIO_PUPD6_Msk +#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD7_Pos (14) +#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD7 GPIO_PUPD7_Msk +#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD8_Pos (16) +#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD8 GPIO_PUPD8_Msk +#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD9_Pos (18) +#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD9 GPIO_PUPD9_Msk +#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD10_Pos (20) +#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD10 GPIO_PUPD10_Msk +#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD11_Pos (22) +#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD11 GPIO_PUPD11_Msk +#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD12_Pos (24) +#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD12 GPIO_PUPD12_Msk +#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD13_Pos (26) +#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD13 GPIO_PUPD13_Msk +#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD14_Pos (28) +#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD14 GPIO_PUPD14_Msk +#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */ + +#define GPIO_PUPD15_Pos (30) +#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */ +#define GPIO_PUPD15 GPIO_PUPD15_Msk +#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */ +#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */ +#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */ + + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_POD register *******************/ +#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/****************** Bit definition for GPIO_AFL register *******************/ +#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */ +#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */ +#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */ +#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */ +#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */ +#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */ +#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */ +#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */ + +/****************** Bit definition for GPIO_AFH register *******************/ +#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */ +#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */ +#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */ +#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */ +#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */ +#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */ +#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */ +#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */ + + +/******************* Bit definition for GPIO_DS register ******************/ +#define GPIO_DS0_Pos (0) +#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ +#define GPIO_DS0 GPIO_DS0_Msk +#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */ +#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */ +#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */ +#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */ + +#define GPIO_DS1_Pos (2) +#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ +#define GPIO_DS1 GPIO_DS1_Msk +#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */ +#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */ +#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */ +#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */ + +#define GPIO_DS2_Pos (4) +#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ +#define GPIO_DS2 GPIO_DS2_Msk +#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */ +#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */ +#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */ +#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */ + +#define GPIO_DS3_Pos (6) +#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ +#define GPIO_DS3 GPIO_DS3_Msk +#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */ +#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */ +#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */ +#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */ + +#define GPIO_DS4_Pos (8) +#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ +#define GPIO_DS4 GPIO_DS4_Msk +#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */ +#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */ +#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */ +#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */ + +#define GPIO_DS5_Pos (10) +#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ +#define GPIO_DS5 GPIO_DS5_Msk +#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */ +#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */ +#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */ +#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */ + +#define GPIO_DS6_Pos (12) +#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ +#define GPIO_DS6 GPIO_DS6_Msk +#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */ +#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */ +#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */ +#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */ + +#define GPIO_DS7_Pos (14) +#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ +#define GPIO_DS7 GPIO_DS7_Msk +#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */ +#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */ +#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */ +#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */ + + +#define GPIO_DS8_Pos (16) +#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ +#define GPIO_DS8 GPIO_DS8_Msk +#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */ +#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */ +#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */ +#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */ + +#define GPIO_DS9_Pos (18) +#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ +#define GPIO_DS9 GPIO_DS9_Msk +#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */ +#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */ +#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */ +#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */ + +#define GPIO_DS10_Pos (20) +#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ +#define GPIO_DS10 GPIO_DS10_Msk +#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */ +#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */ +#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */ +#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */ + +#define GPIO_DS11_Pos (22) +#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ +#define GPIO_DS11 GPIO_DS11_Msk +#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */ +#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */ +#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */ +#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */ + +#define GPIO_DS12_Pos (24) +#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ +#define GPIO_DS12 GPIO_DS12_Msk +#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */ +#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */ +#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */ +#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */ + +#define GPIO_DS13_Pos (26) +#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ +#define GPIO_DS13 GPIO_DS13_Msk +#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */ +#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */ +#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */ +#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */ + +#define GPIO_DS14_Pos (28) +#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ +#define GPIO_DS14 GPIO_DS14_Msk +#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */ +#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */ +#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */ +#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */ + +#define GPIO_DS15_Pos (30) +#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ +#define GPIO_DS15 GPIO_DS15_Msk +#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */ +#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */ +#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */ +#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */ + +/******************* Bit definition for GPIO_SR register *******************/ +#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */ +#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */ +#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */ +#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */ +#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */ +#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */ +#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */ +#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */ +#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */ +#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */ +#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */ +#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */ +#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */ +#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */ +#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */ +#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for AFIO_RMP_CFG register *****************/ +#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */ +#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */ +#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */ +#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */ +#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */ +#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */ +#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */ +#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */ +#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */ +#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */ +#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */ +#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ + +/*!< EXTI5 configuration */ +#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */ +#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */ +#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */ +#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */ +#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */ +#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */ +#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */ + +/*!< EXTI12 configuration */ +#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ + +/*!< EXTI13 configuration */ +#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ +#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ +#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ +#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ +#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ +#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ +#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ +#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ +#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ +#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ +#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ +#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ +#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ +#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ +#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ + + +/****************** Bit definition for EXTI_RT_CFG register *******************/ +#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ +#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ +#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ +#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ +#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ + + + +/****************** Bit definition for EXTI_FT_CFG register *******************/ +#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ +#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ +#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ +#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ +#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ + +/****************** Bit definition for EXTI_SWIE register ******************/ +#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ +#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ +#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ +#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ +#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ +#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ + +/******************* Bit definition for EXTI_PEND register ********************/ +#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ +#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ +#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ +#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ +#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ +#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ +#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ +#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ +#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ + + +/******************************************************************************/ +/* */ +/* LCD Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for LCD_CTRL register *******************/ +#define LCD_CTRL_BUFEN_Msk ((uint32_t)0x00000100) +#define LCD_CTRL_BUFEN_Pos (8U) +#define LCD_CTRL_BUFEN (LCD_CTRL_BUFEN_Msk) /*!< High driving capacity buffer enable bit*/ + +#define LCD_CTRL_MUXSEG_Msk ((uint32_t)0x00000080) +#define LCD_CTRL_MUXSEG_Pos (7U) +#define LCD_CTRL_MUXSEG (LCD_CTRL_MUXSEG_Msk) /*!< Mux segment enable bit*/ + +#define LCD_CTRL_BIAS_Msk ((uint32_t)0x00000060) +#define LCD_CTRL_BIAS_Pos (5U) +#define LCD_CTRL_BIAS (LCD_CTRL_BIAS_Msk) +#define LCD_CTRL_BIAS_0 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< Bias selector bit*/ +#define LCD_CTRL_BIAS_1 (0x2UL << LCD_CTRL_BIAS_Pos) + +#define LCD_CTRL_DUTY_Msk ((uint32_t)0x0000001C) +#define LCD_CTRL_DUTY_Pos (2U) +#define LCD_CTRL_DUTY (LCD_CTRL_DUTY_Msk) /*!< Duty selection bit*/ +#define LCD_CTRL_DUTY_0 (0x1UL << LCD_CTRL_DUTY_Pos) +#define LCD_CTRL_DUTY_1 (0x2UL << LCD_CTRL_DUTY_Pos) +#define LCD_CTRL_DUTY_2 (0x4UL << LCD_CTRL_DUTY_Pos) + +#define LCD_CTRL_VSEL_Msk ((uint32_t)0x00000002) +#define LCD_CTRL_VSEL_Pos (1U) +#define LCD_CTRL_VSEL (LCD_CTRL_VSEL_Msk) /*!< Voltage source selection bit*/ + +#define LCD_CTRL_LCDEN_Msk ((uint32_t)0x00000001) +#define LCD_CTRL_LCDEN_Pos (0U) +#define LCD_CTRL_LCDEN (LCD_CTRL_LCDEN_Msk) /*!< LCD controller enable bit*/ + +/******************* Bit definition for LCD_FCTRL register *******************/ +#define LCD_FCTRL_PRES_Msk ((uint32_t)0x03C00000) +#define LCD_FCTRL_PRES_Pos (22U) +#define LCD_FCTRL_PRES (LCD_FCTRL_PRES_Msk) /*!< 16-bit prescaler bit*/ +#define LCD_FCTRL_PRES_0 (0x1UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_1 (0x2UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_2 (0x4UL << LCD_FCTRL_PRES_Pos) +#define LCD_FCTRL_PRES_3 (0x8UL << LCD_FCTRL_PRES_Pos) + +#define LCD_FCTRL_DIV_Msk ((uint32_t)0x003C0000) +#define LCD_FCTRL_DIV_Pos (18U) +#define LCD_FCTRL_DIV (LCD_FCTRL_DIV_Msk) /*!< DIV clock divider bit*/ +#define LCD_FCTRL_DIV_0 (0x1UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_1 (0x2UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_2 (0x4UL << LCD_FCTRL_DIV_Pos) +#define LCD_FCTRL_DIV_3 (0x8UL << LCD_FCTRL_DIV_Pos) + +#define LCD_FCTRL_BLINK_Msk ((uint32_t)0x00030000) +#define LCD_FCTRL_BLINK_Pos (16U) +#define LCD_FCTRL_BLINK (LCD_FCTRL_BLINK_Msk) /*!< Blink mode selection bit*/ +#define LCD_FCTRL_BLINK_0 (0x1UL << LCD_FCTRL_BLINK_Pos) +#define LCD_FCTRL_BLINK_1 (0x2UL << LCD_FCTRL_BLINK_Pos) + +#define LCD_FCTRL_BLINKF_Msk ((uint32_t)0x0000E000) +#define LCD_FCTRL_BLINKF_Pos (13U) +#define LCD_FCTRL_BLINKF (LCD_FCTRL_BLINKF_Msk) /*!< Blink frequency selection bit*/ +#define LCD_FCTRL_BLINKF_0 (0x1UL << LCD_FCTRL_BLINKF_Pos) +#define LCD_FCTRL_BLINKF_1 (0x2UL << LCD_FCTRL_BLINKF_Pos) +#define LCD_FCTRL_BLINKF_2 (0x4UL << LCD_FCTRL_BLINKF_Pos) + +#define LCD_FCTRL_CONTRAST_Msk ((uint32_t)0x00001C00) +#define LCD_FCTRL_CONTRAST_Pos (10U) +#define LCD_FCTRL_CONTRAST (LCD_FCTRL_CONTRAST_Msk) /*!< Contrast Control bit*/ +#define LCD_FCTRL_CONTRAST_0 (0x1UL << LCD_FCTRL_CONTRAST_Pos) +#define LCD_FCTRL_CONTRAST_1 (0x2UL << LCD_FCTRL_CONTRAST_Pos) +#define LCD_FCTRL_CONTRAST_2 (0x4UL << LCD_FCTRL_CONTRAST_Pos) + +#define LCD_FCTRL_DEAD_Msk ((uint32_t)0x00000380) +#define LCD_FCTRL_DEAD_Pos (7U) +#define LCD_FCTRL_DEAD (LCD_FCTRL_DEAD_Msk) /*!< Dead time duration bit*/ +#define LCD_FCTRL_DEAD_0 (0x1UL << LCD_FCTRL_DEAD_Pos) +#define LCD_FCTRL_DEAD_1 (0x2UL << LCD_FCTRL_DEAD_Pos) +#define LCD_FCTRL_DEAD_2 (0x4UL << LCD_FCTRL_DEAD_Pos) + +#define LCD_FCTRL_PULSEON_Msk ((uint32_t)0x00000070) +#define LCD_FCTRL_PULSEON_Pos (4U) +#define LCD_FCTRL_PULSEON (LCD_FCTRL_PULSEON_Msk) /*!< Pulse on duration bit*/ +#define LCD_FCTRL_PULSEON_0 (0x1UL << LCD_FCTRL_PULSEON_Pos) +#define LCD_FCTRL_PULSEON_1 (0x2UL << LCD_FCTRL_PULSEON_Pos) +#define LCD_FCTRL_PULSEON_2 (0x4UL << LCD_FCTRL_PULSEON_Pos) + +#define LCD_FCTRL_UDDIE_Msk ((uint32_t)0x00000008) +#define LCD_FCTRL_UDDIE_Pos (3U) +#define LCD_FCTRL_UDDIE (LCD_FCTRL_UDDIE_Msk) /*!< Update display done interrupt enable bit*/ + +#define LCD_FCTRL_SOFIE_Msk ((uint32_t)0x00000002) +#define LCD_FCTRL_SOFIE_Pos (1U) +#define LCD_FCTRL_SOFIE (LCD_FCTRL_SOFIE_Msk) /*!< Start of frame interrupt enable bit*/ + +#define LCD_FCTRL_HDEN_Msk ((uint32_t)0x00000001) +#define LCD_FCTRL_HDEN_Pos (0U) +#define LCD_FCTRL_HDEN (LCD_FCTRL_HDEN_Msk) /*!< High drive enable bit*/ + +/******************* Bit definition for LCD_STS register *******************/ +#define LCD_STS_FCRSF_Msk ((uint32_t)0x00000020) +#define LCD_STS_FCRSF_Pos (5U) +#define LCD_STS_FCRSF (LCD_STS_FCRSF_Msk) /*!< LCD Frame Control Register Synchronization flag bit*/ + +#define LCD_STS_RDY_Msk ((uint32_t)0x00000010) +#define LCD_STS_RDY_Pos (4U) +#define LCD_STS_RDY (LCD_STS_RDY_Msk) /*!< VLCD Ready Flag bit*/ + +#define LCD_STS_UDD_Msk ((uint32_t)0x00000008) +#define LCD_STS_UDD_Pos (3U) +#define LCD_STS_UDD (LCD_STS_UDD_Msk) /*!< Update Display Done bit*/ + +#define LCD_STS_UDR_Msk ((uint32_t)0x00000004) +#define LCD_STS_UDR_Pos (2U) +#define LCD_STS_UDR (LCD_STS_UDR_Msk) /*!< Update Display Request bit*/ + +#define LCD_STS_SOF_Msk ((uint32_t)0x00000002) +#define LCD_STS_SOF_Pos (1U) +#define LCD_STS_SOF (LCD_STS_SOF_Msk) /*!< Start of Frame flag*/ + +#define LCD_STS_ENSTS_Msk ((uint32_t)0x00000001) +#define LCD_STS_ENSTS_Pos (0U) +#define LCD_STS_ENSTS (LCD_STS_ENSTS_Msk) /*!< LCD state bit*/ + +/******************* Bit definition for LCD_CLR register *******************/ +#define LCD_CLR_UDDCLR_Msk ((uint32_t)0x00000008) /*!< Update display done clear bit*/ +#define LCD_CLR_UDDCLR_Pos (3U) +#define LCD_CLR_UDDCLR (LCD_CLR_UDDCLR_Msk) + +#define LCD_CLR_SOFCLR_Msk ((uint32_t)0x00000002) /*!FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x.s b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x.s new file mode 100644 index 0000000000000000000000000000000000000000..cee6fb09b258367eaddd5fe4bcff8a7b0c31c6d5 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x.s @@ -0,0 +1,373 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +LCD_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_EWARM.s b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_EWARM.s new file mode 100644 index 0000000000000000000000000000000000000000..e9a39bed20bf9ade38a8f772a03554f78f8b5ea8 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_EWARM.s @@ -0,0 +1,523 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel1_IRQHandler + B DMA_Channel1_IRQHandler + + PUBWEAK DMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel2_IRQHandler + B DMA_Channel2_IRQHandler + + PUBWEAK DMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel3_IRQHandler + B DMA_Channel3_IRQHandler + + PUBWEAK DMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel4_IRQHandler + B DMA_Channel4_IRQHandler + + PUBWEAK DMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel5_IRQHandler + B DMA_Channel5_IRQHandler + + PUBWEAK DMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel6_IRQHandler + B DMA_Channel6_IRQHandler + + PUBWEAK DMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel7_IRQHandler + B DMA_Channel7_IRQHandler + + PUBWEAK DMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Channel8_IRQHandler + B DMA_Channel8_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK COMP_1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_1_2_IRQHandler + B COMP_1_2_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK LPUART_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_IRQHandler + B LPUART_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK CAN_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_TX_IRQHandler + B CAN_TX_IRQHandler + + PUBWEAK CAN_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX0_IRQHandler + B CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK LPUART_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART_WKUP_IRQHandler + B LPUART_WKUP_IRQHandler + + PUBWEAK LPTIM_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM_WKUP_IRQHandler + B LPTIM_WKUP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK SAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAC_IRQHandler + B SAC_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RAMC_PERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAMC_PERR_IRQHandler + B RAMC_PERR_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK UCDR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UCDR_IRQHandler + B UCDR_IRQHandler + + + END + diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_gcc.s b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..7b6435100622c0821e3a8c99ba3853d63276c58f --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/startup/startup_n32l43x_gcc.s @@ -0,0 +1,457 @@ +/** + **************************************************************************** + Copyright (c) 2019, Nations Technologies Inc. + + All rights reserved. + **************************************************************************** + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the disclaimer below. + + Nations' name may not be used to endorse or promote products derived from + this software without specific prior written permission. + + DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + **/ + +* Amount of memory (in bytes) allocated for Stack +* Tailor this value to your application needs +* Stack Configuration +* Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +* +*/ + +/** +****************************************************************************** +* @file startup_n32l43x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT Nations Technologies Inc *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.c b/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.c new file mode 100644 index 0000000000000000000000000000000000000000..a7709362161472b07610a080148be94e14e065aa --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.c @@ -0,0 +1,615 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32l43x.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x.h" + +/* Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your + device's maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume + that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to + drive the System clock. If you are using different crystal you have to adapt + those functions accordingly. + */ + +#define SYSCLK_USE_MSI 0 +#define SYSCLK_USE_HSI 1 +#define SYSCLK_USE_HSE 2 +#define SYSCLK_USE_HSI_PLL 3 +#define SYSCLK_USE_HSE_PLL 4 + +#ifndef SYSCLK_FREQ +#define SYSCLK_FREQ 108000000 +#endif + +/* +* SYSCLK_SRC * +** SYSCLK_USE_MSI ** +** SYSCLK_USE_HSI ** +** SYSCLK_USE_HSE ** +** SYSCLK_USE_HSI_PLL ** +** SYSCLK_USE_HSE_PLL ** +*/ +#ifndef SYSCLK_SRC +#define SYSCLK_SRC SYSCLK_USE_HSE_PLL +#endif + +#define PLL_DIV2_DISABLE 0x00000000 +#define PLL_DIV2_ENABLE 0x00000002 + +#if SYSCLK_SRC == SYSCLK_USE_MSI + + #if (SYSCLK_FREQ == MSI_VALUE_L0) + #define MSI_CLK 0 + #elif (SYSCLK_FREQ == MSI_VALUE_L1) + #define MSI_CLK 1 + #elif (SYSCLK_FREQ == MSI_VALUE_L2) + #define MSI_CLK 2 + #elif (SYSCLK_FREQ == MSI_VALUE_L3) + #define MSI_CLK 3 + #elif (SYSCLK_FREQ == MSI_VALUE_L4) + #define MSI_CLK 4 + #elif (SYSCLK_FREQ == MSI_VALUE_L5) + #define MSI_CLK 5 + #elif (SYSCLK_FREQ == MSI_VALUE_L6) + #define MSI_CLK 6 + #else + #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6) + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI + + #if SYSCLK_FREQ != HSI_VALUE + #error SYSCL_FREQ must be set to HSI_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if SYSCLK_FREQ != HSE_VALUE + #error SYSCL_FREQ must be set to HSE_VALUE + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL + + #ifndef HSI_VALUE + #error HSI_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE) + + #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + #ifndef HSE_VALUE + #error HSE_VALUE must be defined! + #endif + + #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2)) + + #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32) + + #define PLLSRC_DIV 1 + #define PLL_DIV PLL_DIV2_DISABLE + #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE) + + #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32) + + #define PLLSRC_DIV 2 + #define PLL_DIV PLL_DIV2_ENABLE + #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4)) + + #else + #error Cannot make a PLL multiply factor to SYSCLK_FREQ. + #endif + +#else +#error wrong value for SYSCLK_SRC +#endif + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ + +/******************************************************************************* + * Clock Definitions + *******************************************************************************/ +uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +static void SetSysClock(void); + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + */ +void SystemInit(void) +{ + /* FPU settings + * ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSEON, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */ + RCC->CFG &= (uint32_t)0x0700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; + + /* Enable ex mode */ + RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN; + RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN); + + /* Enable ICACHE and Prefetch Buffer */ + FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN); + + /* Checks whether the Low Voltage Mode status is SET or RESET */ + if((FLASH->AC & FLASH_AC_LVMF) != RESET) + { + /* FLASH Low Voltage Mode Disable */ + FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN); + } + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or + * configure other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any + * configuration based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the + * MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the + * HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the + * HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the + * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in n32l43x.h file (default value + * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real + * value may vary depending on the variations in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in n32l43x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in n32l43x.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to + * ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0; + uint8_t msi_clk = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + tmp = RCC->CFG & RCC_CFG_SCLKSTS; + + /* Get MSI clock + * -------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + SystemCoreClock = MSIClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor + * ----------------------*/ + pllmull = RCC->CFG & RCC_CFG_PLLMULFCT; + pllsource = RCC->CFG & RCC_CFG_PLLSRC; + plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV; + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSI_VALUE * pllmull; + } + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + if (plldiv2 == 0x02) + { + /* PLL source clock divided by 2 selected as PLL clock entry */ + SystemCoreClock >>= 1; + } + + break; + + default: + SystemCoreClock = MSIClockTable[msi_clk]; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 + * prescalers. + */ +static void SetSysClock(void) +{ + uint32_t rcc_cfg = 0; + uint32_t rcc_pllhsipre = 0; + uint32_t StartUpCounter = 0; + +#if (SYSCLK_SRC == SYSCLK_USE_MSI) + uint8_t i=0; + bool MSIStatus = 0; + /* Config MSI */ + RCC->CTRLSTS &= 0xFFFFFF8F; + /*Delay for while*/ + for(i=0;i<0x30;i++); + RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4); + /*Delay for while*/ + for(i=0;i<0x30;i++); + /* Enable MSI */ + RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN); + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD; + StartUpCounter++; + } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT)); + + MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET); + if (!MSIStatus) + { + /* If MSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL)) + + bool HSIStatus = 0; + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + /* If HSI fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } + +#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL)) + + bool HSEStatus = 0; + /* Enable HSE */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET); + if (!HSEStatus) + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = MSI_VALUE_L6; + return; + } +#endif + + /* If the system clock is greater than 64MHz, the voltage range of the main voltage regulator + must be configured as 1.1V */ + if(SYSCLK_FREQ >= 64000000) + { + /* Enables PWR peripheral clock */ + RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR; + /* Check PWR->CTRL1.MRSEL configuration */ + if((PWR->CTRL1 & ((uint32_t)PWR_CTRL1_MRSEL)) == ((uint32_t)PWR_CTRL1_MRSEL2)) + { + /* Config 1.1V */ + PWR->CTRL1 |= PWR_CTRL1_MRSEL1; + } + } + + /* Flash wait state + 0: HCLK <= 32M + 1: HCLK <= 64M + 2: HCLK <= 96M + 3: HCLK <= 128M + */ + FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY); + FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000); + + /* HCLK = SYSCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1; + + /* PCLK2 max 54M */ + if (SYSCLK_FREQ > 54000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1; + } + + /* PCLK1 max 27M */ + if (SYSCLK_FREQ > 54000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4; + } + else if (SYSCLK_FREQ > 27000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1; + } + +#if SYSCLK_SRC == SYSCLK_USE_MSI + /* Select MSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI; + + /* Wait till MSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI + /* Select HSI as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSE + /* Select HSE as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + /* clear bits */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT)); + RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV)); + + /* set PLL source */ + rcc_cfg = RCC->CFG; + rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE); + /* PLL DIV */ + rcc_pllhsipre = RCC->PLLHSIPRE; + + #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL + rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2); + #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); + #endif + + /* set PLL DIV */ + rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE); + + /* set PLL multiply factor */ + #if PLL_MUL <= 16 + rcc_cfg |= (PLL_MUL - 2) << 18; + #else + rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27); + #endif + + RCC->CFG = rcc_cfg; + RCC->PLLHSIPRE = rcc_pllhsipre; + + /* Enable PLL */ + RCC->CTRL |= RCC_CTRL_PLLEN; + + /* Wait till PLL is ready */ + while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C) + { + } +#endif +} diff --git a/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.h b/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.h new file mode 100644 index 0000000000000000000000000000000000000000..1b66383384824647dacd35af49dbb0143a166c49 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/CMSIS/device/system_n32l43x.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32l43x.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SYSTEM_N32L43X_H__ +#define __SYSTEM_N32L43X_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32L43X_System + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_N32L43X_H__ */ diff --git a/drivers/hal/nationstech/N32L43x/Kconfig b/drivers/hal/nationstech/N32L43x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..cd9f7cbdd727bf4274a493272c58c0996fc32e78 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/Kconfig @@ -0,0 +1,10 @@ +config SERIES_N32L43X + bool + select ARCH_ARM_CORTEX_M4 + default n + +config SOC_N32L436RBL7 + bool + select MANUFACTOR_NATIONSTECH + select SERIES_N32L43X + default n diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/misc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/misc.h new file mode 100644 index 0000000000000000000000000000000000000000..65d4ec65f706e5bc5d677c8c40dfb28fd123c530 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/misc.h @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @addtogroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete n32l43x Devices IRQ Channels list, please + refer to n32l43x.h file) */ + + uint8_t + NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + +/** + * @} + */ + +/** @addtogroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption +priority | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption +priority | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption +priority | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption +priority | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption +priority | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Constants + * @{ + */ + +/** @addtogroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @addtogroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @addtogroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 \ + ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \ + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 \ + ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \ + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 \ + ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \ + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 \ + ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \ + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 \ + ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \ + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) \ + (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \ + || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @addtogroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) \ + (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_adc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..6fc2419385422401f80f9e86a763ee39187e22b2 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_adc.h @@ -0,0 +1,580 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_adc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_ADC_H__ +#define __N32L43X_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" +#include + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ +#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while(0); +#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while(0); + +#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24)) +#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while(0); +#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while(0); + +/** @addtogroup ADC + * @{ + */ + +/** @addtogroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + + FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref + ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitType; +/** + * @} + */ + +/** @addtogroup ADC_Exported_Constants + * @{ + */ + +#define IsAdcModule(PERIPH) (((PERIPH) == ADC)) + +#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC)) + + + +/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) +#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) +#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) +#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) +#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) +#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) +#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) + + +#define IsAdcExtTrig(REGTRIG) \ + (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_data_align + * @{ + */ + +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) +#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) +/** + * @} + */ + +/** @addtogroup ADC_channels + * @{ + */ + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) + +#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0) +#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17) +#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18) + +#define IsAdcChannel(CHANNEL) \ + (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ + || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ + || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ + || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ + || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) +/** + * @} + */ + +/** @addtogroup ADC_sampling_time + * @{ + */ + +#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) +#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) +#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) +#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) +#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) +#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) +#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) +#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) +#define IsAdcSampleTime(TIME) \ + (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_239CYCLES5)) +/** + * @} + */ + +/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) +#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) +#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) +#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) +#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) +#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) +#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) + + +#define IsAdcExtInjTrig(INJTRIG) \ + (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_INJ_CH_1 ((uint8_t)0x14) +#define ADC_INJ_CH_2 ((uint8_t)0x18) +#define ADC_INJ_CH_3 ((uint8_t)0x1C) +#define ADC_INJ_CH_4 ((uint8_t)0x20) +#define IsAdcInjCh(CHANNEL) \ + (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ + || ((CHANNEL) == ADC_INJ_CH_4)) +/** + * @} + */ + +/** @addtogroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) +#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) +#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) +#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) +#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) +#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) +#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) + +#define IsAdcAnalogWatchdog(WATCHDOG) \ + (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_interrupts_definition + * @{ + */ + +#define ADC_INT_ENDC ((uint16_t)0x0220) +#define ADC_INT_AWD ((uint16_t)0x0140) +#define ADC_INT_JENDC ((uint16_t)0x0480) + +#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) +/** + * @} + */ + +/** @addtogroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_JENDC ((uint8_t)0x04) +#define ADC_FLAG_JSTR ((uint8_t)0x08) +#define ADC_FLAG_STR ((uint8_t)0x10) +#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) +#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) +#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) +#define IsAdcGetFlag(FLAG) \ + (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ + || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) +/** + * @} + */ + +/** @addtogroup ADC_thresholds + * @{ + */ +#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @addtogroup ADC_injected_offset + * @{ + */ + +#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @addtogroup ADC_injected_length + * @{ + */ + +#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_injected_rank + * @{ + */ + +#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_length + * @{ + */ + +#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @addtogroup ADC_regular_rank + * @{ + */ + +#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/************************** fllowing bit seg in ex register **********************/ +/**@addtogroup ADC_channels_ex_style + * @{ + */ + + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1_PA0 ((uint8_t)0x01) +#define ADC_CH_2_PA1 ((uint8_t)0x02) +#define ADC_CH_3_PA2 ((uint8_t)0x03) +#define ADC_CH_4_PA3 ((uint8_t)0x04) +#define ADC_CH_5_PA4 ((uint8_t)0x05) +#define ADC_CH_6_PA5 ((uint8_t)0x06) +#define ADC_CH_7_PA6 ((uint8_t)0x07) +#define ADC_CH_8_PA7 ((uint8_t)0x08) +#define ADC_CH_9_PB0 ((uint8_t)0x09) +#define ADC_CH_10_PB1 ((uint8_t)0x0A) +#define ADC_CH_11_PC0 ((uint8_t)0x0B) +#define ADC_CH_12_PC1 ((uint8_t)0x0C) +#define ADC_CH_13_PC2 ((uint8_t)0x0D) +#define ADC_CH_14_PC3 ((uint8_t)0x0E) +#define ADC_CH_15_PC4 ((uint8_t)0x0F) +#define ADC_CH_16_PC5 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) +/** + * @} + */ + +/**@addtogroup ADC_dif_sel_ch_definition + * @{ + */ +#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF) +#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001) +#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) +#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) +#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) +#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) +#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) +#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) +#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) +#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) +#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) +#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) +#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) +#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) +#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) +#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) +#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) +#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) +#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) +#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) +/** + * @} + */ + +/**@addtogroup ADC_calfact_definition + * @{ + */ +#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) +#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) +/** + * @} + */ + +/**@addtogroup ADC_ctrl3_definition + * @{ + */ +#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) +#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) +#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) +#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) +#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) +#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) +#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) +#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) +#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) + +#define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK) +#define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK)) +typedef enum +{ + ADC_CTRL3_CKMOD_AHB = 0, + ADC_CTRL3_CKMOD_PLL = 1, +} ADC_CTRL3_CKMOD; +typedef enum +{ + ADC_CTRL3_RES_12BIT = 3, + ADC_CTRL3_RES_10BIT = 2, + ADC_CTRL3_RES_8BIT = 1, + ADC_CTRL3_RES_6BIT = 0, +} ADC_CTRL3_RES; +typedef struct +{ + FunctionalState DeepPowerModEn; + FunctionalState JendcIntEn; + FunctionalState EndcIntEn; + ADC_CTRL3_CKMOD ClkMode; + FunctionalState CalAtuoLoadEn; + bool DifModCal; + ADC_CTRL3_RES ResBit; + bool Samp303Style; +} ADC_InitTypeEx; +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; + __IO uint32_t EMC_CTRL; + __IO uint32_t EMC_ST; +} AFEC_TypeDef; + +typedef enum +{ + ADC_REFENCE_Volt_VREF = 0, + ADC_REFENCE_Volt_VREFBUFF = 1, +} ADC_REFERENCE_Volt; + +/** + * @} + */ + +/**@addtogroup ADC_bit_num_definition + * @{ + */ +#define ADC_RST_BIT_12 ((uint32_t)0x03) +#define ADC_RST_BIT_10 ((uint32_t)0x02) +#define ADC_RST_BIT_8 ((uint32_t)0x01) +#define ADC_RESULT_BIT_6 ((uint32_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC_flags_ex_definition + * @{ + */ +#define ADC_FLAG_RDY ((uint8_t)0x20) +#define ADC_FLAG_PD_RDY ((uint8_t)0x40) +#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)) +/** + * @} + */ + +/** @addtogroup ADC_AFEC definition + * @{ + */ +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) + +#define AFEC_CTL ((AFEC_TypeDef *) AFEC_BASE) + +#define RCC_APB1Periph_AFEC ((uint32_t)0x00000100) +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_Module* ADCx); +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_InitStruct(ADC_InitType* ADC_InitStruct); +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); +void ADC_StartCalibration(ADC_Module* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); +uint16_t ADC_GetDat(ADC_Module* ADCx); +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); +void ADC_EnableTempSensorVrefint(FunctionalState Cmd); +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); + +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); + +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); +void Reference_Voltage_Switch(ADC_REFERENCE_Volt Ref_Type); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_ADC_H__ */ + +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_can.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_can.h new file mode 100644 index 0000000000000000000000000000000000000000..81d2e8442672c04802774db45fde98616455142b --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_can.h @@ -0,0 +1,670 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_can.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_CAN_H__ +#define __N32L43X_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @addtogroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t OperatingMode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t RSJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t TBS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t TBS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitType; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t Filter_Scale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState Filter_Act; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitType; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMessage; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMessage; + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Constants + * @{ + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @addtogroup OperatingMode + * @{ + */ + +#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */ +#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) \ + (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \ + || ((MODE) == CAN_Silent_LoopBack_Mode)) +/** + * @} + */ + +/** + * @addtogroup CAN_operating_mode + * @{ + */ +#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */ + +#define IS_CAN_OPERATING_MODE(MODE) \ + (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode)) +/** + * @} + */ + +/** + * @addtogroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */ + +/** + * @} + */ + +/** @addtogroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_RSJW(SJW) \ + (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq)) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq) + +/** + * @} + */ + +/** @addtogroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13) +/** + * @} + */ + +/** @addtogroup CAN_filter_mode + * @{ + */ + +#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode)) +/** + * @} + */ + +/** @addtogroup CAN_filter_scale + * @{ + */ + +#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @addtogroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @addtogroup CAN_identifier_type + * @{ + */ + +#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id)) +/** + * @} + */ + +/** @addtogroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote)) + +/** + * @} + */ + +/** @addtogroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @addtogroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */ + +#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @addtogroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @addtogroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */ + +/** + * @} + */ + +/** @addtogroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */ +#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */ +#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */ +#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */ +#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */ +#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \ + || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \ + || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK)) + +#define IS_CAN_CLEAR_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \ + || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \ + || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + +/** @addtogroup CAN_interrupts + * @{ + */ + +#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/ +#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/ +#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/ +#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/ +#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/ +#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_INT_RQCPM0 CAN_INT_TME +#define CAN_INT_RQCPM1 CAN_INT_TME +#define CAN_INT_RQCPM2 CAN_INT_TME + +#define IS_CAN_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \ + || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \ + || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \ + || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +#define IS_CAN_CLEAR_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \ + || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \ + || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +/** + * @} + */ + +/** @addtogroup CAN_Legacy + * @{ + */ +#define CANINITSTSFAILED CAN_InitSTS_Failed +#define CANINITSTSOK CAN_InitSTS_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Standard_Id +#define CAN_ID_EXT CAN_Extended_Id +#define CAN_RTRQ_DATA CAN_RTRQ_Data +#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote +#define CANTXSTSFAILE CAN_TxSTS_Failed +#define CANTXSTSOK CAN_TxSTS_Ok +#define CANTXSTSPENDING CAN_TxSTS_Pending +#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox +#define CANSLEEPFAILED CAN_SLEEP_Failed +#define CANSLEEPOK CAN_SLEEP_Ok +#define CANWKUFAILED CAN_WKU_Failed +#define CANWKUOK CAN_WKU_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_Module* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam); +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct); +void CAN_InitStruct(CAN_InitType* CAN_InitParam); +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd); +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd); + +/* Transmit functions *********************************************************/ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage); +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage); +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum); +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_EnterSleep(CAN_Module* CANx); +uint8_t CAN_WakeUp(CAN_Module* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrCode(CAN_Module* CANx); +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx); +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd); +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG); +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT); +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_CAN_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_comp.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_comp.h new file mode 100644 index 0000000000000000000000000000000000000000..a64fc0eb427cc2644b244a2cd4e7f26a7fced0d7 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_comp.h @@ -0,0 +1,282 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_comp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_COMP_H__ +#define __N32L43X_COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" +#include + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/** @addtogroup COMP_Exported_Constants + * @{ + */ +typedef enum +{ + COMP1 = 0, + COMP2 = 1, +} COMPX; + +// COMPx_CTRL +#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21) +#define COMP1_CTRL_INPDAC_MASK (0x01L << 20) +#define COMP_CTRL_OUT_MASK (0x01L << 19) +#define COMP_CTRL_BLKING_MASK (0x03L << 16) +typedef enum +{ + COMP_CTRL_BLKING_NO = (0x0L << 16), + COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16), + COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16), +} COMP_CTRL_BLKING; +#define COMPx_CTRL_HYST_MASK (0x03L << 14) +typedef enum +{ + COMP_CTRL_HYST_NO = (0x0L << 14), + COMP_CTRL_HYST_LOW = (0x1L << 14), + COMP_CTRL_HYST_MID = (0x2L << 14), + COMP_CTRL_HYST_HIGH = (0x3L << 14), +} COMP_CTRL_HYST; + +#define COMP_POL_MASK (0x01L << 13) +#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9) +typedef enum +{ + // comp1 out trig + COMP1_CTRL_OUTSEL_NC = (0x0L << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9), + COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9), + COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9), + COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9), + COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9), + COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9), + COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9), + COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9), + COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), + // comp2 out trig + COMP2_CTRL_OUTSEL_NC = (0x0L << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9), + COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9), + COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9), + COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9), + COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9), + COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9), + COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9), + COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9), + COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9), + COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9), + COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9), + COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9), + COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9), + COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9), + COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9), +} COMP_CTRL_OUTTRIG; + +#define COMP_CTRL_INPSEL_MASK (0x0FL<<5) +typedef enum { + //comp1 inp sel + COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100), + COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140), + COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160), + COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180), + COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0), + COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0), + COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0), + COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120), + //comp2 inp sel + COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000), + COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100), + COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120), + COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140), + COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160), + COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180), + COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0), + COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0), + COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0), +}COMP_CTRL_INPSEL; + + +#define COMP_CTRL_INMSEL_MASK (0x07L<<1) +typedef enum { + //comp1 inm sel + COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002), + COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004), + COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006), + COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008), + COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A), + COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C), + COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000), + //comp2 inm sel + COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002), + COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004), + COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006), + COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008), + COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A), + COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C), + COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E), + COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000), +}COMP_CTRL_INMSEL; + +#define COMP_CTRL_EN_MASK (0x01L << 0) + +//COMPx_FILC +#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1. +#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2. +#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable. + +//COMPx_FILP +#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number . + +//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD +#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode. + +//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN +#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTEN_CMP2IEN (0x01L << 1) +#define COMP_INTEN_CMP1IEN (0x01L << 0) + +//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS +#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP. +#define COMP_INTSTS_CMP2IS (0x01L << 1) +#define COMP_INTSTS_CMP1IS (0x01L << 0) + +//COMP_VREFSCL @addtogroup COMP_VREFSCL +#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value. +#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7) +#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value. +#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0) + +//COMP_LOCK @addtogroup COMP_LOCK +#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value. +#define COMP_LOCK_CMP1LK (0x1L << 0) + +//COMP_LPCKSEL @addtogroup COMP_LPCKSEL +#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0) + +//COMP_OSEL @addtogroup COMP_OSEL +#define COMP_OSEL_CMP2XO (0x1L << 0) + +/** + * @} + */ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + // ctrl + bool LowPoweMode; // only COMP1 have this bit + bool InpDacConnect; // only COMP1 have this bit + + COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */ + + COMP_CTRL_HYST Hyst; + + bool PolRev; // out polarity reverse + + COMP_CTRL_OUTTRIG OutTrig; + COMP_CTRL_INPSEL InpSel; + COMP_CTRL_INMSEL InmSel; + + bool En; + + // filter + uint8_t SampWindow; // 5bit + uint8_t Thresh; // 5bit ,need > SampWindow/2 + bool FilterEn; + + // filter psc + uint16_t ClkPsc; +} COMP_InitType; + +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +void COMP_DeInit(void); +void COMP_StructInit(COMP_InitType* COMP_InitStruct); +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct); +void COMP_Enable(COMPX COMPx, FunctionalState en); +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel); +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel); +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig); +uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL +FlagStatus COMP_GetOutStatus(COMPX COMPx); +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx); +void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK +void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN +void COMP_CMP2XorOut(bool En); +void COMP_StopOrLowpower32KClkSel(bool En); +void COMP_WindowModeEn(bool En); +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal); +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW); +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST); +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_ADC_H */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_crc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..bf0ab8b267610aa5969430411480cf92b3d6cc61 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_crc.h @@ -0,0 +1,105 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_crc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_CRC_H__ +#define __N32L43X_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @addtogroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +void CRC32_ResetCrc(void); +uint32_t CRC32_CalcCrc(uint32_t Data); +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC32_GetCrc(void); +void CRC32_SetIDat(uint8_t IDValue); +uint8_t CRC32_GetIDat(void); + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength); +uint16_t CRC16_CalcCRC(uint8_t Data); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_CRC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dac.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..73d55eac076b842187f2e356320d0cad815eeadc --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dac.h @@ -0,0 +1,293 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dac.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_DAC_H__ +#define __N32L43X_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @addtogroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t + LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +} DAC_InitType; + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Constants + * @{ + */ + +/** @addtogroup DAC_trigger_selection + * @{ + */ + +#define DAC_TRG_NONE \ + ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \ + has been loaded, and not by external trigger */ +#define DAC_TRG_T6_TRGO \ + ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T8_TRGO \ + ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \ + only in High-density devices*/ +#define DAC_TRG_T7_TRGO \ + ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T5_TRGO \ + ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T2_TRGO \ + ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T4_TRGO \ + ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_EXT_IT9 \ + ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) \ + (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \ + || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \ + || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE)) + +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040) +#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) \ + (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_UNMASK_LFSRBITS1_0 \ + ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS2_0 \ + ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS3_0 \ + ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS4_0 \ + ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS5_0 \ + ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS6_0 \ + ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS7_0 \ + ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS8_0 \ + ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS9_0 \ + ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS10_0 \ + ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_UNMASK_LFSRBITS11_0 \ + ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \ + (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \ + || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \ + || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \ + || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \ + || ((VALUE) == DAC_TRIAMP_4095)) +/** + * @} + */ + +/** @addtogroup DAC_output_buffer + * @{ + */ + +#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002) +#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE)) +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup DAC_data_alignment + * @{ + */ + +#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000) +#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004) +#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) \ + (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT)) +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVE_NOISE ((uint32_t)0x00000040) +#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(DAC_InitType* DAC_InitStruct); +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct); +void DAC_Enable(FunctionalState Cmd); + +void DAC_DmaEnable(FunctionalState Cmd); +void DAC_SoftTrgEnable(FunctionalState Cmd); +void DAC_SoftwareTrgEnable(FunctionalState Cmd); +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd); +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data); +uint16_t DAC_GetOutputDataVal(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_DAC_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dbg.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dbg.h new file mode 100644 index 0000000000000000000000000000000000000000..c3bf00cc2b949d0dcc3893a0635a14fb2ec65bdd --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dbg.h @@ -0,0 +1,124 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dbg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_DBG_H__ +#define __N32L43X_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @{ + */ + +/** @addtogroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBG_SLEEP ((uint32_t)0x00000001) +#define DBG_STOP ((uint32_t)0x00000002) +#define DBG_STDBY ((uint32_t)0x00000004) +#define DBG_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_TIM1_STOP ((uint32_t)0x00000400) +#define DBG_TIM2_STOP ((uint32_t)0x00000800) +#define DBG_TIM3_STOP ((uint32_t)0x00001000) +#define DBG_TIM4_STOP ((uint32_t)0x00002000) +#define DBG_CAN_STOP ((uint32_t)0x00004000) +#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBG_TIM8_STOP ((uint32_t)0x00020000) +#define DBG_TIM5_STOP ((uint32_t)0x00040000) +#define DBG_TIM6_STOP ((uint32_t)0x00080000) +#define DBG_TIM7_STOP ((uint32_t)0x00100000) +#define DBG_TIM9_STOP ((uint32_t)0x00200000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Functions + * @{ + */ + +void GetUCID(uint8_t *UCIDbuf); +void GetUID(uint8_t *UIDbuf); +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf); +uint32_t DBG_GetRevNum(void); +uint32_t DBG_GetDevNum(void); +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); + +uint32_t DBG_GetFlashSize(void); +uint32_t DBG_GetSramSize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_DBG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dma.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..89d9fde26726111aa54cb16584998377d985b034 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_dma.h @@ -0,0 +1,469 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dma.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_DMA_H__ +#define __N32L43X_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @addtogroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t Direction; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in PeriphDataSize + or MemDataSize members depending in the transfer direction. */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t MemDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitType; + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) \ + (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \ + || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8)) + +/** @addtogroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010) +#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040) +#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080) +#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000) +#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100) +#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200) +#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \ + || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD)) +/** + * @} + */ + +/** @addtogroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \ + || ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @addtogroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020) +#define DMA_MODE_NORMAL ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup DMA_priority_level + * @{ + */ + +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000) +#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000) +#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000) +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \ + || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW)) +/** + * @} + */ + +/** @addtogroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_ENABLE ((uint32_t)0x00004000) +#define DMA_M2M_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE)) + +/** + * @} + */ + +/** @addtogroup DMA_interrupts_definition + * @{ + */ + +#define DMA_INT_TXC ((uint32_t)0x00000002) +#define DMA_INT_HTX ((uint32_t)0x00000004) +#define DMA_INT_ERR ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA_INT_GLB1 ((uint32_t)0x00000001) +#define DMA_INT_TXC1 ((uint32_t)0x00000002) +#define DMA_INT_HTX1 ((uint32_t)0x00000004) +#define DMA_INT_ERR1 ((uint32_t)0x00000008) +#define DMA_INT_GLB2 ((uint32_t)0x00000010) +#define DMA_INT_TXC2 ((uint32_t)0x00000020) +#define DMA_INT_HTX2 ((uint32_t)0x00000040) +#define DMA_INT_ERR2 ((uint32_t)0x00000080) +#define DMA_INT_GLB3 ((uint32_t)0x00000100) +#define DMA_INT_TXC3 ((uint32_t)0x00000200) +#define DMA_INT_HTX3 ((uint32_t)0x00000400) +#define DMA_INT_ERR3 ((uint32_t)0x00000800) +#define DMA_INT_GLB4 ((uint32_t)0x00001000) +#define DMA_INT_TXC4 ((uint32_t)0x00002000) +#define DMA_INT_HTX4 ((uint32_t)0x00004000) +#define DMA_INT_ERR4 ((uint32_t)0x00008000) +#define DMA_INT_GLB5 ((uint32_t)0x00010000) +#define DMA_INT_TXC5 ((uint32_t)0x00020000) +#define DMA_INT_HTX5 ((uint32_t)0x00040000) +#define DMA_INT_ERR5 ((uint32_t)0x00080000) +#define DMA_INT_GLB6 ((uint32_t)0x00100000) +#define DMA_INT_TXC6 ((uint32_t)0x00200000) +#define DMA_INT_HTX6 ((uint32_t)0x00400000) +#define DMA_INT_ERR6 ((uint32_t)0x00800000) +#define DMA_INT_GLB7 ((uint32_t)0x01000000) +#define DMA_INT_TXC7 ((uint32_t)0x02000000) +#define DMA_INT_HTX7 ((uint32_t)0x04000000) +#define DMA_INT_ERR7 ((uint32_t)0x08000000) +#define DMA_INT_GLB8 ((uint32_t)0x10000000) +#define DMA_INT_TXC8 ((uint32_t)0x20000000) +#define DMA_INT_HTX8 ((uint32_t)0x40000000) +#define DMA_INT_ERR8 ((uint32_t)0x80000000) + + +#define IS_DMA_CLR_INT(IT) ((IT) != 0x00) + +#define IS_DMA_GET_IT(IT) \ + (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \ + || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \ + || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \ + || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \ + || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \ + || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \ + || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \ + || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8)) + +/** + * @} + */ + +/** @addtogroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA_FLAG_TE8 ((uint32_t)0x80000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00) + +#define IS_DMA_GET_FLAG(FLAG) \ + (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \ + || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \ + || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \ + || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \ + || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \ + || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \ + || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \ + || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \ + || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \ + || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \ + || ((FLAG) == DMA_FLAG_TE8)) +/** + * @} + */ + +/** @addtogroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** @addtogroup DMA_remap_request_definition + * @{ + */ +#define DMA_REMAP_ADC1 ((uint32_t)0x00000000) +#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001) +#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002) +#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003) +#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004) +#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005) +#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006) +#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007) +#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008) +#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009) +#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A) +#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B) +#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C) +#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D) +#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E) +#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F) +#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010) +#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011) +#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012) +#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013) +#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014) +#define DMA_REMAP_DAC1 ((uint32_t)0x00000015) +#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016) +#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017) +#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018) +#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019) +#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A) +#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B) +#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C) +#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D) +#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E) +#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F) +#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020) +#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021) +#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022) +#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023) +#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024) +#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025) +#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026) +#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027) +#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028) +#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029) +#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A) +#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B) +#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C) +#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D) +#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E) +#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F) +#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030) +#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031) +#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032) +#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033) +#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034) +#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035) +#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036) +#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037) +#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038) +#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039) +#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A) +#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B) +#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C) +#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D) +#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E) + + +#define IS_DMA_REMAP(FLAG) \ + (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \ + || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \ + || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \ + || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \ + || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \ + || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \ + || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \ + || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \ + || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \ + || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \ + || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \ + || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \ + || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \ + || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \ + || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \ + || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \ + || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \ + || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \ + || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_ChannelType* DMAChx); +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam); +void DMA_StructInit(DMA_InitType* DMA_InitParam); +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd); +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd); +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy); +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy); +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy); +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_DMA_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_exti.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..173a9284a08c83d64fb2b71e3dc50c51045d7626 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_exti.h @@ -0,0 +1,234 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_exti.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_EXTI_H__ +#define __N32L43X_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @addtogroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTI_ModeType; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTI_TriggerType; + +#define IS_EXTI_TRIGGER(TRIGGER) \ + (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \ + || ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitType; + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Constants + * @{ + */ + +/** @addtogroup EXTI_Lines + * @{ + */ + +#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ +#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */ +#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */ +#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */ +#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */ +#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */ +#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */ +#define EXTI_LINE26 ((uint32_t)0x4000000) /*!< External interrupt line 26 Connected to the LCD Global interrupt */ +#define EXTI_LINE27 ((uint32_t)0x8000000) /*!< External interrupt line 27 Connected to the LPRCNT Global interrupt */ + + + + + + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) \ + (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \ + || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \ + || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \ + || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \ + || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \ + || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \ + || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27)) + +/** + * @} + */ + +/** @addtogroup EXTI_TSSEL_Line + * @{ + */ +#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000) +#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */ +#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */ +#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */ +#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */ +#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */ +#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */ +#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */ +#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */ +#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */ +#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */ +#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */ +#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */ +#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */ +#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */ +#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */ +#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */ + +#define IS_EXTI_TSSEL_LINE(LINE) \ + (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \ + || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \ + || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \ + || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \ + || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \ + || ((LINE) == EXTI_TSSEL_LINE15)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct); +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct); +void EXTI_TriggerSWInt(uint32_t EXTI_Line); +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line); +void EXTI_ClrStatusFlag(uint32_t EXTI_Line); +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClrITPendBit(uint32_t EXTI_Line); +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_EXTI_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_flash.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..4130c1f6b2f080aee203bcf42a5322936079687b --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_flash.h @@ -0,0 +1,501 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_flash.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_FLASH_H__ +#define __N32L43X_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_RESERVED, + FLASH_ERR_PG, + FLASH_ERR_PV, + FLASH_ERR_WRP, + FLASH_COMPL, + FLASH_ERR_EV, + FLASH_ERR_RDP2, + FLASH_ERR_ADD, + FLASH_TIMEOUT +} FLASH_STS; + +/** + * @brief FLASH_SMPSEL + */ + +typedef enum +{ + FLASH_SMP1 = 0, + FLASH_SMP2 +} FLASH_SMPSEL; + +/** + * @brief FLASH_HSICLOCK + */ + +typedef enum +{ + FLASH_HSICLOCK_ENABLE = 0, + FLASH_HSICLOCK_DISABLE +} FLASH_HSICLOCK; + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Constants + * @{ + */ + +/** @addtogroup Flash_Latency + * @{ + */ + +#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) \ + (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \ + || ((LATENCY) == FLASH_LATENCY_3)) +/** + * @} + */ + +/** @addtogroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS)) +/** + * @} + */ + +/** @addtogroup iCache_Enable_Disable + * @{ + */ + +#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */ +#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */ +#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS)) +/** + * @} + */ + +/** @addtogroup Low Voltage Mode + * @{ + */ + +#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */ +#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */ +#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS)) +/** + * @} + */ + +/** @addtogroup FLASH Sleep Mode + * @{ + */ + +#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */ +#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */ +#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS)) +/** + * @} + */ + +/** @addtogroup SMPSEL_SMP1_SMP2 + * @{ + */ + +#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */ +#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */ +#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2)) +/** + * @} + */ + +/* Values to be used with N32L43x devices */ +#define FLASH_WRP_Pages0to1 \ + ((uint32_t)0x00000001) /*!< N32L43x devices: \ + Write protection of page 0 to 1 */ +#define FLASH_WRP_Pages2to3 \ + ((uint32_t)0x00000002) /*!< N32L43x devices: \ + Write protection of page 2 to 3 */ +#define FLASH_WRP_Pages4to5 \ + ((uint32_t)0x00000004) /*!< N32L43x devices: \ + Write protection of page 4 to 5 */ +#define FLASH_WRP_Pages6to7 \ + ((uint32_t)0x00000008) /*!< N32L43x devices: \ + Write protection of page 6 to 7 */ +#define FLASH_WRP_Pages8to9 \ + ((uint32_t)0x00000010) /*!< N32L43x devices: \ + Write protection of page 8 to 9 */ +#define FLASH_WRP_Pages10to11 \ + ((uint32_t)0x00000020) /*!< N32L43x devices: \ + Write protection of page 10 to 11 */ +#define FLASH_WRP_Pages12to13 \ + ((uint32_t)0x00000040) /*!< N32L43x devices: \ + Write protection of page 12 to 13 */ +#define FLASH_WRP_Pages14to15 \ + ((uint32_t)0x00000080) /*!< N32L43x devices: \ + Write protection of page 14 to 15 */ +#define FLASH_WRP_Pages16to17 \ + ((uint32_t)0x00000100) /*!< N32L43x devices: \ + Write protection of page 16 to 17 */ +#define FLASH_WRP_Pages18to19 \ + ((uint32_t)0x00000200) /*!< N32L43x devices: \ + Write protection of page 18 to 19 */ +#define FLASH_WRP_Pages20to21 \ + ((uint32_t)0x00000400) /*!< N32L43x devices: \ + Write protection of page 20 to 21 */ +#define FLASH_WRP_Pages22to23 \ + ((uint32_t)0x00000800) /*!< N32L43x devices: \ + Write protection of page 22 to 23 */ +#define FLASH_WRP_Pages24to25 \ + ((uint32_t)0x00001000) /*!< N32L43x devices: \ + Write protection of page 24 to 25 */ +#define FLASH_WRP_Pages26to27 \ + ((uint32_t)0x00002000) /*!< N32L43x devices: \ + Write protection of page 26 to 27 */ +#define FLASH_WRP_Pages28to29 \ + ((uint32_t)0x00004000) /*!< N32L43x devices: \ + Write protection of page 28 to 29 */ +#define FLASH_WRP_Pages30to31 \ + ((uint32_t)0x00008000) /*!< N32L43x devices: \ + Write protection of page 30 to 31 */ +#define FLASH_WRP_Pages32to33 \ + ((uint32_t)0x00010000) /*!< N32L43x devices: \ + Write protection of page 32 to 33 */ +#define FLASH_WRP_Pages34to35 \ + ((uint32_t)0x00020000) /*!< N32L43x devices: \ + Write protection of page 34 to 35 */ +#define FLASH_WRP_Pages36to37 \ + ((uint32_t)0x00040000) /*!< N32L43x devices: \ + Write protection of page 36 to 37 */ +#define FLASH_WRP_Pages38to39 \ + ((uint32_t)0x00080000) /*!< N32L43x devices: \ + Write protection of page 38 to 39 */ +#define FLASH_WRP_Pages40to41 \ + ((uint32_t)0x00100000) /*!< N32L43x devices: \ + Write protection of page 40 to 41 */ +#define FLASH_WRP_Pages42to43 \ + ((uint32_t)0x00200000) /*!< N32L43x devices: \ + Write protection of page 42 to 43 */ +#define FLASH_WRP_Pages44to45 \ + ((uint32_t)0x00400000) /*!< N32L43x devices: \ + Write protection of page 44 to 45 */ +#define FLASH_WRP_Pages46to47 \ + ((uint32_t)0x00800000) /*!< N32L43x devices: \ + Write protection of page 46 to 47 */ +#define FLASH_WRP_Pages48to49 \ + ((uint32_t)0x01000000) /*!< N32L43x devices: \ + Write protection of page 48 to 49 */ +#define FLASH_WRP_Pages50to51 \ + ((uint32_t)0x02000000) /*!< N32L43x devices: \ + Write protection of page 50 to 51 */ +#define FLASH_WRP_Pages52to53 \ + ((uint32_t)0x04000000) /*!< N32L43x devices: \ + Write protection of page 52 to 53 */ +#define FLASH_WRP_Pages54to55 \ + ((uint32_t)0x08000000) /*!< N32L43x devices: \ + Write protection of page 54 to 55 */ +#define FLASH_WRP_Pages56to57 \ + ((uint32_t)0x10000000) /*!< N32L43x devices: \ + Write protection of page 56 to 57 */ +#define FLASH_WRP_Pages58to59 \ + ((uint32_t)0x20000000) /*!< N32L43x devices: \ + Write protection of page 58 to 59 */ +#define FLASH_WRP_Pages60to61 \ + ((uint32_t)0x40000000) /*!< N32L43x devices: \ + Write protection of page 60 to 61 */ +#define FLASH_WRP_Pages62to63 \ + ((uint32_t)0x80000000) /*!< N32L43x devices: + Write protection of page 62 to 63 */ + +#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRP_PAGE(PAGE) (1) //(((PAGE) <= FLASH_WRP_AllPages)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP1 + * @{ + */ + +#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */ +#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */ +#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ +#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) + + +/** + * @} + */ + +/** @addtogroup Option_Bytes_RDP2 + * @{ + */ + +#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */ +#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */ +#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT0 + * @{ + */ + +#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */ +#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */ +#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nBOOT1 + * @{ + */ + +#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */ +#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */ +#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nSWBOOT0 + * @{ + */ + +#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */ +#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */ +#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_BOR_LEV + * @{ + */ + +#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */ +#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */ +#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */ +#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */ +#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */ +#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */ +#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */ +#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */ +#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ + || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \ + || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \ + || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7)) + + +/** + * @} + */ +/** @addtogroup FLASH_Interrupts + * @{ + */ +#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */ +#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */ +#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ + +#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @addtogroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */ +#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) \ + (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \ + || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \ + || ((FLAG) == FLASH_FLAG_OBERR)) + +/** + * @} + */ + +/** @addtogroup FLASH_STS_CLRFLAG + * @{ + */ +#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR) + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for N32L43x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf); +void FLASH_iCacheRST(void); +void FLASH_iCacheCmd(uint32_t FLASH_iCache); +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM); +FlagStatus FLASH_GetLowVoltageModeSTS(void); +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM); +FlagStatus FLASH_GetFLASHSleepModeSTS(void); +FLASH_HSICLOCK FLASH_ClockInit(void); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address); +FLASH_STS FLASH_MassErase(void); +FLASH_STS FLASH_EraseOB(void); +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages); +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd); +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void); +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY); +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV); +uint32_t FLASH_GetUserOB(void); +uint32_t FLASH_GetWriteProtectionOB(void); +FlagStatus FLASH_GetReadOutProtectionSTS(void); +FlagStatus FLASH_GetReadOutProtectionL2STS(void); +FlagStatus FLASH_GetPrefetchBufSTS(void); +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel); +FLASH_SMPSEL FLASH_GetSMPSELStatus(void); +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd); +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_STS FLASH_GetSTS(void); +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_FLASH_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_gpio.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..2271e6b025aea4a52c5e169049fe23e1500c7f9c --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_gpio.h @@ -0,0 +1,676 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_gpio.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_GPIO_H__ +#define __N32L43X_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @addtogroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) \ + (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD)) + + +#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\ + ((PERIPH) == (GPIOB))? 1 :\ + ((PERIPH) == (GPIOC))? 2 :3) +#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\ + ((INDEX)==((uint8_t)0x01))? GPIOB :\ + ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD ) + + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Slew_Rate_High = 0, + GPIO_Slew_Rate_Low +} GPIO_SpeedType; +#define IS_GPIO_SLEW_RATE(_RATE_) \ + (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low)) + +/** + * @brief driver strength config + */ + +typedef enum +{ + GPIO_DC_2mA = 0x00, + GPIO_DC_4mA = 0x10, + GPIO_DC_8mA = 0x01, + GPIO_DC_12mA= 0x11 +}GPIO_CurrentType; + +#define IS_GPIO_CURRENT(CURRENT) \ + (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \ + || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA)) +/** + * @brief Configuration Mode enumeration + */ + + +/** @brief GPIO_mode_define Mode definition + * @brief GPIO Configuration Mode + * Values convention: 0xW0yz00YZ + * - W : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ + +typedef enum +{ + GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */ + GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */ + GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */ + GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */ + GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */ + + GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */ + + GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */ + GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */ + GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + + GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */ + GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */ + GPIO_Mode_EVT_Rising_Falling = 0x10320000 +}GPIO_ModeType; + + + +/** + * @} + */ +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\ + ((__MODE__) == GPIO_Mode_Out_PP) ||\ + ((__MODE__) == GPIO_Mode_Out_OD) ||\ + ((__MODE__) == GPIO_Mode_AF_PP) ||\ + ((__MODE__) == GPIO_Mode_AF_OD) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising) ||\ + ((__MODE__) == GPIO_Mode_IT_Falling) ||\ + ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising) ||\ + ((__MODE__) == GPIO_Mode_EVT_Falling) ||\ + ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\ + ((__MODE__) == GPIO_Mode_Analog)) + +/** + * @} + */ + +/** + * @} + */ + +/** @brief GPIO_pull_define Pull definition + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ + +typedef enum +{ + GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */ + GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */ + GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */ +}GPIO_PuPdType; +/** + * @} + */ + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \ + ((__PULL__) == GPIO_Pull_Down)) +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIO_CurrentType GPIO_Current; /*!. + This paramter can be a value of @ref GPIO_CurrentType*/ + + GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_SpeedType */ + + GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_ModeType */ + + uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitType; + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} Bit_OperateType; + +#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET)) + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Exported_Constants + * @{ + */ + +/** @addtogroup GPIO_pins_define + * @{ + */ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF) +#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF) + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) \ + (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \ + || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \ + || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \ + || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15)) + + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE)))) + + + + + +/** + * @} + */ + + + + +/** @addtogroup GPIO_Port_Sources + * @{ + */ + +#define GPIOA_PORT_SOURCE ((uint8_t)0x00) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01) +#define GPIOC_PORT_SOURCE ((uint8_t)0x02) +#define GPIOD_PORT_SOURCE ((uint8_t)0x03) + +#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + + +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE)) + +/** + * @} + */ + +/** @addtogroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00) +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01) +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02) +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03) +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04) +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05) +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06) +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07) +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08) +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09) +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A) +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B) +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C) +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D) +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E) +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) \ + (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE15)) + +/** + * @} + */ + + + +/** @defgroup GPIOx_Alternate_function_selection Alternate function selection + * @{ + */ + +/* + * Alternate function AF0 + */ +#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */ +#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF1 + */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */ +#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF2 + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF3 + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF4 + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF5 + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */ +#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */ + +/** + * + */ + +/* + * Alternate function AF6 + */ + +#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */ +#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */ +#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +/** + * + */ + +/* + * Alternate function AF7 + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */ +#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */ +#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */ +#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF8 + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */ +#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF9 + */ +#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */ +#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF10 + */ +#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */ + +/** + * + */ + + /* + * Alternate function AF11 + */ +#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ + + + /* + * Alternate function AF15 + */ +#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */ + +#define GPIO_NO_AF (GPIO_AF15) +/** + * @} + */ + + +/** + * IS_GPIO_AF macro definition + */ + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \ + ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \ + ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \ + ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \ + ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \ + ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \ + ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \ + ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \ + ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \ + ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \ + ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \ + ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \ + ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \ + ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \ + ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \ + ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \ + ((__AF__) == GPIO_AF10_LCD) || ((__AF__) == GPIO_AF11_LCD) || \ + ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF)) + + + + + +/** + * @} + */ +/** @defgroup GPIO Alternate function remaping + * @{ + */ +#define AFIO_SPI1_NSS (11U) +#define AFIO_SPI2_NSS (10U) + +#define IS_AFIO_SPIX(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS)) +typedef enum +{ + AFIO_SPI_NSS_High_IMPEDANCE = 0U, + AFIO_SPI_NSS_High_LEVEL = 1U +}AFIO_SPI_NSSType; + +#define IS_AFIO_SPI_NSS(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL)) + + +typedef enum +{ + AFIO_ADC_ETRI= 9U, + AFIO_ADC_ETRR = 8U +}AFIO_ADC_ETRType; + +typedef enum +{ + AFIO_ADC_TRIG_EXTI_0 = 0x0U, + AFIO_ADC_TRIG_EXTI_1 = 0x01U, + AFIO_ADC_TRIG_EXTI_2, + AFIO_ADC_TRIG_EXTI_3, + AFIO_ADC_TRIG_EXTI_4, + AFIO_ADC_TRIG_EXTI_5, + AFIO_ADC_TRIG_EXTI_6, + AFIO_ADC_TRIG_EXTI_7, + AFIO_ADC_TRIG_EXTI_8, + AFIO_ADC_TRIG_EXTI_9, + AFIO_ADC_TRIG_EXTI_10, + AFIO_ADC_TRIG_EXTI_11, + AFIO_ADC_TRIG_EXTI_12, + AFIO_ADC_TRIG_EXTI_13, + AFIO_ADC_TRIG_EXTI_14, + AFIO_ADC_TRIG_EXTI_15, + AFIO_ADC_TRIG_TIM8_CH3, + AFIO_ADC_TRIG_TIM8_CH4 +}AFIO_ADC_Trig_RemapType; + +#define IS_AFIO_ADC_ETR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR)) +#define IS_AFIO_ADC_ETRI(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4)) + +#define IS_AFIO_ADC_ETRR(_PARAMETER_) \ + (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\ + ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \ + ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3)) + + /** + * @} + */ + +/** @addtogroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_Module* GPIOx); +void GPIO_AFIOInitDefault(void); +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct); +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx); +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd); +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal); +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource); +void GPIO_CtrlEventOutput(FunctionalState Cmd); +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction); +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource); + +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType); +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_GPIO_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_i2c.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..27d6ebd5007b706f90f20ac3db01dd50c89e0e91 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_i2c.h @@ -0,0 +1,671 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_i2c.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_I2C_H__ +#define __N32L43X_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @addtogroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t ClkSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t BusMode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_BusMode */ + + uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t OwnAddr1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t AckEnable; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitType; + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2)) +/** @addtogroup I2C_BusMode + * @{ + */ + +#define I2C_BUSMODE_I2C ((uint16_t)0x0000) +#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002) +#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A) +#define IS_I2C_BUS_MODE(MODE) \ + (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST)) +/** + * @} + */ + +/** @addtogroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledgement + * @{ + */ + +#define I2C_ACKEN ((uint16_t)0x0400) +#define I2C_ACKDIS ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS)) +/** + * @} + */ + +/** @addtogroup I2C_transfer_direction + * @{ + */ + +#define I2C_DIRECTION_SEND ((uint8_t)0x00) +#define I2C_DIRECTION_RECV ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledged_address + * @{ + */ + +#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000) +#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000) +#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT)) +/** + * @} + */ + +/** @addtogroup I2C_registers + * @{ + */ + +#define I2C_REG_CTRL1 ((uint8_t)0x00) +#define I2C_REG_CTRL2 ((uint8_t)0x04) +#define I2C_REG_OADDR1 ((uint8_t)0x08) +#define I2C_REG_OADDR2 ((uint8_t)0x0C) +#define I2C_REG_DAT ((uint8_t)0x10) +#define I2C_REG_STS1 ((uint8_t)0x14) +#define I2C_REG_STS2 ((uint8_t)0x18) +#define I2C_REG_CLKCTRL ((uint8_t)0x1C) +#define I2C_REG_TMRISE ((uint8_t)0x20) +#define IS_I2C_REG(REGISTER) \ + (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \ + || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \ + || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE)) +/** + * @} + */ + +/** @addtogroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBALERT_LOW ((uint16_t)0x2000) +#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF) +#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH)) +/** + * @} + */ + +/** @addtogroup I2C_PEC_position + * @{ + */ + +#define I2C_PEC_POS_NEXT ((uint16_t)0x0800) +#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACK_POS_NEXT ((uint16_t)0x0800) +#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_BUF ((uint16_t)0x0400) +#define I2C_INT_EVENT ((uint16_t)0x0200) +#define I2C_INT_ERR ((uint16_t)0x0100) +#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_SMBALERT ((uint32_t)0x01008000) +#define I2C_INT_TIMOUT ((uint32_t)0x01004000) +#define I2C_INT_PECERR ((uint32_t)0x01001000) +#define I2C_INT_OVERRUN ((uint32_t)0x01000800) +#define I2C_INT_ACKFAIL ((uint32_t)0x01000400) +#define I2C_INT_ARLOST ((uint32_t)0x01000200) +#define I2C_INT_BUSERR ((uint32_t)0x01000100) +#define I2C_INT_TXDATE ((uint32_t)0x06000080) +#define I2C_INT_RXDATNE ((uint32_t)0x06000040) +#define I2C_INT_STOPF ((uint32_t)0x02000010) +#define I2C_INT_ADDR10F ((uint32_t)0x02000008) +#define I2C_INT_BYTEF ((uint32_t)0x02000004) +#define I2C_INT_ADDRF ((uint32_t)0x02000002) +#define I2C_INT_STARTBF ((uint32_t)0x02000001) + +#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_INT(IT) \ + (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \ + || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \ + || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \ + || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_flags_definition + * @{ + */ + +/** + * @brief STS2 register flags + */ + +#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000) +#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000) +#define I2C_FLAG_TRF ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSMODE ((uint32_t)0x00010000) + +/** + * @brief STS1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800) +#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400) +#define I2C_FLAG_ARLOST ((uint32_t)0x10000200) +#define I2C_FLAG_BUSERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXDATE ((uint32_t)0x10000080) +#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008) +#define I2C_FLAG_BYTEF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDRF ((uint32_t)0x10000002) +#define I2C_FLAG_STARTBF ((uint32_t)0x10000001) + +#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) \ + (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \ + || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \ + || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \ + || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \ + || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \ + || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \ + || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateStart() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* Master mode */ +#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */ +/* --EV5 */ +#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_SendAddr7bit() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_RecvData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +/* EV7x shifter register full */ +#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_ConfigAck()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled + * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) + * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and + * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV2x */ +#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */ +/* --EV4 */ +#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVT(EVENT) \ + (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS)) +/** + * @} + */ + +/** @addtogroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @addtogroup I2C_clock_speed + * @{ + */ + +//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_Module* I2Cx); +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_InitStruct(I2C_InitType* I2C_InitStruct); +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd); +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); +uint8_t I2C_RecvData(I2C_Module* I2Cx); +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register); +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition); +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition); +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd); +uint8_t I2C_GetPec(I2C_Module* I2Cx); +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlag() function (see below). + * The returned value could be compared to events already defined in the + * library (n32l43x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT); +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..f0633ad4b6b30d66aef850ea258010bab67f5a6a --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h @@ -0,0 +1,145 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_iwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_IWDG_H__ +#define __N32L43X_IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @addtogroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Constants + * @{ + */ + +/** @addtogroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WRITE_ENABLE ((uint16_t)0x5555) +#define IWDG_WRITE_DISABLE ((uint16_t)0x0000) +#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE)) +/** + * @} + */ + +/** @addtogroup IWDG_prescaler + * @{ + */ + +#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00) +#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01) +#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02) +#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03) +#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04) +#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05) +#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV256)) +/** + * @} + */ + +/** @addtogroup IWDG_Flag + * @{ + */ + +#define IWDG_PVU_FLAG ((uint16_t)0x0001) +#define IWDG_CRVU_FLAG ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler); +void IWDG_CntReload(uint16_t Reload); +void IWDG_ReloadKey(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_IWDG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lcd.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..9dee4df8fb19688cc45260772696f26a830bdb48 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lcd.h @@ -0,0 +1,735 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_lcd.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#ifndef __N32L43X_LCD_H__ +#define __N32L43X_LCD_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32l43x.h" +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LCD + * @{ + */ + +/* LCD Exported constants --------------------------------------------------------*/ +/** @addtogroup LCD_Exported_Constants LCD Exported Constants + * @{ + */ + +/** + * @brief LCD error code + */ +typedef enum { + LCD_ERROR_OK = 0x00, /*!< No error */ + LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag error */ + LCD_ERROR_UDR = 0x02, /*!< Update display request flag error */ + LCD_ERROR_UDD = 0x03, /*!< Update display done flag error */ + LCD_ERROR_ENSTS = 0x04, /*!< LCD enabled status flag error */ + LCD_ERROR_RDY = 0x05, /*!< LCD VLCD ready flag error */ + LCD_ERROR_PARAM = 0x06, /*!< LCD function parameter error */ + LCD_ERROR_CLK = 0x07, /*!< LCD clock source fail error */ +}LCD_ErrorTypeDef; + +/** +* @brief LCD normal timeout +*/ +#define LCD_TIME_OUT (0x01000000) + +/** + * @defgroup LCD_Clock_Source + */ +#define LCD_CLK_SRC_LSI (RCC_RTCCLK_SRC_LSI) /*!< LSI*/ +#define LCD_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_RTCCLK_SRC_LSE) /*!< LSE */ +#define LCD_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_RTCCLK_SRC_LSE) /*!< LSE bypass */ +#define LCD_CLK_SRC_HSE_DIV32 (RCC_HSE_ENABLE|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE */ +#define LCD_CLK_SRC_HSE_BYPASS_DIV32 (RCC_HSE_BYPASS|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE bypass */ + +/** + * @} + */ + +/** + * @defgroup LCD_RAMRegister + */ +#define LCD_RAM1_COM0 (0x00000000U) +#define LCD_RAM2_COM0 (0x00000001U) +#define LCD_RAM1_COM1 (0x00000002U) +#define LCD_RAM2_COM1 (0x00000003U) +#define LCD_RAM1_COM2 (0x00000004U) +#define LCD_RAM2_COM2 (0x00000005U) +#define LCD_RAM1_COM3 (0x00000006U) +#define LCD_RAM2_COM3 (0x00000007U) +#define LCD_RAM1_COM4 (0x00000008U) +#define LCD_RAM2_COM4 (0x00000009U) +#define LCD_RAM1_COM5 (0x0000000AU) +#define LCD_RAM2_COM5 (0x0000000BU) +#define LCD_RAM1_COM6 (0x0000000CU) +#define LCD_RAM2_COM6 (0x0000000DU) +#define LCD_RAM1_COM7 (0x0000000EU) +#define LCD_RAM2_COM7 (0x0000000FU) +/** + * @} + */ + +/** + * @defgroup LCD_Prescaler + */ +#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */ +#define LCD_PRESCALER_2 (0x1UL << LCD_FCTRL_PRES_Pos) /*!< 0x00400000U CLKPS = LCDCLK/2 */ +#define LCD_PRESCALER_4 (0x2UL << LCD_FCTRL_PRES_Pos) /*!< 0x00800000U CLKPS = LCDCLK/4 */ +#define LCD_PRESCALER_8 (0x3UL << LCD_FCTRL_PRES_Pos) /*!< 0x00C00000U CLKPS = LCDCLK/8 */ +#define LCD_PRESCALER_16 (0x4UL << LCD_FCTRL_PRES_Pos) /*!< 0x01000000U CLKPS = LCDCLK/16 */ +#define LCD_PRESCALER_32 (0x5UL << LCD_FCTRL_PRES_Pos) /*!< 0x01400000U CLKPS = LCDCLK/32 */ +#define LCD_PRESCALER_64 (0x6UL << LCD_FCTRL_PRES_Pos) /*!< 0x01800000U CLKPS = LCDCLK/64 */ +#define LCD_PRESCALER_128 (0x7UL << LCD_FCTRL_PRES_Pos) /*!< 0x01C00000U CLKPS = LCDCLK/128 */ +#define LCD_PRESCALER_256 (0x8UL << LCD_FCTRL_PRES_Pos) /*!< 0x02000000U CLKPS = LCDCLK/256 */ +#define LCD_PRESCALER_512 (0x9UL << LCD_FCTRL_PRES_Pos) /*!< 0x02400000U CLKPS = LCDCLK/512 */ +#define LCD_PRESCALER_1024 (0xAUL << LCD_FCTRL_PRES_Pos) /*!< 0x02800000U CLKPS = LCDCLK/1024 */ +#define LCD_PRESCALER_2048 (0xBUL << LCD_FCTRL_PRES_Pos) /*!< 0x02C00000U CLKPS = LCDCLK/2048 */ +#define LCD_PRESCALER_4096 (0xCUL << LCD_FCTRL_PRES_Pos) /*!< 0x03000000U CLKPS = LCDCLK/4096 */ +#define LCD_PRESCALER_8192 (0xDUL << LCD_FCTRL_PRES_Pos) /*!< 0x03400000U CLKPS = LCDCLK/8192 */ +#define LCD_PRESCALER_16384 (0xEUL << LCD_FCTRL_PRES_Pos) /*!< 0x03800000U CLKPS = LCDCLK/16384 */ +#define LCD_PRESCALER_32768 (0xFUL << LCD_FCTRL_PRES_Pos) /*!< 0x03C00000U CLKPS = LCDCLK/32768 */ +/** + * @} + */ + +/** + * @defgroup LCD_Divider + */ +#define LCD_DIV_16 (0x00000000U) /*!< CLKDIV = CLKPS/(16) */ +#define LCD_DIV_17 (0x1UL << LCD_FCTRL_DIV_Pos) /*!< 0x00040000U CLKDIV = CLKPS/(17) */ +#define LCD_DIV_18 (0x2UL << LCD_FCTRL_DIV_Pos) /*!< 0x00080000U CLKDIV = CLKPS/(18) */ +#define LCD_DIV_19 (0x3UL << LCD_FCTRL_DIV_Pos) /*!< 0x000C0000U CLKDIV = CLKPS/(19) */ +#define LCD_DIV_20 (0x4UL << LCD_FCTRL_DIV_Pos) /*!< 0x00100000U CLKDIV = CLKPS/(20) */ +#define LCD_DIV_21 (0x5UL << LCD_FCTRL_DIV_Pos) /*!< 0x00140000U CLKDIV = CLKPS/(21) */ +#define LCD_DIV_22 (0x6UL << LCD_FCTRL_DIV_Pos) /*!< 0x00180000U CLKDIV = CLKPS/(22) */ +#define LCD_DIV_23 (0x7UL << LCD_FCTRL_DIV_Pos) /*!< 0x001C0000U CLKDIV = CLKPS/(23) */ +#define LCD_DIV_24 (0x8UL << LCD_FCTRL_DIV_Pos) /*!< 0x00200000U CLKDIV = CLKPS/(24) */ +#define LCD_DIV_25 (0x9UL << LCD_FCTRL_DIV_Pos) /*!< 0x00240000U CLKDIV = CLKPS/(25) */ +#define LCD_DIV_26 (0xAUL << LCD_FCTRL_DIV_Pos) /*!< 0x00280000U CLKDIV = CLKPS/(26) */ +#define LCD_DIV_27 (0xBUL << LCD_FCTRL_DIV_Pos) /*!< 0x002C0000U CLKDIV = CLKPS/(27) */ +#define LCD_DIV_28 (0xCUL << LCD_FCTRL_DIV_Pos) /*!< 0x00300000U CLKDIV = CLKPS/(28) */ +#define LCD_DIV_29 (0xDUL << LCD_FCTRL_DIV_Pos) /*!< 0x00340000U CLKDIV = CLKPS/(29) */ +#define LCD_DIV_30 (0xEUL << LCD_FCTRL_DIV_Pos) /*!< 0x00380000U CLKDIV = CLKPS/(30) */ +#define LCD_DIV_31 (0xFUL << LCD_FCTRL_DIV_Pos) /*!< 0x003C0000U CLKDIV = CLKPS/(31) */ +/** + * @} + */ + +/** + * @defgroup LCD_Duty + */ +#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */ +#define LCD_DUTY_1_2 (0x1UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/2 duty */ +#define LCD_DUTY_1_3 (0x2UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/3 duty */ +#define LCD_DUTY_1_4 (0x3UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/4 duty */ +#define LCD_DUTY_1_8 (0x4UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/8 duty */ +/** + * @} + */ + +/** + * @defgroup LCD_Bias + */ +#define LCD_BIAS_1_2 (0x00000000U) /*!< 1/2 Bias */ +#define LCD_BIAS_1_3 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000020U 1/3 Bias */ +#define LCD_BIAS_1_4 (0x2UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000040U 1/4 Bias */ +/** + * @} + */ + +/** + * @defgroup LCD_Voltage_source + */ +#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_EXTERNAL (LCD_CTRL_VSEL) /*!< External voltage source for the LCD */ +/** + * @} + */ + +/** + * @defgroup LCD_Contrast + */ +#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_1 (0x1UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000400U Maximum Voltage = 2.73V */ +#define LCD_CONTRASTLEVEL_2 (0x2UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000800U Maximum Voltage = 2.86V */ +#define LCD_CONTRASTLEVEL_3 (0x3UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000C00U Maximum Voltage = 2.99V */ +#define LCD_CONTRASTLEVEL_4 (0x4UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001000U Maximum Voltage = 3.12V */ +#define LCD_CONTRASTLEVEL_5 (0x5UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001400U Maximum Voltage = 3.26V */ +#define LCD_CONTRASTLEVEL_6 (0x6UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001800U Maximum Voltage = 3.40V */ +#define LCD_CONTRASTLEVEL_7 (0x7UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001C00U Maximum Voltage = 3.55V */ +/** + * @} + */ + +/** + * @defgroup LCD_DeadTime + */ +#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */ +#define LCD_DEADTIME_1 (0x1UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000080U One Phase between different couple of Frame */ +#define LCD_DEADTIME_2 (0x2UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000100U Two Phase between different couple of Frame */ +#define LCD_DEADTIME_3 (0x3UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000180UThree Phase between different couple of Frame */ +#define LCD_DEADTIME_4 (0x4UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000200UFour Phase between different couple of Frame */ +#define LCD_DEADTIME_5 (0x5UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000280UFive Phase between different couple of Frame */ +#define LCD_DEADTIME_6 (0x6UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000300USix Phase between different couple of Frame */ +#define LCD_DEADTIME_7 (0x7UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000380USeven Phase between different couple of Frame */ +/** + * @} + */ + +/** + * @defgroup LCD_PulseOnDuration + */ +#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_1 (0x1U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000010U Pulse ON duration = 1/CK_PS */ +#define LCD_PULSEONDURATION_2 (0x2U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000020U Pulse ON duration = 2/CK_PS */ +#define LCD_PULSEONDURATION_3 (0x3U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000030U Pulse ON duration = 3/CK_PS */ +#define LCD_PULSEONDURATION_4 (0x4U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000040U Pulse ON duration = 4/CK_PS */ +#define LCD_PULSEONDURATION_5 (0x5U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000050U Pulse ON duration = 5/CK_PS */ +#define LCD_PULSEONDURATION_6 (0x6U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000060U Pulse ON duration = 6/CK_PS */ +#define LCD_PULSEONDURATION_7 (0x7U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000070U Pulse ON duration = 7/CK_PS */ +/** + * @} + */ + +/** + * @defgroup LCD_HighDrive + */ +#define LCD_HIGHDRIVE_DISABLE (0x00000000U) /*!< High drive disabled */ +#define LCD_HIGHDRIVE_ENABLE (LCD_FCTRL_HDEN) /*!< High drive enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_HighDrive_Buffer + */ +#define LCD_HIGHDRIVEBUFFER_DISABLE (0x00000000U) /*!< High drive buffer disabled */ +#define LCD_HIGHDRIVEBUFFER_ENABLE (LCD_CTRL_BUFEN) /*!< High drive buffer enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_Blink_Mode + */ +#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disable */ +#define LCD_BLINKMODE_SEG0_COM0 (0x1UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00010000U Blink enabled on SEG[0], COM[0] (1 pixel) */ +#define LCD_BLINKMODE_SEG0_ALLCOM (0x2UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00020000U Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */ +#define LCD_BLINKMODE_ALLSEG_ALLCOM (0x3UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00030000U Blink enabled on all SEG and all COM (all pixels) */ +/** + * @} + */ + +/** + * @defgroup LCD_Blink_Frequency + */ +#define LCD_BLINKFREQ_DIV_8 (0x00000000U) /*!< The Blink frequency = fck_div/8 */ +#define LCD_BLINKFREQ_DIV_16 (0x1UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00002000U The Blink frequency = fck_div/16 */ +#define LCD_BLINKFREQ_DIV_32 (0x2UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00004000U The Blink frequency = fck_div/32 */ +#define LCD_BLINKFREQ_DIV_64 (0x3UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00006000U The Blink frequency = fck_div/64 */ +#define LCD_BLINKFREQ_DIV_128 (0x4UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00008000U The Blink frequency = fck_div/128 */ +#define LCD_BLINKFREQ_DIV_256 (0x5UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000A000U The Blink frequency = fck_div/256 */ +#define LCD_BLINKFREQ_DIV_512 (0x6UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000C000U The Blink frequency = fck_div/512 */ +#define LCD_BLINKFREQ_DIV_1024 (0x7UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000E000U The Blink frequency = fck_div/1024 */ +/** + * @} + */ + +/** + * @defgroup LCD_MuxSegment + */ +#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< Mux segment disabled */ +#define LCD_MUXSEGMENT_ENABLE (LCD_CTRL_MUXSEG) /*!< Mux segment enabled */ +/** + * @} + */ + +/** + * @defgroup LCD_Interrupt + */ +#define LCD_IT_UDD (LCD_FCTRL_UDDIE) /*!< Update display done interrupt */ +#define LCD_IT_SOF (LCD_FCTRL_SOFIE) /*!< Start of frame interrupt */ +/** + * @} + */ + +/** + * @defgroup LCD_Flag + */ +#define LCD_FLAG_ENSTS (LCD_STS_ENSTS) /*!< LCD enable flag*/ +#define LCD_FLAG_SOF (LCD_STS_SOF) /*!< LCD start of frame event flag*/ +#define LCD_FLAG_UDR (LCD_STS_UDR) /*!< Update display request Flag*/ +#define LCD_FLAG_UDD (LCD_STS_UDD) /*!< Update display done event flag */ +#define LCD_FLAG_RDY (LCD_STS_RDY) /*!< Ready flag */ +#define LCD_FLAG_FCRSF (LCD_STS_FCRSF) /*!< LCD frame control register synchronization flag */ +/** + * @} + */ + +/** + * @defgroup LCD_Flag_Clear + */ +#define LCD_FLAG_SOF_CLEAR (LCD_CLR_SOFCLR) /*!< Clear LCD start of frame event flag*/ +#define LCD_FLAG_UDD_CLEAR (LCD_CLR_UDDCLR) /*!< Clear Update display done event flag */ +/** + * @} + */ + + +/* LCD Exported macros -----------------------------------------------------------*/ +/** @defgroup LCD_Exported_Macros LCD Exported Macros + * @{ + */ + +/** @brief Enable the LCD peripheral. + * @param None + * @retval None + */ +#define __LCD_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_LCDEN) + +/** @brief Disable the LCD peripheral. + * @param None + * @retval None + */ +#define __LCD_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_LCDEN) + +/** @brief Enable the LCD voltage output buffer. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_BUF_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_BUFEN) + +/** @brief Disable the LCD voltage output buffer. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_BUF_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_BUFEN) + +/** @brief Enable the LCD mux segment. + * @param None + * @retval None + */ +#define __LCD_MUXSEG_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_MUXSEG) + +/** @brief Disable the LCD mux segment. + * @param None + * @retval None + */ +#define __LCD_MUXSEG_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_MUXSEG) + +/** @brief Select internal VLCD as LCD voltage source + * @param None + * @retval None + */ +#define __LCD_SELECT_INTERNAL_VLCD() CLEAR_BIT(LCD->CTRL, LCD_CTRL_VSEL) + +/** @brief Select external VLCD as LCD voltage source + * @param None + * @retval None + */ +#define __LCD_SELECT_EXTERNAL_VLCD() SET_BIT(LCD->CTRL, LCD_CTRL_VSEL) + +/** @brief Enable the LCD high driver mode. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_ENABLE() SET_BIT(LCD->FCTRL, LCD_FCTRL_HDEN) + +/** @brief Disable the LCD high driver mode. + * @param None + * @retval None + */ +#define __LCD_HIGHDRIVE_DISABLE() CLEAR_BIT(LCD->FCTRL, LCD_FCTRL_HDEN) + +/** @brief Config the prescaler factor + * @param __PRES__ specifies the LCD prescaler + * This parameter can be one of the following values: + * @arg LCD_PRESCALER_1: CLKPS = LCDCLK + * @arg LCD_PRESCALER_2: CLKPS = LCDCLK/2 + * @arg LCD_PRESCALER_4: CLKPS = LCDCLK/4 + * @arg LCD_PRESCALER_8: CLKPS = LCDCLK/8 + * @arg LCD_PRESCALER_16: CLKPS = LCDCLK/16 + * @arg LCD_PRESCALER_32: CLKPS = LCDCLK/32 + * @arg LCD_PRESCALER_64: CLKPS = LCDCLK/64 + * @arg LCD_PRESCALER_128: CLKPS = LCDCLK/128 + * @arg LCD_PRESCALER_256: CLKPS = LCDCLK/256 + * @arg LCD_PRESCALER_512: CLKPS = LCDCLK/512 + * @arg LCD_PRESCALER_1024: CLKPS = LCDCLK/1024 + * @arg LCD_PRESCALER_2048: CLKPS = LCDCLK/2048 + * @arg LCD_PRESCALER_4096: CLKPS = LCDCLK/4096 + * @arg LCD_PRESCALER_8192: CLKPS = LCDCLK/8192 + * @arg LCD_PRESCALER_16384: CLKPS = LCDCLK/16384 + * @arg LCD_PRESCALER_32768: CLKPS = LCDCLK/32768 + * @retval None + */ +#define __LCD_PRESCALER_CONFIG(__PRES__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PRES,__PRES__) + +/** @brief Config the divider factor + * @param __DIV__ specifies the LCD divider + * This parameter can be one of the following values: + * @arg LCD_DIV_16: CLKDIV = CLKPS/(16) + * @arg LCD_DIV_17: CLKDIV = CLKPS/(17) + * @arg LCD_DIV_18: CLKDIV = CLKPS/(18) + * @arg LCD_DIV_19: CLKDIV = CLKPS/(19) + * @arg LCD_DIV_20: CLKDIV = CLKPS/(20) + * @arg LCD_DIV_21: CLKDIV = CLKPS/(21) + * @arg LCD_DIV_22: CLKDIV = CLKPS/(22) + * @arg LCD_DIV_23: CLKDIV = CLKPS/(23) + * @arg LCD_DIV_24: CLKDIV = CLKPS/(24) + * @arg LCD_DIV_25: CLKDIV = CLKPS/(25) + * @arg LCD_DIV_26: CLKDIV = CLKPS/(26) + * @arg LCD_DIV_27: CLKDIV = CLKPS/(27) + * @arg LCD_DIV_28: CLKDIV = CLKPS/(28) + * @arg LCD_DIV_29: CLKDIV = CLKPS/(29) + * @arg LCD_DIV_30: CLKDIV = CLKPS/(30) + * @arg LCD_DIV_31: CLKDIV = CLKPS/(31) + * @retval None + */ +#define __LCD_DIVIDER_CONFIG(__DIV__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DIV,__DIV__) + +/** @brief Config the blink mode and frequency + * @param __BLINKMODE__ specifies the LCD blink mode + * This parameter can be one of the following values: + * @arg LCD_DIV_16: CLKDIV = CLKPS/(16) + * @arg LCD_BLINKMODE_OFF: Blink disable + * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) + * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) + * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels) + * @param __BLINKFREQUENCY__ specifies the LCD blink frequency + * This parameter can be one of the following values: + * @arg LCD_BLINKFREQ_DIV_8: The Blink frequency = fck_div/8 + * @arg LCD_BLINKFREQ_DIV_16: The Blink frequency = fck_div/16 + * @arg LCD_BLINKFREQ_DIV_32: The Blink frequency = fck_div/32 + * @arg LCD_BLINKFREQ_DIV_64: The Blink frequency = fck_div/64 + * @arg LCD_BLINKFREQ_DIV_128: The Blink frequency = fck_div/128 + * @arg LCD_BLINKFREQ_DIV_256: The Blink frequency = fck_div/256 + * @arg LCD_BLINKFREQ_DIV_512: The Blink frequency = fck_div/512 + * @arg LCD_BLINKFREQ_DIV_1024: The Blink frequency = fck_div/1024 + * @retval None + */ +#define __LCD_BLINK_CONFIG(__BLINKMODE__,__BLINKFREQUENCY__) MODIFY_REG(LCD->FCTRL, (LCD_FCTRL_BLINK|LCD_FCTRL_BLINKF),(__BLINKMODE__|__BLINKFREQUENCY__)) + + +/** @brief Config the contrast + * @param __CONTRAST__ specifies the LCD contrast + * This parameter can be one of the following values: + * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V + * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V + * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V + * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V + * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V + * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.26V + * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.40V + * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.55V + * @retval None + */ +#define __LCD_CONTRAST_CONFIG(__CONTRAST__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_CONTRAST,__CONTRAST__) + +/** @brief Config the dead time + * @param __CONTRAST__ specifies the LCD dead time + * This parameter can be one of the following values: + * @arg LCD_DEADTIME_0: No dead Time + * @arg LCD_DEADTIME_1: One Phase between different couple of Frame + * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame + * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame + * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame + * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame + * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame + * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame + * @retval None + */ +#define __LCD_DEADTIME_CONFIG(__DEADTIME__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DEAD,__DEADTIME__) + +/** @brief Config the pulse on duration + * @param __PULSEON__ specifies the LCD pulse on duration in terms of + * CK_PS (prescaled LCD clock period) pulses. + * This parameter can be one of the following values: + * @arg LCD_PULSEONDURATION_0: 0 pulse + * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS + * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS + * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS + * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS + * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS + * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS + * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS + * @retval None + */ +#define __LCD_PULSEONDURATION_CONFIG(__PULSEON__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PULSEON,__PULSEON__) + +/** @brief Enable the specified LCD interrupt. + * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt + * @retval None + */ +#define __LCD_ENABLE_IT(__INTERRUPT__) SET_BIT(LCD->FCTRL, __INTERRUPT__) + +/** @brief Disable the specified LCD interrupt. + * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt + * @retval None + */ +#define __LCD_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(LCD->FCTRL, __INTERRUPT__) + +/** @brief Check whether the specified LCD interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the LCD interrupt source to check. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt. + * @retval The state of __INTERRUPT__ + */ +#define __LCD_GET_IT_SOURCE(__INTERRUPT__) ((LCD->FCTRL) & (__INTERRUPT__)) + +/** @brief Set LCD UDR flag for update dispaly request + * @param None + * @retval None + */ +#define __LCD_UPDATE_REQUEST() SET_BIT(LCD->STS, LCD_FLAG_UDR) + +/** @brief Check whether the specified LCD flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. + * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR + * goes from 0 to 1. On deactivation it reflects the real status of + * LCD so it becomes 0 at the end of the last displayed frame. + * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at + * the beginning of a new frame, at the same time as the display data is + * updated. + * @arg LCD_FLAG_UDR: Update Display Request flag. + * @arg LCD_FLAG_UDD: Update Display Done flag. + * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status + * of the step-up converter. + * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. + * This flag is set by hardware each time the LCD_FCR register is updated + * in the LCDCLK domain. + * @retval The new state of __FLAG__ + */ +#define __LCD_GET_FLAG(__FLAG__) (((LCD->STS) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified LCD pending flag. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LCD_FLAG_SOF_CLEAR: Start of Frame Interrupt + * @arg LCD_FLAG_UDD_CLEAR: Update Display Done Interrupt + * @retval None + */ +#define __LCD_CLEAR_FLAG(__FLAG__) \ + do { \ + SET_BIT((LCD->CLR), (__FLAG__)); \ + CLEAR_BIT((LCD->CLR), (__FLAG__)); \ + }while(0) + +/** @brief Config LCD to keep display in STOP2 mode. + * @param None + * @retval None + */ +#define __LCD_DISPLAY_IN_STOP2() \ + do { \ + SET_BIT(*(__IO uint32_t *)(PWR_BASE+0x08), (0x1UL << 21)); \ + CLEAR_BIT(*(__IO uint32_t *)(PWR_BASE+0x1c), (0x1UL << 7)); \ + }while(0) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LCD_Private_Macros LCD Private Macros + * @{ + */ +#define IS_LCD_RAM_REGISTER_INDEX(__RAMRegIndex__) ((__RAMRegIndex__)<=LCD_RAM2_COM7) + +#define IS_LCD_PRESCALER(_PRESCALER_) \ + (((_PRESCALER_)==LCD_PRESCALER_1) ||((_PRESCALER_)==LCD_PRESCALER_2) \ + ||((_PRESCALER_)==LCD_PRESCALER_4) ||((_PRESCALER_)==LCD_PRESCALER_8) \ + ||((_PRESCALER_)==LCD_PRESCALER_16) ||((_PRESCALER_)==LCD_PRESCALER_32) \ + ||((_PRESCALER_)==LCD_PRESCALER_64) ||((_PRESCALER_)==LCD_PRESCALER_128) \ + ||((_PRESCALER_)==LCD_PRESCALER_256) ||((_PRESCALER_)==LCD_PRESCALER_512) \ + ||((_PRESCALER_)==LCD_PRESCALER_1024)||((_PRESCALER_)==LCD_PRESCALER_2048) \ + ||((_PRESCALER_)==LCD_PRESCALER_4096)||((_PRESCALER_)==LCD_PRESCALER_8192) \ + ||((_PRESCALER_)==LCD_PRESCALER_16384)||((_PRESCALER_)==LCD_PRESCALER_32768)) + +#define IS_LCD_DIVIDER(__DIVIDER__) \ + (((__DIVIDER__)==LCD_DIV_16)||((__DIVIDER__)==LCD_DIV_17)||((__DIVIDER__)==LCD_DIV_18) \ + ||((__DIVIDER__)==LCD_DIV_19)||((__DIVIDER__)==LCD_DIV_20)||((__DIVIDER__)==LCD_DIV_21) \ + ||((__DIVIDER__)==LCD_DIV_22)||((__DIVIDER__)==LCD_DIV_23)||((__DIVIDER__)==LCD_DIV_24) \ + ||((__DIVIDER__)==LCD_DIV_25)||((__DIVIDER__)==LCD_DIV_26)||((__DIVIDER__)==LCD_DIV_27) \ + ||((__DIVIDER__)==LCD_DIV_28)||((__DIVIDER__)==LCD_DIV_29)||((__DIVIDER__)==LCD_DIV_30) \ + ||((__DIVIDER__)==LCD_DIV_31)) + +#define IS_LCD_DUTY(__DUTY__) \ + (((__DUTY__)==LCD_DUTY_STATIC)||((__DUTY__)==LCD_DUTY_1_2) \ + ||((__DUTY__)==LCD_DUTY_1_3) ||((__DUTY__)==LCD_DUTY_1_4) \ + ||((__DUTY__)==LCD_DUTY_1_8) ) + +#define IS_LCD_BIAS(__BIAS__) \ + (((__BIAS__)==LCD_BIAS_1_2)||((__BIAS__)==LCD_BIAS_1_3)||((__BIAS__)==LCD_BIAS_1_4)) + +#define IS_LCD_VOLTAGESOURCE(__SOURCE__) \ + (((__SOURCE__)==LCD_VOLTAGESOURCE_INTERNAL)||((__SOURCE__)==LCD_VOLTAGESOURCE_EXTERNAL)) + +#define IS_LCD_CONTRASTLEVEL(__CONTRAST__) \ + (((__CONTRAST__)==LCD_CONTRASTLEVEL_0) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_1) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_2) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_3) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_4) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_5) \ + ||((__CONTRAST__)==LCD_CONTRASTLEVEL_6) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_7)) + +#define IS_LCD_DEADTIME(__DEADTIME__) \ + (((__DEADTIME__)==LCD_DEADTIME_0) ||((__DEADTIME__)==LCD_DEADTIME_1) \ + ||((__DEADTIME__)==LCD_DEADTIME_2) ||((__DEADTIME__)==LCD_DEADTIME_3) \ + ||((__DEADTIME__)==LCD_DEADTIME_4) ||((__DEADTIME__)==LCD_DEADTIME_5) \ + ||((__DEADTIME__)==LCD_DEADTIME_6) ||((__DEADTIME__)==LCD_DEADTIME_7)) + +#define IS_LCD_PULSEONDURATION(__PULSE__) \ + (((__PULSE__)==LCD_PULSEONDURATION_0) ||((__PULSE__)==LCD_PULSEONDURATION_1) \ + ||((__PULSE__)==LCD_PULSEONDURATION_2) ||((__PULSE__)==LCD_PULSEONDURATION_3) \ + ||((__PULSE__)==LCD_PULSEONDURATION_4) ||((__PULSE__)==LCD_PULSEONDURATION_5) \ + ||((__PULSE__)==LCD_PULSEONDURATION_6) ||((__PULSE__)==LCD_PULSEONDURATION_7)) + +#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) \ + ((((__HIGHDRIVE__))==LCD_HIGHDRIVE_DISABLE)||(((__HIGHDRIVE__))==LCD_HIGHDRIVE_ENABLE)) + +#define IS_LCD_HIGHDRIVEBUFFER(__HIGHDRIVEBUF__) \ + (((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_DISABLE)||((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_ENABLE)) + +#define IS_LCD_BLINKMODE(__BLINKMODE__) \ + (((__BLINKMODE__)==LCD_BLINKMODE_OFF) ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_COM0) \ + ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_ALLCOM) ||((__BLINKMODE__)==LCD_BLINKMODE_ALLSEG_ALLCOM)) + +#define IS_LCD_BLINKFREQ(__BLINKFREQ__) \ + (((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_8) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_16) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_32) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_64) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_128) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_256) \ + ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_512) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_1024)) + +#define IS_LCD_MUXSEGMENT(__MUXSEG__) \ + (((__MUXSEG__)==LCD_MUXSEGMENT_DISABLE)||((__MUXSEG__)==LCD_MUXSEGMENT_ENABLE)) + +#define IS_LCD_FLAG(__FLAG__) \ + (((__FLAG__)==LCD_FLAG_ENSTS)||((__FLAG__)==LCD_FLAG_SOF) \ + ||((__FLAG__)==LCD_FLAG_UDR)||((__FLAG__)==LCD_FLAG_UDD) \ + ||((__FLAG__)==LCD_FLAG_RDY)||((__FLAG__)==LCD_FLAG_FCRSF)) + +#define IS_LCD_CLR_FLAG(__CLEARFLAG__) (((__CLEARFLAG__)==LCD_FLAG_SOF_CLEAR)||((__CLEARFLAG__)==LCD_FLAG_UDD_CLEAR) + + +/** + * @brief LCD Init structure definition + */ + +typedef struct +{ + uint32_t Prescaler; /*!< Configures the LCD Prescaler. + This parameter can be one value of @ref LCD_Prescaler */ + uint32_t Divider; /*!< Configures the LCD Divider. + This parameter can be one value of @ref LCD_Divider */ + uint32_t Duty; /*!< Configures the LCD Duty. + This parameter can be one value of @ref LCD_Duty */ + uint32_t Bias; /*!< Configures the LCD Bias. + This parameter can be one value of @ref LCD_Bias */ + uint32_t VoltageSource; /*!< Selects the LCD Voltage source. + This parameter can be one value of @ref LCD_Voltage_source */ + uint32_t Contrast; /*!< Configures the LCD Contrast. + This parameter can be one value of @ref LCD_Contrast */ + uint32_t DeadTime; /*!< Configures the LCD Dead Time. + This parameter can be one value of @ref LCD_DeadTime */ + uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. + This parameter can be one value of @ref LCD_PulseOnDuration */ + uint32_t HighDrive; /*!< Enable or disable the permanent high driver. + This parameter can be one value of @ref LCD_HighDrive */ + uint32_t HighDriveBuffer; /*!< Enable or disable the high driver buffer. + This parameter can be one value of @ref LCD_HighDrive_Buffer */ + uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. + This parameter can be one value of @ref LCD_Blink_Mode */ + uint32_t BlinkFreq; /*!< Configures the LCD Blink frequency. + This parameter can be one value of @ref LCD_Blink_Frequency */ + uint32_t MuxSegment; /*!< Enable or disable mux segment. + This parameter can be one value of @ref LCD_MuxSegment */ +}LCD_InitType; + + +/** @addtogroup LCD_Exported_Functions + * @{ + */ +LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure ); +void LCD_DeInit(void); + +LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource); + +void LCD_RamClear(void); + +LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void); + +LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData); + + +LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData); + +LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData); + +LCD_ErrorTypeDef LCD_WaitForSynchro(void); + +/** + * @} + */ + + + +#ifdef __cplusplus + } +#endif + +#endif /* __N32L43X_LCD_H__ */ + /** + * @} + */ + + /** + * @} + */ + + /** + * @} + */ + + diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h new file mode 100644 index 0000000000000000000000000000000000000000..4d8de8ab0c9381bfece9e23080c2f39c78e06d9f --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h @@ -0,0 +1,240 @@ +#ifndef __N32L43X_LPRCNT_H__ +#define __N32L43X_LPRCNT_H__ +#include "n32l43x.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* LPRCNT CH_TH mask */ +#define DACREF_default ((uint32_t)0xFFC0FFFF) //Ƚڲοѹ + +/* LPRCNT Chanal define */ +typedef enum +{ + CHANNEL_0 = 0, + CHANNEL_1 = 1, + CHANNEL_2 = 2, +} CHANNELX; + +#define CHANNEL_ERROR 0xff +/* LPRCNT VibrationPowerSelect mask */ +#define POWERSELECT1V5 0 //1.5V +#define POWERSELECT1V65 1 //1.65V +#define POWERSELECT1V8 2 //1.8V +#define POWERSELECT2V0 3 //2.0V + + +/* LPRCNT the alarm sensor scan frequence mask */ +#define FRETIME4 0 +#define FRETIME8 1 +#define FRETIME16 2 +#define FRETIME32 3 +/* LPRCNT MSI division factor mask */ +#define LPRCNT_PRESCALER_DIV1 0x00000000U +#define LPRCNT_PRESCALER_DIV2 0x00010000U +#define LPRCNT_PRESCALER_DIV4 0x00020000U +#define LPRCNT_PRESCALER_DIV8 0x00030000U + +#define LPRCNT_ALMFRE_DIV4 0x00000000U +#define LPRCNT_ALMFRE_DIV8 0x04000000U +#define LPRCNT_ALMFRE_DIV16 0x08000000U +#define LPRCNT_ALMFRE_DIV32 0x0c000000U +/* LPRCNT interrupt mask */ +#define CALIBRATION_INT LPRCNT_CTRL_CALIE +#define REPORT_INT LPRCNT_CTRL_RPTIE +#define ALARM_INT LPRCNT_CTRL_ALMIE +/* LPRCNT interrupt flag mask */ +#define CALIBRATION_INT_FLAG LPRCNT_INTSTS_CALIF +#define REPORT_INT_FLAG LPRCNT_INTSTS_RPTIF +#define ALARM_INT_FLAG LPRCNT_INTSTS_ALMIF +//CMD register +#define START 1 +#define STOP 2 +#define CLEAR 4 +#define CMD_REG_CLR 0x03 +//work mode +#define LPRCNT_MODE 1 +#define CAL_MODE 0 + + +//Time register +#define CLEAR_TIME_VALE 0xFF00C0C0 +//TH register +#define CLEAR_TH_VALE 0xFFFF0000 + +/** + * @brief LPRCNT COMP definition + */ +//COMP bits Clear mask +//#define CMP_HYSEL_CLEAR ((uint32_t)0xFFD8F300) +//#define CMP_INMSEL_CLEAR ((uint32_t)0xFFD88F00) +//#define CMP_FILTH_CLEAR ((uint32_t)0xFD68FF00) + //Filter threshold control +#define CMP_FILTH_MODE0 ((uint32_t)0x00000000) +#define CMP_FILTH_MODE1 ((uint32_t)0x00800000) +#define CMP_FILTH_MODE2 ((uint32_t)0x01000000) + +/** + * @brief define LPRCNT some funtion + */ + +//#define STARTSTS(void) ((bool)(LPRCNT->CMD & 0x01) //read start status +#define LPRCNTModeEnable(mode) do{LPRCNT->CMD &= (~CMD_REG_CLR); LPRCNT->CMD |= (uint32_t)mode;}while(0)//set LPRCNT module CMD . +#define SetLPRCNTWorkMode(mode) do{LPRCNT->CTRL &= (~LPRCNT_CTRL_RCNTM); LPRCNT->CTRL |= (uint32_t)(mode << 24);}while(0)//calibration mode or LPRCNT mode +/** + * @brief define Auto detection + */ +#define AUTODETPERIOD4 0 //count overflow 4*pulse period +#define AUTODETPERIOD8 1 //count overflow 8*pulse period +/**************************************************************************************************************************************/ +/* function structure variable */ +/**************************************************************************************************************************************/ +typedef enum +{ + HYST_NO = (0x0L << 10), + HYST_LOW = (0x1L << 10), + HYST_MID = (0x2L << 10), + HYST_HIGH = (0x3L << 10), +} LPRCNT_COMP_CTRL_HYST; + +typedef enum { + //comp1 inm sel + INMSEL_NC = ((uint32_t)0x00000000), + INMSEL_DAC1 = ((uint32_t)0x00001000), + INMSEL_PA0 = ((uint32_t)0x00002000), + INMSEL_PA5 = ((uint32_t)0x00003000), + INMSEL_PB5 = ((uint32_t)0x00004000), + INMSEL_PD4 = ((uint32_t)0x00005000), + INMSEL_VREF_VC1 = ((uint32_t)0x00006000), + INMSEL_VREF_VC2 = ((uint32_t)0x00007000), +}LPRCNT_COMP_CTRL_INMSEL; +/** + * @brief LPRCNT Init structure definition + */ +typedef struct +{ + uint8_t vibrationtime; + uint8_t dischargetime; + uint8_t chargetime; +} LPRCNT_InitTime; +typedef struct +{ + uint8_t dacreference; + uint8_t undampedTh; + uint8_t dampedTh; +} LPRCNT_InitThreshold; +typedef struct +{ + uint16_t low_speed; + uint8_t hight_speed; + uint8_t swtich_time; +} LPRCNT_Initfrequence; +typedef struct +{ + uint8_t Channel[3]; + uint8_t ChargeVol; + uint8_t WorkMode; + LPRCNT_InitTime ChTime[3]; + LPRCNT_InitThreshold ChTH[3]; + LPRCNT_Initfrequence NormalFreq; + uint8_t AlarmFreq; + uint32_t PrescaleDiv; + uint16_t Circle; + FunctionalState AutoDetEn; + bool AutoWaitPer; + FunctionalState IntEn; + uint32_t Int; + +} LPRCNT_InitType; + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + bool LowPoweMode; //low power mode + LPRCNT_COMP_CTRL_HYST Hyst; //COMP hysteresis + LPRCNT_COMP_CTRL_INMSEL InmSel; //COMP input minus selection + uint16_t ClkPsc; +} LPRCNT_COMP_InitType; + + +/**************************************************************************************************************************************/ +/* specail registers */ +/**************************************************************************************************************************************/ +//LPRCNT module setup time +#define DacSetupTime(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_DACSET); LPRCNT->CAL2 |= (uint32_t)(time);}while(0)//time < 64 ,6bit +#define CompSetupTime(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_CMPSET); LPRCNT->CAL2 |= (uint32_t)(time << 8);}while(0)//time < 64 ,6bit + +#define DacSetupTimeConfig() DacSetupTime(20) +#define CompSetupTimeConfig() CompSetupTime(31) + +#define RcntAdjustCircleNum(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_RCNTADJ); LPRCNT->CAL2 |= (uint32_t)(time << 20);}while(0)//time < 16 ,4bit +#define ChargeAndDischargeGap(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_GAP); LPRCNT->CAL2 |= (uint32_t)(time << 16);}while(0)//time < 16 ,4bit +//Analog filter +#define POPH 0 +#define NEPH 1 +#define ANGFILT_TH (__IO unsigned*)(0x40001800 + 0x1c) +#define ANGFILT_CTRL (__IO unsigned*)(0x40001800 + 0x28) +#define CLERR_ANGTH 0xffffff87 //bit3~6 +#define CLERR_ANGPHA 0xffffefff //bit12 +#define SetAnalogFilterTh(vale) do{(*ANGFILT_TH) &= CLERR_ANGTH;(*ANGFILT_TH) |= (uint32_t)(vale <<3);}while(0) //vale only equal to 0,1,3,8,12 +#define CompAnalogFilterPhase(dir) do{(*ANGFILT_CTRL) &= CLERR_ANGPHA;(*ANGFILT_CTRL) |= (uint32_t)(dir << 12);}while(0)//Analog filtering phase selection +//auto control set funtion +#define PwrAutoChargeEnable(cmd) do{LPRCNT->CAL3 & = (~LPRCNT_CAL3_PWR_DUR_EN);(LPRCNT->CAL3)|= (uint32_t)(cmd <<7);}while(0)//0 :enable 1:disable + +/**************************************************************************************************************************************/ +/* function declaration */ +/**************************************************************************************************************************************/ +void ClearITPendingBit(uint32_t intflag); +void COMP_1_2_IRQHandler(void); +void LPRCNT_IE(uint32_t MODE_IE ,FunctionalState NewState); +void CfgChannelTime(uint8_t Ch,uint8_t VibrationTime ,uint8_t DischargeTime,uint8_t ChargeTime); +void CfgChannelDacRefVol(uint8_t Ch,uint8_t DacRef); +void CfgChannelThr(uint8_t Ch, uint8_t UndampedTh, uint8_t DampedTh); +void SetMsiClkPrescale(uint32_t Div); +void SetAutoReportCircle(uint16_t Circle); +void SetScanAverageValue(uint8_t N); +void SetVibrationPower(uint8_t Value); +void SetNormalSensorScanfrequence(uint16_t low_speed,uint8_t hight_speed,uint8_t swtich_time); +void SetAlarmSensorScanfrequence(uint8_t Period); +void SetAutoDetect(FunctionalState NewState ); +void SetAutoDetectEnale(FunctionalState NewState ); +void SetAutoDetectPeriod(bool per); +uint8_t GetSampleMode(void); +uint8_t GetChannelSensorWavesNum(uint8_t Ch); +uint8_t GetChannelSensorState(uint8_t Ch); +uint16_t GetRotationCircle(void); +uint16_t GetSetRcnt(void); +void ClrRcntCircle(void); +void SetPwrAutoCharge(bool En); +bool ReadStartState(void); +void LPRCNTInit(LPRCNT_InitType* LPRCNT_InitStruct); +void DAC_CMP_ALWSONCmd(FunctionalState NewState); + +void LPRCNT_CompInit(LPRCNT_COMP_InitType* COMP_InitStruct); +void CompDigitalFilterCfg(bool cmd, uint32_t filterTh); +void CompAnalogFilterEn(bool cmd); +void LPRCNTAnalogFilterConfig(void); +//Interruprt mask +void LPRCNT_ClrIntBit(uint32_t intflag); + +INTStatus LPRCNT_GetIntSts(uint32_t Int); +void LPRCNT_IntEn(uint32_t Mode ,FunctionalState NewState); +void CompDigitalFilterPhase(bool dir); + +//for prinft some set values +uint16_t GetNormalSensorLowSpeed(void); +uint8_t GetNormalSensorHightSpeed(void); +uint8_t GetNormalSensorSwtichTime(void); +uint8_t GetDacRefVol(uint8_t Ch); +uint8_t GetUndampedTh(uint8_t Ch); +uint8_t GetDampedTh(uint8_t Ch); +uint8_t GetVibrationTime(uint8_t Ch); +uint8_t GetDischargeTime(uint8_t Ch); +uint8_t GetChargeTime(uint8_t Ch); +#endif /* __LPRCNT_H__ */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lptim.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lptim.h new file mode 100644 index 0000000000000000000000000000000000000000..b6ea77c7e0806c2ba75d9d7a8ff78cfdb68335c2 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lptim.h @@ -0,0 +1,427 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------------- + */ +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32l43x_lptim.h + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ +#ifndef __N32L43X_LPTIM_H +#define __N32L43X_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPTIM + * @{ + */ + +//#if defined (LPTIM) + + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_EC_PRESCALER. + + This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ + + uint32_t Polarity; /*!< Specifies waveform polarity. + This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY. + + This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/ +} LPTIM_InitType; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LPTIM_ReadReg function + * @{ + */ +#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */ +#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */ +#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */ +#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_IT IT Defines + * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions + * @{ + */ +#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */ +/** + * @} + */ + +/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +void LPTIM_DeInit(LPTIM_Module *LPTIMx); +void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct); +ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct); +void LPTIM_Disable(LPTIM_Module *LPTIMx); + + + +void LPTIM_Enable(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx); +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode); +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode); +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx); +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload); +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx); +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue); +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx); +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode); +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx); +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity); +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform); +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx); +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity); +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler); +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx); +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx); +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx); +void LPTIM_TrigSw(LPTIM_Module *LPTIMx); +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity); +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx); +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource); +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx); +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity); +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx); +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx); +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode); +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx); +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx); +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx); +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx); +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx); +/** + * @} + */ + +/** + * @} + */ + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_LPTIM_H */ + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h new file mode 100644 index 0000000000000000000000000000000000000000..7d780274436cffbb9683376202ca1110867c05dc --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h @@ -0,0 +1,280 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_lpuart.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_LPUART_H__ +#define __N32L43X_LPUART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @{ + */ + +/** @addtogroup LPUART_Exported_Types + * @{ + */ + +/** + * @brief LPUART Init Structure definition + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate))) + - FractionalDivider */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (only support + 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t RtsThreshold; /* Specifies RTS Threshold. + This parameter can be a value of @ref RtsThreshold */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref LPUART_Hardware_Flow_Control */ +} LPUART_InitType; + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Constants + * @{ + */ + +/** @addtogroup Parity + * @{ + */ + +#define LPUART_PE_NO ((uint16_t)0x0008) +#define LPUART_PE_EVEN ((uint16_t)0x0000) +#define LPUART_PE_ODD ((uint16_t)0x0001) +#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define LPUART_MODE_RX ((uint16_t)0x0000) +#define LPUART_MODE_TX ((uint16_t)0x0002) +#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX)) +/** + * @} + */ + +/** @addtogroup RtsThreshold + * @{ + */ + +#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000) +#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100) +#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200) +#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \ + (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU)) +/** + * @} + */ + +/** @addtogroup Hardware_Flow_Control + * @{ + */ +#define LPUART_HFCTRL_NONE ((uint16_t)0x0000) +#define LPUART_HFCTRL_CTS ((uint16_t)0x0400) +#define LPUART_HFCTRL_RTS ((uint16_t)0x0800) +#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00) +#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \ + || ((CONTROL) == LPUART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup LPUART_Interrupt_definition + * @{ + */ + +#define LPUART_INT_PE ((uint16_t)0x0001) +#define LPUART_INT_TXC ((uint16_t)0x0102) +#define LPUART_INT_FIFO_OV ((uint16_t)0x0204) +#define LPUART_INT_FIFO_FU ((uint16_t)0x0308) +#define LPUART_INT_FIFO_HF ((uint16_t)0x0410) +#define LPUART_INT_FIFO_NE ((uint16_t)0x0520) +#define LPUART_INT_WUF ((uint16_t)0x0640) +#define IS_LPUART_CFG_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_GET_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +#define IS_LPUART_CLR_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \ + || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF)) +/** + * @} + */ + +/** @addtogroup LPUART_DMA_Requests + * @{ + */ + +#define LPUART_DMAREQ_TX ((uint16_t)0x0020) +#define LPUART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup LPUART_WakeUp_methods + * @{ + */ + +#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000) +#define LPUART_WUSTP_RXNE ((uint16_t)0x1000) +#define LPUART_WUSTP_BYTE ((uint16_t)0x2000) +#define LPUART_WUSTP_FRAME ((uint16_t)0x3000) +#define IS_LPUART_WAKEUP(WAKEUP) \ + (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME)) +/** + * @} + */ + +/** @addtogroup LPUART_Sampling_methods + * @{ + */ + +#define LPUART_SMPCNT_3B ((uint16_t)0x0000) +#define LPUART_SMPCNT_1B ((uint16_t)0x4000) +#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B)) +/** + * @} + */ + +/** @addtogroup LPUART_Flags + * @{ + */ + +#define LPUART_FLAG_PEF ((uint16_t)0x0001) +#define LPUART_FLAG_TXC ((uint16_t)0x0002) +#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004) +#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008) +#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010) +#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020) +#define LPUART_FLAG_CTS ((uint16_t)0x0040) +#define LPUART_FLAG_WUF ((uint16_t)0x0080) +#define LPUART_FLAG_NF ((uint16_t)0x0100) +#define IS_LPUART_FLAG(FLAG) \ + (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \ + || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \ + || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF)) + +#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000)) + +#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Functions + * @{ + */ + +void LPUART_DeInit(void); +void LPUART_Init(LPUART_InitType* LPUART_InitStruct); +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct); +void LPUART_FlushRxFifo(void); +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd); +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd); +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod); +void LPUART_EnableWakeUpStop(FunctionalState Cmd); +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod); +void LPUART_EnableLoopBack(FunctionalState Cmd); +void LPUART_SendData(uint8_t Data); +uint8_t LPUART_ReceiveData(void); +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData); +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG); +void LPUART_ClrFlag(uint16_t LPUART_FLAG); +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT); +void LPUART_ClrIntPendingBit(uint16_t LPART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_LPUART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_opamp.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_opamp.h new file mode 100644 index 0000000000000000000000000000000000000000..cb56fb1f303529aa70c5546b2ef5db1ea6776387 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_opamp.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_opamp.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_OPAMPMP_H__ +#define __N32L43X_OPAMPMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" +#include + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @{ + */ + +/** @addtogroup OPAMP_Exported_Constants + * @{ + */ +typedef enum +{ + OPAMP1 = 0, + OPAMP2 = 4, +} OPAMPX; + +// OPAMP_CS +typedef enum +{ + OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24), + OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24), +}OPAMP2_CS_TIMSRCSEL; +typedef enum +{ + OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19), + OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19), + OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19), + OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19), + OPAMP1_CS_VPSSEL_NC = (0x04L << 19), + + OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19), + OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19), + OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19), + OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19), + OPAMP2_CS_VPSSEL_NC = (0x04L << 19), +} OPAMP_CS_VPSSEL; +typedef enum +{ + OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17), + OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17), + OPAMP1_CS_VMSSEL_NC = (0x02L << 17), + OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17), + + OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17), + OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17), + OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17), + OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17), +} OPAMP_CS_VMSSEL; + +typedef enum +{ + OPAMP1_CS_VPSEL_PA1 = (0x00L << 8), + OPAMP1_CS_VPSEL_PA5 = (0x01L << 8), + OPAMP1_CS_VPSEL_PA4 = (0x02L << 8), + OPAMP1_CS_VPSEL_PA7 = (0x03L << 8), + OPAMP1_CS_VPSEL_NC = (0x04L << 8), + + OPAMP2_CS_VPSEL_PA7 = (0x00L << 8), + OPAMP2_CS_VPSEL_PA4 = (0x01L << 8), + OPAMP2_CS_VPSEL_PB14 = (0x02L << 8), + OPAMP2_CS_VPSEL_PD13 = (0x03L << 8), + OPAMP2_CS_VPSEL_NC = (0x04L << 8), +} OPAMP_CS_VPSEL; +typedef enum +{ + OPAMP1_CS_VMSEL_PA3 = (0x00L << 6), + OPAMP1_CS_VMSEL_PC5 = (0x01L << 6), + OPAMPx_CS_VMSEL_NC = (0x02L << 6), + OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6), + + OPAMP2_CS_VMSEL_PC5 = (0x00L << 6), + OPAMP2_CS_VMSEL_PB0 = (0x01L << 6), + OPAMP2_CS_VMSEL_PA5 = (0x02L << 6), + OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6), +} OPAMP_CS_VMSEL; +typedef enum +{ + OPAMP_CS_PGA_GAIN_2 = (0x00 << 3), + OPAMP_CS_PGA_GAIN_4 = (0x01 << 3), + OPAMP_CS_PGA_GAIN_8 = (0x02 << 3), + OPAMP_CS_PGA_GAIN_16 = (0x03 << 3), + OPAMP_CS_PGA_GAIN_32 = (0x04 << 3), +} OPAMP_CS_PGA_GAIN; +typedef enum +{ + OPAMP_CS_EXT_OPAMP = (0x00 << 1), + OPAMP_CS_PGA_EN = (0x02 << 1), + OPAMP_CS_FOLLOW = (0x03 << 1), +} OPAMP_CS_MOD; + +// bit mask +#define OPAMP_CS_EN_MASK (0x01L << 0) +#define OPAMP_CS_MOD_MASK (0x03L << 1) +#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3) +#define OPAMP_CS_VMSEL_MASK (0x03L << 6) +#define OPAMP_CS_VPSEL_MASK (0x07L << 8) +#define OPAMP_CS_CALON_MASK (0x01L << 11) +#define OPAMP_CS_TSTREF_MASK (0x01L << 13) +#define OPAMP_CS_CALOUT_MASK (0x01L << 14) +#define OPAMP_CS_RANGE_MASK (0x01L << 15) +#define OPAMP_CS_TCMEN_MASK (0x01L << 16) +#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17) +#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19) +#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24) +/** @addtogroup OPAMP_LOCK + * @{ + */ +#define OPAMP_LOCK_1 0x01L +#define OPAMP_LOCK_2 0x02L +/** + * @} + */ +/** + * @} + */ + +/** + * @brief OPAMP Init structure definition + */ + +typedef struct +{ + OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/ + + FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */ + + FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/ + + OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */ + + OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/ +} OPAMP_InitType; + +/** @addtogroup OPAMP_Exported_Functions + * @{ + */ + +void OPAMP_DeInit(void); +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain); +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel); +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel); +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel); +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel); +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx); +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_ADC_H */ + /** + * @} + */ + /** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_pwr.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_pwr.h new file mode 100644 index 0000000000000000000000000000000000000000..750b76877a282523a01954217d4109197703d992 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_pwr.h @@ -0,0 +1,224 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_pwr.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_PWR_H__ +#define __N32L43X_PWR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @addtogroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Constants + * @{ + */ + +/** @addtogroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000) +#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002) +#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004) +#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006) +#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008) +#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A) +#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C) +#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E) + + +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \ + || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \ + || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) ) + +/** + * @} + */ + +/** @addtogroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_REGULATOR_ON ((uint32_t)0x00000000) +#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER)) +/** + * @} + */ + +/** @defgroup SLEEP_mode_entry + * @{ + */ +#define SLEEP_ON_EXIT (1) +#define SLEEP_OFF_EXIT (0) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + + +/** + * @} + */ + + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + +/** @addtogroup PWR_Flag + * @{ + */ +//STS1 +#define PWR_WKUP0_FLAG ((uint32_t)0x00000001) +#define PWR_WKUP1_FLAG ((uint32_t)0x00000002) +#define PWR_WKUP2_FLAG ((uint32_t)0x00000004) +#define PWR_STBY_FLAG ((uint32_t)0x00000100) +//STS2 +#define PWR_LPRUN_FLAG ((uint32_t)0x00000001) +#define PWR_MR_FLAG ((uint32_t)0x00000002) +#define PWR_PVDO_FLAG ((uint32_t)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + +#define IS_PWR_CLEAR_FLAG(FLAG) \ + (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ + || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) + + + +/** @addtogroup SRAM1oSRAM2 retention set + * @{ + */ +//#define SRAM1DIS_SRAM2DIS 0 +//#define SRAM1EN_SRAM2DIS 1 + +//#define SRAM1DIS_SRAM2EN 2 +//#define SRAM1EN_SRAM2EN 3 +/** @addtogroup MR VOLTAGE + * @{ + */ +#define MR_1V0 2 +#define MR_1V1 3 + + +/** + * @} + */ +typedef enum +{ + WAKEUP_PIN0 = 0x0001, + WAKEUP_PIN1 = 0x0002, + WAKEUP_PIN2 = 0x0004, +} WAKEUP_PINX; +/** @addtogroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ +#define LPRUN_SWITCH_ADDR (__IO unsigned*)(0x40007000) +#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20) +#define CLERR_BIT25 0xfdffffff //bit25 +#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while(0) //0:0.9V 1:1.1V +#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while(0) //0:always on 1:duty on +#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while(0) //0:normal mode 1:standby mode +#define _SetLprunSwitch(vale) do{(*LPRUN_SWITCH_ADDR) &= (~0x0600);(*LPRUN_SWITCH_ADDR) |= (uint32_t)(vale <<9);}while(0) +/** @addtogroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessEnable(FunctionalState Cmd); +void PWR_PvdEnable(FunctionalState Cmd); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd); +void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry); +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret); +void PWR_EnterLowPowerRunMode(void); +void PWR_ExitLowPowerRunMode(void); +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry); + +FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_WakeUpPinConfig(void); +void SetSysClock_MSI(void); +uint8_t GetMrVoltage(void); +void PWR_MRconfig(uint8_t voltage); +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_PWR_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rcc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rcc.h new file mode 100644 index 0000000000000000000000000000000000000000..1694d6db63d809e379cb950fc73140c425cc5e7e --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rcc.h @@ -0,0 +1,913 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_rcc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_RCC_H__ +#define __N32L43X_RCC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */ + uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */ +} RCC_ClocksType; + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ + +/** @addtogroup HSE_configuration + * @{ + */ + +#define RCC_HSE_DISABLE ((uint32_t)0x00000000) +#define RCC_HSE_ENABLE ((uint32_t)0x00010000) +#define RCC_HSE_BYPASS ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS)) + +/** + * @} + */ + +/** @addtogroup HSI_configuration + * @{ + */ + +#define RCC_HSI_DISABLE ((uint32_t)0x00000000) +#define RCC_HSI_ENABLE ((uint32_t)0x00000001) +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE)) + +/** + * @} + */ + +/** @addtogroup MSI_configuration + * @{ + */ + +#define RCC_MSI_DISABLE ((uint32_t)0x00000000) +#define RCC_MSI_ENABLE ((uint32_t)0x00000004) +#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE)) + +#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000) +#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010) +#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020) +#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030) +#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040) +#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050) +#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060) +#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \ + || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \ + ) + +/** + * @} + */ + +/** @addtogroup PLL_entry_clock_source + * @{ + */ +#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000) +#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001) + +#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000) +#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000) +#define IS_RCC_PLL_SRC(SOURCE) \ + (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \ + || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2)) + +#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000) +#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002) +#define IS_RCC_PLL_DIVCLK(DIVCLK) \ + (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE)) + +/** + * @} + */ + +/** @addtogroup PLL_multiplication_factor + * @{ + */ +#define RCC_PLL_MUL_2 ((uint32_t)0x00000000) +#define RCC_PLL_MUL_3 ((uint32_t)0x00040000) +#define RCC_PLL_MUL_4 ((uint32_t)0x00080000) +#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000) +#define RCC_PLL_MUL_6 ((uint32_t)0x00100000) +#define RCC_PLL_MUL_7 ((uint32_t)0x00140000) +#define RCC_PLL_MUL_8 ((uint32_t)0x00180000) +#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000) +#define RCC_PLL_MUL_10 ((uint32_t)0x00200000) +#define RCC_PLL_MUL_11 ((uint32_t)0x00240000) +#define RCC_PLL_MUL_12 ((uint32_t)0x00280000) +#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000) +#define RCC_PLL_MUL_14 ((uint32_t)0x00300000) +#define RCC_PLL_MUL_15 ((uint32_t)0x00340000) +#define RCC_PLL_MUL_16 ((uint32_t)0x00380000) +#define RCC_PLL_MUL_17 ((uint32_t)0x08000000) +#define RCC_PLL_MUL_18 ((uint32_t)0x08040000) +#define RCC_PLL_MUL_19 ((uint32_t)0x08080000) +#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000) +#define RCC_PLL_MUL_21 ((uint32_t)0x08100000) +#define RCC_PLL_MUL_22 ((uint32_t)0x08140000) +#define RCC_PLL_MUL_23 ((uint32_t)0x08180000) +#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000) +#define RCC_PLL_MUL_25 ((uint32_t)0x08200000) +#define RCC_PLL_MUL_26 ((uint32_t)0x08240000) +#define RCC_PLL_MUL_27 ((uint32_t)0x08280000) +#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000) +#define RCC_PLL_MUL_29 ((uint32_t)0x08300000) +#define RCC_PLL_MUL_30 ((uint32_t)0x08340000) +#define RCC_PLL_MUL_31 ((uint32_t)0x08380000) +#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000) +#define IS_RCC_PLL_MUL(MUL) \ + (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \ + || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \ + || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \ + || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \ + || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \ + || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \ + || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \ + || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \ + || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \ + || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32)) + +/** + * @} + */ + +/** @addtogroup System_clock_source + * @{ + */ + +#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000) +#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001) +#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002) +#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003) +#define IS_RCC_SYSCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \ + || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK)) +/** + * @} + */ + +/** @addtogroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0) +#define IS_RCC_SYSCLK_DIV(HCLK) \ + (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \ + || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \ + || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @addtogroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_HCLK_DIV2 ((uint32_t)0x00000400) +#define RCC_HCLK_DIV4 ((uint32_t)0x00000500) +#define RCC_HCLK_DIV8 ((uint32_t)0x00000600) +#define RCC_HCLK_DIV16 ((uint32_t)0x00000700) +#define IS_RCC_HCLK_DIV(PCLK) \ + (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \ + || ((PCLK) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @addtogroup RCC_Interrupt_source + * @{ + */ + +#define RCC_INT_LSIRDIF ((uint8_t)0x01) +#define RCC_INT_LSERDIF ((uint8_t)0x02) +#define RCC_INT_HSIRDIF ((uint8_t)0x04) +#define RCC_INT_HSERDIF ((uint8_t)0x08) +#define RCC_INT_PLLRDIF ((uint8_t)0x10) +#define RCC_INT_BORIF ((uint8_t)0x20) +#define RCC_INT_MSIRDIF ((uint8_t)0x40) +#define RCC_INT_CLKSSIF ((uint8_t)0x80) + +#define IS_RCC_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF)) + +#define IS_RCC_GET_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF)) + +#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000) +#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000) +#define RCC_CLR_LSERDIF ((uint32_t)0x00020000) +#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000) +#define RCC_CLR_HSERDIF ((uint32_t)0x00080000) +#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000) +#define RCC_CLR_BORIF ((uint32_t)0x00200000) +#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000) + +#define IS_RCC_CLR_INTF(IT) \ + (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \ + || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF)) + +/** + * @} + */ + +/** @addtogroup USB_Device_clock_source + * @{ + */ + +#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00) +#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01) +#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02) +#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03) + +#define IS_RCC_USBCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \ + || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3)) +/** + * @} + */ + +/** @addtogroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000) +#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000) +#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000) +#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000) +#define IS_RCC_PCLK2_DIV(ADCCLK) \ + (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \ + || ((ADCCLK) == RCC_PCLK2_DIV8)) + +/** + * @} + */ + +/** @addtogroup RCC_CFGR2_Config + * @{ + */ +#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000) +#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000) +#define IS_RCC_TIM18CLKSRC(TIM18CLK) \ + (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK)) + +#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000) +#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000) +#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000) +#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000) +#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000) +#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000) +#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000) +#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000) +#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000) +#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000) +#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000) +#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000) +#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000) +#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000) +#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000) +#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000) +#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000) +#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000) +#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000) +#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000) +#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000) +#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000) +#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000) +#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000) +#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000) +#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000) +#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000) +#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000) +#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000) +#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000) +#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000) +#define IS_RCC_RNGCCLKPRE(DIV) \ + (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32)) + +#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE)) + +#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000) +#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000) +#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000) +#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000) +#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000) +#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000) +#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000) +#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000) +#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000) +#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000) +#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000) +#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000) +#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000) +#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000) +#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000) +#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000) +#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000) +#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000) +#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000) +#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000) +#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000) +#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000) +#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000) +#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000) +#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000) +#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000) +#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000) +#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000) +#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000) +#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000) +#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000) +#define IS_RCC_ADC1MCLKPRE(DIV) \ + (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \ + || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \ + || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \ + || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \ + || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \ + || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \ + || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \ + || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \ + || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \ + || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \ + || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32)) + +#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) +#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) +#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) +#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) +#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) +#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) +#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) +#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) +#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) +#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) +#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) +#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) +#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) +#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) +#define IS_RCC_ADCPLLCLKPRE(DIV) \ + (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \ + || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \ + || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \ + || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \ + || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0)) + +#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) +#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) +#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) +#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) +#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) +#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) +#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) +#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) +#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) +#define IS_RCC_ADCHCLKPRE(DIV) \ + (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \ + || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \ + || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \ + || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00)) +/** + * @} + */ + +/** @addtogroup RCC_CFGR3_Config + * @{ + */ + +#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000) +#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF) + +#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \ + (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE)) + +#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000) +#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800) +#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000) +#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800) +#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000) +#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800) +#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000) +#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800) +#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000) +#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800) +#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000) +#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800) +#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000) +#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800) +#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000) +#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800) +#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000) +#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800) +#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000) +#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800) +#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000) +#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800) +#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000) +#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800) +#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000) +#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800) +#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000) +#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800) +#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000) +#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800) +#define IS_RCC_TRNG1MCLKPRE(VAL) \ + (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \ + || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \ + || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \ + || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \ + || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \ + || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \ + || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \ + || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \ + || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \ + || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \ + || ((VAL) == RCC_TRNG1MCLK_DIV62)) + +#define RCC_UCDR_ENABLE ((uint32_t)0x00000080) +#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F) + +#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF) +#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000) +#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200) +#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \ + (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO)) + +#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF) +#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000) +#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100) +#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \ + (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE)) + +/** + * @} + */ + +/** @addtogroup LSE_configuration + * @{ + */ + +#define RCC_LSE_DISABLE ((uint32_t)0x00000000) +#define RCC_LSE_ENABLE ((uint32_t)0x00000001) +#define RCC_LSE_BYPASS ((uint32_t)0x00000004) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @addtogroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000) +#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \ + || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32)) +/** + * @} + */ + +/** @addtogroup LSX_clock_source + * @{ + */ + +#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000) +#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020) +#define IS_RCC_LSXCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE)) +/** + * @} + */ + +/** @addtogroup AHB_peripheral + * @{ + */ + +#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001) +#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004) +#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010) +#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040) +#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200) +#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800) +#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup APB2_peripheral + * @{ + */ + +#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001) +#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000) +#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000) +#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000) +#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup APB1_peripheral + * @{ + */ + +#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040) +#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080) +#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100) +#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200) +#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400) +#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800) +#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000) +#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000) +#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000) +#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000) +#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000) +#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000) +#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup RET_peripheral + * @{ + */ + +#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040) +#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080) +#define RCC_RET_PERIPH_LCD ((uint32_t)0x00000100) +#define RCC_RET_PERIPH_LPRCNT ((uint32_t)0x00000200) + +#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFC3F) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup LPTIM + * @{ + */ +#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8) + +#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001) +#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002) +#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003) +#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004) +#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005) + +#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \ + || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2)) + +/** + * @} + */ + +/** @addtogroup LPUART + * @{ + */ +#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7) + +#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000) +#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008) +#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010) +#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018) + +#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00) + +/** + * @} + */ + +/** @addtogroup SRAM_CTRLSTS + * @{ + */ + +#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001) +#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008) +#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \ + || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT)) + +#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002) +#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010) +#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \ + || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET)) + +#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004) +#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020) +#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \ + || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG)) + +/** + * @} + */ + +#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000) +#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000) +#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000) +#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000) +#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000) +#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000) +#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000) +#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000) +#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000) +#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000) +#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000) +#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000) +#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000) +#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000) +#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000) +#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000) +#define IS_RCC_MCOCLKPRE(NUM) \ + (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \ + || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \ + || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \ + || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \ + || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \ + || ((NUM) == RCC_MCO_CLK_NUM15)) + +/** @addtogroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NOCLK ((uint8_t)0x00) +#define RCC_MCO_LSI ((uint8_t)0x01) +#define RCC_MCO_LSE ((uint8_t)0x02) +#define RCC_MCO_MSI ((uint8_t)0x03) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +#define IS_RCC_MCO(MCO) \ + (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \ + || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK)) + +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21) +#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31) +#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39) +#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41) +#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44) +#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C) +#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E) +#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61) +#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63) +#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77) +#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79) +#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A) +#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B) +#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C) +#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D) +#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E) +#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) \ + (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \ + || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \ + || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF)) + +#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_ConfigHse(uint32_t RCC_HSE); +ErrorStatus RCC_WaitHseStable(void); +void RCC_ConfigHsi(uint32_t RCC_HSI); +ErrorStatus RCC_WaitHsiStable(void); +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue); +void RCC_EnableHsi(FunctionalState Cmd); +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range); +ErrorStatus RCC_WaitMsiStable(void); +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue); +void RCC_EnableMsi(FunctionalState Cmd); +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK); +void RCC_EnablePll(FunctionalState Cmd); + +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSysclkSrc(void); +void RCC_ConfigHclk(uint32_t RCC_SYSCLK); +void RCC_ConfigPclk1(uint32_t RCC_HCLK); +void RCC_ConfigPclk2(uint32_t RCC_HCLK); +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd); + +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource); + +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource); +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler); + +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler); +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd); +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler); + +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler); +void RCC_EnableTrng1mClk(FunctionalState Cmd); + +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd); + +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode); + +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd); +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd); + +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource); +uint32_t RCC_GetLSXClkSrc(void); + +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource); +uint32_t RCC_GetLPTIMClkSrc(void); +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource); +uint32_t RCC_GetLPUARTClkSrc(void); + +void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd); +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd); +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag); + +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim); +void RCC_EnableLsi(FunctionalState Cmd); +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource); +void RCC_EnableRtcClk(FunctionalState Cmd); +uint32_t RCC_GetRTCClkSrc(void); +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks); +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd); + +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd); +void RCC_EnableLowPowerReset(FunctionalState Cmd); +void RCC_EnableClockSecuritySystem(FunctionalState Cmd); +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd); +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void); +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler); +void RCC_ConfigMco(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClrFlag(void); +INTStatus RCC_GetIntStatus(uint8_t RccInt); +void RCC_ClrIntPendingBit(uint32_t RccClrInt); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_RCC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rtc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..f6449865f7cfdc90e51141d49778b091c392d0bc --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_rtc.h @@ -0,0 +1,789 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_rtc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_RTC_H__ +#define __N32L43X_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x7FFF */ +} RTC_InitType; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_12HOUR_FORMAT is selected or 0-23 range if + the RTC_24HOUR_FORMAT is selected. */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +} RTC_TimeType; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +} RTC_DateType; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +} RTC_AlarmType; + +/** @addtogroup RTC_Exported_Constants + * @{ + */ + +/** @addtogroup RTC_Hour_Formats + * @{ + */ +#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000) +#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT)) +/** + * @} + */ + +/** @addtogroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + +/** @addtogroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @addtogroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_AM_H12 ((uint8_t)0x00) +#define RTC_PM_H12 ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12)) + +/** + * @} + */ + +/** @addtogroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @addtogroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRURY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @addtogroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000) +#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \ + (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000) +#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000) +#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000) +#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_A_ALARM ((uint32_t)0x00000100) +#define RTC_B_ALARM ((uint32_t)0x00000200) +#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM)) +#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions + * @{ + */ +#define RTC_SUBS_MASK_ALL \ + ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \ + There is no comparison on sub seconds \ + for Alarm */ +#define RTC_SUBS_MASK_SS14_1 \ + ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \ + comparison. Only SS[0] is compared. */ +#define RTC_SUBS_MASK_SS14_2 \ + ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \ + comparison. Only SS[1:0] are compared */ +#define RTC_SUBS_MASK_SS14_3 \ + ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \ + comparison. Only SS[2:0] are compared */ +#define RTC_SUBS_MASK_SS14_4 \ + ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \ + comparison. Only SS[3:0] are compared */ +#define RTC_SUBS_MASK_SS14_5 \ + ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \ + comparison. Only SS[4:0] are compared */ +#define RTC_SUBS_MASK_SS14_6 \ + ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \ + comparison. Only SS[5:0] are compared */ +#define RTC_SUBS_MASK_SS14_7 \ + ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \ + comparison. Only SS[6:0] are compared */ +#define RTC_SUBS_MASK_SS14_8 \ + ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \ + comparison. Only SS[7:0] are compared */ +#define RTC_SUBS_MASK_SS14_9 \ + ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \ + comparison. Only SS[8:0] are compared */ +#define RTC_SUBS_MASK_SS14_10 \ + ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \ + comparison. Only SS[9:0] are compared */ +#define RTC_SUBS_MASK_SS14_11 \ + ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \ + comparison. Only SS[10:0] are compared */ +#define RTC_SUBS_MASK_SS14_12 \ + ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \ + comparison.Only SS[11:0] are compared */ +#define RTC_SUBS_MASK_SS14_13 \ + ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \ + comparison. Only SS[12:0] are compared */ +#define RTC_SUBS_MASK_SS14_14 \ + ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \ + comparison.Only SS[13:0] are compared */ +#define RTC_SUBS_MASK_NONE \ + ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \ + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \ + (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \ + || ((INTEN) == RTC_SUBS_MASK_NONE)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004) +#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define IS_RTC_WKUP_CLOCK(CLOCK) \ + (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \ + || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \ + || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS)) +#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @addtogroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \ + (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING)) +/** + * @} + */ + +/** @addtogroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_OUTPUT_DIS ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALA ((uint32_t)0x00200000) +#define RTC_OUTPUT_ALB ((uint32_t)0x00400000) +#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT_MODE(OUTPUT) \ + (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \ + || ((OUTPUT) == RTC_OUTPUT_WKUP)) + +/** + * @} + */ + +/** @addtogroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPOL_LOW ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW)) +/** + * @} + */ + + +/** @addtogroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000) +#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ)) +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define SMOOTH_CALIB_32SEC \ + ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 32s, else 2exp20 RTCCLK seconds */ +#define SMOOTH_CALIB_16SEC \ + ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 16s, else 2exp19 RTCCLK seconds */ +#define SMOOTH_CALIB_8SEC \ + ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \ + (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \ + ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \ + during a X -second window = Y - CALM[8:0]. \ + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \ + ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \ + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \ + (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @addtogroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H)) + +#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) \ + (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET)) +/** + * @} + */ + +/** @addtogroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL)) + +/** + * @} + */ + +/** @addtogroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000) +#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE)) +/** + * @} + */ + +/** @addtogroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + +/** + * @} + */ + +/** @addtogroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TISOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TISF ((uint32_t)0x00000800) +#define RTC_FLAG_WTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSYF ((uint32_t)0x00000020) +#define RTC_FLAG_INITSF ((uint32_t)0x00000010) +#define RTC_FLAG_SHOPF ((uint32_t)0x00000008) +#define RTC_FLAG_WTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \ + ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \ + ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \ + ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \ + ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \ + ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \ + ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_INT_TAMP3 ((uint32_t)0x00080000) +#define RTC_INT_TAMP2 ((uint32_t)0x00040000) +#define RTC_INT_TAMP1 ((uint32_t)0x00020000) +#define RTC_INT_TS ((uint32_t)0x00008000) +#define RTC_INT_WUT ((uint32_t)0x00004000) +#define RTC_INT_ALRB ((uint32_t)0x00002000) +#define RTC_INT_ALRA ((uint32_t)0x00001000) + +#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_INT(IT) \ + (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA)) +#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ + +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for + input tamper 1 */ +#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for + input tamper 2 */ +#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for + input tamper 3 */ +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + + +#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */ +#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_EnableWriteProtection(FunctionalState Cmd); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd); +void RTC_EnableBypassShadow(FunctionalState Cmd); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd); +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd); + +/* Daylight Saving configuration functions ************************************/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse and Smooth Calibration configuration functions **********************/ +void RTC_EnableCalibOutput(FunctionalState Cmd); +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput); +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Output Type Config configuration functions *********************************/ +void RTC_ConfigOutputType(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClrFlag(uint32_t RTC_FLAG); +INTStatus RTC_GetITStatus(uint32_t RTC_INT); +void RTC_ClrIntPendingBit(uint32_t RTC_INT); + +/* WakeUp TSC function **********************************/ +void RTC_EnableWakeUpTsc(uint32_t count); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState); +void RTC_TamperTAMPTSCmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_RTC_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_spi.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..a1bbb013e9eb39a24ed7e97fe0a6622a4b8f5fe3 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_spi.h @@ -0,0 +1,470 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_spi.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_SPI_H__ +#define __N32L43X_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @addtogroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SpiMode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t DataLen; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t CLKPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitType; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2sMode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2sMode */ + + uint16_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref Standard */ + + uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitType; + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2)) + + +/** @addtogroup SPI_data_direction + * @{ + */ + +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400) +#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000) +#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000) +#define IS_SPI_DIR_MODE(MODE) \ + (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ + || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX)) +/** + * @} + */ + +/** @addtogroup SPI_mode + * @{ + */ + +#define SPI_MODE_MASTER ((uint16_t)0x0104) +#define SPI_MODE_SLAVE ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) +/** + * @} + */ + +/** @addtogroup SPI_data_size + * @{ + */ + +#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CLKPOL_LOW ((uint16_t)0x0000) +#define SPI_CLKPOL_HIGH ((uint16_t)0x0002) +#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) +#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001) +#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) +/** + * @} + */ + +/** @addtogroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_SOFT ((uint16_t)0x0200) +#define SPI_NSS_HARD ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) +/** + * @} + */ + +/** @addtogroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) +#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008) +#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010) +#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018) +#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020) +#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028) +#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030) +#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038) +#define IS_SPI_BR_PRESCALER(PRESCALER) \ + (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \ + || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \ + || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \ + || ((PRESCALER) == SPI_BR_PRESCALER_256)) +/** + * @} + */ + +/** @addtogroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FB_MSB ((uint16_t)0x0000) +#define SPI_FB_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) +/** + * @} + */ + +/** @addtogroup I2sMode + * @{ + */ + +#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000) +#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100) +#define I2S_MODE_MASTER_TX ((uint16_t)0x0200) +#define I2S_MODE_MASTER_RX ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) \ + (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \ + || ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @addtogroup Standard + * @{ + */ + +#define I2S_STD_PHILLIPS ((uint16_t)0x0000) +#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010) +#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020) +#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030) +#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) \ + (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \ + || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME)) +/** + * @} + */ + +/** @addtogroup I2S_Data_Format + * @{ + */ + +#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000) +#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001) +#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003) +#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005) +#define IS_I2S_DATA_FMT(FORMAT) \ + (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \ + || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS)) +/** + * @} + */ + +/** @addtogroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLK_ENABLE ((uint16_t)0x0200) +#define I2S_MCLK_DISABLE ((uint16_t)0x0000) +#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE)) +/** + * @} + */ + +/** @addtogroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AUDIO_FREQ_192K ((uint32_t)192000) +#define I2S_AUDIO_FREQ_96K ((uint32_t)96000) +#define I2S_AUDIO_FREQ_48K ((uint32_t)48000) +#define I2S_AUDIO_FREQ_44K ((uint32_t)44100) +#define I2S_AUDIO_FREQ_32K ((uint32_t)32000) +#define I2S_AUDIO_FREQ_22K ((uint32_t)22050) +#define I2S_AUDIO_FREQ_16K ((uint32_t)16000) +#define I2S_AUDIO_FREQ_11K ((uint32_t)11025) +#define I2S_AUDIO_FREQ_8K ((uint32_t)8000) +#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) \ + ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT)) +/** + * @} + */ + +/** @addtogroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CLKPOL_LOW ((uint16_t)0x0000) +#define I2S_CLKPOL_HIGH ((uint16_t)0x0008) +#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMA_TX ((uint16_t)0x0002) +#define SPI_I2S_DMA_RX ((uint16_t)0x0001) +#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @addtogroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSS_HIGH ((uint16_t)0x0100) +#define SPI_NSS_LOW ((uint16_t)0xFEFF) +#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_TX ((uint8_t)0x00) +#define SPI_CRC_RX ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) +/** + * @} + */ + +/** @addtogroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF) +#define SPI_BIDIRECTION_TX ((uint16_t)0x4000) +#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_INT_TE ((uint8_t)0x71) +#define SPI_I2S_INT_RNE ((uint8_t)0x60) +#define SPI_I2S_INT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR)) +#define SPI_I2S_INT_OVER ((uint8_t)0x56) +#define SPI_INT_MODERR ((uint8_t)0x55) +#define SPI_INT_CRCERR ((uint8_t)0x54) +#define I2S_INT_UNDER ((uint8_t)0x53) +#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR)) +#define IS_SPI_I2S_GET_INT(IT) \ + (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \ + || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001) +#define SPI_I2S_TE_FLAG ((uint16_t)0x0002) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0004) +#define I2S_UNDER_FLAG ((uint16_t)0x0008) +#define SPI_CRCERR_FLAG ((uint16_t)0x0010) +#define SPI_MODERR_FLAG ((uint16_t)0x0020) +#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040) +#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080) +#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) +#define IS_SPI_I2S_GET_FLAG(FLAG) \ + (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \ + || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \ + || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_Module* SPIx); +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct); +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct); +void SPI_InitStruct(SPI_InitType* SPI_InitStruct); +void I2S_InitStruct(I2S_InitType* I2S_InitStruct); +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx); +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); +void SPI_TransmitCrcNext(SPI_Module* SPIx); +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx); +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_SPI_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tim.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tim.h new file mode 100644 index 0000000000000000000000000000000000000000..60b6024dad32f9e2ba2fe43eb140701de8db6019 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tim.h @@ -0,0 +1,1101 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_tim.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_TIM_H__ +#define __N32L43X_TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" +#include "stdbool.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @addtogroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t CntMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t ClkDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter + reaches zero, an update event is generated and counting restarts + from the REPCNT value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0 + Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0 + Tim2,Tim4 valid*/ +} TIM_TimeBaseInitType; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t OcMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t OcPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t OcNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} OCInitType; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + uint16_t Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref Channel */ + + uint16_t IcPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t IcSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t IcFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitType; + +/** + * @brief BKDT structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t OssiState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/ + bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/ + bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/ +} TIM_BDTRInitType; + +/** @addtogroup TIM_Exported_constants + * @{ + */ + +#define IsTimAllModule(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST1: TIM 1 and 8 */ +#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8 */ +#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IsTimList3Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList4Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList5Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList6Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList7Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList8Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM8)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList9Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMODE_TIMING ((uint16_t)0x0000) +#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010) +#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020) +#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030) +#define TIM_OCMODE_PWM1 ((uint16_t)0x0060) +#define TIM_OCMODE_PWM2 ((uint16_t)0x0070) +#define IsTimOcMode(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2)) +#define IsTimOc(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \ + || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMODE_SINGLE ((uint16_t)0x0008) +#define TIM_OPMODE_REPET ((uint16_t)0x0000) +#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET)) +/** + * @} + */ + +/** @addtogroup Channel + * @{ + */ + +#define TIM_CH_1 ((uint16_t)0x0000) +#define TIM_CH_2 ((uint16_t)0x0004) +#define TIM_CH_3 ((uint16_t)0x0008) +#define TIM_CH_4 ((uint16_t)0x000C) +#define IsTimCh(CHANNEL) \ + (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4)) +#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2)) +#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3)) +/** + * @} + */ + +/** @addtogroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CLK_DIV1 ((uint16_t)0x0000) +#define TIM_CLK_DIV2 ((uint16_t)0x0100) +#define TIM_CLK_DIV4 ((uint16_t)0x0200) +#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4)) +/** + * @} + */ + +/** @addtogroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CNT_MODE_UP ((uint16_t)0x0000) +#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010) +#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020) +#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040) +#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060) +#define IsTimCntMode(MODE) \ + (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \ + || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002) +#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008) +#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001) +#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004) +#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001) +#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004) +#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Input_enable_disable + * @{ + */ + +#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000) +#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000) +#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Polarity + * @{ + */ + +#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000) +#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000) +#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH)) +/** + * @} + */ + +/** @addtogroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000) +#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000) +#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE)) +/** + * @} + */ + +/** @addtogroup Lock_level + * @{ + */ + +#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000) +#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100) +#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200) +#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300) +#define IsTimLockLevel(LEVEL) \ + (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \ + || ((LEVEL) == TIM_LOCK_LEVEL_3)) +/** + * @} + */ + +/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400) +#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800) +#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100) +#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200) +#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000) +#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002) +#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A) +#define IsTimIcPalaritySingleEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING)) +#define IsTimIcPolarityAnyEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \ + || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_IC_SELECTION_DIRECTTI \ + ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI \ + ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IsTimIcSelection(SELECTION) \ + (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \ + || ((SELECTION) == TIM_IC_SELECTION_TRC)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \ + */ +#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IsTimIcPrescaler(PRESCALER) \ + (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \ + || ((PRESCALER) == TIM_IC_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_interrupt_sources + * @{ + */ + +#define TIM_INT_UPDATE ((uint16_t)0x0001) +#define TIM_INT_CC1 ((uint16_t)0x0002) +#define TIM_INT_CC2 ((uint16_t)0x0004) +#define TIM_INT_CC3 ((uint16_t)0x0008) +#define TIM_INT_CC4 ((uint16_t)0x0010) +#define TIM_INT_COM ((uint16_t)0x0020) +#define TIM_INT_TRIG ((uint16_t)0x0040) +#define TIM_INT_BREAK ((uint16_t)0x0080) +#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IsTimGetInt(IT) \ + (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \ + || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000) +#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001) +#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002) +#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003) +#define TIM_DMABASE_STS ((uint16_t)0x0004) +#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005) +#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006) +#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007) +#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008) +#define TIM_DMABASE_CNT ((uint16_t)0x0009) +#define TIM_DMABASE_PSC ((uint16_t)0x000A) +#define TIM_DMABASE_AR ((uint16_t)0x000B) +#define TIM_DMABASE_REPCNT ((uint16_t)0x000C) +#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D) +#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E) +#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F) +#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010) +#define TIM_DMABASE_BKDT ((uint16_t)0x0011) +#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012) + + +#define IsTimDmaBase(BASE) \ + (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \ + || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \ + || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \ + || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \ + || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \ + || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \ + || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000) +#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100) +#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200) +#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300) +#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400) +#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500) +#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600) +#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700) +#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800) +#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900) +#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00) +#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00) +#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00) +#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00) +#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00) +#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00) +#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000) +#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100) +#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200) +#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300) +#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400) +#define IsTimDmaLength(LENGTH) \ + (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_UPDATE ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_TRIG ((uint16_t)0x4000) +#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000) +#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000) +#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000) +#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000) +#define IsTimExtPreDiv(PRESCALER) \ + (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \ + || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000) +#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010) +#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020) +#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030) +#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040) +#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050) +#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060) +#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070) +#define IsTimTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \ + || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \ + || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF)) +#define IsTimInterTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3)) +/** + * @} + */ + +/** @addtogroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050) +#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060) +#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040) +#define IsTimExtClkSrc(SOURCE) \ + (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED)) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000) +#define IsTimExtTrigPolarity(POLARITY) \ + (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED)) +/** + * @} + */ + +/** @addtogroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001) +#define IsTimPscReloadMode(RELOAD) \ + (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE)) +/** + * @} + */ + +/** @addtogroup TIM_Forced_Action + * @{ + */ + +#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050) +#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040) +#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001) +#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002) +#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003) +#define IsTimEncodeMode(MODE) \ + (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12)) +/** + * @} + */ + +/** @addtogroup TIM_Event_Source + * @{ + */ + +#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001) +#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002) +#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004) +#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008) +#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010) +#define TIM_EVT_SRC_COM ((uint16_t)0x0020) +#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040) +#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080) +#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_Update_Source + * @{ + */ + +#define TIM_UPDATE_SRC_GLOBAL \ + ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008) +#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000) +#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004) +#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000) +#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080) +#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000) +#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000) +#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010) +#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020) +#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030) +#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040) +#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050) +#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060) +#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070) +#define IsTimTrgoSrc(SOURCE) \ + (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \ + || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \ + || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF)) +/** + * @} + */ + +/** @addtogroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004) +#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005) +#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006) +#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007) +#define IsTimSlaveMode(MODE) \ + (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \ + || ((MODE) == TIM_SLAVE_MODE_EXT1)) +/** + * @} + */ + +/** @addtogroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080) +#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000) +#define IsTimMasterSlaveMode(STATE) \ + (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_UPDATE ((uint32_t)0x0001) +#define TIM_FLAG_CC1 ((uint32_t)0x0002) +#define TIM_FLAG_CC2 ((uint32_t)0x0004) +#define TIM_FLAG_CC3 ((uint32_t)0x0008) +#define TIM_FLAG_CC4 ((uint32_t)0x0010) +#define TIM_FLAG_COM ((uint32_t)0x0020) +#define TIM_FLAG_TRIG ((uint32_t)0x0040) +#define TIM_FLAG_BREAK ((uint32_t)0x0080) +#define TIM_FLAG_CC1OF ((uint32_t)0x0200) +#define TIM_FLAG_CC2OF ((uint32_t)0x0400) +#define TIM_FLAG_CC3OF ((uint32_t)0x0800) +#define TIM_FLAG_CC4OF ((uint32_t)0x1000) +#define TIM_FLAG_CC5 ((uint32_t)0x010000) +#define TIM_FLAG_CC6 ((uint32_t)0x020000) + +#define IsTimGetFlag(FLAG) \ + (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \ + || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \ + || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \ + || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \ + || ((FLAG) == TIM_FLAG_CC6)) + +#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Filter + * @{ + */ + +#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +#define TIM_CC1EN ((uint32_t)1<<0) +#define TIM_CC1NEN ((uint32_t)1<<2) +#define TIM_CC2EN ((uint32_t)1<<4) +#define TIM_CC2NEN ((uint32_t)1<<6) +#define TIM_CC3EN ((uint32_t)1<<8) +#define TIM_CC3NEN ((uint32_t)1<<10) +#define TIM_CC4EN ((uint32_t)1<<12) +#define TIM_CC5EN ((uint32_t)1<<16) +#define TIM_CC6EN ((uint32_t)1<<20) + +#define IsAdvancedTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \ + || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \ + || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) ) +#define IsGeneralTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \ + || ((FLAG) == TIM_CC3EN) \ + || ((FLAG) == TIM_CC4EN) ) + +/** @addtogroup TIM_Legacy + * @{ + */ + +#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER +#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS +#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS +#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS +#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS +#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS +#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS +#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS +#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS +#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS +#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS +#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS +#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS +#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS +#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS +#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS +#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS +#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_Module* TIMx); +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct); +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct); +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd); +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource); +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd); +void TIM_ConfigInternalClk(TIM_Module* TIMx); +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, + uint16_t TIM_TIxExternalCLKSource, + uint16_t IcPolarity, + uint16_t ICFilter); +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode); +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity); +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx); +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN); +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode); +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter); +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload); +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1); +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2); +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3); +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4); +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5); +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6); +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCap1(TIM_Module* TIMx); +uint16_t TIM_GetCap2(TIM_Module* TIMx); +uint16_t TIM_GetCap3(TIM_Module* TIMx); +uint16_t TIM_GetCap4(TIM_Module* TIMx); +uint16_t TIM_GetCap5(TIM_Module* TIMx); +uint16_t TIM_GetCap6(TIM_Module* TIMx); +uint16_t TIM_GetCnt(TIM_Module* TIMx); +uint16_t TIM_GetPrescaler(TIM_Module* TIMx); +uint16_t TIM_GetAutoReload(TIM_Module* TIMx); +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN); +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG); +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32L43X_TIM_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tsc.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tsc.h new file mode 100644 index 0000000000000000000000000000000000000000..93e332bc7406725bf11a701a3def26da57f9ba3a --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_tsc.h @@ -0,0 +1,483 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_tsc.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_TSC_H__ +#define __N32L43X_TSC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/** + * @brief TSC error code + */ + typedef enum { + TSC_ERROR_OK = 0x00U, /*!< No error */ + TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ + TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ + TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */ + + }TSC_ErrorTypeDef; + /** + * @ + */ + +/** + * @brief TSC clock source + */ +#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/ +#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */ +#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */ +/** + * @ + */ + + +/** + * @defgroup Detect_Period + */ +#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ +#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ +#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ +#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ +#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ +#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ +#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ +#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ +#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ +#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ +#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ +#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ +#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ +/** + * @ + */ + +/** + * @defgroup Detect_Filter + */ +#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ +#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ +#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ +#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ +/** + * @ + */ + +/** + * @defgroup HW_Detect_Mode + */ +#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ +#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */ +/** + * @ + */ + +/** + * @defgroup Detect_Type + */ +#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk) +#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos) + +#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ +#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */ +#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */ +#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */ +/** + * @ + */ + +/** + * @defgroup TSC_Interrupt + */ +#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ +#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ +/** + * @ + */ + +/** + * @defgroup TSC_Out + */ +#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ +#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */ +#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ +/** + * @ + */ + +/** + * @defgroup TSC_Flag + */ +#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */ + +#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */ +#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */ +#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ +/** + * @ + */ + +/** + * @defgroup TSC_SW_Detect + */ +#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ +#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */ +/** + * @ + */ + +/** + * @defgroup TSC_PadOption + */ +#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ +#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */ +/** + * @ + */ + +/** + * @defgroup TSC_PadSpeed + */ +#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ +#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ +/** + * @ + */ + +/** + * @defgroup TSC_Constant + */ +#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk) +#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ +#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ +#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ +#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */ +/** + * @ + */ + +/** + * @defgroup TSC_DetectMode + */ +#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ +#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ +/** + * @ + */ + +/* TSC Exported macros -----------------------------------------------------------*/ +/** @defgroup TSC_Exported_Macros + * @{ + */ + +/** @brief Enable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Disable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Config TSC detect period for HW detect mode + * @param __PERIOD__ specifies the TSC detect period during HW detect mode + * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK + * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK + * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK + * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK + * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK + * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK + * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK + * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK + * @retval None + */ +#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__) + +/** @brief Config TSC detect filter for HW detect mode + * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode + * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse + * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse + * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse + * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse + * @retval None + */ +#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__) + +/** @brief Config TSC detect type for HW detect mode,less great or both + * @param __TYPE__ specifies the detect type of a sample during HW detect mode + * @arg TSC_DET_TYPE_NONE: Detect disable + * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time + * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time + * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) + and also be less than (basee+delta) during a sample time + * @retval None + */ +#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ + (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \ + __TYPE__) + +/** @brief Enable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Disable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Config the TSC output + * @param __OUT__ specifies where the TSC output should go + * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin + * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR + * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR + * @retval None + */ +#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ + (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\ + __OUT__) + +/** @brief Config the TSC channel + * @param __CHN__ specifies the pin of channels used for detect + * This parameter:bit[0:23] used,bit[24:31] must be 0 + * bitx: TSC channel x + * @retval None + */ +#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) + +/** @brief Enable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Disable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Config the detect channel number during SW detect mode + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval None + */ +#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__) + +/** @brief Config the pad charge type + * @param __OPT__ specifies which resistor is used for charge + * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used + * @arg TSC_PAD_EXTERNAL_RES: External resistor is used + * @retval None + */ +#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__) + +/** @brief Config TSC speed + * @param __SPEED__ specifies the TSC speed range + * @arg TSC_PAD_SPEED_0: Low speed + * @arg TSC_PAD_SPEED_1: Middle speed + * @arg TSC_PAD_SPEED_2: Middle speed + * @arg TSC_PAD_SPEED_3: High speed + * @retval None + */ +#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__) + + +/** @brief Check if the HW detect mode is enable + * @param None + * @retval Current state of HW detect mode + */ +#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) + +/** @brief Check the detect type during HW detect mode + * @param __FLAG__ specifies the flag of detect type + * @arg TSC_FLAG_LESS_DET: Flag of less detect type + * @arg TSC_FLAG_GREAT_DET: Flag of great detect type + * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type + * @retval Current state of flag + */ +#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) + +/** @brief Get the number of channel which is detected now + * @param None + * @retval Current channel number + */ +#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos ) + +/** @brief Get the count value of pulse + * @param None + * @retval Pulse count of current channel + */ +#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos ) + +/** @brief Get the base value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval base value of the channel + */ +#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos) + +/** @brief Get the delta value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval delta value of the channel + */ +#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos ) + +/** @brief Get the internal resist value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval resist value of the channel + */ +#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TSC_Private_Macros + * @{ + */ +#define IS_TSC_DET_PERIOD(_PERIOD_) \ + (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ + ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ + ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ + ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ + ||((_PERIOD_)==TSC_DET_PERIOD_104) ) + +#define IS_TSC_FILTER(_FILTER_) \ + ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ + ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) + +#define IS_TSC_DET_MODE(_MODE_) \ + ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) + +#define IS_TSC_DET_TYPE(_TYPE_) \ + ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ + ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) + +#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) + +#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) + +#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk))) + +#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitType; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref Clock */ + + uint16_t Polarity; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitType; + +/** + * @} + */ + +/** @addtogroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) +/** @addtogroup USART_Word_Length + * @{ + */ + +#define USART_WL_8B ((uint16_t)0x0000) +#define USART_WL_9B ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B)) +/** + * @} + */ + +/** @addtogroup USART_Stop_Bits + * @{ + */ + +#define USART_STPB_1 ((uint16_t)0x0000) +#define USART_STPB_0_5 ((uint16_t)0x1000) +#define USART_STPB_2 ((uint16_t)0x2000) +#define USART_STPB_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) \ + (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \ + || ((STOPBITS) == USART_STPB_1_5)) +/** + * @} + */ + +/** @addtogroup Parity + * @{ + */ + +#define USART_PE_NO ((uint16_t)0x0000) +#define USART_PE_EVEN ((uint16_t)0x0400) +#define USART_PE_ODD ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define USART_MODE_RX ((uint16_t)0x0004) +#define USART_MODE_TX ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @addtogroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HFCTRL_NONE ((uint16_t)0x0000) +#define USART_HFCTRL_RTS ((uint16_t)0x0100) +#define USART_HFCTRL_CTS ((uint16_t)0x0200) +#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \ + || ((CONTROL) == USART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup Clock + * @{ + */ +#define USART_CLK_DISABLE ((uint16_t)0x0000) +#define USART_CLK_ENABLE ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Clock_Polarity + * @{ + */ + +#define USART_CLKPOL_LOW ((uint16_t)0x0000) +#define USART_CLKPOL_HIGH ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH)) + +/** + * @} + */ + +/** @addtogroup USART_Clock_Phase + * @{ + */ + +#define USART_CLKPHA_1EDGE ((uint16_t)0x0000) +#define USART_CLKPHA_2EDGE ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE)) + +/** + * @} + */ + +/** @addtogroup USART_Last_Bit + * @{ + */ + +#define USART_CLKLB_DISABLE ((uint16_t)0x0000) +#define USART_CLKLB_ENABLE ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Interrupt_definition + * @{ + */ + +#define USART_INT_PEF ((uint16_t)0x0028) +#define USART_INT_TXDE ((uint16_t)0x0727) +#define USART_INT_TXC ((uint16_t)0x0626) +#define USART_INT_RXDNE ((uint16_t)0x0525) +#define USART_INT_IDLEF ((uint16_t)0x0424) +#define USART_INT_LINBD ((uint16_t)0x0846) +#define USART_INT_CTSF ((uint16_t)0x096A) +#define USART_INT_ERRF ((uint16_t)0x0060) +#define USART_INT_OREF ((uint16_t)0x0360) +#define USART_INT_NEF ((uint16_t)0x0260) +#define USART_INT_FEF ((uint16_t)0x0160) +#define IS_USART_CFG_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \ + || ((IT) == USART_INT_ERRF)) +#define IS_USART_GET_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \ + || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF)) +#define IS_USART_CLR_INT(IT) \ + (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF)) +/** + * @} + */ + +/** @addtogroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAREQ_TX ((uint16_t)0x0080) +#define USART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup USART_WakeUp_methods + * @{ + */ + +#define USART_WUM_IDLELINE ((uint16_t)0x0000) +#define USART_WUM_ADDRMASK ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK)) +/** + * @} + */ + +/** @addtogroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBDL_10B ((uint16_t)0x0000) +#define USART_LINBDL_11B ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B)) +/** + * @} + */ + +/** @addtogroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004) +#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTSF ((uint16_t)0x0200) +#define USART_FLAG_LINBD ((uint16_t)0x0100) +#define USART_FLAG_TXDE ((uint16_t)0x0080) +#define USART_FLAG_TXC ((uint16_t)0x0040) +#define USART_FLAG_RXDNE ((uint16_t)0x0020) +#define USART_FLAG_IDLEF ((uint16_t)0x0010) +#define USART_FLAG_OREF ((uint16_t)0x0008) +#define USART_FLAG_NEF ((uint16_t)0x0004) +#define USART_FLAG_FEF ((uint16_t)0x0002) +#define USART_FLAG_PEF ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) \ + (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \ + || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \ + || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \ + || ((FLAG) == USART_FLAG_FEF)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \ + ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTSF)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_Module* USARTx); +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct); +void USART_StructInit(USART_InitType* USART_InitStruct); +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct); +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd); +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd); +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr); +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode); +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd); +void USART_SendData(USART_Module* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_Module* USARTx); +void USART_SendBreak(USART_Module* USARTx); +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler); +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd); +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd); +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode); +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd); +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG); +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG); +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT); +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X_USART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..cc83cc398fa197b9bf4383345d312f8be2e5b001 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_wwdg.h + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32L43X_WWDG_H__ +#define __N32L43X_WWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32l43x.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @addtogroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Constants + * @{ + */ + +/** @addtogroup WWDG_Prescaler + * @{ + */ + +#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000) +#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080) +#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100) +#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \ + || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8)) +#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler); +void WWDG_SetWValue(uint8_t WindowValue); +void WWDG_EnableInt(void); +void WWDG_SetCnt(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetEWINTF(void); +void WWDG_ClrEWINTF(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32L43X__WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/misc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/misc.c new file mode 100644 index 0000000000000000000000000000000000000000..ba5f8fef2c7fda4e50b156b7f790c509a4eebc70 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/misc.c @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "misc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @addtogroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @addtogroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority + * 0 bits for subpriority + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains + * the configuration information for the specified NVIC peripheral. + */ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset Vector Table base offset field. This value must be a multiple + * of 0x200. + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE. + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_adc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..55f0430b95181064889278d57ddae1b685d934fe --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_adc.c @@ -0,0 +1,1456 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_adc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_adc.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @addtogroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Defines + * @{ + */ + +/* ADC DISC_NUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISC_EN mask */ +#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800) +#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC INJ_AUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC INJ_DISC_EN mask */ +#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000) +#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC AWDG_CH mask */ +#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF) + +/* CTRL1 register Mask */ +#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) + +/* ADC AD_ON mask */ +#define CTRL2_AD_ON_SET ((uint32_t)0x00000001) +#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTRL2_DMA_SET ((uint32_t)0x00000100) +#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF) + +/* ADC RST_CALI mask */ +#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTRL2_CAL_SET ((uint32_t)0x00000004) + +/* ADC SOFT_START mask */ +#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000) + +/* ADC EXT_TRIG mask */ +#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000) +#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000) +#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC INJ_EXT_SEL mask */ +#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC INJ_EXT_TRIG mask */ +#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000) +#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC INJ_SWSTART mask */ +#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000) +#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000) +#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* CTRL2 register Mask */ +#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR4_SEQ_SET ((uint32_t)0x0000001F) +#define SQR3_SEQ_SET ((uint32_t)0x0000001F) +#define SQR2_SEQ_SET ((uint32_t)0x0000001F) +#define SQR1_SEQ_SET ((uint32_t)0x0000001F) + +/* RSEQ1 register Mask */ +#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSEQ_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC INJ_LEN mask */ +#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000) +#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SAMPTx mask */ +#define SAMPT1_SMP_SET ((uint32_t)0x00000007) +#define SAMPT2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDATx registers offset */ +#define JDAT_OFFSET ((uint8_t)0x28) + +/* ADC1 DAT register base address */ +#define DAT_ADDR ((uint32_t)0x4001244C) + +/* ADC STS register mask */ +#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F) +/** + * @} + */ + +/** @addtogroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_DeInit(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + + if (ADCx == ADC) + { + /* Enable ADC1 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE); + /* Release ADC1 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE); + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InitStruct pointer to an ADC_InitType structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn)); + assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect)); + assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign)); + assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber)); + + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tmpreg1 = ADCx->CTRL1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CTRL1_CLR_MASK; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to WorkMode value */ + /* Set SCAN bit according to MultiChEn value */ + tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8)); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tmpreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tmpreg1 = ADCx->CTRL2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CTRL2_CLR_MASK; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL bits according to ExtTrigSelect value */ + /* Set CONT bit according to ContinueConvEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1)); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tmpreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tmpreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tmpreg1 &= RSEQ1_CLR_MASK; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ChsNumber value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized. + */ +void ADC_InitStruct(ADC_InitType* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* initialize the MultiChEn member */ + ADC_InitStruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_InitStruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1; + /* Initialize the DatAlign member */ + ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_InitStruct->ChsNumber = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd) +{ + uint32_t i =0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AD_ON bit to wake up the ADC from power down mode */ + ADCx->CTRL2 |= CTRL2_AD_ON_SET; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CTRL2 &= CTRL2_AD_ON_RESET; + } + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcDmaModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CTRL2 |= CTRL2_DMA_SET; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CTRL2 &= CTRL2_DMA_RESET; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @param Cmd new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (Cmd != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CTRL1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CTRL1 &= (~(uint32_t)itmask); + } +} + + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_StartCalibration(ADC_Module* ADCx) +{ + uint32_t i =0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Enable the selected ADC calibration process */ + if(ADCx->CALFACT==0) + ADCx->CTRL2 |= CTRL2_CAL_SET; + /*Wait for ADC to filter burr after a delay of more than 8us */ + for(i=0;i<0x1FF;i++); +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + if(ADCx->CALFACT!=0) + bitstatus = RESET; + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of SOFT_START bit */ + if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET) + { + /* SOFT_START bit is set */ + bitstatus = SET; + } + else + { + /* SOFT_START bit is reset */ + bitstatus = RESET; + } + /* Return the SOFT_START bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Number specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + */ +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcSeqDiscNumberValid(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CTRL1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CTRL1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 |= CTRL1_DISC_EN_SET; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 &= CTRL1_DISC_EN_RESET; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcReqRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The Data conversion value. + */ +uint16_t ADC_GetDat(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DAT; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpregister = ADCx->CTRL2; + /* Clear the old external event selection for injected group */ + tmpregister &= CTRL2_INJ_EXT_SEL_RESET; + /* Set the external event selection for injected group */ + tmpregister |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @return The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of INJ_SWSTART bit */ + if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET) + { + /* INJ_SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* INJ_SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the INJ_SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcInjRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Get INJ_LEN value: Number = INJ_LEN+1 */ + tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param Length The sequencer length. + * This parameter must be a number between 1 to 4. + */ +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjLenValid(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Clear the old injected sequnence lenght INJ_LEN bits */ + tmpreg1 &= JSEQ_INJ_LEN_RESET; + /* Set the injected sequnence lenght INJ_LEN bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InjectedChannel the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @param Offset the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + */ +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + assert_param(IsAdcOffsetValid(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t*)tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InjectedChannel the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @return The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDAT_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_AnalogWatchdog the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel + * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog + */ +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpregister &= CTRL1_AWDG_MODE_RESET; + /* Set the analog watchdog enable mode */ + tmpregister |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param HighThreshold the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcValid(HighThreshold)); + assert_param(IsAdcValid(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->WDGHIGH = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->WDGLOW = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear the Analog watchdog channel select bits */ + tmpregister &= CTRL1_AWDG_CH_RESET; + /* Set the Analog watchdog channel */ + tmpregister |= ADC_Channel; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param Cmd new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableTempSensorVrefint(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 |= CTRL2_TSVREFE_SET; + _EnVref1p2() + _EnVref2p0() + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CTRL2 &= CTRL2_TSVREFE_RESET; + _DisVref1p2() + _DisVref2p0() + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + * @return The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + */ +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcClrFlag(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @return The new state of ADC_IT (SET or RESET). + */ +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT); + /* Check the status of the specified ADC interrupt */ + if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + */ +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStructEx. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx) +{ + uint32_t tmpregister = 0; + /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/ + if (ADC_InitStructEx->Samp303Style) + ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK; + else + ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK); + + /*intial ADC_CTRL3 once initiall config*/ + tmpregister = ADCx->CTRL3; + if (ADC_InitStructEx->DeepPowerModEn) + tmpregister |= ADC_CTRL3_DPWMOD_MSK; + else + tmpregister &= (~ADC_CTRL3_DPWMOD_MSK); + + if (ADC_InitStructEx->JendcIntEn) + tmpregister |= ADC_CTRL3_JENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK); + + if (ADC_InitStructEx->EndcIntEn) + tmpregister |= ADC_CTRL3_ENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK); + + if (ADC_InitStructEx->CalAtuoLoadEn) + tmpregister |= ADC_CTRL3_CALALD_MSK; + else + tmpregister &= (~ADC_CTRL3_CALALD_MSK); + + if (ADC_InitStructEx->DifModCal) + tmpregister |= ADC_CTRL3_CALDIF_MSK; + else + tmpregister &= (~ADC_CTRL3_CALDIF_MSK); + + tmpregister &= (~ADC_CTRL3_RES_MSK); + tmpregister |= ADC_InitStructEx->ResBit; + + tmpregister &= (~ADC_CTRL3_CKMOD_MSK); + if(ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL) + tmpregister |= ADC_CTRL3_CKMOD_MSK; + + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ADC_FLAG_NEW specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_RDY ADC ready flag + * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag + * @return The new state of ADC_FLAG_NEW (SET or RESET). + */ +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG_NEW)); + /* Check the status of the specified ADC flag */ + if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET) + { + /* ADC_FLAG_NEW is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG_NEW is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG_NEW status */ + return bitstatus; +} +/** + * @brief Set Adc calibration bypass or enable. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param en enable bypass calibration. + * This parameter can be one of the following values: + * @arg true bypass calibration + * @arg false not bypass calibration + */ +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + if (en) + tmpregister |= ADC_CTRL3_BPCAL_MSK; + else + tmpregister &= (~ADC_CTRL3_BPCAL_MSK); + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Set Adc trans bits width. + * @param ADCx where x can be 1 to select the ADC peripheral. + * @param ResultBitNum specifies num with adc trans width. + * This parameter can be one of the following values: + * @arg ADC_RST_BIT_12 12 bit trans + * @arg ADC_RST_BIT_10 10 bit trans + * @arg ADC_RST_BIT_8 8 bit trans + * @arg ADC_RESULT_BIT_6 6 bit trans + */ +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + tmpregister &= 0xFFFFFFFC; + tmpregister |= ResultBitNum; + ADCx->CTRL3 = tmpregister; + return; +} +/** + * @brief Set Adc Clock bits for AHB . + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx) +{ + ADCx->CTRL3 &= ADC_CLOCK_AHB; +} + +/** + * @brief Set Adc Clock bits for PLL . + * @param ADCx where x can be 1 to select the ADC peripheral. + */ +void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx) +{ + ADCx->CTRL3 |= ADC_CLOCK_PLL; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + + * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + */ +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler) +{ + if(ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){ + RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler); + ADC_AHB_Clock_Mode_Config(ADC); + }else{ + RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1); + ADC_PLL_Clock_Mode_Config(ADC); + } +} + +/** + * @brief ADC reference voltage switch. + * @param Select reference voltage of ADC. + * @arg ADC_REFENCE_Volt_VREF Select VREF+ as reference voltage + * @arg ADC_REFENCE_Volt_VREFBUFF Select VREFBUFF as reference voltage + * @return None. + */ +void Reference_Voltage_Switch(ADC_REFERENCE_Volt Ref_Type) +{ + uint32_t afectemp = 0; + RCC_EnableAPB1PeriphClk(RCC_APB1Periph_AFEC, ENABLE); + + afectemp = AFEC->TESTR0; + afectemp &= 0xFFE5FFC1; + if(Ref_Type == ADC_REFENCE_Volt_VREFBUFF) + { + afectemp |= 0x1A0034; + } + AFEC->TESTR0 = afectemp; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_can.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_can.c new file mode 100644 index 0000000000000000000000000000000000000000..85c41c0201845753e1e11955e59122e39b2bc287 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_can.c @@ -0,0 +1,1372 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_can.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_can.h" +#include "n32l43x_rcc.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @addtogroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */ +#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTS register */ +#define CAN_FLAGS_TSTS ((uint32_t)0x08000000) +/* Flags in RFF1 register */ +#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000) +/* Flags in RFF0 register */ +#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000) +/* Flags in MSTS register */ +#define CAN_FLAGS_MSTS ((uint32_t)0x01000000) +/* Flags in ESTS register */ +#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) +/** + * @} + */ + +/** @addtogroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_FunctionPrototypes + * @{ + */ + +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit); + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx. + */ +void CAN_DeInit(CAN_Module* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Enable CAN reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE); +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitParam. + * @param CAN to select the CAN peripheral. + * @param CAN_InitParam pointer to a CAN_InitType structure that + * contains the configuration information for the + * CAN peripheral. + * @return Constant indicates initialization succeed which will be + * CAN_InitSTS_Failed or CAN_InitSTS_Success. + */ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam) +{ + uint8_t InitStatus = CAN_InitSTS_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP)); + assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode)); + assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW)); + assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1)); + assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2)); + assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler)); + + /* Exit from sleep mode */ + CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ); + + /* Request initialisation */ + CANx->MCTRL |= CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitParam->TTCM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TTCM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitParam->ABOM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_ABOM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitParam->AWKUM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_AWKUM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitParam->NART == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_NART; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART; + } + + /* Set the receive DATFIFO locked mode */ + if (CAN_InitParam->RFLM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_RFLM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM; + } + + /* Set the transmit DATFIFO priority */ + if (CAN_InitParam->TXFP == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TXFP; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP; + } + + /* Set the bit timing register */ + CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24) + | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20) + | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1); + + /* Request leave initialisation */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + InitStatus = CAN_InitSTS_Success; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitFilterStruct. + * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType + * structure that contains the configuration + * information. + */ +void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num)); + assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num; + + /* Initialisation mode for the filter */ + CAN->FMC |= FMC_FINITM; + + /* Filter Deactivation */ + CAN->FA1 &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale) + { + /* 16-bit scale for the filter */ + CAN->FS1 &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId); + } + + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale) + { + /* 32-bit scale for the filter */ + CAN->FS1 |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId); + } + + /* Filter Mode */ + if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode) + { + /*Id/Mask mode for the filter*/ + CAN->FM1 &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */ + { + /*Identifier list mode for the filter*/ + CAN->FM1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter DATFIFO assignment */ + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0) + { + /* DATFIFO 0 assignation for the filter */ + CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1) + { + /* DATFIFO 1 assignation for the filter */ + CAN->FFA1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_InitFilterStruct->Filter_Act == ENABLE) + { + CAN->FA1 |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMC &= ~FMC_FINITM; +} +/** + * @brief Fills each CAN_InitParam member with its default value. + * @param CAN_InitParam pointer to a CAN_InitType structure which + * will be initialized. + */ +void CAN_InitStruct(CAN_InitType* CAN_InitParam) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitParam->TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitParam->ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitParam->AWKUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitParam->NART = DISABLE; + + /* Initialize the receive DATFIFO locked mode */ + CAN_InitParam->RFLM = DISABLE; + + /* Initialize the transmit DATFIFO priority */ + CAN_InitParam->TXFP = DISABLE; + + /* Initialize the OperatingMode member */ + CAN_InitParam->OperatingMode = CAN_Normal_Mode; + + /* Initialize the RSJW member */ + CAN_InitParam->RSJW = CAN_RSJW_1tq; + + /* Initialize the TBS1 member */ + CAN_InitParam->TBS1 = CAN_TBS1_4tq; + + /* Initialize the TBS2 member */ + CAN_InitParam->TBS2 = CAN_TBS2_3tq; + + /* Initialize the BaudRatePrescaler member */ + CAN_InitParam->BaudRatePrescaler = 1; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CAN to select the CAN peripheral. + * @param Cmd new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + */ +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCTRL |= MCTRL_DBGF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCTRL &= ~MCTRL_DBGF; + } +} + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CAN to select the CAN peripheral. + * @param Cmd Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + */ +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCTRL |= CAN_MCTRL_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CAN to select the CAN peripheral. + * @param TxMessage pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @return The number of the mailbox that is used for transmission + * or CAN_TxSTS_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ID(TxMessage->IDE)); + assert_param(IS_CAN_RTRQ(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxSTS_NoMailBox; + } + + if (transmit_mailbox != CAN_TxSTS_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Standard_Id) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TMDL = + (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) + | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TMDH = + (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) + | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx to select the CAN peripheral. + * @param TransmitMailbox the number of the mailbox that is used for + * transmission. + * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed + * in an other case. + */ +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2); + break; + default: + state = CAN_TxSTS_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): + state = CAN_TxSTS_Pending; + break; + /* transmit failed */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Failed; + break; + /* transmit succeeded */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Ok; + break; + default: + state = CAN_TxSTS_Failed; + break; + } + return (uint8_t)state; +} + +/** + * @brief Cancels a transmit request. + * @param CAN to select the CAN peripheral. + * @param Mailbox Mailbox number. + */ +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTS = CAN_TSTS_ABRQM0; + break; + case (CAN_TXMAILBOX_1): + CANx->TSTS = CAN_TSTS_ABRQM1; + break; + case (CAN_TXMAILBOX_2): + CANx->TSTS = CAN_TSTS_ABRQM2; + break; + default: + break; + } +} + +/** + * @brief Receives a message. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + */ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI; + if (RxMessage->IDE == CAN_Standard_Id) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24); + /* Release the DATFIFO */ + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Releases the specified DATFIFO. + * @param CAN to select the CAN peripheral. + * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1. + */ +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CAN to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @return NbMessage : which is the number of pending message. + */ +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum) +{ + uint8_t message_pending = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + if (FIFONum == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03); + } + else if (FIFONum == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Select the CAN Operation mode. + * @param CAN to select the CAN peripheral. + * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one + * of @ref CAN_operating_mode enumeration. + * @return status of the requested mode which can be + * - CAN_ModeSTS_Failed CAN failed entering the specific mode + * - CAN_ModeSTS_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeSTS_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INIAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_Operating_InitMode) + { + /* Request initialisation */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_NormalMode) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != 0) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_SleepMode) + { + /* Request Sleep mode */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else + { + status = CAN_ModeSTS_Failed; + } + + return (uint8_t)status; +} + +/** + * @brief Enters the low power mode. + * @param CAN to select the CAN peripheral. + * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an + * other case. + */ +uint8_t CAN_EnterSleep(CAN_Module* CANx) +{ + uint8_t sleepstatus = CAN_SLEEP_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Sleep mode status */ + if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_SLEEP_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CAN to select the CAN peripheral. + * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_Module* CANx) +{ + uint32_t wait_slak = SLPAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WKU_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ; + + /* Sleep mode status */ + while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WKU_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CAN to select the CAN peripheral. + * @return CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrCode(CAN_Module* CANx) +{ + uint8_t errorcode = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx to to select the CAN peripheral. + * @return CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CAN to to select the CAN peripheral. + * @return LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_INT_TME, + * - CAN_INT_FMP0, + * - CAN_INT_FF0, + * - CAN_INT_FOV0, + * - CAN_INT_FMP1, + * - CAN_INT_FF1, + * - CAN_INT_FOV1, + * - CAN_INT_EWG, + * - CAN_INT_EPV, + * - CAN_INT_LEC, + * - CAN_INT_ERR, + * - CAN_INT_WKU or + * - CAN_INT_SLK. + * @param Cmd new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->INTE |= CAN_INT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->INTE &= ~CAN_INT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWGFL + * - CAN_FLAG_EPVFL + * - CAN_FLAG_BOFFL + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFMP1 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFMP0 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @return The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CAN to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + */ +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */ + { + /* Clear the selected CAN flags */ + CANx->ESTS = (uint32_t)RESET; + } + else /* MSTS or TSTS or RFF0 or RFF1 */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSTS = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSTS = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_INT_TME + * - CAN_INT_FMP0 + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FMP1 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + * @return The current state of CAN_INT (SET or RESET). + */ +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT) +{ + INTStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + + /* check the enable interrupt bit */ + if ((CANx->INTE & CAN_INT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_INT) + { + case CAN_INT_TME: + /* Check CAN_TSTS_RQCPx bits */ + itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2); + break; + case CAN_INT_FMP0: + /* Check CAN_RFF0_FFMP0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0); + break; + case CAN_INT_FF0: + /* Check CAN_RFF0_FFULL0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0); + break; + case CAN_INT_FOV0: + /* Check CAN_RFF0_FFOVR0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0); + break; + case CAN_INT_FMP1: + /* Check CAN_RFF1_FFMP1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1); + break; + case CAN_INT_FF1: + /* Check CAN_RFF1_FFULL1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1); + break; + case CAN_INT_FOV1: + /* Check CAN_RFF1_FFOVR1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1); + break; + case CAN_INT_WKU: + /* Check CAN_MSTS_WKUINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT); + break; + case CAN_INT_SLK: + /* Check CAN_MSTS_SLAKINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT); + break; + case CAN_INT_EWG: + /* Check CAN_ESTS_EWGFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL); + break; + case CAN_INT_EPV: + /* Check CAN_ESTS_EPVFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL); + break; + case CAN_INT_BOF: + /* Check CAN_ESTS_BOFFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL); + break; + case CAN_INT_LEC: + /* Check CAN_ESTS_LEC bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC); + break; + case CAN_INT_ERR: + /* Check CAN_MSTS_ERRINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_INT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CAN to select the CAN peripheral. + * @param CAN_INT specifies the interrupt pending bit to clear. + * - CAN_INT_TME + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + */ +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_INT(CAN_INT)); + + switch (CAN_INT) + { + case CAN_INT_TME: + /* Clear CAN_TSTS_RQCPx (rc_w1)*/ + CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2; + break; + case CAN_INT_FF0: + /* Clear CAN_RFF0_FFULL0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFULL0; + break; + case CAN_INT_FOV0: + /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFOVR0; + break; + case CAN_INT_FF1: + /* Clear CAN_RFF1_FFULL1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFULL1; + break; + case CAN_INT_FOV1: + /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFOVR1; + break; + case CAN_INT_WKU: + /* Clear CAN_MSTS_WKUINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_WKUINT; + break; + case CAN_INT_SLK: + /* Clear CAN_MSTS_SLAKINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_SLAKINT; + break; + case CAN_INT_EWG: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_EPV: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_BOF: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_LEC: + /* Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + break; + case CAN_INT_ERR: + /*Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default: + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg specifies the CAN interrupt register to check. + * @param Int_Bit specifies the interrupt source bit to check. + * @return The new state of the CAN Interrupt (SET or RESET). + */ +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit) +{ + INTStatus pendingbitstatus = RESET; + + if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) + { + /* CAN_INT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_INT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_comp.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_comp.c new file mode 100644 index 0000000000000000000000000000000000000000..58b006ee09c7636c0089b5995fa525a23848bd88 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_comp.c @@ -0,0 +1,385 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_comp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_comp.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @brief COMP driver modules + * @{ + */ + +/** @addtogroup COMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the COMP peripheral registers to their default reset values. + */ +void COMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE); +} +void COMP_StructInit(COMP_InitType* COMP_InitStruct) +{ + COMP_InitStruct->LowPoweMode = false; // only COMP1 have this bit + COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit + + COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */ + + COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK + + COMP_InitStruct->PolRev = false; // out polarity reverse + + COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC; + COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2 + COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s + COMP_InitStruct->FilterEn= false; + COMP_InitStruct->ClkPsc= 0; + COMP_InitStruct->SampWindow= 0; + COMP_InitStruct->Thresh= 0; + COMP_InitStruct->En = false; +} +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct) +{ + COMP_SingleType* pCS; + __IO uint32_t tmp; + if(COMPx == COMP1) + pCS = &COMP->Cmp1; + else + pCS = &COMP->Cmp2; + + // filter + tmp = pCS->FILC; + SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK); + SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK); + SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK); + pCS->FILC = tmp; + // filter psc + pCS->FILP = COMP_InitStruct->ClkPsc; + + // ctrl + tmp = pCS->CTRL; + if (COMPx == COMP1) + { + if (COMP_InitStruct->InpDacConnect) + SetBit(tmp, COMP1_CTRL_INPDAC_MASK); + else + ClrBit(tmp, COMP1_CTRL_INPDAC_MASK); + if (COMP_InitStruct->LowPoweMode) + SetBit(tmp, COMP1_CTRL_PWRMODE_MASK); + else + ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK); + } + SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK); + SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK); + if (COMP_InitStruct->PolRev) + SetBit(tmp, COMP_POL_MASK); + else + ClrBit(tmp, COMP_POL_MASK); + SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK); + if (COMP_InitStruct->En) + SetBit(tmp, COMP_CTRL_EN_MASK); + else + ClrBit(tmp, COMP_CTRL_EN_MASK); + pCS->CTRL = tmp; +} +void COMP_Enable(COMPX COMPx, FunctionalState en) +{ + if(COMPx == COMP1) + { + if (en) + SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK); + } + else + { + if (en) + SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK); + } +} + +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; + +} +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig) +{ + __IO uint32_t tmp; + if(COMPx == COMP1) + tmp = COMP->Cmp1.CTRL; + else + tmp = COMP->Cmp2.CTRL; + + SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK); + + if(COMPx == COMP1) + COMP->Cmp1.CTRL = tmp; + else + COMP->Cmp2.CTRL = tmp; +} + +// return see @COMP_INTSTS_CMPIS +uint32_t COMP_GetIntSts(void) +{ + return COMP->INTSTS; +} +// parma range see @COMP_VREFSCL +// Vv2Trim,Vv1Trim max 63 +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En) +{ + __IO uint32_t tmp = 0; + + SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK); + SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK); + SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK); + SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK); + + COMP->VREFSCL = tmp; +} +// SET when comp out 1 +// RESET when comp out 0 +FlagStatus COMP_GetOutStatus(COMPX COMPx) +{ + if(COMPx == COMP1) + return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; + else + return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; +} +// get one comp interrupt flags +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx) +{ + return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET; +} + +// Lock see @COMP_LOCK +void COMP_SetLock(uint32_t Lock) +{ + COMP->LOCK = Lock; +} +// IntEn see @COMP_INTEN_CMPIEN +void COMP_SetIntEn(uint32_t IntEn) +{ + COMP->INTEN = IntEn; +} +// set comp2 xor output with comp1 +void COMP_CMP2XorOut(bool En) +{ + COMP->CMP2OSEL = (En==true)?0x1L:0x0L; +} +// set stop or lowpower mode that sel 32k clk +void COMP_StopOrLowpower32KClkSel(bool En) +{ + COMP->LPCKSEL = (En==true)?0x1L:0x0L; +} +// set comp1 and comp2 component window compare mode +void COMP_WindowModeEn(bool En) +{ + COMP->WINMODE = (En==true)?0x1L:0x0L; +} + + +/** + * @brief Set the COMP filter clock Prescaler value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1. + * @return void + */ +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILP=FilPreVal; + else + COMP->Cmp2.FILP=FilPreVal; +} + +/** + * @brief Set the COMP filter control value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param FilEn 1 for enable ,0 or disable + * @param TheresNum num under this value is noise + * @param SampPW total sample number in a window + * @return void + */ +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW) +{ + if(COMPx == COMP1) + COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); + else + COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); +} + +/** + * @brief Set the COMP Hyst value. + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param HYST specifies the HYST level. + * This parameter can be one of the following values: +* @arg COMP_CTRL_HYST_NO Hyst disable +* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV +* @arg COMP_CTRL_HYST_MID Hyst level 15mV +* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV + * @return void + */ +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + + tmp&=~COMP_CTRL_HYST_HIGH; + tmp|=HYST; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @brief Set the COMP Blanking source . + * @param COMPx where x can be 1 to 2 to select the COMP peripheral. + * @param BLK specifies the blanking source . + * This parameter can be one of the following values: +* @arg COMP_CTRL_BLKING_NO Blanking disable +* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5 +* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5 + * @return void + */ +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK) +{ + uint32_t tmp; + if(COMPx == COMP1) + tmp=COMP->Cmp1.CTRL; + else + tmp=COMP->Cmp2.CTRL; + tmp&=~(7<<16); + tmp|=BLK; + if(COMPx == COMP1) + COMP->Cmp1.CTRL=tmp; + else + COMP->Cmp2.CTRL=tmp; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_crc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..ee321604889b5c218461134ee563078d8c6d78f0 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_crc.c @@ -0,0 +1,227 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_crc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_crc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @addtogroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DAT). + */ +void CRC32_ResetCrc(void) +{ + /* Reset CRC generator */ + CRC->CRC32CTRL = CRC32_CTRL_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data data word(32-bit) to compute its CRC + * @return 32-bit CRC + */ +uint32_t CRC32_CalcCrc(uint32_t Data) +{ + CRC->CRC32DAT = Data; + + return (CRC->CRC32DAT); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed + * @return 32-bit CRC + */ +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < BufferLength; index++) + { + CRC->CRC32DAT = pBuffer[index]; + } + return (CRC->CRC32DAT); +} + +/** + * @brief Returns the current CRC value. + * @return 32-bit CRC + */ +uint32_t CRC32_GetCrc(void) +{ + return (CRC->CRC32DAT); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue 8-bit value to be stored in the ID register + */ +void CRC32_SetIDat(uint8_t IDValue) +{ + CRC->CRC32IDAT = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @return 8-bit value of the ID register + */ +uint8_t CRC32_GetIDat(void) +{ + return (CRC->CRC32IDAT); +} + +// CRC16 add +void __CRC16_SetLittleEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL; +} +void __CRC16_SetBigEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL; +} +void __CRC16_SetCleanEnable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL; +} +void __CRC16_SetCleanDisable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL; +} + +uint16_t __CRC16_CalcCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; + return (CRC->CRC16D); +} + +void __CRC16_SetCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; +} + +uint16_t __CRC16_GetCrc(void) +{ + return (CRC->CRC16D); +} + +void __CRC16_SetLRC(uint8_t Data) +{ + CRC->LRC = Data; +} + +uint8_t __CRC16_GetLRC(void) +{ + return (CRC->LRC); +} + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + CRC->CRC16D = 0x00; + for (index = 0; index < BufferLength; index++) + { + CRC->CRC16DAT = pBuffer[index]; + } + return (CRC->CRC16D); +} + +uint16_t CRC16_CalcCRC(uint8_t Data) +{ + CRC->CRC16DAT = Data; + + return (CRC->CRC16D); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dac.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..69e6c87fd7200aa2227bcbe54240641163d7e96d --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dac.c @@ -0,0 +1,357 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dac.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_dac.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @addtogroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Defines + * @{ + */ + +/* CTRL register Mask */ +#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000001) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE) + +/* DCH registers offsets */ +#define DR12CH_OFFSET ((uint32_t)0x00000008) + +/* DATO register offset */ +#define DATO_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @addtogroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_InitStruct pointer to a DAC_InitType structure that + * contains the configuration information for the specified DAC channel. + */ +void DAC_Init(DAC_InitType* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput)); + /*---------------------------- DAC CTRL Configuration --------------------------*/ + /* Get the DAC CTRL value */ + tmpreg1 = DAC->CTRL; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CTRL_CLEAR_MASK ); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to Trigger value */ + /* Set WAVEx bits according to WaveGen value */ + /* Set MAMPx bits according to LfsrUnMaskTriAmp value */ + /* Set BOFFx bit according to BufferOutput value */ + tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp + | DAC_InitStruct->BufferOutput); + /* Calculate CTRL register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 ; + /* Write to DAC CTRL */ + DAC->CTRL = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct pointer to a DAC_InitType structure which will + * be initialized. + */ +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct) +{ + /*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the Trigger member */ + DAC_InitStruct->Trigger = DAC_TRG_NONE; + /* Initialize the WaveGen member */ + DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE; + /* Initialize the LfsrUnMaskTriAmp member */ + DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0; + /* Initialize the BufferOutput member */ + DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_Enable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CTRL |= DAC_CTRL_CHEN ; + } + else + { + /* Disable the selected DAC channel */ + DAC->CTRL &= ~DAC_CTRL_CHEN ; + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_DmaEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CTRL |= DAC_CTRL_DMAEN; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CTRL &= ~DAC_CTRL_DMAEN; + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SOTTR |= DAC_SOTTR_TREN ; + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SOTTR &= ~(DAC_SOTTR_TREN); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param Cmd new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftwareTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SOTTR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SOTTR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_Wave Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_WAVE_NOISE noise wave generation + * @arg DAC_WAVE_TRIANGLE triangle wave generation + * @param Cmd new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmp=DAC->CTRL; + tmp&=~(3<<6); + if (Cmd != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + tmp |= DAC_Wave; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + tmp&=~(3<<6); + } + DAC->CTRL =tmp; +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + */ +void DAC_SetChData(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DR12CH_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*)tmp = Data; +} + + + + + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @return The selected DAC channel data output value. + */ +uint16_t DAC_GetOutputDataVal(void) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DATO_OFFSET; + + /* Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dbg.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dbg.c new file mode 100644 index 0000000000000000000000000000000000000000..2447293d5b4f3f56d94006fcc63279226ed6e3a2 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dbg.c @@ -0,0 +1,260 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dbg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_dbg.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @brief DBG driver modules + * @{ + */ + +/** @addtogroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Functions + * @{ + */ + + +void GetUCID(uint8_t *UCIDbuf) +{ + uint8_t num = 0; + uint32_t* ucid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260)) + { + ucid_addr = (uint32_t*)UCID_BASE; + } + else + { + ucid_addr = (uint32_t*)(0x1FFFF260); + } + + for (num = 0; num < UCID_LENGTH;) + { + temp = *(__IO uint32_t*)(ucid_addr++); + UCIDbuf[num++] = (temp & 0xFF); + UCIDbuf[num++] = (temp & 0xFF00) >> 8; + UCIDbuf[num++] = (temp & 0xFF0000) >> 16; + UCIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the UID. + * @return UID + */ + +void GetUID(uint8_t *UIDbuf) +{ + uint8_t num = 0; + uint32_t* uid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270)) + { + uid_addr = (uint32_t*)UID_BASE; + } + else + { + uid_addr = (uint32_t*)(0x1FFFF270); + } + + for (num = 0; num < UID_LENGTH;) + { + temp = *(__IO uint32_t*)(uid_addr++); + UIDbuf[num++] = (temp & 0xFF); + UIDbuf[num++] = (temp & 0xFF00) >> 8; + UIDbuf[num++] = (temp & 0xFF0000) >> 16; + UIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the DBGMCU_ID. + * @return DBGMCU_ID + */ + +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf) +{ + uint8_t num = 0; + uint32_t* dbgid_addr = (void*)0; + uint32_t temp = 0; + + dbgid_addr = (uint32_t*)DBGMCU_ID_BASE; + for (num = 0; num < DBGMCU_ID_LENGTH;) + { + temp = *(__IO uint32_t*)(dbgid_addr++); + DBGMCU_IDbuf[num++] = (temp & 0xFF); + DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8; + DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16; + DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the device revision number. + * @return Device revision identifier + */ +uint32_t DBG_GetRevNum(void) +{ + return (DBG->ID & 0x00FF); +} + +/** + * @brief Returns the device identifier. + * @return Device identifier + */ +uint32_t DBG_GetDevNum(void) +{ + uint32_t id = DBG->ID; + return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBG_Periph specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBG_SLEEP Keep debugger connection during SLEEP mode + * @arg DBG_STOP Keep debugger connection during STOP mode + * @arg DBG_STDBY Keep debugger connection during STANDBY mode + * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted + * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted + * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted + * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted + * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted + * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted + * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted + * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted + * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted + * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted + * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted + * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted + + * @param Cmd new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + */ +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBG_Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + DBG->CTRL |= DBG_Periph; + } + else + { + DBG->CTRL &= ~DBG_Periph; + } +} + +/** + * @brief Get FLASH size of this chip. + * + * @return FLASH size in bytes. + */ +uint32_t DBG_GetFlashSize(void) +{ + return (DBG->ID & 0x000F0000); +} + +/** + * @brief Get SRAM size of this chip. + * + * @return SRAM size in bytes. + */ +uint32_t DBG_GetSramSize(void) +{ + return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dma.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..d489ef18e05c47c07646d419b88a3f08e1e63fb2 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_dma.c @@ -0,0 +1,686 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_dma.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_dma.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @addtogroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Defines + * @{ + */ + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1)) +#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2)) +#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3)) +#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4)) +#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5)) +#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6)) +#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7)) +#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8)) + + +/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + */ +void DMA_DeInit(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + + /* Reset DMAy Channelx control register */ + DMAChx->CHCFG = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAChx->TXNUM = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAChx->PADDR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAChx->MADDR = 0; + + if (DMAChx == DMA_CH1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA->INTCLR |= DMA_CH1_INT_MASK; + } + else if (DMAChx == DMA_CH2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA->INTCLR |= DMA_CH2_INT_MASK; + } + else if (DMAChx == DMA_CH3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA->INTCLR |= DMA_CH3_INT_MASK; + } + else if (DMAChx == DMA_CH4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA->INTCLR |= DMA_CH4_INT_MASK; + } + else if (DMAChx == DMA_CH5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA->INTCLR |= DMA_CH5_INT_MASK; + } + else if (DMAChx == DMA_CH6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA->INTCLR |= DMA_CH6_INT_MASK; + } + else if (DMAChx == DMA_CH7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA->INTCLR |= DMA_CH7_INT_MASK; + } + else if (DMAChx == DMA_CH8) + { + /* Reset interrupt pending bits for DMA1 Channel8 */ + DMA->INTCLR |= DMA_CH8_INT_MASK; + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitParam. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMA_InitParam pointer to a DMA_InitType structure that + * contains the configuration information for the specified DMA Channel. + */ +void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_DIR(DMA_InitParam->Direction)); + assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize)); + assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc)); + assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize)); + assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode)); + assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem)); + + /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/ + /* Get the DMAyChx CHCFG value */ + tmpregister = DMAChx->CHCFG; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpregister &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to Direction value */ + /* Set CIRC bit according to CircularMode value */ + /* Set PINC bit according to PeriphInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to PeriphDataSize value */ + /* Set MSIZE bits according to MemDataSize value */ + /* Set PL bits according to Priority value */ + /* Set the MEM2MEM bit according to Mem2Mem value */ + tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc + | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize + | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem; + + /* Write to DMAy Channelx CHCFG */ + DMAChx->CHCFG = tmpregister; + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMAy Channelx TXNUM */ + DMAChx->TXNUM = DMA_InitParam->BufSize; + + /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/ + /* Write to DMAy Channelx PADDR */ + DMAChx->PADDR = DMA_InitParam->PeriphAddr; + + /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/ + /* Write to DMAy Channelx MADDR */ + DMAChx->MADDR = DMA_InitParam->MemAddr; +} + +/** + * @brief Fills each DMA_InitParam member with its default value. + * @param DMA_InitParam pointer to a DMA_InitType structure which will + * be initialized. + */ +void DMA_StructInit(DMA_InitType* DMA_InitParam) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the PeriphAddr member */ + DMA_InitParam->PeriphAddr = 0; + /* Initialize the MemAddr member */ + DMA_InitParam->MemAddr = 0; + /* Initialize the Direction member */ + DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC; + /* Initialize the BufSize member */ + DMA_InitParam->BufSize = 0; + /* Initialize the PeriphInc member */ + DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE; + /* Initialize the DMA_MemoryInc member */ + DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE; + /* Initialize the PeriphDataSize member */ + DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + /* Initialize the MemDataSize member */ + DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the CircularMode member */ + DMA_InitParam->CircularMode = DMA_MODE_NORMAL; + /* Initialize the Priority member */ + DMA_InitParam->Priority = DMA_PRIORITY_LOW; + /* Initialize the Mem2Mem member */ + DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAChx->CHCFG |= DMA_CHCFG1_CHEN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DMAInt specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_INT_TXC Transfer complete interrupt mask + * @arg DMA_INT_HTX Half transfer interrupt mask + * @arg DMA_INT_ERR Transfer error interrupt mask + * @param Cmd new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + assert_param(IS_DMA_CONFIG_INT(DMAInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAChx->CHCFG |= DMAInt; + } + else + { + /* Disable the selected DMA interrupts */ + DMAChx->CHCFG &= ~DMAInt; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param DataNumber The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAyChx is disabled. + */ +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMA Channelx TXNUM */ + DMAChx->TXNUM = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMA Channelx transfer. + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @return The number of remaining data units in the current DMA Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAChx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAChx->TXNUM)); +} + +/** + * @brief Checks whether the specified DMA Channelx flag is set or not. + * @param DMAFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel7 global flag. + * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMAFlag (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy flag */ + if ((tmpregister & DMAFlag) != (uint32_t)RESET) + { + /* DMAyFlag is set */ + bitstatus = SET; + } + else + { + /* DMAyFlag is reset */ + bitstatus = RESET; + } + + /* Return the DMAyFlag status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's pending flags. + * @param DMAFlag specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_FLAG_GL1 DMA Channel1 global flag. + * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2 DMA Channel2 global flag. + * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3 DMA Channel3 global flag. + * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4 DMA Channel4 global flag. + * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5 DMA Channel5 global flag. + * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6 DMA Channel6 global flag. + * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7 DMA Channel7 global flag. + * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag. + * @arg DMA_FLAG_GL8 DMA Channel8 global flag. + * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag. + * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag. + * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAFlag)); + + /* Calculate the used DMAy */ + /* Clear the selected DMAy flags */ + DMAy->INTCLR = DMAFlag; +} + +/** + * @brief Checks whether the specified DMA Channelx interrupt has occurred or not. + * @param DMA_IT specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMA DMA + * This parameter can be one of the following values: + * @arg DMA . + * @return The new state of DMA_IT (SET or RESET). + */ +INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy interrupt */ + if ((tmpregister & DMA_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMAInt status */ + return bitstatus; +} + +/** + * @brief Clears the DMA Channelx's interrupt pending bits. + * @param DMA_IT specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_INT_GLB1 DMA Channel1 global interrupt. + * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt. + * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt. + * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt. + * @arg DMA_INT_GLB2 DMA Channel2 global interrupt. + * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt. + * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt. + * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt. + * @arg DMA_INT_GLB3 DMA Channel3 global interrupt. + * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt. + * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt. + * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt. + * @arg DMA_INT_GLB4 DMA Channel4 global interrupt. + * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt. + * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt. + * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt. + * @arg DMA_INT_GLB5 DMA Channel5 global interrupt. + * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt. + * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt. + * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt. + * @arg DMA_INT_GLB6 DMA Channel6 global interrupt. + * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt. + * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt. + * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt. + * @arg DMA_INT_GLB7 DMA Channel7 global interrupt. + * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt. + * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt. + * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt. + * @arg DMA_INT_GLB8 DMA Channel8 global interrupt. + * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt. + * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt. + * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + */ +void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLR_INT(DMA_IT)); + + /* Calculate the used DMA */ + /* Clear the selected DMA interrupt pending bits */ + DMAy->INTCLR = DMA_IT; +} + +/** + * @brief Set the DMA Channelx's remap request. + * @param DMA_REMAP specifies the DMA request. + * This parameter can be set by the following values: + * @arg DMA_REMAP_ADC1 DMA Request For ADC1. + * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX. + * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX. + * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX. + * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX. + * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX. + * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX. + * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX. + * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX. + * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX. + * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX. + * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX. + * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX. + * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX. + * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX. + * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX. + * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX. + * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX. + * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX. + * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX. + * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX. + * @arg DMA_REMAP_DAC1 DMA Request For DAC1. + * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1. + * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2. + * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3. + * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4. + * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM. + * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP. + * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG. + * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1. + * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2. + * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3. + * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP. + * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1. + * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3. + * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4. + * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP. + * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG. + * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1. + * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2. + * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3. + * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP. + * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1. + * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2. + * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3. + * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4. + * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP. + * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG. + * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP. + * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP. + * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1. + * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2. + * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3. + * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4. + * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM. + * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP. + * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG. + * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1. + * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG. + * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3. + * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4. + * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP. + * @param DMAy DMA + * This parameter can be one of the following values: + * @arg DMA . + * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel. + * @param Cmd new state of the DMA Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_REMAP(DMA_REMAP)); + + if (Cmd != DISABLE) + { + /* Calculate the used DMAy */ + /* Set the selected DMAy remap request */ + DMAChx->CHSEL = DMA_REMAP; + } + else + { + /* Clear DMAy remap */ + DMAChx->CHSEL = 0; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_exti.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_exti.c new file mode 100644 index 0000000000000000000000000000000000000000..f702b064517745b5e52a69b32c7f7c2fa24c1fdb --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_exti.c @@ -0,0 +1,286 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_exti.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_exti.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @addtogroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + */ +void EXTI_DeInit(void) +{ + EXTI->IMASK = 0x00000000; + EXTI->EMASK = 0x00000000; + EXTI->RT_CFG = 0x00000000; + EXTI->FT_CFG = 0x00000000; + EXTI->PEND = 0x0FFFFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure + * that contains the configuration information for the EXTI peripheral. + */ +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will + * be initialized. + */ +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_TriggerSWInt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIE |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrStatusFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..27) + * @return The new state of EXTI_Line (SET or RESET). + */ +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMASK & EXTI_Line; + if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + */ +void EXTI_ClrITPendBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Select one of EXTI inputs to the RTC TimeStamp event. + * @param EXTI_TSSEL_Line specifies the EXTI lines to select. + * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15). + */ +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line)); + + EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK; + EXTI->TS_SEL |= EXTI_TSSEL_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_flash.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..525fe073df7566de5497260d581b9967dfd67d40 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_flash.c @@ -0,0 +1,1554 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_flash.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_flash.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @addtogroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define AC_LATENCY_MSK ((uint32_t)0x000000F8) +#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF) +#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F) +#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF) +#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF) + +/* Flash Access Control Register bits */ +#define AC_PRFTBS_MSK ((uint32_t)0x00000020) +#define AC_ICAHRST_MSK ((uint32_t)0x00000040) +#define AC_LVMF_MSK ((uint32_t)0x00000100) +#define AC_SLMF_MSK ((uint32_t)0x00000400) + +/* Flash Control Register bits */ +#define CTRL_Set_PG ((uint32_t)0x00000001) +#define CTRL_Reset_PG ((uint32_t)0x00003FFE) +#define CTRL_Set_PER ((uint32_t)0x00000002) +#define CTRL_Reset_PER ((uint32_t)0x00003FFD) +#define CTRL_Set_MER ((uint32_t)0x00000004) +#define CTRL_Reset_MER ((uint32_t)0x00003FFB) +#define CTRL_Set_OPTPG ((uint32_t)0x00000010) +#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF) +#define CTRL_Set_OPTER ((uint32_t)0x00000020) +#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF) +#define CTRL_Set_START ((uint32_t)0x00000040) +#define CTRL_Set_LOCK ((uint32_t)0x00000080) +#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF) +#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000) +#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100) + +/* FLASH Mask */ +#define RDPRTL1_MSK ((uint32_t)0x00000002) +#define RDPRTL2_MSK ((uint32_t)0x80000000) +#define OBR_USER_MSK ((uint32_t)0x0000001C) +#define WRP0_MSK ((uint32_t)0x000000FF) +#define WRP1_MSK ((uint32_t)0x0000FF00) +#define WRP2_MSK ((uint32_t)0x00FF0000) +#define WRP3_MSK ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define L1_RDP_Key ((uint32_t)0xFFFF00A5) +#define RDP_USER_Key ((uint32_t)0xFFF000A5) +#define L2_RDP_Key ((uint32_t)0xFFFF33CC) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @note This function can be used for N32L43x devices. + * @param FLASH_Latency specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1 FLASH One Latency cycle + * @arg FLASH_LATENCY_2 FLASH Two Latency cycles + * @arg FLASH_LATENCY_3 FLASH Three Latency cycles + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpregister = FLASH->AC; + + /* Sets the Latency value */ + tmpregister &= AC_LATENCY_MSK; + tmpregister |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->AC = tmpregister; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for N32L43x devices. + * @param FLASH_PrefetchBuf specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable + */ +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->AC &= AC_PRFTBE_MSK; + FLASH->AC |= FLASH_PrefetchBuf; +} + +/** + * @brief ICache Reset. + * @note This function can be used for N32L43x devices. + */ +void FLASH_iCacheRST(void) +{ + /* ICache Reset */ + FLASH->AC |= FLASH_AC_ICAHRST; +} + +/** + * @brief Enables or disables the iCache. + * @note This function can be used for N32L43x devices. + * @param FLASH_iCache specifies the iCache status. + * This parameter can be one of the following values: + * @arg FLASH_iCache_EN FLASH iCache Enable + * @arg FLASH_iCache_DIS FLASH iCache Disable + */ +void FLASH_iCacheCmd(uint32_t FLASH_iCache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache)); + + /* Enable or disable the iCache */ + FLASH->AC &= AC_ICAHEN_MSK; + FLASH->AC |= FLASH_iCache; +} + +/** + * @brief Enables or disables the Low Voltage Mode. + * @note This function can be used for N32L43x devices. + * @param FLASH_LVM specifies the Low Voltage Mode status. + * This parameter can be one of the following values: + * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable + * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable + */ +void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LVM(FLASH_LVM)); + + /* Enable or disable LVM */ + FLASH->AC &= AC_LVMEN_MSK; + FLASH->AC |= FLASH_LVM; +} + +/** + * @brief Checks whether the Low Voltage Mode status is SET or RESET. + * @note This function can be used for N32L43x devices. + * @return Low Voltage Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetLowVoltageModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the FLASH Sleep Mode. + * @note This function can be used for N32L43x devices. + * @param FLASH_SLM specifies the FLASH Sleep Mode status. + * This parameter can be one of the following values: + * @arg FLASH_SLM_EN FLASH iCache Enable + * @arg FLASH_SLM_DIS FLASH iCache Disable + */ +void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SLM(FLASH_SLM)); + + /* Enable or disable SLM */ + FLASH->AC &= AC_SLMEN_MSK; + FLASH->AC |= FLASH_SLM; +} + +/** + * @brief Checks whether the FLASH Sleep Mode status is SET or RESET. + * @note This function can be used for N32L43x devices. + * @return FLASH Sleep Mode Status (SET or RESET). + */ +FlagStatus FLASH_GetFLASHSleepModeSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32L43x devices. + * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2 + */ +void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel)); + + /* SMP1 or SMP2 */ + FLASH->CTRL &= CTRL_Reset_SMPSEL; + FLASH->CTRL |= FLASH_smpsel; +} + +/** + * @brief Configures the Internal High Speed oscillator + * to program/erase FLASH. + * @note This function can be used for N32L43x devices. + * - For N32L43x devices this function enable HSI. + * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE). + */ +FLASH_HSICLOCK FLASH_ClockInit(void) +{ + bool HSIStatus = 0; + __IO uint32_t StartUpCounter = 0; + FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE; + + if((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET) + { + /* Enable HSI */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF; + StartUpCounter++; + } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET); + if (!HSIStatus) + { + hsiclock_status = FLASH_HSICLOCK_DISABLE; + } + } + return hsiclock_status; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for N32L43x devices. + * - For N32L43x devices this function unlocks Bank. + * to FLASH_Unlock function.. + */ +void FLASH_Unlock(void) +{ + /* Unlocks the FLASH Program Erase Controller */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for N32L43x devices. + * - For N32L43x devices this function Locks Bank. + * to FLASH_Lock function. + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FLASH Program Erase Controller */ + FLASH->CTRL |= CTRL_Set_LOCK; +} + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for N32L43x devices. + * @param Page_Address The page address to be erased. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CTRL |= CTRL_Set_PER; + FLASH->ADD = Page_Address; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CTRL &= CTRL_Reset_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all N32L43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_MassErase(void) +{ + FLASH_STS status = FLASH_COMPL; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= CTRL_Set_MER; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CTRL &= CTRL_Reset_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for N32L43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOB(void) +{ + uint32_t rdptmp = L1_RDP_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdptmp = FLASH_USER_USER; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = (uint32_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the erase status */ + return status; +} + + +/** + * @brief Programs the FLASH User Option Byte: + * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / OB_Data0 / OB_Data1 + * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for N32L43x devices. + * @param OB_RDP1 + * This parameter can be one of the following values: + * @arg OB_RDP1_ENABLE + * @arg OB_RDP1_DISABLE + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @param OB_Data0 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param OB_Data1 + * This parameter can be one of the following values: + * @arg 0x00 ~ 0xFF + * @param WRP_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b N32L43x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages) + * @param OB_RDP2 + * This parameter can be one of the following values: + * @arg OB_RDP2_ENABLE + * @arg OB_RDP2_DISABLE + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2, + uint8_t OB_STDBY, uint8_t OB_Data0, uint8_t OB_Data1, + uint32_t WRP_Pages, uint8_t OB_RDP2, uint8_t OB2_nBOOT0, + uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_RDP1_SOURCE(OB_RDP1)); + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + assert_param(IS_FLASH_WRP_PAGE(WRP_Pages)); + assert_param(IS_OB_RDP2_SOURCE(OB_RDP2)); + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + WRP_Pages = (uint32_t)(~WRP_Pages); + rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY )) << 16)); + data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data1) << 16)); + wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1)); + wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3)); + rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16)); + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Program USER_RDP Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program Data1_Data0 Option Byte value */ + OBT->Data1_Data0 = (uint32_t)data0data1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP1_WRP0 Option Byte value */ + OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program WRP3_WRP2 Option Byte value */ + OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Program USER2_RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + } + } + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for N32L43x devices. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + if((Address & (uint32_t)0x3) != 0) + { + /* The programming address is not a multiple of 4 */ + status = FLASH_ERR_ADD; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to program the new word */ + FLASH->CTRL |= CTRL_Set_PG; + + *(__IO uint32_t*)Address = (uint32_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CTRL &= CTRL_Reset_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for N32L43x devices. + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804. + * @param Data specifies the data to be programmed(Data0 and Data1). + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + *(__IO uint32_t*)Address = (uint32_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for N32L43x devices. + * @param FLASH_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b N32L43x_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63 + * @arg FLASH_WRP_AllPages + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTPG; + + if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF)) + { + OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL)) + { + OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32L43x devices. + * @param Cmd new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + if (Cmd != DISABLE) + { + OBT->USER_RDP = (FLASH_USER_USER & usertmp); + } + else + { + OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection L2. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32L43x devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E); + + /* Get the actual read protection L1 Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() == RESET) + { + usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1); + } + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + OBT->USER_RDP = usertmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Enables the read out protection L2 */ + OBT->USER2_RDP2 = L2_RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for N32L43x devices. + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP2 Reset event when entering STOP2 mode. + * This parameter can be one of the following values: + * @arg OB_STOP2_NORST No reset generated when entering in STOP2 + * @arg OB_STOP2_RST Reset generated when entering in STOP2 + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY) +{ + uint32_t rdpuser_tmp = RDP_USER_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP2_SOURCE(OB_STOP2)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFF00000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = + (uint32_t)rdpuser_tmp + | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY )) << 16); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0]. + * @note This function can be used for N32L43x devices. + * @param OB2_nBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NBOOT0_SET Set nBOOT0 + * @arg OB2_NBOOT0_CLR Clear nBOOT0 + * @param OB2_nBOOT1 + * This parameter can be one of the following values: + * @arg OB2_NBOOT1_SET Set nBOOT1 + * @arg OB2_NBOOT1_CLR Clear nBOOT1 + * @param OB2_nSWBOOT0 + * This parameter can be one of the following values: + * @arg OB2_NSWBOOT0_SET Set nSWBOOT0 + * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0 +* @param OB2_BOR_LEV[2:0] + * This parameter can be one of the following values: + * @arg OB2_BOR_LEV0 + * @arg OB2_BOR_LEV1 + * @arg OB2_BOR_LEV2 + * @arg OB2_BOR_LEV3 + * @arg OB2_BOR_LEV4 + * @arg OB2_BOR_LEV5 + * @arg OB2_BOR_LEV6 + * @arg OB2_BOR_LEV7 + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, + uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV) +{ + uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER); + uint32_t rdp2user2_tmp = 0xFF00FFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0)); + assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1)); + assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0)); + assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdpuser_tmp = 0xFFFF0000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + /* Restore the last RDP1 Option Byte value */ + OBT->USER_RDP = (uint32_t)rdpuser_tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Restore the last RDP2 Option Byte value */ + OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \ + | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for N32L43x devices. + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOB(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OB >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for N32L43x devices. + * @return The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOB(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRP); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for N32L43x devices. + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionSTS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not. + * @note This function can be used for N32L43x devices. + * @return FLASH ReadOut Protection L2 Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionL2STS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for N32L43x devices. + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32L43x devices. + * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2). + */ +FLASH_SMPSEL FLASH_GetSMPSELStatus(void) +{ + FLASH_SMPSEL bitstatus = FLASH_SMP1; + + if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1) + { + bitstatus = FLASH_SMP2; + } + else + { + bitstatus = FLASH_SMP1; + } + /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for N32L43x devices. + * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR FLASH Error Interrupt + * @arg FLASH_INT_FERR EVERR PVERR Interrupt + * @arg FLASH_INT_EOP FLASH end of operation Interrupt + * @param Cmd new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FLASH_INT(FLASH_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CTRL |= FLASH_INT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CTRL &= ~(uint32_t)FLASH_INT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for N32L43x devices. + * @param FLASH_FLAG specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BUSY FLASH Busy flag + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + if (FLASH_FLAG == FLASH_FLAG_OBERR) + { + if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for N32L43x devices. + * @param FLASH_FLAG specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->STS |= FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for N32L43x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_GetSTS(void) +{ + FLASH_STS flashstatus = FLASH_COMPL; + + if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERR_PG; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PVERR) != 0) + { + flashstatus = FLASH_ERR_PV; + } + else + { + if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0) + { + flashstatus = FLASH_ERR_WRP; + } + else + { + if ((FLASH->STS & FLASH_FLAG_EVERR) != 0) + { + flashstatus = FLASH_ERR_EV; + } + else + { + flashstatus = FLASH_COMPL; + } + } + } + } + } + + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for N32L43x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation.. + * @param Timeout FLASH programming Timeout + * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check for the Flash Status */ + status = FLASH_GetSTS(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetSTS(); + Timeout--; + } + if (Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_gpio.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..284b30463db1c25102c5e59f7af30aff01b00a88 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_gpio.c @@ -0,0 +1,768 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_gpio.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_gpio.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @addtogroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- Event control register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +#define GPIO_MODE ((uint32_t)0x00000003) +#define EXTI_MODE ((uint32_t)0x10000000) +#define GPIO_MODE_IT ((uint32_t)0x00010000) +#define GPIO_MODE_EVT ((uint32_t)0x00020000) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300) +#define GPIO_NUMBER ((uint32_t)16) + + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + */ +void GPIO_DeInit(GPIO_Module* GPIOx) +{ + + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + uint32_t GPIO_Pin = GPIO_PIN_ALL; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + /* Check the parameters */ + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + + if (GPIOx == GPIOA) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE); + } + else + { + return; + } + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0) + { + /* Get the IO position */ + iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position); + + if(iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = AFIO->EXTI_CFG[position>>2]; + tmp &= (0x0FuL << (4u*(position & 0x03u))); + if(tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~(iocurrent); + EXTI->EMASK &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~(iocurrent); + EXTI->FT_CFG &= ~(iocurrent); + tmp = 0x0FuL << (4u * (position & 0x03u)); + AFIO->EXTI_CFG[position >> 2u] &= ~tmp; + } + + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + if(position & 0x08) + GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + else + GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + + /* Configure the default value IO Output Type */ + GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U)); + + } + position++; + } +} + + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + */ +void GPIO_AFIOInitDefault(void) +{ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure that + * contains the configuration information for the specified GPIO peripheral. + */ + +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct) +{ + uint32_t pinpos = 0x00U; + uint32_t tmp = 0x00U,tmpregister=0x00U; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull)); + assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + + /*---------------------------- GPIO PL_CFG Configuration ------------------------*/ + + while(((GPIO_InitStruct->Pin)>>position) != 0) + { + iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog)) + { + /* Check if the Alternate function is compliant with the GPIO in use */ + assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate)); + /* Configure Alternate function mapped with the current IO */ + if(position & 0x08) + { + tmp = GPIOx->AFH; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)); + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFH = tmp; + } + else + { + tmp = GPIOx->AFL; + tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ; + GPIOx->AFL = tmp; + } + } + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmpregister = GPIOx->PMODE; + tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |=( tmp << pinpos); + GPIOx->PMODE = tmpregister; + + /* Configure pull-down mode */ + tmpregister = GPIOx->PUPD; + tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03); + tmpregister &=~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp <PUPD = tmpregister; + + + /* Configure driver current*/ + if((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog)) + { + assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current)); + tmpregister = GPIOx->DS; + tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03)); + tmpregister &= ~(((uint32_t)0x03) << pinpos); + tmpregister |= (tmp<DS = tmpregister; + } + /* Configure slew rate*/ + tmp = GPIOx->SR; + tmp &=((uint32_t)(~((uint16_t)0x01 << position))); + tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp; + /*Configure Set/Reset register*/ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down) + { + GPIOx->PBC |= (((uint32_t)0x01) << position); + } + else + { + /* Set the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up) + { + GPIOx->PBSC |= (((uint32_t)0x01) << position); + } + } + + /* In case of Output or Alternate function mode selection */ + if((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) || + (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD)) + { + /* Configure the IO Output Type */ + + tmp= GPIOx->POTYPE; + tmp &= ~(((uint32_t)0x01U) << position) ; + tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->POTYPE = tmp; + } + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if(GPIO_InitStruct->GPIO_Mode & EXTI_MODE) + { + /* Clear EXTI line configuration */ + tmp = EXTI->IMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->IMASK = tmp; + + tmp = EXTI->EMASK; + tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->EMASK = tmp; + + /* Clear Rising Falling edge configuration */ + + tmp = EXTI->RT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->RT_CFG = tmp; + + tmp = EXTI->FT_CFG; + tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE) + { + tmp |= ((uint32_t)0x01 << position); + } + EXTI->FT_CFG = tmp; + } + } + position++; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will + * be initialized. + */ +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = GPIO_PIN_ALL; + GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input; + GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF; + GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull; + GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->PID); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @return GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->POD); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} +void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + // assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBC = Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitCmd specifies the value to be written to the selected bit. + * This parameter can be one of the Bit_OperateType enum values: + * @arg Bit_RESET to clear the port pin + * @arg Bit_SET to set the port pin + */ +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + assert_param(IS_GPIO_BIT_OPERATE(BitCmd)); + + if (BitCmd != Bit_RESET) + { + GPIOx->PBSC = Pin; + } + else + { + GPIOx->PBC = Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param PortVal specifies the value to be written to the port output data register. + */ +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->POD = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx where x can be (A..D) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + tmp |= Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Reset LCKK bit */ + GPIOx->PLOCK = Pin; + /* Set LCKK bit */ + GPIOx->PLOCK = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK; +} + + + +/** + * @brief Changes the mapping of the specified pin. + * @param PortSource selects the GPIO port to be used. + * @param PinSource specifies the pin for the remaping. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param AlternateFunction specifies the alternate function for the remaping. + */ +void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction) +{ + uint32_t tmp = 0x00, tmpregister = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + assert_param(IS_GPIO_AF(AlternateFunction)); + /*Get Peripheral point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + /**/ + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= AlternateFunction << (tmp*4U); + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param PortSource selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t tmpregister = 0x00,tmp = 0x00; + GPIO_Module *GPIOx; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + /*Get Peripheral structure point*/ + GPIOx = GPIO_GET_PERIPH(PortSource); + if(PinSource & (uint8_t)0x08) + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFH register*/ + tmpregister = GPIOx->AFH; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFH register*/ + GPIOx->AFH = tmpregister; + } + else + { + tmp = (uint32_t)(PinSource & (uint8_t)0x07); + /*Read GPIO_AFL register*/ + tmpregister = GPIOx->AFL; + /*Reset corresponding bits*/ + tmpregister &=~((uint32_t)0x0F <<(tmp*4U)); + /*Set corresponding bits*/ + tmpregister |= GPIO_AF3_EVENTOUT; + /*Write to the GPIO_AFL register*/ + GPIOx->AFL = tmpregister; + } +} + +/** + * @brief Enables or disables the Event Output. + * @param Cmd new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + */ +void GPIO_CtrlEventOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd; +} + + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param PortSource selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * @param PinSource specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t port = (uint32_t)PortSource; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u)); + AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u)); +} + +/** + * @brief Selects the alternate function SPIx NSS mode. + * @param AFIO_SPIx_NSS choose which SPI configuration. + * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS. + * @param SpiNssType specifies the SPI_NSS mode to be configured. + * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL. + */ +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS)); + assert_param(IS_AFIO_SPI_NSS(SpiNssType)); + tmp = AFIO->RMP_CFG; + tmp &=(~(0x01U << AFIO_SPIx_NSS)); + tmp |=(SpiNssType << AFIO_SPIx_NSS); + AFIO->RMP_CFG = tmp; +} + +/** + * @brief Configur ADC external trigger. + * @param ADCETRType choose whether to configure rule conversion or injection conversion . + * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR. + * @param ADCTrigRemap specifies the external trigger line be configured. + * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4). + */ +void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETR(ADCETRType)); + if(ADCETRType == AFIO_ADC_ETRI) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRI bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRI)); + /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4) + { + /* select TIM8_CH4 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRI); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<4U)); + tmp |= (ADCTrigRemap<<4U); + } + AFIO->RMP_CFG = tmp; + } + else + { + if(ADCETRType == AFIO_ADC_ETRR) + { + /* Check the parameters */ + assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap)); + tmp = AFIO->RMP_CFG; + /* clear AFIO_RMP_CFG register ETRR bit*/ + tmp &= (~(0x01U << AFIO_ADC_ETRR)); + /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/ + if(ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3) + { + /* select TIM8_CH3 line to connect*/ + tmp |= (0x01U << AFIO_ADC_ETRR); + } + else + { + /* select which external line is connected*/ + tmp &=(~(0x0FU<<0)); + tmp |= ADCTrigRemap; + } + AFIO->RMP_CFG = tmp; + } + } +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_i2c.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..5767a199dd4eeed4ad871aa709300f13789ffa20 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_i2c.c @@ -0,0 +1,1301 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_i2c.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_i2c.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @addtogroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CTRL1_SPEN_SET ((uint16_t)0x0001) +#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTRL1_START_SET ((uint16_t)0x0100) +#define CTRL1_START_RESET ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTRL1_STOP_SET ((uint16_t)0x0200) +#define CTRL1_STOP_RESET ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTRL1_ACK_SET ((uint16_t)0x0400) +#define CTRL1_ACK_RESET ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTRL1_GCEN_SET ((uint16_t)0x0040) +#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTRL1_SWRESET_SET ((uint16_t)0x8000) +#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTRL1_PEC_SET ((uint16_t)0x1000) +#define CTRL1_PEC_RESET ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTRL1_PECEN_SET ((uint16_t)0x0020) +#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTRL1_ARPEN_SET ((uint16_t)0x0010) +#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080) +#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTRL2_DMAEN_SET ((uint16_t)0x0800) +#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTRL2_DMALAST_SET ((uint16_t)0x1000) +#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADDR0_SET ((uint16_t)0x0001) +#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_DUALEN_SET ((uint16_t)0x0001) +#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000) + +/* I2C CHCFG mask */ +#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_MASK ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define INTEN_MASK ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @addtogroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + */ +void I2C_DeInit(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct pointer to a I2C_InitType structure that + * contains the configuration information for the specified I2C peripheral. + */ +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint16_t tmpregister = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksType rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed)); + assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode)); + assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle)); + assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable)); + assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode)); + + /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/ + /* Get the I2Cx CTRL2 value */ + tmpregister = I2Cx->CTRL2; + /* Clear frequency FREQ[5:0] bits */ + tmpregister &= CTRL2_CLKFREQ_RESET; + /* Get pclk1 frequency value */ + RCC_GetClocksFreqValue(&rcc_clocks); + pclk1 = rcc_clocks.Pclk1Freq; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpregister |= freqrange; + /* Write to I2Cx CTRL2 */ + I2Cx->CTRL2 = tmpregister; + + /*---------------------------- I2Cx CHCFG Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TMRISE */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + /* Reset tmpregister value */ + /* Clear F/S, DUTY and CHCFG[11:0] bits */ + tmpregister = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->ClkSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1)); + /* Test if CHCFG value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpregister |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TMRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + // else if((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <= + // 400000)*/ + else + { + if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3)); + } + else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_FMDUTYCYCLE_16_9; + } + + /* Test if CHCFG value is under 0x1*/ + if ((result & CLKCTRL_CLKCTRL_SET) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET); + /* Set Maximum Rise Time for fast mode */ + // if (I2C_InitStruct->ClkSpeed <= 400000) + { + I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + // else//add test + //{ + // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1); + //} + } + /* Write to I2Cx CHCFG */ + I2Cx->CLKCTRL = tmpregister; + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + + /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/ + /* Get the I2Cx CTRL1 value */ + tmpregister = I2Cx->CTRL1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to BusMode value */ + /* Set ACK bit according to AckEnable value */ + tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable); + /* Write to I2Cx CTRL1 */ + I2Cx->CTRL1 = tmpregister; + + /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized. + */ +void I2C_InitStruct(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the ClkSpeed member */ + I2C_InitStruct->ClkSpeed = 5000; + /* Initialize the BusMode member */ + I2C_InitStruct->BusMode = I2C_BUSMODE_I2C; + /* Initialize the FmDutyCycle member */ + I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2; + /* Initialize the OwnAddr1 member */ + I2C_InitStruct->OwnAddr1 = 0; + /* Initialize the AckEnable member */ + I2C_InitStruct->AckEnable = I2C_ACKDIS; + /* Initialize the AddrMode member */ + I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CTRL2 |= CTRL2_DMAEN_SET; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CTRL2 &= CTRL2_DMAEN_RESET; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CTRL2 |= CTRL2_DMALAST_SET; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CTRL2 &= CTRL2_DMALAST_RESET; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL1 |= CTRL1_START_SET; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL1 &= CTRL1_START_RESET; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CTRL1 |= CTRL1_STOP_SET; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CTRL1 &= CTRL1_STOP_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CTRL1 |= CTRL1_ACK_SET; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CTRL1 &= CTRL1_ACK_RESET; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the 7bit I2C own address2. + */ +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address) +{ + uint16_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpregister = I2Cx->OADDR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpregister &= OADDR2_ADDR2_RESET; + + /* Set I2Cx Own address2 */ + tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OADDR2 = tmpregister; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OADDR2 |= OADDR2_DUALEN_SET; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OADDR2 &= OADDR2_DUALEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable generall call */ + I2Cx->CTRL1 |= CTRL1_GCEN_SET; + } + else + { + /* Disable generall call */ + I2Cx->CTRL1 &= CTRL1_GCEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_BUF Buffer interrupt mask + * @arg I2C_INT_EVENT Event interrupt mask + * @arg I2C_INT_ERR Error interrupt mask + * @param Cmd new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_I2C_CFG_INT(I2C_IT)); + + if (Cmd != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CTRL2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CTRL2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Data Byte to be transmitted.. + */ +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Write in the DAT register the data to be sent */ + I2Cx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The value of the received data. + */ +uint8_t I2C_RecvData(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->DAT; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the slave address which will be transmitted + * @param I2C_Direction specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_DIRECTION_SEND Transmitter mode + * @arg I2C_DIRECTION_RECV Receiver mode + */ +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_DIRECTION_SEND) + { + /* Set the address bit0 for read */ + Address |= OADDR1_ADDR0_SET; + } + else + { + /* Reset the address bit0 for write */ + Address &= OADDR1_ADDR0_RESET; + } + /* Send the address */ + I2Cx->DAT = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_REG_CTRL1 CTRL1 register. + * @arg I2C_REG_CTRL2 CTRL2 register. + * @arg I2C_REG_OADDR1 OADDR1 register. + * @arg I2C_REG_OADDR2 OADDR2 register. + * @arg I2C_REG_DAT DAT register. + * @arg I2C_REG_STS1 STS1 register. + * @arg I2C_REG_STS2 STS2 register. + * @arg I2C_REG_CLKCTRL CHCFG register. + * @arg I2C_REG_TMRISE TMRISE register. + * @return The value of the read register. + */ +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_REG(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t*)tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CTRL1 |= CTRL1_SWRESET_SET; + } + else + { + /* Peripheral not under reset */ + I2Cx->CTRL1 &= CTRL1_SWRESET_RESET; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACK_POS_NEXT) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last + * received byte. + * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_ConfigPecLocation() + * but is intended to be used in I2C mode while I2C_ConfigPecLocation() + * is intended to used in SMBUS mode. + * + */ +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POS(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACK_POS_NEXT) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CTRL1 |= I2C_NACK_POS_NEXT; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBALERT_LOW SMBAlert pin driven low + * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high + */ +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBALERT_LOW) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CTRL1 |= I2C_SMBALERT_LOW; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CTRL1 &= I2C_SMBALERT_HIGH; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CTRL1 |= CTRL1_PEC_SET; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CTRL1 &= CTRL1_PEC_RESET; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC + * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_ConfigNackLocation() + * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation() + * is intended to used in I2C mode. + * + */ +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POS(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PEC_POS_NEXT) + { + /* Next byte in shift register is PEC */ + I2Cx->CTRL1 |= I2C_PEC_POS_NEXT; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= CTRL1_PECEN_SET; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= CTRL1_PECEN_RESET; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The PEC value. + */ +uint8_t I2C_GetPec(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->STS2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CTRL1 |= CTRL1_ARPEN_SET; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CTRL1 &= CTRL1_ARPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param FmDutyCycle specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2 + * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9 + */ +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle)); + if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9; + } +} + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlag() function. + * The returned value could be compared to events already defined in the + * library (n32l43x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * n32l43x_i2c.h file. + * + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_DATA_RECVD EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2 + * @arg I2C_EVT_SLAVE_DATA_SENDED EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3 + * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2 + * @arg I2C_EVT_SLAVE_STOP_RECVD EV4 + * @arg I2C_EVT_MASTER_MODE_FLAG EV5 + * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7 + * @arg I2C_EVT_MASTER_DATA_SENDING EV8 + * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2 + * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32l43x_i2c.h file. + * + * @return An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_EVT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32l43x_i2c.h file. + * + * @return The last event + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode) + * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode) + * @arg I2C_FLAG_TRF Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY Bus busy flag + * @arg I2C_FLAG_MSMODE Master/Slave flag + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BYTEF Byte transfer finished flag + * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if (i2creg != 0) + { + /* Get the I2Cx STS1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx STS2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx STS2 register address */ + i2cxbase += 0x18; + } + + if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation + * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the + * second byte of the address in DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetFlag()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 + * register (I2C_GetFlag()) followed by a write operation to I2C_DAT + * register (I2C_SendData()). + */ +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert flag + * @arg I2C_INT_TIMOUT Timeout or Tlow error flag + * @arg I2C_INT_PECERR PEC error in reception flag + * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure flag + * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_INT_BUSERR Bus error flag + * @arg I2C_INT_TXDATE Data register empty flag (Transmitter) + * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_INT_STOPF Stop detection flag (Slave mode) + * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_INT_BYTEF Byte transfer finished flag + * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_INT_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_IT (SET or RESET). + */ +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_INT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2)); + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert interrupt + * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt + * @arg I2C_INT_PECERR PEC error in reception interrupt + * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt + * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode) + * @arg I2C_INT_BUSERR Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second + * byte of the address in I2C_DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_DAT register (I2C_SendData()). + */ +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_INT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_iwdg.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_iwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..2ba0dc5922c5c5bb472d94e49328726b71590fc9 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_iwdg.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_iwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_iwdg.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @addtogroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KEY register bit mask */ +#define KEY_ReloadKey ((uint16_t)0xAAAA) +#define KEY_EnableKey ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers + */ +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE(IWDG_WriteAccess)); + IWDG->KEY = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4 + * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8 + * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16 + * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32 + * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64 + * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128 + * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256 + */ +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler)); + IWDG->PREDIV = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + */ +void IWDG_CntReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RELV = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_ReloadKey(void) +{ + IWDG->KEY = KEY_ReloadKey; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_Enable(void) +{ + IWDG->KEY = KEY_EnableKey; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_PVU_FLAG Prescaler Value Update on going + * @arg IWDG_CRVU_FLAG Reload Value Update on going + * @return The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lcd.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..7c600465460e6a5bf3fedfb899198c703c369f44 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lcd.c @@ -0,0 +1,406 @@ +/***************************************************************************** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* **************************************************************************** +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* Nations' name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ + +/** + * @file n32l43x_lcd.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#include "n32l43x_lcd.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LCD + * @brief LCD driver modules + * @{ + */ + +/** @addtogroup LCD_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LCD_Private_Defines + * @{ + */ + + +/** + * @} + */ + +/** + * @brief Initialize the LCD peripheral according to the specified parameters + * in the LCD_InitStruct. + * @param LCD_InitStructure LCD initialize structure parameters + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure ) +{ + uint32_t tmp, timeout; + + /* Check function parameters */ + assert_param(IS_LCD_BIAS(LCD_InitStructure->Bias)); + assert_param(IS_LCD_BLINKFREQ(LCD_InitStructure->BlinkFreq)); + assert_param(IS_LCD_BLINKMODE(LCD_InitStructure->BlinkMode)); + assert_param(IS_LCD_CONTRASTLEVEL(LCD_InitStructure->Contrast)); + assert_param(IS_LCD_DEADTIME(LCD_InitStructure->DeadTime)); + assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider)); + assert_param(IS_LCD_DUTY(LCD_InitStructure->Duty)); + assert_param(IS_LCD_HIGHDRIVE(LCD_InitStructure->HighDrive)); + assert_param(IS_LCD_HIGHDRIVEBUFFER(LCD_InitStructure->HighDriveBuffer)); + assert_param(IS_LCD_MUXSEGMENT(LCD_InitStructure->MuxSegment)); + assert_param(IS_LCD_PRESCALER(LCD_InitStructure->Prescaler)); + assert_param(IS_LCD_PULSEONDURATION(LCD_InitStructure->PulseOnDuration)); + assert_param(IS_LCD_VOLTAGESOURCE(LCD_InitStructure->VoltageSource)); + + /*Disable LCD controller*/ + __LCD_DISABLE(); + + /*During 1/8 duty mode, 1/4 bias is not supported,use 1/3 bias instead*/ + if(LCD_DUTY_1_8 == LCD_InitStructure->Duty) + { + if(LCD_BIAS_1_4 == LCD_InitStructure->Bias) + LCD_InitStructure->Bias = LCD_BIAS_1_3; + } + + /* set the bits of LCD_CTRL register with corresonding parameters */ + tmp = 0; + tmp |= LCD_InitStructure->HighDriveBuffer; + tmp |= LCD_InitStructure->MuxSegment; + tmp |= LCD_InitStructure->Bias; + tmp |= LCD_InitStructure->Duty; + tmp |= LCD_InitStructure->VoltageSource; + LCD->CTRL = tmp; + + /*If High driver enable, PulseOnDuration must be LCD_PulseOnDuration_1*/ + if(LCD_InitStructure->HighDrive == LCD_HIGHDRIVE_ENABLE) + { + LCD_InitStructure->PulseOnDuration = LCD_PULSEONDURATION_1; + } + + /* set the bits of LCD_FCTRL register with corresonding parameters */ + tmp = 0; + tmp |= LCD_InitStructure->Prescaler; + tmp |= LCD_InitStructure->Divider; + tmp |= LCD_InitStructure->BlinkMode; + tmp |= LCD_InitStructure->BlinkFreq; + tmp |= LCD_InitStructure->Contrast; + tmp |= LCD_InitStructure->DeadTime; + tmp |= LCD_InitStructure->HighDrive; + tmp |= LCD_InitStructure->PulseOnDuration; + LCD->FCTRL = tmp; + + /*Clear LCD display ram, and set the update request flag*/ + LCD_RamClear(); + __LCD_UPDATE_REQUEST(); + + /*Enable LCD controller*/ + __LCD_ENABLE(); + + /*Check the LCD ENSTS status*/ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_ENSTS))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_ENSTS; + } + + /*Wait VLCD stable*/ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_RDY))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_RDY; + } + + return (LCD_WaitForSynchro()); +} + +/** + * @brief DeInitialize the LCD peripheral + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,DISABLE); +} + +/** + * @brief Config the clock source of LCD + * @param LCD_ClkSource specifies the clock source of LCD + * This parameter can be one of the following values: + * @arg LCD_CLK_SRC_LSI: LCD clock source is LSI + * @arg LCD_CLK_SRC_LSE: LCD clock source is LSE,and LSE is oscillator + * @arg LCD_CLK_SRC_LSE_BYPASS: LCD clock source is LSE,and LSE is extennal clock + * @arg LCD_CLK_SRC_HSE_DIV32: LCD clock source is HSE/32,and HSE is oscillator + * @arg LCD_CLK_SRC_HSE_BYPASS_DIV32: LCD clock source is HSE/32,and HSE is extennal clock + * @retval LCD error code + * note: LCD clock is the same with RTC + */ +LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(LCD_CLK_SRC_LSI == LCD_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + if(++timeout >LCD_TIME_OUT) + return LCD_ERROR_CLK; + } + } + else if((LCD_CLK_SRC_LSE==LCD_ClkSource)||(LCD_CLK_SRC_LSE_BYPASS==LCD_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET) + { + RCC_ConfigLse((LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)),0x28); + timeout = 0; + while(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + if(++timeout >LCD_TIME_OUT) + return LCD_ERROR_CLK; + } + } + } + else if((LCD_CLK_SRC_HSE_DIV32==LCD_ClkSource)||(LCD_CLK_SRC_HSE_BYPASS_DIV32==LCD_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF)==RESET) + { + RCC_ConfigHse(LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)); + if(RCC_WaitHseStable()!=SUCCESS) + return LCD_ERROR_CLK; + } + } + else + return LCD_ERROR_PARAM; + + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100; + + /*set LSI as RTC clock source*/ + RCC_ConfigRtcClk(LCD_ClkSource & RCC_LDCTRL_RTCSEL); + + /*Enable RTC clk*/ + RCC_EnableRtcClk(ENABLE); + + /*Enable LCD clk*/ + RCC_EnableRETPeriphClk(RCC_RET_PERIPH_LCD,ENABLE); + + return LCD_ERROR_OK; +} + +/** + * @brief Clear LCD ram register. + * @param None + * @retval None + */ +void LCD_RamClear(void) +{ + uint32_t counter; + + /*Clear lcd ram*/ + for(counter = LCD_RAM1_COM0; counter <= LCD_RAM2_COM7; counter++) + { + LCD->RAM_COM[counter] = 0x0U; + } +} + +/** + * @brief Update Display request. + * @param None + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void) +{ + uint32_t timeout; + + /*Clear UDD flag*/ + __LCD_CLEAR_FLAG(LCD_FLAG_UDD_CLEAR); + + /* set update display request bit*/ + __LCD_UPDATE_REQUEST(); + + /* Wait update complete */ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_UDD))) + { + if(++timeout >= LCD_TIME_OUT) + return LCD_ERROR_UDD; + } + + return LCD_ERROR_OK; +} + +/** + * @brief write to the lcd ram register. + * @param RAMRegisterIndex RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMRegisterMask specifies the LCD RAM Register Data Mask. + * @param RAMData value written to RAM. + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData) +{ + uint32_t timeout; + + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + MODIFY_REG(LCD->RAM_COM[RAMRegisterIndex], ~(RAMRegisterMask), RAMData &(~(RAMRegisterMask))); + + return LCD_ERROR_OK; + +} + +/** + * @brief set some bits of lcd ram register. + * @param RAMRegisterIndex: RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMData: value to be set + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData) +{ + uint32_t timeout; + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + SET_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData); + return LCD_ERROR_OK; +} + +/** + * @brief clear some bits of lcd ram register. + * @param RAMRegisterIndex: RAM register index, + * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2). + * @param RAMData: value to be clear + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData) +{ + uint32_t timeout; + /* Check function parameters */ + assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex)); + + if(RAMRegisterIndex > LCD_RAM2_COM7) + return LCD_ERROR_PARAM; + + /* Wait VLCD request flag clear */ + timeout = 0; + while(__LCD_GET_FLAG(LCD_FLAG_UDR)) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_UDR; + } + } + + /* Write lcd RAMData */ + CLEAR_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData); + return LCD_ERROR_OK; +} + + +/** + * @brief Wait until the LCD FCTRL register is synchronized in the LCDCLK domain. + * This function must be called after any write operation to LCD_FCTRL register. + * @param RAMData: None + * @retval LCD error code + */ +LCD_ErrorTypeDef LCD_WaitForSynchro(void) +{ + uint32_t timeout; + + /* Loop until FCRSF flag is set */ + timeout = 0; + while(RESET == (__LCD_GET_FLAG(LCD_FLAG_FCRSF))) + { + if(++timeout >= LCD_TIME_OUT) + { + return LCD_ERROR_FCRSF; + } + } + + return LCD_ERROR_OK; +} + +/** +* @} +*/ +/** +* @} +*/ + + + diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c new file mode 100644 index 0000000000000000000000000000000000000000..5fd9406f600d6765919c3ca6f1e674120020bf75 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c @@ -0,0 +1,891 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* + * ----------------------------------------------------------------------------- + */ + +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32l43x_LPRCNT.c + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "n32l43x_LPRCNT.h" +//nclude "n32l43x_rcc.h" +//#include "n32l43x.h" +#include "n32l43x_exti.h" +#include "misc.h" +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @defgroup LPRCNT + * @brief LPRCNT driver modules + * @{ + */ + +/** @defgroup LPRCNT_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** + * @brief clear LPRCNT interrupt flag funtion. + * @param intflag: include LPRCNT interrupt flag + * This parameter can be one of the following values: + * @arg CALIBRATION_INT_FLAG + * @arg REPORT_INT_FLAG + * @arg ALARM_INT_FLAG + * @retval None + */ +void LPRCNT_ClrIntBit(uint32_t IntFlag) +{ + LPRCNT->INTSTS |= IntFlag; +} + +/** + * @brief Checks whether the specified LPRCNT interrupt has occurred or not. + * @param LPRCNT_INT specifies the LPRCNT interrupt source to check. + * This parameter can be one of the following values: + * @arg CALIBRATION_INT_FLAG Calibration mode damped oscillation interrupt. + * @arg REPORT_INT_FLAG Report interrupt. + * @arg ALARM_INT_FLAG Alarm interrupt . + * @return The new state of LPRCNT_INT (SET or RESET). + */ +INTStatus LPRCNT_GetIntSts(uint32_t Int) +{ + INTStatus bitstatus = RESET; + uint32_t Temp = 0; + + Temp = LPRCNT->INTSTS ; + Temp &= 0x00070000; + if(Temp == Int) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; + +} +/** + * @brief LPRCNT interrupt funtion. + * @param MODE_IE: include LPRCNT interrupt + * This parameter can be one of the following values: + * @arg CALIBRATION_INT + * @arg REPORT_INT + * @arg ALARM_INT + * @param NewState: open or disable + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +void LPRCNT_IntEn(uint32_t Mode ,FunctionalState NewState) +{ + if(NewState == ENABLE) + { + LPRCNT->CTRL |= Mode; + } + else + { + LPRCNT->CTRL &= ~Mode; + } +} +/** + * @brief configure per channel sensor detection time. + * @param ch: sensor channel . + * @param vibrationtime: comparator processing duration time. + * @param dischargetime: discharge duration time. + * @param chargetime: power charge duration time. + * @retval None + */ +void CfgChannelTime(uint8_t Ch,uint8_t VibrationTime ,uint8_t DischargeTime,uint8_t ChargeTime ) +{ + uint32_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = LPRCNT->CH0CFG1; + Temp &= CLEAR_TIME_VALE; + Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime)); + LPRCNT->CH0CFG1 = Temp; + break; + case CHANNEL_1 : + Temp = LPRCNT->CH1CFG1; + Temp &= CLEAR_TIME_VALE; + Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime)); + LPRCNT->CH1CFG1 = Temp; + break; + case CHANNEL_2 : + Temp = LPRCNT->CH2CFG1; + Temp &= CLEAR_TIME_VALE; + Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime)); + LPRCNT->CH2CFG1 = Temp; + break; + default: break ; + } +} + +/** + * @brief get the comparator processing duration time. + * @param ch: sensor channel . + * @retval duration time + */ +uint8_t GetVibrationTime(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = (LPRCNT->CH0CFG1 >> 16); + break; + case CHANNEL_1 : + Temp = (LPRCNT->CH1CFG1 >> 16); + break; + case CHANNEL_2 : + Temp = (LPRCNT->CH2CFG1 >> 16); + break; + } + return Temp; +} +/** + * @brief get discharge duration time. + * @param ch: sensor channel . + * @retval discharge duration time + */ +uint8_t GetDischargeTime(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = ((LPRCNT->CH0CFG1 >> 8) & 0x3f); + break; + case CHANNEL_1 : + Temp = ((LPRCNT->CH1CFG1 >> 8) & 0x3f); + break; + case CHANNEL_2 : + Temp = ((LPRCNT->CH2CFG1 >> 8) & 0x3f); + break; + } + return Temp; +} +/** + * @brief get charge duration time. + * @param ch: sensor channel . + * @retval charge duration time + */ +uint8_t GetChargeTime(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = (LPRCNT->CH0CFG1 & 0x3f); + break; + case CHANNEL_1 : + Temp = (LPRCNT->CH1CFG1 & 0x3f); + break; + case CHANNEL_2 : + Temp = (LPRCNT->CH2CFG1 & 0x3f); + break; + } + return Temp; +} +/** + * @brief configure per channel sensor detection threshold. + * @param ch: sensor channel . + * @param dacreference: DAC reference value for comparator. + * @retval None + */ +void CfgChannelDacRefVol(uint8_t Ch,uint8_t DacRef) +{ + uint32_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = LPRCNT->CH0CFG0; + Temp &= (~LPRCNT_CH0CFG0_DACREF); + Temp |= (uint32_t)(DacRef <<16); + LPRCNT->CH0CFG0 = Temp; + break; + case CHANNEL_1 : + Temp = LPRCNT->CH1CFG0; + Temp &= (~LPRCNT_CH1CFG0_DACREF); + Temp |= (uint32_t)(DacRef <<16); + LPRCNT->CH1CFG0 = Temp; + break; + case CHANNEL_2 : + Temp = LPRCNT->CH2CFG0; + Temp &= (~LPRCNT_CH2CFG0_DACREF); + Temp |= (uint32_t)(DacRef <<16); + LPRCNT->CH2CFG0 = Temp; + break; + default: + break ; + } + +} +/** + * @brief get the DAC reference voltage. + * @param ch: sensor channel . + * @retval DAC reference voltage values,Temp <= 64 + */ +uint8_t GetDacRefVol(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = ((LPRCNT->CH0CFG0 >> 16) & 0x3f); + break; + case CHANNEL_1 : + Temp = ((LPRCNT->CH1CFG0 >> 16) & 0x3f); + break; + case CHANNEL_2 : + Temp = ((LPRCNT->CH2CFG0 >> 16) & 0x3f); + break; + } + return Temp; +} + +/** + * @brief configure per channel sensor detection threshold. + * @param ch: sensor channel . + * @param undampedTh: undamped threshold. + * @param dampedTh: damped threshold. + * @retval None + */ +void CfgChannelThr(uint8_t Ch, uint8_t UndampedTh, uint8_t DampedTh) +{ + uint32_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = LPRCNT->CH0CFG0; + Temp &= CLEAR_TH_VALE; + Temp |= (uint32_t)((UndampedTh <<8) | DampedTh); + LPRCNT->CH0CFG0 = Temp; + break; + case CHANNEL_1 : + Temp = LPRCNT->CH1CFG0; + Temp &= CLEAR_TH_VALE; + Temp |= (uint32_t)((UndampedTh <<8) | DampedTh); + LPRCNT->CH1CFG0 = Temp; + break; + case CHANNEL_2 : + Temp = LPRCNT->CH2CFG0; + Temp &= CLEAR_TH_VALE; + Temp |= (uint32_t)((UndampedTh <<8) | DampedTh); + LPRCNT->CH2CFG0 = Temp; + break; + default: break ; + } +} + +/** + * @brief get undamped threshold. + * @param ch: sensor channel . + * @retval undamped threshold. + */ +uint8_t GetUndampedTh(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = (LPRCNT->CH0CFG0 >> 8); + break; + case CHANNEL_1 : + Temp = (LPRCNT->CH1CFG0 >> 8); + break; + case CHANNEL_2 : + Temp = (LPRCNT->CH2CFG0 >> 8); + break; + } + return Temp; +} +/** + * @brief get damped threshold. + * @param ch: sensor channel . + * @retval damped threshold. + */ +uint8_t GetDampedTh(uint8_t Ch) +{ + uint8_t Temp = 0; + switch (Ch) + { + case CHANNEL_0 : + Temp = (LPRCNT->CH0CFG0); + break; + case CHANNEL_1 : + Temp = (LPRCNT->CH1CFG0); + break; + case CHANNEL_2 : + Temp = (LPRCNT->CH2CFG0); + break; + } + return Temp; +} +/** + * @brief MSI clock prescale. + * @param div: division factor + * This parameter can be one of the following values: + * @arg LPRCNT_PRESCALER_DIV1 + * @arg LPRCNT_PRESCALER_DIV2 + * @arg LPRCNT_PRESCALER_DIV4 + * @arg LPRCNT_PRESCALER_DIV8 + * @retval None + */ +void SetMsiClkPrescale(uint32_t Div) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_CLKDIV); + Temp |= Div; + LPRCNT->CTRL = Temp; +} + +/** + * @brief get the Circle value . + * @param ch: there are three state mode + * This parameter can be one of the following values: + * @retval the ratation Circle value + */ + +uint16_t GetRotationCircle(void) +{ + uint16_t Temp; + Temp = (uint16_t)LPRCNT->INTSTS; + return Temp ; + +} +/** + * @brief get the user set circle value . + * This parameter can be one of the following values: + * @retval the set ratation Circle value + */ + +uint16_t GetSetRcnt(void) +{ + uint16_t Temp; + Temp = (uint16_t)LPRCNT->CTRL; + return Temp ; +} +/** + * @brief clear the RCNT circle. + * @param None + * @retval None + */ +void ClrRcntCircle(void) +{ + uint32_t Temp; + Temp = LPRCNT->CMD; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CMD_CLRCNT); + Temp |= LPRCNT_CMD_CLRCNT; + LPRCNT->CMD = Temp; +} +/** + * @brief when the setting number is reach ,it is will creat a overflow interrupt. + * @param Circle: the rotating Circle number + * @retval None + */ +void SetAutoReportCircle(uint16_t Circle) +{ + uint32_t Temp = 0; + uint16_t Cnt = 0; + //when set the circle numbers,need add the lase numbers + Cnt = GetRotationCircle(); + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_RPTTH); + Temp |= (uint32_t)(Circle + Cnt); + LPRCNT->CTRL = Temp; + +} +#if 0 +/** + * @brief when the setting number is reach ,it is will creat a overflow interrupt. + * @param Circle: the rotating Circle number + * @retval None + */ +void SetAutoReportCircle(uint16_t Circle) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_RPTTH); + Temp |= (uint32_t)Circle; + LPRCNT->CTRL = Temp; +} +#endif +/** + * @brief enable to auto detect comparator stop. + * @param CMD: ENABLE or DISABLE + * @retval None + */ +void SetAutoDetectEnale(FunctionalState NewState ) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_CMPAUT); + Temp |= (uint32_t)(NewState <<23); + LPRCNT->CTRL = Temp; +} +/** + * @brief set auto detect comparator stop need wait period. + * @param per: AUTODETPERIOD4 or AUTODETPERIOD8 + * @retval None + */ +void SetAutoDetectPeriod(bool per) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CAL3; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CAL3_CMP_AUTO_MODE); + Temp |= (uint32_t)(per <<6); + LPRCNT->CAL3 = Temp; +} +/** + * @brief set auto to charge by DAC. + * @param En: ENABLE or DISABLE + * @retval None + */ +void SetPwrAutoCharge(bool En) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CAL3; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CAL3_PWR_DUR_EN); + Temp |= (uint32_t)(En <<7); + LPRCNT->CAL3 = Temp; +} +/** + * @brief After seveval rounds of scanning , it is necessary to take the average . + * @param n: the scanning times , times = 2^n + * @retval None + */ +void SetScanAverageValue(uint8_t N) +{ + uint32_t Temp = 0; + if (N <= 3) + { + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_AVGSEL); + Temp |= (uint32_t)(N << 18); + LPRCNT->CTRL = Temp; + } +} +/** + * @brief SetVibrationPower. + * @param value: the damped vibration power select. + * This parameter can be one of the following values: + * @arg POWERSELECT1V5 + * @arg POWERSELECT1V65 + * @arg POWERSELECT1V8 + * @arg POWERSELECT2V0 + * @retval None + */ +void SetVibrationPower(uint8_t Value) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_PWRLVL); + Temp |= (uint32_t)(Value << 21); + LPRCNT->CTRL = Temp; +} + +/** + * @brief configure normal sensor scan frequence. + * @param low_speed: if the rotating object does not move for a long time ,it will enter into low speed . + * @param hight_speed: In other cases, MCU keep in hight speed to detect rotation. + * @param swtich_time: the time interval about hight speed swtich to low speed. + * @retval None + */ +void SetNormalSensorScanfrequence(uint16_t Low_speed,uint8_t Hight_speed,uint8_t Swtich_time) +{ + uint32_t Temp = 0; + Temp = LPRCNT->SCTRL; + //clear the bit that need add new vale + Temp &= 0xfc000000; + Temp |= (uint32_t)((Low_speed <<16) | (Swtich_time <<8) | (Hight_speed)); + LPRCNT->SCTRL = Temp; +} +/** + * @brief get normal sensor low speed values. + * @retval low speed values + */ +uint16_t GetNormalSensorLowSpeed(void) +{ + uint16_t Temp = 0; + Temp = (uint16_t)((LPRCNT->SCTRL >> 16) & 0x03ff); + return Temp; +} +/** + * @brief get normal sensor hight speed values. + * @retval hight speed values + */ +uint8_t GetNormalSensorHightSpeed(void) +{ + uint8_t Temp = 0; + Temp = (uint8_t)(LPRCNT->SCTRL); + return Temp; +} +/** + * @brief get normal sensor swtich time. + * @retval swtich time values + */ +uint8_t GetNormalSensorSwtichTime(void) +{ + uint8_t Temp = 0; + Temp = (uint8_t)(LPRCNT->SCTRL >> 8); + return Temp; +} +/** + * @brief SetAlarmSensorScanfrequence. + * @param the frequence is several times than the normal sensor . + * This parameter can be one of the following values: + * @arg FRETIME4 + * @arg FRETIME8 + * @arg FRETIME16 + * @arg FRETIME32 + * @retval None + */ +void SetAlarmSensorScanfrequence(uint8_t Period) +{ + uint32_t Temp = 0; + Temp = LPRCNT->CTRL; + //clear the bit that need add new vale + Temp &= (~LPRCNT_CTRL_ALMPRD); + Temp |= (uint32_t)(Period <<26); + LPRCNT->CTRL = Temp; +} +/** + * @brief set LPRCNT module CMD . + * @param command . + * This parameter can be one of the following values: + * @retval None + */ +//void LPRCNTModeEnable(uint8_t Cmd) +//{ +// LPRCNT->CMD |= (uint32_t)Cmd; +// +//} +/** + * @brief Read lprcnt Start state . + * @param void . + * @retval 0 or 1 + */ +bool ReadStartState(void) +{ + bool temp; + temp = LPRCNT->CMD; + return temp ; +} + +/** + * @brief After the comparator , the square waves can be got for each channel . + * @param ch: there are in total three sensor.The frequence of the three sensors is staggered, + * so the number of square waves will be different. + * @retval the waves number + */ +uint8_t GetChannelSensorWavesNum(uint8_t Ch) +{ + uint8_t Temp =0; + if (Ch == CHANNEL_0) + { + Temp = (LPRCNT->CAL0 & 0x000000ff); + return Temp; + } + else if(Ch == CHANNEL_1) + { + Temp =((LPRCNT->CAL0 & 0x00ff0000)>> 16); + return Temp; + } + else + { + Temp = (LPRCNT->CAL1 & 0x000000ff); + return Temp; + } +} + +/** + * @brief Through the threshold value judgment,per channel can redefine as the state mode . + * @param ch: there are three state mode + * This parameter can be one of the following values: + * @arg 0: undamped + * @arg 1: middle state + * @arg 2: damped + * @retval the state value + */ +uint8_t GetChannelSensorState(uint8_t Ch) +{ + if(Ch == CHANNEL_0) + { + return ((uint8_t)((LPRCNT->CAL0 >> 8) & 0x3)); + } + else if(Ch == CHANNEL_1) + { + return ((uint8_t)((LPRCNT->CAL0 >> 24) & 0x3)); + } + else if(Ch == CHANNEL_2) + { + return ((uint8_t)((LPRCNT->CAL1 >> 8) & 0x3)); + } + else + { + return CHANNEL_ERROR;//channel error + } +} + +/** + * @brief get the sample mode . + * @param ch: there are three state mode + * This parameter can be one of the following values: + * @retval the ratation Circle value + */ +uint8_t GetSampleMode(void) +{ + uint8_t Temp; + Temp = (uint8_t)((LPRCNT->CAL2 >> 25) & 0x01); + return Temp ; +} +/** + * @brief LPRCNT module can work in two mode.this is LPRCNT mode and calibration mode . + * @param mode: working mode . + * This parameter can be one of the following values: + * @arg 0: calibration mode , for calibration rotation object parameters + * @arg 1: LPRCNT mode, the mode can detect the Circle of rotation + * @retval None + */ +//void SetLPRCNTWorkMode(uint8_t mode)//װһ +//{ +// LPRCNT->CTRL |= (uint32_t)(mode << 24); +//} + +/** + * @brief LPRCNT COMP Init. + * @param COMP_InitStruct. + * This parameter can be one of the following values: + * LPRCNT_COMP_InitType + * @retval None + */ +void LPRCNT_CompInit(LPRCNT_COMP_InitType* COMP_InitStruct) +{ + uint32_t Temp ; + Temp = LPRCNT->CAL3; + //clear the bits about COMP hysteresis + Temp &= (~LPRCNT_CAL3_CMP_HYSEL); + Temp |= COMP_InitStruct->Hyst; + //clear input minus selection bits + Temp &= (~LPRCNT_CAL3_CMP_INMSEL); + Temp |= COMP_InitStruct->InmSel; + //COMP low power enable + Temp |= COMP_InitStruct->LowPoweMode; + LPRCNT->CAL3 = Temp; +} + +/** + * @brief DigitalfilterConfig. +* @param cmd:enable or disable. +* @param filterTh:Filter threshold control. + * This parameter can be one of the following values: + * CMP_FILTH_MODE0 : T/2~T + * CMP_FILTH_MODE1 : T~3T/2 + * CMP_FILTH_MODE2 : 3T/2~2T + * @retval None + */ +void CompDigitalFilterCfg(bool Cmd, uint32_t FilterThr) +{ + uint32_t Temp ; + Temp = LPRCNT->CAL3; + //clear FILTH bit + Temp &= (~LPRCNT_CAL3_FILTH); + Temp |= FilterThr; + LPRCNT->CAL3 = Temp; + if (Cmd == ENABLE) + { + LPRCNT->CAL3 |= LPRCNT_CAL3_DIGFILEN; + } + else + { + LPRCNT->CAL3 &= (~LPRCNT_CAL3_DIGFILEN); + } +} +/** + * @brief COMPDigitalfilterEnable. + * @param cmd:ENABLE or DISABLE. + * @retval None + */ +void CompAnalogFilterEn(bool Cmd) +{ + if (Cmd == ENABLE) + { + LPRCNT->CAL3 |= LPRCNT_CAL3_ANGFILEN; + } + else + { + LPRCNT->CAL3 &= (~LPRCNT_CAL3_ANGFILEN); + } +} + +/** + * @brief Digital filter phase control. + * @param direction:P or N. + * @retval None + */ +void CompDigitalFilterPhase(bool dir) +{ + uint32_t Temp ; + Temp = LPRCNT->CAL3; + Temp &= (~LPRCNT_CAL3_DIGFILPH); + if (dir == POPH) + { + Temp |= LPRCNT_CAL3_DIGFILPH_P; + LPRCNT->CAL3 = Temp; + } + else + { + Temp |= LPRCNT_CAL3_DIGFILPH_N; + LPRCNT->CAL3 = Temp; + } +} + + +/** + * @brief DAC & CMP always on enable while 1 round sampling. + * @param NewState:ENABLE or DISABLE. + * @retval None + */ +void DAC_CMP_ALWSONCmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the selected LPRCNT AlwaysONhardware auto turn on MSI clock */ + LPRCNT->CAL3 |= LPRCNT_CAL3_DAC_CMP_ALWSON; + RCC_EnableMsi(DISABLE); + } + else + { + /* Disable the selected LPRCNT stop */ + LPRCNT->CAL3 &= ~LPRCNT_CAL3_DAC_CMP_ALWSON; + } +} +/** + * @brief LPRCNT analog filter,include gated values and phases. + * @param None + * @retval None + */ +void LPRCNTAnalogFilterConfig(void) +{ + SetAnalogFilterTh(1); + CompAnalogFilterPhase(POPH); + CompAnalogFilterEn(ENABLE); +} +/** + * @brief LPRCNT module Init. + * @param LPRCNT are ready to run . + * This parameter can be one of the following values: + * @arg 0: LPRCNT_InitStruct , for init rotation object parameters + * @retval None + */ +void LPRCNTInit(LPRCNT_InitType* LPRCNT_InitStruct) +{ + //clock and charge voltage + SetMsiClkPrescale(LPRCNT_InitStruct->PrescaleDiv); + SetVibrationPower(LPRCNT_InitStruct->ChargeVol); + //SetPwrAutoCharge(ENABLE); + //DAC_CMP_ALWSONCmd(ENABLE); + //sensor time paragram + CfgChannelTime(CHANNEL_0,LPRCNT_InitStruct->ChTime[0].vibrationtime,LPRCNT_InitStruct->ChTime[0].dischargetime,LPRCNT_InitStruct->ChTime[0].chargetime); + CfgChannelTime(CHANNEL_1,LPRCNT_InitStruct->ChTime[1].vibrationtime,LPRCNT_InitStruct->ChTime[1].dischargetime,LPRCNT_InitStruct->ChTime[1].chargetime); + CfgChannelTime(CHANNEL_2,LPRCNT_InitStruct->ChTime[2].vibrationtime,LPRCNT_InitStruct->ChTime[2].dischargetime,LPRCNT_InitStruct->ChTime[2].chargetime); + //sensor state paragram + CfgChannelThr(CHANNEL_0,LPRCNT_InitStruct->ChTH[0].undampedTh,LPRCNT_InitStruct->ChTH[0].dampedTh); + CfgChannelDacRefVol(CHANNEL_0,LPRCNT_InitStruct->ChTH[0].dacreference); + CfgChannelThr(CHANNEL_1,LPRCNT_InitStruct->ChTH[1].undampedTh,LPRCNT_InitStruct->ChTH[1].dampedTh); + CfgChannelDacRefVol(CHANNEL_1,LPRCNT_InitStruct->ChTH[1].dacreference); + CfgChannelThr(CHANNEL_2,LPRCNT_InitStruct->ChTH[2].undampedTh,LPRCNT_InitStruct->ChTH[2].dampedTh); + CfgChannelDacRefVol(CHANNEL_2,LPRCNT_InitStruct->ChTH[2].dacreference); + SetNormalSensorScanfrequence(LPRCNT_InitStruct->NormalFreq.low_speed,LPRCNT_InitStruct->NormalFreq.hight_speed,LPRCNT_InitStruct->NormalFreq.swtich_time); + SetScanAverageValue(0);//default 0 + //scan period + SetNormalSensorScanfrequence(LPRCNT_InitStruct->NormalFreq.low_speed,LPRCNT_InitStruct->NormalFreq.hight_speed,LPRCNT_InitStruct->NormalFreq.swtich_time); + SetAlarmSensorScanfrequence(LPRCNT_InitStruct->AlarmFreq); + SetAutoDetectPeriod(LPRCNT_InitStruct->AutoWaitPer); + SetAutoDetectEnale(LPRCNT_InitStruct->AutoDetEn); + //setup time funtion + DacSetupTimeConfig(); + CompSetupTimeConfig(); + //ChargeAndDischargeGap(5); + ClrRcntCircle(); + SetAutoReportCircle(LPRCNT_InitStruct->Circle); + LPRCNTAnalogFilterConfig();//default to select the analog filter + SetLPRCNTWorkMode(LPRCNT_InitStruct->WorkMode); + //interruput + LPRCNT_ClrIntBit(LPRCNT_INTSTS_RPTIF); + LPRCNT_IntEn(LPRCNT_InitStruct->Int,LPRCNT_InitStruct->IntEn); +} + + + +/** + * @} + */ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ + diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lptim.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lptim.c new file mode 100644 index 0000000000000000000000000000000000000000..cfb49699cb1c43f5485bf1e5a1b12a98745c7bf8 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lptim.c @@ -0,0 +1,1258 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2022, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* + * ----------------------------------------------------------------------------- + */ + +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file n32l43x_lptim.c + * @author + * @date + * @version V1.2.1 + * @brief + ******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "n32l43x_lptim.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @defgroup LPTIM + * @brief LPTIM driver modules + * @{ + */ + +/** @defgroup LPTIM_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ +//#define LPTIM +//#if defined (LPTIM)//LPTIM + +/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +void LPTIM_DeInit(LPTIM_Module* LPTIMx) +{ + if (LPTIMx == LPTIM) + { + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE); + } +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval None + */ +void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM; + LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + + /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFG, + (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note + * @retval None + */ +void LPTIM_Disable(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_Enable(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LPTIM_StartCounter\n + * CR SNGSTRT LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode); +} + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag be set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CMP register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMPOK flag be set, will + * lead to unpredictable results. + * @rmtoll CMP CMP LPTIM_SetCompare + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CMP CMP LPTIM_GetCompare + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL + */ +uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN)); +} + +/** + * @brief Configure the LPTIM instance output (LPTIMx_OUT) + * @note This function must be called when the LPTIM instance is disabled. + * @note Regarding the LPTIM output polarity the change takes effect + * immediately, so the output default value will change immediately after + * the polarity is re-configured, even before the timer is enabled. + * @rmtoll CFG WAVE LPTIM_ConfigOutput\n + * CFG WAVPOL LPTIM_ConfigOutput + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity); +} + +/** + * @brief Set waveform shape + * @rmtoll CFG WAVE LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFG WAVE LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE)); +} + +/** + * @brief Set output polarity + * @rmtoll CFG WAVPOL LPTIM_SetPolarity + * @param LPTIMx Low-Power Timer instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity); +} + +/** + * @brief Get actual output polarity + * @rmtoll CFG WAVPOL LPTIM_GetPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE + */ +uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL)); +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFG PRESC LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + * @retval None + */ +void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFG PRESC LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_PRESCALER_DIV1 + * @arg @ref LPTIM_PRESCALER_DIV2 + * @arg @ref LPTIM_PRESCALER_DIV4 + * @arg @ref LPTIM_PRESCALER_DIV8 + * @arg @ref LPTIM_PRESCALER_DIV16 + * @arg @ref LPTIM_PRESCALER_DIV32 + * @arg @ref LPTIM_PRESCALER_DIV64 + * @arg @ref LPTIM_PRESCALER_DIV128 + */ +uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFG TIMOUT LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFG TIMOUT LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG TRIGEN LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_TrigSw(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n + * CFG TRGFLT LPTIM_ConfigTrigger\n + * CFG TRIGEN LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + * @param Filter This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*) + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LPTIM_TRIG_SOURCE_COMP2 + * + * (*) Value not defined in all devices. \n + * + */ +uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_FILTER_NONE + * @arg @ref LPTIM_TRIG_FILTER_2 + * @arg @ref LPTIM_TRIG_FILTER_4 + * @arg @ref LPTIM_TRIG_FILTER_8 + */ +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_TRIG_POLARITY_RISING + * @arg @ref LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKSEL LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFG CKSEL LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL + */ +uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFG CKFLT LPTIM_ConfigClock\n + * CFG CKPOL LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFG CKPOL LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_POLARITY_RISING + * @arg @ref LPTIM_CLK_POLARITY_FALLING + * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING + */ +uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFG CKFLT LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_CLK_FILTER_NONE + * @arg @ref LPTIM_CLK_FILTER_2 + * @arg @ref LPTIM_CLK_FILTER_4 + * @arg @ref LPTIM_CLK_FILTER_8 + */ +uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG CKPOL LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFG CKPOL LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LPTIM_ENCODER_MODE_RISING + * @arg @ref LPTIM_ENCODER_MODE_FALLING + * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING + */ +uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFG ENC LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC); +} +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFG ENC LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag (CMPMCF) + * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF); +} + +/** + * @brief Inform application whether a compare match interrupt has occurred. + * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occured. + * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMPOKCF). + * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR UP LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Disable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE); +} + +/** + * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. + * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. + * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx) +{ + return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx) +{ + SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx) +{ + CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx) +{ + return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL); +} + +/** + * @} + */ + + +//#endif /* LPTIM */ + +/** + * @} + */ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ + diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lpuart.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lpuart.c new file mode 100644 index 0000000000000000000000000000000000000000..732a03d277171074b02529a0337ccb3d4af23bd5 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_lpuart.c @@ -0,0 +1,536 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_lpuart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_lpuart.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LPUART + * @brief LPUART driver modules + * @{ + */ + +/** @addtogroup LPUART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Defines + * @{ + */ + +#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */ + +#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */ +#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */ + +#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */ +#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */ +#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */ +#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */ +#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */ +#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */ +#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */ +#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */ +#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the LPUART peripheral registers to their default reset values. + */ +void LPUART_DeInit(void) +{ + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE); + RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE); +} + +/** + * @brief Initializes the LPUART peripheral according to the specified + * parameters in the LPUART_InitStruct. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * that contains the configuration information for the specified LPUART + * peripheral. + */ +void LPUART_Init(LPUART_InitType* LPUART_InitStruct) +{ + uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00; + RCC_ClocksType RCC_ClocksStatus; + + /* Check the parameters */ + // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode)); + assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold)); + assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl)); + + // 时钟源判断，波特率范围 + + /*---------------------------- LPUART CTRL Configuration -----------------------*/ + tmpregister = LPUART->CTRL; + /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */ + tmpregister &= CTRL_CLR_MASK; + /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */ + /* Set PCDIS and PSEL bits according to Parity value */ + /* Set the TRS bit according to Mode */ + /* Set RTS_THSEL[1:0] bits according to RtsThrehold */ + /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */ + tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl; + /* Write to LPUART CTRL */ + LPUART->CTRL = (uint16_t)tmpregister; + + /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/ + /* Configure the LPUART Baud Rate -------------------------------------------*/ + clocksrc = RCC_GetLPUARTClkSrc(); + if (clocksrc == RCC_LPUARTCLK_SRC_LSE) + { + apbclock = 0x8000; // 32.768kHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_HSI) + { + apbclock = 0xF42400; // 16MHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.SysclkFreq; + } + else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1) + { + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = apbclock / (LPUART_InitStruct->BaudRate); + + /* Configure sampling method */ + if(integerdivider <= 10) + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B); + } + else + { + LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B); + } + + /* Check baudrate */ + assert_param(IS_LPUART_BAUDRATE(integerdivider)); + /* Write to LPUART BRCFG1 */ + LPUART->BRCFG1 = (uint16_t)integerdivider; + + /* Determine the fractional part */ + fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate); + + tmpregister = 0x00; + tmpdivider = fractionaldivider; + /* Implement the fractional part in the register */ + for( i = 0; i < 8; i++) + { + lastdivider = tmpdivider; + tmpdivider = lastdivider + fractionaldivider; + if((tmpdivider / 10000) ^ (lastdivider / 10000)) + { + tmpregister |= (0x01 << i); + } + } + /* Write to LPUART BRCFG2 */ + LPUART->BRCFG2 = (uint8_t)tmpregister; +} + +/** + * @brief Fills each LPUART_InitStruct member with its default value. + * @param LPUART_InitStruct pointer to a LPUART_InitType structure + * which will be initialized. + */ +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct) +{ + /* LPUART_InitStruct members default value */ + LPUART_InitStruct->BaudRate = 9600; + LPUART_InitStruct->Parity = LPUART_PE_NO; + LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX; + LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU; + LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE; +} + +/** + * @brief Flushes Receiver FIFO. + */ +void LPUART_FlushRxFifo(void) +{ + /* Clear LPUART Flush Receiver FIFO */ + LPUART->CTRL |= CTRL_FLUSH_SET; + while(LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET) + { + } + LPUART->CTRL &= CTRL_FLUSH_RESET; +} + +/** + * @brief Enables or disables the specified LPUART interrupts. + * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @param Cmd new state of the specified LPUART interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CFG_INT(LPUART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + LPUART->INTEN |= (uint8_t)LPUART_INT; + } + else + { + LPUART->INTEN &= (uint8_t)(~LPUART_INT); + } +} + +/** + * @brief Enables or disables the LPUART's DMA interface. + * @param LPUART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg LPUART_DMAREQ_TX LPUART DMA transmit request + * @arg LPUART_DMAREQ_RX LPUART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL |= LPUART_DMAReq; + } + else + { + /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq); + } +} + +/** + * @brief Selects the LPUART WakeUp method. + * @param LPUART_WakeUpMethod specifies the LPUART wakeup method. + * This parameter can be one of the following values: + * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection + * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection + * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte + * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame + */ +void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod)); + + LPUART->CTRL &= CTRL_WUSTP_MASK; + LPUART->CTRL |= LPUART_WakeUpMethod; +} + +/** + * @brief Enables or disables LPUART Wakeup in STOP2 mode. + * @param Cmd new state of the LPUART Wakeup in STOP2 mode. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableWakeUpStop(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */ + LPUART->CTRL |= CTRL_WUSTP_SET; + } + else + { + /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */ + LPUART->CTRL &= CTRL_WUSTP_RESET; + } +} + +/** + * @brief Selects the LPUART Sampling method. + * @param LPUART_SamplingMethod specifies the LPAURT sampling method. + * This parameter can be one of the following values: + * @arg LPUART_SMPCNT_3B 3 Sample bit + * @arg LPUART_SMPCNT_1B 1 Sample bit + */ +void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod) +{ + /* Check the parameters */ + assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod)); + + LPUART->CTRL &= CTRL_SMPCNT_MASK; + LPUART->CTRL |= LPUART_SamplingMethod; +} + +/** + * @brief Enables or disables LPUART Loop Back Self-Test. + * @param Cmd new state of the LPUART Loop Back Self-Test. + * This parameter can be: ENABLE or DISABLE. + */ +void LPUART_EnableLoopBack(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */ + LPUART->CTRL |= CTRL_LOOPBACK_SET; + } + else + { + /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */ + LPUART->CTRL &= CTRL_LOOPBACK_RESET; + } +} + +/** + * @brief Transmits single data through the LPUART peripheral. + * @param Data the data to transmit. + */ +void LPUART_SendData(uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_LPUART_DATA(Data)); + + /* Transmit Data */ + LPUART->DAT = (Data & (uint8_t)0xFF); +} + +/** + * @brief Returns the most recent received data by the LPUART peripheral. + * @return The received data. + */ +uint8_t LPUART_ReceiveData(void) +{ + /* Receive Data */ + return (uint8_t)(LPUART->DAT & (uint8_t)0xFF); +} + +/** + * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode. + * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode. + */ +void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData) +{ + LPUART->WUDAT = LPUART_WakeUpData; +} + +/** + * @brief Checks whether the specified LPUART flag is set or not. + * @param LPUART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + * @return The new state of LPUART_FLAG (SET or RESET). + */ +FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_FLAG(LPUART_FLAG)); + + if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the LPUART's pending flags. + * @param LPUART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LPUART_FLAG_PEF Parity Check Error Flag. + * @arg LPUART_FLAG_TXC TX Complete Flag. + * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag. + * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag. + * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag. + * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag. + * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. + * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag. + * @arg LPUART_FLAG_NF Noise Detection Flag. + */ +void LPUART_ClrFlag(uint16_t LPUART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG)); + + LPUART->STS = (uint16_t)LPUART_FLAG; +} + +/** + * @brief Checks whether the specified LPUART interrupt has occurred or not. + * @param LPUART_INT specifies the LPUART interrupt source to check. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + * @return The new state of LPUART_INT (SET or RESET). + */ +INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_LPUART_GET_INT(LPUART_INT)); + + /* Get the interrupt position */ + itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + itmask &= LPUART->INTEN; + + bitpos = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT){ + bitpos = (bitpos << 0x01); + } + bitpos &= LPUART->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the LPUART's interrupt pending bits. + * @param LPUART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg LPUART_INT_WUF Wake-Up Interrupt + * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt + * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt + * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable + * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt + * @arg LPUART_INT_TXC TX Complete Interrupt + * @arg LPUART_INT_PE Parity Check Error Interrupt + */ +void LPUART_ClrIntPendingBit(uint16_t LPUART_INT) +{ + uint16_t itmask = 0x00; + /* Check the parameters */ + assert_param(IS_LPUART_CLR_INT(LPUART_INT)); + + itmask = ((uint8_t)LPUART_INT) & 0xFF; + if(LPUART_INT_WUF == LPUART_INT) + { + itmask = (itmask << 0x01); + } + LPUART->STS = (uint16_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_opamp.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_opamp.c new file mode 100644 index 0000000000000000000000000000000000000000..f28fe0fa6e3fec34b893ce9be2feead27dd57eb8 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_opamp.c @@ -0,0 +1,198 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_opamp.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_opamp.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @brief OPAMP driver modules + * @{ + */ + +/** @addtogroup OPAMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the OPAMP peripheral registers to their default reset values. + */ +void OPAMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE); +} +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct) +{ + OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6; + OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2; + OPAMP_InitStruct->HighVolRangeEn = ENABLE; + OPAMP_InitStruct->TimeAutoMuxEn = DISABLE; + OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN; +} +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + if(OPAMPx == OPAMP2) + SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL); + SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK); + if(OPAMP_InitStruct->HighVolRangeEn==ENABLE) + SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK); + else + ClrBit(tmp,OPAMP_CS_RANGE_MASK); + if(OPAMP_InitStruct->TimeAutoMuxEn==ENABLE) + SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK); + else + ClrBit(tmp,OPAMP_CS_TCMEN_MASK); + SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK); + *pCs = tmp; +} +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_EN_MASK); + else + ClrBit(*pCs, OPAMP_CS_EN_MASK); +} + +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK); + *pCs = tmp; +} +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false; +} +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_CALON_MASK); + else + ClrBit(*pCs, OPAMP_CS_CALON_MASK); +} +// Lock see @OPAMP_LOCK +void OPAMP_SetLock(uint32_t Lock) +{ + OPAMP->LOCK = Lock; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_pwr.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_pwr.c new file mode 100644 index 0000000000000000000000000000000000000000..4d62fbeaeffcb1cb09469402e1556cbabaeb9460 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_pwr.c @@ -0,0 +1,547 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_pwr.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_pwr.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @addtogroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of DBKP bit */ +#define CTRL_OFFSET (PWR_OFFSET + 0x00) +#define DBKP_BITN 0x08 +#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4)) + +/* Alias word address of PVDEN bit */ +#define PVDEN_BITN 0x04 +#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of WKUPEN bit */ +#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04) +#define WKUPEN_BITN 0x08 +#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + + +void SetSysClock_MSI(void); +/** + * @} + */ + +/** @addtogroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + */ +void PWR_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param Cmd new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_BackupAccessEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd; +} + +/** + * @brief MR voltage selection. + * @param voltage value: 1.0V and 1.1V. + * This parameter can be: MR_1V0 or MR_1V1. + */ +void PWR_MRconfig(uint8_t voltage) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTRL1; + /* Clear MRSEL bits */ + tmpreg &= (~PWR_CTRL1_MRSELMASK); + /* Set voltage*/ + tmpreg |= (uint32_t)(voltage << 9); + PWR->CTRL1 = tmpreg; +} + +/** + * @brief Get MR voltage value. + * @param voltage value: 1.0V and 1.1V. + * @return The value of voltage. + */ +uint8_t GetMrVoltage(void) +{ + uint8_t tmp = 0; + /* 2bits */ + tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03); + return tmp ; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param Cmd new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_PvdEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Can not enable the PVD bit */ + //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; + PWR->CTRL2 |= Cmd; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V + * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V + * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V + * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V + * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V + * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V + * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V + * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT) + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpregister = PWR->CTRL2; + /* Clear PLS[7:5] bits */ + tmpregister &= (~PWR_CTRL2_PLSMASK); + /* Set PRS[7:5] bits according to PWR_PVDLevel value */ + tmpregister |= PWR_PVDLevel; + /* Store the new value */ + PWR->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param Pin: which PIN select to wakeup. + * This parameter can be one of the following values: + * @arg WAKEUP_PIN0 + * @arg WAKEUP_PIN1 + * @arg WAKEUP_PIN2 + * @param Cmd new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd) +{ + uint32_t Temp = 0; + Temp = PWR->CTRL3; + if(ENABLE==Cmd) + { + Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN)); + Temp |= (WKUP_Pin); + PWR->CTRL3 = Temp; + } + else + { + Temp &= (~(WKUP_Pin)); + PWR->CTRL3 = Temp; + } +} + +/** + * @brief Enters SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + /* CLEAR SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); + /* Select SLEEPONEXIT mode entry --------------------------------------------------*/ + if(SLEEPONEXIT == 1) + { + /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } + else if(SLEEPONEXIT == 0) + { + /* Sleep-now */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT); + } + /* Select SLEEP mode entry --------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP2 mode. + * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction + * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET + */ +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + /* Wait MR Voltage Adjust Complete */ + while((PWR->STS2 &0X2) != 2); + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= RetentionMode; + PWR->CTRL3 = tmpreg; + /* Select the regulator state in STOP2 mode ---------------------------------*/ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set stop2 mode select */ + tmpreg |= PWR_CTRL1_STOP2; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters Low power run mode. + * @param + * @arg + * @arg + * @retval None + */ +void PWR_EnterLowPowerRunMode(void) +{ + uint32_t tmpreg = 0; + SetSysClock_MSI(); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + /* config FLASH enter the low power voltage mode */ + FLASH->AC |= FLASH_AC_LVMEN; + while((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + _SetLprunSramVoltage(0); + _SetBandGapMode(0); + _SetPvdBorMode(0); + /* Select the regulator state in LPRUN mode */ + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Set lpr to run the main power domain */ + tmpreg |= PWR_CTRL1_LPREN; + /* Store the new value */ + PWR->CTRL1 = tmpreg; + /* LPRCNT flag ready */ + while((PWR->STS2 &PWR_STS2_LPRUNF) != 0); +} + +/** + * @brief Enters Low power run mode. + * @retval None + */ +void PWR_ExitLowPowerRunMode(void) +{ + PWR->CTRL1 &= ~PWR_CTRL1_LPREN; + _SetLprunSwitch(3); + while((PWR->STS2 &PWR_STS2_MRF) != PWR_STS2_MRF); + while((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF); + FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed + FLASH->AC &= ~FLASH_AC_LVMEN; //clear LVMREQ + while((FLASH->AC &FLASH_AC_LVMF) != 0); //wait LVE is deasserted by polling the LVMVLD bit + _SetPvdBorMode(1); + _SetBandGapMode(1); + _SetLprunSramVoltage(1); + FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time. + _SetLprunSwitch(2); + while((PWR->STS2 &0X2) != 0) // wait MF to be 0 first + { + } + while((PWR->STS2 &0X2) != 2) // wait MF to be 1 then + { + } +} + +/** + * @brief Enters LP_SLEEP mode. + * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0: SLEEP mode with SLEEPONEXIT disable + * @arg 1: SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + PWR_EnterLowPowerRunMode(); + PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry); +} + + /** + * @brief Enters STANDBY mode. + * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction + * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention + * @retval None + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret) +{ + uint32_t tmpreg; + /* Clear Wake-up flag */ + PWR->STSCLR |= PWR_STSCLR_CLRWKUP0; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP1; + PWR->STSCLR |= PWR_STSCLR_CLRWKUP2; + tmpreg = PWR->CTRL3; + /* Clear SRAMRET bits */ + tmpreg &= (~PWR_CTRL3_RAMRETMASK); + /* Set SRAM1/2 select */ + tmpreg |= Sam2Ret; + PWR->CTRL3 = tmpreg; + tmpreg = PWR->CTRL1; + /* Clear LPMS bits */ + tmpreg &= (~PWR_CTRL1_LPMSELMASK); + /* Select STANDBY mode */ + tmpreg |= PWR_CTRL1_STANDBY; + PWR->CTRL1 = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + /* This option is used to ensure that store operations are completed */ + #if defined (__CC_ARM) + __force_stores(); + #endif + /* Select STANDBY mode entry */ + if(PWR_STANDBYEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + * @arg PWR_LPRUN_FLAG: low power work flag + * @arg PWR_MR_FLAG: MR work statue flag + * @arg PWR_PVDO_FLAG: PVD output flag + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + if(STS == 1) + { + if((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag + * @arg PWR_STBY_FLAG: StandBy flag + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + PWR->STSCLR |= PWR_FLAG ; +} + +/** + * @brief set system clock with MSI. + * @param void. + */ +void SetSysClock_MSI(void) +{ + RCC_DeInit(); + if(RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD)) + { + /* Enable MSI and Config Clock */ + RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M); + /* Waits for MSI start-up */ + while(SUCCESS != RCC_WaitMsiStable()); + } + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN); + /* Select MSI as system clock source */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI); + /* Wait till MSI is used as system clock source */ + while (RCC_GetSysclkSrc() != 0x00) + { + } + /* Flash 0 wait state */ + //FLASH_SetLatency(FLASH_LATENCY_0); + /* HCLK = SYSCLK */ + RCC_ConfigHclk(RCC_SYSCLK_DIV1); + /* PCLK2 = HCLK */ + RCC_ConfigPclk2(RCC_HCLK_DIV1); + /* PCLK1 = HCLK */ + RCC_ConfigPclk1(RCC_HCLK_DIV1); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rcc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rcc.c new file mode 100644 index 0000000000000000000000000000000000000000..75bb537d27b59cf0c36a00af49b1695b36518235 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rcc.c @@ -0,0 +1,1887 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_rcc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_rcc.h" + +/** @addtogroup N32L43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @addtogroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of HSIEN bit */ +#define CTRL_OFFSET (RCC_OFFSET + 0x00) +#define HSIEN_BITN 0x00 +#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4)) + +/* Alias word address of PLLEN bit */ +#define PLLEN_BITN 0x18 +#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4)) + +/* Alias word address of CLKSSEN bit */ +#define CLKSSEN_BITN 0x13 +#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4)) + +/* --- CFG Register ---*/ + +/* Alias word address of USBPRES bit */ +#define CFG_OFFSET (RCC_OFFSET + 0x04) + +#define USBPRES_BITN 0x16 +#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4)) + +#define USBPRE_Bit1Number 0x17 +#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4)) + +/* --- CLKINT Register ---*/ + +#define CLKINT_OFFSET (RCC_OFFSET + 0x08) + +/* Alias word address of LSIRDIF bit */ +#define LSIRDIF_BITN 0x00 +#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4)) + +/* --- LDCTRL Register ---*/ + +/* Alias word address of LSECLKSSEN bit */ +#define LSECLKSSEN_BITN 0x03 +#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4)) + +/* Alias word address of RTCEN bit */ +#define LDCTRL_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BITN 0x0F +#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4)) + +/* Alias word address of LDSFTRST bit */ +#define LDSFTRST_BITN 0x10 +#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of LSIEN bit */ +#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24) +#define LSIEN_BITNUMBER 0x00 +#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4)) + +/* Alias word address of MSIEN bit */ +#define MSIEN_BITNUMBER 0x02 +#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF) +#define CTRL_HSEBP_SET ((uint32_t)0x00040000) +#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF) +#define CTRL_HSEEN_SET ((uint32_t)0x00010000) +#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83) +#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE) +#define CTRL_HSIEN_SET ((uint32_t)0x00000001) + +/* CTRLSTS register bit mask */ +#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF) +#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB) +#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004) + +#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F) +#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */ + +/* CFG register bit mask */ +#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF) + +#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000) +#define CFG_PLLSRC_MASK ((uint32_t)0x00010000) +#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000) +#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C) +#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC) +#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F) +#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0) +#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF) +#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700) +#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF) +#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800) + +/* CFG2 register bit mask */ +#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000) +#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF) +#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000) +#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF) +#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000) +#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF) +#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000) +#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF) +#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0) +#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F) +#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F) +#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0) + +/* CFG3 register bit mask */ +#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) + +/* CTRLSTS register bit mask */ +#define CSR_RMRSTF_SET ((uint32_t)0x01000000) +#define CSR_RMVF_Reset ((uint32_t)0xfeffffff) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CLKINT register(Bits[31:0]) base address */ +#define CLKINT_ADDR ((uint32_t)0x40021008) + +/* LDCTRL register base address */ +#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET) + +/* RDCTRL register bit mask */ +#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007) +#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018) + +/* PLLHSIPRE register bit mask */ +#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001) +#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002) + +#define LSE_TRIMR_ADDR ((uint32_t)0x40001808) + +#define LSE_GM_MASK_VALUE (0x1FF) +#define LSE_GM_MAX_VALUE (0x1FF) +#define LSE_GM_DEFAULT_VALUE (0x1FF) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Variables + * @{ + */ + +static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32}; +static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256}; +static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3, + MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6}; + +/** + * @} + */ + +/** @addtogroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + */ +void RCC_DeInit(void) +{ + /* Set MSIEN bit */ + RCC->CTRLSTS |= (uint32_t)0x00000004; + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFE; + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */ + RCC->CFG &= (uint32_t)0xF700FFFF; + /* Reset CFG2 register */ + RCC->CFG2 = 0x00007000; + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + /* Reset RDCTRL register */ + RCC->RDCTRL = 0x00000000; + /* Reset PLLHSIPRE register */ + RCC->PLLHSIPRE = 0x00000000; + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x04BF8000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_DISABLE HSE oscillator OFF + * @arg RCC_HSE_ENABLE HSE oscillator ON + * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +void RCC_ConfigHse(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CTRL &= CTRL_HSEEN_RESET; + /* Reset HSEBYP bit */ + RCC->CTRL &= CTRL_HSEBP_RESET; + /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */ + switch (RCC_HSE) + { + case RCC_HSE_ENABLE: + /* Set HSEEN bit */ + RCC->CTRL |= CTRL_HSEEN_SET; + break; + case RCC_HSE_BYPASS: + /* Set HSEBYP and HSEEN bits */ + RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET; + break; + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitHseStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF); + StartUpCounter++; + } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Configures the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSI specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_DISABLE HSI oscillator OFF + * @arg RCC_HSI_ENABLE HSI oscillator ON + */ +void RCC_ConfigHsi(uint32_t RCC_HSI) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_HSI)); + /* Reset HSIEN bit */ + RCC->CTRL &= CTRL_HSIEN_RESET; + /* Configure HSI */ + switch (RCC_HSI) + { + case RCC_HSI_ENABLE: + /* Set HSIEN bit */ + RCC->CTRL |= CTRL_HSIEN_SET; + break; + default: + break; + } +} + +/** + * @brief Waits for HSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSI oscillator is stable and ready to use + * - ERROR: HSI oscillator not yet ready + */ +ErrorStatus RCC_WaitHsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSIStatus = RESET; + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF); + StartUpCounter++; + } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET)); + if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue)); + tmpregister = RCC->CTRL; + /* Clear HSITRIM[4:0] bits */ + tmpregister &= CTRL_HSITRIM_MASK; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpregister |= (uint32_t)HSICalibrationValue << 2; + /* Store the new value */ + RCC->CTRL = tmpregister; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableHsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the Multi Speed oscillator (MSI). + * @param RCC_MSI specifies the new state of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_DISABLE MSI oscillator OFF + * @arg RCC_MSI_ENABLE MSI oscillator ON + * @param RCC_MSI_Range specifies the clock of the MSI. + * This parameter can be one of the following values: + * @arg RCC_MSI_RANGE_100K 100KHz + * @arg RCC_MSI_RANGE_200K 200KHz + * @arg RCC_MSI_RANGE_400K 400KHz + * @arg RCC_MSI_RANGE_800K 800KHz + * @arg RCC_MSI_RANGE_1M 1MHz + * @arg RCC_MSI_RANGE_2M 2MHz + * @arg RCC_MSI_RANGE_4M 4MHz + */ +void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range) +{ + /* Check the parameters */ + assert_param(IS_RCC_MSI(RCC_MSI)); + assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range)); + /* Set MSIRANGE[2:0] bit */ + RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK; + RCC->CTRLSTS |= RCC_MSI_Range; + /* Configure MSI */ + switch (RCC_MSI) + { + case RCC_MSI_ENABLE: + /* Set MSIEN bit */ + RCC->CTRLSTS |= CTRLSTS_MSIEN_SET; + break; + case RCC_MSI_DISABLE: + /* Reset MSIEN bit */ + RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET; + break; + default: + break; + } +} + +/** + * @brief Waits for MSI start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: MSI oscillator is stable and ready to use + * - ERROR: MSI oscillator not yet ready + */ +ErrorStatus RCC_WaitMsiStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus MSIStatus = RESET; + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD); + StartUpCounter++; + } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET)); + if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Multi Speed oscillator (MSI) calibration value. + * @param MSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0xFF. + */ +void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue)); + tmpregister = RCC->CTRLSTS; + /* Clear MSITRIM[7:0] bits */ + tmpregister &= CTRLSTS_MSITRIM_MASK; + /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */ + tmpregister |= (uint32_t)MSICalibrationValue << 15; + /* Store the new value */ + RCC->CTRLSTS = tmpregister; +} + +/** + * @brief Enables or disables the Multi Speed oscillator (MSI). + * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableMsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource specifies the PLL entry clock source. + * this parameter can be one of the following values: + * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul specifies the PLL multiplication factor. + * this parameter can be RCC_PLLMul_x where x:[2,32] + * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source. + * this parameter can be one of the following values: + * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry + * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry + */ +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK) +{ + uint32_t tmpregister = 0; + uint32_t pllhsipreregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_PLL_SRC(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK)); + tmpregister = RCC->CFG; + pllhsipreregister = RCC->PLLHSIPRE; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */ + tmpregister &= CFG_PLL_MASK; + /* Clear PLLHSIPRE, PLLSRCDIV bits */ + pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK)); + /* Set the PLL configuration bits */ + if((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2)) + { + tmpregister |= RCC_PLLMul; + pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK; + } + /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */ + else + { + tmpregister |= RCC_PLLSource | RCC_PLLMul; + pllhsipreregister |= RCC_PLLDIVCLK; + } + /* Store the new value */ + RCC->CFG = tmpregister; + RCC->PLLHSIPRE = pllhsipreregister; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnablePll(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock + * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock + */ +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource)); + tmpregister = RCC->CFG; + /* Clear SW[1:0] bits */ + tmpregister &= CFG_SCLKSW_MASK; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpregister |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Returns the clock source used as system clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: MSI used as system clock + * - 0x04: HSI used as system clock + * - 0x08: HSE used as system clock + * - 0x0C: PLL used as system clock + */ +uint8_t RCC_GetSysclkSrc(void) +{ + return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK + * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512 + */ +void RCC_ConfigHclk(uint32_t RCC_SYSCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK)); + tmpregister = RCC->CFG; + /* Clear HPRE[3:0] bits */ + tmpregister &= CFG_AHBPRES_RESET_MASK; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpregister |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB1 clock = HCLK + * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16 + */ +void RCC_ConfigPclk1(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE1[2:0] bits */ + tmpregister &= CFG_APB1PRES_RESET_MASK; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB2 clock = HCLK + * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16 + */ +void RCC_ConfigPclk2(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE2[2:0] bits */ + tmpregister &= CFG_APB2PRES_RESET_MASK; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RccInt specifies the RCC interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF BOR interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * + * @param Cmd new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_INT(RccInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8); + } + else + { + /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */ + *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8)); + } +} + +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source + */ +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource)); + *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource; + *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1; +} + +/** + * @brief Configures the TIM1/8 clock (TIM1/8CLK). + * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM18CLK_SRC_TIM18CLK + * @arg RCC_TIM18CLK_SRC_SYSCLK + */ +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource)); + tmpregister = RCC->CFG2; + /* Clear TIMCLK_SEL bits */ + tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK; + /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */ + tmpregister |= RCC_TIM18CLKSource; + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the RNGCCLK prescaler. + * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler. + * This parameter can be one of the following values: + * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1 + * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2 + * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3 + * ... + * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31 + * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32 + */ +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler)); + tmpregister = RCC->CFG2; + /* Clear RNGCPRE[3:0] bits */ + tmpregister &= CFG2_RNGCPRES_RESET_MASK; + /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */ + tmpregister |= RCC_RNGCCLKPrescaler; + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCx 1M clock (ADC1MCLK). + * @param RCC_ADC1MCLKSource specifies the ADC1M clock source. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_SRC_HSI + * @arg RCC_ADC1MCLK_SRC_HSE + * + * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1 + * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2 + * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3 + * ... + * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31 + * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32 + */ +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource)); + assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler)); + tmpregister = RCC->CFG2; + /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */ + tmpregister &= CFG2_ADC1MSEL_RESET_MASK; + tmpregister &= CFG2_ADC1MPRES_RESET_MASK; + /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */ + tmpregister |= RCC_ADC1MCLKSource; + /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */ + tmpregister |= RCC_ADC1MPrescaler; + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK. + * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + * + * @param Cmd specifies the ADCPLLCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable ADCPLLCLK + * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + */ +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmpregister = RCC->CFG2; + /* Clear ADCPLLPRES[4:0] bits */ + tmpregister &= CFG2_ADCPLLPRES_RESET_MASK; + if (Cmd != DISABLE) + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + } + else + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + tmpregister &= RCC_ADCPLLCLK_DISABLE; + } + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + */ +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler)); + tmpregister = RCC->CFG2; + /* Clear ADCHPRE[3:0] bits */ + tmpregister &= CFG2_ADCHPRES_RESET_MASK; + /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_ADCHCLKPrescaler; + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the TRNG 1M clock (TRNG1MCLK). + * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_SRC_HSI + * @arg RCC_TRNG1MCLK_SRC_HSE + * + * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2 + * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4 + * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6 + * ... + * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60 + * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62 + */ +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource)); + assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler)); + tmpregister = RCC->CFG3; + /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */ + tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK; + tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK; + /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */ + tmpregister |= RCC_TRNG1MCLKSource; + /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */ + tmpregister |= RCC_TRNG1MPrescaler; + /* Store the new value */ + RCC->CFG3 = tmpregister; +} + +/** + * @brief Enable/disable TRNG clock (TRNGCLK). + * @param Cmd specifies the TRNGCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable TRNGCLK + * @arg DISABLE disable TRNGCLK + */ +void RCC_EnableTrng1mClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE; + } + else + { + RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE; + } +} + +/** + * @brief Configures the UCDR clock. + * @param RCC_UCDR300MSource specifies the UCDR clock source. + * This parameter can be on of the following values: + * @arg RCC_UCDR300M_SRC_OSC300M + * @arg RCC_UCDR300M_SRC_PLLVCO + * + * @param Cmd enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable UCDR + * @arg DISABLE disable UCDR + */ +void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmpregister = RCC->CFG3; + /* Clear UCDR300MSEL bits */ + tmpregister &= RCC_UCDR300MSource_MASK; + /* Set UCDR300MSEL bits */ + tmpregister |= RCC_UCDR300MSource; + /* Store the new value */ + RCC->CFG3 = tmpregister; + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_UCDR_ENABLE; + } + else + { + RCC->CFG3 &= RCC_UCDR_DISABLE; + } +} + +/** + * @brief Configures the USB Crystal Mode. + * @param RCC_USBXTALESSMode specifies the USB Crystal Mode. + * This parameter can be one of the following values: + * @arg RCC_USBXTALESS_MODE USB work in crystal mode + * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode + */ +void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode)); + /* Clear the USB Crystal Mode bit */ + RCC->CFG3 &= RCC_USBXTALESSMode_MASK; + /* Select the USB Crystal Mode */ + RCC->CFG3 |= RCC_USBXTALESSMode; +} + +/** + * @brief Enables or disables the RET peripheral clock. + * @param RCC_RETPeriph specifies the RET peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM + * @arg RCC_RET_PERIPH_LPUART + * @arg RCC_RET_PERIPH_LCD + * @arg RCC_RET_PERIPH_LPRCNT + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->RDCTRL |= RCC_RETPeriph; + } + else + { + RCC->RDCTRL &= ~RCC_RETPeriph; + } +} + +/** + * @brief Forces or releases RET peripheral reset. + * @param RCC_RETPeriph specifies the RET peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_RET_PERIPH_LPTIM. + * RCC_RET_PERIPH_LPUART. + * RCC_RET_PERIPH_LCD. + * RCC_RET_PERIPH_LPRCNT. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->RDCTRL |= (RCC_RETPeriph << 4); + } + else + { + RCC->RDCTRL &= ~(RCC_RETPeriph << 4); + } +} + +/** + * @brief Configures the LPTIM clock (LPTIMCLK). + * @param RCC_LPTIMCLKSource specifies the LPTIM clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + * @note When switching from comparator1/2 to other clock sources, + * it is suggested to disable comparators first. + */ +void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource)); + //PWR DBP set 1 + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Clear the LPTIM clock source */ + RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK; + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPTIMCLKSource; +} + +/** + * @brief Returns the clock source used as LPTIM clock (LPTIMCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock + * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock + */ +uint32_t RCC_GetLPTIMClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK)); +} + +/** + * @brief Configures the LPUART clock (LPUARTCLK). + * @param RCC_LPUARTCLKSource specifies the LPUART clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock + * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock + */ +void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource)); + /* Clear the LPUART clock source */ + RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK; + /* Select the LPTIM clock source */ + RCC->RDCTRL |= RCC_LPUARTCLKSource; +} + +/** + * @brief Returns the clock source used as LPUART clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock + * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock + */ +uint32_t RCC_GetLPUARTClkSrc(void) +{ + return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK)); +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error interrupts. + * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt + * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt + * + * @param Cmd new state of the specified SRAM1/2 parity error interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORINT(SramErrorInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS |= SramErrorInt; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */ + RCC->SRAM_CTRLSTS &= (~SramErrorInt); + } +} + +/** + * @brief Enables or disables the specified SRAM1/2 parity error reset. + * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset + * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset + * + * @param Cmd new state of the specified SRAM1/2 parity error reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS |= SramErrorReset; + } + else + { + /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */ + RCC->SRAM_CTRLSTS &= (~SramErrorReset); + } +} + +/** + * @brief Clears the specified SRAM1/2 parity error flag. + * @param SramErrorReset specifies the SRAM1/2 parity error flag. + * + * this parameter can be any combination of the following values + * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag + * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag + */ +void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag) +{ + /* Check the parameters */ + assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag)); + RCC->SRAM_CTRLSTS |= SramErrorflag; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) Xtal bias. + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x0~0x1FF + */ +void LSE_XtalConfig(uint16_t LSE_Trim) +{ + uint32_t tmpregister = 0; + tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR; + //clear lse trim[8:0] + tmpregister &= (~(LSE_GM_MASK_VALUE)); + (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE); + tmpregister |= LSE_Trim; + *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_DISABLE LSE oscillator OFF + * @arg RCC_LSE_ENABLE LSE oscillator ON + * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock + * @param LSE_Trim specifies LSE Driver Trim Level. + * Trim value rang 0x00~0x1FF + */ +void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim) +{ + uint32_t LDCTRL_Value; + uint32_t i=0; + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* PWR DBP set 1 Enable PWR Clock */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE); + PWR->CTRL1 |= 0x100; + /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE*/ + LDCTRL_Value = *(__IO uint32_t*)LDCTRL_ADDR; + LDCTRL_Value &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN)); + /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ENABLE: + /* Set LSEON bit */ + LDCTRL_Value |= RCC_LSE_ENABLE; + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + LSE_XtalConfig(LSE_Trim); + break; + case RCC_LSE_DISABLE: + /* Reset LSEON bit */ + LDCTRL_Value &= (~RCC_LSE_DISABLE); + *(__IO uint32_t*)LDCTRL_ADDR =LDCTRL_Value ; + /*Delay for 3 LSE Clock Wait for LSERD bit Reset*/ + for(i=0;i<0x7FF;i++); + break; + case RCC_LSE_BYPASS: + /* Set LSEBYP and LSEON bits */ + LDCTRL_Value |= RCC_LSE_BYPASS; + *(__IO uint32_t*)LDCTRL_ADDR = LDCTRL_Value; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock + */ +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource)); + /* Clear the RTC clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL); + /* Select the RTC clock source */ + RCC->LDCTRL |= RCC_RTCCLKSource; +} + +/** + * @brief Returns the clock source used as RTC clock (RTCCLK). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK) + * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK) + */ +uint32_t RCC_GetRTCClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL)); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function. + * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRtcClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the LSX clock (for TSC/LPRCNT). + * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock + * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock + */ +void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource)); + /* Clear the LSX clock source */ + RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL); + /* Select the LSX clock source */ + RCC->LDCTRL |= RCC_LSXCLKSource; +} + +/** + * @brief Returns the clock source used as LSX clock (for TSC/LPRCNT). + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC/LPRCNT) + * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC/LPRCNT) + */ +uint32_t RCC_GetLSXClkSrc(void) +{ + return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL)); +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks) +{ + uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0; + uint8_t msi_clk = 0; + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFG & CFG_PLLMULFCT_MASK; + pllsource = RCC->CFG & CFG_PLLSRC_MASK; + /* Get MSI clock --------------------------------------------------------*/ + msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4); + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + if (pllsource == 0x00) + { + /* HSI selected as PLL clock entry */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET) + { /* HSI oscillator clock divided by 2 */ + pllclk = (HSI_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSI_VALUE * pllmull; + } + + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + pllclk = (HSE_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSE_VALUE * pllmull; + } + } + /* PLL Div clock */ + if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET) + { /* PLL clock divided by 2 */ + pllclk = (pllclk >> 1); + } + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFG & CFG_SCLKSTS_MASK; + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + case 0x04: /* HSI used as system clock */ + RCC_Clocks->SysclkFreq = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + RCC_Clocks->SysclkFreq = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + RCC_Clocks->SysclkFreq = pllclk; + break; + default: + RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk]; + break; + } + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFG & CFG_AHBPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_ApbAhbPresTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFG & CFG_APB1PRES_SET_MASK; + tmp = tmp >> 8; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFG & CFG_APB2PRES_SET_MASK; + tmp = tmp >> 11; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc; + /* Get ADCHCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK; + presc = s_AdcHclkPresTable[tmp]; + /* ADCHCLK clock frequency */ + RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc; + /* Get ADCPLLCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5 + /* ADCPLLCLK clock frequency */ + RCC_Clocks->AdcPllClkFreq = pllclk / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_DMA + * @arg RCC_AHB_PERIPH_SRAM + * @arg RCC_AHB_PERIPH_FLITF + * @arg RCC_AHB_PERIPH_CRC + * @arg RCC_AHB_PERIPH_RNGC + * @arg RCC_AHB_PERIPH_SAC + * @arg RCC_AHB_PERIPH_ADC + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->AHBPCLKEN |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCLKEN &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PCLKEN |= RCC_APB2Periph; + } + else + { + RCC->APB2PCLKEN &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PCLKEN |= RCC_APB1Periph; + } + else + { + RCC->APB1PCLKEN &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_ADC. + * RCC_AHB_PERIPH_SAC. + * RCC_AHB_PERIPH_RNGC. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->AHBPRST |= RCC_AHBPeriph; + } + else + { + RCC->AHBPRST &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2 + * @param Cmd new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PRST |= RCC_APB2Periph; + } + else + { + RCC->APB2PRST &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC, + * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PRST |= RCC_APB1Periph; + } + else + { + RCC->APB1PRST &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the LowPower domain reset. + * @param Cmd new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLowPowerReset(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param Cmd new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the LSE Clock Security System. + * @param Cmd new state of the LSE Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Get LSE Clock Security System failure status. + * @return LSE Clock Security System failure status (SET or RESET). + */ +FlagStatus RCC_GetLSEClockSecuritySystemStatus(void) +{ + FlagStatus bitstatus = RESET; + /* Check the status of LSE Clock Security System */ + if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return LSE Clock Security System status */ + return bitstatus; +} + +/** + * @brief Configures the MCO PLL clock prescaler. + * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source + * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2) + * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50% + * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50% + */ +void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler)); + tmpregister = RCC->CFG; + /* Clear MCOPRE[3:0] bits */ + tmpregister &= ((uint32_t)0x0FFFFFFF); + /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_MCOCLKPrescaler; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO specifies the clock source to output. + * + * this parameter can be one of the following values: + * @arg RCC_MCO_NOCLK No clock selected + * @arg RCC_MCO_LSI LSI oscillator clock selected + * @arg RCC_MCO_LSE LSE oscillator clock selected + * @arg RCC_MCO_MSI MSI oscillator clock selected + * @arg RCC_MCO_SYSCLK System clock selected + * @arg RCC_MCO_HSI HSI oscillator clock selected + * @arg RCC_MCO_HSE HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK PLL clock selected + * + */ +void RCC_ConfigMco(uint8_t RCC_MCO) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + tmpregister = RCC->CFG; + /* Clear MCO[2:0] bits */ + tmpregister &= ((uint32_t)0xF8FFFFFF); + /* Set MCO[2:0] bits according to RCC_MCO value */ + tmpregister |= ((uint32_t)(RCC_MCO << 24)); + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG specifies the flag to check. + * + * this parameter can be one of the following values: + * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready + * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready + * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready + * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready + * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status + * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag + * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag + * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready + * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag + * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag + * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset + * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset + * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset + * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset + * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset + * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset + * + * @return The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = RCC->CTRL; + } + else if (tmp == 2) /* The flag to check is in BDCTRL register */ + { + statusreg = RCC->LDCTRL; + } + else /* The flag to check is in CTRLSTS register */ + { + statusreg = RCC->CTRLSTS; + } + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST, + * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, + * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +void RCC_ClrFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CTRLSTS |= CSR_RMRSTF_SET; + /* RMVF bit should be reset */ + RCC->CTRLSTS &= CSR_RMVF_Reset; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RccInt specifies the RCC interrupt source to check. + * + * this parameter can be one of the following values: + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * @arg RCC_INT_BORIF interrupt + * @arg RCC_INT_MSIRDIF MSI ready interrupt + * @arg RCC_INT_CLKSSIF Clock Security System interrupt + * + * @return The new state of RccInt (SET or RESET). + */ +INTStatus RCC_GetIntStatus(uint8_t RccInt) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_INT(RccInt)); + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT & RccInt) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RccInt status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RccInt specifies the interrupt pending bit to clear. + * + * this parameter can be any combination of the + * following values: + * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag + * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag + * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag + * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag + * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag + * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag + * @arg RCC_CLR_BORIF Clear BOR interrupt flag + * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag + */ +void RCC_ClrIntPendingBit(uint32_t RccClrInt) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLR_INTF(RccClrInt)); + /* Software set this bit to clear INT flag. */ + RCC->CLKINT |= RccClrInt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rtc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..780be72683c3ab3331cbcccf4ea81b88e9d376fa --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_rtc.c @@ -0,0 +1,2161 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_rtc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_rtc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF) +#define RTC_FLAGS_MASK \ + ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \ + | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \ + | RTC_FLAG_SHOPF)) + +#define INITMODE_TIMEOUT ((uint32_t)0x00002000) +#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000) +#define RECALPF_TIMEOUT ((uint32_t)0x00001000) +#define SHPF_TIMEOUT ((uint32_t)0x00002000) + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** @addtogroup RTC_Private_Functions + * @{ + */ + +/** @addtogroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WRP. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSYF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSYF clear and RSYF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TSH, DAT and CTRL registers */ + RTC->TSH = (uint32_t)0x00000000; + RTC->DATE = (uint32_t)0x00002101; + /* Reset All CTRL bits except CTRL[2:0] */ + RTC->CTRL &= (uint32_t)0x00000007; + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CTRL register bits */ + RTC->CTRL &= (uint32_t)0x00000000; + RTC->WKUPT = (uint32_t)0x0000FFFF; + RTC->PRE = (uint32_t)0x007F00FF; + RTC->ALARMA = (uint32_t)0x00000000; + RTC->ALARMB = (uint32_t)0x00000000; + RTC->SCTRL = (uint32_t)0x00000000; + RTC->CALIB = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + RTC->ALRMBSS = (uint32_t)0x00000000; + /* Reset INTSTS register and exit initialization mode */ + RTC->INITSTS = (uint32_t)0x00000000; + RTC->OPT = (uint32_t)0x00000000; + RTC->TSCWKUPCTRL = (uint32_t)0x00000008; + RTC->TSCWKUPCNT = (uint32_t)0x000002FE; + /* Wait till the RTC RSYF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct pointer to a RTC_InitType structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t i =0; + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CTRL HFMT Bit */ + RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT)); + /* Set RTC_CTRL register */ + RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + /* Configure the RTC PRE */ + RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Delay for the RTC prescale effect */ + for(i=0;i<0x2FF;i++); + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct pointer to a RTC_InitType structure which will be + * initialized. + */ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT; + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_INITSTS[13:8]. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param Cmd new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableWriteProtection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->INITSTS & RTC_INITSTS_INITF; + initcounter++; + } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSYF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TSH and RTC_DATE shadow registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Clear RSYF flag */ + RTC->INITSTS &= (uint32_t)RTC_RSF_MASK; + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF; + synchrocounter++; + } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param Cmd new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd) +{ + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (Cmd != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CTRL |= RTC_CTRL_REFCLKEN; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CTRL &= ~RTC_CTRL_REFCLKEN; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param Cmd new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableBypassShadow(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + if (Cmd != DISABLE) + { + /* Set the BYPS bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS; + } + else + { + /* Reset the BYPS bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains + * the time configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds))); + } + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16)); + } + else + { + tmpregister =(uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16)); + } + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TSH register */ + RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(status!=ERROR) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be + * initialized. + */ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->H12 = RTC_AM_H12; + RTC_TimeStruct->Hours = 0; + RTC_TimeStruct->Minutes = 0; + RTC_TimeStruct->Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will + * contain the returned current time configuration. + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK); + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16); + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes); + RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @return RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpregister = 0; + /* Get subseconds values from the correspondent registers*/ + tmpregister = (uint32_t)(RTC->SUBS); + return (tmpregister); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that contains + * the date configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year))); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month); + assert_param(IS_RTC_MONTH(tmpregister)); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date); + assert_param(IS_RTC_DATE(tmpregister)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13)); + } + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DATE register */ + RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(ERROR!=status) + { + status=RTC_WaitForSynchro(); + } + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct pointer to a RTC_DateType structure which will be + * initialized. + */ +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Date = 1; + RTC_DateStruct->Month = RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that will + * contain the returned current date configuration. + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK); + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13); + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year); + RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month); + RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date); + } +} + +/** + * @} + */ + +/** @addtogroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_EnableAlarm(DISABLE)). + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that + * contains the alarm configuration parameters. + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode)); + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue)); + } + else + { + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue)); + } + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + assert_param(IS_RTC_12HOUR(tmpregister)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds))); + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister)); + } + else + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister)); + } + } + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds)) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_A_ALARM) + { + RTC->ALARMA = (uint32_t)tmpregister; + } + else + { + RTC->ALARMB = (uint32_t)tmpregister; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which + * will be initialized. + */ +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12; + RTC_AlarmStruct->AlarmTime.Hours = 0; + RTC_AlarmStruct->AlarmTime.Minutes = 0; + RTC_AlarmStruct->AlarmTime.Seconds = 0; + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + RTC_AlarmStruct->DateWeekValue = 1; + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will + * contains the output alarm configuration values. + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)(RTC->ALARMA); + } + else + { + tmpregister = (uint32_t)(RTC->ALARMB); + } + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16); + RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8); + RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU)); + RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16); + RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24); + RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL); + RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL); + if (RTC_Format == RTC_FORMAT_BIN) + { + RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes); + RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds); + RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param Cmd new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Configure the Alarm state */ + if (Cmd != DISABLE) + { + RTC->CTRL |= (uint32_t)RTC_Alarm; + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_Alarm; + /* Wait till RTC ALxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8); + alarmcounter++; + } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask.* + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmSubSecondValue specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared. + * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared. + * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared. + * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared. + * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared. + * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared. + * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared. + * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared. + * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared. + * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared. + * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match + * to activate alarm. + */ +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + if (RTC_Alarm == RTC_A_ALARM) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASS = tmpregister; + } + else + { + /* Configure the Alarm B SubSecond register */ + RTC->ALRMBSS = tmpregister; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @return RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpregister = 0; + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV); + } + else + { + tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV); + } + return (tmpregister); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpClock Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16. + * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8. + * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4. + * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2. + * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE. + * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE. + */ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Clear the Wakeup Timer clock source bits in CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL; + /* Configure the clock source */ + RTC->CTRL |= (uint32_t)RTC_WakeUpClock; + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp. + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpCounter specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Configure the Wakeup Timer counter */ + RTC->WKUPT = (uint32_t)RTC_WakeUpCounter; + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @return The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param Cmd new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + */ +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + if (Cmd != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN; + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### Daylight Saving configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaving the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time). + * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time). + * @param RTC_StoreOperation Specifies the value to be written in the BCK bit + * in CTRL register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset. + * @arg RTC_STORE_OPERATION_SET BCK Bit Set. + */ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP); + /* Clear the SU1H and AD1H bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @return RTC Day Light Saving stored operation. + * - RTC_STORE_OPERATION_RESET + * - RTC_STORE_OPERATION_SET + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CTRL & RTC_CTRL_BAKP); +} + +/** + * @} + */ + + + + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_DIS No output selected + * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output. + * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output. + * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output. + * @param RTC_OutputPolarity Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OUTPOL_HIGH The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + * @arg RTC_OUTPOL_LOW The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + */ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_MODE(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL); + /* Configure the output selection and polarity */ + RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions + * @brief Coarse and Smooth Calibrations configuration functions + * +@verbatim + =============================================================================== + ##### Coarse and Smooth Calibrations configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative + * pin. + * @param Cmd new state of the coarse calibration Output. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableCalibOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + if (Cmd != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_COEN; + } + else + { + /* Disable the RTC clock output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz. + * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz. + */ +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /*clear flags before config*/ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_CalibOutput; + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s. + * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s. + * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured + */ +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* check if a calibration is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses + | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + status = SUCCESS; + } + else + { + status = ERROR; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the + * falling edge of the related pin. + * @param Cmd new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN)); + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN); + } + else + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge); + } + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format + * @arg RTC_FORMAT_BCD BCD data format + * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will + * contains the TimeStamp date values. + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK); + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16); + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13); + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours); + RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes); + RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds); + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month); + RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date); + RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @return RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSS); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group11 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in + * Push Pull mode. + */ +void RTC_ConfigOutputType(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE); + RTC->OPT |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar. + * @arg RTC_SHIFT_ADD1S_DISABLE No effect. + * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured + */ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + /* Check if a Shift is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET) + { + /* Configure the Shift settings */ + RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) + using the RTC_SetAlarm() and RTC_EnableAlarm() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 20 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (+) Configure the RTC to generate the RTC wakeup timer event using the + RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is + required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC time-stamp event using the + RTC_EnableTimeStamp() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt mask. + * @arg RTC_INT_WUT WakeUp Timer interrupt mask. + * @arg RTC_INT_ALRB Alarm B interrupt mask. + * @arg RTC_INT_ALRA Alarm A interrupt mask. + * @param Cmd new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_INT(RTC_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + if (Cmd != DISABLE) + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN); + } + else + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN); + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECPF RECALPF event flag. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_INITF Initialization mode flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + * @arg RTC_FLAG_INITSF Registers Configured flag. + * @arg RTC_FLAG_SHOPF Shift operation pending flag. + * @arg RTC_FLAG_WTWF WakeUp Timer Write flag. + * @arg RTC_FLAG_ALBWF Alarm B Write flag. + * @arg RTC_FLAG_ALAWF Alarm A write flag. + * @return The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + /* Get all the flags */ + tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK); + /* Return the status of the flag */ + if ((tmpregister & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG specifies the RTC flag to clear. + * This parameter can be any combination of the following values:. + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag. + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag. + * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + */ +void RTC_ClrFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + /* Clear the Flags in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_INT specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_INT_TS Time Stamp interrupt. + * @arg RTC_INT_WUT WakeUp Timer interrupt. + * @arg RTC_INT_ALRB Alarm B interrupt. + * @arg RTC_INT_ALRA Alarm A interrupt. + * @return The new state of RTC_INT (SET or RESET). + */ +INTStatus RTC_GetITStatus(uint32_t RTC_INT) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0, enablestatus = 0; + uint8_t tamperEnable = 0; + /* Check the parameters */ + assert_param(IS_RTC_GET_INT(RTC_INT)); + /* Get the Interrupt enable Status */ + if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3)) + { + tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16); + if (tamperEnable > 0) + { + enablestatus = SET; + } + } + else + { + enablestatus = (uint32_t)((RTC->CTRL & RTC_INT)); + } + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4))); + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_INT specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_INT_TS Time Stamp interrupt + * @arg RTC_INT_WUT WakeUp Timer interrupt + * @arg RTC_INT_ALRB Alarm B interrupt + * @arg RTC_INT_ALRA Alarm A interrupt + */ +void RTC_ClrIntPendingBit(uint32_t RTC_INT) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_INT(RTC_INT)); + /* Get the RTC_INITSTS Interrupt pending bits mask */ + tmpregister = (uint32_t)(RTC_INT >> 4); + /* Clear the interrupt pending bits in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted. + * @return Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted. + * @return Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} +/** + * @brief Enable wakeup tsc functionand wakeup by the set time + * @param count wakeup time. + */ +void RTC_EnableWakeUpTsc(uint32_t count) +{ + // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1 + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // enter config wakeup cnt mode + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF; + // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI + RTC->TSCWKUPCNT = count; + // exit config wakeup cnt mode + RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF); + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // TSC wakeup enable + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN; +} + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @arg RTC_Tamper_3: Select Tamper 3. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + if (RTC_Tamper == RTC_TAMPER_3) + { + RTC_TamperTrigger <<= 5; + } + if (RTC_Tamper == RTC_TAMPER_2) + { + RTC_TamperTrigger <<= 3; + } + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger); +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level. + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level. + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT); + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ); + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle. + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle. + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH); + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSEN bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS; + } +} + +/** + * @brief Enables or Disables the TAMPTS. + * @param NewState: new state of TAMPTS. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperTAMPTSCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER1_INT: Select Tamper 1. + * @arg RTC_TAMPER2_INT: Select Tamper 2. + * @arg RTC_TAMPER3_INT: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(TAMPxIE)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)TAMPxIE; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~TAMPxIE; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_spi.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..bc12acedd222bb4ce6991ab8e9aed311a8c0b3cb --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_spi.c @@ -0,0 +1,853 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_spi.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_spi.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @addtogroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Defines + * @{ + */ + +/* SPI SPIEN mask */ +#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040) +#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF) + +/* I2S I2SEN mask */ +#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400) +#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF) + +/* SPI CRCNEXT mask */ +#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000) +#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004) +#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0x3040) +#define I2SCFG_CLR_MASK ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xF7FF) +#define I2S_MODE_ENABLE ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S1_CLKSRC ((uint32_t)(0x00020000)) +#define I2S2_CLKSRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @addtogroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx where x can be 1, 2 to select the SPI peripheral. + */ +void SPI_I2S_DeInit(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE); + } + +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_InitStruct pointer to a SPI_InitType structure that + * contains the configuration information for the specified SPI peripheral. + */ +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct) +{ + uint16_t tmpregister = 0; + + /* check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen)); + assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL)); + assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + + /*---------------------------- SPIx CTRL1 Configuration ------------------------*/ + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */ + /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */ + /* Set LSBFirst bit according to FirstBit value */ + /* Set BR bits according to BaudRatePres value */ + /* Set CPOL bit according to CLKPOL value */ + /* Set CPHA bit according to CLKPHA value */ + tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode + | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA + | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit); + /* Write to SPIx CTRL1 */ + SPIx->CTRL1 = tmpregister; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */ + SPIx->I2SCFG &= SPI_MODE_ENABLE; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SPI_InitStruct->CRCPoly; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct pointer to an I2S_InitType structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + */ +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct) +{ + uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksType RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat)); + assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency)); + assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL)); + + /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/ + /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */ + SPIx->I2SCFG &= I2SCFG_CLR_MASK; + SPIx->I2SPREDIV = 0x0002; + + /* Get the I2SCFG register value */ + tmpregister = SPIx->I2SCFG; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if (((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S1 */ + tmp = I2S1_CLKSRC; + } + else + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLKSRC; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SysclkFreq; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPREDIV register the computed value */ + SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpregister |= (uint16_t)( + I2S_MODE_ENABLE + | (uint16_t)(I2S_InitStruct->I2sMode + | (uint16_t)(I2S_InitStruct->Standard + | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL)))); + + /* Write to SPIx I2SCFG */ + SPIx->I2SCFG = tmpregister; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized. + */ +void SPI_InitStruct(SPI_InitType* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; + /* Initialize the CRCPoly member */ + SPI_InitStruct->CRCPoly = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized. + */ +void I2S_InitStruct(I2S_InitType* I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the MCLKEnable member */ + I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE; + + /* Initialize the AudioFrequency member */ + I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT; + + /* Initialize the CLKPOL member */ + I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask + * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask + * @arg SPI_I2S_INT_ERR Error interrupt mask + * @param Cmd new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CTRL2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CTRL2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request + * @param Cmd new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param Data Data to be transmitted. + */ +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Write in the DAT register the data to be sent */ + SPIx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @return The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the data in the DAT register */ + return SPIx->DAT; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_NSSInternalSoft specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSS_HIGH Set NSS pin internally + * @arg SPI_NSS_LOW Reset NSS pin internally + */ +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSS_LOW) + { + /* Set NSS pin internally by software */ + SPIx->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CTRL1 &= SPI_NSS_LOW; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataLen specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit + * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit + */ +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(DataLen)); + /* Clear DFF bit */ + SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS; + /* Set new DFF bit value */ + SPIx->CTRL1 |= DataLen; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + */ +void SPI_TransmitCrcNext(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param Cmd new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_CRC specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_TX Selects Tx CRC register + * @arg SPI_CRC_RX Selects Rx CRC register + * @return The selected CRC register value.. + */ +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_RX) + { + /* Get the Tx CRC register */ + crcreg = SPIx->CRCTDAT; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->CRCRDAT; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @return The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPOLY; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx where x can be 1 or 2 to select the SPI peripheral. + * @param DataDirection specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction + * @arg SPI_BIDIRECTION_RX Selects Rx receive direction + */ +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_BIDIRECTION(DataDirection)); + if (DataDirection == SPI_BIDIRECTION_TX) + { + /* Set the Tx only mode */ + SPIx->CTRL1 |= SPI_BIDIRECTION_TX; + } + else + { + /* Set the Rx only mode */ + SPIx->CTRL1 &= SPI_BIDIRECTION_RX; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag. + * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag. + * @arg SPI_I2S_BUSY_FLAG Busy flag. + * @arg SPI_I2S_OVER_FLAG Overrun flag. + * @arg SPI_MODERR_FLAG Mode Fault flag. + * @arg SPI_CRCERR_FLAG CRC Error flag. + * @arg I2S_UNDER_FLAG Underrun Error flag. + * @arg I2S_CHSIDE_FLAG Channel Side flag. + * @return The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_FLAG specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STS register (SPI_I2S_GetStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STS register (SPI_I2S_GetStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a + * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI). + */ +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->STS = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * - 1 or 2 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt. + * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt. + * @arg SPI_I2S_INT_OVER Overrun interrupt. + * @arg SPI_INT_MODERR Mode Fault interrupt. + * @arg SPI_INT_CRCERR CRC Error interrupt. + * @arg I2S_INT_UNDER Underrun Error interrupt. + * @return The new state of SPI_I2S_IT (SET or RESET). + */ +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx where x can be + * - 1 or 2 in SPI mode + * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable + * the SPI). + */ +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->STS = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tim.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tim.c new file mode 100644 index 0000000000000000000000000000000000000000..ce5fe767b1a9687e58f766b60f2ae2659c361b22 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tim.c @@ -0,0 +1,3290 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_tim.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_tim.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @addtogroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCTRL_ETR_MASK ((uint16_t)0x00FF) +#define CAPCMPMOD_OFFSET ((uint16_t)0x0018) +#define CAPCMPEN_CCE_SET ((uint16_t)0x0001) +#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004) + +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + */ +void TIM_DeInit(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + + if (TIMx == TIM1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE); + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure that contains the configuration information for the + * specified TIM peripheral. + */ +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode)); + assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv)); + + tmpcr1 = TIMx->CTRL1; + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode; + } + + if ((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv; + } + + TIMx->CTRL1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->AR = TIM_TimeBaseInitStruct->Period; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE; + + /*channel input from comp or iom*/ + tmpcr1 = TIMx->CTRL1; + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapCh1FromCompEn) + tmpcr1 |= (0x01L << 11); + else + tmpcr1 &= ~(0x01L << 11); + } + if(TIMx==TIM9) + { + if (TIM_TimeBaseInitStruct->CapCh2FromCompEn) + tmpcr1 |= (0x01L << 12); + else + tmpcr1 &= ~(0x01L << 12); + if (TIM_TimeBaseInitStruct->CapCh3FromCompEn) + tmpcr1 |= (0x01L << 13); + else + tmpcr1 &= ~(0x01L << 13); + if (TIM_TimeBaseInitStruct->CapCh4FromCompEn) + tmpcr1 |= (0x01L << 14); + else + tmpcr1 &= ~(0x01L << 14); + } + /*etr input from comp or iom*/ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9)) + { + if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn) + tmpcr1 |= (0x01L << 15); + else + tmpcr1 &= ~(0x01L << 15); + } + TIMx->CTRL1 = tmpcr1; + /*sel etr from iom or tsc*/ + tmpcr1 = TIMx->CTRL2; + if ((TIMx == TIM2) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn) + tmpcr1 |= (0x01L << 8); + else + tmpcr1 &= ~(0x01L << 8); + } + TIMx->CTRL2 = tmpcr1; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN); + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->OcPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->OutputState; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->OcNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcNIdleState; + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN)); + + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel5 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 5: Reset the CC5E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel6 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 6: Reset the CC6E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT6 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IsTimCh(TIM_ICInitStruct->Channel)); + assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection)); + assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler)); + assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity)); + } + else + { + assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity)); + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + assert_param(IsTimList8Module(TIMx)); + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + assert_param(IsTimList6Module(TIMx)); + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + assert_param(IsTimList3Module(TIMx)); + /* TI3 Configuration */ + ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + assert_param(IsTimList3Module(TIMx)); + /* TI4 Configuration */ + ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING; + uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING) + { + icoppositepolarity = TIM_IC_POLARITY_FALLING; + } + else + { + icoppositepolarity = TIM_IC_POLARITY_RISING; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI) + { + icoppositeselection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI2 Configuration */ + ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI1 Configuration */ + ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that + * contains the BKDT Register configuration information for the TIM peripheral. + */ +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + uint32_t tmp; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState)); + assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState)); + assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel)); + assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break)); + assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel + | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity + | TIM_BDTRInitStruct->AutomaticOutput; + + /*cofigure other break in*/ + tmp = TIMx->CTRL1; + /*IOMBKPEN 0 meaning iom as break enable*/ + if (TIM_BDTRInitStruct->IomBreakEn) + tmp &= ~(0x01L << 10); + else + tmp |= (0x01L << 10); + if (TIM_BDTRInitStruct->LockUpBreakEn) + tmp |= (0x01L << 16); + else + tmp &= ~(0x01L << 16); + if (TIM_BDTRInitStruct->PvdBreakEn) + tmp |= (0x01L << 17); + else + tmp &= ~(0x01L << 17); + TIMx->CTRL1 = tmp; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure which will be initialized. + */ +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Period = 0xFFFF; + TIM_TimeBaseInitStruct->Prescaler = 0x0000; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->RepetCnt = 0x0000; + + TIM_TimeBaseInitStruct->CapCh1FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh2FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh3FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh4FromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct pointer to a OCInitType structure which will + * be initialized. + */ +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x0000; + TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will + * be initialized. + */ +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->Channel = TIM_CH_1; + TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->IcFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which + * will be initialized. + */ +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param Cmd new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CTRL1 |= TIM_CTRL1_CNTEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral. + * @param Cmd new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BKDT |= TIM_BKDT_MOEN; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @param Cmd new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DINTEN |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DINTEN &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_EventSource specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EVT_SRC_UPDATE Timer update Event source + * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source + * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source + * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source + * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source + * @arg TIM_EVT_SRC_COM Timer COM event source + * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source + * @arg TIM_EVT_SRC_BREAK Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8. + */ +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimEvtSrc(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EVTGEN = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_DMABase DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL, + * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN, + * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN, + * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR, + * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2, + * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT, + * TIM_DMABASE_DMACTRL. + * @param TIM_DMABurstLength DMA Burst length. + * This parameter can be one value between: + * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS. + */ +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IsTimDmaBase(TIM_DMABase)); + assert_param(IsTimDmaLength(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 + * to select the TIM peripheral. + * @param TIM_DMASource specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_UPDATE TIM update Interrupt source + * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM TIM Commutation DMA source + * @arg TIM_DMA_TRIG TIM Trigger DMA source + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList9Module(TIMx)); + assert_param(IsTimDmaSrc(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DINTEN |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DINTEN &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIM peripheral. + */ +void TIM_ConfigInternalClk(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_InputTriggerSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + */ +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimInterTrigSel(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector + * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1 + * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2 + * @param IcPolarity specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param ICFilter specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + */ +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource)); + assert_param(IsTimIcPalaritySingleEdge(IcPolarity)); + assert_param(IsTimInCapFilter(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2) + { + ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + else + { + ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + tmpsmcr |= TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCTRL |= TIM_SMCTRL_EXCEN; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + tmpsmcr = TIMx->SMCTRL; + /* Reset the ETR Bits */ + tmpsmcr &= SMCTRL_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= + (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Prescaler specifies the Prescaler Register value + * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event. + * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately. + */ +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimPscReloadMode(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EVTGEN = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param CntMode specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CNT_MODE_UP TIM Up Counting Mode + * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode + * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1 + * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2 + * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3 + */ +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode) +{ + uint32_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimCntMode(CntMode)); + tmpcr1 = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + tmpcr1 |= CntMode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector + * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1 + * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2 + * @arg TIM_TRIG_SEL_ETRF External Trigger input + */ +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimTrigSel(TIM_InputTriggerSource)); + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + * @param TIM_IC2Polarity specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + */ +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IsTimEncodeMode(TIM_EncoderMode)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity)); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL))); + tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P))); + tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF. + */ +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF. + */ +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF. + */ +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF. + */ +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 5 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF. + */ +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Forces the TIMx output 6 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF. + */ +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on AR. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AR Preload Bit */ + TIMx->CTRL1 |= TIM_CTRL1_ARPEN; + } + else + { + /* Reset the AR Preload Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral + * @param Cmd new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the COM Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCUSEL; + } + else + { + /* Reset the COM Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param Cmd new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCDSEL; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIMx peripheral + * @param Cmd new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCPCTL; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC5PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC6PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 5 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 6 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF5 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF6 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param OcPolarity specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P); + tmpccer |= OcPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP); + tmpccer |= OcNPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P); + tmpccer |= (uint32_t)(OcPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP); + tmpccer |= (uint32_t)(OcNPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P); + tmpccer |= (uint32_t)(OcPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP); + tmpccer |= (uint32_t)(OcNPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P); + tmpccer |= (uint32_t)(OcPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 5 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC5 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC5P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P); + tmpccer |= (uint32_t)(OcPolarity << 16); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 6 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC6 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC6P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P); + tmpccer |= (uint32_t)(OcPolarity << 20); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param TIM_CCx specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE. + */ +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimCapCmpState(TIM_CCx)); + + tmp = CAPCMPEN_CCE_SET << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE. + */ +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimComplementaryCh(Channel)); + assert_param(IsTimCapCmpNState(TIM_CCxN)); + + tmp = CAPCMPEN_CCNE_SET << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param OcMode specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMODE_TIMING + * @arg TIM_OCMODE_ACTIVE + * @arg TIM_OCMODE_TOGGLE + * @arg TIM_OCMODE_PWM1 + * @arg TIM_OCMODE_PWM2 + * @arg TIM_FORCED_ACTION_ACTIVE + * @arg TIM_FORCED_ACTION_INACTIVE + */ +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimOc(OcMode)); + + tmp = (uint32_t)TIMx; + tmp += CAPCMPMOD_OFFSET; + + tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint16_t)~tmp1; + + if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3)) + { + tmp += (Channel >> 1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= OcMode; + } + else + { + tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_UpdateSource specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow. + */ +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimUpdateSrc(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the URS Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPRS; + } + else + { + /* Reset the URS Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CTRL2 |= TIM_CTRL2_TI1SEL; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_OPMode specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE + * @arg TIM_OPMODE_REPET + */ +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimOpMOde(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM); + /* Configure the OPM Mode */ + TIMx->CTRL1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral. + * @param TIM_TRGOSource specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO). + * + */ +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IsTimList7Module(TIMx)); + assert_param(IsTimTrgoSrc(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_SlaveMode specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter. + */ +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimSlaveMode(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL); + /* Select the Slave Mode */ + TIMx->SMCTRL |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action + */ +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD); + + /* Set or Reset the MSM Bit */ + TIMx->SMCTRL |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Counter specifies the Counter register new value. + */ +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Autoreload specifies the Autoreload register new value. + */ +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Autoreload Register value */ + TIMx->AR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Compare1 specifies the Capture Compare1 register new value. + */ +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCDAT1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param Compare2 specifies the Capture Compare2 register new value. + */ +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCDAT2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3 specifies the Capture Compare3 register new value. + */ +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCDAT3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4 specifies the Capture Compare4 register new value. + */ +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT4 = Compare4; +} + +/** + * @brief Sets the TIMx Capture Compare5 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare5 specifies the Capture Compare5 register new value. + */ +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT5 = Compare5; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare6 specifies the Capture Compare6 register new value. + */ +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT6 = Compare6; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMOD2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLK_DIV1 TDTS = Tck_tim + * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim + * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim + */ +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimClkDiv(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD); + /* Set the CKD value */ + TIMx->CTRL1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @return Capture Compare 1 Register value. + */ +uint16_t TIM_GetCap1(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCDAT1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @return Capture Compare 2 Register value. + */ +uint16_t TIM_GetCap2(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCDAT2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 3 Register value. + */ +uint16_t TIM_GetCap3(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCDAT3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 4 Register value. + */ +uint16_t TIM_GetCap4(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCDAT4; +} + +/** + * @brief Gets the TIMx Input Capture 5 value. + * @param TIMx where x can be 1 8 to select the TIM peripheral. + * @return Capture Compare 5 Register value. + */ +uint16_t TIM_GetCap5(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 5 Register value */ + return TIMx->CCDAT5; +} + +/** + * @brief Gets the TIMx Input Capture 6 value. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @return Capture Compare 6 Register value. + */ +uint16_t TIM_GetCap6(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 6 Register value */ + return TIMx->CCDAT6; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Counter Register value. + */ +uint16_t TIM_GetCnt(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetAutoReload(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->AR; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral. + * @param TIM_CCEN specifies the Bit to check. + * This parameter can be one of the following values: + * @arg TIM_CC1EN CC1EN Bit + * @arg TIM_CC1NEN CC1NEN Bit + * @arg TIM_CC2EN CC2EN Bit + * @arg TIM_CC2NEN CC2NEN Bit + * @arg TIM_CC3EN CC3EN Bit + * @arg TIM_CC3NEN CC3NEN Bit + * @arg TIM_CC4EN CC4EN Bit + * @arg TIM_CC5EN CC5EN Bit + * @arg TIM_CC6EN CC6EN Bit + * @note + * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + + if(TIMx==TIM1 || TIMx==TIM8){ + assert_param(IsAdvancedTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + }else if(TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){ + assert_param(IsGeneralTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetFlag(TIM_FLAG)); + + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + */ +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimClrFlag(TIM_FLAG)); + + /* Clear the flags */ + TIMx->STS = (uint32_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @return The new state of the TIM_IT(SET or RESET). + */ +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetInt(TIM_IT)); + + itstatus = TIMx->STS & TIM_IT; + + itenable = TIMx->DINTEN & TIM_IT; + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM1 update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + */ +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->STS = (uint32_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F))); + tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F))); + tmpccmr1 |= (uint16_t)(IcFilter << 12); + tmpccmr1 |= (uint16_t)(IcSelection << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F))); + tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F))); + tmpccmr2 |= (uint16_t)(IcSelection << 8); + tmpccmr2 |= (uint16_t)(IcFilter << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN); + } + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tsc.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tsc.c new file mode 100644 index 0000000000000000000000000000000000000000..c3810976d37fc329c61b81047ac17d5fed8ea15a --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_tsc.c @@ -0,0 +1,279 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_tsc.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x.h" +#include "n32l43x_tsc.h" + +/** +* @brief Init TSC config +* @param InitParam: TSC initialize structure +* @return : TSC_ErrorTypeDef +*/ +TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam) +{ + uint32_t tempreg,timeout; + + assert_param(IS_TSC_DET_MODE(InitParam->Mode)); + assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt)); + assert_param(IS_TSC_PAD_SPEED(InitParam->Speed)); + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*TSC_CTRL config*/ + tempreg = 0; + if(InitParam->Mode == TSC_HW_DETECT_MODE) + { + assert_param(IS_TSC_DET_PERIOD(InitParam->Period)); + assert_param(IS_TSC_FILTER(InitParam->Filter)); + assert_param(IS_TSC_DET_TYPE(InitParam->Type)); + assert_param(IS_TSC_INT(InitParam->Int)); + + tempreg |= InitParam->Period; + tempreg |= InitParam->Filter; + tempreg |= InitParam->Type; + tempreg |= InitParam->Int; + } + else + { + assert_param(IS_TSC_OUT(InitParam->Out)); + tempreg |= InitParam->Out; + } + + TSC->CTRL = tempreg; + + /*TSC_ANA_SEL config*/ + TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed; + + return TSC_ERROR_OK; +} + +/** + * @brief Config the clock source of TSC + * @param TSC_ClkSource specifies the clock source of TSC + * This parameter can be one of the following values: + * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default) + * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator + * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock + * @retval TSC error code + */ +TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(TSC_CLK_SRC_LSI == TSC_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + else if((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET) + { + RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28); + timeout = 0; + while(RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + } + else + return TSC_ERROR_PARAMETER; + + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100; + + /*set LSI as TSC clock source*/ + RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL); + + /*Enable TSC clk*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE); + + return TSC_ERROR_OK; +} + +/** +* @brief Configure internal charge resistor for some channels +* @param res: internal resistor selecte +* This parameter can be one of the following values: +* @arg TSC_RESR_CHN_RESIST_0: 1M OHM +* @arg TSC_RESR_CHN_RESIST_1: 882K OHM +* @arg TSC_RESR_CHN_RESIST_2: 756K OHM +* @arg TSC_RESR_CHN_RESIST_3: 630K OHM +* @arg TSC_RESR_CHN_RESIST_4: 504K OHM +* @arg TSC_RESR_CHN_RESIST_5: 378K OHM +* @arg TSC_RESR_CHN_RESIST_6: 252K OHM +* @arg TSC_RESR_CHN_RESIST_7: 126K OHM +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @return: none +*/ +TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ) +{ + uint32_t i,chn,timeout,nReg,nPos; + + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_RESISTOR_VALUE(res)); + + /*Check charge resistor value */ + if(res > TSC_RESRx_CHN_RESIST_7) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /* Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set resistance for each channel one by one*/ + for (i = 0; i> 3; + nPos = (i & 0x7UL)*4; + MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1; + } + + return TSC_ERROR_OK; +} + +/** +* @brief Configure threshold value for some channels +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE +* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA +* @return: None +*/ +TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta) +{ + uint32_t i, chn,timeout; + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_THRESHOLD_BASE(base)); + assert_param(IS_TSC_THRESHOLD_DELTA(delta)); + + /*Check the base and delta value*/ + if( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA)) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SELx_Msk; + + /* Set the base and delta for each channnel one by one*/ + for (i = 0; iTHRHD[i] = (base<>= 1; + } + + return TSC_ERROR_OK; +} + + +/** +* @brief Get parameters of one channel. +* @param ChnCfg: Pointer of TSC_ChnCfg structure. +* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN +* @return: None +*/ +TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum) +{ + uint32_t nReg,nPos; + + assert_param(IS_TSC_CHN_NUMBER(ChannelNum)); + + /*Check channel number*/ + if(!(IS_TSC_CHN_NUMBER(ChannelNum))) + return TSC_ERROR_PARAMETER; + + /* Get the base and delta value for a channel*/ + ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos; + ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos; + + /* Get the charge resistor type for a channel*/ + nReg = ChannelNum>>3; + nPos = (ChannelNum & 0x7UL)*4; + ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk; + + return TSC_ERROR_OK; +} + + diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_usart.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..b12d5b41180aa8af3a8aa19d2999a9b0e19fab65 --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_usart.c @@ -0,0 +1,956 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_usart.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_usart.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @brief USART driver modules + * @{ + */ + +/** @addtogroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Defines + * @{ + */ + +#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ +#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */ +#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */ + +#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */ + +#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_DeInit(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE); + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct pointer to a USART_InitType structure + * that contains the configuration information for the specified USART + * peripheral. + */ +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct) +{ + uint32_t tmpregister = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksType RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear STOP[13:12] bits */ + tmpregister &= CTRL2_STPB_CLR_MASK; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to StopBits value */ + tmpregister |= (uint32_t)USART_InitStruct->StopBits; + + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL1 Configuration -----------------------*/ + tmpregister = USARTx->CTRL1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to WordLength value */ + /* Set PCE and PS bits according to Parity value */ + /* Set TE and RE bits according to Mode value */ + tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode; + /* Write to USART CTRL1 */ + USARTx->CTRL1 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL3 Configuration -----------------------*/ + tmpregister = USARTx->CTRL3; + /* Clear CTSE and RTSE bits */ + tmpregister &= CTRL3_CLR_MASK; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to HardwareFlowControl value */ + tmpregister |= USART_InitStruct->HardwareFlowControl; + /* Write to USART CTRL3 */ + USARTx->CTRL3 = (uint16_t)tmpregister; + + /*---------------------------- USART PBC Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE)) + { + apbclock = RCC_ClocksStatus.Pclk2Freq; + } + else + { + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate))); + tmpregister = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpregister >> 4)); + + /* Implement the fractional part in the register */ + tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + /* Write to USART PBC */ + USARTx->BRCF = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct pointer to a USART_InitType structure + * which will be initialized. + */ +void USART_StructInit(USART_InitType* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->BaudRate = 9600; + USART_InitStruct->WordLength = USART_WL_8B; + USART_InitStruct->StopBits = USART_STPB_1; + USART_InitStruct->Parity = USART_PE_NO; + USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4/UART5. + */ +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct) +{ + uint32_t tmpregister = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit)); + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpregister &= CTRL2_CLOCK_CLR_MASK; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to Clock value */ + /* Set CPOL bit according to Polarity value */ + /* Set CPHA bit according to Phase value */ + /* Set LBCL bit according to LastBit value */ + tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity + | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure which will be initialized. + */ +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->Clock = USART_CLK_DISABLE; + USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW; + USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; + USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_UEN_SET; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_UEN_RESET; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Transmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) + * @param Cmd new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CFG_INT(USART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_INT & INT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CTRL3 register */ + { + usartxbase += 0x14; + } + if (Cmd != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAREQ_TX USART DMA transmit request + * @arg USART_DMAREQ_RX USART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Addr Indicates the address of the USART node. + */ +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Addr)); + + /* Clear the USART address */ + USARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the USART address node */ + USARTx->CTRL2 |= USART_Addr; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUpMode specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WUM_IDLELINE WakeUp by an idle line detection + * @arg USART_WUM_ADDRMASK WakeUp by an address mark + */ +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUpMode)); + + USARTx->CTRL1 &= CTRL1_WUM_MASK; + USARTx->CTRL1 |= USART_WakeUpMode; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_RCVWU_SET; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_RCVWU_RESET; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBDL_10B 10-bit break detection + * @arg USART_LINBDL_11B 11-bit break detection + */ +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CTRL2 &= CTRL2_LINBDL_MASK; + USARTx->CTRL2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 |= CTRL2_LINMEN_SET; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 &= CTRL2_LINMEN_RESET; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data the data to transmit. + */ +void USART_SendData(USART_Module* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DAT = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_SendBreak(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime specifies the guard time. + * @note The guard time bits are not available for UART4/UART5. + */ +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTP &= GTP_LSB_MASK; + /* Set the USART guard time */ + USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + */ +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTP &= GTP_MSB_MASK; + /* Set the USART prescaler */ + USARTx->GTP |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCMEN_SET; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCMEN_RESET; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5. + */ +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCNACK_SET; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCNACK_RESET; + } +} + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_HDMEN_SET; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_HDMEN_RESET; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDAMODE_LOWPPWER + * @arg USART_IRDAMODE_NORMAL + */ +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CTRL3 &= CTRL3_IRDALP_MASK; + USARTx->CTRL3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Cmd new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_IRDAMEN_SET; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LINBD LIN Break detection flag + * @arg USART_FLAG_TXDE Transmit data register empty flag + * @arg USART_FLAG_TXC Transmission Complete flag + * @arg USART_FLAG_RXDNE Receive data register not empty flag + * @arg USART_FLAG_IDLEF Idle Line detection flag + * @arg USART_FLAG_OREF OverRun Error flag + * @arg USART_FLAG_NEF Noise Error flag + * @arg USART_FLAG_FEF Framing Error flag + * @arg USART_FLAG_PEF Parity Error flag + * @return The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if (USART_FLAG == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LINBD LIN Break detection flag. + * @arg USART_FLAG_TXC Transmission Complete flag. + * @arg USART_FLAG_RXDNE Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5 */ + if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->STS = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Tansmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_OREF OverRun Error interrupt + * @arg USART_INT_NEF Noise Error interrupt + * @arg USART_INT_FEF Framing Error interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @return The new state of USART_INT (SET or RESET). + */ +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_INT & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + itmask &= USARTx->CTRL1; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + itmask &= USARTx->CTRL2; + } + else /* The IT is in CTRL3 register */ + { + itmask &= USARTx->CTRL3; + } + + bitpos = USART_INT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXC Transmission complete interrupt. + * @arg USART_INT_RXDNE Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetIntStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetIntStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLR_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_INT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STS = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_wwdg.c b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..25edeea47847db34873114402b7d9f9dcb9e28ea --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/n32l43x_std_periph_driver/src/n32l43x_wwdg.c @@ -0,0 +1,219 @@ +/***************************************************************************** + * Copyright (c) 2022, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32l43x_wwdg.c + * @author Nations + * @version V1.2.1 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32l43x_wwdg.h" +#include "n32l43x_rcc.h" + +/** @addtogroup n32l43x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @addtogroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFG_OFFADDR (WWDG_OFFADDR + 0x04) +#define EWINT_BIT 0x09 +#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_ACTB_SET ((uint32_t)0x00000080) + +/* CFG register bit mask */ +#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F) +#define CFG_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + */ +void WWDG_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8 + */ +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpregister = WWDG->CFG & CFG_TIMERB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpregister |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + */ +void WWDG_SetWValue(uint8_t WindowValue) +{ + __IO uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_WWDG_WVALUE(WindowValue)); + /* Clear W[6:0] bits */ + tmpregister = WWDG->CFG & CFG_W_MASK; + /* Set W[6:0] bits according to WindowValue value */ + tmpregister |= WindowValue & (uint32_t)BIT_MASK; + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + */ +void WWDG_EnableInt(void) +{ + *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_SetCnt(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CTRL = Counter & BIT_MASK; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + WWDG->CTRL = CTRL_ACTB_SET | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetEWINTF(void) +{ + return (FlagStatus)(WWDG->STS); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + */ +void WWDG_ClrEWINTF(void) +{ + WWDG->STS = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/hal/nationstech/N32L43x/weave.yaml b/drivers/hal/nationstech/N32L43x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ec4952a44e6c8decc87e672babc978742bd6a0dd --- /dev/null +++ b/drivers/hal/nationstech/N32L43x/weave.yaml @@ -0,0 +1,33 @@ +# 组名 +group_name: hal/lowlevel + +# 依赖宏控 +depend_macro: + - SERIES_N32L43X + +# 编译连接信息 +build_option: + cpppath: + - n32l43x_std_periph_driver/inc + - CMSIS/core + - CMSIS/device + +# 源码 +source_file: + - CMSIS/device/system_n32l43x.c + - n32l43x_std_periph_driver/src/n32l43x_rcc.c + - n32l43x_std_periph_driver/src/misc.c + - n32l43x_std_periph_driver/src/n32l43x_gpio.c + - n32l43x_std_periph_driver/src/n32l43x_exti.c ? {is_define("OS_USING_PIN")} + - n32l43x_std_periph_driver/src/n32l43x_iwdg.c ? {is_define("OS_USING_WDG")} + - n32l43x_std_periph_driver/src/n32l43x_usart.c ? {is_define("OS_USING_SERIAL")} + - n32l43x_std_periph_driver/src/n32l43x_adc.c ? {is_define("OS_USING_ADC")} + - n32l43x_std_periph_driver/src/n32l43x_dac.c ? {is_define("OS_USING_DAC")} + - n32l43x_std_periph_driver/src/n32l43x_i2c.c ? {is_define("OS_USING_I2C")} + - n32l43x_std_periph_driver/src/n32l43x_spi.c ? {is_define("OS_USING_SPI")} + - n32l43x_std_periph_driver/src/n32l43x_flash.c ? {is_define("OS_USING_FAL")} + - n32l43x_std_periph_driver/src/n32l43x_dma.c ? {is_define("OS_USING_DMA")} + - n32l43x_std_periph_driver/src/n32l43x_rtc.c ? {is_define("BSP_USING_RTC")} + - n32l43x_std_periph_driver/src/n32l43x_pwr.c ? {is_define("BSP_USING_RTC")} + - n32l43x_std_periph_driver/src/n32l43x_tim.c ? {is_define("BSP_USING_TIMER")} + - n32l43x_std_periph_driver/src/n32l43x_eth.c ? {is_define("BSP_USING_ETH")} \ No newline at end of file diff --git a/drivers/hal/nationstech/devices/n32_devices.c b/drivers/hal/nationstech/devices/n32_devices.c index b5bad9e0a6f9a54b4b48fea33638a4f30987c878..64528803f6985e94f64cafc72b68c1b6be4e2096 100644 --- a/drivers/hal/nationstech/devices/n32_devices.c +++ b/drivers/hal/nationstech/devices/n32_devices.c @@ -11,7 +11,7 @@ * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * - * @file n32_devices.c + * @file drv_usart.c * * @brief This file implements usart driver for stm32 * diff --git a/drivers/hal/nationstech/devices/weave.yaml b/drivers/hal/nationstech/devices/weave.yaml index eddb1a62f0b4a637901b9c16d36b052bc53237a6..91f793364ef301ae5cc4b310260bf4c032c203d2 100644 --- a/drivers/hal/nationstech/devices/weave.yaml +++ b/drivers/hal/nationstech/devices/weave.yaml @@ -12,4 +12,4 @@ build_option: # 源码 source_file: - - n32_devices.c \ No newline at end of file + - n32_devices.c diff --git a/drivers/hal/nationstech/drivers/Kconfig b/drivers/hal/nationstech/drivers/Kconfig index 6a522e8afcd873c139c5f426d144249ed85b1804..ea95db92122db08b783bb04155d971a052351c62 100644 --- a/drivers/hal/nationstech/drivers/Kconfig +++ b/drivers/hal/nationstech/drivers/Kconfig @@ -13,8 +13,19 @@ config BSP_USING_USART default y select OS_USING_SERIAL +config BSP_USING_SPI + bool "Enable SPI" + default n + select OS_USING_SPI + config BSP_USING_ONCHIP_FLASH bool "Enable on-chip FLASH" default y - - \ No newline at end of file + +config BSP_USING_TIMER + bool "Enable Timer" + default y + +config OS_USING_ADC + bool "Enable ADC" + default n \ No newline at end of file diff --git a/drivers/hal/nationstech/drivers/drv_common.c b/drivers/hal/nationstech/drivers/n32g43x/drv_common.c similarity index 74% rename from drivers/hal/nationstech/drivers/drv_common.c rename to drivers/hal/nationstech/drivers/n32g43x/drv_common.c index c009d9bc83cfd4e6d2df8a84951118e404d1b56a..8d65a7862551a8e98d00401c48e3a71372d3da21 100644 --- a/drivers/hal/nationstech/drivers/drv_common.c +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_common.c @@ -45,12 +45,34 @@ #include +static volatile os_bool_t hardware_init_done = OS_FALSE; + void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; } +void os_tick_handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + +void SysTick_Handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + static void cortexm_systick_kernel_tick_init(void) { SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); @@ -59,9 +81,39 @@ static void cortexm_systick_kernel_tick_init(void) NVIC_SetPriority(SysTick_IRQn, 0xFF); } +#endif + +#if defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) +void SysTick_Handler(void) +{ + if (hardware_init_done) + { + cortexm_systick_clockevent_isr(); + } + else + { + os_tick_handler(); + } +} +#endif + void hardware_init(void) { - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); // NVIC_PriorityGroup_0, SVCָӲ(Group0λΪӦȼ,ûռ) + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); // 不能是NVIC_PriorityGroup_0, 否则SVC指令会产生硬件错误(Group0所有位为响应优先级,没有抢占) + + + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL = 0; + NVIC_SetPriority(SysTick_IRQn, 0xFF); + NVIC_EnableIRQ(SysTick_IRQn); + + SysTick->LOAD = 10000; /* set reload register */ + SysTick->VAL = 0UL; /* Load the systick Counter Value */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk;; + + } void os_hw_cpu_reset(void) @@ -93,8 +145,7 @@ static os_err_t os_hw_board_init(void) if ((os_size_t)HEAP_END > (os_size_t)HEAP_BEGIN) { os_default_heap_init(); - os_kprintf("mem begin:0x%lx size 0x%lx\n\r",HEAP_BEGIN,(os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN); - os_default_heap_add((void *)HEAP_BEGIN, (os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN,OS_MEM_ALG_DEFAULT); + os_default_heap_add((void *)HEAP_BEGIN, (os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN, OS_MEM_ALG_DEFAULT); } #endif @@ -130,6 +181,8 @@ static os_err_t board_post_init(void) // calc_mult_shift(&mult_systick2msec, &shift_systick2msec, OS_TICK_PER_SECOND, 1000, 1); cortexm_systick_init(); + + hardware_init_done = OS_TRUE; return OS_SUCCESS; } diff --git a/drivers/hal/nationstech/drivers/drv_common.h b/drivers/hal/nationstech/drivers/n32g43x/drv_common.h similarity index 84% rename from drivers/hal/nationstech/drivers/drv_common.h rename to drivers/hal/nationstech/drivers/n32g43x/drv_common.h index 209fc570da44c800a1f2fe440e55a872ec127501..f76a5a8303b90836164853d86569e0cb9ae26ec0 100644 --- a/drivers/hal/nationstech/drivers/drv_common.h +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_common.h @@ -27,7 +27,21 @@ #include #include -#include "n32g45x_hal.h" +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_conf.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_conf.h" +#endif + +#ifdef SERIES_N32L43X +#include "n32l43x_conf.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/drivers/hal/nationstech/drivers/n32g43x/drv_gpio.c b/drivers/hal/nationstech/drivers/n32g43x/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..a6a6f62a0bbb575848bb3604f96a52c3f4164254 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_gpio.c @@ -0,0 +1,429 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.c + * + * @brief This file implements gpio driver for apm32. + * + * @revision + * Date Author Notes + * 2022-01-17 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.gpio" +#include + +#include "drv_gpio.h" + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#define N32_PORT(pin) ((pin) >> 4) +#define N32_PIN(pin) ((pin) & 0x0F) + +struct n32_pin_irq +{ + uint16_t pinbit; + IRQn_Type irqno; +}; + +struct n32_gpio +{ + GPIO_Module *base; + uint32_t rcc; +}; + +static const struct n32_gpio n32_gpio_table[] = +{ +#ifdef GPIOA + {GPIOA, RCC_APB2_PERIPH_GPIOA}, +#ifdef GPIOB + {GPIOB, RCC_APB2_PERIPH_GPIOB}, +#ifdef GPIOC + {GPIOC, RCC_APB2_PERIPH_GPIOC}, +#ifdef GPIOD + {GPIOD, RCC_APB2_PERIPH_GPIOD}, +#ifdef GPIOE + {GPIOE, RCC_APB2_PERIPH_GPIOE}, +#ifdef GPIOF + {GPIOF, RCC_APB2_PERIPH_GPIOF}, +#ifdef GPIOG + {GPIOG, RCC_APB2_PERIPH_GPIOG}, +#endif /* GPIOG */ +#endif /* GPIOF */ +#endif /* GPIOE */ +#endif /* GPIOD */ +#endif /* GPIOC */ +#endif /* GPIOB */ +#endif /* GPIOA */ +}; + +static const struct n32_pin_irq n32_pin_irq[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +}; + +static struct os_pin_irq_hdr n32_pin_irq_hdr_tab[] = { + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, +}; + +static void n32_pin_write(os_device_t *dev, os_base_t pin, os_base_t value) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + if (value) + { // set + gpio->base->PBSC = (1<base->PBC = (1<base->PID & mask) == mask; +} + +static void n32_pin_mode(os_device_t *dev, os_base_t pin, os_base_t mode) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + GPIO_InitType init; + init.Pin = (1<rcc, ENABLE); + GPIO_InitPeripheral(gpio->base, &init); +} + +static os_err_t n32_pin_attach_irq(struct os_device *device, int32_t pin, uint32_t mode, void (*hdr)(void *args), void *args) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == pin + && n32_pin_irq_hdr_tab[Pin].hdr == hdr + && n32_pin_irq_hdr_tab[Pin].mode == mode + && n32_pin_irq_hdr_tab[Pin].args == args) + { + os_irq_unlock(level); + return OS_SUCCESS; + } + + if (n32_pin_irq_hdr_tab[Pin].pin != -1) + { + os_irq_unlock(level); + return OS_BUSY; + } + + n32_pin_irq_hdr_tab[Pin].pin = pin; + n32_pin_irq_hdr_tab[Pin].hdr = hdr; + n32_pin_irq_hdr_tab[Pin].mode = mode; + n32_pin_irq_hdr_tab[Pin].args = args; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_detach_irq(struct os_device *device, int32_t pin) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_INVAL; + } + + n32_pin_irq_hdr_tab[Pin].pin = -1; + n32_pin_irq_hdr_tab[Pin].hdr = OS_NULL; + n32_pin_irq_hdr_tab[Pin].mode = 0; + n32_pin_irq_hdr_tab[Pin].args = OS_NULL; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint32_t enabled) +{ + os_base_t level; + const struct n32_pin_irq *irqmap; + + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + if (enabled == PIN_IRQ_ENABLE) + { + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_ENOSYS; + } + + irqmap = &n32_pin_irq[Pin]; + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + + switch (n32_pin_irq_hdr_tab[Pin].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + case PIN_IRQ_MODE_LOW_LEVEL: + default: + os_irq_unlock(level); + return OS_INVAL; + } + + GPIO_ConfigEXTILine(GPIOA_PORT_SOURCE + Port, GPIO_PIN_SOURCE0 + Pin); + + EXTI_InitPeripheral(&EXTI_InitStructure); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + os_irq_unlock(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + level = os_irq_lock(); + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + + os_irq_unlock(level); + } + else + { + return OS_ENOSYS; + } + + return OS_SUCCESS; +} + +const static struct os_pin_ops n32_pin_ops = { + .pin_mode = n32_pin_mode, + .pin_write = n32_pin_write, + .pin_read = n32_pin_read, + .pin_attach_irq = n32_pin_attach_irq, + .pin_detach_irq = n32_pin_detach_irq, + .pin_irq_enable = n32_pin_irq_enable, +}; + +int os_hw_pin_init(void) +{ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); + + return os_device_pin_register(0, &n32_pin_ops, OS_NULL); +} + +static void n32_pin_irq_hdr(int irqno) +{ + if (n32_pin_irq_hdr_tab[irqno].hdr) + { + n32_pin_irq_hdr_tab[irqno].hdr(n32_pin_irq_hdr_tab[irqno].args); + } +} + + +static void HAL_GPIO_EXTI_IRQHandler(uint16_t EXTI_Line) +{ + if ((EXTI->IMASK & EXTI_Line) + && (EXTI->PEND & EXTI_Line)) + { + EXTI->PEND = EXTI_Line; + + n32_pin_irq_hdr(os_ffs(EXTI_Line) - 1); + } +} + +void EXTI0_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE0); +} + +void EXTI1_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE1); +} + +void EXTI2_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE2); +} + +void EXTI3_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE3); +} + +void EXTI4_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE4); +} + +void EXTI9_5_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE5); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE6); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE7); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE8); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE9); +} + +void EXTI15_10_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE10); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE11); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE12); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE13); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE14); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE15); +} diff --git a/drivers/hal/nationstech/drivers/drv_gpio.h b/drivers/hal/nationstech/drivers/n32g43x/drv_gpio.h similarity index 95% rename from drivers/hal/nationstech/drivers/drv_gpio.h rename to drivers/hal/nationstech/drivers/n32g43x/drv_gpio.h index e21611f5076c69ec6a58b687be66c8261a7ad329..bc074d22d8e507f242c8749fcd80dd4a6ec4c33b 100644 --- a/drivers/hal/nationstech/drivers/drv_gpio.h +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_gpio.h @@ -24,7 +24,7 @@ #ifndef __DRV_GPIO_H__ #define __DRV_GPIO_H__ -#define GET_PIN(port, pin) (((port)<<8) + (pin)) +#define GET_PIN(port, pin) (((port) << 4) + ((pin) & 0x0F)) int os_hw_pin_init(void); diff --git a/drivers/hal/nationstech/drivers/drv_log.h b/drivers/hal/nationstech/drivers/n32g43x/drv_log.h similarity index 100% rename from drivers/hal/nationstech/drivers/drv_log.h rename to drivers/hal/nationstech/drivers/n32g43x/drv_log.h diff --git a/drivers/hal/nationstech/drivers/n32g43x/drv_spi.c b/drivers/hal/nationstech/drivers/n32g43x/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9837ee3f98d8ebac912919abd846776880e32e63 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_spi.c @@ -0,0 +1,381 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.spi" + +#include "drv_spi.h" + +#define SPI_USING_RX_DMA_FLAG (1 << 0) +#define SPI_USING_TX_DMA_FLAG (1 << 1) + +struct n32_spi_bus +{ + struct os_spi_bus spi_bus; + + SPI_Module *hspi; + const struct n32_spi_info *info; + + struct os_spi_configuration *cfg; + + uint8_t spi_dma_flag; + + os_list_node_t list; +}; + +static os_list_node_t n32_spi_list = OS_LIST_INIT(n32_spi_list); + +static os_err_t n32_spi_init(struct n32_spi_bus *spi_bus, struct os_spi_configuration *cfg) +{ + OS_ASSERT(spi_drv != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + GPIO_InitType ioinit; + GPIO_InitStruct(&ioinit); + + ioinit.Pin = spi_bus->info->sck_pin; + ioinit.GPIO_Speed = GPIO_Speed_50MHz; + ioinit.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(spi_bus->info->sck_port, &ioinit); + + ioinit.Pin = spi_bus->info->mosi_pin; + GPIO_InitPeripheral(spi_bus->info->mosi_port, &ioinit); + + ioinit.Pin = spi_bus->info->miso_pin; + ioinit.GPIO_Mode = GPIO_Mode_IPD; + GPIO_InitPeripheral(spi_bus->info->miso_port, &ioinit); + + + switch(spi_bus->info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(spi_bus->info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(spi_bus->info->rcc, ENABLE); + break; + default: + OS_ASSERT(false); + break; + } + + SPI_InitType init; + SPI_InitStruct(&init); + init.NSS = SPI_NSS_SOFT; + + SPI_Module *hspi = spi_bus->hspi; + + if (cfg->mode & OS_SPI_SLAVE) + { + init.SpiMode = SPI_MODE_SLAVE; + } + else + { + init.SpiMode = SPI_MODE_MASTER; + } + + if (cfg->mode & OS_SPI_3WIRE) + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + else + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + + if (cfg->data_width == 8) + { + init.DataLen = SPI_DATA_SIZE_8BITS; + } + else if (cfg->data_width == 16) + { + init.DataLen = SPI_DATA_SIZE_16BITS; + } + else + { + return OS_EIO; + } + + if (cfg->mode & OS_SPI_CPHA) + { + init.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + } + else + { + init.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + } + + if (cfg->mode & OS_SPI_CPOL) + { + init.CLKPOL = SPI_CLKPOL_HIGH; + } + else + { + init.CLKPOL = SPI_CLKPOL_LOW; + } + + if (cfg->mode & OS_SPI_MSB) + { + init.FirstBit = SPI_FB_MSB; + } + else + { + init.FirstBit = SPI_FB_LSB; + } + + // HCLK:100MHz, APB2 CLK: 50MHz 100MHz / 2 + init.BaudRatePres = SPI_BR_PRESCALER_32;//cfg->max_hz; + + SPI_Init(hspi, &init); + + SPI_Enable(hspi, ENABLE); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", spi_bus->spi_bus.parent.name); + return OS_SUCCESS; +} + +static os_err_t spi_configure(struct os_spi_device *device, struct os_spi_configuration *configuration) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(configuration != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + spi_bus->cfg = configuration; + + return n32_spi_init(spi_bus, configuration); +} + +/* clang-format off */ +static uint32_t spixfer(struct os_spi_device *device, struct os_spi_message *message) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(device->bus != OS_NULL); + OS_ASSERT(message != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + SPI_Module *hspi = spi_bus->hspi; + + if (message->cs_take + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_LOW); + } + + SPI_I2S_ReceiveData(hspi); + + // LOG_D(DBG_TAG, "%s transfer prepare and start", spi_drv->config->bus_name); + // LOG_D(DBG_TAG, + // "%s sendbuf: %X, recvbuf: %X, length: %d", + // spi_drv->config->bus_name, + // (uint32_t)message->send_buf, + // (uint32_t)message->recv_buf, + // message->length); + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + //ret = SPI_TransmitReceive_DMA SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else if (message->send_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + //ret = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + } + } + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + } + } + else if (message->recv_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + //ret = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else + { // 错误 message->send_buf、message->recv_buf 都是NULL + return 0; + } + + if (message->cs_release + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_HIGH); + } + + return message->length; +} +/* clang-format on */ + +static const struct os_spi_ops n32_spi_bus_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; + +static int n32_spi_bus_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + os_err_t result = 0; + os_base_t level; + + struct n32_spi_bus *spi_bus = os_calloc(1, sizeof(struct n32_spi_bus)); + + OS_ASSERT(nt_spi); + + spi_bus->info = dev->info; + + spi_bus->hspi = spi_bus->info->hspi; + + level = os_irq_lock(); + os_list_add_tail(&n32_spi_list, &spi_bus->list); + os_irq_unlock(level); + + result = os_spi_bus_register(&spi_bus->spi_bus, dev->name, &n32_spi_bus_ops); + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s bus init done\r\n", dev->name); + + return result; +} + +OS_DRIVER_INFO n32_spi_driver = { + .name = "SPI_Module", + .probe = n32_spi_bus_probe, +}; + +OS_DRIVER_DEFINE(n32_spi_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32g43x/drv_spi.h b/drivers/hal/nationstech/drivers/n32g43x/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..8f52de3fd80ba7bc2a991dfdaf3a578e7d2395b1 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_spi.h @@ -0,0 +1,61 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +#include "n32g45x.h" + +struct n32_spi_info +{ + SPI_Module *hspi; + int rcc_type; + int rcc; + IRQn_Type irq; + + struct + { + DMA_ChannelType *channel; + int rcc; + IRQn_Type irq; + }dma_rx, dma_tx; + + GPIO_Module *nss_port; + int nss_pin; + int nss_rcc; + + GPIO_Module *sck_port; + int sck_pin; + int sck_rcc; + + GPIO_Module *miso_port; + int miso_pin; + int miso_rcc; + + GPIO_Module *mosi_port; + int mosi_pin; + int mosi_rcc; +}; + +#endif /* __DRV_SPI_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32g43x/drv_usart.c b/drivers/hal/nationstech/drivers/n32g43x/drv_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..42847fefa74692753f2eb827b673be9c59d41505 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_usart.c @@ -0,0 +1,640 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.usart" +#include + +#include "drv_usart.h" + +typedef struct n32_usart +{ + struct os_serial_device serial; + + struct n32_usart_info *info; + + soft_dma_t sdma; + uint32_t sdma_hard_size; + + DMA_InitType DMA_InitStructure; + + uint8_t *rx_buff; + uint32_t rx_index; + uint32_t rx_size; + + const uint8_t *tx_buff; + uint32_t tx_count; + uint32_t tx_size; + + os_list_node_t list; +} n32_usart_t; + +static os_list_node_t n32_usart_list = OS_LIST_INIT(n32_usart_list); + +static const struct n32_usart_info *console_uart = OS_NULL; + +static void n32_usart_interrupt_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + OS_ASSERT(uart->rx_buff != OS_NULL); + OS_ASSERT(uart->rx_index < uart->rx_size); + + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + + uart->rx_buff[uart->rx_index++] = USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + if (uart->rx_index > 0) + { + soft_dma_timeout_irq(&uart->sdma); + } + } + + if (uart->rx_index == (uart->rx_size / 2)) + { + soft_dma_half_irq(&uart->sdma); + } + + if (uart->rx_index == uart->rx_size) + { + uart->rx_index = 0; + soft_dma_full_irq(&uart->sdma); + } +} + + +static void n32_usart_dma_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + soft_dma_timeout_irq(&uart->sdma); + } +} + +static void n32_usart_irq_callback(n32_usart_t *uart) +{ + /* rx */ + if (uart->info->dma_channel == OS_NULL) + { + n32_usart_interrupt_rx(uart); + } + else + { + n32_usart_dma_rx(uart); + } + + /* tx */ + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXDE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXDE); + + if (uart->tx_size > 0) + { + if (uart->tx_count == 0) + { + if (uart->info->send_start_hook) + { + uart->info->send_start_hook(); + } + } + + if (uart->tx_count < uart->tx_size) + USART_SendData(uart->info->huart, uart->tx_buff[uart->tx_count++]); + + if (uart->tx_count >= uart->tx_size) + { + uart->tx_size = 0; + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + os_hw_serial_isr_txdone((struct os_serial_device *)uart); + + USART_ConfigInt(uart->info->huart, USART_INT_TXC, ENABLE); + } + } + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXC) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXC); + USART_ConfigInt(uart->info->huart, USART_INT_TXC, DISABLE); + + if (uart->info->send_end_hook) + { + uart->info->send_end_hook(); + } + } +} + +static void usart_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + n32_usart_irq_callback(uart); + return; + } + } +} + +static void usart_dma_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + soft_dma_half_irq(&uart->sdma); + return; + } + } +} + +void USART1_IRQHandler(void) +{ +#ifdef USART1 + usart_irqhandler(USART1); +#endif +} + +void USART2_IRQHandler(void) +{ +#ifdef USART2 + usart_irqhandler(USART2); +#endif +} + +void USART3_IRQHandler(void) +{ +#ifdef USART3 + usart_irqhandler(USART3); +#endif +} + +void DMA_Channel5_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX5, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC5, DMA); + +#ifdef USART1 + usart_dma_irqhandler(USART1); +#endif +} + +void DMA_Channel6_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX6, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC6, DMA); + +#ifdef USART2 + usart_dma_irqhandler(USART2); +#endif +} + +void DMA_Channel3_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX3, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC3, DMA); + +#ifdef USART3 + usart_dma_irqhandler(USART3); +#endif +} + +/* interrupt rx mode */ +static uint32_t n32_sdma_int_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->rx_index; +} + +static os_err_t n32_sdma_int_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->rx_buff = buff; + uart->rx_index = 0; + uart->rx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_int_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + + return n32_sdma_int_get_index(dma); +} + +/* dma rx mode */ +static uint32_t n32_sdma_dma_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->sdma_hard_size - DMA_GetCurrDataCounter(uart->info->dma_channel); +} + +static os_err_t n32_sdma_dma_init(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + RCC_EnableAHBPeriphClk(uart->info->dma_rcc, ENABLE); + + uart->DMA_InitStructure.PeriphAddr = (uint32_t)&uart->info->huart->DAT; + uart->DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; + uart->DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE; + uart->DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + uart->DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + uart->DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Byte; + uart->DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR; + uart->DMA_InitStructure.Priority = DMA_PRIORITY_HIGH; + uart->DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE; + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + return OS_SUCCESS; +} + +static os_err_t n32_sdma_dma_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->sdma_hard_size = size; + + uart->DMA_InitStructure.MemAddr = (uint32_t)buff; + uart->DMA_InitStructure.BufSize = size; + + DMA_Init(uart->info->dma_channel, &uart->DMA_InitStructure); + DMA_EnableChannel(uart->info->dma_channel, ENABLE); + USART_EnableDMA(uart->info->huart, USART_DMAREQ_RX, ENABLE); + + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + DMA_ConfigInt(uart->info->dma_channel, DMA_INT_TXC | DMA_INT_HTX, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_dma_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + DMA_EnableChannel(uart->info->dma_channel, DISABLE); + + return n32_sdma_dma_get_index(dma); +} + +/* sdma callback */ +static void n32_usart_sdma_callback(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + os_hw_serial_isr_rxdone((struct os_serial_device *)uart); +} + +static void n32_usart_sdma_init(struct n32_usart *uart, dma_ring_t *ring) +{ + soft_dma_t *dma = &uart->sdma; + + soft_dma_stop(dma); + + memset(&dma->hard_info, 0, sizeof(dma->hard_info)); + + dma->hard_info.mode = HARD_DMA_MODE_CIRCULAR; + dma->hard_info.max_size = 64 * 1024; + dma->hard_info.flag = HARD_DMA_FLAG_HALF_IRQ | HARD_DMA_FLAG_FULL_IRQ | HARD_DMA_FLAG_TIMEOUT_IRQ; + dma->hard_info.data_timeout = uart_calc_byte_timeout_us(uart->serial.config.baud_rate); + + if (uart->info->dma_channel == OS_NULL) + { + dma->ops.get_index = n32_sdma_int_get_index; + dma->ops.dma_init = OS_NULL; + dma->ops.dma_start = n32_sdma_int_start; + dma->ops.dma_stop = n32_sdma_int_stop; + } + else + { + dma->ops.get_index = n32_sdma_dma_get_index; + dma->ops.dma_init = n32_sdma_dma_init; + dma->ops.dma_start = n32_sdma_dma_start; + dma->ops.dma_stop = n32_sdma_dma_stop; + } + + dma->cbs.dma_half_callback = n32_usart_sdma_callback; + dma->cbs.dma_full_callback = n32_usart_sdma_callback; + dma->cbs.dma_timeout_callback = n32_usart_sdma_callback; + + soft_dma_init(dma); + soft_dma_start(dma, ring); + soft_dma_irq_enable(&uart->sdma, OS_TRUE); +} + +static int __n32_usart_init(const struct n32_usart_info *uart_info, struct serial_configure *cfg) +{ + GPIO_InitType GPIO_InitStructure; + USART_InitType USART_InitStructure; + uint32_t data_bits; + + RCC_EnableAPB2PeriphClk(uart_info->tx_rcc, ENABLE); + RCC_EnableAPB2PeriphClk(uart_info->rx_rcc, ENABLE); + + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStructure.Pin = uart_info->tx_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(uart_info->tx_port, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = uart_info->rx_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input; + GPIO_InitPeripheral(uart_info->rx_port, &GPIO_InitStructure); + + USART_InitStructure.BaudRate = cfg->baud_rate; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.StopBits = USART_STPB_1; + break; + case STOP_BITS_2: + USART_InitStructure.StopBits = USART_STPB_2; + break; + default: + return OS_INVAL; + } + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.Parity = USART_PE_NO; + data_bits = cfg->data_bits; + break; + case PARITY_ODD: + USART_InitStructure.Parity = USART_PE_ODD; + data_bits = cfg->data_bits + 1; + break; + case PARITY_EVEN: + USART_InitStructure.Parity = USART_PE_EVEN; + data_bits = cfg->data_bits + 1; + break; + default: + return OS_INVAL; + } + + switch (data_bits) + { + case DATA_BITS_8: + USART_InitStructure.WordLength = USART_WL_8B; + break; + case DATA_BITS_9: + USART_InitStructure.WordLength = USART_WL_9B; + break; + default: + return OS_INVAL; + } + + switch(uart_info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(uart_info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(uart_info->rcc, ENABLE); + break; + } + + USART_DeInit(uart_info->huart); + USART_Init(uart_info->huart, &USART_InitStructure); + USART_ConfigInt(uart_info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart_info->huart, USART_INT_RXDNE, DISABLE); + USART_Enable(uart_info->huart, ENABLE); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_init(struct os_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + __n32_usart_init(uart->info, cfg); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + n32_usart_sdma_init(uart, &serial->rx_fifo->ring); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_deinit(struct os_serial_device *serial) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + /* rx */ + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + + if (uart->info->dma_channel != OS_NULL) + { + soft_dma_stop(&uart->sdma); + DMA_DeInit(uart->info->dma_channel); + } + + /* tx */ + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + + uart->tx_buff = OS_NULL; + uart->tx_count = 0; + uart->tx_size = 0; + + return 0; +} + +static int n32_uart_start_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + uart->tx_buff = buff; + uart->tx_count = 0; + uart->tx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, ENABLE); + + return size; +} + +/* clang-format off */ +static int n32_usart_poll_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + int i; + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + for (i = 0; i < size; i++) + { + while (USART_GetFlagStatus(uart->info->huart, USART_FLAG_TXC) == RESET); + USART_SendData(uart->info->huart, buff[i]); + } + + return size; +} +/* clang-format on */ + +static const struct os_uart_ops n32_usart_ops = { + .init = n32_usart_init, + .deinit = n32_usart_deinit, + + .start_send = n32_uart_start_send, + .poll_send = n32_usart_poll_send, +}; + +static int n32_usart_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + os_err_t result = 0; + os_base_t level; + + struct n32_usart *uart = os_calloc(1, sizeof(struct n32_usart)); + + OS_ASSERT(uart); + + uart->info = (void*)dev->info; + + struct os_serial_device *serial = &uart->serial; + + serial->ops = &n32_usart_ops; + serial->config = config; + + level = os_irq_lock(); + os_list_add_tail(&n32_usart_list, &uart->list); + os_irq_unlock(level); + + result = os_hw_serial_register(serial, dev->name, NULL); + + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", dev->name); + + return result; +} + +/* clang-format off */ +void __os_hw_console_output(char *str) +{ + int i; + + if (console_uart == OS_NULL) + return; + + for (i = 0; i < strlen(str); i++) + { + while (USART_GetFlagStatus(console_uart->huart, USART_FLAG_TXC) == RESET); + USART_SendData(console_uart->huart, str[i]); + } +} +/* clang-format on */ + +OS_DRIVER_INFO n32_usart_driver = { + .name = "USART_Module", + .probe = n32_usart_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); + +static int n32_usart_early_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + if (strcmp(dev->name, OS_CONSOLE_DEVICE_NAME)) + return OS_SUCCESS; + + console_uart = (const struct n32_usart_info *)dev->info; + + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + __n32_usart_init(console_uart, &config); + + return OS_SUCCESS; +} + +OS_DRIVER_INFO n32_usart_early_driver = { + .name = "USART_Module", + .probe = n32_usart_early_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_early_driver, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32g43x/drv_usart.h b/drivers/hal/nationstech/drivers/n32g43x/drv_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..49bd3889401fcf624adba0ee4ec3850bf44d7a9d --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/drv_usart.h @@ -0,0 +1,64 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +struct n32_usart_info +{ + USART_Module *huart; + int rcc_type; + int rcc; + IRQn_Type irq; + + DMA_ChannelType *dma_channel; + int dma_rcc; + IRQn_Type dma_irq; + + GPIO_Module *tx_port; + int tx_pin; + int tx_rcc; + + GPIO_Module *rx_port; + int rx_pin; + int rx_rcc; + + void (*init_hook)(); + void (*send_start_hook)(void); + void (*send_end_hook)(void); +}; + +#endif /* __DRV_USART_H__ */ diff --git a/drivers/hal/nationstech/drivers/flash/drv_flash.c b/drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.c similarity index 98% rename from drivers/hal/nationstech/drivers/flash/drv_flash.c rename to drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.c index c9f990469a9e65755e6dcde0b85734a67be2e45d..69dcee0c93f300428df2a970782fac835dc4b0ed 100644 --- a/drivers/hal/nationstech/drivers/flash/drv_flash.c +++ b/drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.c @@ -11,7 +11,7 @@ * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * - * @file drv_flash.c + * @file drv_flash_common.c * * @brief This file provides flash read/write/erase functions for N32. * @@ -71,7 +71,7 @@ int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size) if (size < 1) { - return OS_FAILURE; + return OS_INVAL; } for (i = 0; i < size;) diff --git a/drivers/hal/nationstech/drivers/flash/drv_flash.h b/drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.h similarity index 98% rename from drivers/hal/nationstech/drivers/flash/drv_flash.h rename to drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.h index b99f7e1fdee725d8b4bd6e6fd03f113a97f0443d..858a52838ca87e753923bdb557496e316c234563 100644 --- a/drivers/hal/nationstech/drivers/flash/drv_flash.h +++ b/drivers/hal/nationstech/drivers/n32g43x/flash/drv_flash.h @@ -27,8 +27,6 @@ #include "drv_cfg.h" #include -#include "n32g45x_hal.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/drivers/hal/nationstech/drivers/flash/fal_drv_flash.c b/drivers/hal/nationstech/drivers/n32g43x/flash/fal_drv_flash.c similarity index 94% rename from drivers/hal/nationstech/drivers/flash/fal_drv_flash.c rename to drivers/hal/nationstech/drivers/n32g43x/flash/fal_drv_flash.c index 19af4ffb031ae1e1a2630c134f9e021068ac9561..796e9446d5084670f2508bf960e2721dd4e491e5 100644 --- a/drivers/hal/nationstech/drivers/flash/fal_drv_flash.c +++ b/drivers/hal/nationstech/drivers/n32g43x/flash/fal_drv_flash.c @@ -66,9 +66,8 @@ static int n32_flash_probe(const os_driver_info_t *drv, const os_device_info_t * } OS_DRIVER_INFO n32_flash_driver = { - .name = "N32G452_Onchip_Flash", + .name = "N32G43X_Onchip_Flash", .probe = n32_flash_probe, }; -OS_DRIVER_DEFINE(n32_flash_driver, OS_INIT_LEVEL_DEVICE, OS_INIT_SUBLEVEL_HIGH); - +OS_DRIVER_DEFINE(n32_flash_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); diff --git a/drivers/hal/beken/beken72XX_HAL/func/vad/beken_vad/weave.yaml b/drivers/hal/nationstech/drivers/n32g43x/flash/weave.yaml similarity index 41% rename from drivers/hal/beken/beken72XX_HAL/func/vad/beken_vad/weave.yaml rename to drivers/hal/nationstech/drivers/n32g43x/flash/weave.yaml index 5a6a035fe65ca0adf154cc82bde358634159798a..7912c209f51b95324783ded1ee7b081e7acc66ad 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/vad/beken_vad/weave.yaml +++ b/drivers/hal/nationstech/drivers/n32g43x/flash/weave.yaml @@ -1,21 +1,15 @@ # 组名 -group_name: beken_vad +group_name: hal/drivers # 依赖宏控 depend_macro: - - BUILD_LIB + - MANUFACTOR_NATIONSTECH # 编译连接信息 build_option: cpppath: - - . - libs: - - vad - libpath: - - . - libname: - - libvad.a + - . ? {is_define("BSP_USING_ONCHIP_FLASH")} # 源码 source_file: - - ./*.c + - drv_flash.c ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32_it.c b/drivers/hal/nationstech/drivers/n32g43x/n32_it.c similarity index 94% rename from drivers/hal/nationstech/drivers/n32_it.c rename to drivers/hal/nationstech/drivers/n32g43x/n32_it.c index 820d286d429a40b060d171a2fae13b9d43be2cfb..25e7b16e49a9e347ba0d0d4a18893bc2827b36c6 100644 --- a/drivers/hal/nationstech/drivers/n32_it.c +++ b/drivers/hal/nationstech/drivers/n32g43x/n32_it.c @@ -71,12 +71,3 @@ void UsageFault_Handler(void) /* Go to infinite loop when Usage Fault exception occurs */ while (1); } - -void SysTick_Handler(void) -{ - os_tick_increase(); - -#ifdef OS_USING_CLOCKSOURCE - os_clocksource_update(); -#endif -} diff --git a/drivers/hal/nationstech/drivers/n32_it.h b/drivers/hal/nationstech/drivers/n32g43x/n32_it.h similarity index 92% rename from drivers/hal/nationstech/drivers/n32_it.h rename to drivers/hal/nationstech/drivers/n32g43x/n32_it.h index 32f7354e189aef00072bfde99947523b6957c946..ee875664d40ff94b5c3aa75b5b93df07cfcb8413 100644 --- a/drivers/hal/nationstech/drivers/n32_it.h +++ b/drivers/hal/nationstech/drivers/n32g43x/n32_it.h @@ -11,7 +11,7 @@ * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * - * @file n32_it.h + * @file apm32_it.h * * @brief This file provides systick IRQ declaration. * @@ -25,7 +25,13 @@ #include +#ifdef SERIES_N32G4XX #include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/drivers/hal/nationstech/drivers/n32g43x/weave.yaml b/drivers/hal/nationstech/drivers/n32g43x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8d7a65150d1ed0453a678c1dcc94f49142aa4160 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g43x/weave.yaml @@ -0,0 +1,24 @@ +# 组名 +group_name: hal/drivers + +# 依赖宏控 +depend_macro: + - SERIES_N32G43X + +# 编译连接信息 +build_option: + cpppath: + - . + +# 源码 +source_file: + - drv_common.c + - n32_it.c + - drv_gpio.c ? {is_define("BSP_USING_GPIO")} + - drv_usart.c ? {is_define("BSP_USING_USART")} + - drv_adc.c ? {is_define("BSP_USING_ADC")} + - drv_spi.c ? {is_define("BSP_USING_SPI")} + +# 子目录 +add_subdirectory: + - flash ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_common.c b/drivers/hal/nationstech/drivers/n32g45x/drv_common.c new file mode 100644 index 0000000000000000000000000000000000000000..19b702f431f0228a78b3bcfe34ab3b86b2af194d --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_common.c @@ -0,0 +1,192 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.c + * + * @brief This file provides systick time init/IRQ and board init functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "n32_it.h" +#include "board.h" +#include "drv_gpio.h" + +#ifdef OS_USING_DMA +#include +#endif + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#include + +static volatile os_bool_t hardware_init_done = OS_FALSE; + +void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +void os_tick_handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + +void SysTick_Handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +static void cortexm_systick_kernel_tick_init(void) +{ + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; + + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +#endif + +#if defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) +void SysTick_Handler(void) +{ + if (hardware_init_done) + { + cortexm_systick_clockevent_isr(); + } + else + { + os_tick_handler(); + } +} +#endif + +void hardware_init(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); // 不能是NVIC_PriorityGroup_0, 否则SVC指令会产生硬件错误(Group0所有位为响应优先级,没有抢占) + + + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL = 0; + NVIC_SetPriority(SysTick_IRQn, 0xFF); + NVIC_EnableIRQ(SysTick_IRQn); + + SysTick->LOAD = 10000; /* set reload register */ + SysTick->VAL = 0UL; /* Load the systick Counter Value */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk;; + + +} + +void os_hw_cpu_reset(void) +{ + NVIC_SystemReset(); +} + +/** + *********************************************************************************************************************** + * @brief This function will initial STM32 board. + * + * @param[in] none + * + * @return none + *********************************************************************************************************************** + */ +static os_err_t os_hw_board_init(void) +{ + hardware_init(); + os_irq_enable(); + HAL_SuspendTick(); + +#ifdef HAL_SDRAM_MODULE_ENABLED + SDRAM_Init(); +#endif + + /* Heap initialization */ +#if defined(OS_USING_DEFAULT_HEAP) + if ((os_size_t)HEAP_END > (os_size_t)HEAP_BEGIN) + { + os_default_heap_init(); + os_default_heap_add((void *)HEAP_BEGIN, (os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN, OS_MEM_ALG_DEFAULT); + } +#endif + +#ifdef OS_USING_DMA_RAM + os_dma_mem_init(); +#endif + + return OS_SUCCESS; +} +OS_INIT_CALL(os_hw_board_init, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_MIDDLE); + +void cortexm_systick_init(void) +{ +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + cortexm_systick_kernel_tick_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKSOURCE) + cortexm_systick_clocksource_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) + cortexm_systick_clockevent_init(); +#endif +} + +static os_err_t board_post_init(void) +{ +#ifdef OS_USING_PIN + os_hw_pin_init(); +#endif + +#if defined(OS_USING_DWT_FOR_CLOCKSOURCE) && defined(DWT) + cortexm_dwt_init(); +#endif + + // calc_mult_shift(&mult_systick2msec, &shift_systick2msec, OS_TICK_PER_SECOND, 1000, 1); + + cortexm_systick_init(); + + //os_bsp_init(); + + hardware_init_done = OS_TRUE; + + return OS_SUCCESS; +} + +OS_INIT_CALL(board_post_init, OS_INIT_LEVEL_POST_KERNEL, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_common.h b/drivers/hal/nationstech/drivers/n32g45x/drv_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f76a5a8303b90836164853d86569e0cb9ae26ec0 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_common.h @@ -0,0 +1,54 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.h + * + * @brief This file provides declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_conf.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_conf.h" +#endif + +#ifdef SERIES_N32L43X +#include "n32l43x_conf.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/drv_gpio.c b/drivers/hal/nationstech/drivers/n32g45x/drv_gpio.c similarity index 90% rename from drivers/hal/nationstech/drivers/drv_gpio.c rename to drivers/hal/nationstech/drivers/n32g45x/drv_gpio.c index 3e5ce2bf56c962a7a572c24943249c84f4176868..c826e1fcd13b872998d3309bddde6f74f4d9bad8 100644 --- a/drivers/hal/nationstech/drivers/drv_gpio.c +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_gpio.c @@ -29,10 +29,16 @@ #include "drv_gpio.h" +#ifdef SERIES_N32G4XX #include "n32g45x_hal.h" +#endif -#define N32_PORT(pin) ((pin) >> 8) -#define N32_PIN(pin) ((pin) & 0xFF) +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#define N32_PORT(pin) ((pin) >> 4) +#define N32_PIN(pin) ((pin) & 0x0F) struct n32_pin_irq { @@ -189,25 +195,25 @@ static void n32_pin_mode(os_device_t *dev, os_base_t pin, os_base_t mode) static os_err_t n32_pin_attach_irq(struct os_device *device, int32_t pin, uint32_t mode, void (*hdr)(void *args), void *args) { - os_ubase_t level; + os_base_t level; int Pin = N32_PIN(pin); OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); - os_spin_lock_irqsave(&gs_device_lock, &level); + level = os_irq_lock(); if (n32_pin_irq_hdr_tab[Pin].pin == pin && n32_pin_irq_hdr_tab[Pin].hdr == hdr && n32_pin_irq_hdr_tab[Pin].mode == mode && n32_pin_irq_hdr_tab[Pin].args == args) { - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); return OS_SUCCESS; } if (n32_pin_irq_hdr_tab[Pin].pin != -1) { - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); return OS_BUSY; } @@ -216,25 +222,25 @@ static os_err_t n32_pin_attach_irq(struct os_device *device, int32_t pin, uint32 n32_pin_irq_hdr_tab[Pin].mode = mode; n32_pin_irq_hdr_tab[Pin].args = args; - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); return OS_SUCCESS; } static os_err_t n32_pin_detach_irq(struct os_device *device, int32_t pin) { - os_ubase_t level; + os_base_t level; int Pin = N32_PIN(pin); OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); - os_spin_lock_irqsave(&gs_device_lock, &level); + level = os_irq_lock(); if (n32_pin_irq_hdr_tab[Pin].pin == -1) { - os_spin_unlock_irqrestore(&gs_device_lock, level); - return OS_SUCCESS; + os_irq_unlock(level); + return OS_INVAL; } n32_pin_irq_hdr_tab[Pin].pin = -1; @@ -242,14 +248,14 @@ static os_err_t n32_pin_detach_irq(struct os_device *device, int32_t pin) n32_pin_irq_hdr_tab[Pin].mode = 0; n32_pin_irq_hdr_tab[Pin].args = OS_NULL; - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); return OS_SUCCESS; } static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint32_t enabled) { - os_ubase_t level; + os_base_t level; const struct n32_pin_irq *irqmap; int Port = N32_PORT(pin); @@ -260,12 +266,12 @@ static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint if (enabled == PIN_IRQ_ENABLE) { - os_spin_lock_irqsave(&gs_device_lock, &level); + level = os_irq_lock(); if (n32_pin_irq_hdr_tab[Pin].pin == -1) { - os_spin_unlock_irqrestore(&gs_device_lock, level); - return OS_NOSYS; + os_irq_unlock(level); + return OS_ENOSYS; } irqmap = &n32_pin_irq[Pin]; @@ -289,8 +295,8 @@ static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint case PIN_IRQ_MODE_HIGH_LEVEL: case PIN_IRQ_MODE_LOW_LEVEL: default: - os_spin_unlock_irqrestore(&gs_device_lock, level); - return OS_FAILURE; + os_irq_unlock(level); + return OS_INVAL; } GPIO_ConfigEXTILine(GPIOA_PORT_SOURCE + Port, GPIO_PIN_SOURCE0 + Pin); @@ -304,11 +310,11 @@ static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); } else if (enabled == PIN_IRQ_DISABLE) { - os_spin_lock_irqsave(&gs_device_lock, &level); + level = os_irq_lock(); EXTI_InitType EXTI_InitStructure; EXTI_InitStructure.EXTI_Line = irqmap->pinbit; @@ -317,11 +323,11 @@ static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint EXTI_InitStructure.EXTI_LineCmd = DISABLE; EXTI_InitPeripheral(&EXTI_InitStructure); - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); } else { - return OS_NOSYS; + return OS_ENOSYS; } return OS_SUCCESS; diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_gpio.h b/drivers/hal/nationstech/drivers/n32g45x/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..bc074d22d8e507f242c8749fcd80dd4a6ec4c33b --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_gpio.h @@ -0,0 +1,31 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.h + * + * @brief This file provides struct/macro declaration and functions declaration for apm32 gpio driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#define GET_PIN(port, pin) (((port) << 4) + ((pin) & 0x0F)) + +int os_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_log.h b/drivers/hal/nationstech/drivers/n32g45x/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..104db27e69dcc4f4dc5f2e764b88a96223cf00c8 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_log.h @@ -0,0 +1,36 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_log.h + * + * @brief This file defines driver log with specific level and tag. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef DRV_EXT_TAG +#define DBG_EXT_TAG "drv" +#else +#define DBG_EXT_TAG DRV_EXT_TAG +#endif /* DRV_EXT_TAG */ + +#ifdef DRV_EXT_LVL +#define DBG_EXT_LVL DRV_EXT_LVL +#else +#define DBG_EXT_LVL DBG_EXT_INFO +#endif /* DRV_EXT_LVL */ + +#include diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_spi.c b/drivers/hal/nationstech/drivers/n32g45x/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..a2e5745790aac77b238d5c7dd8c3c357b3a3af13 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_spi.c @@ -0,0 +1,384 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.spi" + +#include "drv_spi.h" + +#define SPI_USING_RX_DMA_FLAG (1 << 0) +#define SPI_USING_TX_DMA_FLAG (1 << 1) + +struct n32_spi_bus +{ + struct os_spi_bus spi_bus; + + SPI_Module *hspi; + const struct n32_spi_info *info; + + struct os_spi_configuration *cfg; + + uint8_t spi_dma_flag; + + os_list_node_t list; +}; + +static os_list_node_t n32_spi_list = OS_LIST_INIT(n32_spi_list); + +static os_err_t n32_spi_init(struct n32_spi_bus *spi_bus, struct os_spi_configuration *cfg) +{ + OS_ASSERT(spi_drv != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + GPIO_InitType ioinit; + GPIO_InitStruct(&ioinit); + + ioinit.Pin = spi_bus->info->nss_pin; + ioinit.GPIO_Speed = GPIO_Speed_50MHz; + ioinit.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(spi_bus->info->nss_port, &ioinit); + + ioinit.Pin = spi_bus->info->sck_pin; + GPIO_InitPeripheral(spi_bus->info->sck_port, &ioinit); + + ioinit.Pin = spi_bus->info->mosi_pin; + GPIO_InitPeripheral(spi_bus->info->mosi_port, &ioinit); + + ioinit.Pin = spi_bus->info->miso_pin; + ioinit.GPIO_Mode = GPIO_Mode_IPD; + GPIO_InitPeripheral(spi_bus->info->miso_port, &ioinit); + + + switch(spi_bus->info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(spi_bus->info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(spi_bus->info->rcc, ENABLE); + break; + default: + OS_ASSERT(false); + break; + } + + SPI_InitType init; + SPI_InitStruct(&init); + init.NSS = SPI_NSS_SOFT; + + SPI_Module *hspi = spi_bus->hspi; + + if (cfg->mode & OS_SPI_SLAVE) + { + init.SpiMode = SPI_MODE_SLAVE; + } + else + { + init.SpiMode = SPI_MODE_MASTER; + } + + if (cfg->mode & OS_SPI_3WIRE) + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + else + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + + if (cfg->data_width == 8) + { + init.DataLen = SPI_DATA_SIZE_8BITS; + } + else if (cfg->data_width == 16) + { + init.DataLen = SPI_DATA_SIZE_16BITS; + } + else + { + return OS_EIO; + } + + if (cfg->mode & OS_SPI_CPHA) + { + init.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + } + else + { + init.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + } + + if (cfg->mode & OS_SPI_CPOL) + { + init.CLKPOL = SPI_CLKPOL_HIGH; + } + else + { + init.CLKPOL = SPI_CLKPOL_LOW; + } + + if (cfg->mode & OS_SPI_MSB) + { + init.FirstBit = SPI_FB_MSB; + } + else + { + init.FirstBit = SPI_FB_LSB; + } + + // HCLK:100MHz, APB2 CLK: 50MHz 100MHz / 2 + init.BaudRatePres = SPI_BR_PRESCALER_32;//cfg->max_hz; + + SPI_Init(hspi, &init); + + SPI_Enable(hspi, ENABLE); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", spi_bus->spi_bus.parent.name); + return OS_SUCCESS; +} + +static os_err_t spi_configure(struct os_spi_device *device, struct os_spi_configuration *configuration) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(configuration != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + spi_bus->cfg = configuration; + + return n32_spi_init(spi_bus, configuration); +} + +/* clang-format off */ +static uint32_t spixfer(struct os_spi_device *device, struct os_spi_message *message) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(device->bus != OS_NULL); + OS_ASSERT(message != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + SPI_Module *hspi = spi_bus->hspi; + + if (message->cs_take + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_LOW); + } + + SPI_I2S_ReceiveData(hspi); + + // LOG_D(DBG_TAG, "%s transfer prepare and start", spi_drv->config->bus_name); + // LOG_D(DBG_TAG, + // "%s sendbuf: %X, recvbuf: %X, length: %d", + // spi_drv->config->bus_name, + // (uint32_t)message->send_buf, + // (uint32_t)message->recv_buf, + // message->length); + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + //ret = SPI_TransmitReceive_DMA SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else if (message->send_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + //ret = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + } + } + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + } + } + else if (message->recv_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + //ret = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else + { // 错误 message->send_buf、message->recv_buf 都是NULL + return 0; + } + + if (message->cs_release + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_HIGH); + } + + return message->length; +} +/* clang-format on */ + +static const struct os_spi_ops n32_spi_bus_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; + +static int n32_spi_bus_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + os_err_t result = 0; + os_base_t level; + + struct n32_spi_bus *spi_bus = os_calloc(1, sizeof(struct n32_spi_bus)); + + OS_ASSERT(nt_spi); + + spi_bus->info = dev->info; + + spi_bus->hspi = spi_bus->info->hspi; + + level = os_irq_lock(); + os_list_add_tail(&n32_spi_list, &spi_bus->list); + os_irq_unlock(level); + + result = os_spi_bus_register(&spi_bus->spi_bus, dev->name, &n32_spi_bus_ops); + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s bus init done\r\n", dev->name); + + return result; +} + +OS_DRIVER_INFO n32_spi_driver = { + .name = "SPI_Module", + .probe = n32_spi_bus_probe, +}; + +OS_DRIVER_DEFINE(n32_spi_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32g45x/drv_spi.h b/drivers/hal/nationstech/drivers/n32g45x/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..8f52de3fd80ba7bc2a991dfdaf3a578e7d2395b1 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_spi.h @@ -0,0 +1,61 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +#include "n32g45x.h" + +struct n32_spi_info +{ + SPI_Module *hspi; + int rcc_type; + int rcc; + IRQn_Type irq; + + struct + { + DMA_ChannelType *channel; + int rcc; + IRQn_Type irq; + }dma_rx, dma_tx; + + GPIO_Module *nss_port; + int nss_pin; + int nss_rcc; + + GPIO_Module *sck_port; + int sck_pin; + int sck_rcc; + + GPIO_Module *miso_port; + int miso_pin; + int miso_rcc; + + GPIO_Module *mosi_port; + int mosi_pin; + int mosi_rcc; +}; + +#endif /* __DRV_SPI_H__ */ diff --git a/drivers/hal/nationstech/drivers/drv_usart.c b/drivers/hal/nationstech/drivers/n32g45x/drv_usart.c similarity index 95% rename from drivers/hal/nationstech/drivers/drv_usart.c rename to drivers/hal/nationstech/drivers/n32g45x/drv_usart.c index acb8e4a5d5f8b2c44488c1a940aac9ca9a844b0d..ba4557dd64b46a4dc3439579ff04528f2ca3a0d4 100644 --- a/drivers/hal/nationstech/drivers/drv_usart.c +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_usart.c @@ -52,7 +52,7 @@ typedef struct n32_usart const uint8_t *tx_buff; uint32_t tx_count; uint32_t tx_size; - + os_list_node_t list; } n32_usart_t; @@ -130,9 +130,17 @@ static void n32_usart_irq_callback(n32_usart_t *uart) if (USART_GetIntStatus(uart->info->huart, USART_INT_TXDE) != RESET) { USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXDE); - + if (uart->tx_size > 0) { + if (uart->tx_count == 0) + { + if (uart->info->send_start_hook) + { + uart->info->send_start_hook(uart); + } + } + if (uart->tx_count < uart->tx_size) USART_SendData(uart->info->huart, uart->tx_buff[uart->tx_count++]); @@ -141,9 +149,22 @@ static void n32_usart_irq_callback(n32_usart_t *uart) uart->tx_size = 0; USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); os_hw_serial_isr_txdone((struct os_serial_device *)uart); + + USART_ConfigInt(uart->info->huart, USART_INT_TXC, ENABLE); } } } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXC) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXC); + USART_ConfigInt(uart->info->huart, USART_INT_TXC, DISABLE); + + if (uart->info->send_end_hook) + { + uart->info->send_end_hook(uart); + } + } } static void usart_irqhandler(USART_Module *huart) @@ -382,11 +403,11 @@ static int __n32_usart_init(const struct n32_usart_info *uart_info, struct seria GPIO_InitStructure.Pin = uart_info->rx_pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_InitPeripheral(uart_info->rx_port, &GPIO_InitStructure); - + USART_InitStructure.BaudRate = cfg->baud_rate; USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - + switch (cfg->stop_bits) { case STOP_BITS_1: @@ -466,6 +487,11 @@ static os_err_t n32_usart_init(struct os_serial_device *serial, struct serial_co NVIC_Init(&NVIC_InitStructure); n32_usart_sdma_init(uart, &serial->rx_fifo->ring); + + if (uart->info->init_hook) + { + uart->info->init_hook(uart); + } return OS_SUCCESS; } @@ -548,7 +574,7 @@ static int n32_usart_probe(const os_driver_info_t *drv, const os_device_info_t * struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; os_err_t result = 0; - os_ubase_t level; + os_base_t level; struct n32_usart *uart = os_calloc(1, sizeof(struct n32_usart)); @@ -561,13 +587,15 @@ static int n32_usart_probe(const os_driver_info_t *drv, const os_device_info_t * serial->ops = &n32_usart_ops; serial->config = config; - os_spin_lock_irqsave(&gs_device_lock, &level); + level = os_irq_lock(); os_list_add_tail(&n32_usart_list, &uart->list); - os_spin_unlock_irqrestore(&gs_device_lock, level); + os_irq_unlock(level); result = os_hw_serial_register(serial, dev->name, NULL); - OS_ASSERT(result == OS_SUCCESS); + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", dev->name); return result; } @@ -615,4 +643,3 @@ OS_DRIVER_INFO n32_usart_early_driver = { }; OS_DRIVER_DEFINE(n32_usart_early_driver, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_LOW); - diff --git a/drivers/hal/nationstech/drivers/drv_usart.h b/drivers/hal/nationstech/drivers/n32g45x/drv_usart.h similarity index 92% rename from drivers/hal/nationstech/drivers/drv_usart.h rename to drivers/hal/nationstech/drivers/n32g45x/drv_usart.h index f196ba6286e319ac0f23b2ddccabc14347421a1e..a678ab333ac7a945a6cd3bf0621fa49363ebf2db 100644 --- a/drivers/hal/nationstech/drivers/drv_usart.h +++ b/drivers/hal/nationstech/drivers/n32g45x/drv_usart.h @@ -25,7 +25,7 @@ #include -#include "n32g45x_hal.h" +#include "drv_common.h" struct n32_usart_info { @@ -45,6 +45,10 @@ struct n32_usart_info GPIO_Module *rx_port; int rx_pin; int rx_rcc; + + void (*init_hook)(void*); + void (*send_start_hook)(void*); + void (*send_end_hook)(void*); }; #endif /* __DRV_USART_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.c b/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..69dcee0c93f300428df2a970782fac835dc4b0ed --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.c @@ -0,0 +1,167 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash_common.c + * + * @brief This file provides flash read/write/erase functions for N32. + * + * @revision + * Date Author Notes + * 2022-01-11 OneOS Team First Version + *********************************************************************************************************************** + */ +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.flash" +#include + +#include "drv_flash.h" + +#define N32_FLASH_BLOCK_SIZE (2 * 1024) +#define N32_FLASH_PAGE_SIZE (2 * 1024) + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size) +{ + size_t i; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(uint8_t *)addr; + } + + return size; +} + +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size) +{ + size_t i, j; + os_err_t result = 0; + uint32_t write_data = 0, temp_data = 0; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: write outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + if (addr % 4 != 0) + { + LOG_E(DRV_EXT_TAG, "write addr must be 4-byte alignment"); + return OS_INVAL; + } + + FLASH_Unlock(); + + if (size < 1) + { + return OS_INVAL; + } + + for (i = 0; i < size;) + { + if ((size - i) < 4) + { + for (j = 0; (size - i) > 0; i++, j++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + else + { + for (j = 0; j < 4; j++, i++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + + /* write data */ + if (FLASH_ProgramWord(addr, write_data) == FLASH_COMPL) + { + /* Check the written value */ + if (*(uint32_t *)addr != write_data) + { + LOG_E(DRV_EXT_TAG, "ERROR: write data != read data"); + result = OS_FAILURE; + goto __exit; + } + } + else + { + result = OS_FAILURE; + goto __exit; + } + + temp_data = 0; + write_data = 0; + + addr += 4; + } + +__exit: + FLASH_Lock(); + if (result != 0) + { + return result; + } + + return size; +} + +int n32_flash_erase(uint32_t addr, size_t size) +{ + os_err_t result = OS_SUCCESS; + + const uint32_t page_addr_mask = ~(N32_FLASH_PAGE_SIZE - 1); + uint32_t end_addr = addr + size; + + if (end_addr > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: erase outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + FLASH_Unlock(); + + for (uint32_t page = addr & page_addr_mask; page < end_addr; page+=N32_FLASH_PAGE_SIZE) + { + if (FLASH_EraseOnePage(page) != FLASH_COMPL) + { + result = OS_FAILURE; + goto __exit; + } + } + +__exit: + FLASH_Lock(); + + if (result != OS_SUCCESS) + { + return result; + } + + LOG_D(DRV_EXT_TAG, "erase done: addr (0x%p), size %d", (void *)addr, size); + return size; +} + +#include "fal_drv_flash.c" diff --git a/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.h b/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..858a52838ca87e753923bdb557496e316c234563 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/flash/drv_flash.h @@ -0,0 +1,42 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash.h + * + * @brief This file provides declaration for flash functions. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_FLASH_H__ +#define __DRV_FLASH_H__ + +#include "drv_cfg.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size); +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size); +int n32_flash_erase(uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32g45x/flash/fal_drv_flash.c b/drivers/hal/nationstech/drivers/n32g45x/flash/fal_drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..ffb6f5c82b66b91538ede3a2061e2dbfa4c3dca6 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/flash/fal_drv_flash.c @@ -0,0 +1,73 @@ +#include "string.h" +#include +#include +#include "dlog.h" + +#include "drv_flash.h" + +#if defined(OS_USING_FAL) +#include "fal.h" +#include "ports/flash_info.c" +#endif + +static int n32_fal_flash_read(fal_flash_t *flash, uint32_t page_addr, uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_read(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_write(fal_flash_t *flash, uint32_t page_addr, const uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_write(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_erase(fal_flash_t *flash, uint32_t page_addr, uint32_t page_nr) +{ + int count = n32_flash_erase(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_flash_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + fal_flash_t *fal_flash = os_calloc(1, sizeof(fal_flash_t)); + + if (fal_flash == OS_NULL) + { + os_kprintf("fal flash mem leak %s.\r\n", dev->name); + return -1; + } + + struct onchip_flash_info *flash_info = (struct onchip_flash_info *)dev->info; + + memcpy(fal_flash->name, dev->name, min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))); + + fal_flash->name[min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))] = 0; + + fal_flash->capacity = flash_info->capacity; + fal_flash->block_size = flash_info->block_size; + fal_flash->page_size = flash_info->page_size; + + fal_flash->ops.read_page = n32_fal_flash_read; + fal_flash->ops.write_page = n32_fal_flash_write; + fal_flash->ops.erase_block = n32_fal_flash_erase; + + fal_flash->priv = flash_info; + + return fal_flash_register(fal_flash); +} + +OS_DRIVER_INFO n32_flash_driver = { + .name = "N32G45X_Onchip_Flash", + .probe = n32_flash_probe, +}; + +OS_DRIVER_DEFINE(n32_flash_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); diff --git a/drivers/hal/beken/beken72XX_HAL/func/sensor/beken_sensor/weave.yaml b/drivers/hal/nationstech/drivers/n32g45x/flash/weave.yaml similarity index 40% rename from drivers/hal/beken/beken72XX_HAL/func/sensor/beken_sensor/weave.yaml rename to drivers/hal/nationstech/drivers/n32g45x/flash/weave.yaml index 72c72611733a5a4aa76b4fdef48ae842087f2785..7912c209f51b95324783ded1ee7b081e7acc66ad 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/sensor/beken_sensor/weave.yaml +++ b/drivers/hal/nationstech/drivers/n32g45x/flash/weave.yaml @@ -1,22 +1,15 @@ # 组名 -group_name: beken_sensor +group_name: hal/drivers # 依赖宏控 depend_macro: - - BUILD_LIB + - MANUFACTOR_NATIONSTECH # 编译连接信息 build_option: cpppath: - - . - libs: - - sensor - libpath: - - . - libname: - - libsensor.a - - + - . ? {is_define("BSP_USING_ONCHIP_FLASH")} + # 源码 source_file: - - sensor.c + - drv_flash.c ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32g45x/n32_it.c b/drivers/hal/nationstech/drivers/n32g45x/n32_it.c new file mode 100644 index 0000000000000000000000000000000000000000..25e7b16e49a9e347ba0d0d4a18893bc2827b36c6 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/n32_it.c @@ -0,0 +1,73 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file n32_it.c + * + * @brief This file provides systick time init/IRQ functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include "os_clock.h" +#include "os_stddef.h" +#include "oneos_config.h" + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.irq" +#include + +#include "n32_it.h" +#include "drv_gpio.h" +#include "drv_usart.h" + +void NMI_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + while (1); +} + +void MemManage_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Memory Manage exception occurs */ + while (1); +} + +void BusFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Bus Fault exception occurs */ + while (1); +} + +void UsageFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Usage Fault exception occurs */ + while (1); +} diff --git a/drivers/hal/nationstech/drivers/n32g45x/n32_it.h b/drivers/hal/nationstech/drivers/n32g45x/n32_it.h new file mode 100644 index 0000000000000000000000000000000000000000..ee875664d40ff94b5c3aa75b5b93df07cfcb8413 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/n32_it.h @@ -0,0 +1,48 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file apm32_it.h + * + * @brief This file provides systick IRQ declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __N32_IT__ +#define __N32_IT__ + +#include + +#ifdef SERIES_N32G4XX +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef NVIC_PriorityGroup_4 +#define NVIC_PriorityGroup NVIC_PriorityGroup_4 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/n32g45x/weave.yaml b/drivers/hal/nationstech/drivers/n32g45x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..19eea7b2a52bc4e4c871a657f999670e40438b4a --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32g45x/weave.yaml @@ -0,0 +1,24 @@ +# 组名 +group_name: hal/drivers + +# 依赖宏控 +depend_macro: + - SERIES_N32G45X + +# 编译连接信息 +build_option: + cpppath: + - . + +# 源码 +source_file: + - drv_common.c + - n32_it.c + - drv_gpio.c ? {is_define("BSP_USING_GPIO")} + - drv_usart.c ? {is_define("BSP_USING_USART")} + - drv_adc.c ? {is_define("BSP_USING_ADC")} + - drv_spi.c ? {is_define("BSP_USING_SPI")} + +# 子目录 +add_subdirectory: + - flash ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_common.c b/drivers/hal/nationstech/drivers/n32l40x/drv_common.c new file mode 100644 index 0000000000000000000000000000000000000000..8d65a7862551a8e98d00401c48e3a71372d3da21 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_common.c @@ -0,0 +1,190 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.c + * + * @brief This file provides systick time init/IRQ and board init functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "n32_it.h" +#include "board.h" +#include "drv_gpio.h" + +#ifdef OS_USING_DMA +#include +#endif + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#include + +static volatile os_bool_t hardware_init_done = OS_FALSE; + +void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +void os_tick_handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + +void SysTick_Handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +static void cortexm_systick_kernel_tick_init(void) +{ + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; + + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +#endif + +#if defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) +void SysTick_Handler(void) +{ + if (hardware_init_done) + { + cortexm_systick_clockevent_isr(); + } + else + { + os_tick_handler(); + } +} +#endif + +void hardware_init(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); // 不能是NVIC_PriorityGroup_0, 否则SVC指令会产生硬件错误(Group0所有位为响应优先级,没有抢占) + + + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL = 0; + NVIC_SetPriority(SysTick_IRQn, 0xFF); + NVIC_EnableIRQ(SysTick_IRQn); + + SysTick->LOAD = 10000; /* set reload register */ + SysTick->VAL = 0UL; /* Load the systick Counter Value */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk;; + + +} + +void os_hw_cpu_reset(void) +{ + NVIC_SystemReset(); +} + +/** + *********************************************************************************************************************** + * @brief This function will initial STM32 board. + * + * @param[in] none + * + * @return none + *********************************************************************************************************************** + */ +static os_err_t os_hw_board_init(void) +{ + hardware_init(); + os_irq_enable(); + HAL_SuspendTick(); + +#ifdef HAL_SDRAM_MODULE_ENABLED + SDRAM_Init(); +#endif + + /* Heap initialization */ +#if defined(OS_USING_DEFAULT_HEAP) + if ((os_size_t)HEAP_END > (os_size_t)HEAP_BEGIN) + { + os_default_heap_init(); + os_default_heap_add((void *)HEAP_BEGIN, (os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN, OS_MEM_ALG_DEFAULT); + } +#endif + +#ifdef OS_USING_DMA_RAM + os_dma_mem_init(); +#endif + + return OS_SUCCESS; +} +OS_INIT_CALL(os_hw_board_init, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_MIDDLE); + +void cortexm_systick_init(void) +{ +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + cortexm_systick_kernel_tick_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKSOURCE) + cortexm_systick_clocksource_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) + cortexm_systick_clockevent_init(); +#endif +} + +static os_err_t board_post_init(void) +{ +#ifdef OS_USING_PIN + os_hw_pin_init(); +#endif + +#if defined(OS_USING_DWT_FOR_CLOCKSOURCE) && defined(DWT) + cortexm_dwt_init(); +#endif + + // calc_mult_shift(&mult_systick2msec, &shift_systick2msec, OS_TICK_PER_SECOND, 1000, 1); + + cortexm_systick_init(); + + hardware_init_done = OS_TRUE; + + return OS_SUCCESS; +} + +OS_INIT_CALL(board_post_init, OS_INIT_LEVEL_POST_KERNEL, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_common.h b/drivers/hal/nationstech/drivers/n32l40x/drv_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f76a5a8303b90836164853d86569e0cb9ae26ec0 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_common.h @@ -0,0 +1,54 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.h + * + * @brief This file provides declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_conf.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_conf.h" +#endif + +#ifdef SERIES_N32L43X +#include "n32l43x_conf.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.c b/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..a6a6f62a0bbb575848bb3604f96a52c3f4164254 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.c @@ -0,0 +1,429 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.c + * + * @brief This file implements gpio driver for apm32. + * + * @revision + * Date Author Notes + * 2022-01-17 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.gpio" +#include + +#include "drv_gpio.h" + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#define N32_PORT(pin) ((pin) >> 4) +#define N32_PIN(pin) ((pin) & 0x0F) + +struct n32_pin_irq +{ + uint16_t pinbit; + IRQn_Type irqno; +}; + +struct n32_gpio +{ + GPIO_Module *base; + uint32_t rcc; +}; + +static const struct n32_gpio n32_gpio_table[] = +{ +#ifdef GPIOA + {GPIOA, RCC_APB2_PERIPH_GPIOA}, +#ifdef GPIOB + {GPIOB, RCC_APB2_PERIPH_GPIOB}, +#ifdef GPIOC + {GPIOC, RCC_APB2_PERIPH_GPIOC}, +#ifdef GPIOD + {GPIOD, RCC_APB2_PERIPH_GPIOD}, +#ifdef GPIOE + {GPIOE, RCC_APB2_PERIPH_GPIOE}, +#ifdef GPIOF + {GPIOF, RCC_APB2_PERIPH_GPIOF}, +#ifdef GPIOG + {GPIOG, RCC_APB2_PERIPH_GPIOG}, +#endif /* GPIOG */ +#endif /* GPIOF */ +#endif /* GPIOE */ +#endif /* GPIOD */ +#endif /* GPIOC */ +#endif /* GPIOB */ +#endif /* GPIOA */ +}; + +static const struct n32_pin_irq n32_pin_irq[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +}; + +static struct os_pin_irq_hdr n32_pin_irq_hdr_tab[] = { + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, +}; + +static void n32_pin_write(os_device_t *dev, os_base_t pin, os_base_t value) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + if (value) + { // set + gpio->base->PBSC = (1<base->PBC = (1<base->PID & mask) == mask; +} + +static void n32_pin_mode(os_device_t *dev, os_base_t pin, os_base_t mode) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + GPIO_InitType init; + init.Pin = (1<rcc, ENABLE); + GPIO_InitPeripheral(gpio->base, &init); +} + +static os_err_t n32_pin_attach_irq(struct os_device *device, int32_t pin, uint32_t mode, void (*hdr)(void *args), void *args) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == pin + && n32_pin_irq_hdr_tab[Pin].hdr == hdr + && n32_pin_irq_hdr_tab[Pin].mode == mode + && n32_pin_irq_hdr_tab[Pin].args == args) + { + os_irq_unlock(level); + return OS_SUCCESS; + } + + if (n32_pin_irq_hdr_tab[Pin].pin != -1) + { + os_irq_unlock(level); + return OS_BUSY; + } + + n32_pin_irq_hdr_tab[Pin].pin = pin; + n32_pin_irq_hdr_tab[Pin].hdr = hdr; + n32_pin_irq_hdr_tab[Pin].mode = mode; + n32_pin_irq_hdr_tab[Pin].args = args; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_detach_irq(struct os_device *device, int32_t pin) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_INVAL; + } + + n32_pin_irq_hdr_tab[Pin].pin = -1; + n32_pin_irq_hdr_tab[Pin].hdr = OS_NULL; + n32_pin_irq_hdr_tab[Pin].mode = 0; + n32_pin_irq_hdr_tab[Pin].args = OS_NULL; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint32_t enabled) +{ + os_base_t level; + const struct n32_pin_irq *irqmap; + + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + if (enabled == PIN_IRQ_ENABLE) + { + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_ENOSYS; + } + + irqmap = &n32_pin_irq[Pin]; + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + + switch (n32_pin_irq_hdr_tab[Pin].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + case PIN_IRQ_MODE_LOW_LEVEL: + default: + os_irq_unlock(level); + return OS_INVAL; + } + + GPIO_ConfigEXTILine(GPIOA_PORT_SOURCE + Port, GPIO_PIN_SOURCE0 + Pin); + + EXTI_InitPeripheral(&EXTI_InitStructure); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + os_irq_unlock(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + level = os_irq_lock(); + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + + os_irq_unlock(level); + } + else + { + return OS_ENOSYS; + } + + return OS_SUCCESS; +} + +const static struct os_pin_ops n32_pin_ops = { + .pin_mode = n32_pin_mode, + .pin_write = n32_pin_write, + .pin_read = n32_pin_read, + .pin_attach_irq = n32_pin_attach_irq, + .pin_detach_irq = n32_pin_detach_irq, + .pin_irq_enable = n32_pin_irq_enable, +}; + +int os_hw_pin_init(void) +{ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); + + return os_device_pin_register(0, &n32_pin_ops, OS_NULL); +} + +static void n32_pin_irq_hdr(int irqno) +{ + if (n32_pin_irq_hdr_tab[irqno].hdr) + { + n32_pin_irq_hdr_tab[irqno].hdr(n32_pin_irq_hdr_tab[irqno].args); + } +} + + +static void HAL_GPIO_EXTI_IRQHandler(uint16_t EXTI_Line) +{ + if ((EXTI->IMASK & EXTI_Line) + && (EXTI->PEND & EXTI_Line)) + { + EXTI->PEND = EXTI_Line; + + n32_pin_irq_hdr(os_ffs(EXTI_Line) - 1); + } +} + +void EXTI0_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE0); +} + +void EXTI1_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE1); +} + +void EXTI2_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE2); +} + +void EXTI3_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE3); +} + +void EXTI4_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE4); +} + +void EXTI9_5_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE5); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE6); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE7); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE8); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE9); +} + +void EXTI15_10_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE10); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE11); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE12); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE13); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE14); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE15); +} diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.h b/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..bc074d22d8e507f242c8749fcd80dd4a6ec4c33b --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_gpio.h @@ -0,0 +1,31 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.h + * + * @brief This file provides struct/macro declaration and functions declaration for apm32 gpio driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#define GET_PIN(port, pin) (((port) << 4) + ((pin) & 0x0F)) + +int os_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_log.h b/drivers/hal/nationstech/drivers/n32l40x/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..104db27e69dcc4f4dc5f2e764b88a96223cf00c8 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_log.h @@ -0,0 +1,36 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_log.h + * + * @brief This file defines driver log with specific level and tag. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef DRV_EXT_TAG +#define DBG_EXT_TAG "drv" +#else +#define DBG_EXT_TAG DRV_EXT_TAG +#endif /* DRV_EXT_TAG */ + +#ifdef DRV_EXT_LVL +#define DBG_EXT_LVL DRV_EXT_LVL +#else +#define DBG_EXT_LVL DBG_EXT_INFO +#endif /* DRV_EXT_LVL */ + +#include diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_spi.c b/drivers/hal/nationstech/drivers/n32l40x/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9837ee3f98d8ebac912919abd846776880e32e63 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_spi.c @@ -0,0 +1,381 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.spi" + +#include "drv_spi.h" + +#define SPI_USING_RX_DMA_FLAG (1 << 0) +#define SPI_USING_TX_DMA_FLAG (1 << 1) + +struct n32_spi_bus +{ + struct os_spi_bus spi_bus; + + SPI_Module *hspi; + const struct n32_spi_info *info; + + struct os_spi_configuration *cfg; + + uint8_t spi_dma_flag; + + os_list_node_t list; +}; + +static os_list_node_t n32_spi_list = OS_LIST_INIT(n32_spi_list); + +static os_err_t n32_spi_init(struct n32_spi_bus *spi_bus, struct os_spi_configuration *cfg) +{ + OS_ASSERT(spi_drv != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + GPIO_InitType ioinit; + GPIO_InitStruct(&ioinit); + + ioinit.Pin = spi_bus->info->sck_pin; + ioinit.GPIO_Speed = GPIO_Speed_50MHz; + ioinit.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(spi_bus->info->sck_port, &ioinit); + + ioinit.Pin = spi_bus->info->mosi_pin; + GPIO_InitPeripheral(spi_bus->info->mosi_port, &ioinit); + + ioinit.Pin = spi_bus->info->miso_pin; + ioinit.GPIO_Mode = GPIO_Mode_IPD; + GPIO_InitPeripheral(spi_bus->info->miso_port, &ioinit); + + + switch(spi_bus->info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(spi_bus->info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(spi_bus->info->rcc, ENABLE); + break; + default: + OS_ASSERT(false); + break; + } + + SPI_InitType init; + SPI_InitStruct(&init); + init.NSS = SPI_NSS_SOFT; + + SPI_Module *hspi = spi_bus->hspi; + + if (cfg->mode & OS_SPI_SLAVE) + { + init.SpiMode = SPI_MODE_SLAVE; + } + else + { + init.SpiMode = SPI_MODE_MASTER; + } + + if (cfg->mode & OS_SPI_3WIRE) + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + else + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + + if (cfg->data_width == 8) + { + init.DataLen = SPI_DATA_SIZE_8BITS; + } + else if (cfg->data_width == 16) + { + init.DataLen = SPI_DATA_SIZE_16BITS; + } + else + { + return OS_EIO; + } + + if (cfg->mode & OS_SPI_CPHA) + { + init.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + } + else + { + init.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + } + + if (cfg->mode & OS_SPI_CPOL) + { + init.CLKPOL = SPI_CLKPOL_HIGH; + } + else + { + init.CLKPOL = SPI_CLKPOL_LOW; + } + + if (cfg->mode & OS_SPI_MSB) + { + init.FirstBit = SPI_FB_MSB; + } + else + { + init.FirstBit = SPI_FB_LSB; + } + + // HCLK:100MHz, APB2 CLK: 50MHz 100MHz / 2 + init.BaudRatePres = SPI_BR_PRESCALER_32;//cfg->max_hz; + + SPI_Init(hspi, &init); + + SPI_Enable(hspi, ENABLE); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", spi_bus->spi_bus.parent.name); + return OS_SUCCESS; +} + +static os_err_t spi_configure(struct os_spi_device *device, struct os_spi_configuration *configuration) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(configuration != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + spi_bus->cfg = configuration; + + return n32_spi_init(spi_bus, configuration); +} + +/* clang-format off */ +static uint32_t spixfer(struct os_spi_device *device, struct os_spi_message *message) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(device->bus != OS_NULL); + OS_ASSERT(message != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + SPI_Module *hspi = spi_bus->hspi; + + if (message->cs_take + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_LOW); + } + + SPI_I2S_ReceiveData(hspi); + + // LOG_D(DBG_TAG, "%s transfer prepare and start", spi_drv->config->bus_name); + // LOG_D(DBG_TAG, + // "%s sendbuf: %X, recvbuf: %X, length: %d", + // spi_drv->config->bus_name, + // (uint32_t)message->send_buf, + // (uint32_t)message->recv_buf, + // message->length); + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + //ret = SPI_TransmitReceive_DMA SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else if (message->send_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + //ret = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + } + } + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + } + } + else if (message->recv_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + //ret = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else + { // 错误 message->send_buf、message->recv_buf 都是NULL + return 0; + } + + if (message->cs_release + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_HIGH); + } + + return message->length; +} +/* clang-format on */ + +static const struct os_spi_ops n32_spi_bus_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; + +static int n32_spi_bus_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + os_err_t result = 0; + os_base_t level; + + struct n32_spi_bus *spi_bus = os_calloc(1, sizeof(struct n32_spi_bus)); + + OS_ASSERT(nt_spi); + + spi_bus->info = dev->info; + + spi_bus->hspi = spi_bus->info->hspi; + + level = os_irq_lock(); + os_list_add_tail(&n32_spi_list, &spi_bus->list); + os_irq_unlock(level); + + result = os_spi_bus_register(&spi_bus->spi_bus, dev->name, &n32_spi_bus_ops); + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s bus init done\r\n", dev->name); + + return result; +} + +OS_DRIVER_INFO n32_spi_driver = { + .name = "SPI_Module", + .probe = n32_spi_bus_probe, +}; + +OS_DRIVER_DEFINE(n32_spi_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_spi.h b/drivers/hal/nationstech/drivers/n32l40x/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..8f52de3fd80ba7bc2a991dfdaf3a578e7d2395b1 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_spi.h @@ -0,0 +1,61 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +#include "n32g45x.h" + +struct n32_spi_info +{ + SPI_Module *hspi; + int rcc_type; + int rcc; + IRQn_Type irq; + + struct + { + DMA_ChannelType *channel; + int rcc; + IRQn_Type irq; + }dma_rx, dma_tx; + + GPIO_Module *nss_port; + int nss_pin; + int nss_rcc; + + GPIO_Module *sck_port; + int sck_pin; + int sck_rcc; + + GPIO_Module *miso_port; + int miso_pin; + int miso_rcc; + + GPIO_Module *mosi_port; + int mosi_pin; + int mosi_rcc; +}; + +#endif /* __DRV_SPI_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_usart.c b/drivers/hal/nationstech/drivers/n32l40x/drv_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..42847fefa74692753f2eb827b673be9c59d41505 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_usart.c @@ -0,0 +1,640 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.usart" +#include + +#include "drv_usart.h" + +typedef struct n32_usart +{ + struct os_serial_device serial; + + struct n32_usart_info *info; + + soft_dma_t sdma; + uint32_t sdma_hard_size; + + DMA_InitType DMA_InitStructure; + + uint8_t *rx_buff; + uint32_t rx_index; + uint32_t rx_size; + + const uint8_t *tx_buff; + uint32_t tx_count; + uint32_t tx_size; + + os_list_node_t list; +} n32_usart_t; + +static os_list_node_t n32_usart_list = OS_LIST_INIT(n32_usart_list); + +static const struct n32_usart_info *console_uart = OS_NULL; + +static void n32_usart_interrupt_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + OS_ASSERT(uart->rx_buff != OS_NULL); + OS_ASSERT(uart->rx_index < uart->rx_size); + + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + + uart->rx_buff[uart->rx_index++] = USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + if (uart->rx_index > 0) + { + soft_dma_timeout_irq(&uart->sdma); + } + } + + if (uart->rx_index == (uart->rx_size / 2)) + { + soft_dma_half_irq(&uart->sdma); + } + + if (uart->rx_index == uart->rx_size) + { + uart->rx_index = 0; + soft_dma_full_irq(&uart->sdma); + } +} + + +static void n32_usart_dma_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + soft_dma_timeout_irq(&uart->sdma); + } +} + +static void n32_usart_irq_callback(n32_usart_t *uart) +{ + /* rx */ + if (uart->info->dma_channel == OS_NULL) + { + n32_usart_interrupt_rx(uart); + } + else + { + n32_usart_dma_rx(uart); + } + + /* tx */ + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXDE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXDE); + + if (uart->tx_size > 0) + { + if (uart->tx_count == 0) + { + if (uart->info->send_start_hook) + { + uart->info->send_start_hook(); + } + } + + if (uart->tx_count < uart->tx_size) + USART_SendData(uart->info->huart, uart->tx_buff[uart->tx_count++]); + + if (uart->tx_count >= uart->tx_size) + { + uart->tx_size = 0; + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + os_hw_serial_isr_txdone((struct os_serial_device *)uart); + + USART_ConfigInt(uart->info->huart, USART_INT_TXC, ENABLE); + } + } + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXC) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXC); + USART_ConfigInt(uart->info->huart, USART_INT_TXC, DISABLE); + + if (uart->info->send_end_hook) + { + uart->info->send_end_hook(); + } + } +} + +static void usart_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + n32_usart_irq_callback(uart); + return; + } + } +} + +static void usart_dma_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + soft_dma_half_irq(&uart->sdma); + return; + } + } +} + +void USART1_IRQHandler(void) +{ +#ifdef USART1 + usart_irqhandler(USART1); +#endif +} + +void USART2_IRQHandler(void) +{ +#ifdef USART2 + usart_irqhandler(USART2); +#endif +} + +void USART3_IRQHandler(void) +{ +#ifdef USART3 + usart_irqhandler(USART3); +#endif +} + +void DMA_Channel5_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX5, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC5, DMA); + +#ifdef USART1 + usart_dma_irqhandler(USART1); +#endif +} + +void DMA_Channel6_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX6, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC6, DMA); + +#ifdef USART2 + usart_dma_irqhandler(USART2); +#endif +} + +void DMA_Channel3_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX3, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC3, DMA); + +#ifdef USART3 + usart_dma_irqhandler(USART3); +#endif +} + +/* interrupt rx mode */ +static uint32_t n32_sdma_int_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->rx_index; +} + +static os_err_t n32_sdma_int_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->rx_buff = buff; + uart->rx_index = 0; + uart->rx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_int_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + + return n32_sdma_int_get_index(dma); +} + +/* dma rx mode */ +static uint32_t n32_sdma_dma_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->sdma_hard_size - DMA_GetCurrDataCounter(uart->info->dma_channel); +} + +static os_err_t n32_sdma_dma_init(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + RCC_EnableAHBPeriphClk(uart->info->dma_rcc, ENABLE); + + uart->DMA_InitStructure.PeriphAddr = (uint32_t)&uart->info->huart->DAT; + uart->DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; + uart->DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE; + uart->DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + uart->DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + uart->DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Byte; + uart->DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR; + uart->DMA_InitStructure.Priority = DMA_PRIORITY_HIGH; + uart->DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE; + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + return OS_SUCCESS; +} + +static os_err_t n32_sdma_dma_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->sdma_hard_size = size; + + uart->DMA_InitStructure.MemAddr = (uint32_t)buff; + uart->DMA_InitStructure.BufSize = size; + + DMA_Init(uart->info->dma_channel, &uart->DMA_InitStructure); + DMA_EnableChannel(uart->info->dma_channel, ENABLE); + USART_EnableDMA(uart->info->huart, USART_DMAREQ_RX, ENABLE); + + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + DMA_ConfigInt(uart->info->dma_channel, DMA_INT_TXC | DMA_INT_HTX, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_dma_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + DMA_EnableChannel(uart->info->dma_channel, DISABLE); + + return n32_sdma_dma_get_index(dma); +} + +/* sdma callback */ +static void n32_usart_sdma_callback(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + os_hw_serial_isr_rxdone((struct os_serial_device *)uart); +} + +static void n32_usart_sdma_init(struct n32_usart *uart, dma_ring_t *ring) +{ + soft_dma_t *dma = &uart->sdma; + + soft_dma_stop(dma); + + memset(&dma->hard_info, 0, sizeof(dma->hard_info)); + + dma->hard_info.mode = HARD_DMA_MODE_CIRCULAR; + dma->hard_info.max_size = 64 * 1024; + dma->hard_info.flag = HARD_DMA_FLAG_HALF_IRQ | HARD_DMA_FLAG_FULL_IRQ | HARD_DMA_FLAG_TIMEOUT_IRQ; + dma->hard_info.data_timeout = uart_calc_byte_timeout_us(uart->serial.config.baud_rate); + + if (uart->info->dma_channel == OS_NULL) + { + dma->ops.get_index = n32_sdma_int_get_index; + dma->ops.dma_init = OS_NULL; + dma->ops.dma_start = n32_sdma_int_start; + dma->ops.dma_stop = n32_sdma_int_stop; + } + else + { + dma->ops.get_index = n32_sdma_dma_get_index; + dma->ops.dma_init = n32_sdma_dma_init; + dma->ops.dma_start = n32_sdma_dma_start; + dma->ops.dma_stop = n32_sdma_dma_stop; + } + + dma->cbs.dma_half_callback = n32_usart_sdma_callback; + dma->cbs.dma_full_callback = n32_usart_sdma_callback; + dma->cbs.dma_timeout_callback = n32_usart_sdma_callback; + + soft_dma_init(dma); + soft_dma_start(dma, ring); + soft_dma_irq_enable(&uart->sdma, OS_TRUE); +} + +static int __n32_usart_init(const struct n32_usart_info *uart_info, struct serial_configure *cfg) +{ + GPIO_InitType GPIO_InitStructure; + USART_InitType USART_InitStructure; + uint32_t data_bits; + + RCC_EnableAPB2PeriphClk(uart_info->tx_rcc, ENABLE); + RCC_EnableAPB2PeriphClk(uart_info->rx_rcc, ENABLE); + + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStructure.Pin = uart_info->tx_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(uart_info->tx_port, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = uart_info->rx_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input; + GPIO_InitPeripheral(uart_info->rx_port, &GPIO_InitStructure); + + USART_InitStructure.BaudRate = cfg->baud_rate; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.StopBits = USART_STPB_1; + break; + case STOP_BITS_2: + USART_InitStructure.StopBits = USART_STPB_2; + break; + default: + return OS_INVAL; + } + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.Parity = USART_PE_NO; + data_bits = cfg->data_bits; + break; + case PARITY_ODD: + USART_InitStructure.Parity = USART_PE_ODD; + data_bits = cfg->data_bits + 1; + break; + case PARITY_EVEN: + USART_InitStructure.Parity = USART_PE_EVEN; + data_bits = cfg->data_bits + 1; + break; + default: + return OS_INVAL; + } + + switch (data_bits) + { + case DATA_BITS_8: + USART_InitStructure.WordLength = USART_WL_8B; + break; + case DATA_BITS_9: + USART_InitStructure.WordLength = USART_WL_9B; + break; + default: + return OS_INVAL; + } + + switch(uart_info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(uart_info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(uart_info->rcc, ENABLE); + break; + } + + USART_DeInit(uart_info->huart); + USART_Init(uart_info->huart, &USART_InitStructure); + USART_ConfigInt(uart_info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart_info->huart, USART_INT_RXDNE, DISABLE); + USART_Enable(uart_info->huart, ENABLE); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_init(struct os_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + __n32_usart_init(uart->info, cfg); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + n32_usart_sdma_init(uart, &serial->rx_fifo->ring); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_deinit(struct os_serial_device *serial) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + /* rx */ + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + + if (uart->info->dma_channel != OS_NULL) + { + soft_dma_stop(&uart->sdma); + DMA_DeInit(uart->info->dma_channel); + } + + /* tx */ + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + + uart->tx_buff = OS_NULL; + uart->tx_count = 0; + uart->tx_size = 0; + + return 0; +} + +static int n32_uart_start_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + uart->tx_buff = buff; + uart->tx_count = 0; + uart->tx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, ENABLE); + + return size; +} + +/* clang-format off */ +static int n32_usart_poll_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + int i; + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + for (i = 0; i < size; i++) + { + while (USART_GetFlagStatus(uart->info->huart, USART_FLAG_TXC) == RESET); + USART_SendData(uart->info->huart, buff[i]); + } + + return size; +} +/* clang-format on */ + +static const struct os_uart_ops n32_usart_ops = { + .init = n32_usart_init, + .deinit = n32_usart_deinit, + + .start_send = n32_uart_start_send, + .poll_send = n32_usart_poll_send, +}; + +static int n32_usart_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + os_err_t result = 0; + os_base_t level; + + struct n32_usart *uart = os_calloc(1, sizeof(struct n32_usart)); + + OS_ASSERT(uart); + + uart->info = (void*)dev->info; + + struct os_serial_device *serial = &uart->serial; + + serial->ops = &n32_usart_ops; + serial->config = config; + + level = os_irq_lock(); + os_list_add_tail(&n32_usart_list, &uart->list); + os_irq_unlock(level); + + result = os_hw_serial_register(serial, dev->name, NULL); + + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", dev->name); + + return result; +} + +/* clang-format off */ +void __os_hw_console_output(char *str) +{ + int i; + + if (console_uart == OS_NULL) + return; + + for (i = 0; i < strlen(str); i++) + { + while (USART_GetFlagStatus(console_uart->huart, USART_FLAG_TXC) == RESET); + USART_SendData(console_uart->huart, str[i]); + } +} +/* clang-format on */ + +OS_DRIVER_INFO n32_usart_driver = { + .name = "USART_Module", + .probe = n32_usart_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); + +static int n32_usart_early_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + if (strcmp(dev->name, OS_CONSOLE_DEVICE_NAME)) + return OS_SUCCESS; + + console_uart = (const struct n32_usart_info *)dev->info; + + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + __n32_usart_init(console_uart, &config); + + return OS_SUCCESS; +} + +OS_DRIVER_INFO n32_usart_early_driver = { + .name = "USART_Module", + .probe = n32_usart_early_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_early_driver, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l40x/drv_usart.h b/drivers/hal/nationstech/drivers/n32l40x/drv_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..49bd3889401fcf624adba0ee4ec3850bf44d7a9d --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/drv_usart.h @@ -0,0 +1,64 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +struct n32_usart_info +{ + USART_Module *huart; + int rcc_type; + int rcc; + IRQn_Type irq; + + DMA_ChannelType *dma_channel; + int dma_rcc; + IRQn_Type dma_irq; + + GPIO_Module *tx_port; + int tx_pin; + int tx_rcc; + + GPIO_Module *rx_port; + int rx_pin; + int rx_rcc; + + void (*init_hook)(); + void (*send_start_hook)(void); + void (*send_end_hook)(void); +}; + +#endif /* __DRV_USART_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.c b/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..69dcee0c93f300428df2a970782fac835dc4b0ed --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.c @@ -0,0 +1,167 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash_common.c + * + * @brief This file provides flash read/write/erase functions for N32. + * + * @revision + * Date Author Notes + * 2022-01-11 OneOS Team First Version + *********************************************************************************************************************** + */ +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.flash" +#include + +#include "drv_flash.h" + +#define N32_FLASH_BLOCK_SIZE (2 * 1024) +#define N32_FLASH_PAGE_SIZE (2 * 1024) + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size) +{ + size_t i; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(uint8_t *)addr; + } + + return size; +} + +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size) +{ + size_t i, j; + os_err_t result = 0; + uint32_t write_data = 0, temp_data = 0; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: write outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + if (addr % 4 != 0) + { + LOG_E(DRV_EXT_TAG, "write addr must be 4-byte alignment"); + return OS_INVAL; + } + + FLASH_Unlock(); + + if (size < 1) + { + return OS_INVAL; + } + + for (i = 0; i < size;) + { + if ((size - i) < 4) + { + for (j = 0; (size - i) > 0; i++, j++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + else + { + for (j = 0; j < 4; j++, i++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + + /* write data */ + if (FLASH_ProgramWord(addr, write_data) == FLASH_COMPL) + { + /* Check the written value */ + if (*(uint32_t *)addr != write_data) + { + LOG_E(DRV_EXT_TAG, "ERROR: write data != read data"); + result = OS_FAILURE; + goto __exit; + } + } + else + { + result = OS_FAILURE; + goto __exit; + } + + temp_data = 0; + write_data = 0; + + addr += 4; + } + +__exit: + FLASH_Lock(); + if (result != 0) + { + return result; + } + + return size; +} + +int n32_flash_erase(uint32_t addr, size_t size) +{ + os_err_t result = OS_SUCCESS; + + const uint32_t page_addr_mask = ~(N32_FLASH_PAGE_SIZE - 1); + uint32_t end_addr = addr + size; + + if (end_addr > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: erase outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + FLASH_Unlock(); + + for (uint32_t page = addr & page_addr_mask; page < end_addr; page+=N32_FLASH_PAGE_SIZE) + { + if (FLASH_EraseOnePage(page) != FLASH_COMPL) + { + result = OS_FAILURE; + goto __exit; + } + } + +__exit: + FLASH_Lock(); + + if (result != OS_SUCCESS) + { + return result; + } + + LOG_D(DRV_EXT_TAG, "erase done: addr (0x%p), size %d", (void *)addr, size); + return size; +} + +#include "fal_drv_flash.c" diff --git a/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.h b/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..858a52838ca87e753923bdb557496e316c234563 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/flash/drv_flash.h @@ -0,0 +1,42 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash.h + * + * @brief This file provides declaration for flash functions. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_FLASH_H__ +#define __DRV_FLASH_H__ + +#include "drv_cfg.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size); +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size); +int n32_flash_erase(uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l40x/flash/fal_drv_flash.c b/drivers/hal/nationstech/drivers/n32l40x/flash/fal_drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..b6c7a5d011d2555faa4ece5637183d2f097ffa40 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/flash/fal_drv_flash.c @@ -0,0 +1,73 @@ +#include "string.h" +#include +#include +#include "dlog.h" + +#include "drv_flash.h" + +#if defined(OS_USING_FAL) +#include "fal.h" +#include "ports/flash_info.c" +#endif + +static int n32_fal_flash_read(fal_flash_t *flash, uint32_t page_addr, uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_read(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_write(fal_flash_t *flash, uint32_t page_addr, const uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_write(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_erase(fal_flash_t *flash, uint32_t page_addr, uint32_t page_nr) +{ + int count = n32_flash_erase(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_flash_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + fal_flash_t *fal_flash = os_calloc(1, sizeof(fal_flash_t)); + + if (fal_flash == OS_NULL) + { + os_kprintf("fal flash mem leak %s.\r\n", dev->name); + return -1; + } + + struct onchip_flash_info *flash_info = (struct onchip_flash_info *)dev->info; + + memcpy(fal_flash->name, dev->name, min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))); + + fal_flash->name[min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))] = 0; + + fal_flash->capacity = flash_info->capacity; + fal_flash->block_size = flash_info->block_size; + fal_flash->page_size = flash_info->page_size; + + fal_flash->ops.read_page = n32_fal_flash_read; + fal_flash->ops.write_page = n32_fal_flash_write; + fal_flash->ops.erase_block = n32_fal_flash_erase; + + fal_flash->priv = flash_info; + + return fal_flash_register(fal_flash); +} + +OS_DRIVER_INFO n32_flash_driver = { + .name = "N32L40X_Onchip_Flash", + .probe = n32_flash_probe, +}; + +OS_DRIVER_DEFINE(n32_flash_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); diff --git a/drivers/hal/beken/beken72XX_HAL/func/vad/weave.yaml b/drivers/hal/nationstech/drivers/n32l40x/flash/weave.yaml similarity index 32% rename from drivers/hal/beken/beken72XX_HAL/func/vad/weave.yaml rename to drivers/hal/nationstech/drivers/n32l40x/flash/weave.yaml index e44d8433428b8270877fda8a4b84dcf2c36dba8d..7912c209f51b95324783ded1ee7b081e7acc66ad 100644 --- a/drivers/hal/beken/beken72XX_HAL/func/vad/weave.yaml +++ b/drivers/hal/nationstech/drivers/n32l40x/flash/weave.yaml @@ -1,18 +1,15 @@ # 组名 -group_name: beken_vad_lib +group_name: hal/drivers # 依赖宏控 depend_macro: - - SOC_FAMILY_BK72XX + - MANUFACTOR_NATIONSTECH # 编译连接信息 build_option: cpppath: - - . - libs: - - vad - libpath: - - . -# 子目录 -add_subdirectory: - - beken_vad \ No newline at end of file + - . ? {is_define("BSP_USING_ONCHIP_FLASH")} + +# 源码 +source_file: + - drv_flash.c ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32l40x/n32_it.c b/drivers/hal/nationstech/drivers/n32l40x/n32_it.c new file mode 100644 index 0000000000000000000000000000000000000000..25e7b16e49a9e347ba0d0d4a18893bc2827b36c6 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/n32_it.c @@ -0,0 +1,73 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file n32_it.c + * + * @brief This file provides systick time init/IRQ functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include "os_clock.h" +#include "os_stddef.h" +#include "oneos_config.h" + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.irq" +#include + +#include "n32_it.h" +#include "drv_gpio.h" +#include "drv_usart.h" + +void NMI_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + while (1); +} + +void MemManage_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Memory Manage exception occurs */ + while (1); +} + +void BusFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Bus Fault exception occurs */ + while (1); +} + +void UsageFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Usage Fault exception occurs */ + while (1); +} diff --git a/drivers/hal/nationstech/drivers/n32l40x/n32_it.h b/drivers/hal/nationstech/drivers/n32l40x/n32_it.h new file mode 100644 index 0000000000000000000000000000000000000000..ee875664d40ff94b5c3aa75b5b93df07cfcb8413 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/n32_it.h @@ -0,0 +1,48 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file apm32_it.h + * + * @brief This file provides systick IRQ declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __N32_IT__ +#define __N32_IT__ + +#include + +#ifdef SERIES_N32G4XX +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef NVIC_PriorityGroup_4 +#define NVIC_PriorityGroup NVIC_PriorityGroup_4 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/n32l40x/weave.yaml b/drivers/hal/nationstech/drivers/n32l40x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6c2c01cdf97d59523ef263ba915614802fd4c95b --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l40x/weave.yaml @@ -0,0 +1,24 @@ +# 组名 +group_name: hal/drivers + +# 依赖宏控 +depend_macro: + - SERIES_N32L40X + +# 编译连接信息 +build_option: + cpppath: + - . + +# 源码 +source_file: + - drv_common.c + - n32_it.c + - drv_gpio.c ? {is_define("BSP_USING_GPIO")} + - drv_usart.c ? {is_define("BSP_USING_USART")} + - drv_adc.c ? {is_define("BSP_USING_ADC")} + - drv_spi.c ? {is_define("BSP_USING_SPI")} + +# 子目录 +add_subdirectory: + - flash ? {is_define("BSP_USING_ONCHIP_FLASH")} \ No newline at end of file diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_common.c b/drivers/hal/nationstech/drivers/n32l43x/drv_common.c new file mode 100644 index 0000000000000000000000000000000000000000..8d65a7862551a8e98d00401c48e3a71372d3da21 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_common.c @@ -0,0 +1,190 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.c + * + * @brief This file provides systick time init/IRQ and board init functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "n32_it.h" +#include "board.h" +#include "drv_gpio.h" + +#ifdef OS_USING_DMA +#include +#endif + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#include + +static volatile os_bool_t hardware_init_done = OS_FALSE; + +void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +void os_tick_handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + +void SysTick_Handler(void) +{ + os_tick_increase(); + +#ifdef OS_USING_CLOCKSOURCE + os_clocksource_update(); +#endif +} + +static void cortexm_systick_kernel_tick_init(void) +{ + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; + + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +#endif + +#if defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) +void SysTick_Handler(void) +{ + if (hardware_init_done) + { + cortexm_systick_clockevent_isr(); + } + else + { + os_tick_handler(); + } +} +#endif + +void hardware_init(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); // 不能是NVIC_PriorityGroup_0, 否则SVC指令会产生硬件错误(Group0所有位为响应优先级,没有抢占) + + + SysTick_Config(SystemCoreClock / OS_TICK_PER_SECOND); + SysTick->CTRL = 0; + NVIC_SetPriority(SysTick_IRQn, 0xFF); + NVIC_EnableIRQ(SysTick_IRQn); + + SysTick->LOAD = 10000; /* set reload register */ + SysTick->VAL = 0UL; /* Load the systick Counter Value */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk;; + + +} + +void os_hw_cpu_reset(void) +{ + NVIC_SystemReset(); +} + +/** + *********************************************************************************************************************** + * @brief This function will initial STM32 board. + * + * @param[in] none + * + * @return none + *********************************************************************************************************************** + */ +static os_err_t os_hw_board_init(void) +{ + hardware_init(); + os_irq_enable(); + HAL_SuspendTick(); + +#ifdef HAL_SDRAM_MODULE_ENABLED + SDRAM_Init(); +#endif + + /* Heap initialization */ +#if defined(OS_USING_DEFAULT_HEAP) + if ((os_size_t)HEAP_END > (os_size_t)HEAP_BEGIN) + { + os_default_heap_init(); + os_default_heap_add((void *)HEAP_BEGIN, (os_size_t)HEAP_END - (os_size_t)HEAP_BEGIN, OS_MEM_ALG_DEFAULT); + } +#endif + +#ifdef OS_USING_DMA_RAM + os_dma_mem_init(); +#endif + + return OS_SUCCESS; +} +OS_INIT_CALL(os_hw_board_init, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_MIDDLE); + +void cortexm_systick_init(void) +{ +#ifdef OS_USING_SYSTICK_FOR_KERNEL_TICK + cortexm_systick_kernel_tick_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKSOURCE) + cortexm_systick_clocksource_init(); +#elif defined(OS_USING_SYSTICK_FOR_CLOCKEVENT) + cortexm_systick_clockevent_init(); +#endif +} + +static os_err_t board_post_init(void) +{ +#ifdef OS_USING_PIN + os_hw_pin_init(); +#endif + +#if defined(OS_USING_DWT_FOR_CLOCKSOURCE) && defined(DWT) + cortexm_dwt_init(); +#endif + + // calc_mult_shift(&mult_systick2msec, &shift_systick2msec, OS_TICK_PER_SECOND, 1000, 1); + + cortexm_systick_init(); + + hardware_init_done = OS_TRUE; + + return OS_SUCCESS; +} + +OS_INIT_CALL(board_post_init, OS_INIT_LEVEL_POST_KERNEL, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_common.h b/drivers/hal/nationstech/drivers/n32l43x/drv_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f76a5a8303b90836164853d86569e0cb9ae26ec0 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_common.h @@ -0,0 +1,54 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_common.h + * + * @brief This file provides declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_conf.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_conf.h" +#endif + +#ifdef SERIES_N32L43X +#include "n32l43x_conf.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.c b/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..a6a6f62a0bbb575848bb3604f96a52c3f4164254 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.c @@ -0,0 +1,429 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.c + * + * @brief This file implements gpio driver for apm32. + * + * @revision + * Date Author Notes + * 2022-01-17 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.gpio" +#include + +#include "drv_gpio.h" + +#ifdef SERIES_N32G43X +#include "n32g43x_conf.h" +#endif + +#ifdef SERIES_N32G45X +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#define N32_PORT(pin) ((pin) >> 4) +#define N32_PIN(pin) ((pin) & 0x0F) + +struct n32_pin_irq +{ + uint16_t pinbit; + IRQn_Type irqno; +}; + +struct n32_gpio +{ + GPIO_Module *base; + uint32_t rcc; +}; + +static const struct n32_gpio n32_gpio_table[] = +{ +#ifdef GPIOA + {GPIOA, RCC_APB2_PERIPH_GPIOA}, +#ifdef GPIOB + {GPIOB, RCC_APB2_PERIPH_GPIOB}, +#ifdef GPIOC + {GPIOC, RCC_APB2_PERIPH_GPIOC}, +#ifdef GPIOD + {GPIOD, RCC_APB2_PERIPH_GPIOD}, +#ifdef GPIOE + {GPIOE, RCC_APB2_PERIPH_GPIOE}, +#ifdef GPIOF + {GPIOF, RCC_APB2_PERIPH_GPIOF}, +#ifdef GPIOG + {GPIOG, RCC_APB2_PERIPH_GPIOG}, +#endif /* GPIOG */ +#endif /* GPIOF */ +#endif /* GPIOE */ +#endif /* GPIOD */ +#endif /* GPIOC */ +#endif /* GPIOB */ +#endif /* GPIOA */ +}; + +static const struct n32_pin_irq n32_pin_irq[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +}; + +static struct os_pin_irq_hdr n32_pin_irq_hdr_tab[] = { + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, + {-1, 0, OS_NULL, OS_NULL}, +}; + +static void n32_pin_write(os_device_t *dev, os_base_t pin, os_base_t value) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + if (value) + { // set + gpio->base->PBSC = (1<base->PBC = (1<base->PID & mask) == mask; +} + +static void n32_pin_mode(os_device_t *dev, os_base_t pin, os_base_t mode) +{ + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + + const struct n32_gpio *gpio = &n32_gpio_table[Port]; + + GPIO_InitType init; + init.Pin = (1<rcc, ENABLE); + GPIO_InitPeripheral(gpio->base, &init); +} + +static os_err_t n32_pin_attach_irq(struct os_device *device, int32_t pin, uint32_t mode, void (*hdr)(void *args), void *args) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == pin + && n32_pin_irq_hdr_tab[Pin].hdr == hdr + && n32_pin_irq_hdr_tab[Pin].mode == mode + && n32_pin_irq_hdr_tab[Pin].args == args) + { + os_irq_unlock(level); + return OS_SUCCESS; + } + + if (n32_pin_irq_hdr_tab[Pin].pin != -1) + { + os_irq_unlock(level); + return OS_BUSY; + } + + n32_pin_irq_hdr_tab[Pin].pin = pin; + n32_pin_irq_hdr_tab[Pin].hdr = hdr; + n32_pin_irq_hdr_tab[Pin].mode = mode; + n32_pin_irq_hdr_tab[Pin].args = args; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_detach_irq(struct os_device *device, int32_t pin) +{ + os_base_t level; + + int Pin = N32_PIN(pin); + + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_INVAL; + } + + n32_pin_irq_hdr_tab[Pin].pin = -1; + n32_pin_irq_hdr_tab[Pin].hdr = OS_NULL; + n32_pin_irq_hdr_tab[Pin].mode = 0; + n32_pin_irq_hdr_tab[Pin].args = OS_NULL; + + os_irq_unlock(level); + + return OS_SUCCESS; +} + +static os_err_t n32_pin_irq_enable(struct os_device *device, os_base_t pin, uint32_t enabled) +{ + os_base_t level; + const struct n32_pin_irq *irqmap; + + int Port = N32_PORT(pin); + int Pin = N32_PIN(pin); + + OS_ASSERT(Port < ARRAY_SIZE(n32_gpio_table)); + OS_ASSERT(Pin < ARRAY_SIZE(n32_pin_irq)); + + if (enabled == PIN_IRQ_ENABLE) + { + level = os_irq_lock(); + + if (n32_pin_irq_hdr_tab[Pin].pin == -1) + { + os_irq_unlock(level); + return OS_ENOSYS; + } + + irqmap = &n32_pin_irq[Pin]; + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + + switch (n32_pin_irq_hdr_tab[Pin].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + case PIN_IRQ_MODE_LOW_LEVEL: + default: + os_irq_unlock(level); + return OS_INVAL; + } + + GPIO_ConfigEXTILine(GPIOA_PORT_SOURCE + Port, GPIO_PIN_SOURCE0 + Pin); + + EXTI_InitPeripheral(&EXTI_InitStructure); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + os_irq_unlock(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + level = os_irq_lock(); + + EXTI_InitType EXTI_InitStructure; + EXTI_InitStructure.EXTI_Line = irqmap->pinbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + + os_irq_unlock(level); + } + else + { + return OS_ENOSYS; + } + + return OS_SUCCESS; +} + +const static struct os_pin_ops n32_pin_ops = { + .pin_mode = n32_pin_mode, + .pin_write = n32_pin_write, + .pin_read = n32_pin_read, + .pin_attach_irq = n32_pin_attach_irq, + .pin_detach_irq = n32_pin_detach_irq, + .pin_irq_enable = n32_pin_irq_enable, +}; + +int os_hw_pin_init(void) +{ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); + + return os_device_pin_register(0, &n32_pin_ops, OS_NULL); +} + +static void n32_pin_irq_hdr(int irqno) +{ + if (n32_pin_irq_hdr_tab[irqno].hdr) + { + n32_pin_irq_hdr_tab[irqno].hdr(n32_pin_irq_hdr_tab[irqno].args); + } +} + + +static void HAL_GPIO_EXTI_IRQHandler(uint16_t EXTI_Line) +{ + if ((EXTI->IMASK & EXTI_Line) + && (EXTI->PEND & EXTI_Line)) + { + EXTI->PEND = EXTI_Line; + + n32_pin_irq_hdr(os_ffs(EXTI_Line) - 1); + } +} + +void EXTI0_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE0); +} + +void EXTI1_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE1); +} + +void EXTI2_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE2); +} + +void EXTI3_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE3); +} + +void EXTI4_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE4); +} + +void EXTI9_5_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE5); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE6); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE7); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE8); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE9); +} + +void EXTI15_10_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE10); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE11); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE12); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE13); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE14); + HAL_GPIO_EXTI_IRQHandler(EXTI_LINE15); +} diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.h b/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..bc074d22d8e507f242c8749fcd80dd4a6ec4c33b --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_gpio.h @@ -0,0 +1,31 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_gpio.h + * + * @brief This file provides struct/macro declaration and functions declaration for apm32 gpio driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#define GET_PIN(port, pin) (((port) << 4) + ((pin) & 0x0F)) + +int os_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_log.h b/drivers/hal/nationstech/drivers/n32l43x/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..104db27e69dcc4f4dc5f2e764b88a96223cf00c8 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_log.h @@ -0,0 +1,36 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_log.h + * + * @brief This file defines driver log with specific level and tag. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef DRV_EXT_TAG +#define DBG_EXT_TAG "drv" +#else +#define DBG_EXT_TAG DRV_EXT_TAG +#endif /* DRV_EXT_TAG */ + +#ifdef DRV_EXT_LVL +#define DBG_EXT_LVL DRV_EXT_LVL +#else +#define DBG_EXT_LVL DBG_EXT_INFO +#endif /* DRV_EXT_LVL */ + +#include diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_spi.c b/drivers/hal/nationstech/drivers/n32l43x/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9837ee3f98d8ebac912919abd846776880e32e63 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_spi.c @@ -0,0 +1,381 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.spi" + +#include "drv_spi.h" + +#define SPI_USING_RX_DMA_FLAG (1 << 0) +#define SPI_USING_TX_DMA_FLAG (1 << 1) + +struct n32_spi_bus +{ + struct os_spi_bus spi_bus; + + SPI_Module *hspi; + const struct n32_spi_info *info; + + struct os_spi_configuration *cfg; + + uint8_t spi_dma_flag; + + os_list_node_t list; +}; + +static os_list_node_t n32_spi_list = OS_LIST_INIT(n32_spi_list); + +static os_err_t n32_spi_init(struct n32_spi_bus *spi_bus, struct os_spi_configuration *cfg) +{ + OS_ASSERT(spi_drv != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + GPIO_InitType ioinit; + GPIO_InitStruct(&ioinit); + + ioinit.Pin = spi_bus->info->sck_pin; + ioinit.GPIO_Speed = GPIO_Speed_50MHz; + ioinit.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(spi_bus->info->sck_port, &ioinit); + + ioinit.Pin = spi_bus->info->mosi_pin; + GPIO_InitPeripheral(spi_bus->info->mosi_port, &ioinit); + + ioinit.Pin = spi_bus->info->miso_pin; + ioinit.GPIO_Mode = GPIO_Mode_IPD; + GPIO_InitPeripheral(spi_bus->info->miso_port, &ioinit); + + + switch(spi_bus->info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(spi_bus->info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(spi_bus->info->rcc, ENABLE); + break; + default: + OS_ASSERT(false); + break; + } + + SPI_InitType init; + SPI_InitStruct(&init); + init.NSS = SPI_NSS_SOFT; + + SPI_Module *hspi = spi_bus->hspi; + + if (cfg->mode & OS_SPI_SLAVE) + { + init.SpiMode = SPI_MODE_SLAVE; + } + else + { + init.SpiMode = SPI_MODE_MASTER; + } + + if (cfg->mode & OS_SPI_3WIRE) + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + else + { + init.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + + if (cfg->data_width == 8) + { + init.DataLen = SPI_DATA_SIZE_8BITS; + } + else if (cfg->data_width == 16) + { + init.DataLen = SPI_DATA_SIZE_16BITS; + } + else + { + return OS_EIO; + } + + if (cfg->mode & OS_SPI_CPHA) + { + init.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + } + else + { + init.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + } + + if (cfg->mode & OS_SPI_CPOL) + { + init.CLKPOL = SPI_CLKPOL_HIGH; + } + else + { + init.CLKPOL = SPI_CLKPOL_LOW; + } + + if (cfg->mode & OS_SPI_MSB) + { + init.FirstBit = SPI_FB_MSB; + } + else + { + init.FirstBit = SPI_FB_LSB; + } + + // HCLK:100MHz, APB2 CLK: 50MHz 100MHz / 2 + init.BaudRatePres = SPI_BR_PRESCALER_32;//cfg->max_hz; + + SPI_Init(hspi, &init); + + SPI_Enable(hspi, ENABLE); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", spi_bus->spi_bus.parent.name); + return OS_SUCCESS; +} + +static os_err_t spi_configure(struct os_spi_device *device, struct os_spi_configuration *configuration) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(configuration != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + spi_bus->cfg = configuration; + + return n32_spi_init(spi_bus, configuration); +} + +/* clang-format off */ +static uint32_t spixfer(struct os_spi_device *device, struct os_spi_message *message) +{ + OS_ASSERT(device != OS_NULL); + OS_ASSERT(device->bus != OS_NULL); + OS_ASSERT(message != OS_NULL); + + struct n32_spi_bus *spi_bus = os_container_of(device->bus, struct n32_spi_bus, spi_bus); + SPI_Module *hspi = spi_bus->hspi; + + if (message->cs_take + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_LOW); + } + + SPI_I2S_ReceiveData(hspi); + + // LOG_D(DBG_TAG, "%s transfer prepare and start", spi_drv->config->bus_name); + // LOG_D(DBG_TAG, + // "%s sendbuf: %X, recvbuf: %X, length: %d", + // spi_drv->config->bus_name, + // (uint32_t)message->send_buf, + // (uint32_t)message->recv_buf, + // message->length); + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + //ret = SPI_TransmitReceive_DMA SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else if (message->send_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + //ret = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + const uint8_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[i]); + } + } + else + { + const uint16_t *const send_buf = message->send_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, send_buf[p]); + } + } + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + } + } + else if (message->recv_buf) + { + if (spi_bus->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + //ret = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length); + } + else + { + int step = 1; + if (spi_bus->cfg->data_width > 8) + { + step = 2; + } + + if (step == 1) + { + uint8_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[i] = SPI_I2S_ReceiveData(hspi); + } + } + else + { + uint16_t *const recv_buf = message->recv_buf; + + for(int i=0; ilength; i+=step) + { + const int p = i >> 1; + + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG)); + SPI_I2S_TransmitData(hspi, recv_buf[i]); + while(!SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG)); + recv_buf[p] = SPI_I2S_ReceiveData(hspi); + } + } + } + } + else + { // 错误 message->send_buf、message->recv_buf 都是NULL + return 0; + } + + if (message->cs_release + && device->cs_pin >= 0) + { + os_pin_write(device->cs_pin, PIN_HIGH); + } + + return message->length; +} +/* clang-format on */ + +static const struct os_spi_ops n32_spi_bus_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; + +static int n32_spi_bus_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + os_err_t result = 0; + os_base_t level; + + struct n32_spi_bus *spi_bus = os_calloc(1, sizeof(struct n32_spi_bus)); + + OS_ASSERT(nt_spi); + + spi_bus->info = dev->info; + + spi_bus->hspi = spi_bus->info->hspi; + + level = os_irq_lock(); + os_list_add_tail(&n32_spi_list, &spi_bus->list); + os_irq_unlock(level); + + result = os_spi_bus_register(&spi_bus->spi_bus, dev->name, &n32_spi_bus_ops); + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s bus init done\r\n", dev->name); + + return result; +} + +OS_DRIVER_INFO n32_spi_driver = { + .name = "SPI_Module", + .probe = n32_spi_bus_probe, +}; + +OS_DRIVER_DEFINE(n32_spi_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_spi.h b/drivers/hal/nationstech/drivers/n32l43x/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..8f52de3fd80ba7bc2a991dfdaf3a578e7d2395b1 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_spi.h @@ -0,0 +1,61 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_spi.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +#include "n32g45x.h" + +struct n32_spi_info +{ + SPI_Module *hspi; + int rcc_type; + int rcc; + IRQn_Type irq; + + struct + { + DMA_ChannelType *channel; + int rcc; + IRQn_Type irq; + }dma_rx, dma_tx; + + GPIO_Module *nss_port; + int nss_pin; + int nss_rcc; + + GPIO_Module *sck_port; + int sck_pin; + int sck_rcc; + + GPIO_Module *miso_port; + int miso_pin; + int miso_rcc; + + GPIO_Module *mosi_port; + int mosi_pin; + int mosi_rcc; +}; + +#endif /* __DRV_SPI_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_usart.c b/drivers/hal/nationstech/drivers/n32l43x/drv_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..602cc0ddc6bbeb979559db08e6bff87e2fcdc534 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_usart.c @@ -0,0 +1,639 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.c + * + * @brief This file implements usart driver for apm32 + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.usart" +#include + +#include "drv_usart.h" + +typedef struct n32_usart +{ + struct os_serial_device serial; + + struct n32_usart_info *info; + + soft_dma_t sdma; + uint32_t sdma_hard_size; + + DMA_InitType DMA_InitStructure; + + uint8_t *rx_buff; + uint32_t rx_index; + uint32_t rx_size; + + const uint8_t *tx_buff; + uint32_t tx_count; + uint32_t tx_size; + + os_list_node_t list; +} n32_usart_t; + +static os_list_node_t n32_usart_list = OS_LIST_INIT(n32_usart_list); + +static const struct n32_usart_info *console_uart = OS_NULL; + +static void n32_usart_interrupt_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + OS_ASSERT(uart->rx_buff != OS_NULL); + OS_ASSERT(uart->rx_index < uart->rx_size); + + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + + uart->rx_buff[uart->rx_index++] = USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + if (uart->rx_index > 0) + { + soft_dma_timeout_irq(&uart->sdma); + } + } + + if (uart->rx_index == (uart->rx_size / 2)) + { + soft_dma_half_irq(&uart->sdma); + } + + if (uart->rx_index == uart->rx_size) + { + uart->rx_index = 0; + soft_dma_full_irq(&uart->sdma); + } +} + + +static void n32_usart_dma_rx(n32_usart_t *uart) +{ + if (USART_GetIntStatus(uart->info->huart, USART_INT_RXDNE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_RXDNE); + USART_ReceiveData(uart->info->huart); + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_IDLEF) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_IDLEF); + USART_ReceiveData(uart->info->huart); + + soft_dma_timeout_irq(&uart->sdma); + } +} + +static void n32_usart_irq_callback(n32_usart_t *uart) +{ + /* rx */ + if (uart->info->dma_channel == OS_NULL) + { + n32_usart_interrupt_rx(uart); + } + else + { + n32_usart_dma_rx(uart); + } + + /* tx */ + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXDE) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXDE); + + if (uart->tx_size > 0) + { + if (uart->tx_count == 0) + { + if (uart->info->send_start_hook) + { + uart->info->send_start_hook(); + } + } + + if (uart->tx_count < uart->tx_size) + USART_SendData(uart->info->huart, uart->tx_buff[uart->tx_count++]); + + if (uart->tx_count >= uart->tx_size) + { + uart->tx_size = 0; + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + os_hw_serial_isr_txdone((struct os_serial_device *)uart); + + USART_ConfigInt(uart->info->huart, USART_INT_TXC, ENABLE); + } + } + } + + if (USART_GetIntStatus(uart->info->huart, USART_INT_TXC) != RESET) + { + USART_ClrIntPendingBit(uart->info->huart, USART_INT_TXC); + USART_ConfigInt(uart->info->huart, USART_INT_TXC, DISABLE); + + if (uart->info->send_end_hook) + { + uart->info->send_end_hook(); + } + } +} + +static void usart_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + n32_usart_irq_callback(uart); + return; + } + } +} + +static void usart_dma_irqhandler(USART_Module *huart) +{ + n32_usart_t *uart; + + os_list_for_each_entry(uart, &n32_usart_list, n32_usart_t, list) + { + if (uart->info->huart == huart) + { + soft_dma_half_irq(&uart->sdma); + return; + } + } +} + +void USART1_IRQHandler(void) +{ +#ifdef USART1 + usart_irqhandler(USART1); +#endif +} + +void USART2_IRQHandler(void) +{ +#ifdef USART2 + usart_irqhandler(USART2); +#endif +} + +void USART3_IRQHandler(void) +{ +#ifdef USART3 + usart_irqhandler(USART3); +#endif +} + +void DMA_Channel5_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX5, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC5, DMA); + +#ifdef USART1 + usart_dma_irqhandler(USART1); +#endif +} + +void DMA_Channel6_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX6, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC6, DMA); + +#ifdef USART2 + usart_dma_irqhandler(USART2); +#endif +} + +void DMA_Channel3_IRQHandler(void) +{ + DMA_ClrIntPendingBit(DMA_INT_HTX3, DMA); + DMA_ClrIntPendingBit(DMA_INT_TXC3, DMA); + +#ifdef USART3 + usart_dma_irqhandler(USART3); +#endif +} + +/* interrupt rx mode */ +static uint32_t n32_sdma_int_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->rx_index; +} + +static os_err_t n32_sdma_int_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->rx_buff = buff; + uart->rx_index = 0; + uart->rx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_int_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + + return n32_sdma_int_get_index(dma); +} + +/* dma rx mode */ +static uint32_t n32_sdma_dma_get_index(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + return uart->sdma_hard_size - DMA_GetCurrDataCounter(uart->info->dma_channel); +} + +static os_err_t n32_sdma_dma_init(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + RCC_EnableAHBPeriphClk(uart->info->dma_rcc, ENABLE); + + uart->DMA_InitStructure.PeriphAddr = (uint32_t)&uart->info->huart->DAT; + uart->DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; + uart->DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE; + uart->DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + uart->DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + uart->DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Byte; + uart->DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR; + uart->DMA_InitStructure.Priority = DMA_PRIORITY_HIGH; + uart->DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE; + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + return OS_SUCCESS; +} + +static os_err_t n32_sdma_dma_start(soft_dma_t *dma, void *buff, uint32_t size) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + uart->sdma_hard_size = size; + + uart->DMA_InitStructure.MemAddr = (uint32_t)buff; + uart->DMA_InitStructure.BufSize = size; + + DMA_Init(uart->info->dma_channel, &uart->DMA_InitStructure); + DMA_EnableChannel(uart->info->dma_channel, ENABLE); + USART_EnableDMA(uart->info->huart, USART_DMAREQ_RX, ENABLE); + + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, ENABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, ENABLE); + + DMA_ConfigInt(uart->info->dma_channel, DMA_INT_TXC | DMA_INT_HTX, ENABLE); + + return OS_SUCCESS; +} + +static uint32_t n32_sdma_dma_stop(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + DMA_EnableChannel(uart->info->dma_channel, DISABLE); + + return n32_sdma_dma_get_index(dma); +} + +/* sdma callback */ +static void n32_usart_sdma_callback(soft_dma_t *dma) +{ + n32_usart_t *uart = os_container_of(dma, n32_usart_t, sdma); + + os_hw_serial_isr_rxdone((struct os_serial_device *)uart); +} + +static void n32_usart_sdma_init(struct n32_usart *uart, dma_ring_t *ring) +{ + soft_dma_t *dma = &uart->sdma; + + soft_dma_stop(dma); + + memset(&dma->hard_info, 0, sizeof(dma->hard_info)); + + dma->hard_info.mode = HARD_DMA_MODE_CIRCULAR; + dma->hard_info.max_size = 64 * 1024; + dma->hard_info.flag = HARD_DMA_FLAG_HALF_IRQ | HARD_DMA_FLAG_FULL_IRQ | HARD_DMA_FLAG_TIMEOUT_IRQ; + dma->hard_info.data_timeout = uart_calc_byte_timeout_us(uart->serial.config.baud_rate); + + if (uart->info->dma_channel == OS_NULL) + { + dma->ops.get_index = n32_sdma_int_get_index; + dma->ops.dma_init = OS_NULL; + dma->ops.dma_start = n32_sdma_int_start; + dma->ops.dma_stop = n32_sdma_int_stop; + } + else + { + dma->ops.get_index = n32_sdma_dma_get_index; + dma->ops.dma_init = n32_sdma_dma_init; + dma->ops.dma_start = n32_sdma_dma_start; + dma->ops.dma_stop = n32_sdma_dma_stop; + } + + dma->cbs.dma_half_callback = n32_usart_sdma_callback; + dma->cbs.dma_full_callback = n32_usart_sdma_callback; + dma->cbs.dma_timeout_callback = n32_usart_sdma_callback; + + soft_dma_init(dma); + soft_dma_start(dma, ring); + soft_dma_irq_enable(&uart->sdma, OS_TRUE); +} + +static int __n32_usart_init(const struct n32_usart_info *uart_info, struct serial_configure *cfg) +{ + GPIO_InitType GPIO_InitStructure; + USART_InitType USART_InitStructure; + + RCC_EnableAPB2PeriphClk(uart_info->tx_rcc, ENABLE); + RCC_EnableAPB2PeriphClk(uart_info->rx_rcc, ENABLE); + + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitStructure.Pin = uart_info->tx_pin; + GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Up; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Alternate = uart_info->tx_af; + GPIO_InitPeripheral(uart_info->tx_port, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = uart_info->rx_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Alternate = uart_info->rx_af; + GPIO_InitPeripheral(uart_info->rx_port, &GPIO_InitStructure); + + USART_InitStructure.BaudRate = cfg->baud_rate; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.StopBits = USART_STPB_1; + break; + case STOP_BITS_2: + USART_InitStructure.StopBits = USART_STPB_2; + break; + default: + return OS_INVAL; + } + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.Parity = USART_PE_NO; + break; + case PARITY_ODD: + USART_InitStructure.Parity = USART_PE_ODD; + break; + case PARITY_EVEN: + USART_InitStructure.Parity = USART_PE_EVEN; + break; + default: + return OS_INVAL; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + USART_InitStructure.WordLength = USART_WL_8B; + break; + case DATA_BITS_9: + USART_InitStructure.WordLength = USART_WL_9B; + break; + default: + return OS_INVAL; + } + + switch(uart_info->rcc_type) + { + case 1: + RCC_EnableAPB1PeriphClk(uart_info->rcc, ENABLE); + break; + case 2: + RCC_EnableAPB2PeriphClk(uart_info->rcc, ENABLE); + break; + } + + USART_DeInit(uart_info->huart); + USART_Init(uart_info->huart, &USART_InitStructure); + USART_ConfigInt(uart_info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart_info->huart, USART_INT_RXDNE, DISABLE); + USART_Enable(uart_info->huart, ENABLE); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_init(struct os_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + OS_ASSERT(cfg != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + __n32_usart_init(uart->info, cfg); + + NVIC_InitType NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannel = uart->info->irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + n32_usart_sdma_init(uart, &serial->rx_fifo->ring); + + return OS_SUCCESS; +} + +static os_err_t n32_usart_deinit(struct os_serial_device *serial) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + /* rx */ + USART_ConfigInt(uart->info->huart, USART_INT_IDLEF, DISABLE); + USART_ConfigInt(uart->info->huart, USART_INT_RXDNE, DISABLE); + + if (uart->info->dma_channel != OS_NULL) + { + soft_dma_stop(&uart->sdma); + DMA_DeInit(uart->info->dma_channel); + } + + /* tx */ + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, DISABLE); + + uart->tx_buff = OS_NULL; + uart->tx_count = 0; + uart->tx_size = 0; + + return 0; +} + +static int n32_uart_start_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + uart->tx_buff = buff; + uart->tx_count = 0; + uart->tx_size = size; + + USART_ConfigInt(uart->info->huart, USART_INT_TXDE, ENABLE); + + return size; +} + +/* clang-format off */ +static int n32_usart_poll_send(struct os_serial_device *serial, const uint8_t *buff, os_size_t size) +{ + int i; + struct n32_usart *uart; + + OS_ASSERT(serial != OS_NULL); + + uart = os_container_of(serial, struct n32_usart, serial); + + for (i = 0; i < size; i++) + { + while (USART_GetFlagStatus(uart->info->huart, USART_FLAG_TXC) == RESET); + USART_SendData(uart->info->huart, buff[i]); + } + + return size; +} +/* clang-format on */ + +static const struct os_uart_ops n32_usart_ops = { + .init = n32_usart_init, + .deinit = n32_usart_deinit, + + .start_send = n32_uart_start_send, + .poll_send = n32_usart_poll_send, +}; + +static int n32_usart_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + os_err_t result = 0; + os_base_t level; + + struct n32_usart *uart = os_calloc(1, sizeof(struct n32_usart)); + + OS_ASSERT(uart); + + uart->info = (void*)dev->info; + + struct os_serial_device *serial = &uart->serial; + + serial->ops = &n32_usart_ops; + serial->config = config; + + level = os_irq_lock(); + os_list_add_tail(&n32_usart_list, &uart->list); + os_irq_unlock(level); + + result = os_hw_serial_register(serial, dev->name, NULL); + + OS_ASSERT(result == OS_EOK); + + os_kprintf(DRV_EXT_TAG ": %s init done\r\n", dev->name); + + return result; +} + +/* clang-format off */ +void __os_hw_console_output(char *str) +{ + int i; + + if (console_uart == OS_NULL) + return; + + for (i = 0; i < strlen(str); i++) + { + while (USART_GetFlagStatus(console_uart->huart, USART_FLAG_TXC) == RESET); + USART_SendData(console_uart->huart, str[i]); + } +} +/* clang-format on */ + +OS_DRIVER_INFO n32_usart_driver = { + .name = "USART_Module", + .probe = n32_usart_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); + +static int n32_usart_early_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + if (strcmp(dev->name, OS_CONSOLE_DEVICE_NAME)) + return OS_SUCCESS; + + console_uart = (const struct n32_usart_info *)dev->info; + + struct serial_configure config = OS_SERIAL_CONFIG_DEFAULT; + + __n32_usart_init(console_uart, &config); + + return OS_SUCCESS; +} + +OS_DRIVER_INFO n32_usart_early_driver = { + .name = "USART_Module", + .probe = n32_usart_early_probe, +}; + +OS_DRIVER_DEFINE(n32_usart_early_driver, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_LOW); diff --git a/drivers/hal/nationstech/drivers/n32l43x/drv_usart.h b/drivers/hal/nationstech/drivers/n32l43x/drv_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..6be814fdadfd27c4eb359c0fc6158800059e8720 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/drv_usart.h @@ -0,0 +1,56 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_usart.h + * + * @brief This file provides functions declaration for usart driver. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include + +#include "drv_common.h" + +struct n32_usart_info +{ + USART_Module *huart; + int rcc_type; + int rcc; + IRQn_Type irq; + + DMA_ChannelType *dma_channel; + int dma_rcc; + IRQn_Type dma_irq; + + GPIO_Module *tx_port; + int tx_pin; + int tx_rcc; + int tx_af; // IO复用 + + GPIO_Module *rx_port; + int rx_pin; + int rx_rcc; + int rx_af; + + void (*init_hook)(void); + void (*send_start_hook)(void); + void (*send_end_hook)(void); +}; + +#endif /* __DRV_USART_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.c b/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..69dcee0c93f300428df2a970782fac835dc4b0ed --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.c @@ -0,0 +1,167 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash_common.c + * + * @brief This file provides flash read/write/erase functions for N32. + * + * @revision + * Date Author Notes + * 2022-01-11 OneOS Team First Version + *********************************************************************************************************************** + */ +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.flash" +#include + +#include "drv_flash.h" + +#define N32_FLASH_BLOCK_SIZE (2 * 1024) +#define N32_FLASH_PAGE_SIZE (2 * 1024) + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size) +{ + size_t i; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(uint8_t *)addr; + } + + return size; +} + +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size) +{ + size_t i, j; + os_err_t result = 0; + uint32_t write_data = 0, temp_data = 0; + + if ((addr + size) > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: write outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + if (addr % 4 != 0) + { + LOG_E(DRV_EXT_TAG, "write addr must be 4-byte alignment"); + return OS_INVAL; + } + + FLASH_Unlock(); + + if (size < 1) + { + return OS_INVAL; + } + + for (i = 0; i < size;) + { + if ((size - i) < 4) + { + for (j = 0; (size - i) > 0; i++, j++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + else + { + for (j = 0; j < 4; j++, i++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf++; + } + } + + /* write data */ + if (FLASH_ProgramWord(addr, write_data) == FLASH_COMPL) + { + /* Check the written value */ + if (*(uint32_t *)addr != write_data) + { + LOG_E(DRV_EXT_TAG, "ERROR: write data != read data"); + result = OS_FAILURE; + goto __exit; + } + } + else + { + result = OS_FAILURE; + goto __exit; + } + + temp_data = 0; + write_data = 0; + + addr += 4; + } + +__exit: + FLASH_Lock(); + if (result != 0) + { + return result; + } + + return size; +} + +int n32_flash_erase(uint32_t addr, size_t size) +{ + os_err_t result = OS_SUCCESS; + + const uint32_t page_addr_mask = ~(N32_FLASH_PAGE_SIZE - 1); + uint32_t end_addr = addr + size; + + if (end_addr > N32_FLASH_END_ADDR) + { + LOG_E(DRV_EXT_TAG, "ERROR: erase outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return OS_INVAL; + } + + FLASH_Unlock(); + + for (uint32_t page = addr & page_addr_mask; page < end_addr; page+=N32_FLASH_PAGE_SIZE) + { + if (FLASH_EraseOnePage(page) != FLASH_COMPL) + { + result = OS_FAILURE; + goto __exit; + } + } + +__exit: + FLASH_Lock(); + + if (result != OS_SUCCESS) + { + return result; + } + + LOG_D(DRV_EXT_TAG, "erase done: addr (0x%p), size %d", (void *)addr, size); + return size; +} + +#include "fal_drv_flash.c" diff --git a/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.h b/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..858a52838ca87e753923bdb557496e316c234563 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/flash/drv_flash.h @@ -0,0 +1,42 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file drv_flash.h + * + * @brief This file provides declaration for flash functions. + * + * @revision + * Date Author Notes + * 2021-05-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __DRV_FLASH_H__ +#define __DRV_FLASH_H__ + +#include "drv_cfg.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(uint32_t addr, uint8_t *buf, size_t size); +int n32_flash_write(uint32_t addr, const uint8_t *buf, size_t size); +int n32_flash_erase(uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H__ */ diff --git a/drivers/hal/nationstech/drivers/n32l43x/flash/fal_drv_flash.c b/drivers/hal/nationstech/drivers/n32l43x/flash/fal_drv_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..e5d7f226968ee865c4cd5ffca3db3599acde74e2 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/flash/fal_drv_flash.c @@ -0,0 +1,73 @@ +#include "string.h" +#include +#include +#include "dlog.h" + +#include "drv_flash.h" + +#if defined(OS_USING_FAL) +#include "fal.h" +#include "ports/flash_info.c" +#endif + +static int n32_fal_flash_read(fal_flash_t *flash, uint32_t page_addr, uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_read(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_write(fal_flash_t *flash, uint32_t page_addr, const uint8_t *buff, uint32_t page_nr) +{ + int count = n32_flash_write(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + buff, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_fal_flash_erase(fal_flash_t *flash, uint32_t page_addr, uint32_t page_nr) +{ + int count = n32_flash_erase(N32_FLASH_START_ADDR + page_addr * N32_FLASH_PAGE_SIZE, + page_nr * N32_FLASH_PAGE_SIZE); + + return (count == page_nr * N32_FLASH_PAGE_SIZE) ? 0 : -1; +} + +static int n32_flash_probe(const os_driver_info_t *drv, const os_device_info_t *dev) +{ + fal_flash_t *fal_flash = os_calloc(1, sizeof(fal_flash_t)); + + if (fal_flash == OS_NULL) + { + os_kprintf("fal flash mem leak %s.\r\n", dev->name); + return -1; + } + + struct onchip_flash_info *flash_info = (struct onchip_flash_info *)dev->info; + + memcpy(fal_flash->name, dev->name, min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))); + + fal_flash->name[min(FAL_DEV_NAME_MAX - 1, strlen(dev->name))] = 0; + + fal_flash->capacity = flash_info->capacity; + fal_flash->block_size = flash_info->block_size; + fal_flash->page_size = flash_info->page_size; + + fal_flash->ops.read_page = n32_fal_flash_read; + fal_flash->ops.write_page = n32_fal_flash_write; + fal_flash->ops.erase_block = n32_fal_flash_erase; + + fal_flash->priv = flash_info; + + return fal_flash_register(fal_flash); +} + +OS_DRIVER_INFO n32_flash_driver = { + .name = "N32L43X_Onchip_Flash", + .probe = n32_flash_probe, +}; + +OS_DRIVER_DEFINE(n32_flash_driver, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_HIGH); diff --git a/drivers/hal/nationstech/drivers/n32l43x/flash/weave.yaml b/drivers/hal/nationstech/drivers/n32l43x/flash/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7912c209f51b95324783ded1ee7b081e7acc66ad --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/flash/weave.yaml @@ -0,0 +1,15 @@ +# 组名 +group_name: hal/drivers + +# 依赖宏控 +depend_macro: + - MANUFACTOR_NATIONSTECH + +# 编译连接信息 +build_option: + cpppath: + - . ? {is_define("BSP_USING_ONCHIP_FLASH")} + +# 源码 +source_file: + - drv_flash.c ? {is_define("BSP_USING_ONCHIP_FLASH")} diff --git a/drivers/hal/nationstech/drivers/n32l43x/n32_it.c b/drivers/hal/nationstech/drivers/n32l43x/n32_it.c new file mode 100644 index 0000000000000000000000000000000000000000..25e7b16e49a9e347ba0d0d4a18893bc2827b36c6 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/n32_it.c @@ -0,0 +1,73 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file n32_it.c + * + * @brief This file provides systick time init/IRQ functions. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#include "os_clock.h" +#include "os_stddef.h" +#include "oneos_config.h" + +#ifdef OS_USING_CLOCKSOURCE +#include +#include +#endif + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "drv.irq" +#include + +#include "n32_it.h" +#include "drv_gpio.h" +#include "drv_usart.h" + +void NMI_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + while (1); +} + +void MemManage_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Memory Manage exception occurs */ + while (1); +} + +void BusFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Bus Fault exception occurs */ + while (1); +} + +void UsageFault_Handler(void) +{ + if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected + __BKPT(0); // halt program execution here + } + /* Go to infinite loop when Usage Fault exception occurs */ + while (1); +} diff --git a/drivers/hal/nationstech/drivers/n32l43x/n32_it.h b/drivers/hal/nationstech/drivers/n32l43x/n32_it.h new file mode 100644 index 0000000000000000000000000000000000000000..ee875664d40ff94b5c3aa75b5b93df07cfcb8413 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/n32_it.h @@ -0,0 +1,48 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file apm32_it.h + * + * @brief This file provides systick IRQ declaration. + * + * @revision + * Date Author Notes + * 2022-01-10 OneOS Team First Version + *********************************************************************************************************************** + */ +#ifndef __N32_IT__ +#define __N32_IT__ + +#include + +#ifdef SERIES_N32G4XX +#include "n32g45x_hal.h" +#endif + +#ifdef SERIES_N32L40X +#include "n32l40x_hal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef NVIC_PriorityGroup_4 +#define NVIC_PriorityGroup NVIC_PriorityGroup_4 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/hal/nationstech/drivers/n32l43x/weave.yaml b/drivers/hal/nationstech/drivers/n32l43x/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8af8fc694ebef397b92354092fea1cb0f609ed76 --- /dev/null +++ b/drivers/hal/nationstech/drivers/n32l43x/weave.yaml @@ -0,0 +1,24 @@ +# 组名 +group_name: hal/drivers + +# 依赖宏控 +depend_macro: + - SERIES_N32L43X + +# 编译连接信息 +build_option: + cpppath: + - . + +# 源码 +source_file: + - drv_common.c + - n32_it.c + - drv_gpio.c ? {is_define("BSP_USING_GPIO")} + - drv_usart.c ? {is_define("BSP_USING_USART")} + - drv_adc.c ? {is_define("BSP_USING_ADC")} + - drv_spi.c ? {is_define("BSP_USING_SPI")} + +# 子目录 +add_subdirectory: + - flash ? {is_define("BSP_USING_ONCHIP_FLASH")} \ No newline at end of file diff --git a/drivers/hal/nationstech/drivers/weave.yaml b/drivers/hal/nationstech/drivers/weave.yaml index f4a02ad44dba79bdb39526dcdb50d39498f35bf4..cc1b439c59c6b31a892515688b1f398ee3928fbe 100644 --- a/drivers/hal/nationstech/drivers/weave.yaml +++ b/drivers/hal/nationstech/drivers/weave.yaml @@ -1,20 +1,6 @@ -# 组名 -group_name: hal/drivers - -# 依赖宏控 -depend_macro: - - MANUFACTOR_NATIONSTECH - -# 编译连接信息 -build_option: - cpppath: - - . - - flash ? {is_define("BSP_USING_ONCHIP_FLASH")} - -# 源码 -source_file: - - n32_it.c - - drv_common.c - - drv_gpio.c ? {is_define("BSP_USING_GPIO")} - - drv_usart.c ? {is_define("BSP_USING_USART")} - - flash/drv_flash.c ? {is_define("BSP_USING_ONCHIP_FLASH") and is_define("SERIES_N32G4XX")} +# 子目录 +add_subdirectory: + - n32g43x ? {is_define("SERIES_N32G43X")} + - n32g45x ? {is_define("SERIES_N32G45X")} + - n32l40x ? {is_define("SERIES_N32L40X")} + - n32l43x ? {is_define("SERIES_N32L43X")} diff --git a/drivers/hal/st/drivers/drv_dcmi.c b/drivers/hal/st/drivers/drv_dcmi.c index 8e4734529e5086f2458d48911def03a83d425aec..8dc84e891bfae1f60c7299cacacf7fdb8d469f7e 100644 --- a/drivers/hal/st/drivers/drv_dcmi.c +++ b/drivers/hal/st/drivers/drv_dcmi.c @@ -232,12 +232,6 @@ bool ll_cam_dma_sizes(cam_obj_t *cam) } else { -#if 0 - cam->dma_half_buffer_cnt = 2; - cam->dma_buffer_size = cam->width * cam->height*2*2; - cam->dma_half_buffer_size = cam->dma_buffer_size/2; - cam->dma_node_buffer_size = cam->dma_half_buffer_size; -#endif return ll_cam_calc_rgb_dma(cam); } return 1; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2d6e889c9a5be18801f676b8901e5c19b4a1991b..859ecb554905dc3249e1c2308e3efc0d19b41324 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -54,5 +54,46 @@ menuconfig OS_USING_WLAN default 32 endif - +menuconfig BSP_USING_BK7231N + bool "bk7231n" + select OS_USING_WLAN + select OS_USING_BK_WIFI + select BSP_USING_BK_WIFI + select BSP_USING_BK_LWIP + default n + + if BSP_USING_BK7231N + + choice + prompt "bk7231n mode" + default OS_USING_BK_AP + depends on BSP_USING_BK7231N + + config OS_USING_BK_STATION + bool "bk7231n in sta mode" + + config OS_USING_BK_AP + bool "bk7231n in ap mode" + if OS_USING_BK_AP + config BSP_USING_BK_AP_SSID + string "ssid for ap mode" + default "bk7231n" + + config BSP_USING_BK_AP_PASSWORD + string "password for ap mode" + default "12345678" + + config BSP_USING_BK_AP_CHANNEL + int "channel for ap mode" + default 1 + + config BSP_USING_BK_AP_SECURITY + int "security for ap mode" + default 1 + + endif + endchoice + + endif + endmenu diff --git a/drivers/net/wlan_dev.c b/drivers/net/wlan_dev.c index 8cf92b06f3ee3eb9b3084c89686c11706e7dfb54..992ebf88810143262c33668f90a6e31d0d737a40 100644 --- a/drivers/net/wlan_dev.c +++ b/drivers/net/wlan_dev.c @@ -195,6 +195,12 @@ os_err_t os_wlan_scan_clean_result(struct os_wlan_device *wlan_dev) return OS_EIO; } + if (wlan_dev->scan_result->scan_info) + { + os_free(wlan_dev->scan_result->scan_info); + wlan_dev->scan_result->scan_info = OS_NULL; + } + if (wlan_dev->scan_result) { os_free(wlan_dev->scan_result); diff --git a/drivers/net/wlan_dev.h b/drivers/net/wlan_dev.h index 0d1efd65d6a11e2620aa64ef1045cd9f37538532..883d8308dbc7ba98f87cb7811b74593931669f7c 100644 --- a/drivers/net/wlan_dev.h +++ b/drivers/net/wlan_dev.h @@ -27,6 +27,9 @@ #include #include "net_dev.h" +#define OS_WLAN_FLAG_STA_ONLY (0x1 << 0) +#define OS_WLAN_FLAG_AP_ONLY (0x1 << 1) + #define OS_WLAN_EVET_AP_START 0x01 #define OS_WLAN_EVET_AP_STOP 0x02 #define OS_WLAN_EVET_STA_START 0x03 diff --git a/drivers/serial/weave.yaml b/drivers/serial/weave.yaml index 081843666cbea09ce4a0fb90de2f6ae99c8841f4..1f5b64973b908c8811a974105a317cda941faef8 100644 --- a/drivers/serial/weave.yaml +++ b/drivers/serial/weave.yaml @@ -14,5 +14,6 @@ build_option: source_file: - serial.c -add_directory: +# 子目录 +add_subdirectory: - ./* \ No newline at end of file diff --git a/drivers/spi/spi_msd.c b/drivers/spi/spi_msd.c index 0fe951f95ed715e586ee6ebb814eb19418a2e9bf..0e199aadf32a0621605508728117c640c4bac9ad 100644 --- a/drivers/spi/spi_msd.c +++ b/drivers/spi/spi_msd.c @@ -1552,11 +1552,11 @@ static os_err_t msd_blk_init(os_blk_device_t *blk) /* Memory capacity = (C_SIZE+1) * 512K byte */ card_capacity = (C_SIZE + 1) / 2; /* Unit : Mbyte */ - msd->blk_dev.geometry.capacity = card_capacity; /* 512KB = 1024sector */ + msd->blk_dev.geometry.capacity = card_capacity * 1024ull * 1024ull; /* Byte */ MSD_DEBUG("[info] card capacity : %d.%d Gbyte\r\n", card_capacity / 1024, (card_capacity % 1024) * 100 / 1024); - MSD_DEBUG("[info] sector_count : %d\r\n", + MSD_DEBUG("[info] sector_count : %llu\r\n", msd->blk_dev.geometry.capacity / msd->blk_dev.geometry.block_size); } else diff --git a/kernel/Kconfig b/kernel/Kconfig index 2f73e8a78835e0ee7e1ea31999169611d028d49c..3bd3a5582f5ed117eab1aea62e64e5ac9650a4a2 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -1,5 +1,30 @@ menu "Kernel" + config OS_BOARD_SUPPORT_SMP + bool + default n + + choice + prompt "The max size of kernel object name" + default OS_NAME_MAX_15 + + config OS_NAME_MAX_7 + bool "7" + + config OS_NAME_MAX_15 + bool "15" + + config OS_NAME_MAX_31 + bool "31" + endchoice + config OS_NAME_MAX + int + default 7 if OS_NAME_MAX_7 + default 15 if OS_NAME_MAX_15 + default 31 if OS_NAME_MAX_31 + +menu "SMP" + depends on OS_BOARD_SUPPORT_SMP config OS_USING_SMP bool "Enable SMP" default n @@ -19,25 +44,9 @@ menu "Kernel" config OS_SCHED_STRATEGY_ALL_IPI_SET bool "os sched strategy by setting all suitable ipis" endchoice - choice - prompt "The max size of kernel object name" - default OS_NAME_MAX_15 - - config OS_NAME_MAX_7 - bool "7" - - config OS_NAME_MAX_15 - bool "15" - - config OS_NAME_MAX_31 - bool "31" - endchoice - config OS_NAME_MAX - int - default 7 if OS_NAME_MAX_7 - default 15 if OS_NAME_MAX_15 - default 31 if OS_NAME_MAX_31 +endmenu +menu "Task" choice prompt "The max level value of priority of task" default OS_TASK_PRIORITY_32 @@ -76,81 +85,6 @@ menu "Kernel" range 1 100 default 10 - config OS_USING_OVERFLOW_CHECK - bool "Using stack overflow checking" - default y - help - Enable task stack overflow checking. The stack overflow is checking when - each task switch. - - config OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK - bool "Using interrupt stack overflow checking" - default n - help - Enable interrupt stack overflow checking. The interrupt stack overflow is checking when - each interrupt exit. - - config OS_USING_TASK_HOOK - bool "Using task hook" - default n - help - Allows user to register hooks with task module. - - config OS_USING_ASSERT - bool "Enable global assert" - depends on OS_DEBUG - default y - - config OS_USING_KERNEL_LOCK_CHECK - bool "Enable kernel lock check" - depends on OS_DEBUG - select OS_USING_ASSERT - default y - - config OS_USING_SAFETY_MECHANISM - bool "Enable function safety mechanism" - select OS_USING_ASSERT - select OS_USING_OVERFLOW_CHECK - default n - - - config OS_USING_KERNEL_DEBUG - bool "Enable kernel debug" - depends on OS_DEBUG - default y - - if OS_USING_KERNEL_DEBUG - choice - prompt "The global log level of kernel" - default KLOG_GLOBAL_LEVEL_WARNING - - config KLOG_GLOBAL_LEVEL_ERROR - bool "Error" - config KLOG_GLOBAL_LEVEL_WARNING - bool "Warning" - config KLOG_GLOBAL_LEVEL_INFO - bool "Infomation" - config KLOG_GLOBAL_LEVEL_DEBUG - bool "Debug" - endchoice - config KLOG_GLOBAL_LEVEL - int - default 0 if KLOG_GLOBAL_LEVEL_ERROR - default 1 if KLOG_GLOBAL_LEVEL_WARNING - default 2 if KLOG_GLOBAL_LEVEL_INFO - default 3 if KLOG_GLOBAL_LEVEL_DEBUG - - config KLOG_USING_COLOR - bool "Enable color log" - default y - help - The log will has different color by level - - config KLOG_WITH_FUNC_LINE - bool "Enable kernel log with function name and line number" - default y - endif - config OS_SYS_TASK_STACK_SIZE int "The stack size of sys task" default 2048 @@ -162,7 +96,9 @@ menu "Kernel" config OS_RECYCLE_TASK_STACK_SIZE int "The stack size of recycle task" default 512 +endmenu +menu "Timer" config OS_USING_KERNEL_TIMER bool "Enable kernel timer" default y @@ -208,7 +144,157 @@ menu "Kernel" endif endchoice endif +endmenu + +menu "Log" + config OS_USING_KERNEL_DEBUG + bool "Enable kernel log" + depends on OS_DEBUG + default y + + if OS_USING_KERNEL_DEBUG + choice + prompt "The global log level of kernel" + default KLOG_GLOBAL_LEVEL_WARNING + config KLOG_GLOBAL_LEVEL_ERROR + bool "Error" + config KLOG_GLOBAL_LEVEL_WARNING + bool "Warning" + config KLOG_GLOBAL_LEVEL_INFO + bool "Infomation" + config KLOG_GLOBAL_LEVEL_DEBUG + bool "Debug" + endchoice + config KLOG_GLOBAL_LEVEL + int + default 0 if KLOG_GLOBAL_LEVEL_ERROR + default 1 if KLOG_GLOBAL_LEVEL_WARNING + default 2 if KLOG_GLOBAL_LEVEL_INFO + default 3 if KLOG_GLOBAL_LEVEL_DEBUG + + config KLOG_USING_COLOR + bool "Enable color log" + default y + help + The log will has different color by level + + config KLOG_WITH_FUNC_LINE + bool "Enable kernel log with function name and line number" + default y + endif +endmenu + +menu "Debug" +menu "Check" + config OS_USING_OVERFLOW_CHECK + bool "Using stack overflow checking" + default y + help + Enable task stack overflow checking. The stack overflow is checking when + each task switch. + + config OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK + bool "Using interrupt stack overflow checking" + default n + help + Enable interrupt stack overflow checking. The interrupt stack overflow is checking when + each interrupt exit. + + config OS_USING_TASK_HOOK + bool "Using task hook" + default n + help + Allows user to register hooks with task module. + + config OS_USING_ASSERT + bool "Enable global assert" + depends on OS_DEBUG + default y + + config OS_USING_KERNEL_LOCK_CHECK + bool "Enable kernel lock check" + depends on OS_DEBUG + select OS_USING_ASSERT + default y + + config OS_USING_SAFETY_MECHANISM + bool "Enable function safety mechanism" + select OS_USING_ASSERT + select OS_USING_OVERFLOW_CHECK + default n +endmenu # check +menu "CPU monitor" + config OS_USING_CPU_MONITOR + bool "Monitor CPU usage" + select OS_USING_TASK_HOOK + select OS_TASK_SWITCH_NOTIFY + default n + help + Monitor CPU usage over a period of time. + +endmenu # CPU monitor + +source "$OS_ROOT/kernel/source/debug/mem_monitor/Kconfig" + +menu "Stack trace" + config STACK_TRACE_EN + bool "Stack back trace enable" + default n + + if STACK_TRACE_EN + config EXC_DUMP_STACK + bool "back trace dump stack" + default n + config TASK_STACK_OVERFLOW_STACK_SIZE + int "The stack overflow back trace size" + default 256 + + config CALL_BACK_TRACE_MAX_DEPTH + int "The stack back trace max depth" + default 10 + endif +endmenu # stack trace +endmenu + +menu "IPC" + +menu "IPC Trace & Hook" + config OS_USING_IPC_TRACE + bool "Enable IPC Trace" + default n + select OS_USING_IPC_HOOK + + config OS_IPC_TRACE_ITEM_NUM + int "Maximum IPC Trace item" + depends on OS_USING_IPC_TRACE + default 10 + + config OS_USING_IPC_HOOK + bool "Enable IPC Hook" + default n +endmenu # IPC Trace & Hook +menu "Event" + config OS_USING_EVENT + bool "Enable event flag" + default y +endmenu # Event +menu "Mailbox" + config OS_USING_MAILBOX + bool "Enable mailbox" + default y +endmenu # mailbox +menu "Message queue" + config OS_USING_MESSAGEQUEUE + bool "Enable message queue" + default y +endmenu # MQ +menu "Mutex" + config OS_USING_MUTEX + bool "Enable mutex" + default y +endmenu # mutex +menu "Workqueue" config OS_USING_WORKQUEUE bool "Enable workqueue" depends on OS_USING_KERNEL_TIMER @@ -229,16 +315,8 @@ menu "Kernel" default 0 endif endif - - menu "Inter-task communication and synchronization" - config OS_USING_MUTEX - bool "Enable mutex" - default y - - config OS_USING_SPINLOCK_CHECK - bool "Enable spinlock check" - default n - +endmenu # workqueue +menu "Semaphore" config OS_USING_SEMAPHORE bool "Enable semaphore" default y @@ -268,22 +346,17 @@ menu "Kernel" int "Supported Maximum Semaphore Trace Number" depends on OS_USING_SEM_TRACE default 5 +endmenu # semaphore +menu "Spinlock" + config OS_USING_SPINLOCK_CHECK + bool "Enable spinlock check" + default n +endmenu # Spinlock +endmenu # IPC - config OS_USING_EVENT - bool "Enable event flag" - default y - - config OS_USING_MESSAGEQUEUE - bool "Enable message queue" - default y - - config OS_USING_MAILBOX - bool "Enable mailbox" - default y - endmenu - - menu "Memory management" - config OS_USING_DEFAULT_HEAP +menu "Memory" +menu "Memory-Heap" + config OS_USING_DEFAULT_HEAP bool "Enable Default-Memory-Heap" default y select OS_USING_HEAP @@ -326,7 +399,9 @@ menu "Kernel" help When enable OS_USING_MEM_TRACE with shell, developer can call cmd memtrace endif +endmenu # Memory-Heap +menu "Memory-Pool" config OS_USING_MEM_POOL bool "Enable Memory-Pool" default y @@ -340,49 +415,6 @@ menu "Kernel" help when free memory, will check memory block tag. endif - endmenu - - - config OS_USING_IPC_TRACE - bool "Enable IPC Trace" - default n - select OS_USING_IPC_HOOK - - config OS_IPC_TRACE_ITEM_NUM - int "Maximum IPC Trace item" - depends on OS_USING_IPC_TRACE - default 10 - - config OS_USING_IPC_HOOK - bool "Enable IPC Hook" - default n - - menu "Debug" - config STACK_TRACE_EN - bool "Stack back trace enable" - default n - - if STACK_TRACE_EN - config EXC_DUMP_STACK - bool "back trace dump stack" - default n - config TASK_STACK_OVERFLOW_STACK_SIZE - int "The stack overflow back trace size" - default 256 - - config CALL_BACK_TRACE_MAX_DEPTH - int "The stack back trace max depth" - default 10 - endif - - config OS_USING_CPU_MONITOR - bool "Monitor CPU usage" - select OS_USING_TASK_HOOK - select OS_TASK_SWITCH_NOTIFY - default n - help - Monitor CPU usage over a period of time. - - source "$OS_ROOT/kernel/source/debug/mem_monitor/Kconfig" - endmenu +endmenu # Memory-Pool +endmenu # Memory endmenu diff --git a/notice.txt b/notice.txt new file mode 100644 index 0000000000000000000000000000000000000000..bbd9d9a208989ef088ff21987886a440ff32241a --- /dev/null +++ b/notice.txt @@ -0,0 +1,382 @@ +OPEN SOURCE SOFTWARE NOTICE + +Please note we provide an open source software notice along with this product and/or this product firmware (in the following just “this product”). The open source software licenses are granted by the respective right holders. And the open source licenses prevail all other license information with regard to the respective open source software contained in the product, including but not limited to End User Software Licensing Agreement. This notice is provided on behalf of Huawei Technologies Co. Ltd. and any of its local subsidiaries which may have provided this product to you in your local country. + +Warranty Disclaimer +THE OPEN SOURCE SOFTWARE IN THIS PRODUCT IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL, BUT WITHOUT ANY WARRANTY, WITHOUT EVEN THE IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +Software: easyflash-v4.1 +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: +The MIT License (MIT) + +Copyright (c) 2014-2020 Armink (armink.ztl@gmail.com) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +'Software'), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +Software: h264 +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: GNU LGPL 2.1 + +/* + * Copyright (c) 2000-2003 Fabrice Bellard + * + * This file is part of FFmpeg. + * + * FFmpeg is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * FFmpeg is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with FFmpeg; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Software: arm2d +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: +[Software Name] is licensed under Apache 2.0 + +This product includes software developed at +The Apache Software Foundation (http://www.apache.org/). + +Software: lvgl +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +MIT licence +Copyright (c) 2021 LVGL Kft + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Software: jerryscript  +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: +[Software Name] is licensed under Apache 2.0 + +This product includes software developed at +The Apache Software Foundation (http://www.apache.org/). + + +oftware: Freecoap +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: BSD +/* + * Copyright (c) 2015 Keith Cullen. + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +software: lwip +Copyright notice: +Copyright (c) [Year] [name of copyright holder] +License: BSD + +/** + * @file + * @defgroup altcp Application layered TCP Functions + * @ingroup altcp_api + * + * This file contains the common functions for altcp to work. + * For more details see @ref altcp_api. + */ + +/** + * @defgroup altcp_api Application layered TCP Introduction + * @ingroup callbackstyle_api + * + * Overview + * -------- + * altcp (application layered TCP connection API; to be used from TCPIP thread) + * is an abstraction layer that prevents applications linking hard against the + * @ref tcp.h functions while providing the same functionality. It is used to + * e.g. add SSL/TLS (see LWIP_ALTCP_TLS) or proxy-connect support to an application + * written for the tcp callback API without that application knowing the + * protocol details. + * + * * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + * * This is achieved by simply including "lwip/altcp.h" instead of "lwip/tcp.h", + * replacing "struct tcp_pcb" with "struct altcp_pcb" and prefixing all functions + * with "altcp_" instead of "tcp_". + * + * With altcp support disabled (LWIP_ALTCP==0), applications written against the + * altcp API can still be compiled but are directly linked against the tcp.h + * callback API and then cannot use layered protocols. To minimize code changes + * in this case, the use of altcp_allocators is strongly suggested. + * + * Usage + * ----- + * To make use of this API from an existing tcp raw API application: + * * Include "lwip/altcp.h" instead of "lwip/tcp.h" + * * Replace "struct tcp_pcb" with "struct altcp_pcb" + * * Prefix all called tcp API functions with "altcp_" instead of "tcp_" to link + * against the altcp functions + * * @ref altcp_new (and @ref altcp_new_ip_type/@ref altcp_new_ip6) take + * an @ref altcp_allocator_t as an argument, whereas the original tcp API + * functions take no arguments. + * * An @ref altcp_allocator_t allocator is an object that holds a pointer to an + * allocator object and a corresponding state (e.g. for TLS, the corresponding + * state may hold certificates or keys). This way, the application does not + * even need to know if it uses TLS or pure TCP, this is handled at runtime + * by passing a specific allocator. + * * An application can alternatively bind hard to the altcp_tls API by calling + * @ref altcp_tls_new or @ref altcp_tls_wrap. + * * The TLS layer is not directly implemented by lwIP, but a port to mbedTLS is + * provided. + * * Another altcp layer is proxy-connect to use TLS behind a HTTP proxy (see + * @ref altcp_proxyconnect.h) + * + * altcp_allocator_t + * ----------------- + * An altcp allocator is created by the application by combining an allocator + * callback function and a corresponding state, e.g.:\code{.c} + * static const unsigned char cert[] = {0x2D, ... (see mbedTLS doc for how to create this)}; + * struct altcp_tls_config * conf = altcp_tls_create_config_client(cert, sizeof(cert)); + * altcp_allocator_t tls_allocator = { + * altcp_tls_alloc, conf + * }; + * \endcode + * + * + * struct altcp_tls_config + * ----------------------- + * The struct altcp_tls_config holds state that is needed to create new TLS client + * or server connections (e.g. certificates and private keys). + * + * It is not defined by lwIP itself but by the TLS port (e.g. altcp_tls to mbedTLS + * adaption). However, the parameters used to create it are defined in @ref + * altcp_tls.h (see @ref altcp_tls_create_config_server_privkey_cert for servers + * and @ref altcp_tls_create_config_client/@ref altcp_tls_create_config_client_2wayauth + * for clients). + * + * For mbedTLS, ensure that certificates can be parsed by 'mbedtls_x509_crt_parse()' and + * private keys can be parsed by 'mbedtls_pk_parse_key()'. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ diff --git a/templates/bk7231n/.config b/templates/bk7231n/.config index c38a8736924534eb30a06687917026ce8ae9cd55..3893ce35fbb1d3e774737bb0080e4a8011c928b1 100644 --- a/templates/bk7231n/.config +++ b/templates/bk7231n/.config @@ -7,76 +7,97 @@ CONFIG_ARCH_ARM_ARM968=y # # Kernel # +# CONFIG_OS_USING_SMP is not set # CONFIG_OS_NAME_MAX_7 is not set CONFIG_OS_NAME_MAX_15=y # CONFIG_OS_NAME_MAX_31 is not set CONFIG_OS_NAME_MAX=15 -CONFIG_OS_ALIGN_SIZE=4 # CONFIG_OS_TASK_PRIORITY_8 is not set +# CONFIG_OS_TASK_PRIORITY_16 is not set CONFIG_OS_TASK_PRIORITY_32=y +# CONFIG_OS_TASK_PRIORITY_64 is not set +# CONFIG_OS_TASK_PRIORITY_128 is not set # CONFIG_OS_TASK_PRIORITY_256 is not set CONFIG_OS_TASK_PRIORITY_MAX=32 CONFIG_OS_TICK_PER_SECOND=100 +CONFIG_OS_SCHEDULE_TIME_SLICE=10 CONFIG_OS_USING_OVERFLOW_CHECK=y -CONFIG_OS_MAIN_TASK_STACK_SIZE=2048 -CONFIG_OS_USING_HOOK=y -CONFIG_OS_USING_IDLE_HOOK=y -CONFIG_OS_IDLE_HOOK_LIST_SIZE=4 +# CONFIG_OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK is not set +# CONFIG_OS_USING_TASK_HOOK is not set +CONFIG_OS_USING_ASSERT=y +CONFIG_OS_USING_KERNEL_LOCK_CHECK=y +# CONFIG_OS_USING_SAFETY_MECHANISM is not set +CONFIG_OS_USING_KERNEL_DEBUG=y +# CONFIG_KLOG_GLOBAL_LEVEL_ERROR is not set +CONFIG_KLOG_GLOBAL_LEVEL_WARNING=y +# CONFIG_KLOG_GLOBAL_LEVEL_INFO is not set +# CONFIG_KLOG_GLOBAL_LEVEL_DEBUG is not set +CONFIG_KLOG_GLOBAL_LEVEL=1 +CONFIG_KLOG_USING_COLOR=y +CONFIG_KLOG_WITH_FUNC_LINE=y +CONFIG_OS_SYS_TASK_STACK_SIZE=2048 CONFIG_OS_IDLE_TASK_STACK_SIZE=512 -CONFIG_OS_USING_TIMER_SOFT=y -CONFIG_OS_TIMER_TASK_PRIO=0 +CONFIG_OS_RECYCLE_TASK_STACK_SIZE=512 +CONFIG_OS_USING_KERNEL_TIMER=y +CONFIG_OS_USING_HASH_BUCKET_TIMER=y CONFIG_OS_TIMER_TASK_STACK_SIZE=2048 +CONFIG_OS_HASH_BUCKET_TIMER_POWER=3 +# CONFIG_OS_HASH_BUCKET_TIMER_SORT is not set +# CONFIG_OS_USING_SINGLE_LIST_TIMER is not set CONFIG_OS_USING_WORKQUEUE=y CONFIG_OS_USING_SYSTEM_WORKQUEUE=y CONFIG_OS_SYSTEM_WORKQUEUE_STACK_SIZE=2048 CONFIG_OS_SYSTEM_WORKQUEUE_PRIORITY=8 -# CONFIG_OS_USING_MODULE is not set # -# Task communication +# Inter-task communication and synchronization # -CONFIG_OS_USING_SEMAPHORE=y CONFIG_OS_USING_MUTEX=y +# CONFIG_OS_USING_SPINLOCK_CHECK is not set +CONFIG_OS_USING_SEMAPHORE=y +# CONFIG_OS_SEM_WAIT_HOOK is not set +# CONFIG_OS_SEM_POST_HOOK is not set CONFIG_OS_USING_EVENT=y -CONFIG_OS_USING_MAILBOX=y CONFIG_OS_USING_MESSAGEQUEUE=y -CONFIG_OS_USING_COMPLETION=y -CONFIG_OS_USING_DATAQUEUE=y -CONFIG_OS_USING_WAITQUEUE=y -# end of Task communication +CONFIG_OS_USING_MAILBOX=y +# end of Inter-task communication and synchronization # # Memory management # -CONFIG_OS_USING_MEM_POOL=y -# CONFIG_OS_USING_MEM_HEAP is not set -# CONFIG_OS_USING_NO_HEAP is not set -CONFIG_OS_USING_MEM_SMALL=y -# CONFIG_OS_USING_MEM_SLAB is not set +CONFIG_OS_USING_DEFAULT_HEAP=y CONFIG_OS_USING_HEAP=y -CONFIG_OS_MEM_STATS=y -# CONFIG_OS_USING_MEMTRACE is not set +CONFIG_OS_USING_ALG_FIRSTFIT=y +# CONFIG_OS_USING_ALG_BUDDY is not set +# CONFIG_OS_USING_MEM_TRACE is not set +CONFIG_OS_USING_MEM_POOL=y +# CONFIG_OS_USING_MP_CHECK_TAG is not set # end of Memory management +# CONFIG_OS_USING_IPC_TRACE is not set +# CONFIG_OS_USING_IPC_HOOK is not set + # -# Kernel console +# Debug # -CONFIG_OS_USING_CONSOLE=y -CONFIG_OS_CONSOLE_DEVICE_NAME="uart1" -# end of Kernel console +# CONFIG_STACK_TRACE_EN is not set +# CONFIG_OS_USING_CPU_MONITOR is not set # -# Enable assert +# Memory Monitor # -CONFIG_OS_USING_ASSERT=y -# end of Enable assert +# CONFIG_OS_USING_MEM_MONITOR is not set +# end of Memory Monitor +# end of Debug # end of Kernel # -# C standard library +# C standard library adapter # -CONFIG_OS_USING_LIBC=y -# end of C standard library +CONFIG_OS_USING_LIBC_ADAPTER=y +CONFIG_OS_USING_NEWLIB_ADAPTER=y +CONFIG_OS_USING_ARMCCLIB_ADAPTER=y +# end of C standard library adapter # # Osal @@ -86,48 +107,130 @@ CONFIG_OS_USING_LIBC=y # POSIX compatibility layer # # CONFIG_OS_USING_PTHREADS is not set -CONFIG_OS_USING_POSIX=y -# CONFIG_OS_USING_POSIX_MMAP is not set -# CONFIG_OS_USING_POSIX_TERMIOS is not set -# CONFIG_OS_USING_POSIX_AIO is not set # end of POSIX compatibility layer # # RT-Thread compatibility layer # -# CONFIG_OS_USING_RTTHREAD_ADAPTER is not set +# CONFIG_OS_USING_RTTHREAD_API_V3_1_3 is not set # end of RT-Thread compatibility layer # # CMSIS compatibility layer # -# CONFIG_OS_USING_CMSIS_API is not set +# CONFIG_OS_USING_CMSIS_RTOS2_API_V2_1_2 is not set # end of CMSIS compatibility layer # # FreeRTOS compatibility layer # -# CONFIG_OS_USING_FREERTOS_API_V8_2_0 is not set +# CONFIG_OS_USING_FREERTOS_API_V10_4_3 is not set # end of FreeRTOS compatibility layer + +# +# C++ Features +# +# CONFIG_OS_USING_CPLUSPLUS is not set +# end of C++ Features # end of Osal # # Drivers # CONFIG_OS_USING_DEVICE=y +CONFIG_OS_USING_DEVICE_NOTIFY=y +# CONFIG_OS_DEVICE_SUPPORT_PLUG is not set + +# +# Audio +# +# CONFIG_OS_USING_AUDIO is not set +# end of Audio + +# +# BLOCK +# +CONFIG_OS_USING_BLOCK=y +# end of BLOCK + +# +# Boot +# + +# +# CORTEX-M Boot +# +# end of CORTEX-M Boot +# end of Boot + +# +# Cache +# +CONFIG_BSP_CACHE_LINE_SIZE=32 +# end of Cache + +# +# Camera +# +# CONFIG_OS_USING_CAMERA is not set +# end of Camera + +# +# CAN +# +# CONFIG_OS_USING_CAN is not set +# end of CAN + +# +# CONSOLE +# +CONFIG_OS_USING_CONSOLE=y +CONFIG_OS_CONSOLE_DEVICE_NAME="uart1" +# end of CONSOLE + +# +# DMA +# +CONFIG_OS_USING_DMA=y +CONFIG_OS_USING_DMA_RAM=y +CONFIG_OS_USING_SOFT_DMA=y +CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# end of DMA + +# +# EEPROM +# +# CONFIG_OS_EEPROM_SUPPORT is not set +# end of EEPROM + +# +# FAL +# +# CONFIG_OS_USING_FAL is not set +# end of FAL + +# +# Graphic +# +# CONFIG_OS_USING_GRAPHIC is not set +# end of Graphic # # HAL # -CONFIG_SOC_FAMILY_BK72XX=y -CONFIG_SOC_ARM9_BK7231N=y +CONFIG_MANUFACTOR_BEKEN=y +CONFIG_SOC_ARM9E_BK7231N=y # # Hardware Drivers Config # # CONFIG_BEKEN_DRV_DEBUG is not set CONFIG_BEKEN_USING_UART1=y +CONFIG_BEKEN_UART1_BAUD=115200 CONFIG_BEKEN_USING_UART2=y +CONFIG_BEKEN_UART2_BAUD=115200 # CONFIG_BEKEN_USING_WDT is not set # CONFIG_BEKEN_USING_IIC is not set CONFIG_BEKEN_USING_FLASH=y @@ -135,23 +238,43 @@ CONFIG_BEKEN_USING_FLASH=y CONFIG_BEKEN_USING_GPIO=y CONFIG_BEKEN_USING_WLAN=y CONFIG_LWIP_NETIF_HOSTNAME=1 -CONFIG_BEKEN_USING_WLAN_STA=y -CONFIG_BEKEN_USING_WLAN_AP=y +CONFIG_BSP_USING_BK_STA=y +CONFIG_OS_WLAN_DEVICE_STA_NAME="w0" +CONFIG_BSP_USING_BK_AP=y +CONFIG_OS_WLAN_DEVICE_AP_NAME="bk" CONFIG_OS_WLAN_PROT_LWIP_PBUF_FORCE=y # CONFIG_BEKEN_USING_AUDIO is not set # CONFIG_BEKEN_USING_SPI is not set -# CONFIG_RT_USING_CPU_FFS is not set -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +# CONFIG_OS_USING_CPU_FFS is not set +CONFIG_OS_MAIN_THREAD_STACK_SIZE=2048 # CONFIG_BEKEN_USING_AUTO_POWERSAVE is not set # CONFIG_BEKEN_ATE is not set # end of Hardware Drivers Config # end of HAL # -# Audio +# HwCrypto # -# CONFIG_OS_USING_AUDIO is not set -# end of Audio +# CONFIG_OS_USING_HWCRYPTO is not set +# end of HwCrypto + +# +# I2C +# +# CONFIG_OS_USING_I2C is not set +# end of I2C + +# +# Infrared +# +# CONFIG_OS_USING_INFRARED is not set +# end of Infrared + +# +# LPMGR +# +# CONFIG_OS_USING_LPMGR is not set +# end of LPMGR # # MISC @@ -167,127 +290,142 @@ CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 # end of MISC # -# PIN +# MTD # -CONFIG_OS_USING_PIN=y -CONFIG_OS_PIN_MAX_CHIP=1 -# CONFIG_BSP_USING_PIN_PCF8574 is not set -# end of PIN +CONFIG_OS_USING_MTD=y +# end of MTD # -# Serial +# NAND # -CONFIG_OS_USING_SERIAL=y -CONFIG_OS_SERIAL_RX_BUFSZ=64 -CONFIG_OS_SERIAL_TX_BUFSZ=64 -# end of Serial +# CONFIG_OS_USING_NAND is not set +# end of NAND # -# WDG +# NET # -# CONFIG_OS_USING_WDG is not set -# end of WDG +CONFIG_OS_USING_NET_DEVICE=y +CONFIG_OS_NET_MAC_LENGTH=6 +# CONFIG_OS_NET_DRV_TO_PROTOCOL is not set + +# +# net xfer task config +# +CONFIG_OS_NET_TX_TASK_STACK_SIZE=512 +CONFIG_OS_NET_TX_TASK_PRIORITY=10 +CONFIG_OS_NET_TX_MB_MAX_NUM=4 +CONFIG_OS_NET_RX_TASK_STACK_SIZE=512 +CONFIG_OS_NET_RX_TASK_PRIORITY=9 +# end of net xfer task config + +# +# protocol support +# +CONFIG_OS_NET_PROTOCOL_LWIP=y +# end of protocol support + +CONFIG_OS_USING_WLAN=y +CONFIG_OS_WLAN_SSID_MAX_LENGTH=32 +# CONFIG_BSP_USING_AP6181 is not set +CONFIG_BSP_USING_BK7231N=y +# CONFIG_OS_USING_BK_STATION is not set +CONFIG_OS_USING_BK_AP=y +CONFIG_BSP_USING_BK_AP_SSID="bk7231n" +CONFIG_BSP_USING_BK_AP_PASSWORD="12345678" +CONFIG_BSP_USING_BK_AP_CHANNEL=1 +CONFIG_BSP_USING_BK_AP_SECURITY=1 +# end of NET + +# +# PIN +# +CONFIG_OS_USING_PIN=y +CONFIG_OS_PIN_MAX_CHIP=1 +# CONFIG_BSP_USING_PIN_PCF8574 is not set +# end of PIN # # RTC # CONFIG_OS_USING_RTC=y -CONFIG_OS_USING_SOFT_RTC=y +CONFIG_OS_RTC_DEV_NAME="rtc" # end of RTC # -# CAN +# SDIO # -# CONFIG_OS_USING_CAN is not set -# end of CAN +CONFIG_OS_USING_SDIO=y +CONFIG_OS_SDIO_STACK_SIZE=512 +CONFIG_OS_SDIO_TASK_PRIORITY=15 +CONFIG_OS_MMCSD_STACK_SIZE=1024 +CONFIG_OS_MMCSD_TASK_PREORITY=22 +CONFIG_OS_MMCSD_MAX_PARTITION=16 +# CONFIG_OS_SDIO_DEBUG is not set +# end of SDIO # -# I2C +# Sensors # -# CONFIG_OS_USING_I2C is not set -# end of I2C +# CONFIG_OS_USING_SENSOR is not set +# end of Sensors # -# SPI +# Serial # -# CONFIG_OS_USING_SPI is not set -# CONFIG_BSP_USING_ENC28J60 is not set -# CONFIG_BSP_USING_SDCARD is not set -# CONFIG_BSP_USING_NRF24L01 is not set -# end of SPI +CONFIG_OS_USING_SERIAL=y +CONFIG_OS_SERIAL_DELAY_CLOSE=y +CONFIG_OS_SERIAL_RX_BUFSZ=64 +CONFIG_OS_SERIAL_TX_BUFSZ=64 # -# FAL +# posix serial # -# CONFIG_OS_USING_FAL is not set -# end of FAL +# CONFIG_OS_USING_POSIX_SERIAL is not set +# end of posix serial # -# RTT +# rtt uart # # CONFIG_OS_USING_RTT is not set -# end of RTT +# end of rtt uart +# end of Serial # -# Timer +# SFLASH # -CONFIG_OS_USING_TIMER_DRIVER=y -CONFIG_OS_USING_CLOCKSOURCE=y -# CONFIG_OS_CLOCKSOURCE_SHOW is not set -# CONFIG_OS_USING_TIMEKEEPING is not set -# CONFIG_OS_USING_CLOCKEVENT is not set -# CONFIG_OS_USING_HRTIMER is not set -# end of Timer +# CONFIG_OS_SFLASH_SUPPORT is not set +# end of SFLASH # -# HwCrypto +# SN # -# CONFIG_OS_USING_HWCRYPTO is not set -# end of HwCrypto +# CONFIG_OS_USING_SN is not set +# end of SN # -# SDIO +# SPI # -# CONFIG_OS_USING_SDIO is not set -# end of SDIO +CONFIG_OS_USING_SPI=y +# CONFIG_OS_USING_QSPI is not set +# CONFIG_OS_USING_SPI_MSD is not set +# CONFIG_BSP_USING_ENC28J60 is not set +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_NRF24L01 is not set +# CONFIG_OS_USING_SFUD is not set +# end of SPI # -# WLAN +# Timer # -CONFIG_OS_USING_WIFI=y -CONFIG_OS_WLAN_DEVICE_STA_NAME="w0" -CONFIG_OS_WLAN_DEVICE_AP_NAME="ap" -CONFIG_OS_WLAN_SSID_MAX_LENGTH=32 -CONFIG_OS_WLAN_PASSWORD_MAX_LENGTH=32 -CONFIG_OS_WLAN_DEV_EVENT_NUM=2 -CONFIG_OS_WLAN_MANAGE_ENABLE=y -CONFIG_OS_WLAN_SCAN_WAIT_MS=10000 -CONFIG_OS_WLAN_CONNECT_WAIT_MS=10000 -CONFIG_OS_WLAN_SCAN_SORT=y -CONFIG_OS_WLAN_MSH_CMD_ENABLE=y -CONFIG_OS_WLAN_AUTO_CONNECT_ENABLE=y -CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 -CONFIG_OS_WLAN_CFG_ENABLE=y -CONFIG_OS_WLAN_CFG_INFO_MAX=3 -CONFIG_OS_WLAN_PROT_ENABLE=y -CONFIG_OS_WLAN_PROT_NAME_LEN=8 -CONFIG_OS_WLAN_PROT_MAX=2 -CONFIG_OS_WLAN_DEFAULT_PROT="lwip" -CONFIG_OS_WLAN_PROT_LWIP_ENABLE=y -CONFIG_OS_WLAN_PROT_LWIP_NAME="lwip" -CONFIG_OS_WLAN_WORK_TASK_ENABLE=y -CONFIG_OS_WLAN_WORKQUEUE_TASK_NAME="wlan" -CONFIG_OS_WLAN_WORKQUEUE_TASK_SIZE=2048 -CONFIG_OS_WLAN_WORKQUEUE_TASK_PRIO=15 -# CONFIG_OS_WLAN_DEBUG is not set -# CONFIG_BSP_USING_WIFI_AP6181 is not set -# end of WLAN +# CONFIG_OS_USING_TIMER_DRIVER is not set +CONFIG_OS_USING_TIMEKEEPING=y +# end of Timer # -# Graphic +# TinyUSB # -# CONFIG_OS_USING_GRAPHIC is not set -# end of Graphic +# CONFIG_OS_USING_TINYUSB is not set +# end of TinyUSB # # Touch @@ -295,43 +433,24 @@ CONFIG_OS_WLAN_WORKQUEUE_TASK_PRIO=15 # CONFIG_OS_USING_TOUCH is not set # end of Touch -# -# Sensors -# -# CONFIG_OS_USING_SENSOR is not set -# end of Sensors - # # USB # # CONFIG_OS_USING_USB_DEVICE is not set +# CONFIG_OS_USING_USB_HOST is not set # end of USB # -# Infrared -# -# CONFIG_OS_USING_INFRARED is not set -# end of Infrared - -# -# Low power manager -# -# CONFIG_OS_USING_LPMGR is not set -# end of Low power manager - -# -# NAND +# USB WIFI # -# CONFIG_OS_USING_NAND is not set -# end of NAND +# CONFIG_OS_USING_USB_WIFI is not set +# end of USB WIFI # -# DMA +# WDG # -CONFIG_OS_USING_DMA=y -# end of DMA - -# CONFIG_OS_USING_DRIVERS_SAMPLES is not set +# CONFIG_OS_USING_WDG is not set +# end of WDG # end of Drivers # @@ -339,343 +458,88 @@ CONFIG_OS_USING_DMA=y # # -# Atest +# DBoT # -# CONFIG_OS_USING_ATEST is not set -# end of Atest +# CONFIG_OS_USING_DBOT is not set +# end of DBoT # -# BLE +# WWD # -CONFIG_OS_USING_BLE=y -CONFIG_BLE_USING_NIMBLE=y - -# -# NimBLE -# -CONFIG_BLE_ROLE_BROADCASTER=y -CONFIG_MYNEWT_VAL_BLE_ROLE_BROADCASTER=1 -CONFIG_BLE_ROLE_PERIPHERAL=y -CONFIG_MYNEWT_VAL_BLE_ROLE_PERIPHERAL=1 -# CONFIG_BLE_ROLE_OBSERVER is not set -CONFIG_MYNEWT_VAL_BLE_ROLE_OBSERVER=0 -# CONFIG_BLE_ROLE_CENTRAL is not set -CONFIG_MYNEWT_VAL_BLE_ROLE_CENTRAL=0 -CONFIG_MYNEWT_VAL_BLE_MAX_CONNECTIONS=1 -CONFIG_MYNEWT_VAL_BLE_MAX_PERIODIC_SYNCS=1 -CONFIG_BLE_WHITELIST=y -CONFIG_MYNEWT_VAL_BLE_WHITELIST=1 -CONFIG_MYNEWT_VAL_BLE_MULTI_ADV_INSTANCES=0 -# CONFIG_BLE_EXT_ADV is not set -CONFIG_MYNEWT_VAL_BLE_EXT_ADV=0 -# CONFIG_BLE_PERIODIC_ADV is not set -CONFIG_MYNEWT_VAL_BLE_PERIODIC_ADV=0 -# CONFIG_BLE_PERIODIC_ADV_SYNC_TRANSFER is not set -CONFIG_MYNEWT_VAL_BLE_PERIODIC_ADV_SYNC_TRANSFER=0 -CONFIG_MYNEWT_VAL_BLE_EXT_ADV_MAX_SIZE=31 -CONFIG_MYNEWT_VAL_BLE_VERSION=50 -# CONFIG_BLE_ISO is not set -CONFIG_MYNEWT_VAL_BLE_ISO=0 -# CONFIG_BLE_ISO_TEST is not set -CONFIG_MYNEWT_VAL_BLE_ISO_TEST=0 -CONFIG_MYNEWT_VAL_MSYS_1_BLOCK_COUNT=16 -CONFIG_MYNEWT_VAL_MSYS_1_BLOCK_SIZE=292 -CONFIG_MYNEWT_VAL_MSYS_2_BLOCK_COUNT=0 -CONFIG_MYNEWT_VAL_MSYS_2_BLOCK_SIZE=0 - -# -# HOST -# -CONFIG_OS_USING_NIMBLE_HOST=y -CONFIG_MYNEWT_VAL_BLE_HOST=1 -CONFIG_NIMBLE_CFG_HOST=1 -CONFIG_MYNEWT_VAL_BLE_HOST_THREAD_STACK_SIZE=2048 -CONFIG_MYNEWT_VAL_BLE_HOST_THREAD_PRIORITY=3 -CONFIG_MYNEWT_VAL_BLE_HS_AUTO_START=1 -# CONFIG_BLE_HS_DEBUG is not set -CONFIG_MYNEWT_VAL_BLE_HS_DEBUG=0 -CONFIG_MYNEWT_VAL_BLE_HS_PHONY_HCI_ACKS=0 -CONFIG_MYNEWT_VAL_BLE_HS_REQUIRE_OS=1 -# CONFIG_BLE_MONITOR_UART is not set -CONFIG_MYNEWT_VAL_BLE_MONITOR_UART=0 -CONFIG_MYNEWT_VAL_BLE_MONITOR_UART_DEV="uart0" -CONFIG_MYNEWT_VAL_BLE_MONITOR_UART_BAUDRATE=1000000 -CONFIG_MYNEWT_VAL_BLE_MONITOR_UART_BUFFER_SIZE=64 -# CONFIG_BLE_MONITOR_RTT is not set -CONFIG_MYNEWT_VAL_BLE_MONITOR_RTT=0 -CONFIG_MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_NAME="btmonitor" -CONFIG_MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_SIZE=256 -CONFIG_BLE_MONITOR_RTT_BUFFERED=y -CONFIG_MYNEWT_VAL_BLE_MONITOR_RTT_BUFFERED=1 -CONFIG_MYNEWT_VAL_BLE_MONITOR_CONSOLE_BUFFER_SIZE=128 -CONFIG_MYNEWT_VAL_BLE_L2CAP_MAX_CHANS=3 -CONFIG_MYNEWT_VAL_BLE_L2CAP_SIG_MAX_PROCS=1 -CONFIG_BLE_L2CAP_JOIN_RX_FRAGS=y -CONFIG_MYNEWT_VAL_BLE_L2CAP_JOIN_RX_FRAGS=1 -CONFIG_MYNEWT_VAL_BLE_L2CAP_RX_FRAG_TIMEOUT=30000 -CONFIG_MYNEWT_VAL_BLE_L2CAP_COC_MAX_NUM=0 -CONFIG_MYNEWT_VAL_BLE_L2CAP_COC_MPS=292 -# CONFIG_BLE_L2CAP_ENHANCED_COC is not set -CONFIG_MYNEWT_VAL_BLE_L2CAP_ENHANCED_COC=0 -CONFIG_MYNEWT_VAL_BLE_SM_LEGACY=1 -CONFIG_MYNEWT_VAL_BLE_SM_SC=0 -CONFIG_MYNEWT_VAL_BLE_SM_MAX_PROCS=1 -CONFIG_MYNEWT_VAL_BLE_SM_IO_CAP=0x03 -# CONFIG_BLE_SM_OOB_DATA_FLAG is not set -CONFIG_MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG=0 -# CONFIG_BLE_SM_BONDING is not set -CONFIG_MYNEWT_VAL_BLE_SM_BONDING=0 -# CONFIG_BLE_SM_MITM is not set -CONFIG_MYNEWT_VAL_BLE_SM_MITM=0 -# CONFIG_BLE_SM_KEYPRESS is not set -CONFIG_MYNEWT_VAL_BLE_SM_KEYPRESS=0 -CONFIG_MYNEWT_VAL_BLE_SM_OUR_KEY_DIST=0 -CONFIG_MYNEWT_VAL_BLE_SM_THEIR_KEY_DIST=0 -# CONFIG_BLE_SM_SC_DEBUG_KEYS is not set -CONFIG_MYNEWT_VAL_BLE_SM_SC_DEBUG_KEYS=0 -CONFIG_MYNEWT_VAL_BLE_GAP_MAX_PENDING_CONN_PARAM_UPDATE=1 -# CONFIG_BLE_GATT_DISC_ALL_SVCS is not set -CONFIG_MYNEWT_VAL_BLE_GATT_DISC_ALL_SVCS=0 -# CONFIG_BLE_GATT_DISC_SVC_UUID is not set -CONFIG_MYNEWT_VAL_BLE_GATT_DISC_SVC_UUID=0 -# CONFIG_BLE_GATT_FIND_INC_SVCS is not set -CONFIG_MYNEWT_VAL_BLE_GATT_FIND_INC_SVCS=0 -# CONFIG_BLE_GATT_DISC_ALL_CHRS is not set -CONFIG_MYNEWT_VAL_BLE_GATT_DISC_ALL_CHRS=0 -# CONFIG_BLE_GATT_DISC_CHR_UUID is not set -CONFIG_MYNEWT_VAL_BLE_GATT_DISC_CHR_UUID=0 -# CONFIG_BLE_GATT_DISC_ALL_DSCS is not set -CONFIG_MYNEWT_VAL_BLE_GATT_DISC_ALL_DSCS=0 -# CONFIG_BLE_GATT_READ is not set -CONFIG_MYNEWT_VAL_BLE_GATT_READ=0 -# CONFIG_BLE_GATT_READ_UUID is not set -CONFIG_MYNEWT_VAL_BLE_GATT_READ_UUID=0 -# CONFIG_BLE_GATT_READ_LONG is not set -CONFIG_MYNEWT_VAL_BLE_GATT_READ_LONG=0 -# CONFIG_BLE_GATT_READ_MULT is not set -CONFIG_MYNEWT_VAL_BLE_GATT_READ_MULT=0 -# CONFIG_BLE_GATT_WRITE_NO_RSP is not set -CONFIG_MYNEWT_VAL_BLE_GATT_WRITE_NO_RSP=0 -# CONFIG_BLE_GATT_SIGNED_WRITE is not set -CONFIG_MYNEWT_VAL_BLE_GATT_SIGNED_WRITE=0 -# CONFIG_BLE_GATT_WRITE is not set -CONFIG_MYNEWT_VAL_BLE_GATT_WRITE=0 -# CONFIG_BLE_GATT_WRITE_LONG is not set -CONFIG_MYNEWT_VAL_BLE_GATT_WRITE_LONG=0 -# CONFIG_BLE_GATT_WRITE_RELIABLE is not set -CONFIG_MYNEWT_VAL_BLE_GATT_WRITE_RELIABLE=0 -CONFIG_BLE_GATT_NOTIFY=y -CONFIG_MYNEWT_VAL_BLE_GATT_NOTIFY=1 -CONFIG_BLE_GATT_INDICATE=y -CONFIG_MYNEWT_VAL_BLE_GATT_INDICATE=1 -CONFIG_MYNEWT_VAL_BLE_GATT_READ_MAX_ATTRS=8 -CONFIG_MYNEWT_VAL_BLE_GATT_WRITE_MAX_ATTRS=4 -CONFIG_MYNEWT_VAL_BLE_GATT_MAX_PROCS=4 -CONFIG_MYNEWT_VAL_BLE_GATT_RESUME_RATE=1000 -CONFIG_BLE_ATT_SVR_FIND_INFO=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_FIND_INFO=1 -CONFIG_BLE_ATT_SVR_FIND_TYPE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_FIND_TYPE=1 -CONFIG_BLE_ATT_SVR_READ_TYPE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_READ_TYPE=1 -CONFIG_BLE_ATT_SVR_READ=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_READ=1 -CONFIG_BLE_ATT_SVR_READ_BLOB=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_READ_BLOB=1 -CONFIG_BLE_ATT_SVR_READ_MULT=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_READ_MULT=1 -CONFIG_BLE_ATT_SVR_READ_GROUP_TYPE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_READ_GROUP_TYPE=1 -CONFIG_BLE_ATT_SVR_WRITE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_WRITE=1 -CONFIG_BLE_ATT_SVR_WRITE_NO_RSP=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_WRITE_NO_RSP=1 -CONFIG_BLE_ATT_SVR_SIGNED_WRITE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_SIGNED_WRITE=1 -CONFIG_BLE_ATT_SVR_QUEUED_WRITE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE=1 -CONFIG_BLE_ATT_SVR_NOTIFY=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_NOTIFY=1 -CONFIG_BLE_ATT_SVR_INDICATE=y -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_INDICATE=1 -CONFIG_MYNEWT_VAL_BLE_ATT_PREFERRED_MTU=256 -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES=64 -CONFIG_MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE_TMO=30000 -CONFIG_MYNEWT_VAL_BLE_RPA_TIMEOUT=300 -CONFIG_MYNEWT_VAL_BLE_STORE_MAX_BONDS=3 -CONFIG_MYNEWT_VAL_BLE_STORE_MAX_CCCDS=8 -# CONFIG_BLE_MESH is not set -CONFIG_MYNEWT_VAL_BLE_MESH=0 -# CONFIG_BLE_HS_FLOW_CTRL is not set -CONFIG_MYNEWT_VAL_BLE_HS_FLOW_CTRL=0 -CONFIG_MYNEWT_VAL_BLE_HS_FLOW_CTRL_ITVL=1000 -CONFIG_MYNEWT_VAL_BLE_HS_FLOW_CTRL_THRESH=2 -CONFIG_MYNEWT_VAL_BLE_HS_FLOW_CTRL_TX_ON_DISCONNECT=0 -CONFIG_MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN=1 -CONFIG_MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN_TIMEOUT=2000 -CONFIG_MYNEWT_VAL_BLE_HS_SYSINIT_STAGE=200 -CONFIG_MYNEWT_VAL_BLE_HS_LOG_MOD=4 -CONFIG_MYNEWT_VAL_BLE_HS_LOG_LVL=1 - -# -# Services -# - -# -# ans -# -CONFIG_MYNEWT_VAL_BLE_SVC_ANS_NEW_ALERT_CAT=0 -CONFIG_MYNEWT_VAL_BLE_SVC_ANS_UNR_ALERT_CAT=0 -CONFIG_MYNEWT_VAL_BLE_SVC_ANS_SYSINIT_STAGE=303 -# end of ans - -# -# bas -# -CONFIG_MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM=0 -CONFIG_MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_NOTIFY_ENABLE=1 -CONFIG_MYNEWT_VAL_BLE_SVC_BAS_SYSINIT_STAGE=303 -# end of bas - -# -# bleuart -# -CONFIG_MYNEWT_VAL_BLEUART_MAX_INPUT=120 -CONFIG_MYNEWT_VAL_BLEUART_SYSINIT_STAGE=500 -# end of bleuart - -# -# dis -# -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_DEFAULT_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_READ_PERM=0 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_DEFAULT="Apache Mynewt NimBLE" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_READ_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_DEFAULT="notset" -CONFIG_MYNEWT_VAL_BLE_SVC_DIS_SYSINIT_STAGE=303 -# end of dis +# CONFIG_OS_USING_WWD is not set +# end of WWD # -# gap +# AMS # -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME="nimble" -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_WRITE_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH=31 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE=1157 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL=0 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL=0 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_PPCP_SLAVE_LATENCY=0 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_PPCP_SUPERVISION_TMO=0 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION=-1 -CONFIG_MYNEWT_VAL_BLE_SVC_GAP_SYSINIT_STAGE=301 -# end of gap +# CONFIG_PKG_USING_AMS is not set +# end of AMS # -# gatt -# -CONFIG_MYNEWT_VAL_BLE_SVC_GATT_SYSINIT_STAGE=302 -# end of gatt - -# -# ias -# -CONFIG_MYNEWT_VAL_BLE_SVC_IAS_SYSINIT_STAGE=303 -# end of ias - -# -# ipss +# Atest # -CONFIG_MYNEWT_VAL_BLE_SVC_IPSS_SYSINIT_STAGE=303 -# end of ipss +# CONFIG_OS_USING_ATEST is not set +# end of Atest # -# lls +# BLE # -CONFIG_MYNEWT_VAL_BLE_SVC_LLS_SYSINIT_STAGE=303 -# end of lls # -# tps +# BLE is now only supported on NRF52 # -CONFIG_MYNEWT_VAL_BLE_SVC_TPS_SYSINIT_STAGE=303 -# end of tps -# end of Services +# end of BLE # -# Store +# cJSON # +CONFIG_PKG_USING_CJSON=y +# end of cJSON # -# config +# CLI # -CONFIG_MYNEWT_VAL_BLE_STORE_CONFIG_PERSIST=1 -CONFIG_MYNEWT_VAL_BLE_STORE_SYSINIT_STAGE=500 -# end of config +# CONFIG_OS_USING_CLI is not set +# end of CLI # -# ram +# Cloud # -CONFIG_MYNEWT_VAL_BLE_STORE_RAM_SYSINIT_STAGE=500 -CONFIG_MYNEWT_VAL_BLE_STORE_RAM_DEPRECATED_FLAG=0 -# end of ram -# end of Store # -# Mesh +# Aliyun # -# CONFIG_BLE_HOST_MESH is not set -# end of Mesh -# end of HOST +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# end of Aliyun # -# Controller +# AWS # -# CONFIG_OS_USING_NIMBLE_CONTROLLER is not set -# end of Controller +# CONFIG_PKG_USING_AWS_IOT is not set +# end of AWS # -# Transport +# Baidu # -CONFIG_BLE_USING_RAM=y -# CONFIG_BLE_USING_UART is not set -# CONFIG_BLE_USING_SOCKET is not set -# CONFIG_BLE_USING_USB is not set -CONFIG_MYNEWT_VAL_BLE_HCI_EVT_HI_BUF_COUNT=2 -CONFIG_MYNEWT_VAL_BLE_HCI_EVT_LO_BUF_COUNT=7 -CONFIG_MYNEWT_VAL_BLE_HCI_EVT_BUF_SIZE=70 -CONFIG_MYNEWT_VAL_BLE_ACL_BUF_COUNT=8 -CONFIG_MYNEWT_VAL_BLE_ACL_BUF_SIZE=255 -CONFIG_MYNEWT_VAL_BLE_TRANS_RAM_SYSINIT_STAGE=100 +# CONFIG_BAIDUIOT is not set +# end of Baidu # -# beken-ram +# CTWing # -# end of beken-ram -# end of Transport # -# Drivers +# MQTT # -# end of Drivers - -CONFIG_NIMBLE_CFG_TINYCRYPT=y -# end of NimBLE -# end of BLE +# CONFIG_OS_USING_CTWING_MQTT is not set +# end of MQTT +# end of CTWing # -# Cloud +# Huawei # +# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set +# end of Huawei # # OneNET @@ -699,38 +563,54 @@ CONFIG_NIMBLE_CFG_TINYCRYPT=y # CONFIG_OS_USING_ONENET_EDP is not set # end of EDP # end of OneNET +# end of Cloud # -# Huawei +# CMS # -# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set -# end of Huawei +# CONFIG_USING_CMS is not set +# end of CMS # -# AWS +# Diagnose # -# CONFIG_PKG_USING_AWS_IOT is not set -# end of AWS +# CONFIG_OS_USING_WIRESHARK_DUMP is not set # -# Aliyun +# eCoreDump # -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# end of Aliyun -# end of Cloud +# CONFIG_USING_ECORE_DUMP is not set +# end of eCoreDump +# end of Diagnose # # Dlog # CONFIG_OS_USING_DLOG=y -# CONFIG_DLOG_USING_SYSLOG is not set -# CONFIG_DLOG_OUTPUT_LVL_E is not set -# CONFIG_DLOG_OUTPUT_LVL_W is not set -# CONFIG_DLOG_OUTPUT_LVL_I is not set -CONFIG_DLOG_OUTPUT_LVL_D=y -CONFIG_DLOG_GLOBAL_LEVEL=7 +# CONFIG_DLOG_PRINT_LVL_E is not set +CONFIG_DLOG_PRINT_LVL_W=y +# CONFIG_DLOG_PRINT_LVL_I is not set +# CONFIG_DLOG_PRINT_LVL_D is not set +CONFIG_DLOG_GLOBAL_PRINT_LEVEL=4 +# CONFIG_DLOG_COMPILE_LVL_E is not set +CONFIG_DLOG_COMPILE_LVL_W=y +# CONFIG_DLOG_COMPILE_LVL_I is not set +# CONFIG_DLOG_COMPILE_LVL_D is not set +CONFIG_DLOG_COMPILE_LEVEL=4 # CONFIG_DLOG_USING_ISR_LOG is not set +CONFIG_DLOG_USING_FILTER=y # CONFIG_DLOG_USING_ASYNC_OUTPUT is not set +# CONFIG_DLOG_USING_SYSLOG is not set + +# +# Log format +# +# CONFIG_DLOG_OUTPUT_FLOAT is not set +CONFIG_DLOG_WITH_FUNC_LINE=y +CONFIG_DLOG_USING_COLOR=y +CONFIG_DLOG_OUTPUT_TIME_INFO=y +# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set +# end of Log format # # Dlog backend option @@ -738,21 +618,58 @@ CONFIG_DLOG_GLOBAL_LEVEL=7 CONFIG_DLOG_BACKEND_USING_CONSOLE=y # CONFIG_DLOG_BACKEND_USING_FILESYSTEM is not set # end of Dlog backend option +# end of Dlog -CONFIG_DLOG_USING_FILTER=y +# +# Easyflash +# +# CONFIG_PKG_USING_EASYFLASH is not set +# end of Easyflash # -# Log format +# FFmpeg # -# CONFIG_DLOG_OUTPUT_FLOAT is not set -CONFIG_DLOG_USING_COLOR=y -CONFIG_DLOG_OUTPUT_TIME_INFO=y -# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set -CONFIG_DLOG_OUTPUT_LEVEL_INFO=y -CONFIG_DLOG_OUTPUT_TAG_INFO=y -# CONFIG_DLOG_OUTPUT_TASK_NAME_INFO is not set -# end of Log format -# end of Dlog +# CONFIG_OS_USING_FFMPEG is not set +# end of FFmpeg + +# +# FileSystem +# +CONFIG_OS_USING_VFS=y +CONFIG_VFS_MOUNTPOINT_MAX=4 +CONFIG_VFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_VFS_FD_MAX=16 +# CONFIG_OS_USING_AUTO_MOUNT is not set +# CONFIG_OS_USING_VFS_DEVFS is not set +# CONFIG_OS_USING_VFS_CUTEFS is not set +# CONFIG_OS_USING_VFS_JFFS2 is not set +# CONFIG_OS_USING_VFS_YAFFS is not set +# CONFIG_OS_USING_VFS_FATFS is not set +# CONFIG_OS_USING_VFS_NFS is not set +# CONFIG_OS_USING_VFS_LFS is not set +# end of FileSystem + +# +# GUI +# +CONFIG_OS_GUI_DISP_DEV_NAME="lcd" +CONFIG_OS_GUI_INPUT_DEV_NAME="touch" +# CONFIG_OS_USING_GUI_LVGL is not set +# CONFIG_OS_USING_GUI_ARM2D is not set +# CONFIG_OS_USING_GUI_CMSIS is not set +# end of GUI + +# +# IoTjs +# +# CONFIG_USING_IOTJS is not set +# end of IoTjs + +# +# JerryScript +# +# CONFIG_USING_JERRYSCRIPT is not set +# end of JerryScript # # Network @@ -765,17 +682,22 @@ CONFIG_DLOG_OUTPUT_TAG_INFO=y # end of Acw # -# ANDLINK +# HGN +# +# CONFIG_NET_USING_HGN is not set +# end of HGN + +# +# TCP/IP # -# CONFIG_OS_USING_ANDLINK is not set -# end of ANDLINK # # LwIP # CONFIG_NET_USING_LWIP=y -CONFIG_NET_USING_LWIP202=y -# CONFIG_NET_USING_LWIP212 is not set +CONFIG_NET_USING_LWIP212=y +# CONFIG_NET_USING_LWIP_IPV6 is not set +CONFIG_LWIP_IPV6_FORWARD=1 CONFIG_LWIP_USING_IGMP=y CONFIG_LWIP_USING_ICMP=y # CONFIG_LWIP_USING_SNMP is not set @@ -784,35 +706,23 @@ CONFIG_LWIP_USING_DHCP=y CONFIG_IP_SOF_BROADCAST=1 CONFIG_IP_SOF_BROADCAST_RECV=1 # CONFIG_LWIP_USING_DHCPD is not set - -# -# Static IPv4 Address -# -CONFIG_LWIP_STATIC_IPADDR="192.168.1.30" -CONFIG_LWIP_STATIC_GWADDR="192.168.1.1" -CONFIG_LWIP_STATIC_MSKADDR="255.255.255.0" -# end of Static IPv4 Address - CONFIG_LWIP_USING_UDP=y CONFIG_LWIP_USING_TCP=y CONFIG_LWIP_USING_RAW=y # CONFIG_LWIP_USING_PPP is not set +# CONFIG_LWIP_USING_BRIDGE is not set +# CONFIG_LWIP_USING_NAT is not set CONFIG_LWIP_MEMP_NUM_NETCONN=8 CONFIG_LWIP_PBUF_NUM=8 CONFIG_LWIP_RAW_PCB_NUM=4 -CONFIG_LWIP_UDP_PCB_NUM=6 +CONFIG_LWIP_UDP_PCB_NUM=7 CONFIG_LWIP_TCP_PCB_NUM=4 CONFIG_LWIP_TCP_SEG_NUM=40 CONFIG_LWIP_TCP_SND_BUF=4096 CONFIG_LWIP_TCP_WND_SIZE=4096 CONFIG_LWIP_TCP_TASK_PRIORITY=10 CONFIG_LWIP_TCP_TASK_MBOX_SIZE=8 -CONFIG_LWIP_TCP_TASK_STACKSIZE=4096 -CONFIG_LWIP_NO_RX_TASK=y -CONFIG_LWIP_NO_TX_TASK=y -CONFIG_LWIP_ETH_TASK_PRIORITY=12 -CONFIG_LWIP_ETH_TASK_STACKSIZE=1024 -CONFIG_LWIP_ETH_TASK_MBOX_SIZE=8 +CONFIG_LWIP_TCP_TASK_STACKSIZE=1024 # CONFIG_LWIP_REASSEMBLY_FRAG is not set CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 CONFIG_LWIP_NETIF_LINK_CALLBACK=1 @@ -824,10 +734,14 @@ CONFIG_LWIP_ENABLE_NETIF_LOOPBACK=y CONFIG_LWIP_NETIF_LOOPBACK=1 # CONFIG_LWIP_USING_STATS is not set # CONFIG_LWIP_USING_HW_CHECKSUM is not set +# CONFIG_LWIP_USING_TFTP is not set CONFIG_LWIP_USING_PING=y # CONFIG_LWIP_USING_SNTP is not set +# CONFIG_LWIP_USING_IPERF_TCP_SERVER is not set +# CONFIG_LWIP_ENABLE_APP is not set # CONFIG_LWIP_ENABLE_DEBUG is not set # end of LwIP +# end of TCP/IP # # Molink @@ -836,36 +750,41 @@ CONFIG_LWIP_USING_PING=y # end of Molink # -# OTA +# Protocols # # -# Fota by CMIOT +# CoAP # -# CONFIG_FOTA_USING_CMIOT is not set -# end of Fota by CMIOT -# end of OTA +# CONFIG_COAP_Version is not set +# end of CoAP # -# Protocols +# HTTP +# + +# +# httpclient-v1.1.0 # +# CONFIG_NET_USING_HTTPCLIENT is not set +# end of httpclient-v1.1.0 +# end of HTTP # # LWM2M # -# CONFIG_NET_USING_LWM2M is not set -# end of LWM2M # -# CoAP +# LWM2M-v1.0.0 # -# CONFIG_NET_USING_COAP is not set -# end of CoAP +# CONFIG_NET_USING_LWM2M is not set +# end of LWM2M-v1.0.0 +# end of LWM2M # # MQTT # -# CONFIG_NET_USING_PAHO_MQTT is not set +# CONFIG_NET_USING_MQTT is not set # end of MQTT # @@ -873,12 +792,6 @@ CONFIG_LWIP_USING_PING=y # # CONFIG_NET_USING_WEBSOCKET_CLIENT is not set # end of Websocket - -# -# Httpclient -# -# CONFIG_NET_USING_HTTPCLIENT is not set -# end of Httpclient # end of Protocols # @@ -887,157 +800,129 @@ CONFIG_LWIP_USING_PING=y CONFIG_NET_USING_BSD=y CONFIG_BSD_USING_LWIP=y # end of Socket - -# -# Tools -# -# CONFIG_NET_USING_TOOLS is not set -# end of Tools # end of Network # -# Security +# Iotivity # -# CONFIG_SECURITY_USING_MBEDTLS is not set -# end of Security +# CONFIG_PKG_USING_IOTIVITY is not set +# end of Iotivity # -# Shell +# OneJS # -CONFIG_OS_USING_SHELL=y -CONFIG_SHELL_TASK_NAME="tshell" -CONFIG_SHELL_TASK_PRIORITY=20 -CONFIG_SHELL_TASK_STACK_SIZE=4096 -CONFIG_SHELL_USING_HISTORY=y -CONFIG_SHELL_HISTORY_LINES=5 -CONFIG_SHELL_USING_DESCRIPTION=y -# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set -CONFIG_SHELL_CMD_SIZE=80 -CONFIG_SHELL_ARG_MAX=10 -# CONFIG_SHELL_USING_AUTH is not set -# end of Shell +# CONFIG_OS_USING_ONEJS is not set +# end of OneJS # -# FileSystem +# Optparse # -CONFIG_OS_USING_VFS=y -CONFIG_VFS_USING_WORKDIR=y -CONFIG_VFS_FILESYSTEMS_MAX=2 -CONFIG_VFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_VFS_FD_MAX=16 -# CONFIG_OS_USING_VFS_JFFS2 is not set -# CONFIG_OS_USING_VFS_FATFS is not set -CONFIG_OS_USING_VFS_DEVFS=y -# CONFIG_OS_USING_VFS_CUTEFS is not set -# CONFIG_OS_USING_VFS_NFS is not set -# CONFIG_OS_USING_VFS_YAFFS is not set -# end of FileSystem - -# -# GUI -# -# CONFIG_OS_USING_GUI is not set -# end of GUI +# CONFIG_TP_USING_OPTPARSE is not set +# end of Optparse # -# OnePos +# OTA # -# CONFIG_OS_USING_OnePos is not set -# end of OnePos +# CONFIG_FOTA_USING_CMIOT is not set +# end of OTA # -# Ramdisk +# Position # -# CONFIG_OS_USING_RAMDISK is not set -# end of Ramdisk +# CONFIG_OS_USING_ONEPOS is not set +# end of Position # -# Diagnose +# PowerManager # -# CONFIG_OS_USING_CPU_USAGE is not set -# CONFIG_OS_USING_TASK_MONITOR is not set -# CONFIG_STACK_TRACE_EN is not set -# end of Diagnose +# CONFIG_OS_USING_POWER_MANAGER is not set +# end of PowerManager # -# U+ +# Python # -# CONFIG_OS_USING_Uplus is not set -# end of U+ -# end of Components +# CONFIG_OS_USING_PYTHON is not set +# end of Python # -# Thirdparty +# Ramdisk # +# CONFIG_OS_USING_RAMDISK is not set +# end of Ramdisk # -# Character Conversion +# Security # -# CONFIG_PKG_USING_CHARACTER_CONVERSION is not set -# end of Character Conversion +# CONFIG_SECURITY_USING_LIBSSH is not set +# CONFIG_SECURITY_USING_MBEDTLS is not set # -# MicroPython +# OneTLS # -# CONFIG_PKG_USING_MICROPYTHON is not set -# end of MicroPython +# CONFIG_SECURITY_USING_ONETLS is not set +# end of OneTLS +# end of Security # -# cJSON +# Shell # -CONFIG_PKG_USING_CJSON=y -# end of cJSON +CONFIG_OS_USING_SHELL=y +CONFIG_SHELL_TASK_NAME="tshell" +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_USING_HISTORY=y +CONFIG_SHELL_HISTORY_LINES=5 +CONFIG_SHELL_USING_DESCRIPTION=y +# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set +CONFIG_SHELL_CMD_SIZE=80 +CONFIG_SHELL_PROMPT_SIZE=256 +CONFIG_SHELL_ARG_MAX=10 +# CONFIG_SHELL_USING_AUTH is not set +# end of Shell # -# Easyflash +# SQL # -CONFIG_PKG_USING_EASYFLASH=y -CONFIG_PKG_EASYFLASH_ENV_SETTING_SIZE=1024 -CONFIG_PKG_EASYFLASH_ERASE_GRAN=4096 -CONFIG_PKG_EASYFLASH_START_ADDR=2088960 -# CONFIG_PKG_EASYFLASH_IAP is not set -# CONFIG_PKG_EASYFLASH_DEBUG is not set -# CONFIG_PKG_EASYFLASH_ENV_AUTO_UPDATE is not set -# CONFIG_PKG_EASYFLASH_LOG is not set -# end of Easyflash +# CONFIG_PKG_USING_SQLITE is not set +# end of SQL # -# Netutils +# telnetd # +# CONFIG_TELNET_SERVER is not set +# end of telnetd # -# NTP +# AI # -# CONFIG_PKG_USING_NTP is not set -# end of NTP -# end of Netutils +# CONFIG_OS_USING_UAI is not set +# end of AI +# end of Components # -# ttsAisound +# Demos # -# CONFIG_TTS_AISOUND_SUPPORT is not set -# end of ttsAisound # -# WebClient +# Component demos # -# CONFIG_PKG_USING_WEBCLIENT is not set -# end of WebClient -# end of Thirdparty # -# Boot Config +# Camera web server # -# CONFIG_OS_USE_BOOTLOADER is not set -# end of Boot Config +# CONFIG_OS_USING_CAMERA_WEB_SERVER is not set +# end of Camera web server +# end of Component demos +# end of Demos # # Debug # -# CONFIG_OS_DEBUG is not set +CONFIG_OS_DEBUG=y # CONFIG_LOG_BUFF_SIZE_128 is not set # CONFIG_LOG_BUFF_SIZE_192 is not set CONFIG_LOG_BUFF_SIZE_256=y # CONFIG_LOG_BUFF_SIZE_384 is not set CONFIG_OS_LOG_BUFF_SIZE=256 +# CONFIG_OS_USING_SIMPLE_EXCEPTION is not set # end of Debug diff --git a/templates/bk7231n/.config.old b/templates/bk7231n/.config.old new file mode 100644 index 0000000000000000000000000000000000000000..5da72ee88e0d8283d35f349da3a959a33598c26f --- /dev/null +++ b/templates/bk7231n/.config.old @@ -0,0 +1,928 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) +CONFIG_BOARD_BK7231N=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_ARM9=y +CONFIG_ARCH_ARM_ARM968=y + +# +# Kernel +# +# CONFIG_OS_USING_SMP is not set +# CONFIG_OS_NAME_MAX_7 is not set +CONFIG_OS_NAME_MAX_15=y +# CONFIG_OS_NAME_MAX_31 is not set +CONFIG_OS_NAME_MAX=15 +# CONFIG_OS_TASK_PRIORITY_8 is not set +# CONFIG_OS_TASK_PRIORITY_16 is not set +CONFIG_OS_TASK_PRIORITY_32=y +# CONFIG_OS_TASK_PRIORITY_64 is not set +# CONFIG_OS_TASK_PRIORITY_128 is not set +# CONFIG_OS_TASK_PRIORITY_256 is not set +CONFIG_OS_TASK_PRIORITY_MAX=32 +CONFIG_OS_TICK_PER_SECOND=100 +CONFIG_OS_SCHEDULE_TIME_SLICE=10 +CONFIG_OS_USING_OVERFLOW_CHECK=y +# CONFIG_OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK is not set +# CONFIG_OS_USING_TASK_HOOK is not set +CONFIG_OS_USING_ASSERT=y +CONFIG_OS_USING_KERNEL_LOCK_CHECK=y +# CONFIG_OS_USING_SAFETY_MECHANISM is not set +CONFIG_OS_USING_KERNEL_DEBUG=y +# CONFIG_KLOG_GLOBAL_LEVEL_ERROR is not set +CONFIG_KLOG_GLOBAL_LEVEL_WARNING=y +# CONFIG_KLOG_GLOBAL_LEVEL_INFO is not set +# CONFIG_KLOG_GLOBAL_LEVEL_DEBUG is not set +CONFIG_KLOG_GLOBAL_LEVEL=1 +CONFIG_KLOG_USING_COLOR=y +CONFIG_KLOG_WITH_FUNC_LINE=y +CONFIG_OS_SYS_TASK_STACK_SIZE=2048 +CONFIG_OS_IDLE_TASK_STACK_SIZE=512 +CONFIG_OS_RECYCLE_TASK_STACK_SIZE=512 +CONFIG_OS_USING_KERNEL_TIMER=y +CONFIG_OS_USING_HASH_BUCKET_TIMER=y +CONFIG_OS_TIMER_TASK_STACK_SIZE=2048 +CONFIG_OS_HASH_BUCKET_TIMER_POWER=3 +# CONFIG_OS_HASH_BUCKET_TIMER_SORT is not set +# CONFIG_OS_USING_SINGLE_LIST_TIMER is not set +CONFIG_OS_USING_WORKQUEUE=y +CONFIG_OS_USING_SYSTEM_WORKQUEUE=y +CONFIG_OS_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_OS_SYSTEM_WORKQUEUE_PRIORITY=8 + +# +# Inter-task communication and synchronization +# +CONFIG_OS_USING_MUTEX=y +# CONFIG_OS_USING_SPINLOCK_CHECK is not set +CONFIG_OS_USING_SEMAPHORE=y +# CONFIG_OS_SEM_WAIT_HOOK is not set +# CONFIG_OS_SEM_POST_HOOK is not set +CONFIG_OS_USING_EVENT=y +CONFIG_OS_USING_MESSAGEQUEUE=y +CONFIG_OS_USING_MAILBOX=y +# end of Inter-task communication and synchronization + +# +# Memory management +# +CONFIG_OS_USING_DEFAULT_HEAP=y +CONFIG_OS_USING_HEAP=y +CONFIG_OS_USING_ALG_FIRSTFIT=y +# CONFIG_OS_USING_ALG_BUDDY is not set +# CONFIG_OS_USING_MEM_TRACE is not set +CONFIG_OS_USING_MEM_POOL=y +# CONFIG_OS_USING_MP_CHECK_TAG is not set +# end of Memory management + +# CONFIG_OS_USING_IPC_TRACE is not set +# CONFIG_OS_USING_IPC_HOOK is not set + +# +# Debug +# +# CONFIG_STACK_TRACE_EN is not set +# CONFIG_OS_USING_CPU_MONITOR is not set + +# +# Memory Monitor +# +# CONFIG_OS_USING_MEM_MONITOR is not set +# end of Memory Monitor +# end of Debug +# end of Kernel + +# +# C standard library adapter +# +CONFIG_OS_USING_LIBC_ADAPTER=y +CONFIG_OS_USING_NEWLIB_ADAPTER=y +CONFIG_OS_USING_ARMCCLIB_ADAPTER=y +# end of C standard library adapter + +# +# Osal +# + +# +# POSIX compatibility layer +# +# CONFIG_OS_USING_PTHREADS is not set +# end of POSIX compatibility layer + +# +# RT-Thread compatibility layer +# +# CONFIG_OS_USING_RTTHREAD_API_V3_1_3 is not set +# end of RT-Thread compatibility layer + +# +# CMSIS compatibility layer +# +# CONFIG_OS_USING_CMSIS_RTOS2_API_V2_1_2 is not set +# end of CMSIS compatibility layer + +# +# FreeRTOS compatibility layer +# +# CONFIG_OS_USING_FREERTOS_API_V10_4_3 is not set +# end of FreeRTOS compatibility layer + +# +# C++ Features +# +# CONFIG_OS_USING_CPLUSPLUS is not set +# end of C++ Features +# end of Osal + +# +# Drivers +# +CONFIG_OS_USING_DEVICE=y +CONFIG_OS_USING_DEVICE_NOTIFY=y +# CONFIG_OS_DEVICE_SUPPORT_PLUG is not set + +# +# Audio +# +# CONFIG_OS_USING_AUDIO is not set +# end of Audio + +# +# BLOCK +# +CONFIG_OS_USING_BLOCK=y +# end of BLOCK + +# +# Boot +# + +# +# CORTEX-M Boot +# +# end of CORTEX-M Boot +# end of Boot + +# +# Cache +# +CONFIG_BSP_CACHE_LINE_SIZE=32 +# end of Cache + +# +# Camera +# +# CONFIG_OS_USING_CAMERA is not set +# end of Camera + +# +# CAN +# +# CONFIG_OS_USING_CAN is not set +# end of CAN + +# +# CONSOLE +# +CONFIG_OS_USING_CONSOLE=y +CONFIG_OS_CONSOLE_DEVICE_NAME="uart1" +# end of CONSOLE + +# +# DMA +# +CONFIG_OS_USING_DMA=y +CONFIG_OS_USING_DMA_RAM=y +CONFIG_OS_USING_SOFT_DMA=y +CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# end of DMA + +# +# EEPROM +# +# CONFIG_OS_EEPROM_SUPPORT is not set +# end of EEPROM + +# +# FAL +# +# CONFIG_OS_USING_FAL is not set +# end of FAL + +# +# Graphic +# +# CONFIG_OS_USING_GRAPHIC is not set +# end of Graphic + +# +# HAL +# +CONFIG_MANUFACTOR_BEKEN=y +CONFIG_SOC_ARM9E_BK7231N=y + +# +# Hardware Drivers Config +# +# CONFIG_BEKEN_DRV_DEBUG is not set +CONFIG_BEKEN_USING_UART1=y +CONFIG_BEKEN_UART1_BAUD=115200 +CONFIG_BEKEN_USING_UART2=y +CONFIG_BEKEN_UART2_BAUD=115200 +# CONFIG_BEKEN_USING_WDT is not set +# CONFIG_BEKEN_USING_IIC is not set +CONFIG_BEKEN_USING_FLASH=y +# CONFIG_BEKEN_USING_PWM is not set +CONFIG_BEKEN_USING_GPIO=y +CONFIG_BEKEN_USING_WLAN=y +CONFIG_LWIP_NETIF_HOSTNAME=1 +CONFIG_BSP_USING_BK_STA=y +CONFIG_OS_WLAN_DEVICE_STA_NAME="w0" +CONFIG_BSP_USING_BK_AP=y +CONFIG_OS_WLAN_DEVICE_AP_NAME="bk" +CONFIG_OS_WLAN_PROT_LWIP_PBUF_FORCE=y +# CONFIG_BEKEN_USING_AUDIO is not set +# CONFIG_BEKEN_USING_SPI is not set +# CONFIG_OS_USING_CPU_FFS is not set +CONFIG_OS_MAIN_THREAD_STACK_SIZE=2048 +# CONFIG_BEKEN_USING_AUTO_POWERSAVE is not set +# CONFIG_BEKEN_ATE is not set +# end of Hardware Drivers Config +# end of HAL + +# +# HwCrypto +# +# CONFIG_OS_USING_HWCRYPTO is not set +# end of HwCrypto + +# +# I2C +# +# CONFIG_OS_USING_I2C is not set +# end of I2C + +# +# Infrared +# +# CONFIG_OS_USING_INFRARED is not set +# end of Infrared + +# +# LPMGR +# +# CONFIG_OS_USING_LPMGR is not set +# end of LPMGR + +# +# MISC +# +# CONFIG_OS_USING_PUSH_BUTTON is not set +# CONFIG_OS_USING_LED is not set +# CONFIG_OS_USING_BUZZER is not set +# CONFIG_OS_USING_ADC is not set +# CONFIG_OS_USING_DAC is not set +# CONFIG_OS_USING_PWM is not set +# CONFIG_OS_USING_INPUT_CAPTURE is not set +# CONFIG_OS_USING_PULSE_ENCODER is not set +# end of MISC + +# +# MTD +# +CONFIG_OS_USING_MTD=y +# end of MTD + +# +# NAND +# +# CONFIG_OS_USING_NAND is not set +# end of NAND + +# +# NET +# +CONFIG_OS_USING_NET_DEVICE=y +CONFIG_OS_NET_MAC_LENGTH=6 +# CONFIG_OS_NET_DRV_TO_PROTOCOL is not set + +# +# net xfer task config +# +CONFIG_OS_NET_TX_TASK_STACK_SIZE=512 +CONFIG_OS_NET_TX_TASK_PRIORITY=10 +CONFIG_OS_NET_TX_MB_MAX_NUM=4 +CONFIG_OS_NET_RX_TASK_STACK_SIZE=512 +CONFIG_OS_NET_RX_TASK_PRIORITY=9 +# end of net xfer task config + +# +# protocol support +# +CONFIG_OS_NET_PROTOCOL_LWIP=y +# end of protocol support + +CONFIG_OS_USING_WLAN=y +CONFIG_OS_WLAN_SSID_MAX_LENGTH=32 +# CONFIG_BSP_USING_AP6181 is not set +CONFIG_BSP_USING_BK7231N=y +# CONFIG_OS_USING_BK_STATION is not set +CONFIG_OS_USING_BK_AP=y +CONFIG_BSP_USING_BK_AP_SSID="bk7231n" +CONFIG_BSP_USING_BK_AP_PASSWORD="12345678" +CONFIG_BSP_USING_BK_AP_CHANNEL=1 +CONFIG_BSP_USING_BK_AP_SECURITY=1 +# end of NET + +# +# PIN +# +CONFIG_OS_USING_PIN=y +CONFIG_OS_PIN_MAX_CHIP=1 +# CONFIG_BSP_USING_PIN_PCF8574 is not set +# end of PIN + +# +# RTC +# +CONFIG_OS_USING_RTC=y +CONFIG_OS_RTC_DEV_NAME="rtc" +# end of RTC + +# +# SDIO +# +CONFIG_OS_USING_SDIO=y +CONFIG_OS_SDIO_STACK_SIZE=512 +CONFIG_OS_SDIO_TASK_PRIORITY=15 +CONFIG_OS_MMCSD_STACK_SIZE=1024 +CONFIG_OS_MMCSD_TASK_PREORITY=22 +CONFIG_OS_MMCSD_MAX_PARTITION=16 +# CONFIG_OS_SDIO_DEBUG is not set +# end of SDIO + +# +# Sensors +# +# CONFIG_OS_USING_SENSOR is not set +# end of Sensors + +# +# Serial +# +CONFIG_OS_USING_SERIAL=y +CONFIG_OS_SERIAL_DELAY_CLOSE=y +CONFIG_OS_SERIAL_RX_BUFSZ=64 +CONFIG_OS_SERIAL_TX_BUFSZ=64 + +# +# posix serial +# +# CONFIG_OS_USING_POSIX_SERIAL is not set +# end of posix serial + +# +# rtt uart +# +# CONFIG_OS_USING_RTT is not set +# end of rtt uart +# end of Serial + +# +# SFLASH +# +# CONFIG_OS_SFLASH_SUPPORT is not set +# end of SFLASH + +# +# SN +# +# CONFIG_OS_USING_SN is not set +# end of SN + +# +# SPI +# +CONFIG_OS_USING_SPI=y +# CONFIG_OS_USING_QSPI is not set +# CONFIG_OS_USING_SPI_MSD is not set +# CONFIG_BSP_USING_ENC28J60 is not set +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_NRF24L01 is not set +# CONFIG_OS_USING_SFUD is not set +# end of SPI + +# +# Timer +# +# CONFIG_OS_USING_TIMER_DRIVER is not set +CONFIG_OS_USING_TIMEKEEPING=y +# end of Timer + +# +# TinyUSB +# +# CONFIG_OS_USING_TINYUSB is not set +# end of TinyUSB + +# +# Touch +# +# CONFIG_OS_USING_TOUCH is not set +# end of Touch + +# +# USB +# +# CONFIG_OS_USING_USB_DEVICE is not set +# CONFIG_OS_USING_USB_HOST is not set +# end of USB + +# +# USB WIFI +# +# CONFIG_OS_USING_USB_WIFI is not set +# end of USB WIFI + +# +# WDG +# +# CONFIG_OS_USING_WDG is not set +# end of WDG +# end of Drivers + +# +# Components +# + +# +# DBoT +# +# CONFIG_OS_USING_DBOT is not set +# end of DBoT + +# +# WWD +# +# CONFIG_OS_USING_WWD is not set +# end of WWD + +# +# AMS +# +# CONFIG_PKG_USING_AMS is not set +# end of AMS + +# +# Atest +# +# CONFIG_OS_USING_ATEST is not set +# end of Atest + +# +# BLE +# + +# +# BLE is now only supported on NRF52 +# +# end of BLE + +# +# cJSON +# +CONFIG_PKG_USING_CJSON=y +# end of cJSON + +# +# CLI +# +# CONFIG_OS_USING_CLI is not set +# end of CLI + +# +# Cloud +# + +# +# Aliyun +# +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# end of Aliyun + +# +# AWS +# +# CONFIG_PKG_USING_AWS_IOT is not set +# end of AWS + +# +# Baidu +# +# CONFIG_BAIDUIOT is not set +# end of Baidu + +# +# CTWing +# + +# +# MQTT +# +# CONFIG_OS_USING_CTWING_MQTT is not set +# end of MQTT +# end of CTWing + +# +# Huawei +# +# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set +# end of Huawei + +# +# OneNET +# + +# +# MQTT kit +# +# CONFIG_OS_USING_ONENET_MQTTS is not set +# end of MQTT kit + +# +# NB-IoT kit +# +# CONFIG_OS_USING_ONENET_NBIOT is not set +# end of NB-IoT kit + +# +# EDP +# +# CONFIG_OS_USING_ONENET_EDP is not set +# end of EDP +# end of OneNET +# end of Cloud + +# +# CMS +# +# CONFIG_USING_CMS is not set +# end of CMS + +# +# Diagnose +# +# CONFIG_OS_USING_WIRESHARK_DUMP is not set + +# +# eCoreDump +# +# CONFIG_USING_ECORE_DUMP is not set +# end of eCoreDump +# end of Diagnose + +# +# Dlog +# +CONFIG_OS_USING_DLOG=y +# CONFIG_DLOG_PRINT_LVL_E is not set +# CONFIG_DLOG_PRINT_LVL_W is not set +# CONFIG_DLOG_PRINT_LVL_I is not set +CONFIG_DLOG_PRINT_LVL_D=y +CONFIG_DLOG_GLOBAL_PRINT_LEVEL=7 +# CONFIG_DLOG_COMPILE_LVL_E is not set +CONFIG_DLOG_COMPILE_LVL_W=y +# CONFIG_DLOG_COMPILE_LVL_I is not set +# CONFIG_DLOG_COMPILE_LVL_D is not set +CONFIG_DLOG_COMPILE_LEVEL=4 +# CONFIG_DLOG_USING_ISR_LOG is not set +CONFIG_DLOG_USING_FILTER=y +# CONFIG_DLOG_USING_ASYNC_OUTPUT is not set +# CONFIG_DLOG_USING_SYSLOG is not set + +# +# Log format +# +# CONFIG_DLOG_OUTPUT_FLOAT is not set +CONFIG_DLOG_WITH_FUNC_LINE=y +CONFIG_DLOG_USING_COLOR=y +CONFIG_DLOG_OUTPUT_TIME_INFO=y +# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set +# end of Log format + +# +# Dlog backend option +# +CONFIG_DLOG_BACKEND_USING_CONSOLE=y +# CONFIG_DLOG_BACKEND_USING_FILESYSTEM is not set +# end of Dlog backend option +# end of Dlog + +# +# Easyflash +# +# CONFIG_PKG_USING_EASYFLASH is not set +# end of Easyflash + +# +# FFmpeg +# +# CONFIG_OS_USING_FFMPEG is not set +# end of FFmpeg + +# +# FileSystem +# +CONFIG_OS_USING_VFS=y +CONFIG_VFS_MOUNTPOINT_MAX=4 +CONFIG_VFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_VFS_FD_MAX=16 +# CONFIG_OS_USING_AUTO_MOUNT is not set +# CONFIG_OS_USING_VFS_DEVFS is not set +# CONFIG_OS_USING_VFS_CUTEFS is not set +# CONFIG_OS_USING_VFS_JFFS2 is not set +# CONFIG_OS_USING_VFS_YAFFS is not set +# CONFIG_OS_USING_VFS_FATFS is not set +# CONFIG_OS_USING_VFS_NFS is not set +# CONFIG_OS_USING_VFS_LFS is not set +# end of FileSystem + +# +# GUI +# +CONFIG_OS_GUI_DISP_DEV_NAME="lcd" +CONFIG_OS_GUI_INPUT_DEV_NAME="touch" +# CONFIG_OS_USING_GUI_LVGL is not set +# CONFIG_OS_USING_GUI_ARM2D is not set +# CONFIG_OS_USING_GUI_CMSIS is not set +# end of GUI + +# +# IoTjs +# +# CONFIG_USING_IOTJS is not set +# end of IoTjs + +# +# JerryScript +# +# CONFIG_USING_JERRYSCRIPT is not set +# end of JerryScript + +# +# Network +# + +# +# Acw +# +# CONFIG_NET_USING_ACW is not set +# end of Acw + +# +# HGN +# +# CONFIG_NET_USING_HGN is not set +# end of HGN + +# +# TCP/IP +# + +# +# LwIP +# +CONFIG_NET_USING_LWIP=y +CONFIG_NET_USING_LWIP212=y +# CONFIG_NET_USING_LWIP_IPV6 is not set +CONFIG_LWIP_IPV6_FORWARD=1 +CONFIG_LWIP_USING_IGMP=y +CONFIG_LWIP_USING_ICMP=y +# CONFIG_LWIP_USING_SNMP is not set +CONFIG_LWIP_USING_DNS=y +CONFIG_LWIP_USING_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_LWIP_USING_UDP=y +CONFIG_LWIP_USING_TCP=y +CONFIG_LWIP_USING_RAW=y +# CONFIG_LWIP_USING_PPP is not set +# CONFIG_LWIP_USING_BRIDGE is not set +# CONFIG_LWIP_USING_NAT is not set +CONFIG_LWIP_MEMP_NUM_NETCONN=8 +CONFIG_LWIP_PBUF_NUM=8 +CONFIG_LWIP_RAW_PCB_NUM=4 +CONFIG_LWIP_UDP_PCB_NUM=7 +CONFIG_LWIP_TCP_PCB_NUM=4 +CONFIG_LWIP_TCP_SEG_NUM=40 +CONFIG_LWIP_TCP_SND_BUF=4096 +CONFIG_LWIP_TCP_WND_SIZE=4096 +CONFIG_LWIP_TCP_TASK_PRIORITY=10 +CONFIG_LWIP_TCP_TASK_MBOX_SIZE=8 +CONFIG_LWIP_TCP_TASK_STACKSIZE=1024 +# CONFIG_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_ENABLE_NETIF_LOOPBACK=y +CONFIG_LWIP_NETIF_LOOPBACK=1 +# CONFIG_LWIP_USING_STATS is not set +# CONFIG_LWIP_USING_HW_CHECKSUM is not set +# CONFIG_LWIP_USING_TFTP is not set +CONFIG_LWIP_USING_PING=y +# CONFIG_LWIP_USING_SNTP is not set +# CONFIG_LWIP_USING_IPERF_TCP_SERVER is not set +# CONFIG_LWIP_ENABLE_APP is not set +# CONFIG_LWIP_ENABLE_DEBUG is not set +# end of LwIP +# end of TCP/IP + +# +# Molink +# +# CONFIG_NET_USING_MOLINK is not set +# end of Molink + +# +# Protocols +# + +# +# CoAP +# +# CONFIG_COAP_Version is not set +# end of CoAP + +# +# HTTP +# + +# +# httpclient-v1.1.0 +# +# CONFIG_NET_USING_HTTPCLIENT is not set +# end of httpclient-v1.1.0 +# end of HTTP + +# +# LWM2M +# + +# +# LWM2M-v1.0.0 +# +# CONFIG_NET_USING_LWM2M is not set +# end of LWM2M-v1.0.0 +# end of LWM2M + +# +# MQTT +# +# CONFIG_NET_USING_MQTT is not set +# end of MQTT + +# +# Websocket +# +# CONFIG_NET_USING_WEBSOCKET_CLIENT is not set +# end of Websocket +# end of Protocols + +# +# Socket +# +CONFIG_NET_USING_BSD=y +CONFIG_BSD_USING_LWIP=y +# end of Socket +# end of Network + +# +# Iotivity +# +# CONFIG_PKG_USING_IOTIVITY is not set +# end of Iotivity + +# +# OneJS +# +# CONFIG_OS_USING_ONEJS is not set +# end of OneJS + +# +# Optparse +# +# CONFIG_TP_USING_OPTPARSE is not set +# end of Optparse + +# +# OTA +# +# CONFIG_FOTA_USING_CMIOT is not set +# end of OTA + +# +# Position +# +# CONFIG_OS_USING_ONEPOS is not set +# end of Position + +# +# PowerManager +# +# CONFIG_OS_USING_POWER_MANAGER is not set +# end of PowerManager + +# +# Python +# +# CONFIG_OS_USING_PYTHON is not set +# end of Python + +# +# Ramdisk +# +# CONFIG_OS_USING_RAMDISK is not set +# end of Ramdisk + +# +# Security +# +# CONFIG_SECURITY_USING_LIBSSH is not set +# CONFIG_SECURITY_USING_MBEDTLS is not set + +# +# OneTLS +# +# CONFIG_SECURITY_USING_ONETLS is not set +# end of OneTLS +# end of Security + +# +# Shell +# +CONFIG_OS_USING_SHELL=y +CONFIG_SHELL_TASK_NAME="tshell" +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_USING_HISTORY=y +CONFIG_SHELL_HISTORY_LINES=5 +CONFIG_SHELL_USING_DESCRIPTION=y +# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set +CONFIG_SHELL_CMD_SIZE=80 +CONFIG_SHELL_PROMPT_SIZE=256 +CONFIG_SHELL_ARG_MAX=10 +# CONFIG_SHELL_USING_AUTH is not set +# end of Shell + +# +# SQL +# +# CONFIG_PKG_USING_SQLITE is not set +# end of SQL + +# +# telnetd +# +# CONFIG_TELNET_SERVER is not set +# end of telnetd + +# +# AI +# +# CONFIG_OS_USING_UAI is not set +# end of AI +# end of Components + +# +# Demos +# + +# +# Component demos +# + +# +# Camera web server +# +# CONFIG_OS_USING_CAMERA_WEB_SERVER is not set +# end of Camera web server +# end of Component demos +# end of Demos + +# +# Debug +# +CONFIG_OS_DEBUG=y +# CONFIG_LOG_BUFF_SIZE_128 is not set +# CONFIG_LOG_BUFF_SIZE_192 is not set +CONFIG_LOG_BUFF_SIZE_256=y +# CONFIG_LOG_BUFF_SIZE_384 is not set +CONFIG_OS_LOG_BUFF_SIZE=256 +# CONFIG_OS_USING_SIMPLE_EXCEPTION is not set +# end of Debug diff --git a/templates/bk7231n/.oneos b/templates/bk7231n/.oneos new file mode 100644 index 0000000000000000000000000000000000000000..5ddb3619297c87eefd5545ece3f6a0c4cb6d0930 --- /dev/null +++ b/templates/bk7231n/.oneos @@ -0,0 +1,5 @@ +ONEOS_VERSION: OneOS-V2.3.1 +MANUFACTOR: BEKEN +SERIES: BK72 +MODEL: BK7231 +TEMP: bk7231n diff --git a/templates/bk7231n/.sconsign.dblite b/templates/bk7231n/.sconsign.dblite index c029c2e840b79d2360fbb8cf77662219ded0ad75..c77cbe8e916b89defa9a73dee0c1f319c32fd38b 100644 Binary files a/templates/bk7231n/.sconsign.dblite and b/templates/bk7231n/.sconsign.dblite differ diff --git a/templates/bk7231n/Kconfig b/templates/bk7231n/Kconfig index 0e0694ba842b49c6701db167b509e35b13410bc4..d9c525677173a473db74d5957da7962cdf1c9a3b 100644 --- a/templates/bk7231n/Kconfig +++ b/templates/bk7231n/Kconfig @@ -6,7 +6,7 @@ SRC_HAL=beken config BOARD_BK7231N bool - select SOC_ARM9_BK7231N + select SOC_ARM9E_BK7231N default y source "$OS_ROOT/Kconfig" diff --git a/templates/bk7231n/application/application_ble_demo/SConscript b/templates/bk7231n/application/application_ble_demo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e1bb57a2f5c682c4385c3c7ea945f31c1ff6a3b5 --- /dev/null +++ b/templates/bk7231n/application/application_ble_demo/SConscript @@ -0,0 +1,13 @@ +from build_tools import * +Import('OS_ROOT') +Import('osconfig') + +pwd = PresentDir() +path = [pwd] + +src = Glob('*.c') +group = [] + +if IsDefined(['OS_USING_BLE']): + group = AddCodeGroup('application', src, depend=[''], CPPPATH=path) +Return('group') diff --git a/templates/bk7231n/application/application_ble_demo/nimble_app_cfg.h b/templates/bk7231n/application/application_ble_demo/app_cfg.h similarity index 97% rename from templates/bk7231n/application/application_ble_demo/nimble_app_cfg.h rename to templates/bk7231n/application/application_ble_demo/app_cfg.h index 99f294bdf8a5d7b16d35cf5548ce26c54cced53d..e1e5bde062437482693c2547f45c639bf386e644 100644 --- a/templates/bk7231n/application/application_ble_demo/nimble_app_cfg.h +++ b/templates/bk7231n/application/application_ble_demo/app_cfg.h @@ -20,8 +20,8 @@ * 2020-09-16 OneOS Team First Version *********************************************************************************************************************** */ -#ifndef _NIMBLE_APP_CFG_H_ -#define _NIMBLE_APP_CFG_H_ +#ifndef _APP_CFG_H_ +#define _APP_CFG_H_ #include diff --git a/templates/bk7231n/application/application_ble_demo/serial_print.c b/templates/bk7231n/application/application_ble_demo/serial_print.c index 4a2b923352a55559a477fb204a5941a332fe9467..82c6c364ab2e8b06018e56a5535b0a5459a7cb88 100644 --- a/templates/bk7231n/application/application_ble_demo/serial_print.c +++ b/templates/bk7231n/application/application_ble_demo/serial_print.c @@ -74,7 +74,7 @@ void hci_pkt_write(char type, char *pkt, int len) { struct hci_pkt *hci_pkt_w = &hci_pkt_buf[hci_pkt_num_w]; - uint32_t tick = os_tick_get_value(); + os_uint32_t tick = os_tick_get(); hci_pkt_w->type = type; hci_pkt_w->len = (len > PKT_MAX_LEN) ? PKT_MAX_LEN : len; diff --git a/templates/bk7231n/application/application_demo.c b/templates/bk7231n/application/application_demo.c index d02edfebcdacb131c5f69fdfd64af46a1608e8dd..c57f8922124e77dcb9259704e35c6391420bb246 100644 --- a/templates/bk7231n/application/application_demo.c +++ b/templates/bk7231n/application/application_demo.c @@ -17,7 +17,6 @@ #include "rtos_pub.h" #include "drv_flash.h" #include "wlan_dev.h" -#include "wlan_mgnt.h" #include "error.h" #include #include "os_mq.h" @@ -33,21 +32,20 @@ #include #include +#include +#include +#include -#include +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "beken_wifi" +#include #define CONFIG_INFO_ADDR (0x1FE000) #define LISTEN_SERVER_PORT (28000) - -extern void beken_hw_cpu_reset(void); -extern os_tick_t os_tick_from_ms(uint32_t ms); -extern os_err_t os_task_delay(os_tick_t tick); -extern int wifi_set_mac_address(char *mac); - - +#define MSG_SIZE 24 struct config_info_manager { - os_wlan_mode_t mode; + os_net_mode_t mode; char ssid[32]; char password[32]; }; @@ -56,460 +54,33 @@ struct config_info_manager { static struct config_info_manager g_cfg_info; static beken_thread_t thread_recv_deal; static beken_thread_t thread_server; -static os_msgqueue_id cfg_mq; -static os_msgqueue_dummy_t cfg_mq_dummy; - static int g_msg[32]; static char result[64]; -/* receive data deal task */ -void data_deal_task(beken_thread_arg_t arg) -{ - OSStatus err = kNoErr; - int fd = -1; - int len = 0; - os_size_t recv_size = 0; - - char *buf = NULL; - char *ptr = NULL; - int count = 0; - bool finish = false; - - buf = (char*) os_malloc(1024); - ASSERT(buf); - - while (1) - { - /* get msg from mq */ - if (os_msgqueue_recv(cfg_mq, &fd, sizeof(int), OS_IPC_WAITING_FOREVER, &recv_size) == OS_SUCCESS) - { - os_kprintf("recv msg from message queue, the content:%d\n",fd); - } - - finish = false; - while(!finish) - { - len = lwip_recv(fd, buf, 1024, 0); - - os_kprintf("recv buf= %s, len: %d\n",buf,len); - - if (len <= 0) - { - os_kprintf( "TCP Client is disconnected, fd: %d\n", fd ); - goto exit; - } - - ptr = strtok(buf,"|"); // eg: "sta|beken|12345678|end"; - - if(0 == strcmp(ptr,"sta")) { - finish = true; - g_cfg_info.mode = OS_WLAN_STATION; - } - else if(0 == strcmp(ptr,"ap")){ - finish = true; - g_cfg_info.mode = OS_WLAN_AP; - } - else { - memset(buf,0,1024); - strcpy(result,"parse failed,info err!\n"); - len = lwip_send(fd, result,sizeof(result), 0); - continue; - } - } - - count = 0; - while (ptr) - { /* parse info */ - count++; - ptr = strtok(NULL,"|"); - - if(ptr) { - - switch(count) { - case 1: - memset(g_cfg_info.ssid,'\0',32); - strcpy(g_cfg_info.ssid,ptr); - os_kprintf("ssid:%s\n",g_cfg_info.ssid); - break; - - case 2: - memset(g_cfg_info.password,'\0',32); - strcpy(g_cfg_info.password,ptr); - os_kprintf("password:%s\n",g_cfg_info.password); - break; - - default: - break; - } - } - } - - beken_flash_write(CONFIG_INFO_ADDR,&g_cfg_info,sizeof(struct config_info_manager)); - os_task_delay(os_tick_from_ms(200)); - - strcpy(result,"parse success,get info! reboot later!\n"); - len = lwip_send(fd, result,sizeof(result), 0); - - os_kprintf("parse success,get info! send len=%d, reboot later!\n",len); - os_task_delay(os_tick_from_ms(5000)); - beken_hw_cpu_reset(); - } - -exit: - if (err != kNoErr) - os_kprintf("TCP client thread exit with err: %d\n", err); - - if (buf != NULL) - os_free(buf); - - lwip_close(fd); - rtos_delete_thread(&thread_recv_deal); -} - - -/* tcp server listener task */ -void tcp_server_task( void) -{ - OSStatus err = kNoErr; - struct sockaddr_in server_addr, client_addr; - socklen_t sockaddr_t_size = sizeof(client_addr); - char client_ip_str[16]; - int tcp_listen_fd = -1, client_fd = -1; - fd_set readfds; - - tcp_listen_fd = lwip_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); - - server_addr.sin_family = AF_INET; - server_addr.sin_addr.s_addr = INADDR_ANY;/* Accept conenction request on all network interface */ - server_addr.sin_port = htons(LISTEN_SERVER_PORT);/* Server listen on port: 28000 */ - err = lwip_bind(tcp_listen_fd, (struct sockaddr *) &server_addr, sizeof(server_addr)); - - err = lwip_listen(tcp_listen_fd, 0); - - while (1) - { - FD_ZERO(&readfds); - FD_SET(tcp_listen_fd, &readfds); - - lwip_select( tcp_listen_fd + 1, &readfds, NULL, NULL, NULL); - - if (FD_ISSET(tcp_listen_fd, &readfds)) - { - client_fd = lwip_accept(tcp_listen_fd, (struct sockaddr *) &client_addr, &sockaddr_t_size); - if (client_fd >= 0) - { - os_strcpy(client_ip_str, inet_ntoa(client_addr.sin_addr)); - - /*send msg to mq*/ - if (OS_SUCCESS != os_msgqueue_send(cfg_mq, &client_fd, sizeof(int), OS_IPC_WAITING_NO)) - { - os_kprintf("send message failed!\n"); - lwip_close(client_fd); - client_fd = -1; - } - - os_kprintf("TCP Client %s:%d connected, fd: %d\n", client_ip_str, client_addr.sin_port, client_fd); - } - } - } - - if (err != kNoErr) - os_kprintf("Server listerner thread exit with err: %d \n", err); - - lwip_close(tcp_listen_fd); - rtos_delete_thread(&thread_server); -} +#define wlan_name "wlan0" -void demo_app_test(void) +#ifdef BSP_USING_BK_AP +void demo_ap(void) { - OSStatus err = kNoErr; + struct os_wlan_device *wlan_dev = OS_NULL; - /* init a message queue */ - cfg_mq = os_msgqueue_create_static(&cfg_mq_dummy, "mqt", &g_msg[0], sizeof(g_msg), sizeof(int)); - - - err = rtos_create_thread(&thread_server, BEKEN_APPLICATION_PRIORITY, - "server_demo", - (beken_thread_function_t)tcp_server_task, - 0x800, - (beken_thread_arg_t)0 ); - if(err != kNoErr) - { - os_kprintf("create \"server_demo\" thread failed!\r\n"); - } - - - err = rtos_create_thread(&thread_recv_deal, BEKEN_APPLICATION_PRIORITY, - "recv_deal_demo", - (beken_thread_function_t)data_deal_task, - 0x800, - (beken_thread_arg_t)0 ); - if(err != kNoErr) + wlan_dev = (struct os_wlan_device *)os_device_find(OS_WLAN_DEVICE_AP_NAME); + if (wlan_dev == OS_NULL) { - os_kprintf("create \"recv_deal_demo\" thread failed!\r\n"); - } - -} -SH_CMD_EXPORT(demo_app_test,demo_app_test,"start tcp server demo test."); - - -void demo_flash_read_test(void) -{ - struct config_info_manager info; - - beken_flash_read(CONFIG_INFO_ADDR,&info,sizeof(struct config_info_manager)); - os_kprintf("mode=%d, ssid=%s,password=%s \n",info.mode,info.ssid,info.password); + LOG_E(DRV_EXT_TAG, "wifi_dev cannot find!"); + return OS_SUCCESS; + } + + wlan_dev->info.ssid = "bsp-bk"; + wlan_dev->info.password = "12345678"; + wlan_dev->info.security = OS_WLAN_SECURITY_WPA2_AES_PSK; + wlan_dev->info.country = OS_WLAN_COUNTRY_CHINA; + wlan_dev->info.channel = 1; + + os_kprintf("demo_ap_start_test\r\n"); + os_wlan_start(wlan_dev); } -SH_CMD_EXPORT(demo_flash_read_test,demo_flash_read_test,"beken flash read test."); - - -void demo_flash_write_test(void) -{ - struct config_info_manager info; - char ptr1[]="beken"; - char ptr2[]="12345678"; - - info.mode = OS_WLAN_STATION; - strcpy(info.ssid,ptr1); - strcpy(info.password,ptr2); - - beken_flash_write(CONFIG_INFO_ADDR,&info,sizeof(struct config_info_manager)); - os_kprintf("mode=%d, ssid=%s, password=%s \n",info.mode,info.ssid,info.password); -} -SH_CMD_EXPORT(demo_flash_write_test,demo_flash_write_test,"beken flash write test."); - - -void demo_station_connect_test(void) -{ - struct config_info_manager info; - - beken_flash_read(CONFIG_INFO_ADDR,&info,sizeof(struct config_info_manager)); - - os_wlan_connect(info.ssid,info.password); -} -SH_CMD_EXPORT(demo_station_connect_test,demo_station_connect_test,"station connect wifi of information in flash test."); - -void demo_ap_start_test(void) -{ - os_wlan_staos_ap("bk","12345678"); -} -SH_CMD_EXPORT(demo_ap_start_test,demo_ap_start_test,"ap startup of ssid:beken pass:12345678 test."); - -/* easyflash test demo */ -void easyflash_test(void) -{ - uint32_t i_boot_times = 0;//NULL; - char *c_old_boot_times, c_new_boot_times[11] = {0}; - - /* init */ - easyflash_init(); - - /* get the boot count number from Env */ - c_old_boot_times = ef_get_env("boot_times"); - OS_ASSERT(c_old_boot_times); - i_boot_times = atol(c_old_boot_times); - - /* boot count +1 */ - i_boot_times ++; - os_kprintf("The system now boot %d times\n\r", i_boot_times); - - /* interger to string */ - sprintf(c_new_boot_times,"%ld", i_boot_times); - - /* set and store the boot count number to Env */ - ef_set_env("boot_times", c_new_boot_times); - ef_save_env(); -} -SH_CMD_EXPORT(easyflash_test,easyflash_test,"easyflash test."); - -void demo_set_mac(void) -{ - char test_mac[]={0x28, 0xC2, 0xDD, 0x61, 0x68, 0x62}; - wifi_set_mac_address(test_mac); -} -SH_CMD_EXPORT(demo_set_mac,demo_set_mac,"test_set_mac."); - -#define SW_P20 20 -#define SW_P21 21 -static void demo_set_pin(void) -{ - static unsigned int status = 1; - - os_pin_mode(SW_P20, PIN_MODE_OUTPUT); - os_pin_write(SW_P20, status); - - os_pin_mode(SW_P21, PIN_MODE_OUTPUT); - os_pin_write(SW_P21, status); - - status = 0x01&(~status); -} -SH_CMD_EXPORT(demo_set_pin,demo_set_pin,"demo set gpio pin."); - -#ifdef OS_USING_RTC -static void demo_get_time(void) -{ - time_t t; - int ti = 0; - - ti = (int)time(&t); - - os_kprintf("time:%d\n",ti); -} -SH_CMD_EXPORT(demo_get_time,demo_get_time,"demo get time."); +SH_CMD_EXPORT(demo_ap,demo_ap,"ap startup of ssid:beken pass:12345678 test."); #endif - -//udp test -#define BUFSZ 1024 -//#define SERVER_HOSTNAME "192.168.10.255" -#define SERVER_HOSTNAME "255.255.255.255" - -#define SERVER_TCP_PORT "6588" -#define SERVER_UDP_PORT "6589" -static const char send_data[] = "This is LwIP Client from OneOS."; - - -static void test_udpsocket_send(void) -{ - int ret; - int bytes_received; - int sock = -1; - struct hostent* host = OS_NULL; - uint32_t port; - struct sockaddr_in server_addr; - char * recv_data = OS_NULL; - - /* 分配用于存放接收数据的缓冲 */ - recv_data = malloc(BUFSZ); - if (recv_data == OS_NULL) - { - os_kprintf("No memory"); - return; - } - - /* 创建一个socket，SOCK_DGRAM，udp类型 */ - if ((sock = lwip_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) == -1) - { - /* 创建socket失败 */ - os_kprintf("Create socket error"); - return; - } - - const int on = 1; - - lwip_setsockopt(sock, SOL_SOCKET, SO_BROADCAST, &on, sizeof(on)); //设置套接字选项 - - /* 初始化预连接的服务端地址 */ - host = lwip_gethostbyname(SERVER_HOSTNAME); - port = strtol(SERVER_UDP_PORT, 0, 10); - - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(port); - //server_addr.sin_addr = *((struct in_addr*)host->h_addr); - server_addr.sin_addr.s_addr = INADDR_BROADCAST; - memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - - /*UDP socket send and recv data*/ - os_kprintf("UDP socket [%d] send data to server\n", sock); - ret = lwip_sendto(sock, send_data, strlen(send_data), 0, (struct sockaddr*)&server_addr, sizeof(struct sockaddr)); - - os_kprintf("send ret:%d\n",ret); - - os_task_mdelay(300); - - os_free(recv_data); - lwip_close(sock); -} -SH_CMD_EXPORT(test_udpsocket_send,test_udpsocket_send,"udp socket send data."); - -static void test_udpsocket_recv(void *parameter) -{ - int ret; - int bytes_received; - int sock = -1; - struct hostent* host = OS_NULL; - uint32_t port; - struct sockaddr_in server_addr; - char * recv_data = OS_NULL; - - /* 分配用于存放接收数据的缓冲 */ - recv_data = malloc(BUFSZ); - if (recv_data == OS_NULL) - { - os_kprintf("No memory"); - return; - } - - /* 创建一个socket，SOCK_DGRAM，udp类型 */ - if ((sock = lwip_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) == -1) - { - /* 创建socket失败 */ - os_kprintf("Create socket error"); - return; - } - - const int on = 1; - lwip_setsockopt(sock, SOL_SOCKET, SO_BROADCAST, &on, sizeof(on)); - - /* init */ - host = lwip_gethostbyname(SERVER_HOSTNAME); - port = strtol(SERVER_UDP_PORT, 0, 10); - - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(port); - //server_addr.sin_addr = *((struct in_addr*)host->h_addr); - server_addr.sin_addr.s_addr = INADDR_ANY; - memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - - - /* bind socket to the server address */ - if (lwip_bind(sock, (struct sockaddr *)&server_addr, - sizeof(struct sockaddr)) == -1) - { - /* bind failed. */ - os_kprintf("bind server address failed, errno=%d\n", errno); - lwip_close(sock); - free(recv_data); - return; - } - - struct sockaddr_in recv_addr; - socklen_t len = sizeof(struct sockaddr); - static const char back_data[] = "get data."; - - while(1) - { - bytes_received = lwip_recvfrom(sock, recv_data, BUFSZ, 0,(struct sockaddr*)&recv_addr,&len); - os_kprintf("bytes_received:%d,lwip_recv:%s\n",bytes_received,recv_data); - - ret = lwip_sendto(sock, back_data, strlen(back_data), 0, (struct sockaddr*)&recv_addr, sizeof(struct sockaddr)); - os_kprintf("test_udpsocket_recv send ret:%d sin_family=%d,sin_port=%d,sin_addr.s_addr=%d \n", - ret,recv_addr.sin_family,recv_addr.sin_port,recv_addr.sin_addr.s_addr); - } - - os_free(recv_data); - lwip_close(sock); -} - -void udp_recv_task(void) -{ - os_task_id task; - - task = os_task_create(OS_NULL, OS_NULL, 4096, "udp server", test_udpsocket_recv, OS_NULL, 3); - OS_ASSERT(task); - os_task_startup(task); -} -SH_CMD_EXPORT(udp_recv_task,udp_recv_task,"udp task recv data."); - -void get_rssi(void) -{ - extern int os_wlan_get_rssi(void); - int level = 0; - - level = os_wlan_get_rssi(); - - os_kprintf(" get rssi:%d \n",level); -} -SH_CMD_EXPORT(get_rssi,get_rssi,"get rssi."); - diff --git a/templates/bk7231n/application/ble_cmd.c b/templates/bk7231n/application/ble_cmd.c deleted file mode 100644 index ee6ec4c758c9841095cf25bf943769c6611be56c..0000000000000000000000000000000000000000 --- a/templates/bk7231n/application/ble_cmd.c +++ /dev/null @@ -1,560 +0,0 @@ -//#include -#include "shell.h" -#include "common.h" -#include "param_config.h" - -#if defined(CFG_SUPPORT_BLE) && defined(BEKEN_ATE) - -#include "ble_api.h" -#if (CFG_BLE_VERSION == BLE_VERSION_5_x) -#include "app_ble.h" -#endif -#include "ble_pub.h" - -#if (CFG_BLE_VERSION == BLE_VERSION_4_2) -#define BUILD_UINT16(loByte, hiByte) \ - ((uint16_t)(((loByte) & 0x00FF) + (((hiByte) & 0x00FF) << 8))) - -#define BK_ATT_DECL_PRIMARY_SERVICE 0x2800 -#define BK_ATT_DECL_CHARACTERISTIC 0x2803 -#define BK_ATT_DESC_CLIENT_CHAR_CFG 0x2902 -#define TEST_SERVICE_UUID 0xFFFF -#define WRITE_REQ_CHARACTERISTIC 0xFF01 -#define INDICATE_CHARACTERISTIC 0xFF02 - -static const uint8_t test_svc_uuid[16] = {0xFF,0xFF,0,0,0x34,0x56,0,0,0,0,0x28,0x37,0,0,0,0}; - -enum -{ - TEST_IDX_SVC, - TEST_IDX_FF01_VAL_CHAR, - TEST_IDX_FF01_VAL_VALUE, - TEST_IDX_FF02_VAL_CHAR, - TEST_IDX_FF02_VAL_VALUE, - TEST_IDX_FF02_VAL_IND_CFG, - TEST_IDX_NB, -}; - -bk_attm_desc_t test_att_db[6] = -{ - // Service Declaration - [TEST_IDX_SVC] = {BK_ATT_DECL_PRIMARY_SERVICE, BK_PERM_SET(RD, ENABLE), 0, 0}, - - // Level Characteristic Declaration - [TEST_IDX_FF01_VAL_CHAR] = {BK_ATT_DECL_CHARACTERISTIC, BK_PERM_SET(RD, ENABLE), 0, 0}, - // Level Characteristic Value - [TEST_IDX_FF01_VAL_VALUE] = {WRITE_REQ_CHARACTERISTIC, BK_PERM_SET(WRITE_REQ, ENABLE), BK_PERM_SET(RI, ENABLE) , 128}, - - [TEST_IDX_FF02_VAL_CHAR] = {BK_ATT_DECL_CHARACTERISTIC, BK_PERM_SET(RD, ENABLE), 0, 0}, - // Level Characteristic Value - [TEST_IDX_FF02_VAL_VALUE] = {INDICATE_CHARACTERISTIC, BK_PERM_SET(IND, ENABLE) , BK_PERM_SET(RI, ENABLE) , 128}, - - // Level Characteristic - Client Characteristic Configuration Descriptor - - [TEST_IDX_FF02_VAL_IND_CFG] = {BK_ATT_DESC_CLIENT_CHAR_CFG, BK_PERM_SET(RD, ENABLE)|BK_PERM_SET(WRITE_REQ, ENABLE), 0, 0}, -}; - -ble_err_t bk_ble_init(void) -{ - ble_err_t status; - struct bk_ble_db_cfg ble_db_cfg; - - ble_db_cfg.att_db = test_att_db; - ble_db_cfg.att_db_nb = TEST_IDX_NB; - ble_db_cfg.prf_task_id = 0; - ble_db_cfg.start_hdl = 0; - ble_db_cfg.svc_perm = 0; - memcpy(&(ble_db_cfg.uuid[0]), &test_svc_uuid[0], 16); - - status = bk_ble_create_db(&ble_db_cfg); - - return status; -} - -void appm_adv_data_decode(uint8_t len, const uint8_t *data) -{ - uint8_t index; - uint8_t i; - for(index = 0; index < len;) - { - switch(data[index + 1]) - { - case 0x01: - { - bk_printf("AD_TYPE : "); - for(i = 0; i < data[index] - 1; i++) - { - bk_printf("%02x ",data[index + 2 + i]); - } - bk_printf("\r\n"); - index +=(data[index] + 1); - } - break; - case 0x08: - case 0x09: - { - bk_printf("ADV_NAME : "); - for(i = 0; i < data[index] - 1; i++) - { - bk_printf("%c",data[index + 2 + i]); - } - bk_printf("\r\n"); - index +=(data[index] + 1); - } - break; - case 0x02: - { - bk_printf("UUID : "); - for(i = 0; i < data[index] - 1;) - { - bk_printf("%02x%02x ",data[index + 2 + i],data[index + 3 + i]); - i+=2; - } - bk_printf("\r\n"); - index +=(data[index] + 1); - } - break; - default: - { - index +=(data[index] + 1); - } - break; - } - } - return ; -} - -void ble_write_callback(write_req_t *write_req) -{ - bk_printf("write_cb[prf_id:%d, att_idx:%d, len:%d]\r\n", write_req->prf_id, write_req->att_idx, write_req->len); -} - -uint8_t ble_read_callback(read_req_t *read_req) -{ - bk_printf("read_cb[prf_id:%d, att_idx:%d]\r\n", read_req->prf_id, read_req->att_idx); - read_req->value[0] = 0x10; - read_req->value[1] = 0x20; - read_req->value[2] = 0x30; - return 3; -} - -void ble_event_callback(ble_event_t event, void *param) -{ - switch(event) - { - case BLE_STACK_OK: - { - bk_printf("STACK INIT OK\r\n"); - bk_ble_init(); - } - break; - case BLE_STACK_FAIL: - { - bk_printf("STACK INIT FAIL\r\n"); - } - break; - case BLE_CONNECT: - { - bk_printf("BLE CONNECT\r\n"); - } - break; - case BLE_DISCONNECT: - { - bk_printf("BLE DISCONNECT\r\n"); - } - break; - case BLE_MTU_CHANGE: - { - bk_printf("BLE_MTU_CHANGE:%d\r\n", *(uint16_t *)param); - } - break; - case BLE_TX_DONE: - { - bk_printf("BLE_TX_DONE\r\n"); - } - break; - case BLE_GEN_DH_KEY: - { - bk_printf("BLE_GEN_DH_KEY\r\n"); - } - break; - case BLE_GET_KEY: - { - bk_printf("BLE_GET_KEY\r\n"); - } - break; - case BLE_CREATE_DB_OK: - { - bk_printf("CREATE DB SUCCESS\r\n"); - } - break; - default: - bk_printf("UNKNOW EVENT\r\n"); - break; - } -} - -static void ble_command_usage(void) -{ - bk_printf("ble help - Help information\n"); - bk_printf("ble active - Active ble to with BK7231BTxxx\n"); - bk_printf("ble start_adv - Start advertising as a slave device\n"); - bk_printf("ble stop_adv - Stop advertising as a slave device\n"); - bk_printf("ble notify prf_id att_id value\n"); - bk_printf(" - Send ntf value to master\n"); - bk_printf("ble indicate prf_id att_id value\n"); - bk_printf(" - Send ind value to master\n"); - - bk_printf("ble disc - Disconnect\n"); - bk_printf("ble dut - dut test\n"); -} - -static void ble_get_info_handler(void) -{ - UINT8 *ble_mac; - bk_printf("\r\n****** ble information ************\r\n"); - - if (ble_is_start() == 0) { - bk_printf("no ble startup \r\n"); - return; - } - ble_mac = ble_get_mac_addr(); - bk_printf("* name: %s \r\n", ble_get_name()); - bk_printf("* mac:%02x-%02x-%02x-%02x-%02x-%02x\r\n", ble_mac[0], ble_mac[1],ble_mac[2],ble_mac[3],ble_mac[4],ble_mac[5]); - bk_printf("*********** end *****************\r\n"); -} - -typedef adv_info_t ble_adv_param_t; - -static void ble_advertise(void) -{ - UINT8 mac[6]; - char ble_name[20]; - UINT8 adv_idx, adv_name_len; - - wifi_get_mac_address((char *)mac, CONFIG_ROLE_STA); - adv_name_len = snprintf(ble_name, sizeof(ble_name), "bk72xx-%02x%02x", mac[4], mac[5]); - - memset(&adv_info, 0x00, sizeof(adv_info)); - - adv_info.channel_map = 7; - adv_info.interval_min = 160; - adv_info.interval_max = 160; - - adv_idx = 0; - adv_info.advData[adv_idx] = 0x02; adv_idx++; - adv_info.advData[adv_idx] = 0x01; adv_idx++; - adv_info.advData[adv_idx] = 0x06; adv_idx++; - - adv_info.advData[adv_idx] = adv_name_len + 1; adv_idx +=1; - adv_info.advData[adv_idx] = 0x09; adv_idx +=1; //name - memcpy(&adv_info.advData[adv_idx], ble_name, adv_name_len); adv_idx +=adv_name_len; - - adv_info.advDataLen = adv_idx; - - adv_idx = 0; - - adv_info.respData[adv_idx] = adv_name_len + 1; adv_idx +=1; - adv_info.respData[adv_idx] = 0x08; adv_idx +=1; //name - memcpy(&adv_info.respData[adv_idx], ble_name, adv_name_len); adv_idx +=adv_name_len; - adv_info.respDataLen = adv_idx; - - if (ERR_SUCCESS != appm_start_advertising()) - { - bk_printf("ERROR\r\n"); - } -} - -static void ble(int argc, char **argv) -{ - ble_adv_param_t adv_param; - - if ((argc < 2) || (os_strcmp(argv[1], "help") == 0)) - { - ble_command_usage(); - return ; - } - - if (os_strcmp(argv[1], "active") == 0) - { - ble_set_write_cb(ble_write_callback); - ble_set_read_cb(ble_read_callback); - ble_set_event_cb(ble_event_callback); - ble_activate(NULL); - } - else if(os_strcmp(argv[1], "start_adv") == 0) - { - ble_advertise(); - } - else if(os_strcmp(argv[1], "stop_adv") == 0) - { - if(ERR_SUCCESS != appm_stop_advertising()) - { - bk_printf("ERROR\r\n"); - } - } - else if(os_strcmp(argv[1], "notify") == 0) - { - uint8 len; - uint16 prf_id; - uint16 att_id; - uint8 write_buffer[20]; - - if(argc != 5) - { - ble_command_usage(); - return ; - } - - len = os_strlen(argv[4]); - if(len % 2 != 0) - { - bk_printf("ERROR\r\n"); - return ; - } - hexstr2bin(argv[4], write_buffer, len/2); - - prf_id = atoi(argv[2]); - att_id = atoi(argv[3]); - - if(ERR_SUCCESS != bk_ble_send_ntf_value(len, write_buffer, prf_id, att_id)) - { - bk_printf("ERROR\r\n"); - } - } - else if(os_strcmp(argv[1], "indicate") == 0) - { - uint8 len; - uint16 prf_id; - uint16 att_id; - uint8 write_buffer[20]; - - if(argc != 5) - { - ble_command_usage(); - return ; - } - - len = os_strlen(argv[4]); - if(len % 2 != 0) - { - bk_printf("ERROR\r\n"); - return ; - } - hexstr2bin(argv[4], write_buffer, len/2); - - prf_id = atoi(argv[2]); - att_id = atoi(argv[3]); - - if(ERR_SUCCESS != bk_ble_send_ind_value(len / 2, write_buffer, prf_id, att_id)) - { - bk_printf("ERROR\r\n"); - } - } - else if(os_strcmp(argv[1], "disc") == 0) - { - appm_disconnect(); - } - else if(os_strcmp(argv[1], "dut") == 0) - { - ble_dut_start(); - } -} - -MSH_CMD_EXPORT(ble, ble command); -#endif - -#if (CFG_BLE_VERSION == BLE_VERSION_5_x) -extern struct app_env_tag app_ble_ctx; - -#define BUILD_UINT16(loByte, hiByte) \ - ((uint16_t)(((loByte) & 0x00FF) + (((hiByte) & 0x00FF) << 8))) - -#define BK_ATT_DECL_PRIMARY_SERVICE_128 {0x00,0x28,0,0,0,0,0,0,0,0,0,0,0,0,0,0} -#define BK_ATT_DECL_CHARACTERISTIC_128 {0x03,0x28,0,0,0,0,0,0,0,0,0,0,0,0,0,0} -#define BK_ATT_DESC_CLIENT_CHAR_CFG_128 {0x02,0x29,0,0,0,0,0,0,0,0,0,0,0,0,0,0} - -#define WRITE_REQ_CHARACTERISTIC_128 {0x01,0xFF,0,0,0x34,0x56,0,0,0,0,0x28,0x37,0,0,0,0} -#define INDICATE_CHARACTERISTIC_128 {0x02,0xFF,0,0,0x34,0x56,0,0,0,0,0x28,0x37,0,0,0,0} -#define NOTIFY_CHARACTERISTIC_128 {0x03,0xFF,0,0,0x34,0x56,0,0,0,0,0x28,0x37,0,0,0,0} - -static const uint8_t test_svc_uuid[16] = {0xFF,0xFF,0,0,0x34,0x56,0,0,0,0,0x28,0x37,0,0,0,0}; - -enum -{ - TEST_IDX_SVC, - TEST_IDX_FF01_VAL_CHAR, - TEST_IDX_FF01_VAL_VALUE, - TEST_IDX_FF02_VAL_CHAR, - TEST_IDX_FF02_VAL_VALUE, - TEST_IDX_FF02_VAL_IND_CFG, - TEST_IDX_FF03_VAL_CHAR, - TEST_IDX_FF03_VAL_VALUE, - TEST_IDX_FF03_VAL_NTF_CFG, - TEST_IDX_NB, -}; - -bk_attm_desc_t test_att_db[TEST_IDX_NB] = -{ - // Service Declaration - [TEST_IDX_SVC] = {BK_ATT_DECL_PRIMARY_SERVICE_128, BK_PERM_SET(RD, ENABLE), 0, 0}, - - // Level Characteristic Declaration - [TEST_IDX_FF01_VAL_CHAR] = {BK_ATT_DECL_CHARACTERISTIC_128, BK_PERM_SET(RD, ENABLE), 0, 0}, - // Level Characteristic Value - [TEST_IDX_FF01_VAL_VALUE] = {WRITE_REQ_CHARACTERISTIC_128, BK_PERM_SET(WRITE_REQ, ENABLE), BK_PERM_SET(RI, ENABLE)|BK_PERM_SET(UUID_LEN, UUID_16), 128}, - - [TEST_IDX_FF02_VAL_CHAR] = {BK_ATT_DECL_CHARACTERISTIC_128, BK_PERM_SET(RD, ENABLE), 0, 0}, - // Level Characteristic Value - [TEST_IDX_FF02_VAL_VALUE] = {INDICATE_CHARACTERISTIC_128, BK_PERM_SET(IND, ENABLE), BK_PERM_SET(RI, ENABLE)|BK_PERM_SET(UUID_LEN, UUID_16), 128}, - - // Level Characteristic - Client Characteristic Configuration Descriptor - - [TEST_IDX_FF02_VAL_IND_CFG] = {BK_ATT_DESC_CLIENT_CHAR_CFG_128, BK_PERM_SET(RD, ENABLE)|BK_PERM_SET(WRITE_REQ, ENABLE), 0, 0}, - - [TEST_IDX_FF03_VAL_CHAR] = {BK_ATT_DECL_CHARACTERISTIC_128, BK_PERM_SET(RD, ENABLE), 0, 0}, - // Level Characteristic Value - [TEST_IDX_FF03_VAL_VALUE] = {NOTIFY_CHARACTERISTIC_128, BK_PERM_SET(NTF, ENABLE), BK_PERM_SET(RI, ENABLE)|BK_PERM_SET(UUID_LEN, UUID_16), 128}, - - // Level Characteristic - Client Characteristic Configuration Descriptor - - [TEST_IDX_FF03_VAL_NTF_CFG] = {BK_ATT_DESC_CLIENT_CHAR_CFG_128, BK_PERM_SET(RD, ENABLE)|BK_PERM_SET(WRITE_REQ, ENABLE), 0, 0}, -}; -ble_err_t bk_ble_init(void) -{ - ble_err_t status; - struct bk_ble_db_cfg ble_db_cfg; - - ble_db_cfg.att_db = test_att_db; - ble_db_cfg.att_db_nb = TEST_IDX_NB; - ble_db_cfg.prf_task_id = 0; - ble_db_cfg.start_hdl = 0; - ble_db_cfg.svc_perm = 0; - memcpy(&(ble_db_cfg.uuid[0]), &test_svc_uuid[0], 16); - - status = bk_ble_create_db(&ble_db_cfg); - - return status; -} - -void ble_write_callback(write_req_t *write_req) -{ - bk_printf("write_cb[prf_id:%d, att_idx:%d, len:%d]\r\n", write_req->prf_id, write_req->att_idx, write_req->len); -} - -uint8_t ble_read_callback(read_req_t *read_req) -{ - bk_printf("read_cb[prf_id:%d, att_idx:%d]\r\n", read_req->prf_id, read_req->att_idx); - read_req->value[0] = 0x10; - read_req->value[1] = 0x20; - read_req->value[2] = 0x30; - return 3; -} - -void ble_event_callback(ble_event_t event, void *param) -{ - switch(event) - { - case BLE_STACK_OK: - { - bk_printf("STACK INIT OK\r\n"); - } - break; - case BLE_STACK_FAIL: - { - bk_printf("STACK INIT FAIL\r\n"); - } - break; - case BLE_CONNECT: - { - bk_printf("BLE CONNECT\r\n"); - } - break; - case BLE_DISCONNECT: - { - bk_printf("BLE DISCONNECT\r\n"); - } - break; - case BLE_MTU_CHANGE: - { - bk_printf("BLE_MTU_CHANGE:%d\r\n", *(uint16_t *)param); - } - break; - case BLE_TX_DONE: - { - bk_printf("BLE_TX_DONE\r\n"); - } - break; - case BLE_GEN_DH_KEY: - { - bk_printf("BLE_GEN_DH_KEY\r\n"); - } - break; - case BLE_GET_KEY: - { - bk_printf("BLE_GET_KEY\r\n"); - } - break; - case BLE_CREATE_DB_OK: - { - bk_printf("CREATE DB SUCCESS\r\n"); - } - break; - default: - bk_printf("UNKNOW EVENT\r\n"); - break; - } -} - -static void ble(int argc, char **argv) -{ - uint8_t adv_data[31]; - uint32_t data_len; -// if (os_strcmp(argv[1], "active") == 0) -// { -// ble_set_write_cb(ble_write_callback); -// ble_set_read_cb(ble_read_callback); -// ble_set_event_cb(ble_event_callback); -// bk_ble_init(); -// } -// else if (os_strcmp(argv[1], "adv_create") == 0) -// { -// ble_appm_create_advertising(0x7, 160, 160); -// } -// else if (os_strcmp(argv[1], "set_adv_data") == 0) -// { -// adv_data[0] = 0x02; -// adv_data[1] = 0x01; -// adv_data[2] = 0x06; - -// adv_data[3] = 0x0B; -// adv_data[4] = 0x09; -// memcpy(&adv_data[5], "7231N_BLE", 10); -// ble_appm_set_adv_data(app_ble_ctx.adv_actv_idx, adv_data, 0xF); -// } -// else if (os_strcmp(argv[1], "set_rsp_data") == 0) -// { -// adv_data[0] = 0x07; -// adv_data[1] = 0x08; -// memcpy(&adv_data[2], "7231N", 6); -// ble_appm_set_scan_rsp_data(app_ble_ctx.adv_actv_idx, adv_data, 0x8); -// } -// else if (os_strcmp(argv[1], "adv_start") == 0) -// { -// ble_appm_start_advertising(app_ble_ctx.adv_actv_idx, 0); -// } -// else - if (os_strcmp(argv[1], "dut") == 0) - { - ble_dut_start(); - } - else - { - bk_printf("only support [ble dut] cmd\r\n"); - } -} - -SH_CMD_EXPORT(ble, ble, "ble command"); - -#endif -#endif diff --git a/templates/bk7231n/application/ble_cmd.h b/templates/bk7231n/application/ble_cmd.h deleted file mode 100644 index 4ab16885f48f280876c9ab638b5d6e76394ecc3c..0000000000000000000000000000000000000000 --- a/templates/bk7231n/application/ble_cmd.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _BLE_CMD_H_ -#define _BLE_CMD_H_ - - -#endif/*_BLE_CMD_H_*/ diff --git a/templates/bk7231n/application/main.c b/templates/bk7231n/application/main.c index f4f127b614f1e1b2d4467347a4f1e47aaf6742dc..35eab1f613a9d7b5e2f78658c82104a44ce455f5 100644 --- a/templates/bk7231n/application/main.c +++ b/templates/bk7231n/application/main.c @@ -34,7 +34,14 @@ #include "acw.h" #endif -static void user_task(void *parameter) +#include "typedef.h" + + +#include "icu.h" +#include "icu_pub.h" +#include "arm_arch.h" + +static void user_task1(void *parameter) { while (1) { @@ -42,10 +49,20 @@ static void user_task(void *parameter) print_hci_pkt(); print_str_buf(); #endif - os_task_mdelay(100); + + os_task_msleep(5000); + } +} + +static void user_task2(void *parameter) +{ + while (1) + { + os_task_msleep(5000); } } + int main(void) { os_task_id task; @@ -57,15 +74,20 @@ int main(void) extern void ate_app_init(void); ate_app_init(); #endif - os_kprintf("date:%s\ttime:%s\n", date, time); + #ifdef NET_USING_ACW acw_main_proc(acw_intf_soc_wifi_bk7231n); #endif #ifdef NET_USING_ACW_OLD acw_main_proc(); #endif - task = os_task_create(OS_NULL, OS_NULL, 256, "user", user_task, OS_NULL, 3); + + task = os_task_create(OS_NULL, OS_NULL, 1024,"user1", user_task1, OS_NULL, 10); + OS_ASSERT(task); + os_task_startup(task); + + task = os_task_create(OS_NULL, OS_NULL, 512,"user2", user_task2, OS_NULL, 10); OS_ASSERT(task); os_task_startup(task); diff --git a/templates/bk7231n/application/msh_evm.c b/templates/bk7231n/application/msh_evm.c deleted file mode 100644 index 201d87013dcbef587fd2516e7f82d4971480e47c..0000000000000000000000000000000000000000 --- a/templates/bk7231n/application/msh_evm.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * File : msh_evm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2018-06-06 RT-Thread the first version - */ - -#include -#include "shell.h" -#include "cmd_evm.h" -#include "cmd_rx_sensitivity.h" - -#ifdef BEKEN_ATE - -int txevm(int argc, char **argv) -{ - int ret = do_evm(NULL, 0, argc, argv); - if(ret) - { - os_kprintf("tx_evm bad parameters\r\n"); - } -} -SH_CMD_EXPORT(do_tx_evm, txevm, "do_tx_evm"); - -int rxsens(int argc, char **argv) -{ - int ret = do_rx_sensitivity(NULL, 0, argc, argv); - if(ret) - { - os_kprintf("rx sensitivity bad parameters\r\n"); - } -} -SH_CMD_EXPORT(do_rx_sens, rxsens, "do_rx_sens"); - -#include "param_config.h" -#include "common.h" -int mac(int argc, char **argv) -{ - uint8_t mac[6]; - - if (argc == 1) - { - wifi_get_mac_address((char *)mac, CONFIG_ROLE_STA); - os_kprintf("MAC address: %02x-%02x-%02x-%02x-%02x-%02x\r\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } - else if(argc == 2) - { - hexstr2bin(argv[1], mac, 6); - wifi_set_mac_address((char *)mac); - os_kprintf("Set MAC address: %02x-%02x-%02x-%02x-%02x-%02x\r\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } - else - { - os_kprintf("invalid cmd\r\n"); - } - -} -SH_CMD_EXPORT(set_or_read_mac, mac, "set_or_read_mac"); - -#endif /* BEKEN_ATE */ - diff --git a/templates/bk7231n/application/weave.yaml b/templates/bk7231n/application/weave.yaml index 07016d9cdef6f2e81515bc965ed37235756615dc..86d9c6a9a0c3192966b1d80946bbc5b41fdf707a 100644 --- a/templates/bk7231n/application/weave.yaml +++ b/templates/bk7231n/application/weave.yaml @@ -1,11 +1,6 @@ # 组名 group_name: application -# 编译连接信息 -build_option: - cpppath: - - . - # 源码 source_file: - - ./*.c \ No newline at end of file + - ./*.c diff --git a/templates/bk7231n/application/wlan_test.c b/templates/bk7231n/application/wlan_test.c new file mode 100644 index 0000000000000000000000000000000000000000..1fc1e2500d0a8c94e33504fa0e6d755f7af3a5f9 --- /dev/null +++ b/templates/bk7231n/application/wlan_test.c @@ -0,0 +1,196 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file wlan_test.c + * + * @brief The test file for wlan. + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include +#include +#include +#include + +#define DRV_EXT_LVL DBG_EXT_INFO +#define DRV_EXT_TAG "wlan_test" +#include + +#ifdef OS_USING_BK_AP + #define wlan_name OS_WLAN_DEVICE_AP_NAME +#else + #define wlan_name OS_WLAN_DEVICE_STA_NAME +#endif + + +static int wifi_scan(int argc, char **argv) +{ + int index; + char *security; + struct os_wlan_device *wlan_dev = OS_NULL; + struct os_wlan_scan_result *scan_result = OS_NULL; + + wlan_dev = (struct os_wlan_device *)os_device_find(wlan_name); + if (wlan_dev == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "os_device_find failed!"); + return OS_FAILURE; + } + + scan_result = os_wlan_scan(wlan_dev, 2000, 30); + if (scan_result == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "os_wlan_scan failed!"); + return OS_FAILURE; + } + + os_kprintf("has find %d wifi sorce\r\n", scan_result->count); + os_kprintf(" SSID MAC security rssi chn Mbps\r\n"); + os_kprintf("------------------------------- ----------------- -------------- ---- --- ----\r\n"); + for (index = 0; index < scan_result->count; index++) + { + os_kprintf("%-32.32s", &scan_result->scan_info[index].ssid.val[0]); + os_kprintf("%02x:%02x:%02x:%02x:%02x:%02x ", + scan_result->scan_info[index].bssid[0], + scan_result->scan_info[index].bssid[1], + scan_result->scan_info[index].bssid[2], + scan_result->scan_info[index].bssid[3], + scan_result->scan_info[index].bssid[4], + scan_result->scan_info[index].bssid[5]); + switch (scan_result->scan_info[index].security) + { + case OS_WLAN_SECURITY_OPEN: + security = "OPEN"; + break; + case OS_WLAN_SECURITY_WEP_PSK: + security = "WEP_PSK"; + break; + case OS_WLAN_SECURITY_WEP_SHARED: + security = "WEP_SHARED"; + break; + case OS_WLAN_SECURITY_WPA_TKIP_PSK: + security = "WPA_TKIP_PSK"; + break; + case OS_WLAN_SECURITY_WPA_AES_PSK: + security = "WPA_AES_PSK"; + break; + case OS_WLAN_SECURITY_WPA2_AES_PSK: + security = "WPA2_AES_PSK"; + break; + case OS_WLAN_SECURITY_WPA2_TKIP_PSK: + security = "WPA2_TKIP_PSK"; + break; + case OS_WLAN_SECURITY_WPA2_MIXED_PSK: + security = "WPA2_MIXED_PSK"; + break; + case OS_WLAN_SECURITY_WPS_OPEN: + security = "WPS_OPEN"; + break; + case OS_WLAN_SECURITY_WPS_SECURE: + security = "WPS_SECURE"; + break; + default: + security = "UNKNOWN"; + break; + } + os_kprintf("%-14.14s ", security); + os_kprintf("%-4d ", scan_result->scan_info[index].signal_strength); + os_kprintf("%3d ", scan_result->scan_info[index].channel); + os_kprintf("%4d\r\n", scan_result->scan_info[index].max_data_rate / 1000); + } + + os_wlan_scan_clean_result(wlan_dev); + + return 0; +} +SH_CMD_EXPORT(wifi_scan, wifi_scan, "wifi_scan"); + +static os_wlan_security_t security_map_from_str(char *str) +{ + os_wlan_security_t security; + + if (strcmp("OPEN", str) == 0) + security = OS_WLAN_SECURITY_OPEN; + else if (strcmp("WPA_AES_PSK", str) == 0) + security = OS_WLAN_SECURITY_WPA_AES_PSK; + else if (strcmp("WPA2_AES_PSK", str) == 0) + security = OS_WLAN_SECURITY_WPA2_AES_PSK; + else if (strcmp("WPA2_MIXED_PSK", str) == 0) + security = OS_WLAN_SECURITY_WPA2_MIXED_PSK; + else + security = OS_WLAN_SECURITY_WPA2_AES_PSK; + + return security; +} + +static int wifi_join(int argc, char **argv) +{ + os_wlan_security_t security; + const char *ssid = OS_NULL; + const char *key = OS_NULL; + struct os_wlan_device *wlan_dev = OS_NULL; + + if (argc != 4) + { + os_kprintf("usage: wifi_join ssid key security\r\n"); + os_kprintf(" wifi_join mywifi 12345678 WPA2_AES_PSK\r\n"); + os_kprintf(" wifi_join mywifi null OPEN\r\n"); + return -1; + } + + /* ssid */ + ssid = argv[1]; + + /* Password */ + key = argv[2]; + + /* security */ + security = security_map_from_str(argv[3]); + + wlan_dev = (struct os_wlan_device *)os_device_find(wlan_name); + if (wlan_dev == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "os_device_find failed!"); + } + + if (os_wlan_join(wlan_dev, ssid, key, security) != OS_SUCCESS) + LOG_E(DRV_EXT_TAG, "os_wlan_join failed! %s %s", ssid, key); + else + LOG_I(DRV_EXT_TAG, "os_wlan_join success! %s %s", ssid, key); + + return 0; +} +SH_CMD_EXPORT(wifi_join, wifi_join, "wifi_join"); + +static int wifi_leave(int argc, char *argv[]) +{ + struct os_wlan_device *wlan_dev = OS_NULL; + + wlan_dev = (struct os_wlan_device *)os_device_find(wlan_name); + if (wlan_dev == OS_NULL) + { + LOG_E(DRV_EXT_TAG, "os_device_find failed!"); + } + + if (os_wlan_leave(wlan_dev) != OS_SUCCESS) + LOG_E(DRV_EXT_TAG, "os_wlan_leave failed!"); + else + LOG_I(DRV_EXT_TAG, "os_wlan_leave success!"); + return 0; +} +SH_CMD_EXPORT(wifi_leave, wifi_leave, "wifi_leave"); diff --git a/templates/bk7231n/beken_packager/all_1.00.bin b/templates/bk7231n/beken_packager/all_1.00.bin new file mode 100644 index 0000000000000000000000000000000000000000..83e04dbf4ccaa53f7f9ced52e9bed41113ca5e87 Binary files /dev/null and b/templates/bk7231n/beken_packager/all_1.00.bin differ diff --git a/drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/config.h "b/templates/bk7231n/beken_packager/bootloader\350\256\276\345\244\2071_dump.bin" similarity index 100% rename from drivers/hal/beken/beken72XX_HAL/func/lwip_intf/lwip-2.0.2/test/fuzz/config.h rename to "templates/bk7231n/beken_packager/bootloader\350\256\276\345\244\2071_dump.bin" diff --git a/templates/bk7231n/beken_packager/config.json b/templates/bk7231n/beken_packager/config.json index 80f584ff95f17d3f58152b27acbc88b18ae9b494..b9450dee87cb0cb1d45715648260241f049e77bd 100644 --- a/templates/bk7231n/beken_packager/config.json +++ b/templates/bk7231n/beken_packager/config.json @@ -11,11 +11,11 @@ "size": "68K" }, { - "firmware": "../../../out/bk7231N/oneos.bin", + "firmware": "../out/oneos.bin", "version": "1.00", "partition": "app", "start_addr": "0x00011000", - "size": "1156K" + "size": "1170K" } ] } diff --git a/templates/bk7231n/beken_packager/oneos_uart_1.00.bin b/templates/bk7231n/beken_packager/oneos_uart_1.00.bin new file mode 100644 index 0000000000000000000000000000000000000000..51610c31d49729026cafcfe9d2916caa8a881849 Binary files /dev/null and b/templates/bk7231n/beken_packager/oneos_uart_1.00.bin differ diff --git a/templates/bk7231n/board/board.c b/templates/bk7231n/board/board.c index eb48014b6d3ac6b9c16eb2edcc98bf1e19b75592..f90a2249469707c0dec0a15cffbc0982d04a04b5 100644 --- a/templates/bk7231n/board/board.c +++ b/templates/bk7231n/board/board.c @@ -22,12 +22,10 @@ *********************************************************************************************************************** */ -#include "os_hw.h" #include "os_task.h" #include "os_types.h" #include "os_memory.h" #include "os_sem.h" -#include "os_object.h" #include "shell.h" #include "board.h" @@ -39,6 +37,7 @@ #include "gpio_pub.h" #include "icu.h" +#include "fake_clock_pub.h" #include "arm_arch.h" #include "intc.h" #include "portmacro.h" @@ -60,41 +59,35 @@ struct wdg_context { static struct wdg_context g_wdg_context = { WDG_STATUS_STOP, 0, 0 }; +extern UINT32 soc_driver_init(void); extern void os_clk_init(void); extern void bk_reboot(void); -void os_hw_board_init(void) -{ -#if defined(RT_USING_HEAP) - /* init memory system */ -#if(CFG_SOC_NAME == SOC_BK7221U) - rt_system_heap_init(RT_HW_SDRAM_BEGIN, RT_HW_SDRAM_END); - rt_sdram_heap_init(); -#endif - os_memheap_init(&tcm_heap, "TCM", RT_HW_TCM_BEGIN, RT_HW_TCM_END-RT_HW_TCM_BEGIN); -#endif - +os_err_t os_hw_board_init(void) +{ + os_irq_enable(); + + portENABLE_INTERRUPTS(); + /* Heap initialization */ -#if defined(OS_USING_HEAP) - os_system_heap_init((void *)RT_HW_TCM_BEGIN, (void *)RT_HW_TCM_END); +#ifdef OS_USING_DEFAULT_HEAP + if ((os_size_t)OS_HW_TCM_END > (os_size_t)OS_HW_TCM_BEGIN) + { + os_default_heap_init(); + os_default_heap_add((void *)OS_HW_TCM_BEGIN, (os_size_t)OS_HW_TCM_END - (os_size_t)OS_HW_TCM_BEGIN, OS_MEM_ALG_DEFAULT); + } #endif - /* init hardware */ - driver_init(); - - /* interrupt init */ - rt_hw_interrupt_init(); - + soc_driver_init(); /* init system tick */ os_clk_init(); - portENABLE_INTERRUPTS(); - - os_board_auto_init(); + return OS_SUCCESS; } +OS_INIT_CALL(os_hw_board_init, OS_INIT_LEVEL_PRE_KERNEL_1, OS_INIT_SUBLEVEL_HIGH); #define WDT_DEV_NAME "wdt" /** @@ -107,23 +100,39 @@ void beken_hw_cpu_reset(void) while (1); } -SH_CMD_EXPORT(bk_cpu_reboot,beken_hw_cpu_reset, "bk cpu reboot cmd."); - - #ifdef BEKEN_USING_WLAN static int auto_func_init(void) { func_init_basic(); - func_init_extended(); + + func_init_extended(); + return 0; } -OS_INIT_CALL(auto_func_init, OS_INIT_LEVEL_PRE_DEVICE);#endif +OS_INIT_CALL(auto_func_init, OS_INIT_LEVEL_PRE_DEVICE, OS_INIT_SUBLEVEL_LOW); +#endif extern void cp15_enable_alignfault(void); static int auto_enable_alignfault(void) { cp15_enable_alignfault(); + return 0; } -OS_BOARD_INIT(auto_enable_alignfault); +OS_INIT_CALL(auto_enable_alignfault, OS_INIT_LEVEL_POST_KERNEL, OS_INIT_SUBLEVEL_MIDDLE); + +void print_exception_addr(unsigned int pc, unsigned int lr, unsigned int sp) +{ + os_kprintf("pc is %x, lr is %x, sp is %x\n", pc, lr, sp); + while (1); +} + +void os_hw_cpu_reset(void) +{ + bk_reboot(); + + while (1); +} + + diff --git a/templates/bk7231n/board/board.h b/templates/bk7231n/board/board.h index bb1f7498ba55010629e086d63d53000b0fd0c582..c510fd8bb84dfc1ceb7704dbab012e373b7aad0d 100644 --- a/templates/bk7231n/board/board.h +++ b/templates/bk7231n/board/board.h @@ -26,24 +26,32 @@ #define _BOARD_H_ #include +#include extern unsigned char _empty_ram; +#define BK7231N_FLASH_START_ADRESS ((uint32_t)0x1FE000) //2088960 +#define BK7231N_FLASH_SIZE (2 * 1024 * 1024) +#define BK7231N_FLASH_END_ADRESS ((uint32_t)(BK7231N_FLASH_START_ADRESS + BK7231N_FLASH_SIZE)) +#define BK7231N_FLASH_BLOCK_SIZE (uint32_t)4096 +#define BK7231N_FLASH_PAGE_SIZE (uint32_t)4096 + + /* High Speed */ -#define RT_HW_TCM_BEGIN (void*)&_empty_ram +#define OS_HW_TCM_BEGIN (void*)&_empty_ram #if (CFG_SOC_NAME == SOC_BK7231N) -#define RT_HW_TCM_END (void*)(0x00400000 + 192 * 1024) +#define OS_HW_TCM_END (void*)(0x00400000 + 192 * 1024) #else -#define RT_HW_TCM_END (void*)(0x00400000 + 256 * 1024) +#define OS_HW_TCM_END (void*)(0x00400000 + 256 * 1024) #endif /* Low Speed */ #define RT_HW_SDRAM_BEGIN (void*)(0x00900000) #define RT_HW_SDRAM_END (void*)(0x00900000 + 256 * 1024) -void rt_hw_board_init(void); +os_err_t os_hw_board_init(void); -void rt_sdram_heap_init(void); +void os_sdram_heap_init(void); void *sdram_malloc(unsigned long size); void sdram_free(void *ptr); void *sdram_calloc(unsigned int n, unsigned int size); @@ -54,4 +62,6 @@ void tcm_free(void *ptr); void *tcm_calloc(unsigned int n, unsigned int size); void *tcm_realloc(void *ptr, unsigned long size); +void os_hw_cpu_reset(void); + #endif diff --git a/templates/bk7231n/board/devices.c b/templates/bk7231n/board/devices.c index 47a16d907ec462f52776b6d96e4983c348ab5a20..c2cc11f879e558f8b5f9a1fed86a655ce0333241 100644 --- a/templates/bk7231n/board/devices.c +++ b/templates/bk7231n/board/devices.c @@ -2,43 +2,51 @@ #include "drv_uart.h" #include "uart_pub.h" #include "bus.h" -#include "os_drivers.h" #include "drv_wlan.h" - +#include "uart.h" +#include "icu_pub.h" #ifdef BEKEN_USING_UART1 -struct beken_uart_info uart1_info = { .port = UART1_PORT, - .irqno = IRQ_UART1 - }; - -OS_HAL_DEVICE_DEFINE("Uart_Type","uart1", uart1_info); +struct beken_uart_info uart1_info = { + .port = UART1_PORT, + .irqno = IRQ_UART1, + .inter_reg_addr = REG_UART1_INTR_ENABLE, + .fifo_status = REG_UART1_FIFO_STATUS, + .irq_uart_bit = IRQ_UART1_BIT +}; + +OS_HAL_DEVICE_DEFINE("uart_Type","uart1", uart1_info); #endif #ifdef BEKEN_USING_UART2 -struct beken_uart_info uart2_info = { .port = UART2_PORT, - .irqno = IRQ_UART2 - }; - -OS_HAL_DEVICE_DEFINE("Uart_Type","uart2", uart2_info); +struct beken_uart_info uart2_info = { + .port = UART2_PORT, + .irqno = IRQ_UART2, + .inter_reg_addr = REG_UART2_INTR_ENABLE, + .fifo_status = REG_UART2_FIFO_STATUS, + .irq_uart_bit = IRQ_UART2_BIT +}; + +OS_HAL_DEVICE_DEFINE("uart_Type","uart2", uart2_info); #endif #ifdef BEKEN_USING_WLAN -#ifdef BEKEN_USING_WLAN_STA +#ifdef BSP_USING_BK_STA struct beken_wifi_info wlan_sta_info = { .mac = {0}, .state = 0, .mode = 0, - .work_mode = OS_WLAN_STATION + .work_mode = net_dev_mode_sta }; OS_HAL_DEVICE_DEFINE("Wlan_Type",OS_WLAN_DEVICE_STA_NAME, wlan_sta_info); #endif /* BEKEN_USING_WLAN_STA */ -#ifdef BEKEN_USING_WLAN_AP +#ifdef BSP_USING_BK_AP struct beken_wifi_info wlan_ap_info = { .mac = {0}, .state = 0, .mode = 0, - .work_mode = OS_WLAN_AP + .work_mode = net_dev_mode_ap }; OS_HAL_DEVICE_DEFINE("Wlan_Type",OS_WLAN_DEVICE_AP_NAME, wlan_ap_info); #endif /* #ifdef BEKEN_USING_WLAN_AP */ diff --git a/templates/bk7231n/board/interrupt.c b/templates/bk7231n/board/interrupt.c index 67b89d5197a932a6933b4a0855a25d7de96fa416..28914b22eae5e3e4e15915d8da6f618c44a444f1 100644 --- a/templates/bk7231n/board/interrupt.c +++ b/templates/bk7231n/board/interrupt.c @@ -5,8 +5,6 @@ * */ -#include - #include "interrupt.h" #include "intc.h" #include "icu_pub.h" @@ -28,15 +26,9 @@ static void rt_hw_interrupt_handler(int vector, void *param) /** * This function will initialize hardware interrupt */ -void rt_hw_interrupt_init(void) +void os_hw_interrupt_init(void) { intc_init(); - - /* init interrupt nest, and context in thread sp */ - g_os_interrupt_nest = 0; - os_interrupt_from_task = 0; - os_interrupt_to_task = 0; - os_task_switch_interrupt_flag = 0; } /** diff --git a/templates/bk7231n/board/linker_scripts/link.icf b/templates/bk7231n/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..ef3b1c98c8466eff61930ed54e61c737e0da8a55 --- /dev/null +++ b/templates/bk7231n/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20017FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, last block CSTACK}; diff --git a/templates/bk7231n/board/linker_scripts/link.lds b/templates/bk7231n/board/linker_scripts/link.lds index 43683def8c9770d4402121afdfb96c54b0073971..3f207ef436faebac073175f71f2c3f480fcff5f5 100644 --- a/templates/bk7231n/board/linker_scripts/link.lds +++ b/templates/bk7231n/board/linker_scripts/link.lds @@ -33,7 +33,7 @@ MEMORY flash (rx) : ORIGIN = 0x00010000, LENGTH = 2M - 64k tcm (rw!x): ORIGIN = 0x003F0000, LENGTH = 60k - 512 itcm (rwx): ORIGIN = 0X003FEE00, LENGTH = 4608 - ram (rw!x): ORIGIN = 0x00400100, LENGTH = 192k - 0x100 + ram (rw!x): ORIGIN = 0x00400200, LENGTH = 192k - 0x100 } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -106,6 +106,9 @@ SECTIONS /* code, instructions.for example: i=i+1; */ .text : { + . = ALIGN(0x400); + KEEP(*(.isr_vector)) + . = ALIGN(4); *(.text) *(.text.*) @@ -113,11 +116,16 @@ SECTIONS /* .gnu.warning sections are handled specially by elf32.em. */ *(.gnu.warning) *(.gnu.linkonce.t*) + *(.glue_7t) *(.glue_7) INCLUDE common.lds - *(.glue_7t) *(.glue_7) /* oneos param */ + /* section information for fal flash devices */ + . = ALIGN(4); + __fal_flash_table_start = .; + KEEP(*(fal_flash_table)) + __fal_flash_table_end = .; . = ALIGN(4); @@ -127,8 +135,6 @@ SECTIONS PROVIDE(__ctors_end__ = .); . = ALIGN(4); - - } > flash /* read only data.for example: const int rom_data[3]={1,2,3}; */ diff --git a/templates/bk7231n/board/linker_scripts/link.sct b/templates/bk7231n/board/linker_scripts/link.sct index 81430048959e0dd49681892bb65d42894b0636ea..fce1874ef9e37af18bc646850374110569cc5336 100644 --- a/templates/bk7231n/board/linker_scripts/link.sct +++ b/templates/bk7231n/board/linker_scripts/link.sct @@ -6,6 +6,13 @@ LR_IROM1 0x08000000 0x00080000 { ; load region size_region ER_IROM1 0x08000000 0x00080000 { ; load address = execution address * (vtor_table, +First) * (InRoot$$Sections) + * (FSymTab) + * (AtestTcTab) + * (.init_call*) + * (at_cmd_tab) + * (driver_table) + * (device_table) + * (os_irq_hook) .ANY (+RO) } diff --git a/templates/bk7231n/board/ports/ef_cfg.h b/templates/bk7231n/board/ports/ef_cfg.hk similarity index 95% rename from templates/bk7231n/board/ports/ef_cfg.h rename to templates/bk7231n/board/ports/ef_cfg.hk index 70d10c1e491be0a5bc7c7d342a43a2d4331e7ead..097801a43e7a2086c6dc66dc478d570fb7c8d390 100644 --- a/templates/bk7231n/board/ports/ef_cfg.h +++ b/templates/bk7231n/board/ports/ef_cfg.hk @@ -39,7 +39,7 @@ //#define EF_ENV_USING_PFS_MODE /* the user setting size of ENV, must be word alignment */ -#define ENV_USER_SETTING_SIZE (PKG_EASYFLASH_ENV_SETTING_SIZE) +#define ENV_USER_SETTING_SIZE (1024) #ifdef PKG_EASYFLASH_ENV_AUTO_UPDATE /* Auto update ENV to latest default when current ENV version number is changed. */ @@ -64,7 +64,7 @@ #endif /* the minimum size of flash erasure */ -#define EF_ERASE_MIN_SIZE PKG_EASYFLASH_ERASE_GRAN +#define EF_ERASE_MIN_SIZE 1024 /* the flash write granularity, unit: bit * only support 1(nor flash)/ 8(stm32f4)/ 32(stm32f1)/ 64(stm32l4) */ @@ -97,7 +97,7 @@ * @note the log area size must be more than twice of EF_ERASE_MIN_SIZE */ /* backup area start address */ -#define EF_START_ADDR PKG_EASYFLASH_START_ADDR /* start address of param partition: 0x1FE000 */ +#define EF_START_ADDR PKG_EF_START_ADDR /* start address of param partition: 0x1FE000 */ #ifndef EF_ENV_USING_PFS_MODE #ifndef EF_ENV_USING_WL_MODE diff --git a/templates/bk7231n/board/ports/ef_port.c b/templates/bk7231n/board/ports/ef_port.ck similarity index 97% rename from templates/bk7231n/board/ports/ef_port.c rename to templates/bk7231n/board/ports/ef_port.ck index 7944ad52cae2fe83ccfc50d22301f0d74b0eb0f7..12d46213c6e625baabd62c6256b2a6ae87069837 100644 --- a/templates/bk7231n/board/ports/ef_port.c +++ b/templates/bk7231n/board/ports/ef_port.ck @@ -31,10 +31,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -63,7 +61,7 @@ EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) *default_env = default_env_set; *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]); - os_sem_init(&env_cache_lock, "env lock", 1, OS_IPC_FLAG_PRIO); + os_sem_init(&env_cache_lock, "env lock", 1, 1); return result; } @@ -165,7 +163,7 @@ EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) */ void ef_port_env_lock(void) { - os_sem_wait(&env_cache_lock, OS_IPC_WAITING_FOREVER); + os_sem_wait(&env_cache_lock, OS_WAIT_FOREVER); } /** diff --git a/templates/bk7231n/board/ports/fal_cfg.c b/templates/bk7231n/board/ports/fal_cfg.c new file mode 100644 index 0000000000000000000000000000000000000000..4eaa59b2522fcbd907e9a39522415d0b0df4f34f --- /dev/null +++ b/templates/bk7231n/board/ports/fal_cfg.c @@ -0,0 +1,30 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file fal_cfg.c + * + * @brief Flash abstract layer partition definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + + +static const fal_part_info_t fal_part_info[] = +{ + /* part, flash, addr, size, lock */ + { "easyflash", "onchip_flash", 0x1FE000, 0x00002000, FAL_PART_INFO_FLAGS_UNLOCKED}, +}; + diff --git a/templates/bk7231n/board/ports/flash_info.c b/templates/bk7231n/board/ports/flash_info.c new file mode 100644 index 0000000000000000000000000000000000000000..9a56481df673231e6516a8aa0a76bb0ea52b2c7f --- /dev/null +++ b/templates/bk7231n/board/ports/flash_info.c @@ -0,0 +1,8 @@ +static struct onchip_flash_info onchip_flash = +{ + .start_addr = BK7231N_FLASH_START_ADRESS, + .capacity = BK7231N_FLASH_SIZE, + .block_size = BK7231N_FLASH_BLOCK_SIZE, + .page_size = BK7231N_FLASH_PAGE_SIZE, +}; +OS_HAL_DEVICE_DEFINE("Onchip_Flash_Type", "onchip_flash", onchip_flash); diff --git a/templates/bk7231n/board/arm968_gcc.S b/templates/bk7231n/board/startup/arm968_gcc.S similarity index 100% rename from templates/bk7231n/board/arm968_gcc.S rename to templates/bk7231n/board/startup/arm968_gcc.S diff --git a/templates/bk7231n/board/boot_handlers.S b/templates/bk7231n/board/startup/boot_handlers.S similarity index 78% rename from templates/bk7231n/board/boot_handlers.S rename to templates/bk7231n/board/startup/boot_handlers.S index 4fd0bc6746c1aa12eeab03b07937de2d11adf5e0..5dcea858fd766c2dce3baba214e5fc5746d796ff 100644 --- a/templates/bk7231n/board/boot_handlers.S +++ b/templates/bk7231n/board/startup/boot_handlers.S @@ -31,7 +31,7 @@ .globl do_reserved - #include "sys_config.h" + #include "../sys_config.h" /* ======================================================================== * Macros * ======================================================================== */ @@ -357,54 +357,6 @@ _sysboot_tcmbss_init: .global rt_interrupt_to_thread /* Interrupt */ - .align 5 -do_undefined: - LDMFD SP!, {R0-R1} - PUSH_SVC_REG - STMFD sp!,{r0-r1} - PUSH_ALL_ARM_REG - BOOT_CHANGE_MODE BOOT_MODE_UND BOOT_MODE_MASK - LDMFD SP!, {R0-R1} - BL rt_hw_trap_udef - B . - - .align 5 -do_swi: - LDMFD SP!, {R0-R1} - PUSH_SVC_REG - BL rt_hw_trap_swi - B . - - .align 5 -do_pabort: - LDMFD SP!, {R0-R1} - PUSH_SVC_REG - STMFD sp!,{r0-r1} - PUSH_ALL_ARM_REG - BOOT_CHANGE_MODE BOOT_MODE_ABT BOOT_MODE_MASK - LDMFD SP!, {R0-R1} - BL rt_hw_trap_pabt - B . - - .align 5 -do_dabort: - LDMFD SP!, {R0-R1} - PUSH_SVC_REG - - STMFD sp!,{r0-r1} - PUSH_ALL_ARM_REG - BOOT_CHANGE_MODE BOOT_MODE_ABT BOOT_MODE_MASK - LDMFD SP!, {R0-R1} - BL rt_hw_trap_dabt - B . - - .align 5 -do_reserved: - LDMFD SP!, {R0-R1} - PUSH_SVC_REG - BL rt_hw_trap_resv - B . - .align 5 boot_undefined: STMFD sp!,{r0-r1} @@ -456,116 +408,11 @@ fiq_handler: LDR r0, [R1] BX r0 - .align 5 -do_irq: - LDMFD SP!, {R0-R1} - STMFD SP!, {R0-R12,LR} - - mrs r4, cpsr - orr r1, r4, #0xC0 @; disable interrupt - msr cpsr_c, r1 - - BL os_interrupt_enter - BL rt_irq_dispatch - BL os_interrupt_leave - - LDR R0, =os_task_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD SP!, {R0-R12,LR} - SUBS PC, LR, #4 - -rt_hw_context_switch_interrupt_do: - MOV R1, #0 - STR R1, [R0] - - MOV R1, SP - ADD SP, SP, #4*4 - LDMFD SP!, {R4-R12,LR} - - MRS R0, SPSR - SUB R2, LR, #4 - - MSR CPSR_c, #BOOT_FIQ_IRQ_MASK|BOOT_MODE_SVC - - STMFD SP!, {R2} - STMFD SP!, {R4-R12,LR} - LDMFD R1, {R1-R4} - STMFD SP!, {R1-R4} - STMFD SP!, {R0} - - LDR R4, =os_interrupt_from_task - LDR R5, [R4] - STR SP, [R5] - - LDR R6, =os_interrupt_to_task - LDR R6, [R6] - LDR SP, [R6] - - LDMFD SP!, {R4} - MSR SPSR_cxsf, R4 - - LDMFD SP!, {R0-R12,LR,PC}^ - - .align 5 -do_fiq: - LDMFD SP!, {R0-R1} - STMFD SP!,{R0-R7,LR} - - BL os_interrupt_enter - BL rt_fiq_dispatch - BL os_interrupt_leave - - MRS R3, spsr - AND R2, R3, #0x1F - CMP R2, #0x12 @; fiq from irq(0x12) - BEQ fiq_handler_return - - LDR R0, =os_task_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #1 - BEQ rt_hw_context_switch_interrupt_fiq_do - fiq_handler_return: LDMFD SP!,{R0-R7,LR} SUBS PC, LR, #4 - -rt_hw_context_switch_interrupt_fiq_do: - MOV R1, #0 - STR R1, [R0] - - MOV R1, SP @; pop {R0-R7,LR} but skip R0-R3 - ADD SP, SP, #4*4 - LDMFD SP!, {R4-R7,LR} - - MRS R0, SPSR - SUB R2, LR, #4 @; Save old task's PC to R2 - - MSR CPSR_c, #BOOT_FIQ_IRQ_MASK|BOOT_MODE_SVC - - STMFD SP!, {R2} @; Push old task's PC - STMFD SP!, {R4-R12,LR} @; Push old task's LR,R12-R4 - LDMFD R1, {R1-R4} @; pop old thread R0-R3 to R1-R4 - STMFD SP!, {R1-R4} @; Push old thread R0-R3 - STMFD SP!, {R0} @; Push old task's CPSR - - LDR R4, =os_interrupt_from_task - LDR R5, [R4] - STR SP, [R5] - - LDR R6, =os_interrupt_to_task - LDR R6, [R6] - LDR SP, [R6] - - LDMFD SP!, {R4} - MSR SPSR_cxsf, R4 - - LDMFD SP!, {R0-R12,LR,PC}^ - - + /* ======================================================================== * Globals * ======================================================================== */ diff --git a/templates/bk7231n/board/boot_vectors.S b/templates/bk7231n/board/startup/boot_vectors.S similarity index 100% rename from templates/bk7231n/board/boot_vectors.S rename to templates/bk7231n/board/startup/boot_vectors.S diff --git a/templates/bk7231n/board/weave.yaml b/templates/bk7231n/board/weave.yaml index 3b378b06b57c30b49aa9920a18c733688a5b0ccb..20c55fdc2102fba5880e6cb2b4cb15045178e259 100644 --- a/templates/bk7231n/board/weave.yaml +++ b/templates/bk7231n/board/weave.yaml @@ -1,15 +1,20 @@ # 组名 group_name: bsp +# 源码 +source_file: + - board.c + - devices.c + - interrupt.c + - startup/boot_vectors.S ? {is_compiler("gcc")} + - startup/boot_handlers.S ? {is_compiler("gcc")} + - startup/arm968_gcc.S ? {is_compiler("gcc")} + # 编译连接信息 build_option: cpppath: - . + - ../../../kernel/include/ - ports - - kernel/include - -# 源码 -source_file: - - ./*.c - - ./*.S - - ./ports/ef_port.c ? {is_define('PKG_USING_EASYFLASH')} + cppdefines: + - BK7231N \ No newline at end of file diff --git a/templates/bk7231n/cconfig.h b/templates/bk7231n/cconfig.h index 158daeb4d6d9b40229db9c27ca4a32f6af4472b8..b151177e20e251bfff9b0d2417dfb440b14b7f43 100644 --- a/templates/bk7231n/cconfig.h +++ b/templates/bk7231n/cconfig.h @@ -4,7 +4,7 @@ /* compiler configure file for CMCC IOT in GCC*/ #define HAVE_NEWLIB_H 1 -#define LIBC_VERSION "newlib 2.4.0" +#define LIBC_VERSION "newlib 3.3.0" #define HAVE_SYS_SIGNAL_H 1 #define HAVE_SYS_SELECT_H 1 @@ -12,7 +12,10 @@ #define HAVE_FDSET 1 #define HAVE_SIGACTION 1 -#define GCC_VERSION "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]" +#define HAVE_SIGEVENT 1 +#define HAVE_SIGINFO 1 +#define HAVE_SIGVAL 1 +#define GCC_VERSION "9.3.1 20200408 (release)" #define STDC "2011" #endif diff --git a/templates/bk7231n/make.py b/templates/bk7231n/make.py index 8ba604b26da4aab63b2d9e05677ce62a31971aca..211c9c2261a548c7426d1e39625ee4b3aa501d5c 100644 --- a/templates/bk7231n/make.py +++ b/templates/bk7231n/make.py @@ -4,10 +4,10 @@ import sys import os if len(sys.argv) == 1: - os.system("scons --buildlib=\"beken_sdk\" -j8") - os.system("scons -j8") + os.system("oos build --buildlib=\"beken_sdk\" -j8") + os.system("oos build -j8") elif len(sys.argv) == 2 and sys.argv[1] == "clean": - os.system("scons --buildlib=\"beken_sdk\" -c") - os.system("scons -c") + os.system("oos build --buildlib=\"beken_sdk\" -c") + os.system("oos build -c") else: print("param error!") \ No newline at end of file diff --git a/templates/bk7231n/oneos_config.h b/templates/bk7231n/oneos_config.h index a13bbbff3b1820480a786a8c99bea6b405f34236..e0c4c83c6790389c0869c6c29f86c11445e31246 100644 --- a/templates/bk7231n/oneos_config.h +++ b/templates/bk7231n/oneos_config.h @@ -11,66 +11,67 @@ #define OS_NAME_MAX_15 #define OS_NAME_MAX 15 -#define OS_ALIGN_SIZE 4 #define OS_TASK_PRIORITY_32 #define OS_TASK_PRIORITY_MAX 32 #define OS_TICK_PER_SECOND 100 +#define OS_SCHEDULE_TIME_SLICE 10 #define OS_USING_OVERFLOW_CHECK -#define OS_MAIN_TASK_STACK_SIZE 2048 -#define OS_USING_HOOK -#define OS_USING_IDLE_HOOK -#define OS_IDLE_HOOK_LIST_SIZE 4 +#define OS_USING_ASSERT +#define OS_USING_KERNEL_LOCK_CHECK +#define OS_USING_KERNEL_DEBUG +#define KLOG_GLOBAL_LEVEL_WARNING +#define KLOG_GLOBAL_LEVEL 1 +#define KLOG_USING_COLOR +#define KLOG_WITH_FUNC_LINE +#define OS_SYS_TASK_STACK_SIZE 2048 #define OS_IDLE_TASK_STACK_SIZE 512 -#define OS_USING_TIMER_SOFT -#define OS_TIMER_TASK_PRIO 0 +#define OS_RECYCLE_TASK_STACK_SIZE 512 +#define OS_USING_KERNEL_TIMER +#define OS_USING_HASH_BUCKET_TIMER #define OS_TIMER_TASK_STACK_SIZE 2048 +#define OS_HASH_BUCKET_TIMER_POWER 3 #define OS_USING_WORKQUEUE #define OS_USING_SYSTEM_WORKQUEUE #define OS_SYSTEM_WORKQUEUE_STACK_SIZE 2048 #define OS_SYSTEM_WORKQUEUE_PRIORITY 8 -/* Task communication */ +/* Inter-task communication and synchronization */ -#define OS_USING_SEMAPHORE #define OS_USING_MUTEX +#define OS_USING_SEMAPHORE #define OS_USING_EVENT -#define OS_USING_MAILBOX #define OS_USING_MESSAGEQUEUE -#define OS_USING_COMPLETION -#define OS_USING_DATAQUEUE -#define OS_USING_WAITQUEUE -/* end of Task communication */ +#define OS_USING_MAILBOX +/* end of Inter-task communication and synchronization */ /* Memory management */ -#define OS_USING_MEM_POOL -#define OS_USING_MEM_SMALL +#define OS_USING_DEFAULT_HEAP #define OS_USING_HEAP -#define OS_MEM_STATS +#define OS_USING_ALG_FIRSTFIT +#define OS_USING_MEM_POOL /* end of Memory management */ -/* Kernel console */ +/* Debug */ -#define OS_USING_CONSOLE -#define OS_CONSOLE_DEVICE_NAME "uart1" -/* end of Kernel console */ -/* Enable assert */ +/* Memory Monitor */ -#define OS_USING_ASSERT -/* end of Enable assert */ +/* end of Memory Monitor */ +/* end of Debug */ /* end of Kernel */ -/* C standard library */ +/* C standard library adapter */ -#define OS_USING_LIBC -/* end of C standard library */ +#define OS_USING_LIBC_ADAPTER +#define OS_USING_NEWLIB_ADAPTER +#define OS_USING_ARMCCLIB_ADAPTER +/* end of C standard library adapter */ /* Osal */ /* POSIX compatibility layer */ -#define OS_USING_POSIX /* end of POSIX compatibility layer */ /* RT-Thread compatibility layer */ @@ -84,161 +85,249 @@ /* FreeRTOS compatibility layer */ /* end of FreeRTOS compatibility layer */ + +/* C++ Features */ + +/* end of C++ Features */ /* end of Osal */ /* Drivers */ #define OS_USING_DEVICE +#define OS_USING_DEVICE_NOTIFY + +/* Audio */ + +/* end of Audio */ + +/* BLOCK */ + +#define OS_USING_BLOCK +/* end of BLOCK */ + +/* Boot */ + +/* CORTEX-M Boot */ + +/* end of CORTEX-M Boot */ +/* end of Boot */ + +/* Cache */ + +#define BSP_CACHE_LINE_SIZE 32 +/* end of Cache */ + +/* Camera */ + +/* end of Camera */ + +/* CAN */ + +/* end of CAN */ + +/* CONSOLE */ + +#define OS_USING_CONSOLE +#define OS_CONSOLE_DEVICE_NAME "uart1" +/* end of CONSOLE */ + +/* DMA */ + +#define OS_USING_DMA +#define OS_USING_DMA_RAM +#define OS_USING_SOFT_DMA +#define OS_SOFT_DMA_SUPPORT_NORMAL_MODE +#define OS_SOFT_DMA_SUPPORT_CIRCLE_MODE +#define OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT +/* end of DMA */ + +/* EEPROM */ + +/* end of EEPROM */ + +/* FAL */ + +/* end of FAL */ + +/* Graphic */ + +/* end of Graphic */ /* HAL */ -#define SOC_FAMILY_BK72XX -#define SOC_ARM9_BK7231N +#define MANUFACTOR_BEKEN +#define SOC_ARM9E_BK7231N /* Hardware Drivers Config */ #define BEKEN_USING_UART1 +#define BEKEN_UART1_BAUD 115200 #define BEKEN_USING_UART2 +#define BEKEN_UART2_BAUD 115200 #define BEKEN_USING_FLASH #define BEKEN_USING_GPIO #define BEKEN_USING_WLAN #define LWIP_NETIF_HOSTNAME 1 -#define BEKEN_USING_WLAN_STA -#define BEKEN_USING_WLAN_AP +#define BSP_USING_BK_STA +#define OS_WLAN_DEVICE_STA_NAME "w0" +#define BSP_USING_BK_AP +#define OS_WLAN_DEVICE_AP_NAME "bk" #define OS_WLAN_PROT_LWIP_PBUF_FORCE -#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define OS_MAIN_THREAD_STACK_SIZE 2048 /* end of Hardware Drivers Config */ /* end of HAL */ -/* Audio */ +/* HwCrypto */ -/* end of Audio */ +/* end of HwCrypto */ + +/* I2C */ + +/* end of I2C */ + +/* Infrared */ + +/* end of Infrared */ + +/* LPMGR */ + +/* end of LPMGR */ /* MISC */ /* end of MISC */ -/* PIN */ +/* MTD */ -#define OS_USING_PIN -#define OS_PIN_MAX_CHIP 1 -/* end of PIN */ +#define OS_USING_MTD +/* end of MTD */ -/* Serial */ +/* NAND */ -#define OS_USING_SERIAL -#define OS_SERIAL_RX_BUFSZ 64 -#define OS_SERIAL_TX_BUFSZ 64 -/* end of Serial */ +/* end of NAND */ -/* WDG */ +/* NET */ -/* end of WDG */ +#define OS_USING_NET_DEVICE +#define OS_NET_MAC_LENGTH 6 + +/* net xfer task config */ + +#define OS_NET_TX_TASK_STACK_SIZE 512 +#define OS_NET_TX_TASK_PRIORITY 10 +#define OS_NET_TX_MB_MAX_NUM 4 +#define OS_NET_RX_TASK_STACK_SIZE 512 +#define OS_NET_RX_TASK_PRIORITY 9 +/* end of net xfer task config */ + +/* protocol support */ + +#define OS_NET_PROTOCOL_LWIP +/* end of protocol support */ +#define OS_USING_WLAN +#define OS_WLAN_SSID_MAX_LENGTH 32 +#define BSP_USING_BK7231N +#define OS_USING_BK_AP +#define BSP_USING_BK_AP_SSID "bk7231n" +#define BSP_USING_BK_AP_PASSWORD "12345678" +#define BSP_USING_BK_AP_CHANNEL 1 +#define BSP_USING_BK_AP_SECURITY 1 +/* end of NET */ + +/* PIN */ + +#define OS_USING_PIN +#define OS_PIN_MAX_CHIP 1 +/* end of PIN */ /* RTC */ #define OS_USING_RTC -#define OS_USING_SOFT_RTC +#define OS_RTC_DEV_NAME "rtc" /* end of RTC */ -/* CAN */ +/* SDIO */ -/* end of CAN */ +#define OS_USING_SDIO +#define OS_SDIO_STACK_SIZE 512 +#define OS_SDIO_TASK_PRIORITY 15 +#define OS_MMCSD_STACK_SIZE 1024 +#define OS_MMCSD_TASK_PREORITY 22 +#define OS_MMCSD_MAX_PARTITION 16 +/* end of SDIO */ -/* I2C */ +/* Sensors */ -/* end of I2C */ +/* end of Sensors */ -/* SPI */ +/* Serial */ -/* end of SPI */ +#define OS_USING_SERIAL +#define OS_SERIAL_DELAY_CLOSE +#define OS_SERIAL_RX_BUFSZ 64 +#define OS_SERIAL_TX_BUFSZ 64 -/* FAL */ +/* posix serial */ -/* end of FAL */ +/* end of posix serial */ -/* RTT */ +/* rtt uart */ -/* end of RTT */ +/* end of rtt uart */ +/* end of Serial */ -/* Timer */ +/* SFLASH */ -#define OS_USING_TIMER_DRIVER -#define OS_USING_CLOCKSOURCE -/* end of Timer */ +/* end of SFLASH */ -/* HwCrypto */ +/* SN */ -/* end of HwCrypto */ +/* end of SN */ -/* SDIO */ +/* SPI */ -/* end of SDIO */ +#define OS_USING_SPI +/* end of SPI */ -/* WLAN */ +/* Timer */ -#define OS_USING_WIFI -#define OS_WLAN_DEVICE_STA_NAME "w0" -#define OS_WLAN_DEVICE_AP_NAME "ap" -#define OS_WLAN_SSID_MAX_LENGTH 32 -#define OS_WLAN_PASSWORD_MAX_LENGTH 32 -#define OS_WLAN_DEV_EVENT_NUM 2 -#define OS_WLAN_MANAGE_ENABLE -#define OS_WLAN_SCAN_WAIT_MS 10000 -#define OS_WLAN_CONNECT_WAIT_MS 10000 -#define OS_WLAN_SCAN_SORT -#define OS_WLAN_MSH_CMD_ENABLE -#define OS_WLAN_AUTO_CONNECT_ENABLE -#define AUTO_CONNECTION_PERIOD_MS 2000 -#define OS_WLAN_CFG_ENABLE -#define OS_WLAN_CFG_INFO_MAX 3 -#define OS_WLAN_PROT_ENABLE -#define OS_WLAN_PROT_NAME_LEN 8 -#define OS_WLAN_PROT_MAX 2 -#define OS_WLAN_DEFAULT_PROT "lwip" -#define OS_WLAN_PROT_LWIP_ENABLE -#define OS_WLAN_PROT_LWIP_NAME "lwip" -#define OS_WLAN_WORK_TASK_ENABLE -#define OS_WLAN_WORKQUEUE_TASK_NAME "wlan" -#define OS_WLAN_WORKQUEUE_TASK_SIZE 2048 -#define OS_WLAN_WORKQUEUE_TASK_PRIO 15 -/* end of WLAN */ +#define OS_USING_TIMEKEEPING +/* end of Timer */ -/* Graphic */ +/* TinyUSB */ -/* end of Graphic */ +/* end of TinyUSB */ /* Touch */ /* end of Touch */ -/* Sensors */ - -/* end of Sensors */ - /* USB */ /* end of USB */ -/* Infrared */ +/* USB WIFI */ -/* end of Infrared */ +/* end of USB WIFI */ -/* Low power manager */ +/* WDG */ -/* end of Low power manager */ +/* end of WDG */ +/* end of Drivers */ -/* NAND */ +/* Components */ -/* end of NAND */ +/* DBoT */ -/* DMA */ +/* end of DBoT */ -#define OS_USING_DMA -/* end of DMA */ -/* end of Drivers */ +/* WWD */ -/* Components */ +/* end of WWD */ + +/* AMS */ + +/* end of AMS */ /* Atest */ @@ -246,271 +335,43 @@ /* BLE */ -#define OS_USING_BLE -#define BLE_USING_NIMBLE - -/* NimBLE */ - -#define BLE_ROLE_BROADCASTER -#define MYNEWT_VAL_BLE_ROLE_BROADCASTER 1 -#define BLE_ROLE_PERIPHERAL -#define MYNEWT_VAL_BLE_ROLE_PERIPHERAL 1 -#define MYNEWT_VAL_BLE_ROLE_OBSERVER 0 -#define MYNEWT_VAL_BLE_ROLE_CENTRAL 0 -#define MYNEWT_VAL_BLE_MAX_CONNECTIONS 1 -#define MYNEWT_VAL_BLE_MAX_PERIODIC_SYNCS 1 -#define BLE_WHITELIST -#define MYNEWT_VAL_BLE_WHITELIST 1 -#define MYNEWT_VAL_BLE_MULTI_ADV_INSTANCES 0 -#define MYNEWT_VAL_BLE_EXT_ADV 0 -#define MYNEWT_VAL_BLE_PERIODIC_ADV 0 -#define MYNEWT_VAL_BLE_PERIODIC_ADV_SYNC_TRANSFER 0 -#define MYNEWT_VAL_BLE_EXT_ADV_MAX_SIZE 31 -#define MYNEWT_VAL_BLE_VERSION 50 -#define MYNEWT_VAL_BLE_ISO 0 -#define MYNEWT_VAL_BLE_ISO_TEST 0 -#define MYNEWT_VAL_MSYS_1_BLOCK_COUNT 16 -#define MYNEWT_VAL_MSYS_1_BLOCK_SIZE 292 -#define MYNEWT_VAL_MSYS_2_BLOCK_COUNT 0 -#define MYNEWT_VAL_MSYS_2_BLOCK_SIZE 0 - -/* HOST */ - -#define OS_USING_NIMBLE_HOST -#define MYNEWT_VAL_BLE_HOST 1 -#define NIMBLE_CFG_HOST 1 -#define MYNEWT_VAL_BLE_HOST_THREAD_STACK_SIZE 2048 -#define MYNEWT_VAL_BLE_HOST_THREAD_PRIORITY 3 -#define MYNEWT_VAL_BLE_HS_AUTO_START 1 -#define MYNEWT_VAL_BLE_HS_DEBUG 0 -#define MYNEWT_VAL_BLE_HS_PHONY_HCI_ACKS 0 -#define MYNEWT_VAL_BLE_HS_REQUIRE_OS 1 -#define MYNEWT_VAL_BLE_MONITOR_UART 0 -#define MYNEWT_VAL_BLE_MONITOR_UART_DEV "uart0" -#define MYNEWT_VAL_BLE_MONITOR_UART_BAUDRATE 1000000 -#define MYNEWT_VAL_BLE_MONITOR_UART_BUFFER_SIZE 64 -#define MYNEWT_VAL_BLE_MONITOR_RTT 0 -#define MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_NAME "btmonitor" -#define MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_SIZE 256 -#define BLE_MONITOR_RTT_BUFFERED -#define MYNEWT_VAL_BLE_MONITOR_RTT_BUFFERED 1 -#define MYNEWT_VAL_BLE_MONITOR_CONSOLE_BUFFER_SIZE 128 -#define MYNEWT_VAL_BLE_L2CAP_MAX_CHANS 3 -#define MYNEWT_VAL_BLE_L2CAP_SIG_MAX_PROCS 1 -#define BLE_L2CAP_JOIN_RX_FRAGS -#define MYNEWT_VAL_BLE_L2CAP_JOIN_RX_FRAGS 1 -#define MYNEWT_VAL_BLE_L2CAP_RX_FRAG_TIMEOUT 30000 -#define MYNEWT_VAL_BLE_L2CAP_COC_MAX_NUM 0 -#define MYNEWT_VAL_BLE_L2CAP_COC_MPS 292 -#define MYNEWT_VAL_BLE_L2CAP_ENHANCED_COC 0 -#define MYNEWT_VAL_BLE_SM_LEGACY 1 -#define MYNEWT_VAL_BLE_SM_SC 0 -#define MYNEWT_VAL_BLE_SM_MAX_PROCS 1 -#define MYNEWT_VAL_BLE_SM_IO_CAP 0x03 -#define MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG 0 -#define MYNEWT_VAL_BLE_SM_BONDING 0 -#define MYNEWT_VAL_BLE_SM_MITM 0 -#define MYNEWT_VAL_BLE_SM_KEYPRESS 0 -#define MYNEWT_VAL_BLE_SM_OUR_KEY_DIST 0 -#define MYNEWT_VAL_BLE_SM_THEIR_KEY_DIST 0 -#define MYNEWT_VAL_BLE_SM_SC_DEBUG_KEYS 0 -#define MYNEWT_VAL_BLE_GAP_MAX_PENDING_CONN_PARAM_UPDATE 1 -#define MYNEWT_VAL_BLE_GATT_DISC_ALL_SVCS 0 -#define MYNEWT_VAL_BLE_GATT_DISC_SVC_UUID 0 -#define MYNEWT_VAL_BLE_GATT_FIND_INC_SVCS 0 -#define MYNEWT_VAL_BLE_GATT_DISC_ALL_CHRS 0 -#define MYNEWT_VAL_BLE_GATT_DISC_CHR_UUID 0 -#define MYNEWT_VAL_BLE_GATT_DISC_ALL_DSCS 0 -#define MYNEWT_VAL_BLE_GATT_READ 0 -#define MYNEWT_VAL_BLE_GATT_READ_UUID 0 -#define MYNEWT_VAL_BLE_GATT_READ_LONG 0 -#define MYNEWT_VAL_BLE_GATT_READ_MULT 0 -#define MYNEWT_VAL_BLE_GATT_WRITE_NO_RSP 0 -#define MYNEWT_VAL_BLE_GATT_SIGNED_WRITE 0 -#define MYNEWT_VAL_BLE_GATT_WRITE 0 -#define MYNEWT_VAL_BLE_GATT_WRITE_LONG 0 -#define MYNEWT_VAL_BLE_GATT_WRITE_RELIABLE 0 -#define BLE_GATT_NOTIFY -#define MYNEWT_VAL_BLE_GATT_NOTIFY 1 -#define BLE_GATT_INDICATE -#define MYNEWT_VAL_BLE_GATT_INDICATE 1 -#define MYNEWT_VAL_BLE_GATT_READ_MAX_ATTRS 8 -#define MYNEWT_VAL_BLE_GATT_WRITE_MAX_ATTRS 4 -#define MYNEWT_VAL_BLE_GATT_MAX_PROCS 4 -#define MYNEWT_VAL_BLE_GATT_RESUME_RATE 1000 -#define BLE_ATT_SVR_FIND_INFO -#define MYNEWT_VAL_BLE_ATT_SVR_FIND_INFO 1 -#define BLE_ATT_SVR_FIND_TYPE -#define MYNEWT_VAL_BLE_ATT_SVR_FIND_TYPE 1 -#define BLE_ATT_SVR_READ_TYPE -#define MYNEWT_VAL_BLE_ATT_SVR_READ_TYPE 1 -#define BLE_ATT_SVR_READ -#define MYNEWT_VAL_BLE_ATT_SVR_READ 1 -#define BLE_ATT_SVR_READ_BLOB -#define MYNEWT_VAL_BLE_ATT_SVR_READ_BLOB 1 -#define BLE_ATT_SVR_READ_MULT -#define MYNEWT_VAL_BLE_ATT_SVR_READ_MULT 1 -#define BLE_ATT_SVR_READ_GROUP_TYPE -#define MYNEWT_VAL_BLE_ATT_SVR_READ_GROUP_TYPE 1 -#define BLE_ATT_SVR_WRITE -#define MYNEWT_VAL_BLE_ATT_SVR_WRITE 1 -#define BLE_ATT_SVR_WRITE_NO_RSP -#define MYNEWT_VAL_BLE_ATT_SVR_WRITE_NO_RSP 1 -#define BLE_ATT_SVR_SIGNED_WRITE -#define MYNEWT_VAL_BLE_ATT_SVR_SIGNED_WRITE 1 -#define BLE_ATT_SVR_QUEUED_WRITE -#define MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE 1 -#define BLE_ATT_SVR_NOTIFY -#define MYNEWT_VAL_BLE_ATT_SVR_NOTIFY 1 -#define BLE_ATT_SVR_INDICATE -#define MYNEWT_VAL_BLE_ATT_SVR_INDICATE 1 -#define MYNEWT_VAL_BLE_ATT_PREFERRED_MTU 256 -#define MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES 64 -#define MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE_TMO 30000 -#define MYNEWT_VAL_BLE_RPA_TIMEOUT 300 -#define MYNEWT_VAL_BLE_STORE_MAX_BONDS 3 -#define MYNEWT_VAL_BLE_STORE_MAX_CCCDS 8 -#define MYNEWT_VAL_BLE_MESH 0 -#define MYNEWT_VAL_BLE_HS_FLOW_CTRL 0 -#define MYNEWT_VAL_BLE_HS_FLOW_CTRL_ITVL 1000 -#define MYNEWT_VAL_BLE_HS_FLOW_CTRL_THRESH 2 -#define MYNEWT_VAL_BLE_HS_FLOW_CTRL_TX_ON_DISCONNECT 0 -#define MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN 1 -#define MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN_TIMEOUT 2000 -#define MYNEWT_VAL_BLE_HS_SYSINIT_STAGE 200 -#define MYNEWT_VAL_BLE_HS_LOG_MOD 4 -#define MYNEWT_VAL_BLE_HS_LOG_LVL 1 - -/* Services */ - -/* ans */ - -#define MYNEWT_VAL_BLE_SVC_ANS_NEW_ALERT_CAT 0 -#define MYNEWT_VAL_BLE_SVC_ANS_UNR_ALERT_CAT 0 -#define MYNEWT_VAL_BLE_SVC_ANS_SYSINIT_STAGE 303 -/* end of ans */ - -/* bas */ - -#define MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM 0 -#define MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_NOTIFY_ENABLE 1 -#define MYNEWT_VAL_BLE_SVC_BAS_SYSINIT_STAGE 303 -/* end of bas */ - -/* bleuart */ - -#define MYNEWT_VAL_BLEUART_MAX_INPUT 120 -#define MYNEWT_VAL_BLEUART_SYSINIT_STAGE 500 -/* end of bleuart */ - -/* dis */ - -#define MYNEWT_VAL_BLE_SVC_DIS_DEFAULT_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_READ_PERM 0 -#define MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_DEFAULT "Apache Mynewt NimBLE" -#define MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_READ_PERM -1 -#define MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_DEFAULT "notset" -#define MYNEWT_VAL_BLE_SVC_DIS_SYSINIT_STAGE 303 -/* end of dis */ - -/* gap */ - -#define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME "nimble" -#define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_WRITE_PERM -1 -#define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH 31 -#define MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE 1157 -#define MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM -1 -#define MYNEWT_VAL_BLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL 0 -#define MYNEWT_VAL_BLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL 0 -#define MYNEWT_VAL_BLE_SVC_GAP_PPCP_SLAVE_LATENCY 0 -#define MYNEWT_VAL_BLE_SVC_GAP_PPCP_SUPERVISION_TMO 0 -#define MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION -1 -#define MYNEWT_VAL_BLE_SVC_GAP_SYSINIT_STAGE 301 -/* end of gap */ - -/* gatt */ - -#define MYNEWT_VAL_BLE_SVC_GATT_SYSINIT_STAGE 302 -/* end of gatt */ - -/* ias */ - -#define MYNEWT_VAL_BLE_SVC_IAS_SYSINIT_STAGE 303 -/* end of ias */ - -/* ipss */ - -#define MYNEWT_VAL_BLE_SVC_IPSS_SYSINIT_STAGE 303 -/* end of ipss */ - -/* lls */ - -#define MYNEWT_VAL_BLE_SVC_LLS_SYSINIT_STAGE 303 -/* end of lls */ - -/* tps */ - -#define MYNEWT_VAL_BLE_SVC_TPS_SYSINIT_STAGE 303 -/* end of tps */ -/* end of Services */ +/* BLE is now only supported on NRF52 */ -/* Store */ +/* end of BLE */ -/* config */ +/* cJSON */ -#define MYNEWT_VAL_BLE_STORE_CONFIG_PERSIST 1 -#define MYNEWT_VAL_BLE_STORE_SYSINIT_STAGE 500 -/* end of config */ +#define PKG_USING_CJSON +/* end of cJSON */ -/* ram */ +/* CLI */ -#define MYNEWT_VAL_BLE_STORE_RAM_SYSINIT_STAGE 500 -#define MYNEWT_VAL_BLE_STORE_RAM_DEPRECATED_FLAG 0 -/* end of ram */ -/* end of Store */ +/* end of CLI */ -/* Mesh */ +/* Cloud */ -/* end of Mesh */ -/* end of HOST */ +/* Aliyun */ -/* Controller */ +/* end of Aliyun */ -/* end of Controller */ +/* AWS */ -/* Transport */ +/* end of AWS */ -#define BLE_USING_RAM -#define MYNEWT_VAL_BLE_HCI_EVT_HI_BUF_COUNT 2 -#define MYNEWT_VAL_BLE_HCI_EVT_LO_BUF_COUNT 7 -#define MYNEWT_VAL_BLE_HCI_EVT_BUF_SIZE 70 -#define MYNEWT_VAL_BLE_ACL_BUF_COUNT 8 -#define MYNEWT_VAL_BLE_ACL_BUF_SIZE 255 -#define MYNEWT_VAL_BLE_TRANS_RAM_SYSINIT_STAGE 100 +/* Baidu */ -/* beken-ram */ +/* end of Baidu */ -/* end of beken-ram */ -/* end of Transport */ +/* CTWing */ -/* Drivers */ +/* MQTT */ -/* end of Drivers */ -#define NIMBLE_CFG_TINYCRYPT -/* end of NimBLE */ -/* end of BLE */ +/* end of MQTT */ +/* end of CTWing */ -/* Cloud */ +/* Huawei */ + +/* end of Huawei */ /* OneNET */ @@ -526,87 +387,109 @@ /* end of EDP */ /* end of OneNET */ +/* end of Cloud */ -/* Huawei */ +/* CMS */ -/* end of Huawei */ +/* end of CMS */ -/* AWS */ +/* Diagnose */ -/* end of AWS */ -/* Aliyun */ +/* eCoreDump */ -/* end of Aliyun */ -/* end of Cloud */ +/* end of eCoreDump */ +/* end of Diagnose */ /* Dlog */ #define OS_USING_DLOG -#define DLOG_OUTPUT_LVL_D -#define DLOG_GLOBAL_LEVEL 7 - -/* Dlog backend option */ - -#define DLOG_BACKEND_USING_CONSOLE -/* end of Dlog backend option */ +#define DLOG_PRINT_LVL_W +#define DLOG_GLOBAL_PRINT_LEVEL 4 +#define DLOG_COMPILE_LVL_W +#define DLOG_COMPILE_LEVEL 4 #define DLOG_USING_FILTER /* Log format */ +#define DLOG_WITH_FUNC_LINE #define DLOG_USING_COLOR #define DLOG_OUTPUT_TIME_INFO -#define DLOG_OUTPUT_LEVEL_INFO -#define DLOG_OUTPUT_TAG_INFO /* end of Log format */ + +/* Dlog backend option */ + +#define DLOG_BACKEND_USING_CONSOLE +/* end of Dlog backend option */ /* end of Dlog */ +/* Easyflash */ + +/* end of Easyflash */ + +/* FFmpeg */ + +/* end of FFmpeg */ + +/* FileSystem */ + +#define OS_USING_VFS +#define VFS_MOUNTPOINT_MAX 4 +#define VFS_FILESYSTEM_TYPES_MAX 4 +#define VFS_FD_MAX 16 +/* end of FileSystem */ + +/* GUI */ + +#define OS_GUI_DISP_DEV_NAME "lcd" +#define OS_GUI_INPUT_DEV_NAME "touch" +/* end of GUI */ + +/* IoTjs */ + +/* end of IoTjs */ + +/* JerryScript */ + +/* end of JerryScript */ + /* Network */ /* Acw */ /* end of Acw */ -/* ANDLINK */ +/* HGN */ + +/* end of HGN */ -/* end of ANDLINK */ +/* TCP/IP */ /* LwIP */ #define NET_USING_LWIP -#define NET_USING_LWIP202 +#define NET_USING_LWIP212 +#define LWIP_IPV6_FORWARD 1 #define LWIP_USING_IGMP #define LWIP_USING_ICMP #define LWIP_USING_DNS #define LWIP_USING_DHCP #define IP_SOF_BROADCAST 1 #define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define LWIP_STATIC_IPADDR "192.168.1.30" -#define LWIP_STATIC_GWADDR "192.168.1.1" -#define LWIP_STATIC_MSKADDR "255.255.255.0" -/* end of Static IPv4 Address */ #define LWIP_USING_UDP #define LWIP_USING_TCP #define LWIP_USING_RAW #define LWIP_MEMP_NUM_NETCONN 8 #define LWIP_PBUF_NUM 8 #define LWIP_RAW_PCB_NUM 4 -#define LWIP_UDP_PCB_NUM 6 +#define LWIP_UDP_PCB_NUM 7 #define LWIP_TCP_PCB_NUM 4 #define LWIP_TCP_SEG_NUM 40 #define LWIP_TCP_SND_BUF 4096 #define LWIP_TCP_WND_SIZE 4096 #define LWIP_TCP_TASK_PRIORITY 10 #define LWIP_TCP_TASK_MBOX_SIZE 8 -#define LWIP_TCP_TASK_STACKSIZE 4096 -#define LWIP_NO_RX_TASK -#define LWIP_NO_TX_TASK -#define LWIP_ETH_TASK_PRIORITY 12 -#define LWIP_ETH_TASK_STACKSIZE 1024 -#define LWIP_ETH_TASK_MBOX_SIZE 8 +#define LWIP_TCP_TASK_STACKSIZE 1024 #define LWIP_NETIF_STATUS_CALLBACK 1 #define LWIP_NETIF_LINK_CALLBACK 1 #define SO_REUSE 1 @@ -617,27 +500,31 @@ #define LWIP_NETIF_LOOPBACK 1 #define LWIP_USING_PING /* end of LwIP */ +/* end of TCP/IP */ /* Molink */ /* end of Molink */ -/* OTA */ +/* Protocols */ -/* Fota by CMIOT */ +/* CoAP */ -/* end of Fota by CMIOT */ -/* end of OTA */ +/* end of CoAP */ -/* Protocols */ +/* HTTP */ -/* LWM2M */ +/* httpclient-v1.1.0 */ -/* end of LWM2M */ +/* end of httpclient-v1.1.0 */ +/* end of HTTP */ -/* CoAP */ +/* LWM2M */ -/* end of CoAP */ +/* LWM2M-v1.0.0 */ + +/* end of LWM2M-v1.0.0 */ +/* end of LWM2M */ /* MQTT */ @@ -646,10 +533,6 @@ /* Websocket */ /* end of Websocket */ - -/* Httpclient */ - -/* end of Httpclient */ /* end of Protocols */ /* Socket */ @@ -657,105 +540,88 @@ #define NET_USING_BSD #define BSD_USING_LWIP /* end of Socket */ - -/* Tools */ - -/* end of Tools */ /* end of Network */ -/* Security */ - -/* end of Security */ - -/* Shell */ +/* Iotivity */ -#define OS_USING_SHELL -#define SHELL_TASK_NAME "tshell" -#define SHELL_TASK_PRIORITY 20 -#define SHELL_TASK_STACK_SIZE 4096 -#define SHELL_USING_HISTORY -#define SHELL_HISTORY_LINES 5 -#define SHELL_USING_DESCRIPTION -#define SHELL_CMD_SIZE 80 -#define SHELL_ARG_MAX 10 -/* end of Shell */ +/* end of Iotivity */ -/* FileSystem */ +/* OneJS */ -#define OS_USING_VFS -#define VFS_USING_WORKDIR -#define VFS_FILESYSTEMS_MAX 2 -#define VFS_FILESYSTEM_TYPES_MAX 2 -#define VFS_FD_MAX 16 -#define OS_USING_VFS_DEVFS -/* end of FileSystem */ +/* end of OneJS */ -/* GUI */ +/* Optparse */ -/* end of GUI */ +/* end of Optparse */ -/* OnePos */ +/* OTA */ -/* end of OnePos */ +/* end of OTA */ -/* Ramdisk */ +/* Position */ -/* end of Ramdisk */ +/* end of Position */ -/* Diagnose */ +/* PowerManager */ -/* end of Diagnose */ +/* end of PowerManager */ -/* U+ */ +/* Python */ -/* end of U+ */ -/* end of Components */ +/* end of Python */ -/* Thirdparty */ +/* Ramdisk */ -/* Character Conversion */ +/* end of Ramdisk */ -/* end of Character Conversion */ +/* Security */ -/* MicroPython */ -/* end of MicroPython */ +/* OneTLS */ -/* cJSON */ +/* end of OneTLS */ +/* end of Security */ -#define PKG_USING_CJSON -/* end of cJSON */ +/* Shell */ -/* Easyflash */ +#define OS_USING_SHELL +#define SHELL_TASK_NAME "tshell" +#define SHELL_TASK_PRIORITY 20 +#define SHELL_TASK_STACK_SIZE 4096 +#define SHELL_USING_HISTORY +#define SHELL_HISTORY_LINES 5 +#define SHELL_USING_DESCRIPTION +#define SHELL_CMD_SIZE 80 +#define SHELL_PROMPT_SIZE 256 +#define SHELL_ARG_MAX 10 +/* end of Shell */ -#define PKG_USING_EASYFLASH -#define PKG_EASYFLASH_ENV_SETTING_SIZE 1024 -#define PKG_EASYFLASH_ERASE_GRAN 4096 -#define PKG_EASYFLASH_START_ADDR 2088960 -/* end of Easyflash */ +/* SQL */ -/* Netutils */ +/* end of SQL */ -/* NTP */ +/* telnetd */ -/* end of NTP */ -/* end of Netutils */ +/* end of telnetd */ -/* ttsAisound */ +/* AI */ -/* end of ttsAisound */ +/* end of AI */ +/* end of Components */ -/* WebClient */ +/* Demos */ -/* end of WebClient */ -/* end of Thirdparty */ +/* Component demos */ -/* Boot Config */ +/* Camera web server */ -/* end of Boot Config */ +/* end of Camera web server */ +/* end of Component demos */ +/* end of Demos */ /* Debug */ +#define OS_DEBUG #define LOG_BUFF_SIZE_256 #define OS_LOG_BUFF_SIZE 256 /* end of Debug */ diff --git a/templates/bk7231n/osconfig.py b/templates/bk7231n/osconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..e653c5b33e4444ab723402acd54e19301fe335fd --- /dev/null +++ b/templates/bk7231n/osconfig.py @@ -0,0 +1,143 @@ +import os + +# toolchains options +ARCH = 'arm' +CPU = 'beken' +CROSS_TOOL = 'gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('OS_CC'): + CROSS_TOOL = os.getenv('OS_CC') +if os.getenv('OS_ROOT'): + OS_ROOT = os.getenv('OS_ROOT') + +# cross_tool provides the cross compiler +# COMPILER_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + COMPILER = 'gcc' + COMPILER_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + COMPILER = 'armcc' + # Notice: The installation path of armcc cannot have Chinese + COMPILER_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + COMPILER = 'iar' + COMPILER_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if CROSS_TOOL == 'gcc' and os.getenv('OS_EXEC_PATH'): + COMPILER_PATH = os.getenv('OS_EXEC_PATH') + +BUILD = 'release' + +if COMPILER == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + RESULT_SUFFIX = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=arm968e-s -marm -mthumb-interwork -marm -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -w -g ' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET oneos.bin\n' + SIZE + ' $TARGET \n' + +elif COMPILER == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + RESULT_SUFFIX = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --split_sections --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list oneos.map --strict' + CFLAGS += ' -I "' + COMPILER_PATH + '/ARM/ARMCC/include"' + LFLAGS += ' --libpath="' + COMPILER_PATH + '/ARM/ARMCC/lib"' + + #CFLAGS += ' -D__MICROLIB ' + #AFLAGS += ' --pd "__MICROLIB SETA 1" ' + #LFLAGS += ' --library_type=microlib ' + COMPILER_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output oneos.bin \nfromelf -z $TARGET' + +elif COMPILER == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + RESULT_SUFFIX = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + COMPILER_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + COMPILER_PATH = COMPILER_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET oneos.bin' diff --git a/templates/bk7231n/settings-gcc.yaml b/templates/bk7231n/settings-gcc.yaml index 8c804290c863e285a97b35f8e59f66f4d7bdebf9..9b01b04b338c61d73cf1acb7f9741b51df244a5f 100644 --- a/templates/bk7231n/settings-gcc.yaml +++ b/templates/bk7231n/settings-gcc.yaml @@ -1,19 +1,30 @@ # 编译选项（支持条件表达式） option: cflags: # General options that are passed to the C compiler (C only; not C++). - - ' -mcpu=arm968e-s -mthumb-interwork -mthumb -ffunction-sections -fdata-sections' - - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -mcpu=arm968e-s -marm -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O2 -gdwarf-2 -w -g ? {is_mode("O0")}' - ' -O2 ? {is_mode(''O2'')}' - ' -Os ? {is_mode(''Os'')}' cxxflags: # General options that are passed to the C++ compiler. - - ' -mcpu=arm968e-s -mthumb-interwork -mthumb -ffunction-sections -fdata-sections' - - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -mcpu=arm968e-s -marm -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O2 -gdwarf-2 -w -g ? {is_mode("O0")}' - ' -O2 ? {is_mode(''O2'')}' - ' -Os ? {is_mode(''Os'')}' asflags: # General options passed to the assembler. - ' -c' - - ' -mcpu=arm968e-s -mthumb-interwork -mthumb -ffunction-sections -fdata-sections' + - ' -mcpu=arm968e-s -w -marm -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections' - ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + - ' -gdwarf-2 ? {is_mode(''O0'')}' linkflags: # General user options passed to the linker. - - ' -mcpu=arm968e-s -mthumb-interwork -mthumb -ffunction-sections -fdata-sections' - - ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' \ No newline at end of file + - ' -mcpu=arm968e-s -w -marm -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections' + - ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + +# 构建前/后动作（支持条件表达式） +action: + postbuild: # 构建后处理 + - '$OBJCOPY -R .reserved_ram -O binary $TARGET oneos.bin' + - '$SIZE $TARGET' + prebuild: + - 'script:sys.path.append("$OS_ROOT" + "/drivers/hal/beken/scripts/");import prebuild;prebuild.prebuild("$PRO_ROOT")' \ No newline at end of file diff --git a/templates/cm32m4xxr-128/.config b/templates/cm32m4xxr-128/.config index 4813fd70d41efabed3b97b61d88509b5ab6c8e7b..33d95caeebac0a1c62580a87a06a2f215453c0ca 100644 --- a/templates/cm32m4xxr-128/.config +++ b/templates/cm32m4xxr-128/.config @@ -78,7 +78,7 @@ CONFIG_OS_USING_MEM_POOL=y # CONFIG_OS_USING_IPC_HOOK is not set # -# Diagnose +# Debug # # CONFIG_STACK_TRACE_EN is not set # CONFIG_OS_USING_CPU_MONITOR is not set @@ -88,7 +88,7 @@ CONFIG_OS_USING_MEM_POOL=y # # CONFIG_OS_USING_MEM_MONITOR is not set # end of Memory Monitor -# end of Diagnose +# end of Debug # end of Kernel # @@ -196,7 +196,7 @@ CONFIG_OS_USING_DMA_RAM=y CONFIG_OS_USING_SOFT_DMA=y CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y -CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT is not set # end of DMA # @@ -331,7 +331,7 @@ CONFIG_OS_USING_MTD=y # # CONFIG_OS_USING_NET_DEVICE is not set # CONFIG_OS_USING_WLAN is not set -# CONFIG_BSP_USING_AP6181 is not set +# CONFIG_BSP_USING_BK7231N is not set # end of NET # @@ -419,7 +419,7 @@ CONFIG_OS_USING_QSPI=y CONFIG_OS_USING_TIMER_DRIVER=y CONFIG_OS_USING_CLOCKSOURCE=y # CONFIG_OS_CLOCKSOURCE_SHOW is not set -# CONFIG_OS_USING_TIMEKEEPING is not set +CONFIG_OS_USING_TIMEKEEPING=y CONFIG_OS_CLOCKSOURCE_BEST="" CONFIG_OS_USING_CLOCKEVENT=y # CONFIG_OS_CLOCKEVENT_SHOW is not set @@ -477,12 +477,6 @@ CONFIG_OS_USING_WDG=y # CONFIG_OS_USING_DBOT is not set # end of DBoT -# -# WWD -# -# CONFIG_OS_USING_WWD is not set -# end of WWD - # # AMS # @@ -526,12 +520,6 @@ CONFIG_OS_USING_WDG=y # CONFIG_PKG_USING_ALI_IOTKIT is not set # end of Aliyun -# -# Amap -# -# CONFIG_AMAP_WEB_SERVICE is not set -# end of Amap - # # AWS # @@ -637,29 +625,6 @@ CONFIG_OS_GUI_INPUT_DEV_NAME="touch" # CONFIG_OS_USING_GUI_CMSIS is not set # end of GUI -# -# Industrial -# - -# -# CANOpen -# -# CONFIG_OS_USING_CANFESTIVAL is not set -# end of CANOpen - -# -# CoDeSys -# -# CONFIG_OS_USING_CODESYS is not set -# end of CoDeSys - -# -# ModBus -# -# CONFIG_OS_USING_UCMODBUS is not set -# end of ModBus -# end of Industrial - # # IoTjs # @@ -846,8 +811,30 @@ CONFIG_SHELL_ARG_MAX=10 # # CONFIG_TELNET_SERVER is not set # end of telnetd + +# +# AI +# +# CONFIG_OS_USING_UAI is not set +# end of AI # end of Components +# +# Demos +# + +# +# Component demos +# + +# +# Camera web server +# +# CONFIG_OS_USING_CAMERA_WEB_SERVER is not set +# end of Camera web server +# end of Component demos +# end of Demos + # # Debug # diff --git a/templates/cm32m4xxr-128/oneos_config.h b/templates/cm32m4xxr-128/oneos_config.h index 87b1de1099eb94f85ed9e6bbdedd5eea40ed8ba8..9e16057b8cf1d7ad6e2742fb7050cffff7d65bea 100644 --- a/templates/cm32m4xxr-128/oneos_config.h +++ b/templates/cm32m4xxr-128/oneos_config.h @@ -50,13 +50,13 @@ #define OS_USING_MEM_POOL /* end of Memory management */ -/* Diagnose */ +/* Debug */ /* Memory Monitor */ /* end of Memory Monitor */ -/* end of Diagnose */ +/* end of Debug */ /* end of Kernel */ /* C standard library adapter */ @@ -136,7 +136,6 @@ #define OS_USING_SOFT_DMA #define OS_SOFT_DMA_SUPPORT_NORMAL_MODE #define OS_SOFT_DMA_SUPPORT_CIRCLE_MODE -#define OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT /* end of DMA */ /* EEPROM */ @@ -273,6 +272,7 @@ #define OS_USING_TIMER_DRIVER #define OS_USING_CLOCKSOURCE +#define OS_USING_TIMEKEEPING #define OS_CLOCKSOURCE_BEST "" #define OS_USING_CLOCKEVENT #define OS_CLOCKEVENT_BEST "" @@ -313,10 +313,6 @@ /* end of DBoT */ -/* WWD */ - -/* end of WWD */ - /* AMS */ /* end of AMS */ @@ -345,10 +341,6 @@ /* end of Aliyun */ -/* Amap */ - -/* end of Amap */ - /* AWS */ /* end of AWS */ @@ -418,21 +410,6 @@ #define OS_GUI_INPUT_DEV_NAME "touch" /* end of GUI */ -/* Industrial */ - -/* CANOpen */ - -/* end of CANOpen */ - -/* CoDeSys */ - -/* end of CoDeSys */ - -/* ModBus */ - -/* end of ModBus */ -/* end of Industrial */ - /* IoTjs */ /* end of IoTjs */ @@ -557,8 +534,22 @@ /* telnetd */ /* end of telnetd */ + +/* AI */ + +/* end of AI */ /* end of Components */ +/* Demos */ + +/* Component demos */ + +/* Camera web server */ + +/* end of Camera web server */ +/* end of Component demos */ +/* end of Demos */ + /* Debug */ #define OS_DEBUG diff --git a/templates/configs/Kconfig b/templates/configs/Kconfig index de7729dedb2fe2432e26fc205730740c78f8fe1c..8e25cd2e8dccb5ef02961a60aeaee976e3545a4f 100644 --- a/templates/configs/Kconfig +++ b/templates/configs/Kconfig @@ -41,8 +41,8 @@ choice config MANUFACTOR_CSKY bool "CSKY" - #config MANUFACTOR_BEKEN - # bool "BEKEN" + config MANUFACTOR_BEKEN + bool "BEKEN" config MANUFACTOR_APM32 bool "APM32" diff --git a/templates/configs/SConscript b/templates/configs/SConscript index 72e4279db184b8796f19ed7ff0b0029afadc5017..871f4297c70cd27f430cc6d71e7f8265453f7749 100644 --- a/templates/configs/SConscript +++ b/templates/configs/SConscript @@ -37,6 +37,7 @@ inq_table = {} inq_table['MANUFACTOR_STM32'] = 'st' inq_table['MANUFACTOR_GD32'] = 'gd' inq_table['MANUFACTOR_GD32V'] = 'gd32v' +inq_table['MANUFACTOR_NATIONSTECH'] = 'nationstech' inq_table['MANUFACTOR_NXP'] = 'nxp' inq_table['MANUFACTOR_HDSC'] = 'hdsc' inq_table['MANUFACTOR_CMIOT'] = 'cmiot' diff --git a/templates/configs/beken/SConscript b/templates/configs/beken/SConscript index d39ee2cecf7c2ba8a7512069d0436316eb543f31..3370b53a8f738116af3d3bc2ba25b4063756d1e3 100644 --- a/templates/configs/beken/SConscript +++ b/templates/configs/beken/SConscript @@ -4,7 +4,7 @@ import importlib import importlib.util inq_table = {} -inq_table['SERIES_NRF52'] = 'nrf52' +inq_table['SERIES_BK72'] = 'bk72' def soc_type_inq(g): for inq in inq_table: diff --git a/templates/configs/beken/bk72/Kconfig b/templates/configs/beken/bk72/Kconfig index d023f1e3585013f252e0d77977282248f9f5558c..4af0ea401e1dd47dec5d09c2e8d70fef7be9cfe5 100644 --- a/templates/configs/beken/bk72/Kconfig +++ b/templates/configs/beken/bk72/Kconfig @@ -5,7 +5,7 @@ choice Select the device in BK72 config MODEL_BK7231 - bool "Bk7231" + bool "bk7231" endchoice if MODEL_BK7231 diff --git a/templates/configs/beken/bk72/bk7231n/Kconfig b/templates/configs/beken/bk72/bk7231n/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..823d2c4181d6d9339103debeba7bbe7107afed2e --- /dev/null +++ b/templates/configs/beken/bk72/bk7231n/Kconfig @@ -0,0 +1,9 @@ +choice + prompt "|------SUB MODEL" + default TEMP_bk7231n + help + Select the device in bk7231 + + config TEMP_bk7231n + bool "bk7231n" +endchoice diff --git a/templates/configs/beken/bk72/bk7231n/SConscript b/templates/configs/beken/bk72/bk7231n/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..d900df17359bcfab470d8aa41bb85e9df6b98288 --- /dev/null +++ b/templates/configs/beken/bk72/bk7231n/SConscript @@ -0,0 +1,18 @@ +import os +import sys +import importlib +import importlib.util + + + +def soc_type_inq(g): + target_path = None + + loader = importlib.machinery.SourceFileLoader(os.path.basename(target_script), target_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.template(g) + return target_path + + diff --git a/templates/configs/nationstech/Kconfig b/templates/configs/nationstech/Kconfig index 3af369525704039e57b30ebff9671b31222503cc..f8d4a9c30a8fc9ebf2c023609fb235759c38d36c 100644 --- a/templates/configs/nationstech/Kconfig +++ b/templates/configs/nationstech/Kconfig @@ -1,13 +1,34 @@ choice prompt "|--SERIES" - default SERIES_N32G4XX + default SERIES_N32G45X help Select the device in N32 - - config SERIES_N32G4XX - bool "N32G4XX" + + config SERIES_N32G43X + bool "N32G43X" + + config SERIES_N32G45X + bool "N32G45X" + + config SERIES_N32L40X + bool "N32L40X" + + config SERIES_N32L43X + bool "N32L43X" endchoice -if SERIES_N32G4XX - source "$OS_ROOT/templates/configs/nationstech/n32g4xx/Kconfig" +if SERIES_N32G43X + source "$OS_ROOT/templates/configs/nationstech/n32g43x/Kconfig" +endif + +if SERIES_N32G45X + source "$OS_ROOT/templates/configs/nationstech/n32g45x/Kconfig" +endif + +if SERIES_N32L40X + source "$OS_ROOT/templates/configs/nationstech/n32l40x/Kconfig" +endif + +if SERIES_N32L43X + source "$OS_ROOT/templates/configs/nationstech/n32l43x/Kconfig" endif diff --git a/templates/configs/nationstech/SConscript b/templates/configs/nationstech/SConscript index f52ab00cb48eba854e156bcea4a664ab7b78f52b..49dd580dc2c803c9fef0e70185887ff978b08fee 100644 --- a/templates/configs/nationstech/SConscript +++ b/templates/configs/nationstech/SConscript @@ -4,7 +4,10 @@ import importlib import importlib.util inq_table = {} -inq_table['SERIES_N32G4XX'] = 'n32g4xx' +inq_table['SERIES_N32G43X'] = 'n32g43x' +inq_table['SERIES_N32G45X'] = 'n32g45x' +inq_table['SERIES_N32L40X'] = 'n32l40x' +inq_table['SERIES_N32L43X'] = 'n32l43x' def soc_type_inq(g): for inq in inq_table: diff --git a/templates/configs/nationstech/n32g43x/Kconfig b/templates/configs/nationstech/n32g43x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..3b03daceaef2975371dd13531661772ca5a3c484 --- /dev/null +++ b/templates/configs/nationstech/n32g43x/Kconfig @@ -0,0 +1,14 @@ +choice + prompt "|----MODEL" + default MODEL_N32G435 + help + Select the device in N32G43X + + config MODEL_N32G435 + bool "N32G435" + +endchoice + +if MODEL_N32G435 + source "$OS_ROOT/templates/configs/nationstech/n32g43x/n32g435/Kconfig" +endif diff --git a/templates/configs/nationstech/n32g43x/SConscript b/templates/configs/nationstech/n32g43x/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3e3525e0aa6462d10ade5ae705615dd6190eaa27 --- /dev/null +++ b/templates/configs/nationstech/n32g43x/SConscript @@ -0,0 +1,32 @@ +import os +import sys +import importlib +import importlib.util + + +inq_table = {} +inq_table['MODEL_N32G435'] = 'n32g435' + + +def soc_type_inq(g): + for inq in inq_table: + if inq not in g: + continue + + print(inq) + + realdir = os.path.dirname(os.path.realpath(__file__)) + + sub_path = os.path.join(realdir, inq_table[inq]) + sub_script = os.path.join(sub_path, "SConscript") + + loader = importlib.machinery.SourceFileLoader('SConscript', sub_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.soc_type_inq(g) + + return target_path + + return None + diff --git a/templates/configs/nxp/imxrt10xx/imxrt1064/Kconfig b/templates/configs/nationstech/n32g43x/n32g435/Kconfig similarity index 30% rename from templates/configs/nxp/imxrt10xx/imxrt1064/Kconfig rename to templates/configs/nationstech/n32g43x/n32g435/Kconfig index 34b9fa0361fd9278b3c71306529ea8dbacbe960e..de46b60504e52cbb03e00c9ebe26181a4fc39f68 100644 --- a/templates/configs/nxp/imxrt10xx/imxrt1064/Kconfig +++ b/templates/configs/nationstech/n32g43x/n32g435/Kconfig @@ -1,10 +1,10 @@ choice prompt "|------SUB MODEL" - default TEMP_imxrt1064-nxp-evk + default TEMP_n32g435rbl7-1616n help - Select the device in IMXRT1064 + Select the device in N32G435 - config TEMP_imxrt1064-nxp-evk - bool "imxrt1064-nxp-evk" - + config TEMP_n32g435rbl7-1616n + bool "N32G435RBL7-1616N" + endchoice diff --git a/templates/configs/nxp/imxrt10xx/imxrt1064/SConscript b/templates/configs/nationstech/n32g43x/n32g435/SConscript similarity index 86% rename from templates/configs/nxp/imxrt10xx/imxrt1064/SConscript rename to templates/configs/nationstech/n32g43x/n32g435/SConscript index 4a39d1ef46e05f050af9013e8f16c0aa2cfcc62f..8d71f60e5520665ce76c81456c48f7d1308b255b 100644 --- a/templates/configs/nxp/imxrt10xx/imxrt1064/SConscript +++ b/templates/configs/nationstech/n32g43x/n32g435/SConscript @@ -3,7 +3,7 @@ import sys import importlib import importlib.util -template_dir = "../templates/nxp-common" +template_dir = "../templates/n32g43x-common/" def soc_type_inq(g): target_path = None @@ -15,4 +15,4 @@ def soc_type_inq(g): loader.exec_module(mod) target_path = mod.template(template_dir, g) - return target_path \ No newline at end of file + return target_path diff --git a/templates/configs/nationstech/n32g4xx/Kconfig b/templates/configs/nationstech/n32g45x/Kconfig similarity index 62% rename from templates/configs/nationstech/n32g4xx/Kconfig rename to templates/configs/nationstech/n32g45x/Kconfig index ddbb0f02fbd6899f68ccb9d4211fb7603afb4327..5caa41147e8a05a831eef334f4cc752d47738aab 100644 --- a/templates/configs/nationstech/n32g4xx/Kconfig +++ b/templates/configs/nationstech/n32g45x/Kconfig @@ -2,7 +2,7 @@ choice prompt "|----MODEL" default MODEL_N32G452 help - Select the device in N32G4XX + Select the device in N32G45X config MODEL_N32G452 bool "N32G452" @@ -10,5 +10,5 @@ choice endchoice if MODEL_N32G452 - source "$OS_ROOT/templates/configs/nationstech/n32g4xx/n32g452/Kconfig" + source "$OS_ROOT/templates/configs/nationstech/n32g45x/n32g452/Kconfig" endif diff --git a/templates/configs/nationstech/n32g4xx/SConscript b/templates/configs/nationstech/n32g45x/SConscript similarity index 100% rename from templates/configs/nationstech/n32g4xx/SConscript rename to templates/configs/nationstech/n32g45x/SConscript diff --git a/templates/configs/nationstech/n32g4xx/n32g452/Kconfig b/templates/configs/nationstech/n32g45x/n32g452/Kconfig similarity index 100% rename from templates/configs/nationstech/n32g4xx/n32g452/Kconfig rename to templates/configs/nationstech/n32g45x/n32g452/Kconfig diff --git a/templates/configs/nationstech/n32g4xx/n32g452/SConscript b/templates/configs/nationstech/n32g45x/n32g452/SConscript similarity index 100% rename from templates/configs/nationstech/n32g4xx/n32g452/SConscript rename to templates/configs/nationstech/n32g45x/n32g452/SConscript diff --git a/templates/configs/nationstech/n32l40x/Kconfig b/templates/configs/nationstech/n32l40x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..37ba6143901a56b201c3b6332d2d4f74c076e8e9 --- /dev/null +++ b/templates/configs/nationstech/n32l40x/Kconfig @@ -0,0 +1,14 @@ +choice + prompt "|----MODEL" + default MODEL_N32L406 + help + Select the device in N32L40X + + config MODEL_N32L406 + bool "N32L406" + +endchoice + +if MODEL_N32L406 + source "$OS_ROOT/templates/configs/nationstech/n32l40x/n32l406/Kconfig" +endif diff --git a/templates/configs/nationstech/n32l40x/SConscript b/templates/configs/nationstech/n32l40x/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..62f7150fb63499104d2fa216b4e15df54ab8172c --- /dev/null +++ b/templates/configs/nationstech/n32l40x/SConscript @@ -0,0 +1,32 @@ +import os +import sys +import importlib +import importlib.util + + +inq_table = {} +inq_table['MODEL_N32L406'] = 'n32l406' + + +def soc_type_inq(g): + for inq in inq_table: + if inq not in g: + continue + + print(inq) + + realdir = os.path.dirname(os.path.realpath(__file__)) + + sub_path = os.path.join(realdir, inq_table[inq]) + sub_script = os.path.join(sub_path, "SConscript") + + loader = importlib.machinery.SourceFileLoader('SConscript', sub_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.soc_type_inq(g) + + return target_path + + return None + diff --git a/templates/configs/nationstech/n32l40x/n32l406/Kconfig b/templates/configs/nationstech/n32l40x/n32l406/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..6c713c44344a0e9064bd75bc059e09e27a998530 --- /dev/null +++ b/templates/configs/nationstech/n32l40x/n32l406/Kconfig @@ -0,0 +1,10 @@ +choice + prompt "|------SUB MODEL" + default TEMP_n32l406rbl7-1616n + help + Select the device in N32L406 + + config TEMP_n32l406rbl7-1616n + bool "N32L406RBL7-1616N" + +endchoice diff --git a/templates/configs/nationstech/n32l40x/n32l406/SConscript b/templates/configs/nationstech/n32l40x/n32l406/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..23008de8646a72803dbe05fbad896613978ce27e --- /dev/null +++ b/templates/configs/nationstech/n32l40x/n32l406/SConscript @@ -0,0 +1,18 @@ +import os +import sys +import importlib +import importlib.util + +template_dir = "../templates/n32l40x-common/" + +def soc_type_inq(g): + target_path = None + + target_script = "../scripts/generate.py" + loader = importlib.machinery.SourceFileLoader(os.path.basename(target_script), target_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.template(template_dir, g) + + return target_path diff --git a/templates/configs/nationstech/n32l43x/Kconfig b/templates/configs/nationstech/n32l43x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..ad1e1d41aa6ce3b892c8b3ef8ffb80b64b38632c --- /dev/null +++ b/templates/configs/nationstech/n32l43x/Kconfig @@ -0,0 +1,14 @@ +choice + prompt "|----MODEL" + default MODEL_N32L436 + help + Select the device in N32L43X + + config MODEL_N32L436 + bool "N32L436" + +endchoice + +if MODEL_N32L436 + source "$OS_ROOT/templates/configs/nationstech/n32l43x/n32l436/Kconfig" +endif diff --git a/templates/configs/nationstech/n32l43x/SConscript b/templates/configs/nationstech/n32l43x/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..50d30b09f7595c5d2f0c266691f564bcc8427ad7 --- /dev/null +++ b/templates/configs/nationstech/n32l43x/SConscript @@ -0,0 +1,32 @@ +import os +import sys +import importlib +import importlib.util + + +inq_table = {} +inq_table['MODEL_N32L436'] = 'n32l436' + + +def soc_type_inq(g): + for inq in inq_table: + if inq not in g: + continue + + print(inq) + + realdir = os.path.dirname(os.path.realpath(__file__)) + + sub_path = os.path.join(realdir, inq_table[inq]) + sub_script = os.path.join(sub_path, "SConscript") + + loader = importlib.machinery.SourceFileLoader('SConscript', sub_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.soc_type_inq(g) + + return target_path + + return None + diff --git a/templates/configs/nationstech/n32l43x/n32l436/Kconfig b/templates/configs/nationstech/n32l43x/n32l436/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..dc5d271e9f60c840b1e4fde743ae16833ee6b66d --- /dev/null +++ b/templates/configs/nationstech/n32l43x/n32l436/Kconfig @@ -0,0 +1,10 @@ +choice + prompt "|------SUB MODEL" + default TEMP_n32l436rbl7-1616n + help + Select the device in N32L436 + + config TEMP_n32l436rbl7-1616n + bool "N32L436RBL7-1616N" + +endchoice diff --git a/templates/configs/nationstech/n32l43x/n32l436/SConscript b/templates/configs/nationstech/n32l43x/n32l436/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fafd942736054edc73872455baaae636bdaf9862 --- /dev/null +++ b/templates/configs/nationstech/n32l43x/n32l436/SConscript @@ -0,0 +1,18 @@ +import os +import sys +import importlib +import importlib.util + +template_dir = "../templates/n32l43x-common/" + +def soc_type_inq(g): + target_path = None + + target_script = "../scripts/generate.py" + loader = importlib.machinery.SourceFileLoader(os.path.basename(target_script), target_script) + spec = importlib.util.spec_from_loader(loader.name, loader) + mod = importlib.util.module_from_spec(spec) + loader.exec_module(mod) + target_path = mod.template(template_dir, g) + + return target_path diff --git a/templates/configs/nxp/imxrt10xx/Kconfig b/templates/configs/nxp/imxrt10xx/Kconfig index 908094395f4c88e53a9599c98099478b55474abe..b1060be963f001c2ef7b29a1266539dd6a16f416 100644 --- a/templates/configs/nxp/imxrt10xx/Kconfig +++ b/templates/configs/nxp/imxrt10xx/Kconfig @@ -9,9 +9,6 @@ choice config MODEL_IMXRT1060 bool "IMXRT1060" - - config MODEL_IMXRT1064 - bool "IMXRT1064" endchoice if MODEL_IMXRT1050 @@ -21,8 +18,4 @@ endif if MODEL_IMXRT1060 source "$OS_ROOT/templates/configs/nxp/imxrt10xx/imxrt1060/Kconfig" endif - -if MODEL_IMXRT1064 - source "$OS_ROOT/templates/configs/nxp/imxrt10xx/imxrt1064/Kconfig" -endif \ No newline at end of file diff --git a/templates/configs/nxp/imxrt10xx/SConscript b/templates/configs/nxp/imxrt10xx/SConscript index c9f453d88586e792bb566b2ea9fb5b573e2592fc..650083007346299f7cb16b6a7eb8d276194a7a99 100644 --- a/templates/configs/nxp/imxrt10xx/SConscript +++ b/templates/configs/nxp/imxrt10xx/SConscript @@ -6,7 +6,6 @@ import importlib.util inq_table = {} inq_table['SERIES_NXP_IMXRT1050'] = 'imxrt1050' inq_table['SERIES_NXP_IMXRT1060'] = 'imxrt1060' -inq_table['SERIES_NXP_IMXRT1020'] = 'imxrt1020' def soc_type_inq(g): for inq in inq_table: diff --git a/templates/configs/samsung/SConscript b/templates/configs/samsung/SConscript index 6bd9c3c08e676b9ec30509c9f616995e167edfba..103d689598d6d713d54df42642eecdb4efa6d40a 100644 --- a/templates/configs/samsung/SConscript +++ b/templates/configs/samsung/SConscript @@ -4,7 +4,7 @@ import importlib import importlib.util inq_table = {} -inq_table['SERIES_Exynos4412'] = 'Exynos4412' +inq_table['SERIES_Exynos'] = 'exynos' def soc_type_inq(g): for inq in inq_table: diff --git a/templates/configs/wch/SConscript b/templates/configs/wch/SConscript index 4396bfbebb83335f43e1138d1bcf6f79a1146226..64dc55281dcf27a3fb552ab67c86de25ae5e650a 100644 --- a/templates/configs/wch/SConscript +++ b/templates/configs/wch/SConscript @@ -4,7 +4,8 @@ import importlib import importlib.util inq_table = {} -inq_table['SERIES_CH32V3'] = 'v3' +inq_table['SERIES_CH32V'] = 'ch32v' +inq_table['SERIES_CH5'] = 'ch5xx' def soc_type_inq(g): for inq in inq_table: diff --git a/templates/itop-4412/Kconfig b/templates/itop-4412/Kconfig index 38c269dc03fe6f67ffb95a74d0892d9e04486265..4c584bb02ac035347b6360a037a7eec7dc4b6463 100644 --- a/templates/itop-4412/Kconfig +++ b/templates/itop-4412/Kconfig @@ -10,6 +10,7 @@ config BOARD_ITOP_4412 bool select ARCH_ARM_V7_EXYNOS4 select SOC_FAMILY_EXYNOS4412 + select OS_BOARD_SUPPORT_SMP default y source "$OS_ROOT/Kconfig" diff --git a/templates/n32g435rbl7-1616n/.config b/templates/n32g435rbl7-1616n/.config new file mode 100644 index 0000000000000000000000000000000000000000..f493b51068c8dc5f1ac6e0a85488951b9b26b666 --- /dev/null +++ b/templates/n32g435rbl7-1616n/.config @@ -0,0 +1,800 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) +CONFIG_BOARD_N32L406RBL7_MXIO_1616N=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# Kernel +# +# CONFIG_OS_NAME_MAX_7 is not set +CONFIG_OS_NAME_MAX_15=y +# CONFIG_OS_NAME_MAX_31 is not set +CONFIG_OS_NAME_MAX=15 +# CONFIG_OS_TASK_PRIORITY_8 is not set +# CONFIG_OS_TASK_PRIORITY_16 is not set +CONFIG_OS_TASK_PRIORITY_32=y +# CONFIG_OS_TASK_PRIORITY_64 is not set +# CONFIG_OS_TASK_PRIORITY_128 is not set +# CONFIG_OS_TASK_PRIORITY_256 is not set +CONFIG_OS_TASK_PRIORITY_MAX=32 +CONFIG_OS_TICK_PER_SECOND=1000 +CONFIG_OS_SCHEDULE_TIME_SLICE=10 +CONFIG_OS_USING_OVERFLOW_CHECK=y +# CONFIG_OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK is not set +# CONFIG_OS_USING_TASK_HOOK is not set +# CONFIG_OS_USING_ASSERT is not set +# CONFIG_OS_USING_KERNEL_LOCK_CHECK is not set +# CONFIG_OS_USING_SAFETY_MECHANISM is not set +CONFIG_OS_USING_KERNEL_DEBUG=y +# CONFIG_KLOG_GLOBAL_LEVEL_ERROR is not set +CONFIG_KLOG_GLOBAL_LEVEL_WARNING=y +# CONFIG_KLOG_GLOBAL_LEVEL_INFO is not set +# CONFIG_KLOG_GLOBAL_LEVEL_DEBUG is not set +CONFIG_KLOG_GLOBAL_LEVEL=1 +CONFIG_KLOG_USING_COLOR=y +CONFIG_KLOG_WITH_FUNC_LINE=y +CONFIG_OS_MAIN_TASK_STACK_SIZE=2048 +CONFIG_OS_IDLE_TASK_STACK_SIZE=512 +CONFIG_OS_RECYCLE_TASK_STACK_SIZE=512 +CONFIG_OS_USING_TIMER=y +CONFIG_OS_TIMER_TASK_STACK_SIZE=512 +CONFIG_OS_TIMER_POWER=3 +# CONFIG_OS_TIMER_SORT is not set +CONFIG_OS_USING_WORKQUEUE=y +CONFIG_OS_USING_SYSTEM_WORKQUEUE=y +CONFIG_OS_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_OS_SYSTEM_WORKQUEUE_PRIORITY=0 + +# +# Inter-task communication and synchronization +# +CONFIG_OS_USING_MUTEX=y +# CONFIG_OS_USING_SPINLOCK_CHECK is not set +CONFIG_OS_USING_SEMAPHORE=y +# CONFIG_OS_SEM_WAIT_HOOK is not set +# CONFIG_OS_SEM_POST_HOOK is not set +# CONFIG_OS_USING_EVENT is not set +# CONFIG_OS_USING_MESSAGEQUEUE is not set +# CONFIG_OS_USING_MAILBOX is not set +# end of Inter-task communication and synchronization + +# +# Memory management +# +CONFIG_OS_USING_SYS_HEAP=y +CONFIG_OS_USING_MEM_HEAP=y +CONFIG_OS_USING_ALG_FIRSTFIT=y +# CONFIG_OS_USING_ALG_BUDDY is not set +# CONFIG_OS_USING_MEM_TRACE is not set +# CONFIG_OS_USING_MEM_POOL is not set +# end of Memory management + +# CONFIG_OS_USING_IPC_TRACE is not set +# CONFIG_OS_USING_IPC_HOOK is not set +# end of Kernel + +# +# C standard library adapter +# +CONFIG_OS_USING_LIBC_ADAPTER=y +CONFIG_OS_USING_NEWLIB_ADAPTER=y +CONFIG_OS_USING_ARMCCLIB_ADAPTER=y +# end of C standard library adapter + +# +# Osal +# + +# +# POSIX compatibility layer +# +# CONFIG_OS_USING_PTHREADS is not set +# end of POSIX compatibility layer + +# +# RT-Thread compatibility layer +# +# CONFIG_OS_USING_RTTHREAD_API_V3_1_3 is not set +# end of RT-Thread compatibility layer + +# +# CMSIS compatibility layer +# +# CONFIG_OS_USING_CMSIS_RTOS2_API_V2_1_2 is not set +# end of CMSIS compatibility layer + +# +# FreeRTOS compatibility layer +# +# CONFIG_OS_USING_FREERTOS_API_V10_4_3 is not set +# end of FreeRTOS compatibility layer + +# +# C++ Features +# +# CONFIG_OS_USING_CPLUSPLUS is not set +# end of C++ Features +# end of Osal + +# +# Drivers +# +CONFIG_OS_USING_DEVICE=y +CONFIG_OS_USING_DEVICE_NOTIFY=y +# CONFIG_OS_DEVICE_SUPPORT_PLUG is not set + +# +# Audio +# +# CONFIG_OS_USING_AUDIO is not set +# end of Audio + +# +# BLOCK +# +CONFIG_OS_USING_BLOCK=y +# end of BLOCK + +# +# Boot +# + +# +# CORTEX-M Boot +# +CONFIG_BSP_INCLUDE_VECTOR_TABLE=y +# CONFIG_BSP_BOOT_OPTION is not set +# end of CORTEX-M Boot +# end of Boot + +# +# CAN +# +# CONFIG_OS_USING_CAN is not set +# end of CAN + +# +# CONSOLE +# +CONFIG_OS_USING_CONSOLE=y +CONFIG_OS_CONSOLE_DEVICE_NAME="usart1" +# end of CONSOLE + +# +# DMA +# +CONFIG_OS_USING_DMA=y +CONFIG_OS_USING_DMA_RAM=y +CONFIG_OS_USING_SOFT_DMA=y +CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# end of DMA + +# +# EEPROM +# +# CONFIG_OS_EEPROM_SUPPORT is not set +# end of EEPROM + +# +# FAL +# +CONFIG_OS_USING_FAL=y +# CONFIG_OS_FAL_RAM is not set +# end of FAL + +# +# Graphic +# +# CONFIG_OS_USING_GRAPHIC is not set +# end of Graphic + +# +# HAL +# +CONFIG_MANUFACTOR_NATIONSTECH=y +CONFIG_SERIES_N32L40X=y +CONFIG_SOC_N32L406RBL7=y +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_USART=y +CONFIG_BSP_USING_ONCHIP_FLASH=y +CONFIG_BSP_USING_TIMER=y +# end of HAL + +# +# HwCrypto +# +# CONFIG_OS_USING_HWCRYPTO is not set +# end of HwCrypto + +# +# I2C +# +# CONFIG_OS_USING_I2C is not set +# end of I2C + +# +# Infrared +# +# CONFIG_OS_USING_INFRARED is not set +# end of Infrared + +# +# LPMGR +# +# CONFIG_OS_USING_LPMGR is not set +# end of LPMGR + +# +# MISC +# +CONFIG_OS_USING_PUSH_BUTTON=y +CONFIG_OS_USING_LED=y +# CONFIG_OS_USING_BUZZER is not set +# CONFIG_OS_USING_ADC is not set +# CONFIG_OS_USING_DAC is not set +# CONFIG_OS_USING_PWM is not set +# CONFIG_OS_USING_INPUT_CAPTURE is not set +# CONFIG_OS_USING_PULSE_ENCODER is not set +# end of MISC + +# +# MTD +# +# CONFIG_OS_USING_MTD is not set +# end of MTD + +# +# NAND +# +# CONFIG_OS_USING_NAND is not set +# end of NAND + +# +# NET +# +# CONFIG_OS_USING_NET_DEVICE is not set +# CONFIG_OS_USING_WLAN is not set +# CONFIG_BSP_USING_AP6181 is not set +# end of NET + +# +# PIN +# +CONFIG_OS_USING_PIN=y +CONFIG_OS_PIN_MAX_CHIP=1 +# CONFIG_BSP_USING_PIN_PCF8574 is not set +# end of PIN + +# +# RTC +# +# CONFIG_OS_USING_RTC is not set +# end of RTC + +# +# SDIO +# +# CONFIG_OS_USING_SDIO is not set +# end of SDIO + +# +# Sensors +# +# CONFIG_OS_USING_SENSOR is not set +# end of Sensors + +# +# Serial +# +CONFIG_OS_USING_SERIAL=y +CONFIG_OS_SERIAL_DELAY_CLOSE=y +CONFIG_OS_SERIAL_RX_BUFSZ=64 +CONFIG_OS_SERIAL_TX_BUFSZ=64 + +# +# posix serial +# +# CONFIG_OS_USING_POSIX_SERIAL is not set +# end of posix serial + +# +# rtt uart +# +# CONFIG_OS_USING_RTT is not set +# end of rtt uart +# end of Serial + +# +# SFLASH +# +# CONFIG_OS_SFLASH_SUPPORT is not set +# end of SFLASH + +# +# SN +# +# CONFIG_OS_USING_SN is not set +# end of SN + +# +# SPI +# +# CONFIG_OS_USING_SPI is not set +# CONFIG_BSP_USING_ENC28J60 is not set +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_NRF24L01 is not set +# CONFIG_BSP_USING_TPS_1 is not set +# CONFIG_OS_USING_SFUD is not set +# end of SPI + +# +# Timer +# +CONFIG_OS_USING_TIMER_DRIVER=y +CONFIG_OS_USING_CLOCKSOURCE=y +# CONFIG_OS_CLOCKSOURCE_SHOW is not set +# CONFIG_OS_USING_TIMEKEEPING is not set +CONFIG_OS_CLOCKSOURCE_BEST="" +# CONFIG_OS_USING_CLOCKEVENT is not set +# CONFIG_OS_USING_HRTIMER is not set + +# +# cortex-m & riscv hardware timer config +# +CONFIG_OS_USING_SYSTICK_FOR_KERNEL_TICK=y +# CONFIG_OS_USING_SYSTICK_FOR_CLOCKSOURCE is not set +CONFIG_OS_USING_DWT_FOR_CLOCKSOURCE=y +# end of cortex-m & riscv hardware timer config +# end of Timer + +# +# TinyUSB +# +# CONFIG_OS_USING_TINYUSB is not set +# end of TinyUSB + +# +# Touch +# +# CONFIG_OS_USING_TOUCH is not set +# end of Touch + +# +# USB +# +# CONFIG_OS_USING_USB_DEVICE is not set +# CONFIG_OS_USING_USB_HOST is not set +# end of USB + +# +# WDG +# +# CONFIG_OS_USING_WDG is not set +# end of WDG +# end of Drivers + +# +# Components +# + +# +# MicroPython +# +# CONFIG_PKG_USING_MICROPYTHON is not set +# end of MicroPython + +# +# WWD +# +# CONFIG_OS_USING_WWD is not set +# end of WWD + +# +# AMS +# +# CONFIG_PKG_USING_AMS is not set +# end of AMS + +# +# Atest +# +# CONFIG_OS_USING_ATEST is not set +# end of Atest + +# +# BLE +# +# CONFIG_OS_USING_BLE is not set +# end of BLE + +# +# cJSON +# +# CONFIG_PKG_USING_CJSON is not set +# end of cJSON + +# +# CLI +# +# CONFIG_OS_USING_CLI is not set +# end of CLI + +# +# Cloud +# + +# +# Aliyun +# +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# end of Aliyun + +# +# AWS +# +# CONFIG_PKG_USING_AWS_IOT is not set +# end of AWS + +# +# Baidu +# +# CONFIG_BAIDUIOT is not set +# end of Baidu + +# +# CTWing +# + +# +# MQTT +# +# CONFIG_OS_USING_CTWING_MQTT is not set +# end of MQTT +# end of CTWing + +# +# Huawei +# +# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set +# end of Huawei + +# +# OneNET +# + +# +# MQTT kit +# +# CONFIG_OS_USING_ONENET_MQTTS is not set +# end of MQTT kit + +# +# NB-IoT kit +# +# CONFIG_OS_USING_ONENET_NBIOT is not set +# end of NB-IoT kit + +# +# EDP +# +# CONFIG_OS_USING_ONENET_EDP is not set +# end of EDP +# end of OneNET +# end of Cloud + +# +# CMS +# +CONFIG_CMS_LITE=y +# CONFIG_CMS_STD is not set + +# +# CMS Connect +# +# CONFIG_USING_CMS_CONNECT is not set +# end of CMS Connect + +# +# CMS ID +# +# CONFIG_CMS_USING_ID is not set +# end of CMS ID +# end of CMS + +# +# Diagnose +# +# CONFIG_STACK_TRACE_EN is not set +# CONFIG_OS_USING_CPU_MONITER is not set +# CONFIG_OS_USING_WIRESHARK_DUMP is not set + +# +# eCoreDump +# +# CONFIG_USING_ECORE_DUMP is not set +# end of eCoreDump + +# +# Memory Monitor +# +# CONFIG_OS_USING_MEM_MONITOR is not set +# end of Memory Monitor +# end of Diagnose + +# +# Dlog +# +CONFIG_OS_USING_DLOG=y +# CONFIG_DLOG_PRINT_LVL_E is not set +CONFIG_DLOG_PRINT_LVL_W=y +# CONFIG_DLOG_PRINT_LVL_I is not set +# CONFIG_DLOG_PRINT_LVL_D is not set +CONFIG_DLOG_GLOBAL_PRINT_LEVEL=4 +# CONFIG_DLOG_COMPILE_LVL_E is not set +# CONFIG_DLOG_COMPILE_LVL_W is not set +# CONFIG_DLOG_COMPILE_LVL_I is not set +CONFIG_DLOG_COMPILE_LVL_D=y +CONFIG_DLOG_COMPILE_LEVEL=7 +CONFIG_DLOG_USING_ISR_LOG=y +CONFIG_DLOG_USING_FILTER=y +CONFIG_DLOG_USING_ASYNC_OUTPUT=y +CONFIG_DLOG_ASYNC_OUTPUT_BUF_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_PRIORITY=20 +# CONFIG_DLOG_USING_SYSLOG is not set + +# +# Log format +# +# CONFIG_DLOG_OUTPUT_FLOAT is not set +CONFIG_DLOG_WITH_FUNC_LINE=y +CONFIG_DLOG_USING_COLOR=y +CONFIG_DLOG_OUTPUT_TIME_INFO=y +# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set +# end of Log format + +# +# Dlog backend option +# +CONFIG_DLOG_BACKEND_USING_CONSOLE=y +# CONFIG_DLOG_BACKEND_USING_FILESYSTEM is not set +# end of Dlog backend option +# end of Dlog + +# +# Easyflash +# +# CONFIG_PKG_USING_EASYFLASH is not set +# end of Easyflash + +# +# FileSystem +# +# CONFIG_OS_USING_VFS is not set +# end of FileSystem + +# +# GUI +# +CONFIG_OS_GUI_DISP_DEV_NAME="lcd" +CONFIG_OS_GUI_INPUT_DEV_NAME="touch" +# CONFIG_OS_USING_GUI_LVGL is not set +# end of GUI + +# +# Industrial +# + +# +# CANOpen +# +# CONFIG_OS_USING_CANFESTIVAL is not set +# end of CANOpen + +# +# CoDeSys +# +# CONFIG_OS_USING_CODESYS is not set +# end of CoDeSys + +# +# ModBus +# +# CONFIG_OS_USING_UCMODBUS is not set +# end of ModBus + +# +# PROFINET +# +# CONFIG_OS_USING_P_NET is not set +# end of PROFINET +# end of Industrial + +# +# IoTjs +# +# CONFIG_USING_IOTJS is not set +# end of IoTjs + +# +# JerryScript +# +# CONFIG_USING_JERRYSCRIPT is not set +# end of JerryScript + +# +# Network +# + +# +# Acw +# +# CONFIG_NET_USING_ACW is not set +# end of Acw + +# +# TCP/IP +# + +# +# LwIP +# +# CONFIG_NET_USING_LWIP is not set +# end of LwIP +# end of TCP/IP + +# +# Molink +# +# CONFIG_NET_USING_MOLINK is not set +# end of Molink + +# +# Protocols +# + +# +# CoAP +# +# CONFIG_NET_USING_COAP is not set +# end of CoAP + +# +# HTTP +# + +# +# httpclient-v1.1.0 +# +# CONFIG_NET_USING_HTTPCLIENT is not set +# end of httpclient-v1.1.0 +# end of HTTP + +# +# LWM2M +# + +# +# LWM2M-v1.0.0 +# +# CONFIG_NET_USING_LWM2M is not set +# end of LWM2M-v1.0.0 +# end of LWM2M + +# +# MQTT +# +# CONFIG_NET_USING_MQTT is not set +# end of MQTT + +# +# Websocket +# +# CONFIG_NET_USING_WEBSOCKET_CLIENT is not set +# end of Websocket +# end of Protocols + +# +# Socket +# +# CONFIG_NET_USING_BSD is not set +# end of Socket +# end of Network + +# +# Iotivity +# +# CONFIG_PKG_USING_IOTIVITY is not set +# end of Iotivity + +# +# Optparse +# +# CONFIG_TP_USING_OPTPARSE is not set +# end of Optparse + +# +# OTA +# + +# +# Fota by CMIOT +# +# CONFIG_FOTA_USING_CMIOT is not set +# end of Fota by CMIOT +# end of OTA + +# +# Position +# +# CONFIG_OS_USING_ONEPOS is not set +# end of Position + +# +# PowerManager +# +# CONFIG_OS_USING_POWER_MANAGER is not set +# end of PowerManager + +# +# Ramdisk +# +# CONFIG_OS_USING_RAMDISK is not set +# end of Ramdisk + +# +# Security +# +# CONFIG_SECURITY_USING_MBEDTLS is not set + +# +# OneTLS +# +# CONFIG_SECURITY_USING_ONETLS is not set +# end of OneTLS +# end of Security + +# +# Shell +# +CONFIG_OS_USING_SHELL=y +CONFIG_SHELL_TASK_NAME="tshell" +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=2048 +CONFIG_SHELL_USING_HISTORY=y +CONFIG_SHELL_HISTORY_LINES=5 +CONFIG_SHELL_USING_DESCRIPTION=y +# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set +CONFIG_SHELL_CMD_SIZE=80 +CONFIG_SHELL_PROMPT_SIZE=256 +CONFIG_SHELL_ARG_MAX=10 +# CONFIG_SHELL_USING_AUTH is not set +# end of Shell + +# +# SQL +# +# CONFIG_PKG_USING_SQLITE is not set +# end of SQL + +# +# telnetd +# +# CONFIG_TELNET_SERVER is not set +# end of telnetd +# end of Components + +# +# Debug +# +CONFIG_OS_DEBUG=y +# CONFIG_LOG_BUFF_SIZE_128 is not set +# CONFIG_LOG_BUFF_SIZE_192 is not set +CONFIG_LOG_BUFF_SIZE_256=y +# CONFIG_LOG_BUFF_SIZE_384 is not set +CONFIG_OS_LOG_BUFF_SIZE=256 +# end of Debug diff --git a/templates/n32g435rbl7-1616n/.gitignore b/templates/n32g435rbl7-1616n/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..232a385f9b0c1f71bc227b6fad5fd55d32a9f449 --- /dev/null +++ b/templates/n32g435rbl7-1616n/.gitignore @@ -0,0 +1,21 @@ +RTE +DebugConfig +Listings +Objects +EventRecorderStub.scvd +.config.old +.sconsign.dblite +__pycache__ +build +one-os.bin +DebugConfig +*.uvguix.* +board/CubeMX_Config/MDK-ARM +board/CubeMX_Config/Drivers +*.o +*.pyc +*.log +*cconfig.h +oneos.bin +JLinkLog.txt +oneos.map diff --git a/templates/n32g435rbl7-1616n/JLinkSettings.ini b/templates/n32g435rbl7-1616n/JLinkSettings.ini new file mode 100644 index 0000000000000000000000000000000000000000..5bf646cfbe39a54f952ae60b02812968c80d0eff --- /dev/null +++ b/templates/n32g435rbl7-1616n/JLinkSettings.ini @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M4" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/templates/n32g435rbl7-1616n/Kconfig b/templates/n32g435rbl7-1616n/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..762ff5598c6722cd7ef2e370d6eb89c872266057 --- /dev/null +++ b/templates/n32g435rbl7-1616n/Kconfig @@ -0,0 +1,12 @@ +mainmenu "OneOS Configuration" + +#Define the relative path to root directory of os code +OS_ROOT=../.. +SRC_HAL=nationstech + +config BOARD_N32G435RBL7_1616N + bool + select SOC_N32G435RBL7 + default y + +source "$OS_ROOT/Kconfig" diff --git a/templates/n32g435rbl7-1616n/application/main.c b/templates/n32g435rbl7-1616n/application/main.c new file mode 100644 index 0000000000000000000000000000000000000000..aef16e440890b547757285d2d9a59980ad0160b2 --- /dev/null +++ b/templates/n32g435rbl7-1616n/application/main.c @@ -0,0 +1,62 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file main.c + * + * @brief User application entry + * + * @revision + * Date Author Notes + * 2020-11-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include + +static void user_task(void *parameter) +{ + int i = 0; + + for (i = 0; i < led_table_size; i++) + { + os_pin_mode(led_table[i].pin, PIN_MODE_OUTPUT); + } + + while (1) + { + for (i = 0; i < led_table_size; i++) + { + os_pin_write(led_table[i].pin, led_table[i].active_level); + os_task_msleep(200); + + os_pin_write(led_table[i].pin, !led_table[i].active_level); + os_task_msleep(200); + } + } +} + +int main(void) +{ + os_task_id task; + + task = os_task_create(OS_NULL, + OS_NULL, 512, + "user", + user_task, NULL, + 3); + OS_ASSERT(task); + os_task_startup(task); + + return 0; +} diff --git a/templates/n32g435rbl7-1616n/application/weave.yaml b/templates/n32g435rbl7-1616n/application/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fa32136884eea1e91681fced4cfe4dcc6c4d45f2 --- /dev/null +++ b/templates/n32g435rbl7-1616n/application/weave.yaml @@ -0,0 +1,6 @@ +# 组名 +group_name: application + +# 源码 +source_file: + - main.c \ No newline at end of file diff --git a/templates/n32g435rbl7-1616n/board/board.c b/templates/n32g435rbl7-1616n/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..48a68479516b2bffdf12b02764099e6895107203 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/board.c @@ -0,0 +1,50 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.c + * + * @brief Initializes the CPU, System clocks, and Peripheral device + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include "board.h" +#include + +#ifdef OS_USING_LED +const led_t led_table[] = { + {GET_PIN(0, 8), PIN_LOW}, + {GET_PIN(1, 12), PIN_LOW}, + {GET_PIN(1, 13), PIN_LOW}, + {GET_PIN(1, 15), PIN_LOW}, +}; + +const int led_table_size = ARRAY_SIZE(led_table); +#endif + +#ifdef OS_USING_PUSH_BUTTON +const struct push_button key_table[] = { + {GET_PIN(1, 7), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 8), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 9), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 13), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 14), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 15), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, +}; + +const int key_table_size = ARRAY_SIZE(key_table); + +#endif diff --git a/templates/n32g435rbl7-1616n/board/board.h b/templates/n32g435rbl7-1616n/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..56fbf3edc07c44e3d9ffa5531638e725e42277b3 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/board.h @@ -0,0 +1,69 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.h + * + * @brief Board resource definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "drv_common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define N32_FLASH_START_ADDR ((uint32_t)0x08000000) +#define N32_FLASH_SIZE (256 * 1024) +#define N32_FLASH_END_ADDR ((uint32_t)(N32_FLASH_START_ADDR + N32_FLASH_SIZE)) + +#define N32_SRAM1_START (0x20000020) +#define N32_SRAM1_SIZE (144 * 1024 - 32) +#define N32_SRAM1_END (N32_SRAM1_START + N32_SRAM1_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END N32_SRAM1_END + +#ifdef OS_USING_PUSH_BUTTON +extern const struct push_button key_table[]; +extern const int key_table_size; +#endif + +#ifdef OS_USING_LED +extern const led_t led_table[]; +extern const int led_table_size; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/templates/n32g435rbl7-1616n/board/linker_scripts/link.icf b/templates/n32g435rbl7-1616n/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..ef3b1c98c8466eff61930ed54e61c737e0da8a55 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20017FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, last block CSTACK}; diff --git a/templates/n32g435rbl7-1616n/board/linker_scripts/link.lds b/templates/n32g435rbl7-1616n/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ed2f6646dbe62f4f4a6a7ad746de9c956b0a5707 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/linker_scripts/link.lds @@ -0,0 +1,149 @@ +/* + * linker script for STM32F1XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 0x00040000 /* 256K flash */ + RAM0 (rx) : ORIGIN = 0x20000000, LENGTH = 0x20 /* 0x20 sram */ + RAM1 (rx) : ORIGIN = 0x20000020, LENGTH = 0x5FE0 /* 0x5FE0 sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x800; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(vtor_table)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + INCLUDE common.lds + + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + } > ROM = 0 + + . = ALIGN(4); + _etext = .; + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + .reserved_ram : + { + * (reserved_ram) + } > RAM0 + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM1 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM1 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM1 + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/templates/n32g435rbl7-1616n/board/linker_scripts/link.sct b/templates/n32g435rbl7-1616n/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..759a23b4e54076ecc67105dd1f1b8274dcce6ae6 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/linker_scripts/link.sct @@ -0,0 +1,20 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (vtor_table, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_IRAM0 0x20000000 0x20 { ; RW data + * (reserved_ram) + } + + RW_IRAM1 0x20000020 0x00005FE0 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/templates/n32g435rbl7-1616n/board/peripherals/peripherals.c b/templates/n32g435rbl7-1616n/board/peripherals/peripherals.c new file mode 100644 index 0000000000000000000000000000000000000000..5f9b04f27746523338f1392b1cda1530f3a6b6da --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/peripherals/peripherals.c @@ -0,0 +1,50 @@ +#include "oneos_config.h" +#include +#include + +#include "drv_common.h" + +#ifdef BSP_USING_USART +#include "drv_usart.h" +const struct n32_usart_info usart1_info = { + .huart = USART1, + .rcc_type = 2, + .rcc = RCC_APB2_PERIPH_USART1, + .irq = USART1_IRQn, + + .dma_channel = NULL, //DMA_CH2, // 用作Console, 不能启用DMA + .dma_rcc = 1, + .dma_irq = DMA_Channel2_IRQn, + + .tx_port = GPIOA, + .tx_pin = GPIO_PIN_9, + .tx_rcc = RCC_APB2_PERIPH_GPIOA, + + .rx_port = GPIOA, + .rx_pin = GPIO_PIN_10, + .rx_rcc = RCC_APB2_PERIPH_GPIOA +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart1", usart1_info); + +const struct n32_usart_info usart2_info = { + .huart = USART2, + .rcc_type = 1, + .rcc = RCC_APB1_PERIPH_USART3, + .irq = USART2_IRQn, + + .dma_channel = DMA_CH4, + .dma_rcc = 1, + .dma_irq = DMA_Channel4_IRQn, + + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_4, + .tx_rcc = RCC_APB2_PERIPH_GPIOB, + + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_5, + .rx_rcc = RCC_APB2_PERIPH_GPIOB +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart2", usart2_info); +#endif diff --git a/templates/bk7231n/application/application_ble_demo/weave.yaml b/templates/n32g435rbl7-1616n/board/peripherals/weave.yaml similarity index 58% rename from templates/bk7231n/application/application_ble_demo/weave.yaml rename to templates/n32g435rbl7-1616n/board/peripherals/weave.yaml index 9521d0165c28ad9653d8c526dc3fa0262aba12eb..c91f78a3137f7745b507d5e162fa5b54ad06615b 100644 --- a/templates/bk7231n/application/application_ble_demo/weave.yaml +++ b/templates/n32g435rbl7-1616n/board/peripherals/weave.yaml @@ -1,5 +1,5 @@ # 组名 -group_name: application +group_name: bsp # 编译连接信息 build_option: @@ -8,4 +8,4 @@ build_option: # 源码 source_file: - - ./*.c ? {is_define("OS_USING_BLE")} \ No newline at end of file + - peripherals.c \ No newline at end of file diff --git a/templates/n32g435rbl7-1616n/board/ports/ef_cfg.h b/templates/n32g435rbl7-1616n/board/ports/ef_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..d7ecfb5c6350e221d356d2a6906fef6faf515139 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/ports/ef_cfg.h @@ -0,0 +1,125 @@ +/* + * This file is part of the EasyFlash Library. + * + * Copyright (c) 2015, Armink, + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Function: It is the configure head file for this library. + * Created on: 2018-05-19 + */ + +#ifndef EF_CFG_H_ +#define EF_CFG_H_ + +#include + +/* using ENV function */ +#define EF_USING_ENV +#define EF_ENV_USING_LEGACY_MODE + +/* using power fail safeguard mode for ENV */ +#define EF_ENV_USING_PFS_MODE + +/* the user setting size of ENV, must be word alignment */ +#define ENV_USER_SETTING_SIZE (PKG_EASYFLASH_ENV_SETTING_SIZE) + +#ifdef PKG_EASYFLASH_ENV_AUTO_UPDATE +/* Auto update ENV to latest default when current ENV version number is changed. */ +#define EF_ENV_AUTO_UPDATE +/** + * ENV version number defined by user. + * Please change it when your firmware add a new ENV to default_env_set. + */ +#define EF_ENV_VER_NUM PKG_EASYFLASH_ENV_VER_NUM +#endif + +/* using IAP function */ +#ifdef PKG_EASYFLASH_IAP +#define EF_USING_IAP +#endif + +/* using save log function */ +#ifdef PKG_EASYFLASH_LOG +#define EF_USING_LOG +/* saved log area size */ +#define LOG_AREA_SIZE (PKG_EASYFLASH_LOG_AREA_SIZE) +#endif + +/* the minimum size of flash erasure */ +#define EF_ERASE_MIN_SIZE PKG_EASYFLASH_ERASE_GRAN + +/* the flash write granularity, unit: bit + * only support 1(nor flash)/ 8(stm32f4)/ 32(stm32f1)/ 64(stm32l4) */ +#define EF_WRITE_GRAN 64 +/** + * + * This all Backup Area Flash storage index. All used flash area configure is under here. + * |----------------------------| Storage Size + * | Environment variables area | ENV area size @see ENV_AREA_SIZE + * | 1.system section | ENV_SYSTEM_SIZE + * | 2:data section | ENV_AREA_SIZE - ENV_SYSTEM_SIZE + * |----------------------------| + * | Saved log area | Log area size @see LOG_AREA_SIZE + * |----------------------------| + * |(IAP)Downloaded application | IAP already downloaded application, unfixed size + * |----------------------------| + * + * @note all area sizes must be aligned with EF_ERASE_MIN_SIZE + * @note EasyFlash will use ram to buffer the ENV. At some point flash's EF_ERASE_MIN_SIZE may become so big, + * and you want to keep ENV size smaller. To do it you must define ENV_USER_SETTING_SIZE for ENV. + * @note ENV area size has some limitations in different modes. + * 1.Normal mode: no limitations + * 2.Wear leveling mode: system section will used a flash section and the data section will use at least 2 flash + * sections 3.Power fail safeguard mode: ENV area will has a backup. It is twice as normal mode. 4.Wear leveling and + * power fail safeguard mode: The required capacity will be 2 times the total capacity in wear leveling mode. For + * example: The EF_ERASE_MIN_SIZE is 128K and the ENV_USER_SETTING_SIZE: 2K. The ENV_AREA_SIZE in different mode you can + * define 1.Normal mode: 1*EF_ERASE_MIN_SIZE 2.Wear leveling mode: 3*EF_ERASE_MIN_SIZE (It has 2 data section to store + * ENV. So ENV can erase at least 200,000 times) 3.Power fail safeguard mode: 2*EF_ERASE_MIN_SIZE 4.Wear leveling and + * power fail safeguard mode: 6*EF_ERASE_MIN_SIZE + * @note the log area size must be more than twice of EF_ERASE_MIN_SIZE + */ +/* backup area start address */ +#define EF_START_ADDR PKG_EASYFLASH_START_ADDR + +#ifndef EF_ENV_USING_PFS_MODE +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in normal mode. */ +#define ENV_AREA_SIZE (1 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling mode. */ +#define ENV_AREA_SIZE (4 * EF_ERASE_MIN_SIZE) +#endif +#else +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in power fail safeguard mode. */ +#define ENV_AREA_SIZE (2 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling and power fail safeguard mode. */ +#define ENV_AREA_SIZE (6 * EF_ERASE_MIN_SIZE) +#endif +#endif + +/* print debug information of flash */ +#ifdef PKG_EASYFLASH_DEBUG +#define PRINT_DEBUG +#endif + +#endif /* EF_CFG_H_ */ diff --git a/templates/n32g435rbl7-1616n/board/ports/fal_cfg.c b/templates/n32g435rbl7-1616n/board/ports/fal_cfg.c new file mode 100644 index 0000000000000000000000000000000000000000..2a68fd1a31c0d97bca7f0db45015350365384598 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/ports/fal_cfg.c @@ -0,0 +1,27 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file fal_cfg.c + * + * @brief Flash abstract layer partition definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ +static const fal_part_info_t fal_part_info[] = { + /* part, flash, addr, size, lock */ + {"app", "onchip_flash", 0x00000000, 120*1024, FAL_PART_INFO_FLAGS_LOCKED}, + {"user", "onchip_flash", 120*1024, 8*1024, FAL_PART_INFO_FLAGS_UNLOCKED}, +}; diff --git a/templates/n32g435rbl7-1616n/board/ports/flash_info.c b/templates/n32g435rbl7-1616n/board/ports/flash_info.c new file mode 100644 index 0000000000000000000000000000000000000000..9bcaebee13c242427456857f6916cb0a1d254fed --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/ports/flash_info.c @@ -0,0 +1,7 @@ +static struct onchip_flash_info flash_info = { + .start_addr = N32_FLASH_START_ADDR, + .capacity = N32_FLASH_SIZE, + .block_size = N32_FLASH_BLOCK_SIZE, + .page_size = N32_FLASH_PAGE_SIZE, +}; +OS_HAL_DEVICE_DEFINE("N32G43X_Onchip_Flash", "onchip_flash", flash_info); diff --git a/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_arm.s b/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_arm.s new file mode 100644 index 0000000000000000000000000000000000000000..ea9bb0d2321ac3b0ad3d2bccd8daae3b8384dcb9 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_arm.s @@ -0,0 +1,373 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +___initial_sp + EXPORT ___initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD 0 ; Reserved + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_gcc.s b/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..18e111231d69b08dfde12b6f73286af0c1115cd5 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/startup/startup_n32g43x_gcc.s @@ -0,0 +1,421 @@ +/** +****************************************************************************** +* @file startup_n32g43x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT NATIONSTECH *****END OF FILE****/ diff --git a/templates/n32g435rbl7-1616n/board/weave.yaml b/templates/n32g435rbl7-1616n/board/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..02573794386f7eaa6b0c3ade3ffbd4548e9756f7 --- /dev/null +++ b/templates/n32g435rbl7-1616n/board/weave.yaml @@ -0,0 +1,22 @@ +# 组名 +group_name: bsp + +# 编译连接信息 +build_option: + cpppath: + - . + - ports + cppdefines: + - N32G43X + - HSE_VALUE=25000000 + - SYSCLK_FREQ=100000000 + +# 源码 +source_file: + - board.c + - startup/startup_n32g43x_gcc.s ? {is_compiler("gcc")} + - startup/startup_n32g43x_arm.s ? {is_compiler("armcc")} + +# 子目录 +add_subdirectory: + - ./* \ No newline at end of file diff --git a/templates/n32g435rbl7-1616n/oneos_config.h b/templates/n32g435rbl7-1616n/oneos_config.h new file mode 100644 index 0000000000000000000000000000000000000000..f78e56585745e218d7188e745e584379680b1e17 --- /dev/null +++ b/templates/n32g435rbl7-1616n/oneos_config.h @@ -0,0 +1,537 @@ +#ifndef __ONEOS_CONFIG_H__ +#define __ONEOS_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ +#define BOARD_N32L406RBL7_MXIO_1616N +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* Kernel */ + +#define OS_NAME_MAX_15 +#define OS_NAME_MAX 15 +#define OS_TASK_PRIORITY_32 +#define OS_TASK_PRIORITY_MAX 32 +#define OS_TICK_PER_SECOND 1000 +#define OS_SCHEDULE_TIME_SLICE 10 +#define OS_USING_OVERFLOW_CHECK +#define OS_USING_KERNEL_DEBUG +#define KLOG_GLOBAL_LEVEL_WARNING +#define KLOG_GLOBAL_LEVEL 1 +#define KLOG_USING_COLOR +#define KLOG_WITH_FUNC_LINE +#define OS_MAIN_TASK_STACK_SIZE 2048 +#define OS_IDLE_TASK_STACK_SIZE 512 +#define OS_RECYCLE_TASK_STACK_SIZE 512 +#define OS_USING_TIMER +#define OS_TIMER_TASK_STACK_SIZE 512 +#define OS_TIMER_POWER 3 +#define OS_USING_WORKQUEUE +#define OS_USING_SYSTEM_WORKQUEUE +#define OS_SYSTEM_WORKQUEUE_STACK_SIZE 2048 +#define OS_SYSTEM_WORKQUEUE_PRIORITY 0 + +/* Inter-task communication and synchronization */ + +#define OS_USING_MUTEX +#define OS_USING_SEMAPHORE +/* end of Inter-task communication and synchronization */ + +/* Memory management */ + +#define OS_USING_SYS_HEAP +#define OS_USING_MEM_HEAP +#define OS_USING_ALG_FIRSTFIT +/* end of Memory management */ +/* end of Kernel */ + +/* C standard library adapter */ + +#define OS_USING_LIBC_ADAPTER +#define OS_USING_NEWLIB_ADAPTER +#define OS_USING_ARMCCLIB_ADAPTER +/* end of C standard library adapter */ + +/* Osal */ + +/* POSIX compatibility layer */ + +/* end of POSIX compatibility layer */ + +/* RT-Thread compatibility layer */ + +/* end of RT-Thread compatibility layer */ + +/* CMSIS compatibility layer */ + +/* end of CMSIS compatibility layer */ + +/* FreeRTOS compatibility layer */ + +/* end of FreeRTOS compatibility layer */ + +/* C++ Features */ + +/* end of C++ Features */ +/* end of Osal */ + +/* Drivers */ + +#define OS_USING_DEVICE +#define OS_USING_DEVICE_NOTIFY + +/* Audio */ + +/* end of Audio */ + +/* BLOCK */ + +#define OS_USING_BLOCK +/* end of BLOCK */ + +/* Boot */ + +/* CORTEX-M Boot */ + +#define BSP_INCLUDE_VECTOR_TABLE +/* end of CORTEX-M Boot */ +/* end of Boot */ + +/* CAN */ + +/* end of CAN */ + +/* CONSOLE */ + +#define OS_USING_CONSOLE +#define OS_CONSOLE_DEVICE_NAME "usart1" +/* end of CONSOLE */ + +/* DMA */ + +#define OS_USING_DMA +#define OS_USING_DMA_RAM +#define OS_USING_SOFT_DMA +#define OS_SOFT_DMA_SUPPORT_NORMAL_MODE +#define OS_SOFT_DMA_SUPPORT_CIRCLE_MODE +#define OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT +/* end of DMA */ + +/* EEPROM */ + +/* end of EEPROM */ + +/* FAL */ + +#define OS_USING_FAL +/* end of FAL */ + +/* Graphic */ + +/* end of Graphic */ + +/* HAL */ + +#define MANUFACTOR_NATIONSTECH +#define SERIES_N32L40X +#define SOC_N32L406RBL7 +#define BSP_USING_GPIO +#define BSP_USING_LED +#define BSP_USING_USART +#define BSP_USING_ONCHIP_FLASH +#define BSP_USING_TIMER +/* end of HAL */ + +/* HwCrypto */ + +/* end of HwCrypto */ + +/* I2C */ + +/* end of I2C */ + +/* Infrared */ + +/* end of Infrared */ + +/* LPMGR */ + +/* end of LPMGR */ + +/* MISC */ + +#define OS_USING_PUSH_BUTTON +#define OS_USING_LED +/* end of MISC */ + +/* MTD */ + +/* end of MTD */ + +/* NAND */ + +/* end of NAND */ + +/* NET */ + +/* end of NET */ + +/* PIN */ + +#define OS_USING_PIN +#define OS_PIN_MAX_CHIP 1 +/* end of PIN */ + +/* RTC */ + +/* end of RTC */ + +/* SDIO */ + +/* end of SDIO */ + +/* Sensors */ + +/* end of Sensors */ + +/* Serial */ + +#define OS_USING_SERIAL +#define OS_SERIAL_DELAY_CLOSE +#define OS_SERIAL_RX_BUFSZ 64 +#define OS_SERIAL_TX_BUFSZ 64 + +/* posix serial */ + +/* end of posix serial */ + +/* rtt uart */ + +/* end of rtt uart */ +/* end of Serial */ + +/* SFLASH */ + +/* end of SFLASH */ + +/* SN */ + +/* end of SN */ + +/* SPI */ + +/* end of SPI */ + +/* Timer */ + +#define OS_USING_TIMER_DRIVER +#define OS_USING_CLOCKSOURCE +#define OS_CLOCKSOURCE_BEST "" + +/* cortex-m & riscv hardware timer config */ + +#define OS_USING_SYSTICK_FOR_KERNEL_TICK +#define OS_USING_DWT_FOR_CLOCKSOURCE +/* end of cortex-m & riscv hardware timer config */ +/* end of Timer */ + +/* TinyUSB */ + +/* end of TinyUSB */ + +/* Touch */ + +/* end of Touch */ + +/* USB */ + +/* end of USB */ + +/* WDG */ + +/* end of WDG */ +/* end of Drivers */ + +/* Components */ + +/* MicroPython */ + +/* end of MicroPython */ + +/* WWD */ + +/* end of WWD */ + +/* AMS */ + +/* end of AMS */ + +/* Atest */ + +/* end of Atest */ + +/* BLE */ + +/* end of BLE */ + +/* cJSON */ + +/* end of cJSON */ + +/* CLI */ + +/* end of CLI */ + +/* Cloud */ + +/* Aliyun */ + +/* end of Aliyun */ + +/* AWS */ + +/* end of AWS */ + +/* Baidu */ + +/* end of Baidu */ + +/* CTWing */ + +/* MQTT */ + +/* end of MQTT */ +/* end of CTWing */ + +/* Huawei */ + +/* end of Huawei */ + +/* OneNET */ + +/* MQTT kit */ + +/* end of MQTT kit */ + +/* NB-IoT kit */ + +/* end of NB-IoT kit */ + +/* EDP */ + +/* end of EDP */ +/* end of OneNET */ +/* end of Cloud */ + +/* CMS */ + +#define CMS_LITE + +/* CMS Connect */ + +/* end of CMS Connect */ + +/* CMS ID */ + +/* end of CMS ID */ +/* end of CMS */ + +/* Diagnose */ + + +/* eCoreDump */ + +/* end of eCoreDump */ + +/* Memory Monitor */ + +/* end of Memory Monitor */ +/* end of Diagnose */ + +/* Dlog */ + +#define OS_USING_DLOG +#define DLOG_PRINT_LVL_W +#define DLOG_GLOBAL_PRINT_LEVEL 4 +#define DLOG_COMPILE_LVL_D +#define DLOG_COMPILE_LEVEL 7 +#define DLOG_USING_ISR_LOG +#define DLOG_USING_FILTER +#define DLOG_USING_ASYNC_OUTPUT +#define DLOG_ASYNC_OUTPUT_BUF_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_PRIORITY 20 + +/* Log format */ + +#define DLOG_WITH_FUNC_LINE +#define DLOG_USING_COLOR +#define DLOG_OUTPUT_TIME_INFO +/* end of Log format */ + +/* Dlog backend option */ + +#define DLOG_BACKEND_USING_CONSOLE +/* end of Dlog backend option */ +/* end of Dlog */ + +/* Easyflash */ + +/* end of Easyflash */ + +/* FileSystem */ + +/* end of FileSystem */ + +/* GUI */ + +#define OS_GUI_DISP_DEV_NAME "lcd" +#define OS_GUI_INPUT_DEV_NAME "touch" +/* end of GUI */ + +/* Industrial */ + +/* CANOpen */ + +/* end of CANOpen */ + +/* CoDeSys */ + +/* end of CoDeSys */ + +/* ModBus */ + +/* end of ModBus */ + +/* PROFINET */ + +/* end of PROFINET */ +/* end of Industrial */ + +/* IoTjs */ + +/* end of IoTjs */ + +/* JerryScript */ + +/* end of JerryScript */ + +/* Network */ + +/* Acw */ + +/* end of Acw */ + +/* TCP/IP */ + +/* LwIP */ + +/* end of LwIP */ +/* end of TCP/IP */ + +/* Molink */ + +/* end of Molink */ + +/* Protocols */ + +/* CoAP */ + +/* end of CoAP */ + +/* HTTP */ + +/* httpclient-v1.1.0 */ + +/* end of httpclient-v1.1.0 */ +/* end of HTTP */ + +/* LWM2M */ + +/* LWM2M-v1.0.0 */ + +/* end of LWM2M-v1.0.0 */ +/* end of LWM2M */ + +/* MQTT */ + +/* end of MQTT */ + +/* Websocket */ + +/* end of Websocket */ +/* end of Protocols */ + +/* Socket */ + +/* end of Socket */ +/* end of Network */ + +/* Iotivity */ + +/* end of Iotivity */ + +/* Optparse */ + +/* end of Optparse */ + +/* OTA */ + +/* Fota by CMIOT */ + +/* end of Fota by CMIOT */ +/* end of OTA */ + +/* Position */ + +/* end of Position */ + +/* PowerManager */ + +/* end of PowerManager */ + +/* Ramdisk */ + +/* end of Ramdisk */ + +/* Security */ + + +/* OneTLS */ + +/* end of OneTLS */ +/* end of Security */ + +/* Shell */ + +#define OS_USING_SHELL +#define SHELL_TASK_NAME "tshell" +#define SHELL_TASK_PRIORITY 20 +#define SHELL_TASK_STACK_SIZE 2048 +#define SHELL_USING_HISTORY +#define SHELL_HISTORY_LINES 5 +#define SHELL_USING_DESCRIPTION +#define SHELL_CMD_SIZE 80 +#define SHELL_PROMPT_SIZE 256 +#define SHELL_ARG_MAX 10 +/* end of Shell */ + +/* SQL */ + +/* end of SQL */ + +/* telnetd */ + +/* end of telnetd */ +/* end of Components */ + +/* Debug */ + +#define OS_DEBUG +#define LOG_BUFF_SIZE_256 +#define OS_LOG_BUFF_SIZE 256 +/* end of Debug */ + +#endif /* __ONEOS_CONFIG_H__ */ + diff --git a/templates/n32g435rbl7-1616n/osconfig.py b/templates/n32g435rbl7-1616n/osconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..f4b271be0d5da7e937218bfacb0f025d66a73970 --- /dev/null +++ b/templates/n32g435rbl7-1616n/osconfig.py @@ -0,0 +1,149 @@ +import os + +# toolchains options +ARCH = 'arm' +CPU = 'cortex-m4' +CROSS_TOOL = 'gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('OS_CC'): + CROSS_TOOL = os.getenv('OS_CC') +if os.getenv('OS_ROOT'): + OS_ROOT = os.getenv('OS_ROOT') + +# cross_tool provides the cross compiler +# COMPILER_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + COMPILER = 'gcc' + COMPILER_PATH = '' +elif CROSS_TOOL == 'keil': + COMPILER = 'armcc' + # Notice: The installation path of armcc cannot have Chinese + COMPILER_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + COMPILER = 'iar' + COMPILER_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + + +if COMPILER == 'gcc': + # "BUILD" can be: 'debug_O0', 'release_O2' or 'release_Os' + BUILD = 'debug_O0' +else: + BUILD = 'debug' + +if COMPILER == 'gcc': + # toolchains + if COMPILER_PATH == '': + COMPILER_PATH = os.getenv('OS_EXEC_PATH') + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + RESULT_SUFFIX = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -L $OS_ROOT/drivers/link/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug_O0': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + elif BUILD == 'release_O2': + CFLAGS += ' -O2' + else: + CFLAGS += ' -Os' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -R .reserved_ram -O binary $TARGET oneos.bin\n' + SIZE + ' $TARGET \n' + +elif COMPILER == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + RESULT_SUFFIX = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --split_sections --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list oneos.map --strict' + CFLAGS += ' -I "' + COMPILER_PATH + '/ARM/ARMCC/include"' + LFLAGS += ' --libpath="' + COMPILER_PATH + '/ARM/ARMCC/lib"' + + #CFLAGS += ' -D__MICROLIB ' + #AFLAGS += ' --pd "__MICROLIB SETA 1" ' + #LFLAGS += ' --library_type=microlib ' + COMPILER_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output oneos.bin \nfromelf -z $TARGET' + +elif COMPILER == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + RESULT_SUFFIX = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + COMPILER_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + COMPILER_PATH = COMPILER_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET oneos.bin' diff --git a/templates/n32g435rbl7-1616n/project.uvoptx b/templates/n32g435rbl7-1616n/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..fdf13d150d7619b5238f25764f7c8a16bb225f88 --- /dev/null +++ b/templates/n32g435rbl7-1616n/project.uvoptx @@ -0,0 +1,1469 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G43x -FL020000 -FS08000000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G43x -FL020000 -FS08000000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + application + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + application\main.c + main.c + 0 + 0 + + + + + arch + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_atomic.c + arch_atomic.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_exception.c + arch_exception.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + arch_exception_rvds.S + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_interrupt.c + arch_interrupt.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_misc.c + arch_misc.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_task.c + arch_task.c + 0 + 0 + + + 2 + 8 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + arch_task_switch_rvds.S + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + board\peripherals\peripherals.c + peripherals.c + 0 + 0 + + + 3 + 11 + 2 + 0 + 0 + 0 + board\startup\startup_n32g43x.s + startup_n32g43x.s + 0 + 0 + + + + + cli + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli.c + cli.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_cms.c + cli_cms.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_lwip.c + cli_lwip.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_molink.c + cli_molink.c + 0 + 0 + + + + + common + 0 + 0 + 0 + 0 + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\common\source\option_parse.c + option_parse.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_blk_buff.c + ring_blk_buff.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_buff.c + ring_buff.c + 0 + 0 + + + + + dlog + 0 + 0 + 0 + 0 + + 6 + 19 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\backend\console_backend.c + console_backend.c + 0 + 0 + + + 6 + 20 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\dlog.c + dlog.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 7 + 21 + 1 + 0 + 0 + 0 + ..\..\drivers\block\block_device.c + block_device.c + 0 + 0 + + + 7 + 22 + 1 + 0 + 0 + 0 + ..\..\drivers\bus\bus.c + bus.c + 0 + 0 + + + 7 + 23 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource.c + clocksource.c + 0 + 0 + + + 7 + 24 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource_cortexm.c + clocksource_cortexm.c + 0 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + ..\..\drivers\console\console.c + console.c + 0 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + ..\..\drivers\device.c + device.c + 0 + 0 + + + 7 + 27 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\dma_ram.c + dma_ram.c + 0 + 0 + + + 7 + 28 + 1 + 0 + 0 + 0 + ..\..\drivers\driver.c + driver.c + 0 + 0 + + + 7 + 29 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal.c + fal.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_block.c + fal_block.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_part.c + fal_part.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\drivers\pin\pin.c + pin.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\drivers\misc\push_button.c + push_button.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\soft_dma.c + soft_dma.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\timer.c + timer.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\drivers\boot\cotex-m\vector_table.c + vector_table.c + 0 + 0 + + + + + hal/drivers + 0 + 0 + 0 + 0 + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_common.c + drv_common.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_usart.c + drv_usart.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + 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..\..\libc\source\armlibc\access.c + access.c + 0 + 0 + + + 11 + 69 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\chdir.c + chdir.c + 0 + 0 + + + 11 + 70 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\close.c + close.c + 0 + 0 + + + 11 + 71 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\dirent.c + dirent.c + 0 + 0 + + + 11 + 72 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fcntl.c + fcntl.c + 0 + 0 + + + 11 + 73 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fstat.c + fstat.c + 0 + 0 + + + 11 + 74 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fsync.c + fsync.c + 0 + 0 + + + 11 + 75 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\getcwd.c + getcwd.c + 0 + 0 + + + 11 + 76 + 1 + 0 + 0 + 0 + ..\..\libc\source\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + 11 + 77 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\ioctl.c + ioctl.c + 0 + 0 + + + 11 + 78 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\libc.c + libc.c + 0 + 0 + + + 11 + 79 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\lseek.c + lseek.c + 0 + 0 + + + 11 + 80 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 11 + 81 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mkdir.c + mkdir.c + 0 + 0 + + + 11 + 82 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\open.c + open.c + 0 + 0 + + + 11 + 83 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\read.c + read.c + 0 + 0 + + + 11 + 84 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rename.c + rename.c + 0 + 0 + + + 11 + 85 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rmdir.c + rmdir.c + 0 + 0 + + + 11 + 86 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stat.c + stat.c + 0 + 0 + + + 11 + 87 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\statfs.c + statfs.c + 0 + 0 + + + 11 + 88 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stdio.c + stdio.c + 0 + 0 + + + 11 + 89 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strdup.c + strdup.c + 0 + 0 + + + 11 + 90 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strnlen.c + strnlen.c + 0 + 0 + + + 11 + 91 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stubs.c + stubs.c + 0 + 0 + + + 11 + 92 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\time.c + time.c + 0 + 0 + + + 11 + 93 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\unlink.c + unlink.c + 0 + 0 + + + 11 + 94 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\write.c + write.c + 0 + 0 + + + + + shell + 0 + 0 + 0 + 0 + + 12 + 95 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_buildin_cmd.c + shell_buildin_cmd.c + 0 + 0 + + + 12 + 96 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_main.c + shell_main.c + 0 + 0 + + + 12 + 97 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_process.c + shell_process.c + 0 + 0 + + + 12 + 98 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_symbol.c + shell_symbol.c + 0 + 0 + + + + diff --git a/templates/n32g435rbl7-1616n/project.uvprojx b/templates/n32g435rbl7-1616n/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..890c2384def7a0aada6479fb1ed87cfcb79d67a3 --- /dev/null +++ b/templates/n32g435rbl7-1616n/project.uvprojx @@ -0,0 +1,953 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32G435RB + Nationstech + Nationstech.N32G43x_DFP.0.9.3 + http://www.keil.com/pack/ + IRAM(0x20000000,0x8000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32G43x -FS08000000 -FL020000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM)) + 0 + $$Device:N32G435RB$firmware\CMSIS\device\n32g43x.h + + + + + + + + + + $$Device:N32G435RB$svd\N32G435.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + OS_TASK_SWITCH_NOTIFY, N32G45X + + .;..\..\components\uai\library;..\..\arch\arm\armv7m\include;board;board\ports;board\peripherals;..\..\components\cli\include;..\..\common\include;..\..\components\dlog\include;..\..\drivers;..\..\drivers\boot\cotex-m;..\..\drivers\bus;..\..\drivers\console;..\..\drivers\dma;..\..\drivers\fal;..\..\drivers\misc;..\..\drivers\pin;..\..\drivers\serial;..\..\drivers\timer;..\..\components\diagnose\eCoreDump;..\..\drivers\hal\nationstech\drivers\n32g43x;..\..\drivers\hal\nationstech\drivers\n32g43x\flash;..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\inc;..\..\drivers\hal\nationstech\N32G43x\CMSIS\core;..\..\drivers\hal\nationstech\N32G43x\CMSIS\device;..\..\kernel\include;..\..\libc\include;..\..\libc\include\extension;..\..\libc\include\armlibc;..\..\components\shell\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + OS_TASK_SWITCH_NOTIFY + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress L6314,L6330 + + + + + + + + application + + + main.c + 1 + application\main.c + + + + + arch + + + arch_atomic.c + 1 + ..\..\arch\arm\armv7m\arch_atomic.c + + + arch_exception.c + 1 + ..\..\arch\arm\armv7m\arch_exception.c + + + arch_exception_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + + + arch_interrupt.c + 1 + ..\..\arch\arm\armv7m\arch_interrupt.c + + + arch_misc.c + 1 + ..\..\arch\arm\armv7m\arch_misc.c + + + arch_task.c + 1 + ..\..\arch\arm\armv7m\arch_task.c + + + arch_task_switch_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + + + + + bsp + + + board.c + 1 + board\board.c + + + peripherals.c + 1 + board\peripherals\peripherals.c + + + startup_n32g43x.s + 2 + board\startup\startup_n32g43x.s + + + + + cli + + + cli.c + 1 + ..\..\components\cli\source\cli.c + + + cli_cms.c + 1 + ..\..\components\cli\source\cli_cms.c + + + cli_lwip.c + 1 + ..\..\components\cli\source\cli_lwip.c + + + cli_molink.c + 1 + ..\..\components\cli\source\cli_molink.c + + + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_common.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\misc.c + + + n32g43x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_dma.c + + + n32g43x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_exti.c + + + n32g43x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_flash.c + + + n32g43x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_gpio.c + + + n32g43x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_rcc.c + + + n32g43x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_tim.c + + + n32g43x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_usart.c + + + system_n32g43x.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\CMSIS\device\system_n32g43x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/n32g435rbl7-1616n/settings-gcc.yaml b/templates/n32g435rbl7-1616n/settings-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c764ee1dabe7c2e958b9035f0565d981e7514cb3 --- /dev/null +++ b/templates/n32g435rbl7-1616n/settings-gcc.yaml @@ -0,0 +1,27 @@ +# 编译选项（支持条件表达式） +option: + cflags: # General options that are passed to the C compiler (C only; not C++). + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + cxxflags: # General options that are passed to the C++ compiler. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + asflags: # General options passed to the assembler. + - ' -c' + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + - ' -gdwarf-2 ? {is_mode(''O0'')}' + linkflags: # General user options passed to the linker. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + +# 构建前/后动作（支持条件表达式） +action: + prebuild: + - 'script:sys.path.append("$OS_ROOT" + "/drivers/hal/nationstech/scripts/");import prebuild;prebuild.prebuild("$PRO_ROOT")' \ No newline at end of file diff --git a/templates/n32g435rbl7-1616n/template.uvoptx b/templates/n32g435rbl7-1616n/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..fdf13d150d7619b5238f25764f7c8a16bb225f88 --- /dev/null +++ b/templates/n32g435rbl7-1616n/template.uvoptx @@ -0,0 +1,1469 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G43x -FL020000 -FS08000000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G43x -FL020000 -FS08000000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + 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board\board.c + board.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + board\peripherals\peripherals.c + peripherals.c + 0 + 0 + + + 3 + 11 + 2 + 0 + 0 + 0 + board\startup\startup_n32g43x.s + startup_n32g43x.s + 0 + 0 + + + + + cli + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli.c + cli.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_cms.c + cli_cms.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_lwip.c + cli_lwip.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_molink.c + cli_molink.c + 0 + 0 + + + + + common + 0 + 0 + 0 + 0 + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\common\source\option_parse.c + option_parse.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_blk_buff.c + ring_blk_buff.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_buff.c + ring_buff.c + 0 + 0 + + + + + dlog + 0 + 0 + 0 + 0 + + 6 + 19 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\backend\console_backend.c + console_backend.c + 0 + 0 + + + 6 + 20 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\dlog.c + dlog.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 7 + 21 + 1 + 0 + 0 + 0 + ..\..\drivers\block\block_device.c + block_device.c + 0 + 0 + + + 7 + 22 + 1 + 0 + 0 + 0 + ..\..\drivers\bus\bus.c + bus.c + 0 + 0 + + + 7 + 23 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource.c + clocksource.c + 0 + 0 + + + 7 + 24 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource_cortexm.c + clocksource_cortexm.c + 0 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + ..\..\drivers\console\console.c + console.c + 0 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + ..\..\drivers\device.c + device.c + 0 + 0 + + + 7 + 27 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\dma_ram.c + dma_ram.c + 0 + 0 + + + 7 + 28 + 1 + 0 + 0 + 0 + ..\..\drivers\driver.c + driver.c + 0 + 0 + + + 7 + 29 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal.c + fal.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_block.c + fal_block.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_part.c + fal_part.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\drivers\pin\pin.c + pin.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\drivers\misc\push_button.c + push_button.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\soft_dma.c + soft_dma.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\timer.c + timer.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\drivers\boot\cotex-m\vector_table.c + vector_table.c + 0 + 0 + + + + + hal/drivers + 0 + 0 + 0 + 0 + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_common.c + drv_common.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_usart.c + drv_usart.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32g43x\n32_it.c + n32_it.c + 0 + 0 + + + + + hal/lowlevel + 0 + 0 + 0 + 0 + + 9 + 42 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 9 + 43 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_dma.c + n32g43x_dma.c + 0 + 0 + + + 9 + 44 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_exti.c + n32g43x_exti.c + 0 + 0 + + + 9 + 45 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_flash.c + n32g43x_flash.c + 0 + 0 + + + 9 + 46 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_gpio.c + n32g43x_gpio.c + 0 + 0 + + + 9 + 47 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_rcc.c + n32g43x_rcc.c + 0 + 0 + + + 9 + 48 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_tim.c + n32g43x_tim.c + 0 + 0 + + + 9 + 49 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_usart.c + n32g43x_usart.c + 0 + 0 + + + 9 + 50 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32G43x\CMSIS\device\system_n32g43x.c + system_n32g43x.c + 0 + 0 + + + + + kernel + 0 + 0 + 0 + 0 + + 10 + 51 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_block.c + os_block.c + 0 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_clock.c + os_clock.c + 0 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_idle.c + os_idle.c + 0 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_lock.c + os_kernel_lock.c + 0 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_log.c + os_kernel_log.c + 0 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mem_firstfit.c + os_mem_firstfit.c + 0 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_memory.c + os_memory.c + 0 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mutex.c + os_mutex.c + 0 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sched.c + os_sched.c + 0 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sem.c + os_sem.c + 0 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_spinlock.c + os_spinlock.c + 0 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_startup.c + os_startup.c + 0 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_task.c + os_task.c + 0 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_timer_hash.c + os_timer_hash.c + 0 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_util.c + os_util.c + 0 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_version.c + os_version.c + 0 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_workqueue.c + os_workqueue.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 11 + 68 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\access.c + access.c + 0 + 0 + + + 11 + 69 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\chdir.c + chdir.c + 0 + 0 + + + 11 + 70 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\close.c + close.c + 0 + 0 + + + 11 + 71 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\dirent.c + dirent.c + 0 + 0 + + + 11 + 72 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fcntl.c + fcntl.c + 0 + 0 + + + 11 + 73 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fstat.c + fstat.c + 0 + 0 + + + 11 + 74 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fsync.c + fsync.c + 0 + 0 + + + 11 + 75 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\getcwd.c + getcwd.c + 0 + 0 + + + 11 + 76 + 1 + 0 + 0 + 0 + ..\..\libc\source\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + 11 + 77 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\ioctl.c + ioctl.c + 0 + 0 + + + 11 + 78 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\libc.c + libc.c + 0 + 0 + + + 11 + 79 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\lseek.c + lseek.c + 0 + 0 + + + 11 + 80 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 11 + 81 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mkdir.c + mkdir.c + 0 + 0 + + + 11 + 82 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\open.c + open.c + 0 + 0 + + + 11 + 83 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\read.c + read.c + 0 + 0 + + + 11 + 84 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rename.c + rename.c + 0 + 0 + + + 11 + 85 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rmdir.c + rmdir.c + 0 + 0 + + + 11 + 86 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stat.c + stat.c + 0 + 0 + + + 11 + 87 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\statfs.c + statfs.c + 0 + 0 + + + 11 + 88 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stdio.c + stdio.c + 0 + 0 + + + 11 + 89 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strdup.c + strdup.c + 0 + 0 + + + 11 + 90 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strnlen.c + strnlen.c + 0 + 0 + + + 11 + 91 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stubs.c + stubs.c + 0 + 0 + + + 11 + 92 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\time.c + time.c + 0 + 0 + + + 11 + 93 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\unlink.c + unlink.c + 0 + 0 + + + 11 + 94 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\write.c + write.c + 0 + 0 + + + + + shell + 0 + 0 + 0 + 0 + + 12 + 95 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_buildin_cmd.c + shell_buildin_cmd.c + 0 + 0 + + + 12 + 96 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_main.c + shell_main.c + 0 + 0 + + + 12 + 97 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_process.c + shell_process.c + 0 + 0 + + + 12 + 98 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_symbol.c + shell_symbol.c + 0 + 0 + + + + diff --git a/templates/n32g435rbl7-1616n/template.uvprojx b/templates/n32g435rbl7-1616n/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..890c2384def7a0aada6479fb1ed87cfcb79d67a3 --- /dev/null +++ b/templates/n32g435rbl7-1616n/template.uvprojx @@ -0,0 +1,953 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32G435RB + Nationstech + Nationstech.N32G43x_DFP.0.9.3 + http://www.keil.com/pack/ + IRAM(0x20000000,0x8000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32G43x -FS08000000 -FL020000 -FP0($$Device:N32G435RB$Flash\N32G43x.FLM)) + 0 + $$Device:N32G435RB$firmware\CMSIS\device\n32g43x.h + + + + + + + + + + $$Device:N32G435RB$svd\N32G435.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + OS_TASK_SWITCH_NOTIFY, N32G45X + + .;..\..\components\uai\library;..\..\arch\arm\armv7m\include;board;board\ports;board\peripherals;..\..\components\cli\include;..\..\common\include;..\..\components\dlog\include;..\..\drivers;..\..\drivers\boot\cotex-m;..\..\drivers\bus;..\..\drivers\console;..\..\drivers\dma;..\..\drivers\fal;..\..\drivers\misc;..\..\drivers\pin;..\..\drivers\serial;..\..\drivers\timer;..\..\components\diagnose\eCoreDump;..\..\drivers\hal\nationstech\drivers\n32g43x;..\..\drivers\hal\nationstech\drivers\n32g43x\flash;..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\inc;..\..\drivers\hal\nationstech\N32G43x\CMSIS\core;..\..\drivers\hal\nationstech\N32G43x\CMSIS\device;..\..\kernel\include;..\..\libc\include;..\..\libc\include\extension;..\..\libc\include\armlibc;..\..\components\shell\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + OS_TASK_SWITCH_NOTIFY + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress L6314,L6330 + + + + + + + + application + + + main.c + 1 + application\main.c + + + + + arch + + + arch_atomic.c + 1 + ..\..\arch\arm\armv7m\arch_atomic.c + + + arch_exception.c + 1 + ..\..\arch\arm\armv7m\arch_exception.c + + + arch_exception_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + + + arch_interrupt.c + 1 + ..\..\arch\arm\armv7m\arch_interrupt.c + + + arch_misc.c + 1 + ..\..\arch\arm\armv7m\arch_misc.c + + + arch_task.c + 1 + ..\..\arch\arm\armv7m\arch_task.c + + + arch_task_switch_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + + + + + bsp + + + board.c + 1 + board\board.c + + + peripherals.c + 1 + board\peripherals\peripherals.c + + + startup_n32g43x.s + 2 + board\startup\startup_n32g43x.s + + + + + cli + + + cli.c + 1 + ..\..\components\cli\source\cli.c + + + cli_cms.c + 1 + ..\..\components\cli\source\cli_cms.c + + + cli_lwip.c + 1 + ..\..\components\cli\source\cli_lwip.c + + + cli_molink.c + 1 + ..\..\components\cli\source\cli_molink.c + + + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_common.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32g43x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\misc.c + + + n32g43x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_dma.c + + + n32g43x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_exti.c + + + n32g43x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_flash.c + + + n32g43x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_gpio.c + + + n32g43x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_rcc.c + + + n32g43x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_tim.c + + + n32g43x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\n32g43x_std_periph_driver\src\n32g43x_usart.c + + + system_n32g43x.c + 1 + ..\..\drivers\hal\nationstech\N32G43x\CMSIS\device\system_n32g43x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/n32g452ccl7-mxppih/.config b/templates/n32g452ccl7-mxppih/.config index 89f33558debaa17de5febb0710193fa12cfb7c4a..c948ea5d07914a26a43fa124e3ee589cd6fad75b 100644 --- a/templates/n32g452ccl7-mxppih/.config +++ b/templates/n32g452ccl7-mxppih/.config @@ -18,7 +18,7 @@ CONFIG_OS_TASK_PRIORITY_32=y # CONFIG_OS_TASK_PRIORITY_128 is not set # CONFIG_OS_TASK_PRIORITY_256 is not set CONFIG_OS_TASK_PRIORITY_MAX=32 -CONFIG_OS_TICK_PER_SECOND=100 +CONFIG_OS_TICK_PER_SECOND=1000 CONFIG_OS_SCHEDULE_TIME_SLICE=10 CONFIG_OS_USING_OVERFLOW_CHECK=y # CONFIG_OS_USING_TASK_HOOK is not set diff --git a/templates/n32g452ccl7-mxppih/application/main.c b/templates/n32g452ccl7-mxppih/application/main.c index b38563b0bb302f5602739a10fe3a8f82a24ffe5c..960b77db7517de82c4d882fd93afedea99517d56 100644 --- a/templates/n32g452ccl7-mxppih/application/main.c +++ b/templates/n32g452ccl7-mxppih/application/main.c @@ -50,7 +50,11 @@ int main(void) { os_task_id task; - task = os_task_create(OS_NULL, OS_NULL, 512, "user", user_task, OS_NULL, 3); + task = os_task_create(OS_NULL, + OS_NULL, 512, + "user", + user_task, NULL, + 3); OS_ASSERT(task); os_task_startup(task); diff --git a/templates/n32g452ccl7-mxppih/board/board.h b/templates/n32g452ccl7-mxppih/board/board.h index 4ce2431dc6fef582b5e69213e3c11de926e78320..56fbf3edc07c44e3d9ffa5531638e725e42277b3 100644 --- a/templates/n32g452ccl7-mxppih/board/board.h +++ b/templates/n32g452ccl7-mxppih/board/board.h @@ -24,7 +24,7 @@ #ifndef __BOARD_H__ #define __BOARD_H__ -#include "n32g45x_hal.h" +#include "drv_common.h" #include #ifdef __cplusplus diff --git a/templates/n32g452ccl7-mxppih/board/peripherals/peripherals.c b/templates/n32g452ccl7-mxppih/board/peripherals/peripherals.c index aa903d601931526c96b0fd13d09066a8014bc8aa..00ff754b50cae91169ee3498ad2911d75d08b78e 100644 --- a/templates/n32g452ccl7-mxppih/board/peripherals/peripherals.c +++ b/templates/n32g452ccl7-mxppih/board/peripherals/peripherals.c @@ -2,7 +2,7 @@ #include #include -#include "n32g45x_hal.h" +#include "drv_common.h" #ifdef BSP_USING_USART #include "drv_usart.h" @@ -12,7 +12,7 @@ const struct n32_usart_info usart1_info = { .rcc = RCC_APB2_PERIPH_USART1, .irq = USART1_IRQn, - .dma_channel = DMA1_CH5, + .dma_channel = NULL, //DMA1_CH5, // 用作Console, 不能启用DMA .dma_rcc = 1, .dma_irq = DMA1_Channel5_IRQn, diff --git a/templates/n32g452ccl7-mxppih/board/ports/fal_cfg.c b/templates/n32g452ccl7-mxppih/board/ports/fal_cfg.c index a10c72663517996795b8315d941b04211cdb7b90..6e88be5f63186ae06006afbb69239e983e1baa82 100644 --- a/templates/n32g452ccl7-mxppih/board/ports/fal_cfg.c +++ b/templates/n32g452ccl7-mxppih/board/ports/fal_cfg.c @@ -22,5 +22,6 @@ */ static const fal_part_info_t fal_part_info[] = { /* part, flash, addr, size, lock */ - {"user", "onchip_flash", 0x00000000, 8*1024, FAL_PART_INFO_FLAGS_UNLOCKED}, + {"app", "onchip_flash", 0x00000000, 248*1024, FAL_PART_INFO_FLAGS_LOCKED}, + {"user", "onchip_flash", 248*1024, 8*1024, FAL_PART_INFO_FLAGS_UNLOCKED}, }; diff --git a/templates/n32g452ccl7-mxppih/board/ports/flash_info.c b/templates/n32g452ccl7-mxppih/board/ports/flash_info.c index e44ce5246feb9efa31dcf9b9037e3f51639ac959..f0eed5cadd6b14437b5f3e5752c790c1509b0c46 100644 --- a/templates/n32g452ccl7-mxppih/board/ports/flash_info.c +++ b/templates/n32g452ccl7-mxppih/board/ports/flash_info.c @@ -4,4 +4,4 @@ static struct onchip_flash_info flash_info = { .block_size = N32_FLASH_BLOCK_SIZE, .page_size = N32_FLASH_PAGE_SIZE, }; -OS_HAL_DEVICE_DEFINE("N32G452_Onchip_Flash", "onchip_flash", flash_info); +OS_HAL_DEVICE_DEFINE("N32G45X_Onchip_Flash", "onchip_flash", flash_info); diff --git a/templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x.s b/templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x_arm.s similarity index 100% rename from templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x.s rename to templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x_arm.s diff --git a/templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x_gcc.s b/templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..526fcb0194923ad812328d01db15cb57f30bbb3a --- /dev/null +++ b/templates/n32g452ccl7-mxppih/board/startup/startup_n32g45x_gcc.s @@ -0,0 +1,485 @@ +/** + ****************************************************************************** + * @file startup_n32g45x_gcc.S + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1, ADC2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word ADC3_4_IRQHandler /* ADC3 & ADC4 */ + .word XFMC_IRQHandler /* XFMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel5 */ + .word ETH_IRQHandler /* Ethernet global interrupt */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word QSPI_IRQHandler /* QSPI */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel7 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word I2C4_EV_IRQHandler /* I2C4 event */ + .word I2C4_ER_IRQHandler /* I2C4 error */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel8 */ + .word DVP_IRQHandler /* DVP */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_4_IRQHandler + .thumb_set ADC3_4_IRQHandler,Default_Handler + + .weak XFMC_IRQHandler + .thumb_set XFMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak QSPI_IRQHandler + .thumb_set QSPI_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak UART6_IRQHandler + .thumb_set UART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT NATIONSTECH *****END OF FILE****/ diff --git a/templates/n32g452ccl7-mxppih/board/weave.yaml b/templates/n32g452ccl7-mxppih/board/weave.yaml index 66677988639dbb124f6b8e5f930d6344ac8ebb84..9bd34c8292f3e9afd983071bd3112e90ae71dc87 100644 --- a/templates/n32g452ccl7-mxppih/board/weave.yaml +++ b/templates/n32g452ccl7-mxppih/board/weave.yaml @@ -8,11 +8,14 @@ build_option: - ports cppdefines: - N32G45X + - HSE_VALUE=25000000 + - SYSCLK_FREQ=100000000 # 源码 source_file: - board.c - - startup/startup_n32g45x.s ? {is_compiler("armcc")} + - startup/startup_n32g45x_gcc.s ? {is_compiler("gcc")} + - startup/startup_n32g45x_arm.s ? {is_compiler("armcc")} # 子目录 add_subdirectory: diff --git a/templates/n32l406rbl7-1616n/.config b/templates/n32l406rbl7-1616n/.config new file mode 100644 index 0000000000000000000000000000000000000000..f493b51068c8dc5f1ac6e0a85488951b9b26b666 --- /dev/null +++ b/templates/n32l406rbl7-1616n/.config @@ -0,0 +1,800 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) +CONFIG_BOARD_N32L406RBL7_MXIO_1616N=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# Kernel +# +# CONFIG_OS_NAME_MAX_7 is not set +CONFIG_OS_NAME_MAX_15=y +# CONFIG_OS_NAME_MAX_31 is not set +CONFIG_OS_NAME_MAX=15 +# CONFIG_OS_TASK_PRIORITY_8 is not set +# CONFIG_OS_TASK_PRIORITY_16 is not set +CONFIG_OS_TASK_PRIORITY_32=y +# CONFIG_OS_TASK_PRIORITY_64 is not set +# CONFIG_OS_TASK_PRIORITY_128 is not set +# CONFIG_OS_TASK_PRIORITY_256 is not set +CONFIG_OS_TASK_PRIORITY_MAX=32 +CONFIG_OS_TICK_PER_SECOND=1000 +CONFIG_OS_SCHEDULE_TIME_SLICE=10 +CONFIG_OS_USING_OVERFLOW_CHECK=y +# CONFIG_OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK is not set +# CONFIG_OS_USING_TASK_HOOK is not set +# CONFIG_OS_USING_ASSERT is not set +# CONFIG_OS_USING_KERNEL_LOCK_CHECK is not set +# CONFIG_OS_USING_SAFETY_MECHANISM is not set +CONFIG_OS_USING_KERNEL_DEBUG=y +# CONFIG_KLOG_GLOBAL_LEVEL_ERROR is not set +CONFIG_KLOG_GLOBAL_LEVEL_WARNING=y +# CONFIG_KLOG_GLOBAL_LEVEL_INFO is not set +# CONFIG_KLOG_GLOBAL_LEVEL_DEBUG is not set +CONFIG_KLOG_GLOBAL_LEVEL=1 +CONFIG_KLOG_USING_COLOR=y +CONFIG_KLOG_WITH_FUNC_LINE=y +CONFIG_OS_MAIN_TASK_STACK_SIZE=2048 +CONFIG_OS_IDLE_TASK_STACK_SIZE=512 +CONFIG_OS_RECYCLE_TASK_STACK_SIZE=512 +CONFIG_OS_USING_TIMER=y +CONFIG_OS_TIMER_TASK_STACK_SIZE=512 +CONFIG_OS_TIMER_POWER=3 +# CONFIG_OS_TIMER_SORT is not set +CONFIG_OS_USING_WORKQUEUE=y +CONFIG_OS_USING_SYSTEM_WORKQUEUE=y +CONFIG_OS_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_OS_SYSTEM_WORKQUEUE_PRIORITY=0 + +# +# Inter-task communication and synchronization +# +CONFIG_OS_USING_MUTEX=y +# CONFIG_OS_USING_SPINLOCK_CHECK is not set +CONFIG_OS_USING_SEMAPHORE=y +# CONFIG_OS_SEM_WAIT_HOOK is not set +# CONFIG_OS_SEM_POST_HOOK is not set +# CONFIG_OS_USING_EVENT is not set +# CONFIG_OS_USING_MESSAGEQUEUE is not set +# CONFIG_OS_USING_MAILBOX is not set +# end of Inter-task communication and synchronization + +# +# Memory management +# +CONFIG_OS_USING_SYS_HEAP=y +CONFIG_OS_USING_MEM_HEAP=y +CONFIG_OS_USING_ALG_FIRSTFIT=y +# CONFIG_OS_USING_ALG_BUDDY is not set +# CONFIG_OS_USING_MEM_TRACE is not set +# CONFIG_OS_USING_MEM_POOL is not set +# end of Memory management + +# CONFIG_OS_USING_IPC_TRACE is not set +# CONFIG_OS_USING_IPC_HOOK is not set +# end of Kernel + +# +# C standard library adapter +# +CONFIG_OS_USING_LIBC_ADAPTER=y +CONFIG_OS_USING_NEWLIB_ADAPTER=y +CONFIG_OS_USING_ARMCCLIB_ADAPTER=y +# end of C standard library adapter + +# +# Osal +# + +# +# POSIX compatibility layer +# +# CONFIG_OS_USING_PTHREADS is not set +# end of POSIX compatibility layer + +# +# RT-Thread compatibility layer +# +# CONFIG_OS_USING_RTTHREAD_API_V3_1_3 is not set +# end of RT-Thread compatibility layer + +# +# CMSIS compatibility layer +# +# CONFIG_OS_USING_CMSIS_RTOS2_API_V2_1_2 is not set +# end of CMSIS compatibility layer + +# +# FreeRTOS compatibility layer +# +# CONFIG_OS_USING_FREERTOS_API_V10_4_3 is not set +# end of FreeRTOS compatibility layer + +# +# C++ Features +# +# CONFIG_OS_USING_CPLUSPLUS is not set +# end of C++ Features +# end of Osal + +# +# Drivers +# +CONFIG_OS_USING_DEVICE=y +CONFIG_OS_USING_DEVICE_NOTIFY=y +# CONFIG_OS_DEVICE_SUPPORT_PLUG is not set + +# +# Audio +# +# CONFIG_OS_USING_AUDIO is not set +# end of Audio + +# +# BLOCK +# +CONFIG_OS_USING_BLOCK=y +# end of BLOCK + +# +# Boot +# + +# +# CORTEX-M Boot +# +CONFIG_BSP_INCLUDE_VECTOR_TABLE=y +# CONFIG_BSP_BOOT_OPTION is not set +# end of CORTEX-M Boot +# end of Boot + +# +# CAN +# +# CONFIG_OS_USING_CAN is not set +# end of CAN + +# +# CONSOLE +# +CONFIG_OS_USING_CONSOLE=y +CONFIG_OS_CONSOLE_DEVICE_NAME="usart1" +# end of CONSOLE + +# +# DMA +# +CONFIG_OS_USING_DMA=y +CONFIG_OS_USING_DMA_RAM=y +CONFIG_OS_USING_SOFT_DMA=y +CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# end of DMA + +# +# EEPROM +# +# CONFIG_OS_EEPROM_SUPPORT is not set +# end of EEPROM + +# +# FAL +# +CONFIG_OS_USING_FAL=y +# CONFIG_OS_FAL_RAM is not set +# end of FAL + +# +# Graphic +# +# CONFIG_OS_USING_GRAPHIC is not set +# end of Graphic + +# +# HAL +# +CONFIG_MANUFACTOR_NATIONSTECH=y +CONFIG_SERIES_N32L40X=y +CONFIG_SOC_N32L406RBL7=y +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_USART=y +CONFIG_BSP_USING_ONCHIP_FLASH=y +CONFIG_BSP_USING_TIMER=y +# end of HAL + +# +# HwCrypto +# +# CONFIG_OS_USING_HWCRYPTO is not set +# end of HwCrypto + +# +# I2C +# +# CONFIG_OS_USING_I2C is not set +# end of I2C + +# +# Infrared +# +# CONFIG_OS_USING_INFRARED is not set +# end of Infrared + +# +# LPMGR +# +# CONFIG_OS_USING_LPMGR is not set +# end of LPMGR + +# +# MISC +# +CONFIG_OS_USING_PUSH_BUTTON=y +CONFIG_OS_USING_LED=y +# CONFIG_OS_USING_BUZZER is not set +# CONFIG_OS_USING_ADC is not set +# CONFIG_OS_USING_DAC is not set +# CONFIG_OS_USING_PWM is not set +# CONFIG_OS_USING_INPUT_CAPTURE is not set +# CONFIG_OS_USING_PULSE_ENCODER is not set +# end of MISC + +# +# MTD +# +# CONFIG_OS_USING_MTD is not set +# end of MTD + +# +# NAND +# +# CONFIG_OS_USING_NAND is not set +# end of NAND + +# +# NET +# +# CONFIG_OS_USING_NET_DEVICE is not set +# CONFIG_OS_USING_WLAN is not set +# CONFIG_BSP_USING_AP6181 is not set +# end of NET + +# +# PIN +# +CONFIG_OS_USING_PIN=y +CONFIG_OS_PIN_MAX_CHIP=1 +# CONFIG_BSP_USING_PIN_PCF8574 is not set +# end of PIN + +# +# RTC +# +# CONFIG_OS_USING_RTC is not set +# end of RTC + +# +# SDIO +# +# CONFIG_OS_USING_SDIO is not set +# end of SDIO + +# +# Sensors +# +# CONFIG_OS_USING_SENSOR is not set +# end of Sensors + +# +# Serial +# +CONFIG_OS_USING_SERIAL=y +CONFIG_OS_SERIAL_DELAY_CLOSE=y +CONFIG_OS_SERIAL_RX_BUFSZ=64 +CONFIG_OS_SERIAL_TX_BUFSZ=64 + +# +# posix serial +# +# CONFIG_OS_USING_POSIX_SERIAL is not set +# end of posix serial + +# +# rtt uart +# +# CONFIG_OS_USING_RTT is not set +# end of rtt uart +# end of Serial + +# +# SFLASH +# +# CONFIG_OS_SFLASH_SUPPORT is not set +# end of SFLASH + +# +# SN +# +# CONFIG_OS_USING_SN is not set +# end of SN + +# +# SPI +# +# CONFIG_OS_USING_SPI is not set +# CONFIG_BSP_USING_ENC28J60 is not set +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_NRF24L01 is not set +# CONFIG_BSP_USING_TPS_1 is not set +# CONFIG_OS_USING_SFUD is not set +# end of SPI + +# +# Timer +# +CONFIG_OS_USING_TIMER_DRIVER=y +CONFIG_OS_USING_CLOCKSOURCE=y +# CONFIG_OS_CLOCKSOURCE_SHOW is not set +# CONFIG_OS_USING_TIMEKEEPING is not set +CONFIG_OS_CLOCKSOURCE_BEST="" +# CONFIG_OS_USING_CLOCKEVENT is not set +# CONFIG_OS_USING_HRTIMER is not set + +# +# cortex-m & riscv hardware timer config +# +CONFIG_OS_USING_SYSTICK_FOR_KERNEL_TICK=y +# CONFIG_OS_USING_SYSTICK_FOR_CLOCKSOURCE is not set +CONFIG_OS_USING_DWT_FOR_CLOCKSOURCE=y +# end of cortex-m & riscv hardware timer config +# end of Timer + +# +# TinyUSB +# +# CONFIG_OS_USING_TINYUSB is not set +# end of TinyUSB + +# +# Touch +# +# CONFIG_OS_USING_TOUCH is not set +# end of Touch + +# +# USB +# +# CONFIG_OS_USING_USB_DEVICE is not set +# CONFIG_OS_USING_USB_HOST is not set +# end of USB + +# +# WDG +# +# CONFIG_OS_USING_WDG is not set +# end of WDG +# end of Drivers + +# +# Components +# + +# +# MicroPython +# +# CONFIG_PKG_USING_MICROPYTHON is not set +# end of MicroPython + +# +# WWD +# +# CONFIG_OS_USING_WWD is not set +# end of WWD + +# +# AMS +# +# CONFIG_PKG_USING_AMS is not set +# end of AMS + +# +# Atest +# +# CONFIG_OS_USING_ATEST is not set +# end of Atest + +# +# BLE +# +# CONFIG_OS_USING_BLE is not set +# end of BLE + +# +# cJSON +# +# CONFIG_PKG_USING_CJSON is not set +# end of cJSON + +# +# CLI +# +# CONFIG_OS_USING_CLI is not set +# end of CLI + +# +# Cloud +# + +# +# Aliyun +# +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# end of Aliyun + +# +# AWS +# +# CONFIG_PKG_USING_AWS_IOT is not set +# end of AWS + +# +# Baidu +# +# CONFIG_BAIDUIOT is not set +# end of Baidu + +# +# CTWing +# + +# +# MQTT +# +# CONFIG_OS_USING_CTWING_MQTT is not set +# end of MQTT +# end of CTWing + +# +# Huawei +# +# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set +# end of Huawei + +# +# OneNET +# + +# +# MQTT kit +# +# CONFIG_OS_USING_ONENET_MQTTS is not set +# end of MQTT kit + +# +# NB-IoT kit +# +# CONFIG_OS_USING_ONENET_NBIOT is not set +# end of NB-IoT kit + +# +# EDP +# +# CONFIG_OS_USING_ONENET_EDP is not set +# end of EDP +# end of OneNET +# end of Cloud + +# +# CMS +# +CONFIG_CMS_LITE=y +# CONFIG_CMS_STD is not set + +# +# CMS Connect +# +# CONFIG_USING_CMS_CONNECT is not set +# end of CMS Connect + +# +# CMS ID +# +# CONFIG_CMS_USING_ID is not set +# end of CMS ID +# end of CMS + +# +# Diagnose +# +# CONFIG_STACK_TRACE_EN is not set +# CONFIG_OS_USING_CPU_MONITER is not set +# CONFIG_OS_USING_WIRESHARK_DUMP is not set + +# +# eCoreDump +# +# CONFIG_USING_ECORE_DUMP is not set +# end of eCoreDump + +# +# Memory Monitor +# +# CONFIG_OS_USING_MEM_MONITOR is not set +# end of Memory Monitor +# end of Diagnose + +# +# Dlog +# +CONFIG_OS_USING_DLOG=y +# CONFIG_DLOG_PRINT_LVL_E is not set +CONFIG_DLOG_PRINT_LVL_W=y +# CONFIG_DLOG_PRINT_LVL_I is not set +# CONFIG_DLOG_PRINT_LVL_D is not set +CONFIG_DLOG_GLOBAL_PRINT_LEVEL=4 +# CONFIG_DLOG_COMPILE_LVL_E is not set +# CONFIG_DLOG_COMPILE_LVL_W is not set +# CONFIG_DLOG_COMPILE_LVL_I is not set +CONFIG_DLOG_COMPILE_LVL_D=y +CONFIG_DLOG_COMPILE_LEVEL=7 +CONFIG_DLOG_USING_ISR_LOG=y +CONFIG_DLOG_USING_FILTER=y +CONFIG_DLOG_USING_ASYNC_OUTPUT=y +CONFIG_DLOG_ASYNC_OUTPUT_BUF_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_PRIORITY=20 +# CONFIG_DLOG_USING_SYSLOG is not set + +# +# Log format +# +# CONFIG_DLOG_OUTPUT_FLOAT is not set +CONFIG_DLOG_WITH_FUNC_LINE=y +CONFIG_DLOG_USING_COLOR=y +CONFIG_DLOG_OUTPUT_TIME_INFO=y +# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set +# end of Log format + +# +# Dlog backend option +# +CONFIG_DLOG_BACKEND_USING_CONSOLE=y +# CONFIG_DLOG_BACKEND_USING_FILESYSTEM is not set +# end of Dlog backend option +# end of Dlog + +# +# Easyflash +# +# CONFIG_PKG_USING_EASYFLASH is not set +# end of Easyflash + +# +# FileSystem +# +# CONFIG_OS_USING_VFS is not set +# end of FileSystem + +# +# GUI +# +CONFIG_OS_GUI_DISP_DEV_NAME="lcd" +CONFIG_OS_GUI_INPUT_DEV_NAME="touch" +# CONFIG_OS_USING_GUI_LVGL is not set +# end of GUI + +# +# Industrial +# + +# +# CANOpen +# +# CONFIG_OS_USING_CANFESTIVAL is not set +# end of CANOpen + +# +# CoDeSys +# +# CONFIG_OS_USING_CODESYS is not set +# end of CoDeSys + +# +# ModBus +# +# CONFIG_OS_USING_UCMODBUS is not set +# end of ModBus + +# +# PROFINET +# +# CONFIG_OS_USING_P_NET is not set +# end of PROFINET +# end of Industrial + +# +# IoTjs +# +# CONFIG_USING_IOTJS is not set +# end of IoTjs + +# +# JerryScript +# +# CONFIG_USING_JERRYSCRIPT is not set +# end of JerryScript + +# +# Network +# + +# +# Acw +# +# CONFIG_NET_USING_ACW is not set +# end of Acw + +# +# TCP/IP +# + +# +# LwIP +# +# CONFIG_NET_USING_LWIP is not set +# end of LwIP +# end of TCP/IP + +# +# Molink +# +# CONFIG_NET_USING_MOLINK is not set +# end of Molink + +# +# Protocols +# + +# +# CoAP +# +# CONFIG_NET_USING_COAP is not set +# end of CoAP + +# +# HTTP +# + +# +# httpclient-v1.1.0 +# +# CONFIG_NET_USING_HTTPCLIENT is not set +# end of httpclient-v1.1.0 +# end of HTTP + +# +# LWM2M +# + +# +# LWM2M-v1.0.0 +# +# CONFIG_NET_USING_LWM2M is not set +# end of LWM2M-v1.0.0 +# end of LWM2M + +# +# MQTT +# +# CONFIG_NET_USING_MQTT is not set +# end of MQTT + +# +# Websocket +# +# CONFIG_NET_USING_WEBSOCKET_CLIENT is not set +# end of Websocket +# end of Protocols + +# +# Socket +# +# CONFIG_NET_USING_BSD is not set +# end of Socket +# end of Network + +# +# Iotivity +# +# CONFIG_PKG_USING_IOTIVITY is not set +# end of Iotivity + +# +# Optparse +# +# CONFIG_TP_USING_OPTPARSE is not set +# end of Optparse + +# +# OTA +# + +# +# Fota by CMIOT +# +# CONFIG_FOTA_USING_CMIOT is not set +# end of Fota by CMIOT +# end of OTA + +# +# Position +# +# CONFIG_OS_USING_ONEPOS is not set +# end of Position + +# +# PowerManager +# +# CONFIG_OS_USING_POWER_MANAGER is not set +# end of PowerManager + +# +# Ramdisk +# +# CONFIG_OS_USING_RAMDISK is not set +# end of Ramdisk + +# +# Security +# +# CONFIG_SECURITY_USING_MBEDTLS is not set + +# +# OneTLS +# +# CONFIG_SECURITY_USING_ONETLS is not set +# end of OneTLS +# end of Security + +# +# Shell +# +CONFIG_OS_USING_SHELL=y +CONFIG_SHELL_TASK_NAME="tshell" +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=2048 +CONFIG_SHELL_USING_HISTORY=y +CONFIG_SHELL_HISTORY_LINES=5 +CONFIG_SHELL_USING_DESCRIPTION=y +# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set +CONFIG_SHELL_CMD_SIZE=80 +CONFIG_SHELL_PROMPT_SIZE=256 +CONFIG_SHELL_ARG_MAX=10 +# CONFIG_SHELL_USING_AUTH is not set +# end of Shell + +# +# SQL +# +# CONFIG_PKG_USING_SQLITE is not set +# end of SQL + +# +# telnetd +# +# CONFIG_TELNET_SERVER is not set +# end of telnetd +# end of Components + +# +# Debug +# +CONFIG_OS_DEBUG=y +# CONFIG_LOG_BUFF_SIZE_128 is not set +# CONFIG_LOG_BUFF_SIZE_192 is not set +CONFIG_LOG_BUFF_SIZE_256=y +# CONFIG_LOG_BUFF_SIZE_384 is not set +CONFIG_OS_LOG_BUFF_SIZE=256 +# end of Debug diff --git a/templates/n32l406rbl7-1616n/.gitignore b/templates/n32l406rbl7-1616n/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..232a385f9b0c1f71bc227b6fad5fd55d32a9f449 --- /dev/null +++ b/templates/n32l406rbl7-1616n/.gitignore @@ -0,0 +1,21 @@ +RTE +DebugConfig +Listings +Objects +EventRecorderStub.scvd +.config.old +.sconsign.dblite +__pycache__ +build +one-os.bin +DebugConfig +*.uvguix.* +board/CubeMX_Config/MDK-ARM +board/CubeMX_Config/Drivers +*.o +*.pyc +*.log +*cconfig.h +oneos.bin +JLinkLog.txt +oneos.map diff --git a/templates/n32l406rbl7-1616n/JLinkSettings.ini b/templates/n32l406rbl7-1616n/JLinkSettings.ini new file mode 100644 index 0000000000000000000000000000000000000000..5bf646cfbe39a54f952ae60b02812968c80d0eff --- /dev/null +++ b/templates/n32l406rbl7-1616n/JLinkSettings.ini @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M4" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/templates/n32l406rbl7-1616n/Kconfig b/templates/n32l406rbl7-1616n/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..ca96768dd73388cd2e157ed1dc2f792cfb05e927 --- /dev/null +++ b/templates/n32l406rbl7-1616n/Kconfig @@ -0,0 +1,12 @@ +mainmenu "OneOS Configuration" + +#Define the relative path to root directory of os code +OS_ROOT=../.. +SRC_HAL=nationstech + +config BOARD_N32L406RBL7_MXIO_1616N + bool + select SOC_N32L406RBL7 + default y + +source "$OS_ROOT/Kconfig" diff --git a/templates/n32l406rbl7-1616n/application/main.c b/templates/n32l406rbl7-1616n/application/main.c new file mode 100644 index 0000000000000000000000000000000000000000..aef16e440890b547757285d2d9a59980ad0160b2 --- /dev/null +++ b/templates/n32l406rbl7-1616n/application/main.c @@ -0,0 +1,62 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file main.c + * + * @brief User application entry + * + * @revision + * Date Author Notes + * 2020-11-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include + +static void user_task(void *parameter) +{ + int i = 0; + + for (i = 0; i < led_table_size; i++) + { + os_pin_mode(led_table[i].pin, PIN_MODE_OUTPUT); + } + + while (1) + { + for (i = 0; i < led_table_size; i++) + { + os_pin_write(led_table[i].pin, led_table[i].active_level); + os_task_msleep(200); + + os_pin_write(led_table[i].pin, !led_table[i].active_level); + os_task_msleep(200); + } + } +} + +int main(void) +{ + os_task_id task; + + task = os_task_create(OS_NULL, + OS_NULL, 512, + "user", + user_task, NULL, + 3); + OS_ASSERT(task); + os_task_startup(task); + + return 0; +} diff --git a/templates/n32l406rbl7-1616n/application/weave.yaml b/templates/n32l406rbl7-1616n/application/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fa32136884eea1e91681fced4cfe4dcc6c4d45f2 --- /dev/null +++ b/templates/n32l406rbl7-1616n/application/weave.yaml @@ -0,0 +1,6 @@ +# 组名 +group_name: application + +# 源码 +source_file: + - main.c \ No newline at end of file diff --git a/templates/n32l406rbl7-1616n/board/board.c b/templates/n32l406rbl7-1616n/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..48a68479516b2bffdf12b02764099e6895107203 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/board.c @@ -0,0 +1,50 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.c + * + * @brief Initializes the CPU, System clocks, and Peripheral device + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include "board.h" +#include + +#ifdef OS_USING_LED +const led_t led_table[] = { + {GET_PIN(0, 8), PIN_LOW}, + {GET_PIN(1, 12), PIN_LOW}, + {GET_PIN(1, 13), PIN_LOW}, + {GET_PIN(1, 15), PIN_LOW}, +}; + +const int led_table_size = ARRAY_SIZE(led_table); +#endif + +#ifdef OS_USING_PUSH_BUTTON +const struct push_button key_table[] = { + {GET_PIN(1, 7), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 8), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 9), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 13), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 14), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 15), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, +}; + +const int key_table_size = ARRAY_SIZE(key_table); + +#endif diff --git a/templates/n32l406rbl7-1616n/board/board.h b/templates/n32l406rbl7-1616n/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..56fbf3edc07c44e3d9ffa5531638e725e42277b3 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/board.h @@ -0,0 +1,69 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.h + * + * @brief Board resource definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "drv_common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define N32_FLASH_START_ADDR ((uint32_t)0x08000000) +#define N32_FLASH_SIZE (256 * 1024) +#define N32_FLASH_END_ADDR ((uint32_t)(N32_FLASH_START_ADDR + N32_FLASH_SIZE)) + +#define N32_SRAM1_START (0x20000020) +#define N32_SRAM1_SIZE (144 * 1024 - 32) +#define N32_SRAM1_END (N32_SRAM1_START + N32_SRAM1_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END N32_SRAM1_END + +#ifdef OS_USING_PUSH_BUTTON +extern const struct push_button key_table[]; +extern const int key_table_size; +#endif + +#ifdef OS_USING_LED +extern const led_t led_table[]; +extern const int led_table_size; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/templates/n32l406rbl7-1616n/board/linker_scripts/link.icf b/templates/n32l406rbl7-1616n/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..ef3b1c98c8466eff61930ed54e61c737e0da8a55 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20017FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, last block CSTACK}; diff --git a/templates/n32l406rbl7-1616n/board/linker_scripts/link.lds b/templates/n32l406rbl7-1616n/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ed2f6646dbe62f4f4a6a7ad746de9c956b0a5707 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/linker_scripts/link.lds @@ -0,0 +1,149 @@ +/* + * linker script for STM32F1XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 0x00040000 /* 256K flash */ + RAM0 (rx) : ORIGIN = 0x20000000, LENGTH = 0x20 /* 0x20 sram */ + RAM1 (rx) : ORIGIN = 0x20000020, LENGTH = 0x5FE0 /* 0x5FE0 sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x800; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(vtor_table)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + INCLUDE common.lds + + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + } > ROM = 0 + + . = ALIGN(4); + _etext = .; + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + .reserved_ram : + { + * (reserved_ram) + } > RAM0 + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM1 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM1 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM1 + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/templates/n32l406rbl7-1616n/board/linker_scripts/link.sct b/templates/n32l406rbl7-1616n/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..759a23b4e54076ecc67105dd1f1b8274dcce6ae6 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/linker_scripts/link.sct @@ -0,0 +1,20 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (vtor_table, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_IRAM0 0x20000000 0x20 { ; RW data + * (reserved_ram) + } + + RW_IRAM1 0x20000020 0x00005FE0 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/templates/n32l406rbl7-1616n/board/peripherals/peripherals.c b/templates/n32l406rbl7-1616n/board/peripherals/peripherals.c new file mode 100644 index 0000000000000000000000000000000000000000..5f9b04f27746523338f1392b1cda1530f3a6b6da --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/peripherals/peripherals.c @@ -0,0 +1,50 @@ +#include "oneos_config.h" +#include +#include + +#include "drv_common.h" + +#ifdef BSP_USING_USART +#include "drv_usart.h" +const struct n32_usart_info usart1_info = { + .huart = USART1, + .rcc_type = 2, + .rcc = RCC_APB2_PERIPH_USART1, + .irq = USART1_IRQn, + + .dma_channel = NULL, //DMA_CH2, // 用作Console, 不能启用DMA + .dma_rcc = 1, + .dma_irq = DMA_Channel2_IRQn, + + .tx_port = GPIOA, + .tx_pin = GPIO_PIN_9, + .tx_rcc = RCC_APB2_PERIPH_GPIOA, + + .rx_port = GPIOA, + .rx_pin = GPIO_PIN_10, + .rx_rcc = RCC_APB2_PERIPH_GPIOA +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart1", usart1_info); + +const struct n32_usart_info usart2_info = { + .huart = USART2, + .rcc_type = 1, + .rcc = RCC_APB1_PERIPH_USART3, + .irq = USART2_IRQn, + + .dma_channel = DMA_CH4, + .dma_rcc = 1, + .dma_irq = DMA_Channel4_IRQn, + + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_4, + .tx_rcc = RCC_APB2_PERIPH_GPIOB, + + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_5, + .rx_rcc = RCC_APB2_PERIPH_GPIOB +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart2", usart2_info); +#endif diff --git a/drivers/hal/beken/drivers/wlan/weave.yaml b/templates/n32l406rbl7-1616n/board/peripherals/weave.yaml similarity index 48% rename from drivers/hal/beken/drivers/wlan/weave.yaml rename to templates/n32l406rbl7-1616n/board/peripherals/weave.yaml index 7ccf4506b4d14fa4f752a2b294269c8921d8cca0..c91f78a3137f7745b507d5e162fa5b54ad06615b 100644 --- a/drivers/hal/beken/drivers/wlan/weave.yaml +++ b/templates/n32l406rbl7-1616n/board/peripherals/weave.yaml @@ -1,9 +1,5 @@ # 组名 -group_name: drv_wlan - -# 依赖宏控 -depend_macro: - - BEKEN_USING_WLAN +group_name: bsp # 编译连接信息 build_option: @@ -12,5 +8,4 @@ build_option: # 源码 source_file: - - ./*.c - - ./*.S \ No newline at end of file + - peripherals.c \ No newline at end of file diff --git a/templates/n32l406rbl7-1616n/board/ports/ef_cfg.h b/templates/n32l406rbl7-1616n/board/ports/ef_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..d7ecfb5c6350e221d356d2a6906fef6faf515139 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/ports/ef_cfg.h @@ -0,0 +1,125 @@ +/* + * This file is part of the EasyFlash Library. + * + * Copyright (c) 2015, Armink, + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Function: It is the configure head file for this library. + * Created on: 2018-05-19 + */ + +#ifndef EF_CFG_H_ +#define EF_CFG_H_ + +#include + +/* using ENV function */ +#define EF_USING_ENV +#define EF_ENV_USING_LEGACY_MODE + +/* using power fail safeguard mode for ENV */ +#define EF_ENV_USING_PFS_MODE + +/* the user setting size of ENV, must be word alignment */ +#define ENV_USER_SETTING_SIZE (PKG_EASYFLASH_ENV_SETTING_SIZE) + +#ifdef PKG_EASYFLASH_ENV_AUTO_UPDATE +/* Auto update ENV to latest default when current ENV version number is changed. */ +#define EF_ENV_AUTO_UPDATE +/** + * ENV version number defined by user. + * Please change it when your firmware add a new ENV to default_env_set. + */ +#define EF_ENV_VER_NUM PKG_EASYFLASH_ENV_VER_NUM +#endif + +/* using IAP function */ +#ifdef PKG_EASYFLASH_IAP +#define EF_USING_IAP +#endif + +/* using save log function */ +#ifdef PKG_EASYFLASH_LOG +#define EF_USING_LOG +/* saved log area size */ +#define LOG_AREA_SIZE (PKG_EASYFLASH_LOG_AREA_SIZE) +#endif + +/* the minimum size of flash erasure */ +#define EF_ERASE_MIN_SIZE PKG_EASYFLASH_ERASE_GRAN + +/* the flash write granularity, unit: bit + * only support 1(nor flash)/ 8(stm32f4)/ 32(stm32f1)/ 64(stm32l4) */ +#define EF_WRITE_GRAN 64 +/** + * + * This all Backup Area Flash storage index. All used flash area configure is under here. + * |----------------------------| Storage Size + * | Environment variables area | ENV area size @see ENV_AREA_SIZE + * | 1.system section | ENV_SYSTEM_SIZE + * | 2:data section | ENV_AREA_SIZE - ENV_SYSTEM_SIZE + * |----------------------------| + * | Saved log area | Log area size @see LOG_AREA_SIZE + * |----------------------------| + * |(IAP)Downloaded application | IAP already downloaded application, unfixed size + * |----------------------------| + * + * @note all area sizes must be aligned with EF_ERASE_MIN_SIZE + * @note EasyFlash will use ram to buffer the ENV. At some point flash's EF_ERASE_MIN_SIZE may become so big, + * and you want to keep ENV size smaller. To do it you must define ENV_USER_SETTING_SIZE for ENV. + * @note ENV area size has some limitations in different modes. + * 1.Normal mode: no limitations + * 2.Wear leveling mode: system section will used a flash section and the data section will use at least 2 flash + * sections 3.Power fail safeguard mode: ENV area will has a backup. It is twice as normal mode. 4.Wear leveling and + * power fail safeguard mode: The required capacity will be 2 times the total capacity in wear leveling mode. For + * example: The EF_ERASE_MIN_SIZE is 128K and the ENV_USER_SETTING_SIZE: 2K. The ENV_AREA_SIZE in different mode you can + * define 1.Normal mode: 1*EF_ERASE_MIN_SIZE 2.Wear leveling mode: 3*EF_ERASE_MIN_SIZE (It has 2 data section to store + * ENV. So ENV can erase at least 200,000 times) 3.Power fail safeguard mode: 2*EF_ERASE_MIN_SIZE 4.Wear leveling and + * power fail safeguard mode: 6*EF_ERASE_MIN_SIZE + * @note the log area size must be more than twice of EF_ERASE_MIN_SIZE + */ +/* backup area start address */ +#define EF_START_ADDR PKG_EASYFLASH_START_ADDR + +#ifndef EF_ENV_USING_PFS_MODE +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in normal mode. */ +#define ENV_AREA_SIZE (1 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling mode. */ +#define ENV_AREA_SIZE (4 * EF_ERASE_MIN_SIZE) +#endif +#else +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in power fail safeguard mode. */ +#define ENV_AREA_SIZE (2 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling and power fail safeguard mode. */ +#define ENV_AREA_SIZE (6 * EF_ERASE_MIN_SIZE) +#endif +#endif + +/* print debug information of flash */ +#ifdef PKG_EASYFLASH_DEBUG +#define PRINT_DEBUG +#endif + +#endif /* EF_CFG_H_ */ diff --git a/templates/n32l406rbl7-1616n/board/ports/fal_cfg.c b/templates/n32l406rbl7-1616n/board/ports/fal_cfg.c new file mode 100644 index 0000000000000000000000000000000000000000..2a68fd1a31c0d97bca7f0db45015350365384598 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/ports/fal_cfg.c @@ -0,0 +1,27 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file fal_cfg.c + * + * @brief Flash abstract layer partition definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ +static const fal_part_info_t fal_part_info[] = { + /* part, flash, addr, size, lock */ + {"app", "onchip_flash", 0x00000000, 120*1024, FAL_PART_INFO_FLAGS_LOCKED}, + {"user", "onchip_flash", 120*1024, 8*1024, FAL_PART_INFO_FLAGS_UNLOCKED}, +}; diff --git a/templates/n32l406rbl7-1616n/board/ports/flash_info.c b/templates/n32l406rbl7-1616n/board/ports/flash_info.c new file mode 100644 index 0000000000000000000000000000000000000000..c8ee695c6133a1e017eb6e644e743b13c0a5f9b3 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/ports/flash_info.c @@ -0,0 +1,7 @@ +static struct onchip_flash_info flash_info = { + .start_addr = N32_FLASH_START_ADDR, + .capacity = N32_FLASH_SIZE, + .block_size = N32_FLASH_BLOCK_SIZE, + .page_size = N32_FLASH_PAGE_SIZE, +}; +OS_HAL_DEVICE_DEFINE("N32GL40X_Onchip_Flash", "onchip_flash", flash_info); diff --git a/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_arm.s b/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_arm.s new file mode 100644 index 0000000000000000000000000000000000000000..9f7e4e928f34727a1823c1378ad64dd94d0589f4 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_arm.s @@ -0,0 +1,375 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +___initial_sp + EXPORT ___initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +LCD_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_gcc.s b/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..19f6ee2d32fac934e498d9981c7a8f45e5c9640b --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/startup/startup_n32l40x_gcc.s @@ -0,0 +1,421 @@ +/** +****************************************************************************** +* @file startup_n32l40x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT Nations Technologies Inc *****END OF FILE****/ diff --git a/templates/n32l406rbl7-1616n/board/weave.yaml b/templates/n32l406rbl7-1616n/board/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a68100a2eae3e6f61d0027138061a2df2094aed0 --- /dev/null +++ b/templates/n32l406rbl7-1616n/board/weave.yaml @@ -0,0 +1,22 @@ +# 组名 +group_name: bsp + +# 编译连接信息 +build_option: + cpppath: + - . + - ports + cppdefines: + - N32L40X + - HSE_VALUE=25000000 + - SYSCLK_FREQ=100000000 + +# 源码 +source_file: + - board.c + - startup/startup_n32l40x_gcc.s ? {is_compiler("gcc")} + - startup/startup_n32l40x_arm.s ? {is_compiler("armcc")} + +# 子目录 +add_subdirectory: + - ./* \ No newline at end of file diff --git a/templates/n32l406rbl7-1616n/oneos_config.h b/templates/n32l406rbl7-1616n/oneos_config.h new file mode 100644 index 0000000000000000000000000000000000000000..f78e56585745e218d7188e745e584379680b1e17 --- /dev/null +++ b/templates/n32l406rbl7-1616n/oneos_config.h @@ -0,0 +1,537 @@ +#ifndef __ONEOS_CONFIG_H__ +#define __ONEOS_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ +#define BOARD_N32L406RBL7_MXIO_1616N +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* Kernel */ + +#define OS_NAME_MAX_15 +#define OS_NAME_MAX 15 +#define OS_TASK_PRIORITY_32 +#define OS_TASK_PRIORITY_MAX 32 +#define OS_TICK_PER_SECOND 1000 +#define OS_SCHEDULE_TIME_SLICE 10 +#define OS_USING_OVERFLOW_CHECK +#define OS_USING_KERNEL_DEBUG +#define KLOG_GLOBAL_LEVEL_WARNING +#define KLOG_GLOBAL_LEVEL 1 +#define KLOG_USING_COLOR +#define KLOG_WITH_FUNC_LINE +#define OS_MAIN_TASK_STACK_SIZE 2048 +#define OS_IDLE_TASK_STACK_SIZE 512 +#define OS_RECYCLE_TASK_STACK_SIZE 512 +#define OS_USING_TIMER +#define OS_TIMER_TASK_STACK_SIZE 512 +#define OS_TIMER_POWER 3 +#define OS_USING_WORKQUEUE +#define OS_USING_SYSTEM_WORKQUEUE +#define OS_SYSTEM_WORKQUEUE_STACK_SIZE 2048 +#define OS_SYSTEM_WORKQUEUE_PRIORITY 0 + +/* Inter-task communication and synchronization */ + +#define OS_USING_MUTEX +#define OS_USING_SEMAPHORE +/* end of Inter-task communication and synchronization */ + +/* Memory management */ + +#define OS_USING_SYS_HEAP +#define OS_USING_MEM_HEAP +#define OS_USING_ALG_FIRSTFIT +/* end of Memory management */ +/* end of Kernel */ + +/* C standard library adapter */ + +#define OS_USING_LIBC_ADAPTER +#define OS_USING_NEWLIB_ADAPTER +#define OS_USING_ARMCCLIB_ADAPTER +/* end of C standard library adapter */ + +/* Osal */ + +/* POSIX compatibility layer */ + +/* end of POSIX compatibility layer */ + +/* RT-Thread compatibility layer */ + +/* end of RT-Thread compatibility layer */ + +/* CMSIS compatibility layer */ + +/* end of CMSIS compatibility layer */ + +/* FreeRTOS compatibility layer */ + +/* end of FreeRTOS compatibility layer */ + +/* C++ Features */ + +/* end of C++ Features */ +/* end of Osal */ + +/* Drivers */ + +#define OS_USING_DEVICE +#define OS_USING_DEVICE_NOTIFY + +/* Audio */ + +/* end of Audio */ + +/* BLOCK */ + +#define OS_USING_BLOCK +/* end of BLOCK */ + +/* Boot */ + +/* CORTEX-M Boot */ + +#define BSP_INCLUDE_VECTOR_TABLE +/* end of CORTEX-M Boot */ +/* end of Boot */ + +/* CAN */ + +/* end of CAN */ + +/* CONSOLE */ + +#define OS_USING_CONSOLE +#define OS_CONSOLE_DEVICE_NAME "usart1" +/* end of CONSOLE */ + +/* DMA */ + +#define OS_USING_DMA +#define OS_USING_DMA_RAM +#define OS_USING_SOFT_DMA +#define OS_SOFT_DMA_SUPPORT_NORMAL_MODE +#define OS_SOFT_DMA_SUPPORT_CIRCLE_MODE +#define OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT +/* end of DMA */ + +/* EEPROM */ + +/* end of EEPROM */ + +/* FAL */ + +#define OS_USING_FAL +/* end of FAL */ + +/* Graphic */ + +/* end of Graphic */ + +/* HAL */ + +#define MANUFACTOR_NATIONSTECH +#define SERIES_N32L40X +#define SOC_N32L406RBL7 +#define BSP_USING_GPIO +#define BSP_USING_LED +#define BSP_USING_USART +#define BSP_USING_ONCHIP_FLASH +#define BSP_USING_TIMER +/* end of HAL */ + +/* HwCrypto */ + +/* end of HwCrypto */ + +/* I2C */ + +/* end of I2C */ + +/* Infrared */ + +/* end of Infrared */ + +/* LPMGR */ + +/* end of LPMGR */ + +/* MISC */ + +#define OS_USING_PUSH_BUTTON +#define OS_USING_LED +/* end of MISC */ + +/* MTD */ + +/* end of MTD */ + +/* NAND */ + +/* end of NAND */ + +/* NET */ + +/* end of NET */ + +/* PIN */ + +#define OS_USING_PIN +#define OS_PIN_MAX_CHIP 1 +/* end of PIN */ + +/* RTC */ + +/* end of RTC */ + +/* SDIO */ + +/* end of SDIO */ + +/* Sensors */ + +/* end of Sensors */ + +/* Serial */ + +#define OS_USING_SERIAL +#define OS_SERIAL_DELAY_CLOSE +#define OS_SERIAL_RX_BUFSZ 64 +#define OS_SERIAL_TX_BUFSZ 64 + +/* posix serial */ + +/* end of posix serial */ + +/* rtt uart */ + +/* end of rtt uart */ +/* end of Serial */ + +/* SFLASH */ + +/* end of SFLASH */ + +/* SN */ + +/* end of SN */ + +/* SPI */ + +/* end of SPI */ + +/* Timer */ + +#define OS_USING_TIMER_DRIVER +#define OS_USING_CLOCKSOURCE +#define OS_CLOCKSOURCE_BEST "" + +/* cortex-m & riscv hardware timer config */ + +#define OS_USING_SYSTICK_FOR_KERNEL_TICK +#define OS_USING_DWT_FOR_CLOCKSOURCE +/* end of cortex-m & riscv hardware timer config */ +/* end of Timer */ + +/* TinyUSB */ + +/* end of TinyUSB */ + +/* Touch */ + +/* end of Touch */ + +/* USB */ + +/* end of USB */ + +/* WDG */ + +/* end of WDG */ +/* end of Drivers */ + +/* Components */ + +/* MicroPython */ + +/* end of MicroPython */ + +/* WWD */ + +/* end of WWD */ + +/* AMS */ + +/* end of AMS */ + +/* Atest */ + +/* end of Atest */ + +/* BLE */ + +/* end of BLE */ + +/* cJSON */ + +/* end of cJSON */ + +/* CLI */ + +/* end of CLI */ + +/* Cloud */ + +/* Aliyun */ + +/* end of Aliyun */ + +/* AWS */ + +/* end of AWS */ + +/* Baidu */ + +/* end of Baidu */ + +/* CTWing */ + +/* MQTT */ + +/* end of MQTT */ +/* end of CTWing */ + +/* Huawei */ + +/* end of Huawei */ + +/* OneNET */ + +/* MQTT kit */ + +/* end of MQTT kit */ + +/* NB-IoT kit */ + +/* end of NB-IoT kit */ + +/* EDP */ + +/* end of EDP */ +/* end of OneNET */ +/* end of Cloud */ + +/* CMS */ + +#define CMS_LITE + +/* CMS Connect */ + +/* end of CMS Connect */ + +/* CMS ID */ + +/* end of CMS ID */ +/* end of CMS */ + +/* Diagnose */ + + +/* eCoreDump */ + +/* end of eCoreDump */ + +/* Memory Monitor */ + +/* end of Memory Monitor */ +/* end of Diagnose */ + +/* Dlog */ + +#define OS_USING_DLOG +#define DLOG_PRINT_LVL_W +#define DLOG_GLOBAL_PRINT_LEVEL 4 +#define DLOG_COMPILE_LVL_D +#define DLOG_COMPILE_LEVEL 7 +#define DLOG_USING_ISR_LOG +#define DLOG_USING_FILTER +#define DLOG_USING_ASYNC_OUTPUT +#define DLOG_ASYNC_OUTPUT_BUF_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_PRIORITY 20 + +/* Log format */ + +#define DLOG_WITH_FUNC_LINE +#define DLOG_USING_COLOR +#define DLOG_OUTPUT_TIME_INFO +/* end of Log format */ + +/* Dlog backend option */ + +#define DLOG_BACKEND_USING_CONSOLE +/* end of Dlog backend option */ +/* end of Dlog */ + +/* Easyflash */ + +/* end of Easyflash */ + +/* FileSystem */ + +/* end of FileSystem */ + +/* GUI */ + +#define OS_GUI_DISP_DEV_NAME "lcd" +#define OS_GUI_INPUT_DEV_NAME "touch" +/* end of GUI */ + +/* Industrial */ + +/* CANOpen */ + +/* end of CANOpen */ + +/* CoDeSys */ + +/* end of CoDeSys */ + +/* ModBus */ + +/* end of ModBus */ + +/* PROFINET */ + +/* end of PROFINET */ +/* end of Industrial */ + +/* IoTjs */ + +/* end of IoTjs */ + +/* JerryScript */ + +/* end of JerryScript */ + +/* Network */ + +/* Acw */ + +/* end of Acw */ + +/* TCP/IP */ + +/* LwIP */ + +/* end of LwIP */ +/* end of TCP/IP */ + +/* Molink */ + +/* end of Molink */ + +/* Protocols */ + +/* CoAP */ + +/* end of CoAP */ + +/* HTTP */ + +/* httpclient-v1.1.0 */ + +/* end of httpclient-v1.1.0 */ +/* end of HTTP */ + +/* LWM2M */ + +/* LWM2M-v1.0.0 */ + +/* end of LWM2M-v1.0.0 */ +/* end of LWM2M */ + +/* MQTT */ + +/* end of MQTT */ + +/* Websocket */ + +/* end of Websocket */ +/* end of Protocols */ + +/* Socket */ + +/* end of Socket */ +/* end of Network */ + +/* Iotivity */ + +/* end of Iotivity */ + +/* Optparse */ + +/* end of Optparse */ + +/* OTA */ + +/* Fota by CMIOT */ + +/* end of Fota by CMIOT */ +/* end of OTA */ + +/* Position */ + +/* end of Position */ + +/* PowerManager */ + +/* end of PowerManager */ + +/* Ramdisk */ + +/* end of Ramdisk */ + +/* Security */ + + +/* OneTLS */ + +/* end of OneTLS */ +/* end of Security */ + +/* Shell */ + +#define OS_USING_SHELL +#define SHELL_TASK_NAME "tshell" +#define SHELL_TASK_PRIORITY 20 +#define SHELL_TASK_STACK_SIZE 2048 +#define SHELL_USING_HISTORY +#define SHELL_HISTORY_LINES 5 +#define SHELL_USING_DESCRIPTION +#define SHELL_CMD_SIZE 80 +#define SHELL_PROMPT_SIZE 256 +#define SHELL_ARG_MAX 10 +/* end of Shell */ + +/* SQL */ + +/* end of SQL */ + +/* telnetd */ + +/* end of telnetd */ +/* end of Components */ + +/* Debug */ + +#define OS_DEBUG +#define LOG_BUFF_SIZE_256 +#define OS_LOG_BUFF_SIZE 256 +/* end of Debug */ + +#endif /* __ONEOS_CONFIG_H__ */ + diff --git a/templates/n32l406rbl7-1616n/osconfig.py b/templates/n32l406rbl7-1616n/osconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..f4b271be0d5da7e937218bfacb0f025d66a73970 --- /dev/null +++ b/templates/n32l406rbl7-1616n/osconfig.py @@ -0,0 +1,149 @@ +import os + +# toolchains options +ARCH = 'arm' +CPU = 'cortex-m4' +CROSS_TOOL = 'gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('OS_CC'): + CROSS_TOOL = os.getenv('OS_CC') +if os.getenv('OS_ROOT'): + OS_ROOT = os.getenv('OS_ROOT') + +# cross_tool provides the cross compiler +# COMPILER_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + COMPILER = 'gcc' + COMPILER_PATH = '' +elif CROSS_TOOL == 'keil': + COMPILER = 'armcc' + # Notice: The installation path of armcc cannot have Chinese + COMPILER_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + COMPILER = 'iar' + COMPILER_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + + +if COMPILER == 'gcc': + # "BUILD" can be: 'debug_O0', 'release_O2' or 'release_Os' + BUILD = 'debug_O0' +else: + BUILD = 'debug' + +if COMPILER == 'gcc': + # toolchains + if COMPILER_PATH == '': + COMPILER_PATH = os.getenv('OS_EXEC_PATH') + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + RESULT_SUFFIX = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -L $OS_ROOT/drivers/link/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug_O0': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + elif BUILD == 'release_O2': + CFLAGS += ' -O2' + else: + CFLAGS += ' -Os' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -R .reserved_ram -O binary $TARGET oneos.bin\n' + SIZE + ' $TARGET \n' + +elif COMPILER == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + RESULT_SUFFIX = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --split_sections --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list oneos.map --strict' + CFLAGS += ' -I "' + COMPILER_PATH + '/ARM/ARMCC/include"' + LFLAGS += ' --libpath="' + COMPILER_PATH + '/ARM/ARMCC/lib"' + + #CFLAGS += ' -D__MICROLIB ' + #AFLAGS += ' --pd "__MICROLIB SETA 1" ' + #LFLAGS += ' --library_type=microlib ' + COMPILER_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output oneos.bin \nfromelf -z $TARGET' + +elif COMPILER == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + RESULT_SUFFIX = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + COMPILER_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + COMPILER_PATH = COMPILER_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET oneos.bin' diff --git a/templates/n32l406rbl7-1616n/project.uvoptx b/templates/n32l406rbl7-1616n/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..3d230f73566e1ba7e3bf0a33577aaa2d7605fc8e --- /dev/null +++ b/templates/n32l406rbl7-1616n/project.uvoptx @@ -0,0 +1,1469 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L40x -FL020000 -FS08000000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U0700000000110041330000194e4c5741 -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0N32L40x.FLM -FS08000000 -FL020000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + application + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + application\main.c + main.c + 0 + 0 + + + + + arch + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_atomic.c + arch_atomic.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_exception.c + arch_exception.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + arch_exception_rvds.S + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_interrupt.c + arch_interrupt.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_misc.c + arch_misc.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_task.c + arch_task.c + 0 + 0 + + + 2 + 8 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + arch_task_switch_rvds.S + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + board\peripherals\peripherals.c + peripherals.c + 0 + 0 + + + 3 + 11 + 2 + 0 + 0 + 0 + board\startup\startup_n32l40x.s + startup_n32l40x.s + 0 + 0 + + + + + cli + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli.c + cli.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_cms.c + cli_cms.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_lwip.c + cli_lwip.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_molink.c + cli_molink.c + 0 + 0 + + + + + common + 0 + 0 + 0 + 0 + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\common\source\option_parse.c + option_parse.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_blk_buff.c + ring_blk_buff.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_buff.c + ring_buff.c + 0 + 0 + + + + + dlog + 0 + 0 + 0 + 0 + + 6 + 19 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\backend\console_backend.c + console_backend.c + 0 + 0 + + + 6 + 20 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\dlog.c + dlog.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 7 + 21 + 1 + 0 + 0 + 0 + ..\..\drivers\block\block_device.c + block_device.c + 0 + 0 + + + 7 + 22 + 1 + 0 + 0 + 0 + ..\..\drivers\bus\bus.c + bus.c + 0 + 0 + + + 7 + 23 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource.c + clocksource.c + 0 + 0 + + + 7 + 24 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource_cortexm.c + clocksource_cortexm.c + 0 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + ..\..\drivers\console\console.c + console.c + 0 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + ..\..\drivers\device.c + device.c + 0 + 0 + + + 7 + 27 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\dma_ram.c + dma_ram.c + 0 + 0 + + + 7 + 28 + 1 + 0 + 0 + 0 + ..\..\drivers\driver.c + driver.c + 0 + 0 + + + 7 + 29 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal.c + fal.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_block.c + fal_block.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_part.c + fal_part.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\drivers\pin\pin.c + pin.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\drivers\misc\push_button.c + push_button.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\soft_dma.c + soft_dma.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\timer.c + timer.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\drivers\boot\cotex-m\vector_table.c + vector_table.c + 0 + 0 + + + + + hal/drivers + 0 + 0 + 0 + 0 + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_common.c + drv_common.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_usart.c + drv_usart.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l40x\n32_it.c + n32_it.c + 0 + 0 + + + + + hal/lowlevel + 0 + 0 + 0 + 0 + + 9 + 42 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 9 + 43 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_dma.c + n32l40x_dma.c + 0 + 0 + + + 9 + 44 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_exti.c + n32l40x_exti.c + 0 + 0 + + + 9 + 45 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_flash.c + n32l40x_flash.c + 0 + 0 + + + 9 + 46 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_gpio.c + n32l40x_gpio.c + 0 + 0 + + + 9 + 47 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_rcc.c + n32l40x_rcc.c + 0 + 0 + + + 9 + 48 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_tim.c + n32l40x_tim.c + 0 + 0 + + + 9 + 49 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_usart.c + n32l40x_usart.c + 0 + 0 + + + 9 + 50 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L40x\CMSIS\device\system_n32l40x.c + system_n32l40x.c + 0 + 0 + + + + + kernel + 0 + 0 + 0 + 0 + + 10 + 51 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_block.c + os_block.c + 0 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_clock.c + os_clock.c + 0 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_idle.c + os_idle.c + 0 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_lock.c + os_kernel_lock.c + 0 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_log.c + os_kernel_log.c + 0 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mem_firstfit.c + os_mem_firstfit.c + 0 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_memory.c + os_memory.c + 0 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mutex.c + os_mutex.c + 0 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sched.c + os_sched.c + 0 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sem.c + os_sem.c + 0 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_spinlock.c + os_spinlock.c + 0 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_startup.c + os_startup.c + 0 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_task.c + os_task.c + 0 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_timer_hash.c + os_timer_hash.c + 0 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_util.c + os_util.c + 0 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_version.c + os_version.c + 0 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_workqueue.c + os_workqueue.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 11 + 68 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\access.c + access.c + 0 + 0 + + + 11 + 69 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\chdir.c + chdir.c + 0 + 0 + + + 11 + 70 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\close.c + close.c + 0 + 0 + + + 11 + 71 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\dirent.c + dirent.c + 0 + 0 + + + 11 + 72 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fcntl.c + fcntl.c + 0 + 0 + + + 11 + 73 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fstat.c + fstat.c + 0 + 0 + + + 11 + 74 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fsync.c + fsync.c + 0 + 0 + + + 11 + 75 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\getcwd.c + getcwd.c + 0 + 0 + + + 11 + 76 + 1 + 0 + 0 + 0 + ..\..\libc\source\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + 11 + 77 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\ioctl.c + ioctl.c + 0 + 0 + + + 11 + 78 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\libc.c + libc.c + 0 + 0 + + + 11 + 79 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\lseek.c + lseek.c + 0 + 0 + + + 11 + 80 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 11 + 81 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mkdir.c + mkdir.c + 0 + 0 + + + 11 + 82 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\open.c + open.c + 0 + 0 + + + 11 + 83 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\read.c + read.c + 0 + 0 + + + 11 + 84 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rename.c + rename.c + 0 + 0 + + + 11 + 85 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rmdir.c + rmdir.c + 0 + 0 + + + 11 + 86 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stat.c + stat.c + 0 + 0 + + + 11 + 87 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\statfs.c + statfs.c + 0 + 0 + + + 11 + 88 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stdio.c + stdio.c + 0 + 0 + + + 11 + 89 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strdup.c + strdup.c + 0 + 0 + + + 11 + 90 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strnlen.c + strnlen.c + 0 + 0 + + + 11 + 91 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stubs.c + stubs.c + 0 + 0 + + + 11 + 92 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\time.c + time.c + 0 + 0 + + + 11 + 93 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\unlink.c + unlink.c + 0 + 0 + + + 11 + 94 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\write.c + write.c + 0 + 0 + + + + + shell + 0 + 0 + 0 + 0 + + 12 + 95 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_buildin_cmd.c + shell_buildin_cmd.c + 0 + 0 + + + 12 + 96 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_main.c + shell_main.c + 0 + 0 + + + 12 + 97 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_process.c + shell_process.c + 0 + 0 + + + 12 + 98 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_symbol.c + shell_symbol.c + 0 + 0 + + + + diff --git a/templates/n32l406rbl7-1616n/project.uvprojx b/templates/n32l406rbl7-1616n/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..bac2b19f26c9e3e3af45eb343d2345f7ca26b9fd --- /dev/null +++ b/templates/n32l406rbl7-1616n/project.uvprojx @@ -0,0 +1,953 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32L406RB + Nationstech + Nationstech.N32L40x_DFP.0.1.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x6000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32L40x -FS08000000 -FL020000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM)) + 0 + $$Device:N32L406RB$firmware\CMSIS\device\n32l40x.h + + + + + + + + + + $$Device:N32L406RB$svd\N32L406.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + N32G45X, OS_TASK_SWITCH_NOTIFY + + .;..\..\components\uai\library;..\..\arch\arm\armv7m\include;board;board\ports;board\peripherals;..\..\components\cli\include;..\..\common\include;..\..\components\dlog\include;..\..\drivers;..\..\drivers\boot\cotex-m;..\..\drivers\bus;..\..\drivers\console;..\..\drivers\dma;..\..\drivers\fal;..\..\drivers\misc;..\..\drivers\pin;..\..\drivers\serial;..\..\drivers\timer;..\..\components\diagnose\eCoreDump;..\..\drivers\hal\nationstech\drivers\n32l40x;..\..\drivers\hal\nationstech\drivers\n32l40x\flash;..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\inc;..\..\drivers\hal\nationstech\N32L40x\CMSIS\core;..\..\drivers\hal\nationstech\N32L40x\CMSIS\device;..\..\kernel\include;..\..\libc\include;..\..\libc\include\extension;..\..\libc\include\armlibc;..\..\components\shell\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + OS_TASK_SWITCH_NOTIFY + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress L6314,L6330 + + + + + + + + application + + + main.c + 1 + application\main.c + + + + + arch + + + arch_atomic.c + 1 + ..\..\arch\arm\armv7m\arch_atomic.c + + + arch_exception.c + 1 + ..\..\arch\arm\armv7m\arch_exception.c + + + arch_exception_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + + + arch_interrupt.c + 1 + ..\..\arch\arm\armv7m\arch_interrupt.c + + + arch_misc.c + 1 + ..\..\arch\arm\armv7m\arch_misc.c + + + arch_task.c + 1 + ..\..\arch\arm\armv7m\arch_task.c + + + arch_task_switch_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + + + + + bsp + + + board.c + 1 + board\board.c + + + peripherals.c + 1 + board\peripherals\peripherals.c + + + startup_n32l40x.s + 2 + board\startup\startup_n32l40x.s + + + + + cli + + + cli.c + 1 + ..\..\components\cli\source\cli.c + + + cli_cms.c + 1 + ..\..\components\cli\source\cli_cms.c + + + cli_lwip.c + 1 + ..\..\components\cli\source\cli_lwip.c + + + cli_molink.c + 1 + ..\..\components\cli\source\cli_molink.c + + + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_common.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\misc.c + + + n32l40x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_dma.c + + + n32l40x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_exti.c + + + n32l40x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_flash.c + + + n32l40x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_gpio.c + + + n32l40x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_rcc.c + + + n32l40x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_tim.c + + + n32l40x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_usart.c + + + system_n32l40x.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\CMSIS\device\system_n32l40x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/n32l406rbl7-1616n/settings-gcc.yaml b/templates/n32l406rbl7-1616n/settings-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c764ee1dabe7c2e958b9035f0565d981e7514cb3 --- /dev/null +++ b/templates/n32l406rbl7-1616n/settings-gcc.yaml @@ -0,0 +1,27 @@ +# 编译选项（支持条件表达式） +option: + cflags: # General options that are passed to the C compiler (C only; not C++). + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + cxxflags: # General options that are passed to the C++ compiler. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + asflags: # General options passed to the assembler. + - ' -c' + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + - ' -gdwarf-2 ? {is_mode(''O0'')}' + linkflags: # General user options passed to the linker. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + +# 构建前/后动作（支持条件表达式） +action: + prebuild: + - 'script:sys.path.append("$OS_ROOT" + "/drivers/hal/nationstech/scripts/");import prebuild;prebuild.prebuild("$PRO_ROOT")' \ No newline at end of file diff --git a/templates/n32l406rbl7-1616n/template.uvoptx b/templates/n32l406rbl7-1616n/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..3d230f73566e1ba7e3bf0a33577aaa2d7605fc8e --- /dev/null +++ b/templates/n32l406rbl7-1616n/template.uvoptx @@ -0,0 +1,1469 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L40x -FL020000 -FS08000000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U0700000000110041330000194e4c5741 -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0N32L40x.FLM -FS08000000 -FL020000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + application + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + application\main.c + main.c + 0 + 0 + + + + + arch + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_atomic.c + arch_atomic.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_exception.c + arch_exception.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + arch_exception_rvds.S + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_interrupt.c + arch_interrupt.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_misc.c + arch_misc.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + 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11 + 78 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\libc.c + libc.c + 0 + 0 + + + 11 + 79 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\lseek.c + lseek.c + 0 + 0 + + + 11 + 80 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 11 + 81 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mkdir.c + mkdir.c + 0 + 0 + + + 11 + 82 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\open.c + open.c + 0 + 0 + + + 11 + 83 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\read.c + read.c + 0 + 0 + + + 11 + 84 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rename.c + rename.c + 0 + 0 + + + 11 + 85 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rmdir.c + rmdir.c + 0 + 0 + + + 11 + 86 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stat.c + stat.c + 0 + 0 + + + 11 + 87 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\statfs.c + statfs.c + 0 + 0 + + + 11 + 88 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stdio.c + stdio.c + 0 + 0 + + + 11 + 89 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strdup.c + strdup.c + 0 + 0 + + + 11 + 90 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strnlen.c + strnlen.c + 0 + 0 + + + 11 + 91 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stubs.c + stubs.c + 0 + 0 + + + 11 + 92 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\time.c + time.c + 0 + 0 + + + 11 + 93 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\unlink.c + unlink.c + 0 + 0 + + + 11 + 94 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\write.c + write.c + 0 + 0 + + + + + shell + 0 + 0 + 0 + 0 + + 12 + 95 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_buildin_cmd.c + shell_buildin_cmd.c + 0 + 0 + + + 12 + 96 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_main.c + shell_main.c + 0 + 0 + + + 12 + 97 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_process.c + shell_process.c + 0 + 0 + + + 12 + 98 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_symbol.c + shell_symbol.c + 0 + 0 + + + + diff --git a/templates/n32l406rbl7-1616n/template.uvprojx b/templates/n32l406rbl7-1616n/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..bac2b19f26c9e3e3af45eb343d2345f7ca26b9fd --- /dev/null +++ b/templates/n32l406rbl7-1616n/template.uvprojx @@ -0,0 +1,953 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32L406RB + Nationstech + Nationstech.N32L40x_DFP.0.1.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x6000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32L40x -FS08000000 -FL020000 -FP0($$Device:N32L406RB$Flash\N32L40x.FLM)) + 0 + $$Device:N32L406RB$firmware\CMSIS\device\n32l40x.h + + + + + + + + + + $$Device:N32L406RB$svd\N32L406.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + N32G45X, OS_TASK_SWITCH_NOTIFY + + .;..\..\components\uai\library;..\..\arch\arm\armv7m\include;board;board\ports;board\peripherals;..\..\components\cli\include;..\..\common\include;..\..\components\dlog\include;..\..\drivers;..\..\drivers\boot\cotex-m;..\..\drivers\bus;..\..\drivers\console;..\..\drivers\dma;..\..\drivers\fal;..\..\drivers\misc;..\..\drivers\pin;..\..\drivers\serial;..\..\drivers\timer;..\..\components\diagnose\eCoreDump;..\..\drivers\hal\nationstech\drivers\n32l40x;..\..\drivers\hal\nationstech\drivers\n32l40x\flash;..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\inc;..\..\drivers\hal\nationstech\N32L40x\CMSIS\core;..\..\drivers\hal\nationstech\N32L40x\CMSIS\device;..\..\kernel\include;..\..\libc\include;..\..\libc\include\extension;..\..\libc\include\armlibc;..\..\components\shell\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + OS_TASK_SWITCH_NOTIFY + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress L6314,L6330 + + + + + + + + application + + + main.c + 1 + application\main.c + + + + + arch + + + arch_atomic.c + 1 + ..\..\arch\arm\armv7m\arch_atomic.c + + + arch_exception.c + 1 + ..\..\arch\arm\armv7m\arch_exception.c + + + arch_exception_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + + + arch_interrupt.c + 1 + ..\..\arch\arm\armv7m\arch_interrupt.c + + + arch_misc.c + 1 + ..\..\arch\arm\armv7m\arch_misc.c + + + arch_task.c + 1 + ..\..\arch\arm\armv7m\arch_task.c + + + arch_task_switch_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + + + + + bsp + + + board.c + 1 + board\board.c + + + peripherals.c + 1 + board\peripherals\peripherals.c + + + startup_n32l40x.s + 2 + board\startup\startup_n32l40x.s + + + + + cli + + + cli.c + 1 + ..\..\components\cli\source\cli.c + + + cli_cms.c + 1 + ..\..\components\cli\source\cli_cms.c + + + cli_lwip.c + 1 + ..\..\components\cli\source\cli_lwip.c + + + cli_molink.c + 1 + ..\..\components\cli\source\cli_molink.c + + + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_common.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l40x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\misc.c + + + n32l40x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_dma.c + + + n32l40x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_exti.c + + + n32l40x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_flash.c + + + n32l40x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_gpio.c + + + n32l40x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_rcc.c + + + n32l40x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_tim.c + + + n32l40x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\n32l40x_std_periph_driver\src\n32l40x_usart.c + + + system_n32l40x.c + 1 + ..\..\drivers\hal\nationstech\N32L40x\CMSIS\device\system_n32l40x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/n32l436rbl7-1616n/.config b/templates/n32l436rbl7-1616n/.config new file mode 100644 index 0000000000000000000000000000000000000000..f493b51068c8dc5f1ac6e0a85488951b9b26b666 --- /dev/null +++ b/templates/n32l436rbl7-1616n/.config @@ -0,0 +1,800 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) +CONFIG_BOARD_N32L406RBL7_MXIO_1616N=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# Kernel +# +# CONFIG_OS_NAME_MAX_7 is not set +CONFIG_OS_NAME_MAX_15=y +# CONFIG_OS_NAME_MAX_31 is not set +CONFIG_OS_NAME_MAX=15 +# CONFIG_OS_TASK_PRIORITY_8 is not set +# CONFIG_OS_TASK_PRIORITY_16 is not set +CONFIG_OS_TASK_PRIORITY_32=y +# CONFIG_OS_TASK_PRIORITY_64 is not set +# CONFIG_OS_TASK_PRIORITY_128 is not set +# CONFIG_OS_TASK_PRIORITY_256 is not set +CONFIG_OS_TASK_PRIORITY_MAX=32 +CONFIG_OS_TICK_PER_SECOND=1000 +CONFIG_OS_SCHEDULE_TIME_SLICE=10 +CONFIG_OS_USING_OVERFLOW_CHECK=y +# CONFIG_OS_USING_INTERRUPT_STACK_OVERFLOW_CHECK is not set +# CONFIG_OS_USING_TASK_HOOK is not set +# CONFIG_OS_USING_ASSERT is not set +# CONFIG_OS_USING_KERNEL_LOCK_CHECK is not set +# CONFIG_OS_USING_SAFETY_MECHANISM is not set +CONFIG_OS_USING_KERNEL_DEBUG=y +# CONFIG_KLOG_GLOBAL_LEVEL_ERROR is not set +CONFIG_KLOG_GLOBAL_LEVEL_WARNING=y +# CONFIG_KLOG_GLOBAL_LEVEL_INFO is not set +# CONFIG_KLOG_GLOBAL_LEVEL_DEBUG is not set +CONFIG_KLOG_GLOBAL_LEVEL=1 +CONFIG_KLOG_USING_COLOR=y +CONFIG_KLOG_WITH_FUNC_LINE=y +CONFIG_OS_MAIN_TASK_STACK_SIZE=2048 +CONFIG_OS_IDLE_TASK_STACK_SIZE=512 +CONFIG_OS_RECYCLE_TASK_STACK_SIZE=512 +CONFIG_OS_USING_TIMER=y +CONFIG_OS_TIMER_TASK_STACK_SIZE=512 +CONFIG_OS_TIMER_POWER=3 +# CONFIG_OS_TIMER_SORT is not set +CONFIG_OS_USING_WORKQUEUE=y +CONFIG_OS_USING_SYSTEM_WORKQUEUE=y +CONFIG_OS_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_OS_SYSTEM_WORKQUEUE_PRIORITY=0 + +# +# Inter-task communication and synchronization +# +CONFIG_OS_USING_MUTEX=y +# CONFIG_OS_USING_SPINLOCK_CHECK is not set +CONFIG_OS_USING_SEMAPHORE=y +# CONFIG_OS_SEM_WAIT_HOOK is not set +# CONFIG_OS_SEM_POST_HOOK is not set +# CONFIG_OS_USING_EVENT is not set +# CONFIG_OS_USING_MESSAGEQUEUE is not set +# CONFIG_OS_USING_MAILBOX is not set +# end of Inter-task communication and synchronization + +# +# Memory management +# +CONFIG_OS_USING_SYS_HEAP=y +CONFIG_OS_USING_MEM_HEAP=y +CONFIG_OS_USING_ALG_FIRSTFIT=y +# CONFIG_OS_USING_ALG_BUDDY is not set +# CONFIG_OS_USING_MEM_TRACE is not set +# CONFIG_OS_USING_MEM_POOL is not set +# end of Memory management + +# CONFIG_OS_USING_IPC_TRACE is not set +# CONFIG_OS_USING_IPC_HOOK is not set +# end of Kernel + +# +# C standard library adapter +# +CONFIG_OS_USING_LIBC_ADAPTER=y +CONFIG_OS_USING_NEWLIB_ADAPTER=y +CONFIG_OS_USING_ARMCCLIB_ADAPTER=y +# end of C standard library adapter + +# +# Osal +# + +# +# POSIX compatibility layer +# +# CONFIG_OS_USING_PTHREADS is not set +# end of POSIX compatibility layer + +# +# RT-Thread compatibility layer +# +# CONFIG_OS_USING_RTTHREAD_API_V3_1_3 is not set +# end of RT-Thread compatibility layer + +# +# CMSIS compatibility layer +# +# CONFIG_OS_USING_CMSIS_RTOS2_API_V2_1_2 is not set +# end of CMSIS compatibility layer + +# +# FreeRTOS compatibility layer +# +# CONFIG_OS_USING_FREERTOS_API_V10_4_3 is not set +# end of FreeRTOS compatibility layer + +# +# C++ Features +# +# CONFIG_OS_USING_CPLUSPLUS is not set +# end of C++ Features +# end of Osal + +# +# Drivers +# +CONFIG_OS_USING_DEVICE=y +CONFIG_OS_USING_DEVICE_NOTIFY=y +# CONFIG_OS_DEVICE_SUPPORT_PLUG is not set + +# +# Audio +# +# CONFIG_OS_USING_AUDIO is not set +# end of Audio + +# +# BLOCK +# +CONFIG_OS_USING_BLOCK=y +# end of BLOCK + +# +# Boot +# + +# +# CORTEX-M Boot +# +CONFIG_BSP_INCLUDE_VECTOR_TABLE=y +# CONFIG_BSP_BOOT_OPTION is not set +# end of CORTEX-M Boot +# end of Boot + +# +# CAN +# +# CONFIG_OS_USING_CAN is not set +# end of CAN + +# +# CONSOLE +# +CONFIG_OS_USING_CONSOLE=y +CONFIG_OS_CONSOLE_DEVICE_NAME="usart1" +# end of CONSOLE + +# +# DMA +# +CONFIG_OS_USING_DMA=y +CONFIG_OS_USING_DMA_RAM=y +CONFIG_OS_USING_SOFT_DMA=y +CONFIG_OS_SOFT_DMA_SUPPORT_NORMAL_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_CIRCLE_MODE=y +CONFIG_OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT=y +# end of DMA + +# +# EEPROM +# +# CONFIG_OS_EEPROM_SUPPORT is not set +# end of EEPROM + +# +# FAL +# +CONFIG_OS_USING_FAL=y +# CONFIG_OS_FAL_RAM is not set +# end of FAL + +# +# Graphic +# +# CONFIG_OS_USING_GRAPHIC is not set +# end of Graphic + +# +# HAL +# +CONFIG_MANUFACTOR_NATIONSTECH=y +CONFIG_SERIES_N32L40X=y +CONFIG_SOC_N32L406RBL7=y +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_USART=y +CONFIG_BSP_USING_ONCHIP_FLASH=y +CONFIG_BSP_USING_TIMER=y +# end of HAL + +# +# HwCrypto +# +# CONFIG_OS_USING_HWCRYPTO is not set +# end of HwCrypto + +# +# I2C +# +# CONFIG_OS_USING_I2C is not set +# end of I2C + +# +# Infrared +# +# CONFIG_OS_USING_INFRARED is not set +# end of Infrared + +# +# LPMGR +# +# CONFIG_OS_USING_LPMGR is not set +# end of LPMGR + +# +# MISC +# +CONFIG_OS_USING_PUSH_BUTTON=y +CONFIG_OS_USING_LED=y +# CONFIG_OS_USING_BUZZER is not set +# CONFIG_OS_USING_ADC is not set +# CONFIG_OS_USING_DAC is not set +# CONFIG_OS_USING_PWM is not set +# CONFIG_OS_USING_INPUT_CAPTURE is not set +# CONFIG_OS_USING_PULSE_ENCODER is not set +# end of MISC + +# +# MTD +# +# CONFIG_OS_USING_MTD is not set +# end of MTD + +# +# NAND +# +# CONFIG_OS_USING_NAND is not set +# end of NAND + +# +# NET +# +# CONFIG_OS_USING_NET_DEVICE is not set +# CONFIG_OS_USING_WLAN is not set +# CONFIG_BSP_USING_AP6181 is not set +# end of NET + +# +# PIN +# +CONFIG_OS_USING_PIN=y +CONFIG_OS_PIN_MAX_CHIP=1 +# CONFIG_BSP_USING_PIN_PCF8574 is not set +# end of PIN + +# +# RTC +# +# CONFIG_OS_USING_RTC is not set +# end of RTC + +# +# SDIO +# +# CONFIG_OS_USING_SDIO is not set +# end of SDIO + +# +# Sensors +# +# CONFIG_OS_USING_SENSOR is not set +# end of Sensors + +# +# Serial +# +CONFIG_OS_USING_SERIAL=y +CONFIG_OS_SERIAL_DELAY_CLOSE=y +CONFIG_OS_SERIAL_RX_BUFSZ=64 +CONFIG_OS_SERIAL_TX_BUFSZ=64 + +# +# posix serial +# +# CONFIG_OS_USING_POSIX_SERIAL is not set +# end of posix serial + +# +# rtt uart +# +# CONFIG_OS_USING_RTT is not set +# end of rtt uart +# end of Serial + +# +# SFLASH +# +# CONFIG_OS_SFLASH_SUPPORT is not set +# end of SFLASH + +# +# SN +# +# CONFIG_OS_USING_SN is not set +# end of SN + +# +# SPI +# +# CONFIG_OS_USING_SPI is not set +# CONFIG_BSP_USING_ENC28J60 is not set +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_NRF24L01 is not set +# CONFIG_BSP_USING_TPS_1 is not set +# CONFIG_OS_USING_SFUD is not set +# end of SPI + +# +# Timer +# +CONFIG_OS_USING_TIMER_DRIVER=y +CONFIG_OS_USING_CLOCKSOURCE=y +# CONFIG_OS_CLOCKSOURCE_SHOW is not set +# CONFIG_OS_USING_TIMEKEEPING is not set +CONFIG_OS_CLOCKSOURCE_BEST="" +# CONFIG_OS_USING_CLOCKEVENT is not set +# CONFIG_OS_USING_HRTIMER is not set + +# +# cortex-m & riscv hardware timer config +# +CONFIG_OS_USING_SYSTICK_FOR_KERNEL_TICK=y +# CONFIG_OS_USING_SYSTICK_FOR_CLOCKSOURCE is not set +CONFIG_OS_USING_DWT_FOR_CLOCKSOURCE=y +# end of cortex-m & riscv hardware timer config +# end of Timer + +# +# TinyUSB +# +# CONFIG_OS_USING_TINYUSB is not set +# end of TinyUSB + +# +# Touch +# +# CONFIG_OS_USING_TOUCH is not set +# end of Touch + +# +# USB +# +# CONFIG_OS_USING_USB_DEVICE is not set +# CONFIG_OS_USING_USB_HOST is not set +# end of USB + +# +# WDG +# +# CONFIG_OS_USING_WDG is not set +# end of WDG +# end of Drivers + +# +# Components +# + +# +# MicroPython +# +# CONFIG_PKG_USING_MICROPYTHON is not set +# end of MicroPython + +# +# WWD +# +# CONFIG_OS_USING_WWD is not set +# end of WWD + +# +# AMS +# +# CONFIG_PKG_USING_AMS is not set +# end of AMS + +# +# Atest +# +# CONFIG_OS_USING_ATEST is not set +# end of Atest + +# +# BLE +# +# CONFIG_OS_USING_BLE is not set +# end of BLE + +# +# cJSON +# +# CONFIG_PKG_USING_CJSON is not set +# end of cJSON + +# +# CLI +# +# CONFIG_OS_USING_CLI is not set +# end of CLI + +# +# Cloud +# + +# +# Aliyun +# +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# end of Aliyun + +# +# AWS +# +# CONFIG_PKG_USING_AWS_IOT is not set +# end of AWS + +# +# Baidu +# +# CONFIG_BAIDUIOT is not set +# end of Baidu + +# +# CTWing +# + +# +# MQTT +# +# CONFIG_OS_USING_CTWING_MQTT is not set +# end of MQTT +# end of CTWing + +# +# Huawei +# +# CONFIG_USING_HUAWEI_CLOUD_CONNECT is not set +# end of Huawei + +# +# OneNET +# + +# +# MQTT kit +# +# CONFIG_OS_USING_ONENET_MQTTS is not set +# end of MQTT kit + +# +# NB-IoT kit +# +# CONFIG_OS_USING_ONENET_NBIOT is not set +# end of NB-IoT kit + +# +# EDP +# +# CONFIG_OS_USING_ONENET_EDP is not set +# end of EDP +# end of OneNET +# end of Cloud + +# +# CMS +# +CONFIG_CMS_LITE=y +# CONFIG_CMS_STD is not set + +# +# CMS Connect +# +# CONFIG_USING_CMS_CONNECT is not set +# end of CMS Connect + +# +# CMS ID +# +# CONFIG_CMS_USING_ID is not set +# end of CMS ID +# end of CMS + +# +# Diagnose +# +# CONFIG_STACK_TRACE_EN is not set +# CONFIG_OS_USING_CPU_MONITER is not set +# CONFIG_OS_USING_WIRESHARK_DUMP is not set + +# +# eCoreDump +# +# CONFIG_USING_ECORE_DUMP is not set +# end of eCoreDump + +# +# Memory Monitor +# +# CONFIG_OS_USING_MEM_MONITOR is not set +# end of Memory Monitor +# end of Diagnose + +# +# Dlog +# +CONFIG_OS_USING_DLOG=y +# CONFIG_DLOG_PRINT_LVL_E is not set +CONFIG_DLOG_PRINT_LVL_W=y +# CONFIG_DLOG_PRINT_LVL_I is not set +# CONFIG_DLOG_PRINT_LVL_D is not set +CONFIG_DLOG_GLOBAL_PRINT_LEVEL=4 +# CONFIG_DLOG_COMPILE_LVL_E is not set +# CONFIG_DLOG_COMPILE_LVL_W is not set +# CONFIG_DLOG_COMPILE_LVL_I is not set +CONFIG_DLOG_COMPILE_LVL_D=y +CONFIG_DLOG_COMPILE_LEVEL=7 +CONFIG_DLOG_USING_ISR_LOG=y +CONFIG_DLOG_USING_FILTER=y +CONFIG_DLOG_USING_ASYNC_OUTPUT=y +CONFIG_DLOG_ASYNC_OUTPUT_BUF_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE=2048 +CONFIG_DLOG_ASYNC_OUTPUT_TASK_PRIORITY=20 +# CONFIG_DLOG_USING_SYSLOG is not set + +# +# Log format +# +# CONFIG_DLOG_OUTPUT_FLOAT is not set +CONFIG_DLOG_WITH_FUNC_LINE=y +CONFIG_DLOG_USING_COLOR=y +CONFIG_DLOG_OUTPUT_TIME_INFO=y +# CONFIG_DLOG_TIME_USING_TIMESTAMP is not set +# end of Log format + +# +# Dlog backend option +# +CONFIG_DLOG_BACKEND_USING_CONSOLE=y +# CONFIG_DLOG_BACKEND_USING_FILESYSTEM is not set +# end of Dlog backend option +# end of Dlog + +# +# Easyflash +# +# CONFIG_PKG_USING_EASYFLASH is not set +# end of Easyflash + +# +# FileSystem +# +# CONFIG_OS_USING_VFS is not set +# end of FileSystem + +# +# GUI +# +CONFIG_OS_GUI_DISP_DEV_NAME="lcd" +CONFIG_OS_GUI_INPUT_DEV_NAME="touch" +# CONFIG_OS_USING_GUI_LVGL is not set +# end of GUI + +# +# Industrial +# + +# +# CANOpen +# +# CONFIG_OS_USING_CANFESTIVAL is not set +# end of CANOpen + +# +# CoDeSys +# +# CONFIG_OS_USING_CODESYS is not set +# end of CoDeSys + +# +# ModBus +# +# CONFIG_OS_USING_UCMODBUS is not set +# end of ModBus + +# +# PROFINET +# +# CONFIG_OS_USING_P_NET is not set +# end of PROFINET +# end of Industrial + +# +# IoTjs +# +# CONFIG_USING_IOTJS is not set +# end of IoTjs + +# +# JerryScript +# +# CONFIG_USING_JERRYSCRIPT is not set +# end of JerryScript + +# +# Network +# + +# +# Acw +# +# CONFIG_NET_USING_ACW is not set +# end of Acw + +# +# TCP/IP +# + +# +# LwIP +# +# CONFIG_NET_USING_LWIP is not set +# end of LwIP +# end of TCP/IP + +# +# Molink +# +# CONFIG_NET_USING_MOLINK is not set +# end of Molink + +# +# Protocols +# + +# +# CoAP +# +# CONFIG_NET_USING_COAP is not set +# end of CoAP + +# +# HTTP +# + +# +# httpclient-v1.1.0 +# +# CONFIG_NET_USING_HTTPCLIENT is not set +# end of httpclient-v1.1.0 +# end of HTTP + +# +# LWM2M +# + +# +# LWM2M-v1.0.0 +# +# CONFIG_NET_USING_LWM2M is not set +# end of LWM2M-v1.0.0 +# end of LWM2M + +# +# MQTT +# +# CONFIG_NET_USING_MQTT is not set +# end of MQTT + +# +# Websocket +# +# CONFIG_NET_USING_WEBSOCKET_CLIENT is not set +# end of Websocket +# end of Protocols + +# +# Socket +# +# CONFIG_NET_USING_BSD is not set +# end of Socket +# end of Network + +# +# Iotivity +# +# CONFIG_PKG_USING_IOTIVITY is not set +# end of Iotivity + +# +# Optparse +# +# CONFIG_TP_USING_OPTPARSE is not set +# end of Optparse + +# +# OTA +# + +# +# Fota by CMIOT +# +# CONFIG_FOTA_USING_CMIOT is not set +# end of Fota by CMIOT +# end of OTA + +# +# Position +# +# CONFIG_OS_USING_ONEPOS is not set +# end of Position + +# +# PowerManager +# +# CONFIG_OS_USING_POWER_MANAGER is not set +# end of PowerManager + +# +# Ramdisk +# +# CONFIG_OS_USING_RAMDISK is not set +# end of Ramdisk + +# +# Security +# +# CONFIG_SECURITY_USING_MBEDTLS is not set + +# +# OneTLS +# +# CONFIG_SECURITY_USING_ONETLS is not set +# end of OneTLS +# end of Security + +# +# Shell +# +CONFIG_OS_USING_SHELL=y +CONFIG_SHELL_TASK_NAME="tshell" +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=2048 +CONFIG_SHELL_USING_HISTORY=y +CONFIG_SHELL_HISTORY_LINES=5 +CONFIG_SHELL_USING_DESCRIPTION=y +# CONFIG_SHELL_ECHO_DISABLE_DEFAULT is not set +CONFIG_SHELL_CMD_SIZE=80 +CONFIG_SHELL_PROMPT_SIZE=256 +CONFIG_SHELL_ARG_MAX=10 +# CONFIG_SHELL_USING_AUTH is not set +# end of Shell + +# +# SQL +# +# CONFIG_PKG_USING_SQLITE is not set +# end of SQL + +# +# telnetd +# +# CONFIG_TELNET_SERVER is not set +# end of telnetd +# end of Components + +# +# Debug +# +CONFIG_OS_DEBUG=y +# CONFIG_LOG_BUFF_SIZE_128 is not set +# CONFIG_LOG_BUFF_SIZE_192 is not set +CONFIG_LOG_BUFF_SIZE_256=y +# CONFIG_LOG_BUFF_SIZE_384 is not set +CONFIG_OS_LOG_BUFF_SIZE=256 +# end of Debug diff --git a/templates/n32l436rbl7-1616n/.gitignore b/templates/n32l436rbl7-1616n/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..232a385f9b0c1f71bc227b6fad5fd55d32a9f449 --- /dev/null +++ b/templates/n32l436rbl7-1616n/.gitignore @@ -0,0 +1,21 @@ +RTE +DebugConfig +Listings +Objects +EventRecorderStub.scvd +.config.old +.sconsign.dblite +__pycache__ +build +one-os.bin +DebugConfig +*.uvguix.* +board/CubeMX_Config/MDK-ARM +board/CubeMX_Config/Drivers +*.o +*.pyc +*.log +*cconfig.h +oneos.bin +JLinkLog.txt +oneos.map diff --git a/templates/n32l436rbl7-1616n/JLinkSettings.ini b/templates/n32l436rbl7-1616n/JLinkSettings.ini new file mode 100644 index 0000000000000000000000000000000000000000..5bf646cfbe39a54f952ae60b02812968c80d0eff --- /dev/null +++ b/templates/n32l436rbl7-1616n/JLinkSettings.ini @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M4" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/templates/n32l436rbl7-1616n/Kconfig b/templates/n32l436rbl7-1616n/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..ff33a807f43a88abf607cb1b39b9d09811f48f53 --- /dev/null +++ b/templates/n32l436rbl7-1616n/Kconfig @@ -0,0 +1,12 @@ +mainmenu "OneOS Configuration" + +#Define the relative path to root directory of os code +OS_ROOT=../.. +SRC_HAL=nationstech + +config BOARD_N32L436RBL7_1616N + bool + select SOC_N32L436RBL7 + default y + +source "$OS_ROOT/Kconfig" diff --git a/templates/n32l436rbl7-1616n/application/main.c b/templates/n32l436rbl7-1616n/application/main.c new file mode 100644 index 0000000000000000000000000000000000000000..aef16e440890b547757285d2d9a59980ad0160b2 --- /dev/null +++ b/templates/n32l436rbl7-1616n/application/main.c @@ -0,0 +1,62 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file main.c + * + * @brief User application entry + * + * @revision + * Date Author Notes + * 2020-11-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include +#include + +static void user_task(void *parameter) +{ + int i = 0; + + for (i = 0; i < led_table_size; i++) + { + os_pin_mode(led_table[i].pin, PIN_MODE_OUTPUT); + } + + while (1) + { + for (i = 0; i < led_table_size; i++) + { + os_pin_write(led_table[i].pin, led_table[i].active_level); + os_task_msleep(200); + + os_pin_write(led_table[i].pin, !led_table[i].active_level); + os_task_msleep(200); + } + } +} + +int main(void) +{ + os_task_id task; + + task = os_task_create(OS_NULL, + OS_NULL, 512, + "user", + user_task, NULL, + 3); + OS_ASSERT(task); + os_task_startup(task); + + return 0; +} diff --git a/templates/n32l436rbl7-1616n/application/weave.yaml b/templates/n32l436rbl7-1616n/application/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fa32136884eea1e91681fced4cfe4dcc6c4d45f2 --- /dev/null +++ b/templates/n32l436rbl7-1616n/application/weave.yaml @@ -0,0 +1,6 @@ +# 组名 +group_name: application + +# 源码 +source_file: + - main.c \ No newline at end of file diff --git a/templates/n32l436rbl7-1616n/board/board.c b/templates/n32l436rbl7-1616n/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..48a68479516b2bffdf12b02764099e6895107203 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/board.c @@ -0,0 +1,50 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.c + * + * @brief Initializes the CPU, System clocks, and Peripheral device + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#include "board.h" +#include + +#ifdef OS_USING_LED +const led_t led_table[] = { + {GET_PIN(0, 8), PIN_LOW}, + {GET_PIN(1, 12), PIN_LOW}, + {GET_PIN(1, 13), PIN_LOW}, + {GET_PIN(1, 15), PIN_LOW}, +}; + +const int led_table_size = ARRAY_SIZE(led_table); +#endif + +#ifdef OS_USING_PUSH_BUTTON +const struct push_button key_table[] = { + {GET_PIN(1, 7), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 8), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(1, 9), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 13), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 14), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, + {GET_PIN(2, 15), PIN_MODE_INPUT_PULLUP, PIN_IRQ_MODE_FALLING}, +}; + +const int key_table_size = ARRAY_SIZE(key_table); + +#endif diff --git a/templates/n32l436rbl7-1616n/board/board.h b/templates/n32l436rbl7-1616n/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..a4a351a8e5d652d2f9bdb311268a286138c54c09 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/board.h @@ -0,0 +1,69 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file board.h + * + * @brief Board resource definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "drv_common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define N32_FLASH_START_ADDR ((uint32_t)0x08000000) +#define N32_FLASH_SIZE (128 * 1024) +#define N32_FLASH_END_ADDR ((uint32_t)(N32_FLASH_START_ADDR + N32_FLASH_SIZE)) + +#define N32_SRAM1_START (0x20000020) +#define N32_SRAM1_SIZE (32 * 1024 - 0x20) +#define N32_SRAM1_END (N32_SRAM1_START + N32_SRAM1_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END N32_SRAM1_END + +#ifdef OS_USING_PUSH_BUTTON +extern const struct push_button key_table[]; +extern const int key_table_size; +#endif + +#ifdef OS_USING_LED +extern const led_t led_table[]; +extern const int led_table_size; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/templates/n32l436rbl7-1616n/board/linker_scripts/link.icf b/templates/n32l436rbl7-1616n/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..ef3b1c98c8466eff61930ed54e61c737e0da8a55 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20017FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, last block CSTACK}; diff --git a/templates/n32l436rbl7-1616n/board/linker_scripts/link.lds b/templates/n32l436rbl7-1616n/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ed2f6646dbe62f4f4a6a7ad746de9c956b0a5707 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/linker_scripts/link.lds @@ -0,0 +1,149 @@ +/* + * linker script for STM32F1XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 0x00040000 /* 256K flash */ + RAM0 (rx) : ORIGIN = 0x20000000, LENGTH = 0x20 /* 0x20 sram */ + RAM1 (rx) : ORIGIN = 0x20000020, LENGTH = 0x5FE0 /* 0x5FE0 sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x800; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(vtor_table)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + INCLUDE common.lds + + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + } > ROM = 0 + + . = ALIGN(4); + _etext = .; + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + .reserved_ram : + { + * (reserved_ram) + } > RAM0 + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM1 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM1 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM1 + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/templates/n32l436rbl7-1616n/board/linker_scripts/link.sct b/templates/n32l436rbl7-1616n/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..759a23b4e54076ecc67105dd1f1b8274dcce6ae6 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/linker_scripts/link.sct @@ -0,0 +1,20 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (vtor_table, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_IRAM0 0x20000000 0x20 { ; RW data + * (reserved_ram) + } + + RW_IRAM1 0x20000020 0x00005FE0 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/templates/n32l436rbl7-1616n/board/peripherals/peripherals.c b/templates/n32l436rbl7-1616n/board/peripherals/peripherals.c new file mode 100644 index 0000000000000000000000000000000000000000..c8eeefd1842ed36327edbf9bb2d6a6ff5f19f3c1 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/peripherals/peripherals.c @@ -0,0 +1,62 @@ +#include "oneos_config.h" +#include +#include + +#include "drv_common.h" + +#ifdef BSP_USING_USART +#include "drv_usart.h" +const struct n32_usart_info usart1_info = { + .huart = USART1, + .rcc_type = 2, + .rcc = RCC_APB2_PERIPH_USART1, + .irq = USART1_IRQn, + + .dma_channel = NULL, //DMA_CH2, // 用作Console, 不能启用DMA + .dma_rcc = 1, + .dma_irq = DMA_Channel2_IRQn, + + .tx_port = GPIOA, + .tx_pin = GPIO_PIN_9, + .tx_rcc = RCC_APB2_PERIPH_GPIOA, + .tx_af = GPIO_AF4_USART1, + + .rx_port = GPIOA, + .rx_pin = GPIO_PIN_10, + .rx_rcc = RCC_APB2_PERIPH_GPIOA, + .rx_af = GPIO_AF4_USART1, + + .init_hook = NULL, + .send_start_hook = NULL, + .send_end_hook = NULL +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart1", usart1_info); + +const struct n32_usart_info usart2_info = { + .huart = USART2, + .rcc_type = 1, + .rcc = RCC_APB1_PERIPH_USART3, + .irq = USART2_IRQn, + + .dma_channel = DMA_CH4, + .dma_rcc = 1, + .dma_irq = DMA_Channel4_IRQn, + + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_4, + .tx_rcc = RCC_APB2_PERIPH_GPIOB, + .tx_af = GPIO_AF4_USART2, + + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_5, + .rx_rcc = RCC_APB2_PERIPH_GPIOB, + .rx_af = GPIO_AF6_USART2, + + .init_hook = NULL, + .send_start_hook = NULL, + .send_end_hook = NULL +}; + +OS_HAL_DEVICE_DEFINE("USART_Module", "usart2", usart2_info); +#endif diff --git a/drivers/hal/beken/beken72XX_HAL/beken_sdk/weave.yaml b/templates/n32l436rbl7-1616n/board/peripherals/weave.yaml similarity index 41% rename from drivers/hal/beken/beken72XX_HAL/beken_sdk/weave.yaml rename to templates/n32l436rbl7-1616n/board/peripherals/weave.yaml index 34f33707da8822de27f66dd501a80071b8eecc53..c91f78a3137f7745b507d5e162fa5b54ad06615b 100644 --- a/drivers/hal/beken/beken72XX_HAL/beken_sdk/weave.yaml +++ b/templates/n32l436rbl7-1616n/board/peripherals/weave.yaml @@ -1,13 +1,11 @@ # 组名 -group_name: beken_sdk - -# 依赖宏控 -depend_macro: - - SOC_FAMILY_BK72XX +group_name: bsp # 编译连接信息 build_option: cpppath: - . - libpath: - - . + +# 源码 +source_file: + - peripherals.c \ No newline at end of file diff --git a/templates/n32l436rbl7-1616n/board/ports/ef_cfg.h b/templates/n32l436rbl7-1616n/board/ports/ef_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..d7ecfb5c6350e221d356d2a6906fef6faf515139 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/ports/ef_cfg.h @@ -0,0 +1,125 @@ +/* + * This file is part of the EasyFlash Library. + * + * Copyright (c) 2015, Armink, + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Function: It is the configure head file for this library. + * Created on: 2018-05-19 + */ + +#ifndef EF_CFG_H_ +#define EF_CFG_H_ + +#include + +/* using ENV function */ +#define EF_USING_ENV +#define EF_ENV_USING_LEGACY_MODE + +/* using power fail safeguard mode for ENV */ +#define EF_ENV_USING_PFS_MODE + +/* the user setting size of ENV, must be word alignment */ +#define ENV_USER_SETTING_SIZE (PKG_EASYFLASH_ENV_SETTING_SIZE) + +#ifdef PKG_EASYFLASH_ENV_AUTO_UPDATE +/* Auto update ENV to latest default when current ENV version number is changed. */ +#define EF_ENV_AUTO_UPDATE +/** + * ENV version number defined by user. + * Please change it when your firmware add a new ENV to default_env_set. + */ +#define EF_ENV_VER_NUM PKG_EASYFLASH_ENV_VER_NUM +#endif + +/* using IAP function */ +#ifdef PKG_EASYFLASH_IAP +#define EF_USING_IAP +#endif + +/* using save log function */ +#ifdef PKG_EASYFLASH_LOG +#define EF_USING_LOG +/* saved log area size */ +#define LOG_AREA_SIZE (PKG_EASYFLASH_LOG_AREA_SIZE) +#endif + +/* the minimum size of flash erasure */ +#define EF_ERASE_MIN_SIZE PKG_EASYFLASH_ERASE_GRAN + +/* the flash write granularity, unit: bit + * only support 1(nor flash)/ 8(stm32f4)/ 32(stm32f1)/ 64(stm32l4) */ +#define EF_WRITE_GRAN 64 +/** + * + * This all Backup Area Flash storage index. All used flash area configure is under here. + * |----------------------------| Storage Size + * | Environment variables area | ENV area size @see ENV_AREA_SIZE + * | 1.system section | ENV_SYSTEM_SIZE + * | 2:data section | ENV_AREA_SIZE - ENV_SYSTEM_SIZE + * |----------------------------| + * | Saved log area | Log area size @see LOG_AREA_SIZE + * |----------------------------| + * |(IAP)Downloaded application | IAP already downloaded application, unfixed size + * |----------------------------| + * + * @note all area sizes must be aligned with EF_ERASE_MIN_SIZE + * @note EasyFlash will use ram to buffer the ENV. At some point flash's EF_ERASE_MIN_SIZE may become so big, + * and you want to keep ENV size smaller. To do it you must define ENV_USER_SETTING_SIZE for ENV. + * @note ENV area size has some limitations in different modes. + * 1.Normal mode: no limitations + * 2.Wear leveling mode: system section will used a flash section and the data section will use at least 2 flash + * sections 3.Power fail safeguard mode: ENV area will has a backup. It is twice as normal mode. 4.Wear leveling and + * power fail safeguard mode: The required capacity will be 2 times the total capacity in wear leveling mode. For + * example: The EF_ERASE_MIN_SIZE is 128K and the ENV_USER_SETTING_SIZE: 2K. The ENV_AREA_SIZE in different mode you can + * define 1.Normal mode: 1*EF_ERASE_MIN_SIZE 2.Wear leveling mode: 3*EF_ERASE_MIN_SIZE (It has 2 data section to store + * ENV. So ENV can erase at least 200,000 times) 3.Power fail safeguard mode: 2*EF_ERASE_MIN_SIZE 4.Wear leveling and + * power fail safeguard mode: 6*EF_ERASE_MIN_SIZE + * @note the log area size must be more than twice of EF_ERASE_MIN_SIZE + */ +/* backup area start address */ +#define EF_START_ADDR PKG_EASYFLASH_START_ADDR + +#ifndef EF_ENV_USING_PFS_MODE +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in normal mode. */ +#define ENV_AREA_SIZE (1 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling mode. */ +#define ENV_AREA_SIZE (4 * EF_ERASE_MIN_SIZE) +#endif +#else +#ifndef EF_ENV_USING_WL_MODE +/* ENV area total bytes size in power fail safeguard mode. */ +#define ENV_AREA_SIZE (2 * EF_ERASE_MIN_SIZE) +#else +/* ENV area total bytes size in wear leveling and power fail safeguard mode. */ +#define ENV_AREA_SIZE (6 * EF_ERASE_MIN_SIZE) +#endif +#endif + +/* print debug information of flash */ +#ifdef PKG_EASYFLASH_DEBUG +#define PRINT_DEBUG +#endif + +#endif /* EF_CFG_H_ */ diff --git a/templates/n32l436rbl7-1616n/board/ports/fal_cfg.c b/templates/n32l436rbl7-1616n/board/ports/fal_cfg.c new file mode 100644 index 0000000000000000000000000000000000000000..6285128540943f75c9dd5786a6f5aa13b076b7eb --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/ports/fal_cfg.c @@ -0,0 +1,28 @@ +/** + *********************************************************************************************************************** + * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd. + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with + * the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on + * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @file fal_cfg.c + * + * @brief Flash abstract layer partition definition + * + * @revision + * Date Author Notes + * 2020-02-20 OneOS Team First Version + *********************************************************************************************************************** + */ +static const fal_part_info_t fal_part_info[] = { + /* part, flash, addr, size, lock */ + /* part, flash, addr, size, lock */ + {"app", "onchip_flash", 0x00000000, 120*1024, FAL_PART_INFO_FLAGS_LOCKED}, + {"user", "onchip_flash", 120*1024, 8*1024, FAL_PART_INFO_FLAGS_UNLOCKED}, +}; diff --git a/templates/n32l436rbl7-1616n/board/ports/flash_info.c b/templates/n32l436rbl7-1616n/board/ports/flash_info.c new file mode 100644 index 0000000000000000000000000000000000000000..e1ab44a199e7f3721f2c8b02f5481b710e9d3e9e --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/ports/flash_info.c @@ -0,0 +1,7 @@ +static struct onchip_flash_info flash_info = { + .start_addr = N32_FLASH_START_ADDR, + .capacity = N32_FLASH_SIZE, + .block_size = N32_FLASH_BLOCK_SIZE, + .page_size = N32_FLASH_PAGE_SIZE, +}; +OS_HAL_DEVICE_DEFINE("N32L43X_Onchip_Flash", "onchip_flash", flash_info); diff --git a/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_arm.s b/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_arm.s new file mode 100644 index 0000000000000000000000000000000000000000..1a2948b66c24cf27e7f279e7ce98eb4609b5875d --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_arm.s @@ -0,0 +1,375 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations' name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001500 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +___initial_sp + EXPORT ___initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000300 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA_Channel1_IRQHandler ; DMA Channel 1 + DCD DMA_Channel2_IRQHandler ; DMA Channel 2 + DCD DMA_Channel3_IRQHandler ; DMA Channel 3 + DCD DMA_Channel4_IRQHandler ; DMA Channel 4 + DCD DMA_Channel5_IRQHandler ; DMA Channel 5 + DCD DMA_Channel6_IRQHandler ; DMA Channel 6 + DCD DMA_Channel7_IRQHandler ; DMA Channel 7 + DCD DMA_Channel8_IRQHandler ; DMA Channel 8 + DCD ADC_IRQHandler ; ADC + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22 + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD LPUART_IRQHandler ; LPUART + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP + DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP + DCD LCD_IRQHandler ; LCD + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD RAMC_PERR_IRQHandler ; RAMC ERR + DCD TIM9_IRQHandler ; TIM9 + DCD UCDR_IRQHandler ; UCDR ERR +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_IRQHandler [WEAK] + EXPORT DMA_Channel5_IRQHandler [WEAK] + EXPORT DMA_Channel6_IRQHandler [WEAK] + EXPORT DMA_Channel7_IRQHandler [WEAK] + EXPORT DMA_Channel8_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT COMP_1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT LPUART_WKUP_IRQHandler [WEAK] + EXPORT LPTIM_WKUP_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RAMC_PERR_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT UCDR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_IRQHandler +DMA_Channel5_IRQHandler +DMA_Channel6_IRQHandler +DMA_Channel7_IRQHandler +DMA_Channel8_IRQHandler +ADC_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +COMP_1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +LPUART_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +LPUART_WKUP_IRQHandler +LPTIM_WKUP_IRQHandler +LCD_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +RAMC_PERR_IRQHandler +TIM9_IRQHandler +UCDR_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_gcc.s b/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_gcc.s new file mode 100644 index 0000000000000000000000000000000000000000..23f59c94ca474ac0b4815d219794a6ad5d5bf336 --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/startup/startup_n32l43x_gcc.s @@ -0,0 +1,421 @@ +/** +****************************************************************************** +* @file startup_n32l43x_gcc.s +****************************************************************************** +*/ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word LPUART_IRQHandler /* LPUART */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word CAN_TX_IRQHandler /* CAN TX */ + .word CAN_RX0_IRQHandler /* CAN RX0 */ + .word CAN_RX1_IRQHandler /* CAN RX1 */ + .word CAN_SCE_IRQHandler /* CAN SCE */ + .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */ + .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */ + .word LCD_IRQHandler /* LCD */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + .word RAMC_PERR_IRQHandler /* RAMC ERR */ + .word TIM9_IRQHandler /* TIM9 */ + .word UCDR_IRQHandler /* UCDR ERR */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA_Channel1_IRQHandler + .thumb_set DMA_Channel1_IRQHandler,Default_Handler + + .weak DMA_Channel2_IRQHandler + .thumb_set DMA_Channel2_IRQHandler,Default_Handler + + .weak DMA_Channel3_IRQHandler + .thumb_set DMA_Channel3_IRQHandler,Default_Handler + + .weak DMA_Channel4_IRQHandler + .thumb_set DMA_Channel4_IRQHandler,Default_Handler + + .weak DMA_Channel5_IRQHandler + .thumb_set DMA_Channel5_IRQHandler,Default_Handler + + .weak DMA_Channel6_IRQHandler + .thumb_set DMA_Channel6_IRQHandler,Default_Handler + + .weak DMA_Channel7_IRQHandler + .thumb_set DMA_Channel7_IRQHandler,Default_Handler + + .weak DMA_Channel8_IRQHandler + .thumb_set DMA_Channel8_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak COMP_1_2_IRQHandler + .thumb_set COMP_1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak LPUART_WKUP_IRQHandler + .thumb_set LPUART_WKUP_IRQHandler,Default_Handler + + .weak LPTIM_WKUP_IRQHandler + .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RAMC_PERR_IRQHandler + .thumb_set RAMC_PERR_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak UCDR_IRQHandler + .thumb_set UCDR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT NATIONSTECH *****END OF FILE****/ diff --git a/templates/n32l436rbl7-1616n/board/weave.yaml b/templates/n32l436rbl7-1616n/board/weave.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8d19c55fdd5169fa5331c416ac908f9ceefd8bcf --- /dev/null +++ b/templates/n32l436rbl7-1616n/board/weave.yaml @@ -0,0 +1,22 @@ +# 组名 +group_name: bsp + +# 编译连接信息 +build_option: + cpppath: + - . + - ports + cppdefines: + - N32L43X + - HSE_VALUE=25000000 + - SYSCLK_FREQ=100000000 + +# 源码 +source_file: + - board.c + - startup/startup_n32l43x_gcc.s ? {is_compiler("gcc")} + - startup/startup_n32l43x_arm.s ? {is_compiler("armcc")} + +# 子目录 +add_subdirectory: + - ./* \ No newline at end of file diff --git a/templates/n32l436rbl7-1616n/oneos_config.h b/templates/n32l436rbl7-1616n/oneos_config.h new file mode 100644 index 0000000000000000000000000000000000000000..f78e56585745e218d7188e745e584379680b1e17 --- /dev/null +++ b/templates/n32l436rbl7-1616n/oneos_config.h @@ -0,0 +1,537 @@ +#ifndef __ONEOS_CONFIG_H__ +#define __ONEOS_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ +#define BOARD_N32L406RBL7_MXIO_1616N +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* Kernel */ + +#define OS_NAME_MAX_15 +#define OS_NAME_MAX 15 +#define OS_TASK_PRIORITY_32 +#define OS_TASK_PRIORITY_MAX 32 +#define OS_TICK_PER_SECOND 1000 +#define OS_SCHEDULE_TIME_SLICE 10 +#define OS_USING_OVERFLOW_CHECK +#define OS_USING_KERNEL_DEBUG +#define KLOG_GLOBAL_LEVEL_WARNING +#define KLOG_GLOBAL_LEVEL 1 +#define KLOG_USING_COLOR +#define KLOG_WITH_FUNC_LINE +#define OS_MAIN_TASK_STACK_SIZE 2048 +#define OS_IDLE_TASK_STACK_SIZE 512 +#define OS_RECYCLE_TASK_STACK_SIZE 512 +#define OS_USING_TIMER +#define OS_TIMER_TASK_STACK_SIZE 512 +#define OS_TIMER_POWER 3 +#define OS_USING_WORKQUEUE +#define OS_USING_SYSTEM_WORKQUEUE +#define OS_SYSTEM_WORKQUEUE_STACK_SIZE 2048 +#define OS_SYSTEM_WORKQUEUE_PRIORITY 0 + +/* Inter-task communication and synchronization */ + +#define OS_USING_MUTEX +#define OS_USING_SEMAPHORE +/* end of Inter-task communication and synchronization */ + +/* Memory management */ + +#define OS_USING_SYS_HEAP +#define OS_USING_MEM_HEAP +#define OS_USING_ALG_FIRSTFIT +/* end of Memory management */ +/* end of Kernel */ + +/* C standard library adapter */ + +#define OS_USING_LIBC_ADAPTER +#define OS_USING_NEWLIB_ADAPTER +#define OS_USING_ARMCCLIB_ADAPTER +/* end of C standard library adapter */ + +/* Osal */ + +/* POSIX compatibility layer */ + +/* end of POSIX compatibility layer */ + +/* RT-Thread compatibility layer */ + +/* end of RT-Thread compatibility layer */ + +/* CMSIS compatibility layer */ + +/* end of CMSIS compatibility layer */ + +/* FreeRTOS compatibility layer */ + +/* end of FreeRTOS compatibility layer */ + +/* C++ Features */ + +/* end of C++ Features */ +/* end of Osal */ + +/* Drivers */ + +#define OS_USING_DEVICE +#define OS_USING_DEVICE_NOTIFY + +/* Audio */ + +/* end of Audio */ + +/* BLOCK */ + +#define OS_USING_BLOCK +/* end of BLOCK */ + +/* Boot */ + +/* CORTEX-M Boot */ + +#define BSP_INCLUDE_VECTOR_TABLE +/* end of CORTEX-M Boot */ +/* end of Boot */ + +/* CAN */ + +/* end of CAN */ + +/* CONSOLE */ + +#define OS_USING_CONSOLE +#define OS_CONSOLE_DEVICE_NAME "usart1" +/* end of CONSOLE */ + +/* DMA */ + +#define OS_USING_DMA +#define OS_USING_DMA_RAM +#define OS_USING_SOFT_DMA +#define OS_SOFT_DMA_SUPPORT_NORMAL_MODE +#define OS_SOFT_DMA_SUPPORT_CIRCLE_MODE +#define OS_SOFT_DMA_SUPPORT_SIMUL_TIMEOUT +/* end of DMA */ + +/* EEPROM */ + +/* end of EEPROM */ + +/* FAL */ + +#define OS_USING_FAL +/* end of FAL */ + +/* Graphic */ + +/* end of Graphic */ + +/* HAL */ + +#define MANUFACTOR_NATIONSTECH +#define SERIES_N32L40X +#define SOC_N32L406RBL7 +#define BSP_USING_GPIO +#define BSP_USING_LED +#define BSP_USING_USART +#define BSP_USING_ONCHIP_FLASH +#define BSP_USING_TIMER +/* end of HAL */ + +/* HwCrypto */ + +/* end of HwCrypto */ + +/* I2C */ + +/* end of I2C */ + +/* Infrared */ + +/* end of Infrared */ + +/* LPMGR */ + +/* end of LPMGR */ + +/* MISC */ + +#define OS_USING_PUSH_BUTTON +#define OS_USING_LED +/* end of MISC */ + +/* MTD */ + +/* end of MTD */ + +/* NAND */ + +/* end of NAND */ + +/* NET */ + +/* end of NET */ + +/* PIN */ + +#define OS_USING_PIN +#define OS_PIN_MAX_CHIP 1 +/* end of PIN */ + +/* RTC */ + +/* end of RTC */ + +/* SDIO */ + +/* end of SDIO */ + +/* Sensors */ + +/* end of Sensors */ + +/* Serial */ + +#define OS_USING_SERIAL +#define OS_SERIAL_DELAY_CLOSE +#define OS_SERIAL_RX_BUFSZ 64 +#define OS_SERIAL_TX_BUFSZ 64 + +/* posix serial */ + +/* end of posix serial */ + +/* rtt uart */ + +/* end of rtt uart */ +/* end of Serial */ + +/* SFLASH */ + +/* end of SFLASH */ + +/* SN */ + +/* end of SN */ + +/* SPI */ + +/* end of SPI */ + +/* Timer */ + +#define OS_USING_TIMER_DRIVER +#define OS_USING_CLOCKSOURCE +#define OS_CLOCKSOURCE_BEST "" + +/* cortex-m & riscv hardware timer config */ + +#define OS_USING_SYSTICK_FOR_KERNEL_TICK +#define OS_USING_DWT_FOR_CLOCKSOURCE +/* end of cortex-m & riscv hardware timer config */ +/* end of Timer */ + +/* TinyUSB */ + +/* end of TinyUSB */ + +/* Touch */ + +/* end of Touch */ + +/* USB */ + +/* end of USB */ + +/* WDG */ + +/* end of WDG */ +/* end of Drivers */ + +/* Components */ + +/* MicroPython */ + +/* end of MicroPython */ + +/* WWD */ + +/* end of WWD */ + +/* AMS */ + +/* end of AMS */ + +/* Atest */ + +/* end of Atest */ + +/* BLE */ + +/* end of BLE */ + +/* cJSON */ + +/* end of cJSON */ + +/* CLI */ + +/* end of CLI */ + +/* Cloud */ + +/* Aliyun */ + +/* end of Aliyun */ + +/* AWS */ + +/* end of AWS */ + +/* Baidu */ + +/* end of Baidu */ + +/* CTWing */ + +/* MQTT */ + +/* end of MQTT */ +/* end of CTWing */ + +/* Huawei */ + +/* end of Huawei */ + +/* OneNET */ + +/* MQTT kit */ + +/* end of MQTT kit */ + +/* NB-IoT kit */ + +/* end of NB-IoT kit */ + +/* EDP */ + +/* end of EDP */ +/* end of OneNET */ +/* end of Cloud */ + +/* CMS */ + +#define CMS_LITE + +/* CMS Connect */ + +/* end of CMS Connect */ + +/* CMS ID */ + +/* end of CMS ID */ +/* end of CMS */ + +/* Diagnose */ + + +/* eCoreDump */ + +/* end of eCoreDump */ + +/* Memory Monitor */ + +/* end of Memory Monitor */ +/* end of Diagnose */ + +/* Dlog */ + +#define OS_USING_DLOG +#define DLOG_PRINT_LVL_W +#define DLOG_GLOBAL_PRINT_LEVEL 4 +#define DLOG_COMPILE_LVL_D +#define DLOG_COMPILE_LEVEL 7 +#define DLOG_USING_ISR_LOG +#define DLOG_USING_FILTER +#define DLOG_USING_ASYNC_OUTPUT +#define DLOG_ASYNC_OUTPUT_BUF_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_STACK_SIZE 2048 +#define DLOG_ASYNC_OUTPUT_TASK_PRIORITY 20 + +/* Log format */ + +#define DLOG_WITH_FUNC_LINE +#define DLOG_USING_COLOR +#define DLOG_OUTPUT_TIME_INFO +/* end of Log format */ + +/* Dlog backend option */ + +#define DLOG_BACKEND_USING_CONSOLE +/* end of Dlog backend option */ +/* end of Dlog */ + +/* Easyflash */ + +/* end of Easyflash */ + +/* FileSystem */ + +/* end of FileSystem */ + +/* GUI */ + +#define OS_GUI_DISP_DEV_NAME "lcd" +#define OS_GUI_INPUT_DEV_NAME "touch" +/* end of GUI */ + +/* Industrial */ + +/* CANOpen */ + +/* end of CANOpen */ + +/* CoDeSys */ + +/* end of CoDeSys */ + +/* ModBus */ + +/* end of ModBus */ + +/* PROFINET */ + +/* end of PROFINET */ +/* end of Industrial */ + +/* IoTjs */ + +/* end of IoTjs */ + +/* JerryScript */ + +/* end of JerryScript */ + +/* Network */ + +/* Acw */ + +/* end of Acw */ + +/* TCP/IP */ + +/* LwIP */ + +/* end of LwIP */ +/* end of TCP/IP */ + +/* Molink */ + +/* end of Molink */ + +/* Protocols */ + +/* CoAP */ + +/* end of CoAP */ + +/* HTTP */ + +/* httpclient-v1.1.0 */ + +/* end of httpclient-v1.1.0 */ +/* end of HTTP */ + +/* LWM2M */ + +/* LWM2M-v1.0.0 */ + +/* end of LWM2M-v1.0.0 */ +/* end of LWM2M */ + +/* MQTT */ + +/* end of MQTT */ + +/* Websocket */ + +/* end of Websocket */ +/* end of Protocols */ + +/* Socket */ + +/* end of Socket */ +/* end of Network */ + +/* Iotivity */ + +/* end of Iotivity */ + +/* Optparse */ + +/* end of Optparse */ + +/* OTA */ + +/* Fota by CMIOT */ + +/* end of Fota by CMIOT */ +/* end of OTA */ + +/* Position */ + +/* end of Position */ + +/* PowerManager */ + +/* end of PowerManager */ + +/* Ramdisk */ + +/* end of Ramdisk */ + +/* Security */ + + +/* OneTLS */ + +/* end of OneTLS */ +/* end of Security */ + +/* Shell */ + +#define OS_USING_SHELL +#define SHELL_TASK_NAME "tshell" +#define SHELL_TASK_PRIORITY 20 +#define SHELL_TASK_STACK_SIZE 2048 +#define SHELL_USING_HISTORY +#define SHELL_HISTORY_LINES 5 +#define SHELL_USING_DESCRIPTION +#define SHELL_CMD_SIZE 80 +#define SHELL_PROMPT_SIZE 256 +#define SHELL_ARG_MAX 10 +/* end of Shell */ + +/* SQL */ + +/* end of SQL */ + +/* telnetd */ + +/* end of telnetd */ +/* end of Components */ + +/* Debug */ + +#define OS_DEBUG +#define LOG_BUFF_SIZE_256 +#define OS_LOG_BUFF_SIZE 256 +/* end of Debug */ + +#endif /* __ONEOS_CONFIG_H__ */ + diff --git a/templates/n32l436rbl7-1616n/osconfig.py b/templates/n32l436rbl7-1616n/osconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..f4b271be0d5da7e937218bfacb0f025d66a73970 --- /dev/null +++ b/templates/n32l436rbl7-1616n/osconfig.py @@ -0,0 +1,149 @@ +import os + +# toolchains options +ARCH = 'arm' +CPU = 'cortex-m4' +CROSS_TOOL = 'gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('OS_CC'): + CROSS_TOOL = os.getenv('OS_CC') +if os.getenv('OS_ROOT'): + OS_ROOT = os.getenv('OS_ROOT') + +# cross_tool provides the cross compiler +# COMPILER_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + COMPILER = 'gcc' + COMPILER_PATH = '' +elif CROSS_TOOL == 'keil': + COMPILER = 'armcc' + # Notice: The installation path of armcc cannot have Chinese + COMPILER_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + COMPILER = 'iar' + COMPILER_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + + +if COMPILER == 'gcc': + # "BUILD" can be: 'debug_O0', 'release_O2' or 'release_Os' + BUILD = 'debug_O0' +else: + BUILD = 'debug' + +if COMPILER == 'gcc': + # toolchains + if COMPILER_PATH == '': + COMPILER_PATH = os.getenv('OS_EXEC_PATH') + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + RESULT_SUFFIX = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -L $OS_ROOT/drivers/link/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug_O0': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + elif BUILD == 'release_O2': + CFLAGS += ' -O2' + else: + CFLAGS += ' -Os' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -R .reserved_ram -O binary $TARGET oneos.bin\n' + SIZE + ' $TARGET \n' + +elif COMPILER == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + RESULT_SUFFIX = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --split_sections --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list oneos.map --strict' + CFLAGS += ' -I "' + COMPILER_PATH + '/ARM/ARMCC/include"' + LFLAGS += ' --libpath="' + COMPILER_PATH + '/ARM/ARMCC/lib"' + + #CFLAGS += ' -D__MICROLIB ' + #AFLAGS += ' --pd "__MICROLIB SETA 1" ' + #LFLAGS += ' --library_type=microlib ' + COMPILER_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output oneos.bin \nfromelf -z $TARGET' + +elif COMPILER == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + RESULT_SUFFIX = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + COMPILER_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + COMPILER_PATH = COMPILER_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET oneos.bin' diff --git a/templates/n32l436rbl7-1616n/project.uvoptx b/templates/n32l436rbl7-1616n/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..589b7bd13cc070e136f7a17854922db072068911 --- /dev/null +++ b/templates/n32l436rbl7-1616n/project.uvoptx @@ -0,0 +1,1481 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0N32L43x.FLM -FS08000000 -FL020000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + application + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + application\main.c + main.c + 0 + 0 + + + + + arch + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_atomic.c + arch_atomic.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_exception.c + arch_exception.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + arch_exception_rvds.S + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_interrupt.c + arch_interrupt.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_misc.c + arch_misc.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\arch_task.c + arch_task.c + 0 + 0 + + + 2 + 8 + 2 + 0 + 0 + 0 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + arch_task_switch_rvds.S + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + board\peripherals\peripherals.c + peripherals.c + 0 + 0 + + + 3 + 11 + 2 + 0 + 0 + 0 + board\startup\startup_n32l43x.s + startup_n32l43x.s + 0 + 0 + + + + + cli + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli.c + cli.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_cms.c + cli_cms.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_lwip.c + cli_lwip.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\components\cli\source\cli_molink.c + cli_molink.c + 0 + 0 + + + + + common + 0 + 0 + 0 + 0 + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\common\source\option_parse.c + option_parse.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_blk_buff.c + ring_blk_buff.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\common\source\ring_buff.c + ring_buff.c + 0 + 0 + + + + + dlog + 0 + 0 + 0 + 0 + + 6 + 19 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\backend\console_backend.c + console_backend.c + 0 + 0 + + + 6 + 20 + 1 + 0 + 0 + 0 + ..\..\components\dlog\source\dlog.c + dlog.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 7 + 21 + 1 + 0 + 0 + 0 + ..\..\drivers\block\block_device.c + block_device.c + 0 + 0 + + + 7 + 22 + 1 + 0 + 0 + 0 + ..\..\drivers\bus\bus.c + bus.c + 0 + 0 + + + 7 + 23 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource.c + clocksource.c + 0 + 0 + + + 7 + 24 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\clocksource_cortexm.c + clocksource_cortexm.c + 0 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + ..\..\drivers\console\console.c + console.c + 0 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + ..\..\drivers\device.c + device.c + 0 + 0 + + + 7 + 27 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\dma_ram.c + dma_ram.c + 0 + 0 + + + 7 + 28 + 1 + 0 + 0 + 0 + ..\..\drivers\driver.c + driver.c + 0 + 0 + + + 7 + 29 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal.c + fal.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_block.c + fal_block.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\drivers\fal\fal_part.c + fal_part.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\drivers\pin\pin.c + pin.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\drivers\misc\push_button.c + push_button.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\drivers\dma\soft_dma.c + soft_dma.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\drivers\timer\timer.c + timer.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\drivers\boot\cotex-m\vector_table.c + vector_table.c + 0 + 0 + + + + + hal/drivers + 0 + 0 + 0 + 0 + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_common.c + drv_common.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l43x\flash\drv_flash.c + drv_flash.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_usart.c + drv_usart.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\drivers\n32l43x\n32_it.c + n32_it.c + 0 + 0 + + + + + hal/lowlevel + 0 + 0 + 0 + 0 + + 9 + 43 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 9 + 44 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_dma.c + n32l43x_dma.c + 0 + 0 + + + 9 + 45 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_exti.c + n32l43x_exti.c + 0 + 0 + + + 9 + 46 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_flash.c + n32l43x_flash.c + 0 + 0 + + + 9 + 47 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_gpio.c + n32l43x_gpio.c + 0 + 0 + + + 9 + 48 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_rcc.c + n32l43x_rcc.c + 0 + 0 + + + 9 + 49 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_tim.c + n32l43x_tim.c + 0 + 0 + + + 9 + 50 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_usart.c + n32l43x_usart.c + 0 + 0 + + + 9 + 51 + 1 + 0 + 0 + 0 + ..\..\drivers\hal\nationstech\N32L43x\CMSIS\device\system_n32l43x.c + system_n32l43x.c + 0 + 0 + + + + + kernel + 0 + 0 + 0 + 0 + + 10 + 52 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_block.c + os_block.c + 0 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_clock.c + os_clock.c + 0 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_idle.c + os_idle.c + 0 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_lock.c + os_kernel_lock.c + 0 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_kernel_log.c + os_kernel_log.c + 0 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mem_firstfit.c + os_mem_firstfit.c + 0 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_memory.c + os_memory.c + 0 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_mutex.c + os_mutex.c + 0 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sched.c + os_sched.c + 0 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_sem.c + os_sem.c + 0 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_spinlock.c + os_spinlock.c + 0 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_startup.c + os_startup.c + 0 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_task.c + os_task.c + 0 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_timer_hash.c + os_timer_hash.c + 0 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_util.c + os_util.c + 0 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_version.c + os_version.c + 0 + 0 + + + 10 + 68 + 1 + 0 + 0 + 0 + ..\..\kernel\source\os_workqueue.c + os_workqueue.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 11 + 69 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\access.c + access.c + 0 + 0 + + + 11 + 70 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\chdir.c + chdir.c + 0 + 0 + + + 11 + 71 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\close.c + close.c + 0 + 0 + + + 11 + 72 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\dirent.c + dirent.c + 0 + 0 + + + 11 + 73 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fcntl.c + fcntl.c + 0 + 0 + + + 11 + 74 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fstat.c + fstat.c + 0 + 0 + + + 11 + 75 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\fsync.c + fsync.c + 0 + 0 + + + 11 + 76 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\getcwd.c + getcwd.c + 0 + 0 + + + 11 + 77 + 1 + 0 + 0 + 0 + ..\..\libc\source\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + 11 + 78 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\ioctl.c + ioctl.c + 0 + 0 + + + 11 + 79 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\libc.c + libc.c + 0 + 0 + + + 11 + 80 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\lseek.c + lseek.c + 0 + 0 + + + 11 + 81 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 11 + 82 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\mkdir.c + mkdir.c + 0 + 0 + + + 11 + 83 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\open.c + open.c + 0 + 0 + + + 11 + 84 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\read.c + read.c + 0 + 0 + + + 11 + 85 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rename.c + rename.c + 0 + 0 + + + 11 + 86 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\rmdir.c + rmdir.c + 0 + 0 + + + 11 + 87 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stat.c + stat.c + 0 + 0 + + + 11 + 88 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\statfs.c + statfs.c + 0 + 0 + + + 11 + 89 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stdio.c + stdio.c + 0 + 0 + + + 11 + 90 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strdup.c + strdup.c + 0 + 0 + + + 11 + 91 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\strnlen.c + strnlen.c + 0 + 0 + + + 11 + 92 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\stubs.c + stubs.c + 0 + 0 + + + 11 + 93 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\time.c + time.c + 0 + 0 + + + 11 + 94 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\unlink.c + unlink.c + 0 + 0 + + + 11 + 95 + 1 + 0 + 0 + 0 + ..\..\libc\source\armlibc\write.c + write.c + 0 + 0 + + + + + shell + 0 + 0 + 0 + 0 + + 12 + 96 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_buildin_cmd.c + shell_buildin_cmd.c + 0 + 0 + + + 12 + 97 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_main.c + shell_main.c + 0 + 0 + + + 12 + 98 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_process.c + shell_process.c + 0 + 0 + + + 12 + 99 + 1 + 0 + 0 + 0 + ..\..\components\shell\source\shell_symbol.c + shell_symbol.c + 0 + 0 + + + + diff --git a/templates/n32l436rbl7-1616n/project.uvprojx b/templates/n32l436rbl7-1616n/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..8fe7739da552ad016a3085320232506adb59d254 --- /dev/null +++ b/templates/n32l436rbl7-1616n/project.uvprojx @@ -0,0 +1,958 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32L436RB + Nationstech + Nationstech.N32L43x_DFP.0.1.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x8000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32L43x -FS08000000 -FL020000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM)) + 0 + $$Device:N32L436RB$firmware\CMSIS\device\n32l43x.h + + + + + + + + + + $$Device:N32L436RB$svd\N32L436.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + N32L43X, OS_TASK_SWITCH_NOTIFY, HSE_VALUE=25000000, SYSCLK_FREQ=100000000 + + .;..\..\components\uai\library;..\..\arch\arm\armv7m\include;board;board\ports;board\peripherals;..\..\components\cli\include;..\..\common\include;..\..\components\dlog\include;..\..\drivers;..\..\drivers\boot\cotex-m;..\..\drivers\bus;..\..\drivers\console;..\..\drivers\dma;..\..\drivers\fal;..\..\drivers\misc;..\..\drivers\pin;..\..\drivers\serial;..\..\drivers\timer;..\..\components\diagnose\eCoreDump;..\..\drivers\hal\nationstech\drivers\n32l43x;..\..\drivers\hal\nationstech\drivers\n32l43x\flash;..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\inc;..\..\drivers\hal\nationstech\N32L43x\CMSIS\core;..\..\drivers\hal\nationstech\N32L43x\CMSIS\device;..\..\kernel\include;..\..\libc\include;..\..\libc\include\extension;..\..\libc\include\armlibc;..\..\components\shell\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + OS_TASK_SWITCH_NOTIFY + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress L6314,L6330 + + + + + + + + application + + + main.c + 1 + application\main.c + + + + + arch + + + arch_atomic.c + 1 + ..\..\arch\arm\armv7m\arch_atomic.c + + + arch_exception.c + 1 + ..\..\arch\arm\armv7m\arch_exception.c + + + arch_exception_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_exception_rvds.S + + + arch_interrupt.c + 1 + ..\..\arch\arm\armv7m\arch_interrupt.c + + + arch_misc.c + 1 + ..\..\arch\arm\armv7m\arch_misc.c + + + arch_task.c + 1 + ..\..\arch\arm\armv7m\arch_task.c + + + arch_task_switch_rvds.S + 2 + ..\..\arch\arm\armv7m\rvds\arch_task_switch_rvds.S + + + + + bsp + + + board.c + 1 + board\board.c + + + peripherals.c + 1 + board\peripherals\peripherals.c + + + startup_n32l43x.s + 2 + board\startup\startup_n32l43x.s + + + + + cli + + + cli.c + 1 + ..\..\components\cli\source\cli.c + + + cli_cms.c + 1 + ..\..\components\cli\source\cli_cms.c + + + cli_lwip.c + 1 + ..\..\components\cli\source\cli_lwip.c + + + cli_molink.c + 1 + ..\..\components\cli\source\cli_molink.c + + + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_common.c + + + drv_flash.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\flash\drv_flash.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\misc.c + + + n32l43x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_dma.c + + + n32l43x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_exti.c + + + n32l43x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_flash.c + + + n32l43x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_gpio.c + + + n32l43x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_rcc.c + + + n32l43x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_tim.c + + + n32l43x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_usart.c + + + system_n32l43x.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\CMSIS\device\system_n32l43x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/n32l436rbl7-1616n/settings-gcc.yaml b/templates/n32l436rbl7-1616n/settings-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c764ee1dabe7c2e958b9035f0565d981e7514cb3 --- /dev/null +++ b/templates/n32l436rbl7-1616n/settings-gcc.yaml @@ -0,0 +1,27 @@ +# 编译选项（支持条件表达式） +option: + cflags: # General options that are passed to the C compiler (C only; not C++). + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + cxxflags: # General options that are passed to the C++ compiler. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Dgcc' + - ' -O0 -gdwarf-2 -g ? {is_mode("O0")}' + - ' -O2 ? {is_mode(''O2'')}' + - ' -Os ? {is_mode(''Os'')}' + asflags: # General options passed to the assembler. + - ' -c' + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + - ' -gdwarf-2 ? {is_mode(''O0'')}' + linkflags: # General user options passed to the linker. + - ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + - ' -Wl,--gc-sections,-Map=oneos.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + +# 构建前/后动作（支持条件表达式） +action: + prebuild: + - 'script:sys.path.append("$OS_ROOT" + "/drivers/hal/nationstech/scripts/");import prebuild;prebuild.prebuild("$PRO_ROOT")' \ No newline at end of file diff --git a/templates/n32l436rbl7-1616n/template.uvoptx b/templates/n32l436rbl7-1616n/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..589b7bd13cc070e136f7a17854922db072068911 --- /dev/null +++ b/templates/n32l436rbl7-1616n/template.uvoptx @@ -0,0 +1,1481 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + oneos + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0N32L43x.FLM -FS08000000 -FL020000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + 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### uVision Project, (C) Keil Software
+ + + + oneos + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32L436RB + Nationstech + Nationstech.N32L43x_DFP.0.1.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x8000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32L43x -FS08000000 -FL020000 -FP0($$Device:N32L436RB$Flash\N32L43x.FLM)) + 0 + $$Device:N32L436RB$firmware\CMSIS\device\n32l43x.h + + + + + + + + + + $$Device:N32L436RB$svd\N32L436.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + project + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + ..\..\drivers\hal\st\scripts\prebuild.bat + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output oneos.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 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+ + + + common + + + option_parse.c + 1 + ..\..\common\source\option_parse.c + + + ring_blk_buff.c + 1 + ..\..\common\source\ring_blk_buff.c + + + ring_buff.c + 1 + ..\..\common\source\ring_buff.c + + + + + dlog + + + console_backend.c + 1 + ..\..\components\dlog\source\backend\console_backend.c + + + dlog.c + 1 + ..\..\components\dlog\source\dlog.c + + + + + drivers + + + block_device.c + 1 + ..\..\drivers\block\block_device.c + + + bus.c + 1 + ..\..\drivers\bus\bus.c + + + clocksource.c + 1 + ..\..\drivers\timer\clocksource.c + + + clocksource_cortexm.c + 1 + ..\..\drivers\timer\clocksource_cortexm.c + + + console.c + 1 + ..\..\drivers\console\console.c + + + device.c + 1 + ..\..\drivers\device.c + + + dma_ram.c + 1 + ..\..\drivers\dma\dma_ram.c + + + driver.c + 1 + ..\..\drivers\driver.c + + + fal.c + 1 + ..\..\drivers\fal\fal.c + + + fal_block.c + 1 + ..\..\drivers\fal\fal_block.c + + + fal_part.c + 1 + ..\..\drivers\fal\fal_part.c + + + pin.c + 1 + ..\..\drivers\pin\pin.c + + + push_button.c + 1 + ..\..\drivers\misc\push_button.c + + + serial.c + 1 + ..\..\drivers\serial\serial.c + + + soft_dma.c + 1 + ..\..\drivers\dma\soft_dma.c + + + timer.c + 1 + ..\..\drivers\timer\timer.c + + + vector_table.c + 1 + ..\..\drivers\boot\cotex-m\vector_table.c + + + + + hal/drivers + + + drv_common.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_common.c + + + drv_flash.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\flash\drv_flash.c + + + drv_gpio.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_gpio.c + + + drv_usart.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\drv_usart.c + + + n32_it.c + 1 + ..\..\drivers\hal\nationstech\drivers\n32l43x\n32_it.c + + + + + hal/lowlevel + + + misc.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\misc.c + + + n32l43x_dma.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_dma.c + + + n32l43x_exti.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_exti.c + + + n32l43x_flash.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_flash.c + + + n32l43x_gpio.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_gpio.c + + + n32l43x_rcc.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_rcc.c + + + n32l43x_tim.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_tim.c + + + n32l43x_usart.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\n32l43x_std_periph_driver\src\n32l43x_usart.c + + + system_n32l43x.c + 1 + ..\..\drivers\hal\nationstech\N32L43x\CMSIS\device\system_n32l43x.c + + + + + kernel + + + os_block.c + 1 + ..\..\kernel\source\os_block.c + + + os_clock.c + 1 + ..\..\kernel\source\os_clock.c + + + os_idle.c + 1 + ..\..\kernel\source\os_idle.c + + + os_kernel_lock.c + 1 + ..\..\kernel\source\os_kernel_lock.c + + + os_kernel_log.c + 1 + ..\..\kernel\source\os_kernel_log.c + + + os_mem_firstfit.c + 1 + ..\..\kernel\source\os_mem_firstfit.c + + + os_memory.c + 1 + ..\..\kernel\source\os_memory.c + + + os_mutex.c + 1 + ..\..\kernel\source\os_mutex.c + + + os_sched.c + 1 + ..\..\kernel\source\os_sched.c + + + os_sem.c + 1 + ..\..\kernel\source\os_sem.c + + + os_spinlock.c + 1 + ..\..\kernel\source\os_spinlock.c + + + os_startup.c + 1 + ..\..\kernel\source\os_startup.c + + + os_task.c + 1 + ..\..\kernel\source\os_task.c + + + os_timer_hash.c + 1 + ..\..\kernel\source\os_timer_hash.c + + + os_util.c + 1 + ..\..\kernel\source\os_util.c + + + os_version.c + 1 + ..\..\kernel\source\os_version.c + + + os_workqueue.c + 1 + ..\..\kernel\source\os_workqueue.c + + + + + libc + + + access.c + 1 + ..\..\libc\source\armlibc\access.c + + + chdir.c + 1 + ..\..\libc\source\armlibc\chdir.c + + + close.c + 1 + ..\..\libc\source\armlibc\close.c + + + dirent.c + 1 + ..\..\libc\source\armlibc\dirent.c + + + fcntl.c + 1 + ..\..\libc\source\armlibc\fcntl.c + + + fstat.c + 1 + ..\..\libc\source\armlibc\fstat.c + + + fsync.c + 1 + ..\..\libc\source\armlibc\fsync.c + + + getcwd.c + 1 + ..\..\libc\source\armlibc\getcwd.c + + + gmtime_r.c + 1 + ..\..\libc\source\common\gmtime_r.c + + + ioctl.c + 1 + ..\..\libc\source\armlibc\ioctl.c + + + libc.c + 1 + ..\..\libc\source\armlibc\libc.c + + + lseek.c + 1 + ..\..\libc\source\armlibc\lseek.c + + + mem_std.c + 1 + ..\..\libc\source\armlibc\mem_std.c + + + mkdir.c + 1 + ..\..\libc\source\armlibc\mkdir.c + + + open.c + 1 + ..\..\libc\source\armlibc\open.c + + + read.c + 1 + ..\..\libc\source\armlibc\read.c + + + rename.c + 1 + ..\..\libc\source\armlibc\rename.c + + + rmdir.c + 1 + ..\..\libc\source\armlibc\rmdir.c + + + stat.c + 1 + ..\..\libc\source\armlibc\stat.c + + + statfs.c + 1 + ..\..\libc\source\armlibc\statfs.c + + + stdio.c + 1 + ..\..\libc\source\armlibc\stdio.c + + + strdup.c + 1 + ..\..\libc\source\armlibc\strdup.c + + + strnlen.c + 1 + ..\..\libc\source\armlibc\strnlen.c + + + stubs.c + 1 + ..\..\libc\source\armlibc\stubs.c + + + time.c + 1 + ..\..\libc\source\armlibc\time.c + + + unlink.c + 1 + ..\..\libc\source\armlibc\unlink.c + + + write.c + 1 + ..\..\libc\source\armlibc\write.c + + + + + shell + + + shell_buildin_cmd.c + 1 + ..\..\components\shell\source\shell_buildin_cmd.c + + + shell_main.c + 1 + ..\..\components\shell\source\shell_main.c + + + shell_process.c + 1 + ..\..\components\shell\source\shell_process.c + + + shell_symbol.c + 1 + ..\..\components\shell\source\shell_symbol.c + + + + + + + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/templates/nrf52840-pca10056/board/linker_scripts/link.lds b/templates/nrf52840-pca10056/board/linker_scripts/link.lds index 728279a43c39107edc0d74e7a169b2ca7ed32fbc..669b32765a3be71e61e2ab45117d8a7da0e875fb 100644 --- a/templates/nrf52840-pca10056/board/linker_scripts/link.lds +++ b/templates/nrf52840-pca10056/board/linker_scripts/link.lds @@ -1,138 +1,3 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x30000, LENGTH = 0x50000 - RAM (rx) : ORIGIN = 0x20002010, LENGTH = 0xdff0 /* 0xdff0 sram */ -} - -SECTIONS -{ -} - -SECTIONS -{ - . = ALIGN(4); - .mem_section_dummy_ram : - { - } - .log_dynamic_data : - { - PROVIDE(__start_log_dynamic_data = .); - KEEP(*(SORT(.log_dynamic_data*))) - PROVIDE(__stop_log_dynamic_data = .); - } > RAM - .log_filter_data : - { - PROVIDE(__start_log_filter_data = .); - KEEP(*(SORT(.log_filter_data*))) - PROVIDE(__stop_log_filter_data = .); - } > RAM - .cli_sorted_cmd_ptrs : - { - PROVIDE(__start_cli_sorted_cmd_ptrs = .); - KEEP(*(.cli_sorted_cmd_ptrs)) - PROVIDE(__stop_cli_sorted_cmd_ptrs = .); - } > RAM - .fs_data : - { - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - } > RAM - -} INSERT AFTER .data; - -SECTIONS -{ - .mem_section_dummy_rom : - { - } - .sdh_ant_observers : - { - PROVIDE(__start_sdh_ant_observers = .); - KEEP(*(SORT(.sdh_ant_observers*))) - PROVIDE(__stop_sdh_ant_observers = .); - } > FLASH - .sdh_ble_observers : - { - PROVIDE(__start_sdh_ble_observers = .); - KEEP(*(SORT(.sdh_ble_observers*))) - PROVIDE(__stop_sdh_ble_observers = .); - } > FLASH - .sdh_soc_observers : - { - PROVIDE(__start_sdh_soc_observers = .); - KEEP(*(SORT(.sdh_soc_observers*))) - PROVIDE(__stop_sdh_soc_observers = .); - } > FLASH - .sdh_req_observers : - { - PROVIDE(__start_sdh_req_observers = .); - KEEP(*(SORT(.sdh_req_observers*))) - PROVIDE(__stop_sdh_req_observers = .); - } > FLASH - .sdh_state_observers : - { - PROVIDE(__start_sdh_state_observers = .); - KEEP(*(SORT(.sdh_state_observers*))) - PROVIDE(__stop_sdh_state_observers = .); - } > FLASH - .sdh_stack_observers : - { - PROVIDE(__start_sdh_stack_observers = .); - KEEP(*(SORT(.sdh_stack_observers*))) - PROVIDE(__stop_sdh_stack_observers = .); - } > FLASH - .log_const_data : - { - PROVIDE(__start_log_const_data = .); - KEEP(*(SORT(.log_const_data*))) - PROVIDE(__stop_log_const_data = .); - } > FLASH - .nrf_balloc : - { - PROVIDE(__start_nrf_balloc = .); - KEEP(*(.nrf_balloc)) - PROVIDE(__stop_nrf_balloc = .); - } > FLASH - .nrf_queue : - { - PROVIDE(__start_nrf_queue = .); - KEEP(*(.nrf_queue)) - PROVIDE(__stop_nrf_queue = .); - } > FLASH - .cli_command : - { - PROVIDE(__start_cli_command = .); - KEEP(*(.cli_command)) - PROVIDE(__stop_cli_command = .); - } > FLASH - .crypto_data : - { - PROVIDE(__start_crypto_data = .); - KEEP(*(SORT(.crypto_data*))) - PROVIDE(__stop_crypto_data = .); - } > FLASH - .pwr_mgmt_data : - { - PROVIDE(__start_pwr_mgmt_data = .); - KEEP(*(SORT(.pwr_mgmt_data*))) - PROVIDE(__stop_pwr_mgmt_data = .); - } > FLASH - .log_backends : - { - PROVIDE(__start_log_backends = .); - KEEP(*(SORT(.log_backends*))) - PROVIDE(__stop_log_backends = .); - } > FLASH - -} INSERT AFTER .text - - /* * linker script for NRF52 with GNU ld */ @@ -140,13 +5,12 @@ SECTIONS /* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ - RAM0 (rx) : ORIGIN = 0x20000000, LENGTH = 0x20 /* 0x20 sram */ - RAM1 (rx) : ORIGIN = 0x20000020, LENGTH = 0x17fe0 /* 0x17fe0 sram */ - RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 32k /* 32K sram */ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1024k /* 512KB flash */ + RAM0 (rx) : ORIGIN = 0x20000000, LENGTH = 0x20 /* 0x20 sram */ + RAM1 (rx) : ORIGIN = 0x20000020, LENGTH = 0x3FFE0 /* 0x3FFE0 sram */ } ENTRY(Reset_Handler) -_system_stack_size = 0x200; +_system_stack_size = 4096; SECTIONS { @@ -203,10 +67,6 @@ SECTIONS .data : AT (_sidata) { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; diff --git a/templates/nrf52840-pca10056/board/startup/gcc_startup_nrf52.s b/templates/nrf52840-pca10056/board/startup/gcc_startup_nrf52.s index f79585b00a344d5f3d6fbd82aa99b5e9bc7360cb..7cad9e3d9fcb23749d047bcbf085255356e32ff2 100644 --- a/templates/nrf52840-pca10056/board/startup/gcc_startup_nrf52.s +++ b/templates/nrf52840-pca10056/board/startup/gcc_startup_nrf52.s @@ -227,9 +227,9 @@ Reset_Handler: * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =_etext + ldr r1, =_sidata ldr r2, =_sdata - ldr r3, =__bss_start__ + ldr r3, =_edata subs r3, r3, r2 ble .L_loop1_done @@ -253,7 +253,7 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ -#ifdef __STARTUP_CLEAR_BSS +@ #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ @@ -268,7 +268,7 @@ Reset_Handler: bgt .L_loop3 .L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS */ +@ #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ bl SystemInit @@ -277,7 +277,7 @@ Reset_Handler: * If those libraries are not accessible, define __START as your entry point. */ #ifndef __START -#define __START _start +#define __START entry #endif bl __START